projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: TC, Pass attr to tc_act can_offload()
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
f6dfb4c3 42#include <net/arp.h>
3616d08b 43#include <net/ipv6_stubs.h>
f828ca6a 44#include <net/bareudp.h>
d34eb2fc 45#include <net/bonding.h>
e8f887ac 46#include "en.h"
f0da4daa 47#include "en/tc/post_act.h"
1d447a39 48#include "en_rep.h"
768c3667 49#include "en/rep/tc.h"
e2394a61 50#include "en/rep/neigh.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
3f6d08d1 53#include "fs_core.h"
2c81bfd5 54#include "en/port.h"
101f4de9 55#include "en/tc_tun.h"
0a7fcb78 56#include "en/mapping.h"
4c3844d9 57#include "en/tc_ct.h"
b2fdf3d0 58#include "en/mod_hdr.h"
0d9f9647 59#include "en/tc_tun_encap.h"
0027d70c 60#include "en/tc/sample.h"
fad54790 61#include "en/tc/act/act.h"
04de7dda 62#include "lib/devcom.h"
9272e3df 63#include "lib/geneve.h"
ae430332 64#include "lib/fs_chains.h"
7a978759 65#include "diag/en_tc_tracepoint.h"
1fe3e316 66#include <asm/div64.h>
016c8946
JK		 67#include "lag/lag.h"
68#include "lag/mp.h"
e8f887ac 69
acff797c 70#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 71#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 72
8f1e0b97
PB		 73struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
74 [CHAIN_TO_REG] = {
75 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
76 .moffset = 0,
ed2fe7ba 77 .mlen = 16,
8f1e0b97 78 },
10742efc
VB		 79 [VPORT_TO_REG] = {
80 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 81 .moffset = 16,
82 .mlen = 16,
10742efc 83 },
0a7fcb78
PB		 84 [TUNNEL_TO_REG] = {
85 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 86 .moffset = 8,
87 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 88 .soffset = MLX5_BYTE_OFF(fte_match_param,
89 misc_parameters_2.metadata_reg_c_1),
90 },
4c3844d9 91 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 92 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 93 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
94 [MARK_TO_REG] = mark_to_reg_ct,
95 [LABELS_TO_REG] = labels_to_reg_ct,
96 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 97 /* For NIC rules we store the restore metadata directly
c7569097
AL		 98 * into reg_b that is passed to SW since we don't
99 * jump between steering domains.
100 */
101 [NIC_CHAIN_TO_REG] = {
102 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
103 .moffset = 0,
ed2fe7ba 104 .mlen = 16,
c7569097 105 },
aedd133d 106 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 107};
108
9ba33339
RD		 109/* To avoid false lock dependency warning set the tc_ht lock
110 * class different than the lock class of the ht being used when deleting
111 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
112 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
113 * it's different than the ht->mutex here.
114 */
115static struct lock_class_key tc_ht_lock_key;
116
0a7fcb78
PB		 117static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
118
119void
120mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
121 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 122 u32 val,
0a7fcb78
PB		 123 u32 mask)
124{
ed2fe7ba 125 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 126 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 127 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 128 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 129 u32 max_mask = GENMASK(match_len - 1, 0);
130 __be32 curr_mask_be, curr_val_be;
131 u32 curr_mask, curr_val;
0a7fcb78
PB		 132
133 fmask = headers_c + soffset;
134 fval = headers_v + soffset;
135
ed2fe7ba
PB		 136 memcpy(&curr_mask_be, fmask, 4);
137 memcpy(&curr_val_be, fval, 4);
138
139 curr_mask = be32_to_cpu(curr_mask_be);
140 curr_val = be32_to_cpu(curr_val_be);
141
142 //move to correct offset
143 WARN_ON(mask > max_mask);
144 mask <<= moffset;
145 val <<= moffset;
146 max_mask <<= moffset;
147
148 //zero val and mask
149 curr_mask &= ~max_mask;
150 curr_val &= ~max_mask;
0a7fcb78 151
ed2fe7ba
PB		 152 //add current to mask
153 curr_mask |= mask;
154 curr_val |= val;
155
156 //back to be32 and write
157 curr_mask_be = cpu_to_be32(curr_mask);
158 curr_val_be = cpu_to_be32(curr_val);
159
160 memcpy(fmask, &curr_mask_be, 4);
161 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 162
163 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
164}
165
7e36feeb
PB		 166void
167mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
168 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 169 u32 *val,
7e36feeb
PB		 170 u32 *mask)
171{
ed2fe7ba 172 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 173 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 174 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 175 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 176 u32 max_mask = GENMASK(match_len - 1, 0);
177 __be32 curr_mask_be, curr_val_be;
178 u32 curr_mask, curr_val;
7e36feeb
PB		 179
180 fmask = headers_c + soffset;
181 fval = headers_v + soffset;
182
ed2fe7ba
PB		 183 memcpy(&curr_mask_be, fmask, 4);
184 memcpy(&curr_val_be, fval, 4);
185
186 curr_mask = be32_to_cpu(curr_mask_be);
187 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 188
ed2fe7ba
PB		 189 *mask = (curr_mask >> moffset) & max_mask;
190 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 191}
192
0a7fcb78 193int
c7b9038d
VB		 194mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
195 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
196 enum mlx5_flow_namespace_type ns,
197 enum mlx5e_tc_attr_to_reg type,
198 u32 data)
0a7fcb78
PB		 199{
200 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
201 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
202 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
203 char *modact;
204 int err;
205
2c0e5cf5
PB		 206 modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
207 if (IS_ERR(modact))
208 return PTR_ERR(modact);
0a7fcb78
PB		 209
210 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 211 if (mlen == 32)
0a7fcb78
PB		 212 mlen = 0;
213
214 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
215 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 216 MLX5_SET(set_action_in, modact, offset, moffset);
217 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 218 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 219 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 220 mod_hdr_acts->num_actions++;
221
c7b9038d 222 return err;
0a7fcb78
PB		 223}
224
27484f71
AL		 225struct mlx5e_tc_int_port_priv *
226mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
227{
228 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
229 struct mlx5_rep_uplink_priv *uplink_priv;
230 struct mlx5e_rep_priv *uplink_rpriv;
231
232 if (is_mdev_switchdev_mode(priv->mdev)) {
233 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
234 uplink_priv = &uplink_rpriv->uplink_priv;
235
236 return uplink_priv->int_port_priv;
237 }
238
239 return NULL;
240}
241
aedd133d
AL		 242static struct mlx5_tc_ct_priv *
243get_ct_priv(struct mlx5e_priv *priv)
244{
245 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
246 struct mlx5_rep_uplink_priv *uplink_priv;
247 struct mlx5e_rep_priv *uplink_rpriv;
248
e8711402 249 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 250 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
251 uplink_priv = &uplink_rpriv->uplink_priv;
252
253 return uplink_priv->ct_priv;
254 }
255
256 return priv->fs.tc.ct;
257}
258
0027d70c 259static struct mlx5e_tc_psample *
f94d6389
CM		 260get_sample_priv(struct mlx5e_priv *priv)
261{
262 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
263 struct mlx5_rep_uplink_priv *uplink_priv;
264 struct mlx5e_rep_priv *uplink_rpriv;
265
266 if (is_mdev_switchdev_mode(priv->mdev)) {
267 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
268 uplink_priv = &uplink_rpriv->uplink_priv;
269
0027d70c 270 return uplink_priv->tc_psample;
f94d6389
CM		 271 }
272
273 return NULL;
274}
f94d6389 275
aedd133d
AL		 276struct mlx5_flow_handle *
277mlx5_tc_rule_insert(struct mlx5e_priv *priv,
278 struct mlx5_flow_spec *spec,
279 struct mlx5_flow_attr *attr)
280{
281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
282
e8711402 283 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 284 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
285
286 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
287}
288
289void
290mlx5_tc_rule_delete(struct mlx5e_priv *priv,
291 struct mlx5_flow_handle *rule,
292 struct mlx5_flow_attr *attr)
293{
294 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
295
e8711402 296 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 297 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
298
299 return;
300 }
301
302 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
303}
304
c7b9038d
VB		 305int
306mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
307 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
308 enum mlx5_flow_namespace_type ns,
309 enum mlx5e_tc_attr_to_reg type,
310 u32 data)
311{
312 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
313
314 return ret < 0 ? ret : 0;
315}
316
317void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
318 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
319 enum mlx5e_tc_attr_to_reg type,
320 int act_id, u32 data)
321{
322 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
323 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
324 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
325 char *modact;
326
2c0e5cf5 327 modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
c7b9038d
VB		 328
329 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 330 if (mlen == 32)
c7b9038d
VB		 331 mlen = 0;
332
333 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
334 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 335 MLX5_SET(set_action_in, modact, offset, moffset);
336 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 337 MLX5_SET(set_action_in, modact, data, data);
338}
339
77ab67b7
OG		 340struct mlx5e_hairpin {
341 struct mlx5_hairpin *pair;
342
343 struct mlx5_core_dev *func_mdev;
3f6d08d1 344 struct mlx5e_priv *func_priv;
77ab67b7 345 u32 tdn;
a6696735 346 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 347
348 int num_channels;
349 struct mlx5e_rqt indir_rqt;
a6696735 350 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 351 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 352};
353
5c65c564
OG		 354struct mlx5e_hairpin_entry {
355 /* a node of a hash table which keeps all the hairpin entries */
356 struct hlist_node hairpin_hlist;
357
73edca73
VB		 358 /* protects flows list */
359 spinlock_t flows_lock;
5c65c564
OG		 360 /* flows sharing the same hairpin */
361 struct list_head flows;
db76ca24
VB		 362 /* hpe's that were not fully initialized when dead peer update event
363 * function traversed them.
364 */
365 struct list_head dead_peer_wait_list;
5c65c564 366
d8822868 367 u16 peer_vhca_id;
106be53b 368 u8 prio;
5c65c564 369 struct mlx5e_hairpin *hp;
e4f9abbd 370 refcount_t refcnt;
db76ca24 371 struct completion res_ready;
5c65c564
OG		 372};
373
5a7e5bcb
VB		 374static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
375 struct mlx5e_tc_flow *flow);
376
0d9f9647 377struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 378{
379 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
380 return ERR_PTR(-EINVAL);
381 return flow;
382}
383
0d9f9647 384void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 385{
386 if (refcount_dec_and_test(&flow->refcnt)) {
387 mlx5e_tc_del_flow(priv, flow);
c5d326b2 388 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 389 }
390}
391
aedd133d 392bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 393{
394 return flow_flag_test(flow, ESWITCH);
395}
396
67d62ee7 397bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
84179981
PB		 398{
399 return flow_flag_test(flow, FT);
400}
401
0d9f9647 402bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 403{
404 return flow_flag_test(flow, OFFLOADED);
405}
406
e36db1ee 407int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
11c9c548 408{
b2fdf3d0
PB		 409 return mlx5e_is_eswitch_flow(flow) ?
410 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 411}
412
dd58edc3 413static struct mod_hdr_tbl *
b2fdf3d0 414get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 415{
416 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
417
e36db1ee 418 return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
b2fdf3d0 419 &esw->offloads.mod_hdr :
dd58edc3
VB		 420 &priv->fs.tc.mod_hdr;
421}
422
11c9c548
OG		 423static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
424 struct mlx5e_tc_flow *flow,
425 struct mlx5e_tc_flow_parse_attr *parse_attr)
426{
b2fdf3d0
PB		 427 struct mlx5_modify_hdr *modify_hdr;
428 struct mlx5e_mod_hdr_handle *mh;
11c9c548 429
b2fdf3d0 430 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
e36db1ee 431 mlx5e_get_flow_namespace(flow),
b2fdf3d0
PB		 432 &parse_attr->mod_hdr_acts);
433 if (IS_ERR(mh))
434 return PTR_ERR(mh);
11c9c548 435
b2fdf3d0 436 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 437 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 438 flow->mh = mh;
11c9c548
OG		 439
440 return 0;
11c9c548
OG		 441}
442
443static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
444 struct mlx5e_tc_flow *flow)
445{
5a7e5bcb 446 /* flow wasn't fully initialized */
dd58edc3 447 if (!flow->mh)
5a7e5bcb
VB		 448 return;
449
b2fdf3d0
PB		 450 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
451 flow->mh);
dd58edc3 452 flow->mh = NULL;
11c9c548
OG		 453}
454
77ab67b7
OG		 455static
456struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
457{
b1c2f631 458 struct mlx5_core_dev *mdev;
77ab67b7
OG		 459 struct net_device *netdev;
460 struct mlx5e_priv *priv;
461
b1c2f631
DC		 462 netdev = dev_get_by_index(net, ifindex);
463 if (!netdev)
464 return ERR_PTR(-ENODEV);
465
77ab67b7 466 priv = netdev_priv(netdev);
b1c2f631
DC		 467 mdev = priv->mdev;
468 dev_put(netdev);
469
470 /* Mirred tc action holds a refcount on the ifindex net_device (see
471 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
472 * after dev_put(netdev), while we're in the context of adding a tc flow.
473 *
474 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
475 * stored in a hairpin object, which exists until all flows, that refer to it, get
476 * removed.
477 *
478 * On the other hand, after a hairpin object has been created, the peer net_device may
479 * be removed/unbound while there are still some hairpin flows that are using it. This
480 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
481 * NETDEV_UNREGISTER event of the peer net_device.
482 */
483 return mdev;
77ab67b7
OG		 484}
485
486static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
487{
a6696735 488 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 489 int err;
490
a6696735
MM		 491 builder = mlx5e_tir_builder_alloc(false);
492 if (!builder)
493 return -ENOMEM;
494
77ab67b7
OG		 495 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
496 if (err)
a6696735 497 goto out;
77ab67b7 498
a6696735
MM		 499 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
500 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 501 if (err)
502 goto create_tir_err;
503
a6696735
MM		 504out:
505 mlx5e_tir_builder_free(builder);
506 return err;
77ab67b7
OG		 507
508create_tir_err:
509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 510
511 goto out;
77ab67b7
OG		 512}
513
514static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
515{
a6696735 516 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 517 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
518}
519
3f6d08d1
OG		 520static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
521{
3f6d08d1
OG		 522 struct mlx5e_priv *priv = hp->func_priv;
523 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 524 struct mlx5e_rss_params_indir *indir;
525 int err;
3f6d08d1 526
06e9f13a
MM		 527 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
528 if (!indir)
3f6d08d1
OG		 529 return -ENOMEM;
530
43befe99 531 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 532 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 533 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
534 indir);
3f6d08d1 535
06e9f13a 536 kvfree(indir);
3f6d08d1
OG		 537 return err;
538}
539
540static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
541{
542 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 543 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 544 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 545 struct mlx5e_tir_builder *builder;
546 int err = 0;
547
548 builder = mlx5e_tir_builder_alloc(false);
549 if (!builder)
550 return -ENOMEM;
551
43ec0f41 552 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 553
554 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 555 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 556
65d6b6e5 557 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 558
a6696735
MM		 559 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
560 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
561 false);
43ec0f41 562 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 563
a6696735 564 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 565 if (err) {
566 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
567 goto err_destroy_tirs;
568 }
a6696735
MM		 569
570 mlx5e_tir_builder_clear(builder);
3f6d08d1 571 }
3f6d08d1 572
a6696735
MM		 573out:
574 mlx5e_tir_builder_free(builder);
3f6d08d1 575 return err;
a6696735
MM		 576
577err_destroy_tirs:
578 max_tt = tt;
579 for (tt = 0; tt < max_tt; tt++)
580 mlx5e_tir_destroy(&hp->indir_tir[tt]);
581
582 goto out;
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
586{
587 int tt;
588
589 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 590 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 591}
592
593static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
594 struct ttc_params *ttc_params)
595{
596 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
597 int tt;
598
599 memset(ttc_params, 0, sizeof(*ttc_params));
600
bc29764e
MG		 601 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
602 MLX5_FLOW_NAMESPACE_KERNEL);
603 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
604 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
605 ttc_params->dests[tt].tir_num =
606 tt == MLX5_TT_ANY ?
607 mlx5e_tir_get_tirn(&hp->direct_tir) :
608 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
609 }
3f6d08d1 610
3f6d08d1
OG		 611 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
612 ft_attr->prio = MLX5E_TC_PRIO;
613}
614
615static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
616{
617 struct mlx5e_priv *priv = hp->func_priv;
618 struct ttc_params ttc_params;
619 int err;
620
621 err = mlx5e_hairpin_create_indirect_rqt(hp);
622 if (err)
623 return err;
624
625 err = mlx5e_hairpin_create_indirect_tirs(hp);
626 if (err)
627 goto err_create_indirect_tirs;
628
629 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 630 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
631 if (IS_ERR(hp->ttc)) {
632 err = PTR_ERR(hp->ttc);
3f6d08d1 633 goto err_create_ttc_table;
f4b45940 634 }
3f6d08d1
OG		 635
636 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 637 hp->num_channels,
638 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 639
640 return 0;
641
642err_create_ttc_table:
643 mlx5e_hairpin_destroy_indirect_tirs(hp);
644err_create_indirect_tirs:
06e9f13a 645 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 646
647 return err;
648}
649
650static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
651{
f4b45940 652 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 653 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 654 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 655}
656
77ab67b7
OG		 657static struct mlx5e_hairpin *
658mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
659 int peer_ifindex)
660{
661 struct mlx5_core_dev *func_mdev, *peer_mdev;
662 struct mlx5e_hairpin *hp;
663 struct mlx5_hairpin *pair;
664 int err;
665
666 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
667 if (!hp)
668 return ERR_PTR(-ENOMEM);
669
670 func_mdev = priv->mdev;
671 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 672 if (IS_ERR(peer_mdev)) {
673 err = PTR_ERR(peer_mdev);
674 goto create_pair_err;
675 }
77ab67b7
OG		 676
677 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
678 if (IS_ERR(pair)) {
679 err = PTR_ERR(pair);
680 goto create_pair_err;
681 }
682 hp->pair = pair;
683 hp->func_mdev = func_mdev;
3f6d08d1
OG		 684 hp->func_priv = priv;
685 hp->num_channels = params->num_channels;
77ab67b7
OG		 686
687 err = mlx5e_hairpin_create_transport(hp);
688 if (err)
689 goto create_transport_err;
690
3f6d08d1
OG		 691 if (hp->num_channels > 1) {
692 err = mlx5e_hairpin_rss_init(hp);
693 if (err)
694 goto rss_init_err;
695 }
696
77ab67b7
OG		 697 return hp;
698
3f6d08d1
OG		 699rss_init_err:
700 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 701create_transport_err:
702 mlx5_core_hairpin_destroy(hp->pair);
703create_pair_err:
704 kfree(hp);
705 return ERR_PTR(err);
706}
707
708static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
709{
3f6d08d1
OG		 710 if (hp->num_channels > 1)
711 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 712 mlx5e_hairpin_destroy_transport(hp);
713 mlx5_core_hairpin_destroy(hp->pair);
714 kvfree(hp);
715}
716
106be53b
OG		 717static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
718{
719 return (peer_vhca_id << 16 | prio);
720}
721
5c65c564 722static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 723 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 724{
725 struct mlx5e_hairpin_entry *hpe;
106be53b 726 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 727
728 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 729 hairpin_hlist, hash_key) {
e4f9abbd
VB		 730 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
731 refcount_inc(&hpe->refcnt);
5c65c564 732 return hpe;
e4f9abbd 733 }
5c65c564
OG		 734 }
735
736 return NULL;
737}
738
e4f9abbd
VB		 739static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
740 struct mlx5e_hairpin_entry *hpe)
741{
742 /* no more hairpin flows for us, release the hairpin pair */
b32accda 743 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 744 return;
b32accda
VB		 745 hash_del(&hpe->hairpin_hlist);
746 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 747
db76ca24
VB		 748 if (!IS_ERR_OR_NULL(hpe->hp)) {
749 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
750 dev_name(hpe->hp->pair->peer_mdev->device));
751
752 mlx5e_hairpin_destroy(hpe->hp);
753 }
e4f9abbd
VB		 754
755 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 756 kfree(hpe);
757}
758
106be53b
OG		 759#define UNKNOWN_MATCH_PRIO 8
760
761static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 762 struct mlx5_flow_spec *spec, u8 *match_prio,
763 struct netlink_ext_ack *extack)
106be53b
OG		 764{
765 void *headers_c, *headers_v;
766 u8 prio_val, prio_mask = 0;
767 bool vlan_present;
768
769#ifdef CONFIG_MLX5_CORE_EN_DCB
770 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 771 NL_SET_ERR_MSG_MOD(extack,
772 "only PCP trust state supported for hairpin");
106be53b
OG		 773 return -EOPNOTSUPP;
774 }
775#endif
776 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
777 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
778
779 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
780 if (vlan_present) {
781 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
782 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
783 }
784
785 if (!vlan_present || !prio_mask) {
786 prio_val = UNKNOWN_MATCH_PRIO;
787 } else if (prio_mask != 0x7) {
e98bedf5
EB		 788 NL_SET_ERR_MSG_MOD(extack,
789 "masked priority match not supported for hairpin");
106be53b
OG		 790 return -EOPNOTSUPP;
791 }
792
793 *match_prio = prio_val;
794 return 0;
795}
796
5c65c564
OG		 797static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
798 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 799 struct mlx5e_tc_flow_parse_attr *parse_attr,
800 struct netlink_ext_ack *extack)
5c65c564 801{
98b66cb1 802 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 803 struct mlx5_hairpin_params params;
d8822868 804 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 805 struct mlx5e_hairpin_entry *hpe;
806 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 807 u64 link_speed64;
808 u32 link_speed;
106be53b 809 u8 match_prio;
d8822868 810 u16 peer_id;
5c65c564
OG		 811 int err;
812
d8822868 813 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 814 if (IS_ERR(peer_mdev)) {
815 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
816 return PTR_ERR(peer_mdev);
817 }
818
d8822868 819 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 820 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 821 return -EOPNOTSUPP;
822 }
823
d8822868 824 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 825 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
826 extack);
106be53b
OG		 827 if (err)
828 return err;
b32accda
VB		 829
830 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 831 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 832 if (hpe) {
833 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
834 wait_for_completion(&hpe->res_ready);
835
836 if (IS_ERR(hpe->hp)) {
837 err = -EREMOTEIO;
838 goto out_err;
839 }
5c65c564 840 goto attach_flow;
db76ca24 841 }
5c65c564
OG		 842
843 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 844 if (!hpe) {
db76ca24
VB		 845 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
846 return -ENOMEM;
b32accda 847 }
5c65c564 848
73edca73 849 spin_lock_init(&hpe->flows_lock);
5c65c564 850 INIT_LIST_HEAD(&hpe->flows);
db76ca24 851 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 852 hpe->peer_vhca_id = peer_id;
106be53b 853 hpe->prio = match_prio;
e4f9abbd 854 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 855 init_completion(&hpe->res_ready);
856
857 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
858 hash_hairpin_info(peer_id, match_prio));
859 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 860
6cdc686a 861 params.log_data_size = 16;
5c65c564
OG		 862 params.log_data_size = min_t(u8, params.log_data_size,
863 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
864 params.log_data_size = max_t(u8, params.log_data_size,
865 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 866
eb9180f7
OG		 867 params.log_num_packets = params.log_data_size -
868 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
869 params.log_num_packets = min_t(u8, params.log_num_packets,
870 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
871
872 params.q_counter = priv->q_counter;
3f6d08d1 873 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 874 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 875 link_speed = max_t(u32, link_speed, 50000);
876 link_speed64 = link_speed;
877 do_div(link_speed64, 50000);
878 params.num_channels = link_speed64;
879
5c65c564 880 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 881 hpe->hp = hp;
882 complete_all(&hpe->res_ready);
5c65c564
OG		 883 if (IS_ERR(hp)) {
884 err = PTR_ERR(hp);
db76ca24 885 goto out_err;
5c65c564
OG		 886 }
887
eb9180f7 888 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 889 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 890 dev_name(hp->pair->peer_mdev->device),
eb9180f7 891 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 892
5c65c564 893attach_flow:
3f6d08d1 894 if (hpe->hp->num_channels > 1) {
226f2ca3 895 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 896 flow->attr->nic_attr->hairpin_ft =
897 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 898 } else {
a6696735 899 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 900 }
b32accda 901
e4f9abbd 902 flow->hpe = hpe;
73edca73 903 spin_lock(&hpe->flows_lock);
5c65c564 904 list_add(&flow->hairpin, &hpe->flows);
73edca73 905 spin_unlock(&hpe->flows_lock);
3f6d08d1 906
5c65c564
OG		 907 return 0;
908
db76ca24
VB		 909out_err:
910 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 911 return err;
912}
913
914static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
915 struct mlx5e_tc_flow *flow)
916{
5a7e5bcb 917 /* flow wasn't fully initialized */
e4f9abbd 918 if (!flow->hpe)
5a7e5bcb
VB		 919 return;
920
73edca73 921 spin_lock(&flow->hpe->flows_lock);
5c65c564 922 list_del(&flow->hairpin);
73edca73
VB		 923 spin_unlock(&flow->hpe->flows_lock);
924
e4f9abbd
VB		 925 mlx5e_hairpin_put(priv, flow->hpe);
926 flow->hpe = NULL;
5c65c564
OG		 927}
928
08247066
AL		 929struct mlx5_flow_handle *
930mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
931 struct mlx5_flow_spec *spec,
c620b772 932 struct mlx5_flow_attr *attr)
e8f887ac 933{
08247066 934 struct mlx5_flow_context *flow_context = &spec->flow_context;
67d62ee7 935 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c620b772 936 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 937 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 938 struct mlx5_flow_destination dest[2] = {};
66958ed9 939 struct mlx5_flow_act flow_act = {
3bc4b7bf 940 .action = attr->action,
bb0ee7dc 941 .flags = FLOW_ACT_NO_APPEND,
66958ed9 942 };
08247066 943 struct mlx5_flow_handle *rule;
c7569097 944 struct mlx5_flow_table *ft;
08247066 945 int dest_ix = 0;
e8f887ac 946
bb0ee7dc 947 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 948 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 949
aedd133d
AL		 950 if (attr->dest_ft) {
951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
952 dest[dest_ix].ft = attr->dest_ft;
953 dest_ix++;
954 } else if (nic_attr->hairpin_ft) {
08247066 955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 956 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 957 dest_ix++;
c620b772 958 } else if (nic_attr->hairpin_tirn) {
08247066 959 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 960 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 961 dest_ix++;
3f6d08d1
OG		 962 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
963 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 964 if (attr->dest_chain) {
965 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
966 attr->dest_chain, 1,
967 MLX5E_TC_FT_LEVEL);
968 if (IS_ERR(dest[dest_ix].ft))
969 return ERR_CAST(dest[dest_ix].ft);
970 } else {
6783f0a2 971 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 972 }
3f6d08d1 973 dest_ix++;
5c65c564 974 }
aad7e08d 975
c7569097
AL		 976 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
977 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
978 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
979
08247066 980 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 981 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 982 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 983 dest_ix++;
aad7e08d
AV		 984 }
985
08247066 986 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 987 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 988
6a064674
AL		 989 mutex_lock(&tc->t_lock);
990 if (IS_ERR_OR_NULL(tc->t)) {
991 /* Create the root table here if doesn't exist yet */
992 tc->t =
c7569097 993 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 994
995 if (IS_ERR(tc->t)) {
996 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 997 netdev_err(priv->netdev,
998 "Failed to create tc offload table\n");
c7569097
AL		 999 rule = ERR_CAST(priv->fs.tc.t);
1000 goto err_ft_get;
e8f887ac 1001 }
e8f887ac 1002 }
08247066 1003 mutex_unlock(&tc->t_lock);
e8f887ac 1004
aedd133d
AL		 1005 if (attr->chain || attr->prio)
1006 ft = mlx5_chains_get_table(nic_chains,
1007 attr->chain, attr->prio,
1008 MLX5E_TC_FT_LEVEL);
1009 else
1010 ft = attr->ft;
1011
c7569097
AL		 1012 if (IS_ERR(ft)) {
1013 rule = ERR_CAST(ft);
1014 goto err_ft_get;
1015 }
1016
c620b772 1017 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1018 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1019
c7569097 1020 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1021 &flow_act, dest, dest_ix);
1022 if (IS_ERR(rule))
c7569097 1023 goto err_rule;
08247066
AL		 1024
1025 return rule;
c7569097
AL		 1026
1027err_rule:
aedd133d
AL		 1028 if (attr->chain || attr->prio)
1029 mlx5_chains_put_table(nic_chains,
1030 attr->chain, attr->prio,
1031 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1032err_ft_get:
1033 if (attr->dest_chain)
1034 mlx5_chains_put_table(nic_chains,
1035 attr->dest_chain, 1,
1036 MLX5E_TC_FT_LEVEL);
1037
1038 return ERR_CAST(rule);
08247066
AL		 1039}
1040
df67ad62
RD		 1041static int
1042alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1043 struct mlx5_flow_attr *attr)
1044
1045{
1046 struct mlx5_fc *counter;
1047
1048 counter = mlx5_fc_create(counter_dev, true);
1049 if (IS_ERR(counter))
1050 return PTR_ERR(counter);
1051
1052 attr->counter = counter;
1053 return 0;
1054}
1055
08247066
AL		 1056static int
1057mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1058 struct mlx5e_tc_flow *flow,
1059 struct netlink_ext_ack *extack)
1060{
c6cfe113 1061 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1062 struct mlx5_flow_attr *attr = flow->attr;
08247066 1063 struct mlx5_core_dev *dev = priv->mdev;
08247066
AL		 1064 int err;
1065
c6cfe113
RD		 1066 parse_attr = attr->parse_attr;
1067
08247066
AL		 1068 if (flow_flag_test(flow, HAIRPIN)) {
1069 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1070 if (err)
1071 return err;
1072 }
1073
1074 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
df67ad62
RD		 1075 err = alloc_flow_attr_counter(dev, attr);
1076 if (err)
1077 return err;
08247066
AL		 1078 }
1079
1080 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1081 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2c0e5cf5 1082 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
08247066
AL		 1083 if (err)
1084 return err;
1085 }
1086
aedd133d
AL		 1087 if (flow_flag_test(flow, CT))
1088 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1089 attr, &parse_attr->mod_hdr_acts);
1090 else
1091 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1092 attr);
aad7e08d 1093
a2b7189b 1094 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1095}
1096
08247066 1097void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1098 struct mlx5_flow_handle *rule,
1099 struct mlx5_flow_attr *attr)
08247066 1100{
67d62ee7 1101 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c7569097 1102
08247066 1103 mlx5_del_flow_rules(rule);
c7569097 1104
aedd133d
AL		 1105 if (attr->chain || attr->prio)
1106 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1107 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1108
1109 if (attr->dest_chain)
1110 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1111 MLX5E_TC_FT_LEVEL);
08247066
AL		 1112}
1113
d85cdccb
OG		 1114static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1115 struct mlx5e_tc_flow *flow)
1116{
c620b772 1117 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1118 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1119
c7569097
AL		 1120 flow_flag_clear(flow, OFFLOADED);
1121
aedd133d
AL		 1122 if (flow_flag_test(flow, CT))
1123 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1124 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1125 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1126
c7569097
AL		 1127 /* Remove root table if no rules are left to avoid
1128 * extra steering hops.
1129 */
b6fac0b4 1130 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1131 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1132 !IS_ERR_OR_NULL(tc->t)) {
67d62ee7 1133 mlx5_chains_put_table(mlx5e_nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1134 priv->fs.tc.t = NULL;
1135 }
b6fac0b4 1136 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1137
513f8f7f 1138 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1139 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1140
972fe492
RD		 1141 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1142 mlx5_fc_destroy(priv->mdev, attr->counter);
aedd133d 1143
226f2ca3 1144 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1145 mlx5e_hairpin_flow_del(priv, flow);
c620b772 1146
88d97486 1147 kvfree(attr->parse_attr);
c620b772 1148 kfree(flow->attr);
d85cdccb
OG		 1149}
1150
0d9f9647 1151struct mlx5_flow_handle *
6d2a3ed0
OG		 1152mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1153 struct mlx5e_tc_flow *flow,
1154 struct mlx5_flow_spec *spec,
c620b772 1155 struct mlx5_flow_attr *attr)
6d2a3ed0 1156{
1ef3018f 1157 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1158 struct mlx5_flow_handle *rule;
4c3844d9 1159
89e39467
PB		 1160 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1161 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1162
1ef3018f
PB		 1163 if (flow_flag_test(flow, CT)) {
1164 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1165
69e2916e 1166 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1167 flow, spec, attr,
1ef3018f 1168 mod_hdr_acts);
f94d6389 1169 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1170 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1171 mlx5e_tc_get_flow_tun_id(flow));
69e2916e
PB		 1172 } else {
1173 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1174 }
6d2a3ed0 1175
6d2a3ed0
OG		 1176 if (IS_ERR(rule))
1177 return rule;
1178
c620b772 1179 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1180 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1181 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1182 if (flow_flag_test(flow, CT))
1183 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1184 else
1185 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1186 return flow->rule[1];
1187 }
1188 }
1189
6d2a3ed0
OG		 1190 return rule;
1191}
1192
0d9f9647
VB		 1193void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1194 struct mlx5e_tc_flow *flow,
1195 struct mlx5_flow_attr *attr)
6d2a3ed0 1196{
226f2ca3 1197 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1198
89e39467
PB		 1199 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1200 goto offload_rule_0;
1201
c620b772 1202 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1203 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1204
2820110d
CM		 1205 if (flow_flag_test(flow, CT))
1206 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1207 else if (flow_flag_test(flow, SAMPLE))
1208 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1209 else
89e39467 1210offload_rule_0:
2820110d 1211 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
6d2a3ed0
OG		 1212}
1213
0d9f9647 1214struct mlx5_flow_handle *
5dbe906f
PB		 1215mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1216 struct mlx5e_tc_flow *flow,
178f69b4 1217 struct mlx5_flow_spec *spec)
5dbe906f 1218{
c620b772 1219 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1220 struct mlx5_flow_handle *rule;
1221
c620b772
AL		 1222 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1223 if (!slow_attr)
1224 return ERR_PTR(-ENOMEM);
5dbe906f 1225
c620b772
AL		 1226 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1227 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1228 slow_attr->esw_attr->split_count = 0;
1229 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1230
1231 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1232 if (!IS_ERR(rule))
226f2ca3 1233 flow_flag_set(flow, SLOW);
5dbe906f 1234
c620b772
AL		 1235 kfree(slow_attr);
1236
5dbe906f
PB		 1237 return rule;
1238}
1239
0d9f9647
VB		 1240void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1241 struct mlx5e_tc_flow *flow)
5dbe906f 1242{
c620b772 1243 struct mlx5_flow_attr *slow_attr;
178f69b4 1244
c620b772 1245 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1246 if (!slow_attr) {
1247 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1248 return;
1249 }
c620b772
AL		 1250
1251 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1252 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1253 slow_attr->esw_attr->split_count = 0;
1254 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1255 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1256 flow_flag_clear(flow, SLOW);
c620b772 1257 kfree(slow_attr);
5dbe906f
PB		 1258}
1259
ad86755b
VB		 1260/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1261 * function.
1262 */
1263static void unready_flow_add(struct mlx5e_tc_flow *flow,
1264 struct list_head *unready_flows)
1265{
1266 flow_flag_set(flow, NOT_READY);
1267 list_add_tail(&flow->unready, unready_flows);
1268}
1269
1270/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1271 * function.
1272 */
1273static void unready_flow_del(struct mlx5e_tc_flow *flow)
1274{
1275 list_del(&flow->unready);
1276 flow_flag_clear(flow, NOT_READY);
1277}
1278
b4a23329
RD		 1279static void add_unready_flow(struct mlx5e_tc_flow *flow)
1280{
1281 struct mlx5_rep_uplink_priv *uplink_priv;
1282 struct mlx5e_rep_priv *rpriv;
1283 struct mlx5_eswitch *esw;
1284
1285 esw = flow->priv->mdev->priv.eswitch;
1286 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1287 uplink_priv = &rpriv->uplink_priv;
1288
ad86755b
VB		 1289 mutex_lock(&uplink_priv->unready_flows_lock);
1290 unready_flow_add(flow, &uplink_priv->unready_flows);
1291 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1292}
1293
1294static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1295{
ad86755b
VB		 1296 struct mlx5_rep_uplink_priv *uplink_priv;
1297 struct mlx5e_rep_priv *rpriv;
1298 struct mlx5_eswitch *esw;
1299
1300 esw = flow->priv->mdev->priv.eswitch;
1301 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1302 uplink_priv = &rpriv->uplink_priv;
1303
1304 mutex_lock(&uplink_priv->unready_flows_lock);
1305 unready_flow_del(flow);
1306 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1307}
1308
a508728a 1309bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1310{
1311 struct mlx5_core_dev *out_mdev, *route_mdev;
1312 struct mlx5e_priv *out_priv, *route_priv;
1313
1314 out_priv = netdev_priv(out_dev);
1315 out_mdev = out_priv->mdev;
1316 route_priv = netdev_priv(route_dev);
1317 route_mdev = route_priv->mdev;
1318
1319 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1320 route_mdev->coredev_type != MLX5_COREDEV_VF)
1321 return false;
1322
ab3f3d5e 1323 return mlx5e_same_hw_devs(out_priv, route_priv);
10742efc
VB		 1324}
1325
a508728a 1326int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1327{
1328 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1329 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1330 struct mlx5_core_dev *route_mdev;
1331 struct mlx5_eswitch *esw;
1332 u16 vhca_id;
1333 int err;
1334
1335 out_priv = netdev_priv(out_dev);
1336 esw = out_priv->mdev->priv.eswitch;
1337 route_priv = netdev_priv(route_dev);
1338 route_mdev = route_priv->mdev;
1339
1340 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1341 if (mlx5_lag_is_active(out_priv->mdev)) {
1342 /* In lag case we may get devices from different eswitch instances.
1343 * If we failed to get vport num, it means, mostly, that we on the wrong
1344 * eswitch.
1345 */
1346 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1347 if (err != -ENOENT)
1348 return err;
1349
1350 devcom = out_priv->mdev->priv.devcom;
1351 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1352 if (!esw)
1353 return -ENODEV;
1354 }
1355
10742efc 1356 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1357 if (devcom)
1358 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1359 return err;
1360}
1361
c7b9038d
VB		 1362int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1363 struct mlx5e_tc_flow_parse_attr *parse_attr,
1364 struct mlx5e_tc_flow *flow)
1365{
1366 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1367 struct mlx5_modify_hdr *mod_hdr;
1368
1369 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
e36db1ee 1370 mlx5e_get_flow_namespace(flow),
c7b9038d
VB		 1371 mod_hdr_acts->num_actions,
1372 mod_hdr_acts->actions);
1373 if (IS_ERR(mod_hdr))
1374 return PTR_ERR(mod_hdr);
1375
1376 WARN_ON(flow->attr->modify_hdr);
1377 flow->attr->modify_hdr = mod_hdr;
1378
1379 return 0;
1380}
1381
39542e23
RD		 1382static int
1383set_encap_dests(struct mlx5e_priv *priv,
1384 struct mlx5e_tc_flow *flow,
c118ebc9 1385 struct mlx5_flow_attr *attr,
39542e23
RD		 1386 struct netlink_ext_ack *extack,
1387 bool *encap_valid,
1388 bool *vf_tun)
1389{
1390 struct mlx5e_tc_flow_parse_attr *parse_attr;
39542e23
RD		 1391 struct mlx5_esw_flow_attr *esw_attr;
1392 struct net_device *encap_dev = NULL;
1393 struct mlx5e_rep_priv *rpriv;
1394 struct mlx5e_priv *out_priv;
1395 int out_index;
1396 int err = 0;
1397
1398 parse_attr = attr->parse_attr;
1399 esw_attr = attr->esw_attr;
1400 *vf_tun = false;
1401 *encap_valid = true;
1402
1403 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1404 struct net_device *out_dev;
1405 int mirred_ifindex;
1406
1407 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1408 continue;
1409
1410 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1411 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1412 if (!out_dev) {
1413 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1414 err = -ENODEV;
1415 goto out;
1416 }
c118ebc9 1417 err = mlx5e_attach_encap(priv, flow, attr, out_dev, out_index,
39542e23
RD		 1418 extack, &encap_dev, encap_valid);
1419 dev_put(out_dev);
1420 if (err)
1421 goto out;
1422
1423 if (esw_attr->dests[out_index].flags &
1424 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1425 !esw_attr->dest_int_port)
1426 *vf_tun = true;
1427
1428 out_priv = netdev_priv(encap_dev);
1429 rpriv = out_priv->ppriv;
1430 esw_attr->dests[out_index].rep = rpriv->rep;
1431 esw_attr->dests[out_index].mdev = out_priv->mdev;
1432 }
1433
1434 if (*vf_tun && esw_attr->out_count > 1) {
1435 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1436 err = -EOPNOTSUPP;
1437 goto out;
1438 }
1439
1440out:
1441 return err;
1442}
1443
1444static void
1445clean_encap_dests(struct mlx5e_priv *priv,
1446 struct mlx5e_tc_flow *flow,
c118ebc9 1447 struct mlx5_flow_attr *attr,
39542e23
RD		 1448 bool *vf_tun)
1449{
39542e23
RD		 1450 struct mlx5_esw_flow_attr *esw_attr;
1451 int out_index;
1452
1453 esw_attr = attr->esw_attr;
1454 *vf_tun = false;
1455
1456 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1457 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1458 continue;
1459
1460 if (esw_attr->dests[out_index].flags &
1461 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1462 !esw_attr->dest_int_port)
1463 *vf_tun = true;
1464
c118ebc9 1465 mlx5e_detach_encap(priv, flow, attr, out_index);
39542e23
RD		 1466 kfree(attr->parse_attr->tun_info[out_index]);
1467 }
1468}
1469
c83954ab 1470static int
74491de9 1471mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1472 struct mlx5e_tc_flow *flow,
1473 struct netlink_ext_ack *extack)
adb4c123
OG		 1474{
1475 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1476 struct mlx5e_tc_flow_parse_attr *parse_attr;
1477 struct mlx5_flow_attr *attr = flow->attr;
1478 struct mlx5_esw_flow_attr *esw_attr;
39542e23 1479 bool vf_tun, encap_valid;
39ac237c 1480 u32 max_prio, max_chain;
0ad060ee 1481 int err = 0;
8b32580d 1482
b16eb3c8
AL		 1483 parse_attr = attr->parse_attr;
1484 esw_attr = attr->esw_attr;
1485
84179981
PB		 1486 /* We check chain range only for tc flows.
1487 * For ft flows, we checked attr->chain was originally 0 and set it to
1488 * FDB_FT_CHAIN which is outside tc range.
1489 * See mlx5e_rep_setup_ft_cb().
1490 */
ae430332 1491 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1492 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1493 NL_SET_ERR_MSG_MOD(extack,
1494 "Requested chain is out of supported range");
8914add2
VB		 1495 err = -EOPNOTSUPP;
1496 goto err_out;
bf07aa73
PB		 1497 }
1498
ae430332 1499 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1500 if (attr->prio > max_prio) {
61644c3d
RD		 1501 NL_SET_ERR_MSG_MOD(extack,
1502 "Requested priority is out of supported range");
8914add2
VB		 1503 err = -EOPNOTSUPP;
1504 goto err_out;
bf07aa73 1505 }
e52c2802 1506
777bb800
VB		 1507 if (flow_flag_test(flow, TUN_RX)) {
1508 err = mlx5e_attach_decap_route(priv, flow);
1509 if (err)
8914add2 1510 goto err_out;
b16eb3c8
AL		 1511
1512 if (!attr->chain && esw_attr->int_port) {
1513 /* If decap route device is internal port, change the
1514 * source vport value in reg_c0 back to uplink just in
1515 * case the rule performs goto chain > 0. If we have a miss
1516 * on chain > 0 we want the metadata regs to hold the
1517 * chain id so SW will resume handling of this packet
1518 * from the proper chain.
1519 */
1520 u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1521 esw_attr->in_rep->vport);
1522
1523 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1524 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1525 metadata);
1526 if (err)
31108d14 1527 goto err_out;
077cdda7
RD		 1528
1529 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
b16eb3c8 1530 }
777bb800
VB		 1531 }
1532
14e6b038
EC		 1533 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1534 err = mlx5e_attach_decap(priv, flow, extack);
1535 if (err)
8914add2 1536 goto err_out;
14e6b038
EC		 1537 }
1538
166f431e
AL		 1539 if (netif_is_ovs_master(parse_attr->filter_dev)) {
1540 struct mlx5e_tc_int_port *int_port;
1541
1542 if (attr->chain) {
1543 NL_SET_ERR_MSG_MOD(extack,
1544 "Internal port rule is only supported on chain 0");
31108d14
CJ		 1545 err = -EOPNOTSUPP;
1546 goto err_out;
166f431e
AL		 1547 }
1548
1549 if (attr->dest_chain) {
1550 NL_SET_ERR_MSG_MOD(extack,
1551 "Internal port rule offload doesn't support goto action");
31108d14
CJ		 1552 err = -EOPNOTSUPP;
1553 goto err_out;
166f431e
AL		 1554 }
1555
1556 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1557 parse_attr->filter_dev->ifindex,
1558 flow_flag_test(flow, EGRESS) ?
1559 MLX5E_TC_INT_PORT_EGRESS :
1560 MLX5E_TC_INT_PORT_INGRESS);
31108d14
CJ		 1561 if (IS_ERR(int_port)) {
1562 err = PTR_ERR(int_port);
1563 goto err_out;
1564 }
166f431e
AL		 1565
1566 esw_attr->int_port = int_port;
1567 }
1568
c118ebc9 1569 err = set_encap_dests(priv, flow, attr, extack, &encap_valid, &vf_tun);
39542e23 1570 if (err)
7d1a3d08 1571 goto err_out;
7d1a3d08 1572
8b32580d 1573 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1574 if (err)
8914add2 1575 goto err_out;
adb4c123 1576
d5a3c2b6
RD		 1577 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1578 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1579 if (vf_tun) {
1580 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1581 if (err)
1582 goto err_out;
1583 } else {
1584 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1585 if (err)
1586 goto err_out;
1587 }
d7e75a32
OG		 1588 }
1589
b8aee822 1590 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
df67ad62
RD		 1591 err = alloc_flow_attr_counter(esw_attr->counter_dev, attr);
1592 if (err)
8914add2 1593 goto err_out;
b8aee822
MB		 1594 }
1595
0ad060ee
RD		 1596 /* we get here if one of the following takes place:
1597 * (1) there's no error
1598 * (2) there's an encap action and we don't have valid neigh
3c37745e 1599 */
bc1d75fa 1600 if (!encap_valid)
178f69b4 1601 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1602 else
6d2a3ed0 1603 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1604
8914add2
VB		 1605 if (IS_ERR(flow->rule[0])) {
1606 err = PTR_ERR(flow->rule[0]);
1607 goto err_out;
1608 }
1609 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1610
1611 return 0;
8914add2
VB		 1612
1613err_out:
1614 flow_flag_set(flow, FAILED);
1615 return err;
aa0cbbae 1616}
d85cdccb 1617
9272e3df
YK		 1618static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1619{
c620b772 1620 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1621 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1622 spec->match_value,
1623 misc_parameters_3);
1624 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1625 headers_v,
1626 geneve_tlv_option_0_data);
1627
1628 return !!geneve_tlv_opt_0_data;
1629}
1630
d85cdccb
OG		 1631static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1632 struct mlx5e_tc_flow *flow)
1633{
1634 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1635 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1636 struct mlx5_esw_flow_attr *esw_attr;
39542e23 1637 bool vf_tun;
d85cdccb 1638
777bb800 1639 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1640 mlx5e_put_flow_tunnel_id(flow);
1641
12a240a4 1642 if (flow_flag_test(flow, NOT_READY))
b4a23329 1643 remove_unready_flow(flow);
ef06c9ee 1644
226f2ca3
VB		 1645 if (mlx5e_is_offloaded_flow(flow)) {
1646 if (flow_flag_test(flow, SLOW))
178f69b4 1647 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1648 else
1649 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1650 }
362980ea 1651 complete_all(&flow->del_hw_done);
d85cdccb 1652
9272e3df
YK		 1653 if (mlx5_flow_has_geneve_opt(flow))
1654 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1655
513f8f7f 1656 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1657
777bb800
VB		 1658 if (flow->decap_route)
1659 mlx5e_detach_decap_route(priv, flow);
1660
c118ebc9 1661 clean_encap_dests(priv, flow, attr, &vf_tun);
d7e75a32 1662
aedd133d 1663 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1664
c7b9038d 1665 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
2c0e5cf5 1666 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1667 if (vf_tun && attr->modify_hdr)
1668 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1669 else
1670 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1671 }
b8aee822
MB		 1672
1673 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1674 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038 1675
166f431e
AL		 1676 if (esw_attr->int_port)
1677 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->int_port);
1678
27484f71
AL		 1679 if (esw_attr->dest_int_port)
1680 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->dest_int_port);
1681
14e6b038
EC		 1682 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1683 mlx5e_detach_decap(priv, flow);
c620b772 1684
88d97486
RD		 1685 kfree(attr->sample_attr);
1686 kvfree(attr->esw_attr->rx_tun_attr);
1687 kvfree(attr->parse_attr);
c620b772 1688 kfree(flow->attr);
d85cdccb
OG		 1689}
1690
0d9f9647 1691struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1692{
c620b772 1693 return flow->attr->counter;
b8aee822
MB		 1694}
1695
6a06c2f7 1696/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1697void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1698{
1699 struct mlx5e_tc_flow *flow, *tmp;
1700
1701 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1702 mlx5e_flow_put(priv, flow);
1703}
1704
04de7dda
RD		 1705static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1706{
1707 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1708
226f2ca3
VB		 1709 if (!flow_flag_test(flow, ESWITCH) ||
1710 !flow_flag_test(flow, DUP))
04de7dda
RD		 1711 return;
1712
1713 mutex_lock(&esw->offloads.peer_mutex);
1714 list_del(&flow->peer);
1715 mutex_unlock(&esw->offloads.peer_mutex);
1716
226f2ca3 1717 flow_flag_clear(flow, DUP);
04de7dda 1718
eb252c3a
RD		 1719 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1720 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1721 kfree(flow->peer_flow);
1722 }
1723
04de7dda
RD		 1724 flow->peer_flow = NULL;
1725}
1726
1727static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1728{
1729 struct mlx5_core_dev *dev = flow->priv->mdev;
1730 struct mlx5_devcom *devcom = dev->priv.devcom;
1731 struct mlx5_eswitch *peer_esw;
1732
1733 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1734 if (!peer_esw)
1735 return;
1736
1737 __mlx5e_tc_del_fdb_peer_flow(flow);
1738 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1739}
1740
e8f887ac 1741static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1742 struct mlx5e_tc_flow *flow)
e8f887ac 1743{
226f2ca3 1744 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1745 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1746 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1747 } else {
d85cdccb 1748 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1749 }
e8f887ac
AV		 1750}
1751
ee950e5d 1752static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1753{
1754 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1755 struct flow_action *flow_action = &rule->action;
1756 const struct flow_action_entry *act;
1757 int i;
1758
ee950e5d
CM		 1759 if (chain)
1760 return false;
1761
0a7fcb78
PB		 1762 flow_action_for_each(i, act, flow_action) {
1763 switch (act->id) {
1764 case FLOW_ACTION_GOTO:
1765 return true;
ee950e5d
CM		 1766 case FLOW_ACTION_SAMPLE:
1767 return true;
0a7fcb78
PB		 1768 default:
1769 continue;
1770 }
1771 }
1772
1773 return false;
1774}
bbd00f7e 1775
0a7fcb78
PB		 1776static int
1777enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1778 struct flow_dissector_key_enc_opts *opts,
1779 struct netlink_ext_ack *extack,
1780 bool *dont_care)
1781{
1782 struct geneve_opt *opt;
1783 int off = 0;
1784
1785 *dont_care = true;
1786
1787 while (opts->len > off) {
1788 opt = (struct geneve_opt *)&opts->data[off];
1789
1790 if (!(*dont_care) || opt->opt_class || opt->type ||
1791 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1792 *dont_care = false;
1793
c51323ee 1794 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1795 opt->type != U8_MAX) {
c50775d0
RD		 1796 NL_SET_ERR_MSG_MOD(extack,
1797 "Partial match of tunnel options in chain > 0 isn't supported");
0a7fcb78
PB		 1798 netdev_warn(priv->netdev,
1799 "Partial match of tunnel options in chain > 0 isn't supported");
1800 return -EOPNOTSUPP;
1801 }
1802 }
1803
1804 off += sizeof(struct geneve_opt) + opt->length * 4;
1805 }
1806
1807 return 0;
1808}
1809
1810#define COPY_DISSECTOR(rule, diss_key, dst)\
1811({ \
1812 struct flow_rule *__rule = (rule);\
1813 typeof(dst) __dst = dst;\
1814\
1815 memcpy(__dst,\
1816 skb_flow_dissector_target(__rule->match.dissector,\
1817 diss_key,\
1818 __rule->match.key),\
1819 sizeof(*__dst));\
1820})
1821
1822static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1823 struct mlx5e_tc_flow *flow,
1824 struct flow_cls_offload *f,
1825 struct net_device *filter_dev)
bbd00f7e 1826{
f9e30088 1827 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1828 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1829 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1830 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1831 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1832 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1833 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1834 struct mlx5e_rep_priv *uplink_rpriv;
1835 struct tunnel_match_key tunnel_key;
1836 bool enc_opts_is_dont_care = true;
1837 u32 tun_id, enc_opts_id = 0;
1838 struct mlx5_eswitch *esw;
1839 u32 value, mask;
8f256622 1840 int err;
2e72eb43 1841
0a7fcb78
PB		 1842 esw = priv->mdev->priv.eswitch;
1843 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1844 uplink_priv = &uplink_rpriv->uplink_priv;
1845
1846 memset(&tunnel_key, 0, sizeof(tunnel_key));
1847 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1848 &tunnel_key.enc_control);
1849 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1850 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1851 &tunnel_key.enc_ipv4);
1852 else
1853 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1854 &tunnel_key.enc_ipv6);
1855 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1856 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1857 &tunnel_key.enc_tp);
1858 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1859 &tunnel_key.enc_key_id);
1860 tunnel_key.filter_ifindex = filter_dev->ifindex;
1861
1862 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1863 if (err)
101f4de9 1864 return err;
bbd00f7e 1865
0a7fcb78
PB		 1866 flow_rule_match_enc_opts(rule, &enc_opts_match);
1867 err = enc_opts_is_dont_care_or_full_match(priv,
1868 enc_opts_match.mask,
1869 extack,
1870 &enc_opts_is_dont_care);
1871 if (err)
1872 goto err_enc_opts;
fe1587a7 1873
0a7fcb78 1874 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1875 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1876 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1877 sizeof(*enc_opts_match.key));
1878 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1879 sizeof(*enc_opts_match.mask));
1880
0a7fcb78 1881 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1882 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1883 if (err)
1884 goto err_enc_opts;
1885 }
fe1587a7 1886
0a7fcb78
PB		 1887 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1888 mask = enc_opts_id ? TUNNEL_ID_MASK :
1889 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1890
0a7fcb78
PB		 1891 if (attr->chain) {
1892 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1893 TUNNEL_TO_REG, value, mask);
1894 } else {
1895 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1896 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1897 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1898 TUNNEL_TO_REG, value);
1899 if (err)
1900 goto err_set;
fe1587a7 1901
0a7fcb78 1902 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1903 }
bbd00f7e 1904
0a7fcb78
PB		 1905 flow->tunnel_id = value;
1906 return 0;
bcef735c 1907
0a7fcb78
PB		 1908err_set:
1909 if (enc_opts_id)
1910 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1911 enc_opts_id);
1912err_enc_opts:
1913 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1914 return err;
1915}
bcef735c 1916
0a7fcb78
PB		 1917static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1918{
1919 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1920 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1921 struct mlx5_rep_uplink_priv *uplink_priv;
1922 struct mlx5e_rep_priv *uplink_rpriv;
1923 struct mlx5_eswitch *esw;
bcef735c 1924
0a7fcb78
PB		 1925 esw = flow->priv->mdev->priv.eswitch;
1926 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1927 uplink_priv = &uplink_rpriv->uplink_priv;
1928
1929 if (tun_id)
1930 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1931 if (enc_opts_id)
1932 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1933 enc_opts_id);
1934}
e98bedf5 1935
4c3844d9
PB		 1936u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1937{
1938 return flow->tunnel_id;
1939}
1940
fca53304
EB		 1941void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1942 struct flow_match_basic *match, bool outer,
1943 void *headers_c, void *headers_v)
1944{
1945 bool ip_version_cap;
1946
1947 ip_version_cap = outer ?
1948 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1949 ft_field_support.outer_ip_version) :
1950 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1951 ft_field_support.inner_ip_version);
1952
1953 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1954 (match->key->n_proto == htons(ETH_P_IP) ||
1955 match->key->n_proto == htons(ETH_P_IPV6))) {
1956 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1958 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1959 } else {
1960 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1961 ntohs(match->mask->n_proto));
1962 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1963 ntohs(match->key->n_proto));
1964 }
4a5d5d73
EB		 1965}
1966
0d9f9647 1967u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1968{
1969 void *headers_v;
1970 u16 ethertype;
1971 u8 ip_version;
1972
1973 if (outer)
1974 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1975 else
1976 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1977
1978 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1979 /* Return ip_version converted from ethertype anyway */
1980 if (!ip_version) {
1981 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1982 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1983 ip_version = 4;
1984 else if (ethertype == ETH_P_IPV6)
1985 ip_version = 6;
1986 }
1987 return ip_version;
1988}
1989
b6dfff21
PB		 1990/* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
1991 * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
1992 * +---------+----------------------------------------+
1993 * |Arriving | Arriving Outer Header |
1994 * | Inner +---------+---------+---------+----------+
1995 * | Header | Not-ECT | ECT(0) | ECT(1) | CE |
1996 * +---------+---------+---------+---------+----------+
1997 * | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop> |
1998 * | ECT(0) | ECT(0) | ECT(0) | ECT(1) | CE* |
1999 * | ECT(1) | ECT(1) | ECT(1) | ECT(1)* | CE* |
2000 * | CE | CE | CE | CE | CE |
2001 * +---------+---------+---------+---------+----------+
2002 *
2003 * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2004 * the inner ip_ecn value before hardware decap action.
2005 *
2006 * Cells marked are changed from original inner packet ip_ecn value during decap, and
2007 * so matching those values on inner ip_ecn before decap will fail.
2008 *
2009 * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2010 * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2011 * and such we can drop the inner ip_ecn=CE match.
2012 */
2013
2014static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2015 struct flow_cls_offload *f,
2016 bool *match_inner_ecn)
2017{
2018 u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2019 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2020 struct netlink_ext_ack *extack = f->common.extack;
2021 struct flow_match_ip match;
2022
2023 *match_inner_ecn = true;
2024
2025 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2026 flow_rule_match_enc_ip(rule, &match);
2027 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2028 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2029 }
2030
2031 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2032 flow_rule_match_ip(rule, &match);
2033 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2034 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2035 }
2036
2037 if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2038 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2039 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2040 return -EOPNOTSUPP;
2041 }
2042
2043 if (!outer_ecn_mask) {
2044 if (!inner_ecn_mask)
2045 return 0;
2046
2047 NL_SET_ERR_MSG_MOD(extack,
2048 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2049 netdev_warn(priv->netdev,
2050 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2051 return -EOPNOTSUPP;
2052 }
2053
2054 if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2055 NL_SET_ERR_MSG_MOD(extack,
2056 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2057 netdev_warn(priv->netdev,
2058 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2059 return -EOPNOTSUPP;
2060 }
2061
2062 if (!inner_ecn_mask)
2063 return 0;
2064
2065 /* Both inner and outer have full mask on ecn */
2066
2067 if (outer_ecn_key == INET_ECN_ECT_1) {
2068 /* inner ecn might change by DECAP action */
2069
2070 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2071 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2072 return -EOPNOTSUPP;
2073 }
2074
2075 if (outer_ecn_key != INET_ECN_CE)
2076 return 0;
2077
2078 if (inner_ecn_key != INET_ECN_CE) {
2079 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2080 NL_SET_ERR_MSG_MOD(extack,
2081 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2082 netdev_warn(priv->netdev,
2083 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2084 return -EOPNOTSUPP;
2085 }
2086
2087 /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2088 * drop match on inner ecn
2089 */
2090 *match_inner_ecn = false;
2091
2092 return 0;
2093}
2094
bbd00f7e 2095static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2096 struct mlx5e_tc_flow *flow,
bbd00f7e 2097 struct mlx5_flow_spec *spec,
f9e30088 2098 struct flow_cls_offload *f,
0a7fcb78
PB		 2099 struct net_device *filter_dev,
2100 u8 *match_level,
2101 bool *match_inner)
bbd00f7e 2102{
a508728a 2103 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 2104 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2105 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2106 bool needs_mapping, sets_mapping;
8f256622 2107 int err;
2e72eb43 2108
0885ae1a
A		 2109 if (!mlx5e_is_eswitch_flow(flow)) {
2110 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
0a7fcb78 2111 return -EOPNOTSUPP;
0885ae1a 2112 }
0a7fcb78 2113
c620b772 2114 needs_mapping = !!flow->attr->chain;
ee950e5d 2115 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 2116 *match_inner = !needs_mapping;
2117
2118 if ((needs_mapping || sets_mapping) &&
636bb968 2119 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
c50775d0
RD		 2120 NL_SET_ERR_MSG_MOD(extack,
2121 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2122 netdev_warn(priv->netdev,
636bb968 2123 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2124 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2125 }
2126
c620b772 2127 if (!flow->attr->chain) {
0a7fcb78
PB		 2128 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2129 match_level);
2130 if (err) {
e98bedf5 2131 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2132 "Failed to parse tunnel attributes");
2133 netdev_warn(priv->netdev,
2134 "Failed to parse tunnel attributes");
2135 return err;
e98bedf5
EB		 2136 }
2137
14e6b038
EC		 2138 /* With mpls over udp we decapsulate using packet reformat
2139 * object
2140 */
2141 if (!netif_is_bareudp(filter_dev))
c620b772 2142 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 2143 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2144 if (err)
2145 return err;
2146 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2147 struct mlx5_flow_spec *tmp_spec;
2148
2149 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2150 if (!tmp_spec) {
2151 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2152 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2153 return -ENOMEM;
2154 }
2155 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2156
2157 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2158 if (err) {
2159 kvfree(tmp_spec);
2160 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2161 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2162 return err;
2163 }
2164 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2165 kvfree(tmp_spec);
2166 if (err)
2167 return err;
bcef735c
OG		 2168 }
2169
0a7fcb78
PB		 2170 if (!needs_mapping && !sets_mapping)
2171 return 0;
bbd00f7e 2172
0a7fcb78 2173 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2174}
bbd00f7e 2175
0a7fcb78 2176static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2177{
0a7fcb78
PB		 2178 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2179 inner_headers);
bbd00f7e
HHZ		 2180}
2181
0a7fcb78 2182static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2183{
0a7fcb78
PB		 2184 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2185 inner_headers);
2186}
2187
2188static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2189{
2190 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2191 outer_headers);
2192}
2193
2194static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2195{
2196 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2197 outer_headers);
8377629e
EB		 2198}
2199
8ee72638 2200void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
8377629e
EB		 2201{
2202 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2203 get_match_inner_headers_value(spec) :
2204 get_match_outer_headers_value(spec);
2205}
2206
8ee72638 2207void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
0a7fcb78
PB		 2208{
2209 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2210 get_match_inner_headers_criteria(spec) :
2211 get_match_outer_headers_criteria(spec);
8377629e
EB		 2212}
2213
6d65bc64 2214static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2215 struct flow_cls_offload *f)
2216{
2217 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2218 struct netlink_ext_ack *extack = f->common.extack;
2219 struct net_device *ingress_dev;
2220 struct flow_match_meta match;
2221
2222 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2223 return 0;
2224
2225 flow_rule_match_meta(rule, &match);
e3e0f9b2 2226 if (!match.mask->ingress_ifindex)
2227 return 0;
2228
6d65bc64 2229 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2230 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2231 return -EOPNOTSUPP;
6d65bc64 2232 }
2233
2234 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2235 match.key->ingress_ifindex);
2236 if (!ingress_dev) {
2237 NL_SET_ERR_MSG_MOD(extack,
2238 "Can't find the ingress port to match on");
a683012a 2239 return -ENOENT;
6d65bc64 2240 }
2241
2242 if (ingress_dev != filter_dev) {
2243 NL_SET_ERR_MSG_MOD(extack,
2244 "Can't match on the ingress filter port");
a683012a 2245 return -EOPNOTSUPP;
6d65bc64 2246 }
2247
2248 return 0;
2249}
2250
72046a91
EC		 2251static bool skip_key_basic(struct net_device *filter_dev,
2252 struct flow_cls_offload *f)
2253{
2254 /* When doing mpls over udp decap, the user needs to provide
2255 * MPLS_UC as the protocol in order to be able to match on mpls
2256 * label fields. However, the actual ethertype is IP so we want to
2257 * avoid matching on this, otherwise we'll fail the match.
2258 */
2259 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2260 return true;
2261
2262 return false;
2263}
2264
de0af0bf 2265static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2266 struct mlx5e_tc_flow *flow,
de0af0bf 2267 struct mlx5_flow_spec *spec,
f9e30088 2268 struct flow_cls_offload *f,
54c177ca 2269 struct net_device *filter_dev,
93b3586e 2270 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2271{
e98bedf5 2272 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2273 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2274 outer_headers);
2275 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2276 outer_headers);
699e96dd
JL		 2277 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2278 misc_parameters);
2279 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2280 misc_parameters);
a3222a2d
MD		 2281 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2282 misc_parameters_3);
2283 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2284 misc_parameters_3);
f9e30088 2285 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2286 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2287 enum fs_flow_table_type fs_type;
b6dfff21 2288 bool match_inner_ecn = true;
e3a2b7ed
AV		 2289 u16 addr_type = 0;
2290 u8 ip_proto = 0;
93b3586e 2291 u8 *match_level;
6d65bc64 2292 int err;
e3a2b7ed 2293
afe93f71 2294 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2295 match_level = outer_match_level;
de0af0bf 2296
8f256622 2297 if (dissector->used_keys &
3d144578
VB		 2298 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2299 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2300 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2301 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2302 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2303 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2304 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2305 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2306 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2307 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2308 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2309 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2310 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2311 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2312 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2313 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2314 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2315 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2316 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2317 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2318 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2319 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2320 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2321 dissector->used_keys);
e3a2b7ed
AV		 2322 return -EOPNOTSUPP;
2323 }
2324
075973c7 2325 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2326 bool match_inner = false;
bbd00f7e 2327
0a7fcb78
PB		 2328 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2329 outer_match_level, &match_inner);
2330 if (err)
2331 return err;
2332
2333 if (match_inner) {
2334 /* header pointers should point to the inner headers
2335 * if the packet was decapsulated already.
2336 * outer headers are set by parse_tunnel_attr.
2337 */
2338 match_level = inner_match_level;
2339 headers_c = get_match_inner_headers_criteria(spec);
2340 headers_v = get_match_inner_headers_value(spec);
2341 }
b6dfff21
PB		 2342
2343 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2344 if (err)
2345 return err;
bbd00f7e
HHZ		 2346 }
2347
6d65bc64 2348 err = mlx5e_flower_parse_meta(filter_dev, f);
2349 if (err)
2350 return err;
2351
72046a91
EC		 2352 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2353 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2354 struct flow_match_basic match;
2355
2356 flow_rule_match_basic(rule, &match);
fca53304
EB		 2357 mlx5e_tc_set_ethertype(priv->mdev, &match,
2358 match_level == outer_match_level,
2359 headers_c, headers_v);
e3a2b7ed 2360
8f256622 2361 if (match.mask->n_proto)
d708f902 2362 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2363 }
35a605db
EB		 2364 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2365 is_vlan_dev(filter_dev)) {
2366 struct flow_dissector_key_vlan filter_dev_mask;
2367 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2368 struct flow_match_vlan match;
2369
35a605db
EB		 2370 if (is_vlan_dev(filter_dev)) {
2371 match.key = &filter_dev_key;
2372 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2373 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2374 match.key->vlan_priority = 0;
2375 match.mask = &filter_dev_mask;
2376 memset(match.mask, 0xff, sizeof(*match.mask));
2377 match.mask->vlan_priority = 0;
2378 } else {
2379 flow_rule_match_vlan(rule, &match);
2380 }
8f256622
PNA		 2381 if (match.mask->vlan_id ||
2382 match.mask->vlan_priority ||
2383 match.mask->vlan_tpid) {
2384 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2385 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2386 svlan_tag, 1);
2387 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2388 svlan_tag, 1);
2389 } else {
2390 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2391 cvlan_tag, 1);
2392 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2393 cvlan_tag, 1);
2394 }
095b6cfd 2395
8f256622
PNA		 2396 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2397 match.mask->vlan_id);
2398 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2399 match.key->vlan_id);
358d79a4 2400
8f256622
PNA		 2401 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2402 match.mask->vlan_priority);
2403 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2404 match.key->vlan_priority);
54782900 2405
d708f902 2406 *match_level = MLX5_MATCH_L2;
54782900 2407 }
d3a80bb5 2408 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2409 /* cvlan_tag enabled in match criteria and
2410 * disabled in match value means both S & C tags
2411 * don't exist (untagged of both)
2412 */
cee26487 2413 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2414 *match_level = MLX5_MATCH_L2;
54782900
OG		 2415 }
2416
8f256622
PNA		 2417 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2418 struct flow_match_vlan match;
2419
12d5cbf8 2420 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2421 if (match.mask->vlan_id ||
2422 match.mask->vlan_priority ||
2423 match.mask->vlan_tpid) {
afe93f71
RD		 2424 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2425 fs_type)) {
2426 NL_SET_ERR_MSG_MOD(extack,
2427 "Matching on CVLAN is not supported");
2428 return -EOPNOTSUPP;
2429 }
2430
8f256622 2431 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2432 MLX5_SET(fte_match_set_misc, misc_c,
2433 outer_second_svlan_tag, 1);
2434 MLX5_SET(fte_match_set_misc, misc_v,
2435 outer_second_svlan_tag, 1);
2436 } else {
2437 MLX5_SET(fte_match_set_misc, misc_c,
2438 outer_second_cvlan_tag, 1);
2439 MLX5_SET(fte_match_set_misc, misc_v,
2440 outer_second_cvlan_tag, 1);
2441 }
2442
2443 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2444 match.mask->vlan_id);
699e96dd 2445 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2446 match.key->vlan_id);
699e96dd 2447 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2448 match.mask->vlan_priority);
699e96dd 2449 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2450 match.key->vlan_priority);
699e96dd
JL		 2451
2452 *match_level = MLX5_MATCH_L2;
0faddfe6 2453 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2454 }
2455 }
2456
8f256622
PNA		 2457 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2458 struct flow_match_eth_addrs match;
54782900 2459
8f256622 2460 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2461 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2462 dmac_47_16),
8f256622 2463 match.mask->dst);
d3a80bb5
OG		 2464 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2465 dmac_47_16),
8f256622 2466 match.key->dst);
d3a80bb5
OG		 2467
2468 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2469 smac_47_16),
8f256622 2470 match.mask->src);
d3a80bb5
OG		 2471 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2472 smac_47_16),
8f256622 2473 match.key->src);
d3a80bb5 2474
8f256622
PNA		 2475 if (!is_zero_ether_addr(match.mask->src) ||
2476 !is_zero_ether_addr(match.mask->dst))
d708f902 2477 *match_level = MLX5_MATCH_L2;
54782900
OG		 2478 }
2479
8f256622
PNA		 2480 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2481 struct flow_match_control match;
54782900 2482
8f256622
PNA		 2483 flow_rule_match_control(rule, &match);
2484 addr_type = match.key->addr_type;
54782900
OG		 2485
2486 /* the HW doesn't support frag first/later */
0885ae1a
A		 2487 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2488 NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
54782900 2489 return -EOPNOTSUPP;
0885ae1a 2490 }
54782900 2491
8f256622 2492 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2493 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2495 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2496
2497 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2498 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2499 *match_level = MLX5_MATCH_L2;
54782900
OG		 2500 /* *** L2 attributes parsing up to here *** */
2501 else
83621b7d 2502 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2503 }
2504 }
2505
8f256622
PNA		 2506 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2507 struct flow_match_basic match;
2508
2509 flow_rule_match_basic(rule, &match);
2510 ip_proto = match.key->ip_proto;
54782900
OG		 2511
2512 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2513 match.mask->ip_proto);
54782900 2514 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2515 match.key->ip_proto);
54782900 2516
8f256622 2517 if (match.mask->ip_proto)
d708f902 2518 *match_level = MLX5_MATCH_L3;
54782900
OG		 2519 }
2520
e3a2b7ed 2521 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2522 struct flow_match_ipv4_addrs match;
e3a2b7ed 2523
8f256622 2524 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2525 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2526 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2527 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2528 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2529 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2530 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2531 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2532 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2533 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2534 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2535 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2536 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2537
8f256622 2538 if (match.mask->src || match.mask->dst)
d708f902 2539 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2540 }
2541
2542 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2543 struct flow_match_ipv6_addrs match;
e3a2b7ed 2544
8f256622 2545 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2546 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2547 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2548 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2549 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2550 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2551 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2552
2553 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2554 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2555 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2556 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2557 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2558 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2559
8f256622
PNA		 2560 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2561 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2562 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2563 }
2564
8f256622
PNA		 2565 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2566 struct flow_match_ip match;
1f97a526 2567
8f256622 2568 flow_rule_match_ip(rule, &match);
b6dfff21
PB		 2569 if (match_inner_ecn) {
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2571 match.mask->tos & 0x3);
2572 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2573 match.key->tos & 0x3);
2574 }
1f97a526 2575
8f256622
PNA		 2576 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2577 match.mask->tos >> 2);
2578 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2579 match.key->tos >> 2);
1f97a526 2580
8f256622
PNA		 2581 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2582 match.mask->ttl);
2583 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2584 match.key->ttl);
1f97a526 2585
8f256622 2586 if (match.mask->ttl &&
a8ade55f 2587 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2588 ft_field_support.outer_ipv4_ttl)) {
2589 NL_SET_ERR_MSG_MOD(extack,
2590 "Matching on TTL is not supported");
1f97a526 2591 return -EOPNOTSUPP;
e98bedf5 2592 }
a8ade55f 2593
8f256622 2594 if (match.mask->tos || match.mask->ttl)
d708f902 2595 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2596 }
2597
54782900
OG		 2598 /* *** L3 attributes parsing up to here *** */
2599
8f256622
PNA		 2600 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2601 struct flow_match_ports match;
2602
2603 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2604 switch (ip_proto) {
2605 case IPPROTO_TCP:
2606 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2607 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2608 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2609 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2610
2611 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2612 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2613 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2614 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2615 break;
2616
2617 case IPPROTO_UDP:
2618 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2619 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2620 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2621 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2622
2623 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2624 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2625 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2626 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2627 break;
2628 default:
e98bedf5
EB		 2629 NL_SET_ERR_MSG_MOD(extack,
2630 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2631 netdev_err(priv->netdev,
2632 "Only UDP and TCP transport are supported\n");
2633 return -EINVAL;
2634 }
de0af0bf 2635
8f256622 2636 if (match.mask->src || match.mask->dst)
d708f902 2637 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2638 }
2639
8f256622
PNA		 2640 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2641 struct flow_match_tcp match;
e77834ec 2642
8f256622 2643 flow_rule_match_tcp(rule, &match);
e77834ec 2644 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2645 ntohs(match.mask->flags));
e77834ec 2646 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2647 ntohs(match.key->flags));
e77834ec 2648
8f256622 2649 if (match.mask->flags)
d708f902 2650 *match_level = MLX5_MATCH_L4;
e77834ec 2651 }
a3222a2d
MD		 2652 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2653 struct flow_match_icmp match;
e77834ec 2654
a3222a2d
MD		 2655 flow_rule_match_icmp(rule, &match);
2656 switch (ip_proto) {
2657 case IPPROTO_ICMP:
2658 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2659 MLX5_FLEX_PROTO_ICMP)) {
2660 NL_SET_ERR_MSG_MOD(extack,
2661 "Match on Flex protocols for ICMP is not supported");
a3222a2d 2662 return -EOPNOTSUPP;
0885ae1a 2663 }
a3222a2d
MD		 2664 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2665 match.mask->type);
2666 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2667 match.key->type);
2668 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2669 match.mask->code);
2670 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2671 match.key->code);
2672 break;
2673 case IPPROTO_ICMPV6:
2674 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2675 MLX5_FLEX_PROTO_ICMPV6)) {
2676 NL_SET_ERR_MSG_MOD(extack,
2677 "Match on Flex protocols for ICMPV6 is not supported");
a3222a2d 2678 return -EOPNOTSUPP;
0885ae1a 2679 }
a3222a2d
MD		 2680 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2681 match.mask->type);
2682 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2683 match.key->type);
2684 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2685 match.mask->code);
2686 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2687 match.key->code);
2688 break;
2689 default:
2690 NL_SET_ERR_MSG_MOD(extack,
2691 "Code and type matching only with ICMP and ICMPv6");
2692 netdev_err(priv->netdev,
2693 "Code and type matching only with ICMP and ICMPv6\n");
2694 return -EINVAL;
2695 }
2696 if (match.mask->code || match.mask->type) {
2697 *match_level = MLX5_MATCH_L4;
2698 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2699 }
2700 }
39c538d6 2701 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2702 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2703 !netif_is_bareudp(filter_dev)) {
2704 NL_SET_ERR_MSG_MOD(extack,
2705 "Matching on MPLS is supported only for MPLS over UDP");
2706 netdev_err(priv->netdev,
2707 "Matching on MPLS is supported only for MPLS over UDP\n");
2708 return -EOPNOTSUPP;
2709 }
2710
e3a2b7ed
AV		 2711 return 0;
2712}
2713
de0af0bf 2714static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2715 struct mlx5e_tc_flow *flow,
de0af0bf 2716 struct mlx5_flow_spec *spec,
f9e30088 2717 struct flow_cls_offload *f,
54c177ca 2718 struct net_device *filter_dev)
de0af0bf 2719{
93b3586e 2720 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2721 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2722 struct mlx5_core_dev *dev = priv->mdev;
2723 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2724 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2725 struct mlx5_eswitch_rep *rep;
226f2ca3 2726 bool is_eswitch_flow;
de0af0bf
RD		 2727 int err;
2728
93b3586e
HN		 2729 inner_match_level = MLX5_MATCH_NONE;
2730 outer_match_level = MLX5_MATCH_NONE;
2731
0a7fcb78
PB		 2732 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2733 &inner_match_level, &outer_match_level);
93b3586e
HN		 2734 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2735 outer_match_level : inner_match_level;
de0af0bf 2736
226f2ca3
VB		 2737 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2738 if (!err && is_eswitch_flow) {
1d447a39 2739 rep = rpriv->rep;
b05af6aa 2740 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2741 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2742 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2743 NL_SET_ERR_MSG_MOD(extack,
2744 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2745 netdev_warn(priv->netdev,
2746 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2747 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2748 return -EOPNOTSUPP;
2749 }
2750 }
2751
c620b772
AL		 2752 flow->attr->inner_match_level = inner_match_level;
2753 flow->attr->outer_match_level = outer_match_level;
2754
38aa51c1 2755
de0af0bf
RD		 2756 return err;
2757}
2758
d79b6df6
OG		 2759struct mlx5_fields {
2760 u8 field;
88f30bbc
DL		 2761 u8 field_bsize;
2762 u32 field_mask;
d79b6df6 2763 u32 offset;
27c11b6b 2764 u32 match_offset;
d79b6df6
OG		 2765};
2766
88f30bbc
DL		 2767#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2768 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2769 offsetof(struct pedit_headers, field) + (off), \
2770 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2771
2ef86872
EB		 2772/* masked values are the same and there are no rewrites that do not have a
2773 * match.
2774 */
2775#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2776 type matchmaskx = *(type *)(matchmaskp); \
2777 type matchvalx = *(type *)(matchvalp); \
2778 type maskx = *(type *)(maskp); \
2779 type valx = *(type *)(valp); \
2780 \
2781 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2782 matchmaskx)); \
2783})
2784
27c11b6b 2785static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2786 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2787{
2788 bool same = false;
2789
88f30bbc
DL		 2790 switch (bsize) {
2791 case 8:
2ef86872 2792 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2793 break;
88f30bbc 2794 case 16:
2ef86872 2795 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2796 break;
88f30bbc 2797 case 32:
2ef86872 2798 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2799 break;
2800 }
2801
2802 return same;
2803}
a8e4f0c4 2804
d79b6df6 2805static struct mlx5_fields fields[] = {
88f30bbc
DL		 2806 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2807 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2808 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2809 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2810 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2811 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2812
ab9341b5 2813 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2814 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2815 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2816 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2817
2818 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2819 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2820 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2821 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2822 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2823 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2824 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2825 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2826 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2827 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2828 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2829 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2830 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2831 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2832 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2833 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2834 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2835 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2836
88f30bbc
DL		 2837 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2838 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2839 /* in linux iphdr tcp_flags is 8 bits long */
2840 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2841
88f30bbc
DL		 2842 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2843 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2844};
2845
82198d8b
MD		 2846static unsigned long mask_to_le(unsigned long mask, int size)
2847{
2848 __be32 mask_be32;
2849 __be16 mask_be16;
2850
2851 if (size == 32) {
2852 mask_be32 = (__force __be32)(mask);
2853 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2854 } else if (size == 16) {
2855 mask_be32 = (__force __be32)(mask);
2856 mask_be16 = *(__be16 *)&mask_be32;
2857 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2858 }
2859
2860 return mask;
2861}
09bf9792 2862
6ae4a6a5
PB		 2863static int offload_pedit_fields(struct mlx5e_priv *priv,
2864 int namespace,
e98bedf5 2865 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2866 u32 *action_flags,
e98bedf5 2867 struct netlink_ext_ack *extack)
d79b6df6
OG		 2868{
2869 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
09bf9792 2870 struct pedit_headers_action *hdrs = parse_attr->hdrs;
88f30bbc
DL		 2871 void *headers_c, *headers_v, *action, *vals_p;
2872 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2873 struct mlx5e_tc_mod_hdr_acts *mod_acts;
82198d8b 2874 unsigned long mask, field_mask;
2c0e5cf5
PB		 2875 int i, first, last, next_z;
2876 struct mlx5_fields *f;
88f30bbc
DL		 2877 u8 cmd;
2878
6ae4a6a5 2879 mod_acts = &parse_attr->mod_hdr_acts;
8ee72638
RD		 2880 headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
2881 headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2882
73867881
PNA		 2883 set_masks = &hdrs[0].masks;
2884 add_masks = &hdrs[1].masks;
2885 set_vals = &hdrs[0].vals;
2886 add_vals = &hdrs[1].vals;
d79b6df6 2887
d79b6df6 2888 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2889 bool skip;
2890
d79b6df6
OG		 2891 f = &fields[i];
2892 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2893 s_mask = 0;
2894 a_mask = 0;
d79b6df6
OG		 2895
2896 s_masks_p = (void *)set_masks + f->offset;
2897 a_masks_p = (void *)add_masks + f->offset;
2898
88f30bbc
DL		 2899 s_mask = *s_masks_p & f->field_mask;
2900 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2901
2902 if (!s_mask && !a_mask) /* nothing to offload here */
2903 continue;
2904
2905 if (s_mask && a_mask) {
e98bedf5
EB		 2906 NL_SET_ERR_MSG_MOD(extack,
2907 "can't set and add to the same HW field");
61b6a6c3
CH		 2908 netdev_warn(priv->netdev,
2909 "mlx5: can't set and add to the same HW field (%x)\n",
2910 f->field);
d79b6df6
OG		 2911 return -EOPNOTSUPP;
2912 }
2913
27c11b6b 2914 skip = false;
d79b6df6 2915 if (s_mask) {
27c11b6b
EB		 2916 void *match_mask = headers_c + f->match_offset;
2917 void *match_val = headers_v + f->match_offset;
2918
d79b6df6
OG		 2919 cmd = MLX5_ACTION_TYPE_SET;
2920 mask = s_mask;
2921 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2922 /* don't rewrite if we have a match on the same value */
2923 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2924 match_mask, f->field_bsize))
27c11b6b 2925 skip = true;
d79b6df6 2926 /* clear to denote we consumed this field */
88f30bbc 2927 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2928 } else {
2929 cmd = MLX5_ACTION_TYPE_ADD;
2930 mask = a_mask;
2931 vals_p = (void *)add_vals + f->offset;
27c11b6b 2932 /* add 0 is no change */
88f30bbc 2933 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2934 skip = true;
d79b6df6 2935 /* clear to denote we consumed this field */
88f30bbc 2936 *a_masks_p &= ~f->field_mask;
d79b6df6 2937 }
27c11b6b
EB		 2938 if (skip)
2939 continue;
d79b6df6 2940
82198d8b 2941 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2942
88f30bbc
DL		 2943 first = find_first_bit(&mask, f->field_bsize);
2944 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2945 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2946 if (first < next_z && next_z < last) {
e98bedf5
EB		 2947 NL_SET_ERR_MSG_MOD(extack,
2948 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2949 netdev_warn(priv->netdev,
2950 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2951 mask);
d79b6df6
OG		 2952 return -EOPNOTSUPP;
2953 }
2954
2c0e5cf5
PB		 2955 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
2956 if (IS_ERR(action)) {
6ae4a6a5
PB		 2957 NL_SET_ERR_MSG_MOD(extack,
2958 "too many pedit actions, can't offload");
2959 mlx5_core_warn(priv->mdev,
2960 "mlx5: parsed %d pedit actions, can't do more\n",
2961 mod_acts->num_actions);
2c0e5cf5 2962 return PTR_ERR(action);
6ae4a6a5
PB		 2963 }
2964
d79b6df6
OG		 2965 MLX5_SET(set_action_in, action, action_type, cmd);
2966 MLX5_SET(set_action_in, action, field, f->field);
2967
2968 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2969 int start;
2970
82198d8b
MD		 2971 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2972
88f30bbc 2973 /* if field is bit sized it can start not from first bit */
82198d8b 2974 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2975
2976 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2977 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2978 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2979 }
2980
88f30bbc 2981 if (f->field_bsize == 32)
2b64beba 2982 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2983 else if (f->field_bsize == 16)
2b64beba 2984 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2985 else if (f->field_bsize == 8)
2b64beba 2986 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2987
6ae4a6a5 2988 ++mod_acts->num_actions;
d79b6df6
OG		 2989 }
2990
d79b6df6
OG		 2991 return 0;
2992}
2993
d79b6df6
OG		 2994static const struct pedit_headers zero_masks = {};
2995
918ed7bf
RD		 2996static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
2997 struct mlx5e_tc_flow_parse_attr *parse_attr,
2998 struct netlink_ext_ack *extack)
c500c86b
PNA		 2999{
3000 struct pedit_headers *cmd_masks;
c500c86b
PNA		 3001 u8 cmd;
3002
d79b6df6 3003 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
09bf9792 3004 cmd_masks = &parse_attr->hdrs[cmd].masks;
d79b6df6 3005 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
09bf9792 3006 NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
b3a433de 3007 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3008 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3009 16, 1, cmd_masks, sizeof(zero_masks), true);
918ed7bf 3010 return -EOPNOTSUPP;
d79b6df6
OG		 3011 }
3012 }
3013
3014 return 0;
918ed7bf
RD		 3015}
3016
3017static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3018 struct mlx5e_tc_flow_parse_attr *parse_attr,
3019 u32 *action_flags,
3020 struct netlink_ext_ack *extack)
3021{
3022 int err;
3023
3024 err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3025 if (err)
3026 goto out_dealloc_parsed_actions;
3027
3028 err = verify_offload_pedit_fields(priv, parse_attr, extack);
3029 if (err)
3030 goto out_dealloc_parsed_actions;
3031
3032 return 0;
d79b6df6
OG		 3033
3034out_dealloc_parsed_actions:
2c0e5cf5 3035 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3036 return err;
3037}
3038
8998576b
DL		 3039struct ip_ttl_word {
3040 __u8 ttl;
3041 __u8 protocol;
3042 __sum16 check;
3043};
3044
3045struct ipv6_hoplimit_word {
3046 __be16 payload_len;
3047 __u8 nexthdr;
3048 __u8 hop_limit;
3049};
3050
1836d780
RD		 3051static bool
3052is_action_keys_supported(const struct flow_action_entry *act, bool ct_flow,
3053 bool *modify_ip_header, bool *modify_tuple,
3054 struct netlink_ext_ack *extack)
8998576b
DL		 3055{
3056 u32 mask, offset;
3057 u8 htype;
3058
3059 htype = act->mangle.htype;
3060 offset = act->mangle.offset;
3061 mask = ~act->mangle.mask;
3062 /* For IPv4 & IPv6 header check 4 byte word,
3063 * to determine that modified fields
3064 * are NOT ttl & hop_limit only.
3065 */
3066 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3067 struct ip_ttl_word *ttl_word =
3068 (struct ip_ttl_word *)&mask;
3069
3070 if (offset != offsetof(struct iphdr, ttl) ||
3071 ttl_word->protocol ||
3072 ttl_word->check) {
4c3844d9
PB		 3073 *modify_ip_header = true;
3074 }
3075
7e36feeb
PB		 3076 if (offset >= offsetof(struct iphdr, saddr))
3077 *modify_tuple = true;
3078
3079 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3080 NL_SET_ERR_MSG_MOD(extack,
3081 "can't offload re-write of ipv4 address with action ct");
1836d780 3082 return false;
8998576b
DL		 3083 }
3084 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3085 struct ipv6_hoplimit_word *hoplimit_word =
3086 (struct ipv6_hoplimit_word *)&mask;
3087
3088 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3089 hoplimit_word->payload_len ||
3090 hoplimit_word->nexthdr) {
4c3844d9
PB		 3091 *modify_ip_header = true;
3092 }
3093
7e36feeb
PB		 3094 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3095 *modify_tuple = true;
3096
3097 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3098 NL_SET_ERR_MSG_MOD(extack,
3099 "can't offload re-write of ipv6 address with action ct");
1836d780 3100 return false;
8998576b 3101 }
7e36feeb
PB		 3102 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3103 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3104 *modify_tuple = true;
3105 if (ct_flow) {
3106 NL_SET_ERR_MSG_MOD(extack,
3107 "can't offload re-write of transport header ports with action ct");
1836d780 3108 return false;
7e36feeb 3109 }
8998576b 3110 }
4c3844d9 3111
1836d780 3112 return true;
8998576b
DL		 3113}
3114
96b5b458
DC		 3115static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3116 bool ct_flow, struct netlink_ext_ack *extack,
3117 struct mlx5e_priv *priv,
3118 struct mlx5_flow_spec *spec)
3119{
3120 if (!modify_tuple || ct_clear)
3121 return true;
3122
3123 if (ct_flow) {
3124 NL_SET_ERR_MSG_MOD(extack,
3125 "can't offload tuple modification with non-clear ct()");
3126 netdev_info(priv->netdev,
3127 "can't offload tuple modification with non-clear ct()");
3128 return false;
3129 }
3130
3131 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3132 * (or after clear action), as otherwise, since the tuple is changed,
3133 * we can't restore ct state
3134 */
3135 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3136 NL_SET_ERR_MSG_MOD(extack,
3137 "can't offload tuple modification with ct matches and no ct(clear) action");
3138 netdev_info(priv->netdev,
3139 "can't offload tuple modification with ct matches and no ct(clear) action");
3140 return false;
3141 }
3142
3143 return true;
3144}
3145
3d486ec4
OS		 3146static bool modify_header_match_supported(struct mlx5e_priv *priv,
3147 struct mlx5_flow_spec *spec,
73867881 3148 struct flow_action *flow_action,
4c3844d9 3149 u32 actions, bool ct_flow,
7e36feeb 3150 bool ct_clear,
e98bedf5 3151 struct netlink_ext_ack *extack)
bdd66ac0 3152{
73867881 3153 const struct flow_action_entry *act;
7e36feeb 3154 bool modify_ip_header, modify_tuple;
fca53304 3155 void *headers_c;
bdd66ac0
OG		 3156 void *headers_v;
3157 u16 ethertype;
8998576b 3158 u8 ip_proto;
1836d780 3159 int i;
bdd66ac0 3160
8ee72638
RD		 3161 headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3162 headers_v = mlx5e_get_match_headers_value(actions, spec);
bdd66ac0
OG		 3163 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3164
3165 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3166 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3167 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3168 goto out_ok;
3169
3170 modify_ip_header = false;
7e36feeb 3171 modify_tuple = false;
73867881
PNA		 3172 flow_action_for_each(i, act, flow_action) {
3173 if (act->id != FLOW_ACTION_MANGLE &&
3174 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3175 continue;
3176
1836d780
RD		 3177 if (!is_action_keys_supported(act, ct_flow,
3178 &modify_ip_header,
3179 &modify_tuple, extack))
3180 return false;
bdd66ac0
OG		 3181 }
3182
96b5b458
DC		 3183 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3184 priv, spec))
7e36feeb 3185 return false;
7e36feeb 3186
bdd66ac0 3187 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3188 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3189 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3190 NL_SET_ERR_MSG_MOD(extack,
3191 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3192 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3193 ip_proto);
bdd66ac0
OG		 3194 return false;
3195 }
3196
3197out_ok:
3198 return true;
3199}
3200
9c1d3511
RD		 3201static bool
3202actions_match_supported_fdb(struct mlx5e_priv *priv,
3203 struct mlx5e_tc_flow_parse_attr *parse_attr,
3204 struct mlx5e_tc_flow *flow,
3205 struct netlink_ext_ack *extack)
bdd66ac0 3206{
d4f401d9 3207 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
9c1d3511 3208 bool ct_flow, ct_clear;
bdd66ac0 3209
9c1d3511
RD		 3210 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3211 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3212
d4f401d9
RD		 3213 if (esw_attr->split_count && ct_flow &&
3214 !MLX5_CAP_GEN(esw_attr->in_mdev, reg_c_preserve)) {
9c1d3511
RD		 3215 /* All registers used by ct are cleared when using
3216 * split rules.
3217 */
3218 NL_SET_ERR_MSG_MOD(extack, "Can't offload mirroring with action ct");
3219 return false;
3220 }
3221
d4f401d9
RD		 3222 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3223 NL_SET_ERR_MSG_MOD(extack,
3224 "current firmware doesn't support split rule for port mirroring");
3225 netdev_warn_once(priv->netdev,
3226 "current firmware doesn't support split rule for port mirroring\n");
3227 return false;
3228 }
3229
9c1d3511
RD		 3230 return true;
3231}
3232
3233static bool
3234actions_match_supported(struct mlx5e_priv *priv,
3235 struct flow_action *flow_action,
3236 struct mlx5e_tc_flow_parse_attr *parse_attr,
3237 struct mlx5e_tc_flow *flow,
3238 struct netlink_ext_ack *extack)
3239{
3240 u32 actions = flow->attr->action;
3241 bool ct_flow, ct_clear;
3242
3243 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
c620b772 3244 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
c620b772 3245
6b50cf45
RD		 3246 if (!(actions &
3247 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3248 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
3249 return false;
3250 }
3251
9c1d3511
RD		 3252 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3253 !modify_header_match_supported(priv, &parse_attr->spec, flow_action,
3254 actions, ct_flow, ct_clear, extack))
3255 return false;
bdd66ac0 3256
9c1d3511
RD		 3257 if (mlx5e_is_eswitch_flow(flow) &&
3258 !actions_match_supported_fdb(priv, parse_attr, flow, extack))
3259 return false;
bdd66ac0
OG		 3260
3261 return true;
3262}
3263
32134847
MD		 3264static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3265{
3266 return priv->mdev == peer_priv->mdev;
3267}
3268
ab3f3d5e 3269bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
5c65c564
OG		 3270{
3271 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3272 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3273
3274 fmdev = priv->mdev;
3275 pmdev = peer_priv->mdev;
3276
59c9d35e
AH		 3277 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3278 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3279
816f6706 3280 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3281}
3282
8333d53e
RD		 3283static int
3284parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3285 struct flow_action *flow_action)
3286{
3287 struct netlink_ext_ack *extack = parse_state->extack;
3288 struct mlx5e_tc_flow *flow = parse_state->flow;
3289 struct mlx5_flow_attr *attr = flow->attr;
3290 enum mlx5_flow_namespace_type ns_type;
3291 struct mlx5e_priv *priv = flow->priv;
3292 const struct flow_action_entry *act;
3293 struct mlx5e_tc_act *tc_act;
3294 int err, i;
3295
3296 ns_type = mlx5e_get_flow_namespace(flow);
3297
3298 flow_action_for_each(i, act, flow_action) {
3299 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3300 if (!tc_act) {
3301 NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3302 return -EOPNOTSUPP;
3303 }
3304
8be9686d 3305 if (!tc_act->can_offload(parse_state, act, i, attr))
8333d53e
RD		 3306 return -EOPNOTSUPP;
3307
3308 err = tc_act->parse_action(parse_state, act, priv, attr);
3309 if (err)
3310 return err;
3311 }
3312
dd5ab6d1
RD		 3313 flow_action_for_each(i, act, flow_action) {
3314 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3315 if (!tc_act || !tc_act->post_parse ||
8be9686d 3316 !tc_act->can_offload(parse_state, act, i, attr))
dd5ab6d1
RD		 3317 continue;
3318
3319 err = tc_act->post_parse(parse_state, priv, attr);
3320 if (err)
3321 return err;
3322 }
3323
8333d53e
RD		 3324 return 0;
3325}
3326
d9581e2f
RD		 3327static int
3328actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
e98bedf5 3329 struct mlx5e_tc_flow *flow,
d9581e2f 3330 struct mlx5_flow_attr *attr,
e98bedf5 3331 struct netlink_ext_ack *extack)
d9581e2f
RD		 3332{
3333 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
09bf9792 3334 struct pedit_headers_action *hdrs = parse_attr->hdrs;
d9581e2f
RD		 3335 enum mlx5_flow_namespace_type ns_type;
3336 int err;
3337
3338 if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3339 !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3340 return 0;
3341
e36db1ee 3342 ns_type = mlx5e_get_flow_namespace(flow);
d9581e2f 3343
09bf9792 3344 err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
d9581e2f
RD		 3345 if (err)
3346 return err;
3347
d9581e2f
RD		 3348 if (parse_attr->mod_hdr_acts.num_actions > 0)
3349 return 0;
3350
fc3a879a 3351 /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
d9581e2f 3352 attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2c0e5cf5 3353 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d9581e2f
RD		 3354
3355 if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3356 return 0;
3357
3358 if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3359 (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3360 attr->esw_attr->split_count = 0;
3361
3362 return 0;
3363}
3364
df990477
RD		 3365static int
3366flow_action_supported(struct flow_action *flow_action,
3367 struct netlink_ext_ack *extack)
3368{
3369 if (!flow_action_has_entries(flow_action)) {
3370 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3371 return -EINVAL;
3372 }
3373
3374 if (!flow_action_hw_stats_check(flow_action, extack,
3375 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3376 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
3377 return -EOPNOTSUPP;
3378 }
3379
3380 return 0;
3381}
3382
d9581e2f
RD		 3383static int
3384parse_tc_nic_actions(struct mlx5e_priv *priv,
3385 struct flow_action *flow_action,
3386 struct mlx5e_tc_flow *flow,
3387 struct netlink_ext_ack *extack)
e3a2b7ed 3388{
fad54790 3389 struct mlx5e_tc_act_parse_state *parse_state;
c6cfe113 3390 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3391 struct mlx5_flow_attr *attr = flow->attr;
8333d53e 3392 int err;
e3a2b7ed 3393
df990477
RD		 3394 err = flow_action_supported(flow_action, extack);
3395 if (err)
3396 return err;
319a1d19 3397
fad54790 3398 attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3399 parse_attr = attr->parse_attr;
fad54790
RD		 3400 parse_state = &parse_attr->parse_state;
3401 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3402 parse_state->ct_priv = get_ct_priv(priv);
e3a2b7ed 3403
8333d53e
RD		 3404 err = parse_tc_actions(parse_state, flow_action);
3405 if (err)
3406 return err;
e3a2b7ed 3407
09bf9792 3408 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
d9581e2f
RD		 3409 if (err)
3410 return err;
3411
73867881 3412 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3413 return -EOPNOTSUPP;
3414
e3a2b7ed
AV		 3415 return 0;
3416}
3417
32134847 3418static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3419 struct net_device *peer_netdev)
3420{
3421 struct mlx5e_priv *peer_priv;
3422
3423 peer_priv = netdev_priv(peer_netdev);
3424
3425 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3426 mlx5e_eswitch_vf_rep(priv->netdev) &&
3427 mlx5e_eswitch_vf_rep(peer_netdev) &&
ab3f3d5e 3428 mlx5e_same_hw_devs(priv, peer_priv));
d34eb2fc
OG		 3429}
3430
32134847
MD		 3431static bool same_hw_reps(struct mlx5e_priv *priv,
3432 struct net_device *peer_netdev)
3433{
3434 struct mlx5e_priv *peer_priv;
3435
3436 peer_priv = netdev_priv(peer_netdev);
3437
3438 return mlx5e_eswitch_rep(priv->netdev) &&
3439 mlx5e_eswitch_rep(peer_netdev) &&
ab3f3d5e 3440 mlx5e_same_hw_devs(priv, peer_priv);
32134847
MD		 3441}
3442
3443static bool is_lag_dev(struct mlx5e_priv *priv,
3444 struct net_device *peer_netdev)
3445{
3446 return ((mlx5_lag_is_sriov(priv->mdev) ||
3447 mlx5_lag_is_multipath(priv->mdev)) &&
3448 same_hw_reps(priv, peer_netdev));
3449}
3450
f6dc1264
PB		 3451bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3452 struct net_device *out_dev)
3453{
32134847
MD		 3454 if (is_merged_eswitch_vfs(priv, out_dev))
3455 return true;
3456
3457 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3458 return true;
3459
3460 return mlx5e_eswitch_rep(out_dev) &&
32134847 3461 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3462}
3463
27484f71
AL		 3464int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
3465 struct mlx5_flow_attr *attr,
3466 int ifindex,
3467 enum mlx5e_tc_int_port_type type,
3468 u32 *action,
3469 int out_index)
3470{
3471 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
3472 struct mlx5e_tc_int_port_priv *int_port_priv;
3473 struct mlx5e_tc_flow_parse_attr *parse_attr;
3474 struct mlx5e_tc_int_port *dest_int_port;
3475 int err;
3476
3477 parse_attr = attr->parse_attr;
3478 int_port_priv = mlx5e_get_int_port_priv(priv);
3479
3480 dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
3481 if (IS_ERR(dest_int_port))
3482 return PTR_ERR(dest_int_port);
3483
3484 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
3485 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
3486 mlx5e_tc_int_port_get_metadata(dest_int_port));
3487 if (err) {
3488 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
3489 return err;
3490 }
3491
3492 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3493
3494 esw_attr->dest_int_port = dest_int_port;
3495 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
3496
3497 /* Forward to root fdb for matching against the new source vport */
3498 attr->dest_chain = 0;
3499
3500 return 0;
3501}
3502
8333d53e
RD		 3503static int
3504parse_tc_fdb_actions(struct mlx5e_priv *priv,
3505 struct flow_action *flow_action,
3506 struct mlx5e_tc_flow *flow,
3507 struct netlink_ext_ack *extack)
03a9d11e 3508{
fad54790 3509 struct mlx5e_tc_act_parse_state *parse_state;
c620b772 3510 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3511 struct mlx5_flow_attr *attr = flow->attr;
c620b772 3512 struct mlx5_esw_flow_attr *esw_attr;
8333d53e 3513 int err;
03a9d11e 3514
df990477
RD		 3515 err = flow_action_supported(flow_action, extack);
3516 if (err)
3517 return err;
319a1d19 3518
c620b772
AL		 3519 esw_attr = attr->esw_attr;
3520 parse_attr = attr->parse_attr;
fad54790
RD		 3521 parse_state = &parse_attr->parse_state;
3522 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3523 parse_state->ct_priv = get_ct_priv(priv);
c620b772 3524
8333d53e
RD		 3525 err = parse_tc_actions(parse_state, flow_action);
3526 if (err)
3527 return err;
bdd66ac0 3528
166f431e
AL		 3529 /* Forward to/from internal port can only have 1 dest */
3530 if ((netif_is_ovs_master(parse_attr->filter_dev) || esw_attr->dest_int_port) &&
3531 esw_attr->out_count > 1) {
27484f71 3532 NL_SET_ERR_MSG_MOD(extack,
166f431e 3533 "Rules with internal port can have only one destination");
27484f71
AL		 3534 return -EOPNOTSUPP;
3535 }
3536
09bf9792 3537 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
d9581e2f
RD		 3538 if (err)
3539 return err;
3540
73867881 3541 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3542 return -EOPNOTSUPP;
3543
31c8eba5 3544 return 0;
03a9d11e
OG		 3545}
3546
226f2ca3 3547static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3548{
226f2ca3 3549 unsigned long __flow_flags = 0;
60bd4af8 3550
226f2ca3
VB		 3551 if (flags & MLX5_TC_FLAG(INGRESS))
3552 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3553 if (flags & MLX5_TC_FLAG(EGRESS))
3554 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3555
226f2ca3
VB		 3556 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3557 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3558 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3559 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3560 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3561 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3562
60bd4af8
OG		 3563 *flow_flags = __flow_flags;
3564}
3565
05866c82
OG		 3566static const struct rhashtable_params tc_ht_params = {
3567 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3568 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3569 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3570 .automatic_shrinking = true,
3571};
3572
226f2ca3
VB		 3573static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3574 unsigned long flags)
05866c82 3575{
655dc3d2
OG		 3576 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3577 struct mlx5e_rep_priv *uplink_rpriv;
3578
226f2ca3 3579 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3580 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3581 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3582 } else /* NIC offload */
655dc3d2 3583 return &priv->fs.tc.ht;
05866c82
OG		 3584}
3585
04de7dda
RD		 3586static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3587{
c620b772
AL		 3588 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3589 struct mlx5_flow_attr *attr = flow->attr;
3590 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3591 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3592 bool act_is_encap = !!(attr->action &
3593 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 3594 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 3595 MLX5_DEVCOM_ESW_OFFLOADS);
3596
10fbb1cd
RD		 3597 if (!esw_paired)
3598 return false;
3599
c620b772
AL		 3600 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
3601 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 3602 (is_rep_ingress || act_is_encap))
3603 return true;
3604
3605 return false;
04de7dda
RD		 3606}
3607
c620b772
AL		 3608struct mlx5_flow_attr *
3609mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
3610{
3611 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
3612 sizeof(struct mlx5_esw_flow_attr) :
3613 sizeof(struct mlx5_nic_flow_attr);
3614 struct mlx5_flow_attr *attr;
3615
3616 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
3617}
3618
a88780a9
RD		 3619static int
3620mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3621 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3622 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3623 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3624{
17091853 3625 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3626 struct mlx5_flow_attr *attr;
3bc4b7bf 3627 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 3628 int err = -ENOMEM;
3629 int out_index;
e3a2b7ed 3630
c620b772 3631 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 3632 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 3633 if (!parse_attr || !flow)
3634 goto err_free;
c620b772
AL		 3635
3636 flow->flags = flow_flags;
3637 flow->cookie = f->cookie;
3638 flow->priv = priv;
3639
e36db1ee 3640 attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
ff7ea04a 3641 if (!attr)
e3a2b7ed 3642 goto err_free;
ff7ea04a 3643
c620b772 3644 flow->attr = attr;
e3a2b7ed 3645
5a7e5bcb
VB		 3646 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3647 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 3648 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 3649 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 3650 refcount_set(&flow->refcnt, 1);
95435ad7 3651 init_completion(&flow->init_done);
362980ea 3652 init_completion(&flow->del_hw_done);
e3a2b7ed 3653
a88780a9
RD		 3654 *__flow = flow;
3655 *__parse_attr = parse_attr;
3656
3657 return 0;
3658
3659err_free:
3660 kfree(flow);
3661 kvfree(parse_attr);
3662 return err;
3663}
3664
c7569097
AL		 3665static void
3666mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
3667 struct mlx5e_tc_flow_parse_attr *parse_attr,
3668 struct flow_cls_offload *f)
3669{
3670 attr->parse_attr = parse_attr;
3671 attr->chain = f->common.chain_index;
3672 attr->prio = f->common.prio;
3673}
3674
988ab9c7 3675static void
c620b772 3676mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 3677 struct mlx5e_priv *priv,
3678 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3679 struct flow_cls_offload *f,
988ab9c7
TZ		 3680 struct mlx5_eswitch_rep *in_rep,
3681 struct mlx5_core_dev *in_mdev)
3682{
3683 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3684 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 3685
c7569097 3686 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 3687
3688 esw_attr->in_rep = in_rep;
3689 esw_attr->in_mdev = in_mdev;
3690
3691 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3692 MLX5_COUNTER_SOURCE_ESWITCH)
3693 esw_attr->counter_dev = in_mdev;
3694 else
3695 esw_attr->counter_dev = priv->mdev;
3696}
3697
71129676 3698static struct mlx5e_tc_flow *
04de7dda 3699__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3700 struct flow_cls_offload *f,
226f2ca3 3701 unsigned long flow_flags,
04de7dda
RD		 3702 struct net_device *filter_dev,
3703 struct mlx5_eswitch_rep *in_rep,
71129676 3704 struct mlx5_core_dev *in_mdev)
a88780a9 3705{
f9e30088 3706 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3707 struct netlink_ext_ack *extack = f->common.extack;
3708 struct mlx5e_tc_flow_parse_attr *parse_attr;
3709 struct mlx5e_tc_flow *flow;
3710 int attr_size, err;
e3a2b7ed 3711
226f2ca3 3712 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3713 attr_size = sizeof(struct mlx5_esw_flow_attr);
3714 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3715 &parse_attr, &flow);
3716 if (err)
3717 goto out;
988ab9c7 3718
d11afc26 3719 parse_attr->filter_dev = filter_dev;
c620b772 3720 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 3721 priv, parse_attr,
3722 f, in_rep, in_mdev);
3723
54c177ca
OS		 3724 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3725 f, filter_dev);
d11afc26
OS		 3726 if (err)
3727 goto err_free;
a88780a9 3728
7e36feeb 3729 /* actions validation depends on parsing the ct matches first */
aedd133d 3730 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 3731 &flow->attr->ct_attr, extack);
a88780a9
RD		 3732 if (err)
3733 goto err_free;
3734
d4bb0531
RD		 3735 /* always set IP version for indirect table handling */
3736 flow->attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3737
70f8019e 3738 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 3739 if (err)
3740 goto err_free;
3741
7040632d 3742 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3743 complete_all(&flow->init_done);
ef06c9ee
RD		 3744 if (err) {
3745 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3746 goto err_free;
3747
b4a23329 3748 add_unready_flow(flow);
ef06c9ee 3749 }
e3a2b7ed 3750
71129676 3751 return flow;
a88780a9
RD		 3752
3753err_free:
5a7e5bcb 3754 mlx5e_flow_put(priv, flow);
a88780a9 3755out:
71129676 3756 return ERR_PTR(err);
a88780a9
RD		 3757}
3758
f9e30088 3759static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3760 struct mlx5e_tc_flow *flow,
226f2ca3 3761 unsigned long flow_flags)
04de7dda
RD		 3762{
3763 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3764 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 3765 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 3766 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3767 struct mlx5e_tc_flow_parse_attr *parse_attr;
3768 struct mlx5e_rep_priv *peer_urpriv;
3769 struct mlx5e_tc_flow *peer_flow;
3770 struct mlx5_core_dev *in_mdev;
3771 int err = 0;
3772
3773 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3774 if (!peer_esw)
3775 return -ENODEV;
3776
3777 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3778 peer_priv = netdev_priv(peer_urpriv->netdev);
3779
3780 /* in_mdev is assigned of which the packet originated from.
3781 * So packets redirected to uplink use the same mdev of the
3782 * original flow and packets redirected from uplink use the
3783 * peer mdev.
3784 */
c620b772 3785 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3786 in_mdev = peer_priv->mdev;
3787 else
3788 in_mdev = priv->mdev;
3789
c620b772 3790 parse_attr = flow->attr->parse_attr;
95dc1902 3791 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 3792 parse_attr->filter_dev,
c620b772 3793 attr->in_rep, in_mdev);
71129676
JG		 3794 if (IS_ERR(peer_flow)) {
3795 err = PTR_ERR(peer_flow);
04de7dda 3796 goto out;
71129676 3797 }
04de7dda
RD		 3798
3799 flow->peer_flow = peer_flow;
226f2ca3 3800 flow_flag_set(flow, DUP);
04de7dda
RD		 3801 mutex_lock(&esw->offloads.peer_mutex);
3802 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3803 mutex_unlock(&esw->offloads.peer_mutex);
3804
3805out:
3806 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3807 return err;
3808}
3809
3810static int
3811mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3812 struct flow_cls_offload *f,
226f2ca3 3813 unsigned long flow_flags,
04de7dda
RD		 3814 struct net_device *filter_dev,
3815 struct mlx5e_tc_flow **__flow)
3816{
3817 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3818 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3819 struct mlx5_core_dev *in_mdev = priv->mdev;
3820 struct mlx5e_tc_flow *flow;
3821 int err;
3822
71129676
JG		 3823 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3824 in_mdev);
3825 if (IS_ERR(flow))
3826 return PTR_ERR(flow);
04de7dda
RD		 3827
3828 if (is_peer_flow_needed(flow)) {
95dc1902 3829 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3830 if (err) {
3831 mlx5e_tc_del_fdb_flow(priv, flow);
3832 goto out;
3833 }
3834 }
3835
3836 *__flow = flow;
3837
3838 return 0;
3839
3840out:
3841 return err;
3842}
3843
a88780a9
RD		 3844static int
3845mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3846 struct flow_cls_offload *f,
226f2ca3 3847 unsigned long flow_flags,
d11afc26 3848 struct net_device *filter_dev,
a88780a9
RD		 3849 struct mlx5e_tc_flow **__flow)
3850{
f9e30088 3851 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3852 struct netlink_ext_ack *extack = f->common.extack;
3853 struct mlx5e_tc_flow_parse_attr *parse_attr;
3854 struct mlx5e_tc_flow *flow;
3855 int attr_size, err;
3856
c7569097
AL		 3857 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
3858 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3859 return -EOPNOTSUPP;
3860 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 3861 return -EOPNOTSUPP;
c7569097 3862 }
bf07aa73 3863
226f2ca3 3864 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3865 attr_size = sizeof(struct mlx5_nic_flow_attr);
3866 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3867 &parse_attr, &flow);
3868 if (err)
3869 goto out;
3870
d11afc26 3871 parse_attr->filter_dev = filter_dev;
c7569097
AL		 3872 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
3873
54c177ca
OS		 3874 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3875 f, filter_dev);
d11afc26
OS		 3876 if (err)
3877 goto err_free;
3878
aedd133d
AL		 3879 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
3880 &flow->attr->ct_attr, extack);
3881 if (err)
3882 goto err_free;
3883
c6cfe113 3884 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3885 if (err)
3886 goto err_free;
3887
c6cfe113 3888 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 3889 if (err)
3890 goto err_free;
3891
226f2ca3 3892 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3893 *__flow = flow;
3894
3895 return 0;
e3a2b7ed 3896
e3a2b7ed 3897err_free:
8914add2 3898 flow_flag_set(flow, FAILED);
2c0e5cf5 3899 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
5a7e5bcb 3900 mlx5e_flow_put(priv, flow);
a88780a9
RD		 3901out:
3902 return err;
3903}
3904
3905static int
3906mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3907 struct flow_cls_offload *f,
226f2ca3 3908 unsigned long flags,
d11afc26 3909 struct net_device *filter_dev,
a88780a9
RD		 3910 struct mlx5e_tc_flow **flow)
3911{
3912 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3913 unsigned long flow_flags;
a88780a9
RD		 3914 int err;
3915
3916 get_flags(flags, &flow_flags);
3917
bf07aa73
PB		 3918 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3919 return -EOPNOTSUPP;
3920
f6455de0 3921 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3922 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3923 filter_dev, flow);
a88780a9 3924 else
d11afc26
OS		 3925 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3926 filter_dev, flow);
a88780a9
RD		 3927
3928 return err;
3929}
3930
553f9328
VP		 3931static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
3932 struct mlx5e_rep_priv *rpriv)
3933{
3934 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 3935 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
3936 * function is called from NIC mode.
553f9328 3937 */
2fb15e72 3938 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 3939}
3940
71d82d2a 3941int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3942 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3943{
3944 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3945 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 3946 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 3947 struct mlx5e_tc_flow *flow;
3948 int err = 0;
3949
7dc84de9
RD		 3950 if (!mlx5_esw_hold(priv->mdev))
3951 return -EAGAIN;
3952
3953 mlx5_esw_get(priv->mdev);
3954
c5d326b2
VB		 3955 rcu_read_lock();
3956 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 3957 if (flow) {
553f9328
VP		 3958 /* Same flow rule offloaded to non-uplink representor sharing tc block,
3959 * just return 0.
3960 */
3961 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 3962 goto rcu_unlock;
553f9328 3963
a88780a9
RD		 3964 NL_SET_ERR_MSG_MOD(extack,
3965 "flow cookie already exists, ignoring");
3966 netdev_warn_once(priv->netdev,
3967 "flow cookie %lx already exists, ignoring\n",
3968 f->cookie);
0e1c1a2f 3969 err = -EEXIST;
c1aea9e1 3970 goto rcu_unlock;
a88780a9 3971 }
c1aea9e1
VB		 3972rcu_unlock:
3973 rcu_read_unlock();
3974 if (flow)
3975 goto out;
a88780a9 3976
7a978759 3977 trace_mlx5e_configure_flower(f);
d11afc26 3978 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3979 if (err)
3980 goto out;
3981
553f9328
VP		 3982 /* Flow rule offloaded to non-uplink representor sharing tc block,
3983 * set the flow's owner dev.
3984 */
3985 if (is_flow_rule_duplicate_allowed(dev, rpriv))
3986 flow->orig_dev = dev;
3987
c5d326b2 3988 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3989 if (err)
3990 goto err_free;
3991
7dc84de9 3992 mlx5_esw_release(priv->mdev);
a88780a9
RD		 3993 return 0;
3994
3995err_free:
5a7e5bcb 3996 mlx5e_flow_put(priv, flow);
a88780a9 3997out:
7dc84de9
RD		 3998 mlx5_esw_put(priv->mdev);
3999 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4000 return err;
4001}
4002
8f8ae895
OG		 4003static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4004{
226f2ca3
VB		 4005 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4006 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4007
226f2ca3
VB		 4008 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4009 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4010}
4011
71d82d2a 4012int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4013 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4014{
d9ee0491 4015 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4016 struct mlx5e_tc_flow *flow;
c5d326b2 4017 int err;
e3a2b7ed 4018
c5d326b2 4019 rcu_read_lock();
ab818362 4020 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4021 if (!flow || !same_flow_direction(flow, flags)) {
4022 err = -EINVAL;
4023 goto errout;
4024 }
e3a2b7ed 4025
c5d326b2
VB		 4026 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4027 * set.
4028 */
4029 if (flow_flag_test_and_set(flow, DELETED)) {
4030 err = -EINVAL;
4031 goto errout;
4032 }
05866c82 4033 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4034 rcu_read_unlock();
e3a2b7ed 4035
7a978759 4036 trace_mlx5e_delete_flower(f);
5a7e5bcb 4037 mlx5e_flow_put(priv, flow);
e3a2b7ed 4038
7dc84de9 4039 mlx5_esw_put(priv->mdev);
e3a2b7ed 4040 return 0;
c5d326b2
VB		 4041
4042errout:
4043 rcu_read_unlock();
4044 return err;
e3a2b7ed
AV		 4045}
4046
71d82d2a 4047int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4048 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4049{
04de7dda 4050 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4051 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4052 struct mlx5_eswitch *peer_esw;
aad7e08d 4053 struct mlx5e_tc_flow *flow;
aad7e08d 4054 struct mlx5_fc *counter;
316d5f72
RD		 4055 u64 lastuse = 0;
4056 u64 packets = 0;
4057 u64 bytes = 0;
5a7e5bcb 4058 int err = 0;
aad7e08d 4059
c5d326b2
VB		 4060 rcu_read_lock();
4061 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4062 tc_ht_params));
4063 rcu_read_unlock();
5a7e5bcb
VB		 4064 if (IS_ERR(flow))
4065 return PTR_ERR(flow);
4066
4067 if (!same_flow_direction(flow, flags)) {
4068 err = -EINVAL;
4069 goto errout;
4070 }
aad7e08d 4071
4c3844d9 4072 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4073 counter = mlx5e_tc_get_counter(flow);
4074 if (!counter)
5a7e5bcb 4075 goto errout;
aad7e08d 4076
316d5f72
RD		 4077 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4078 }
aad7e08d 4079
316d5f72
RD		 4080 /* Under multipath it's possible for one rule to be currently
4081 * un-offloaded while the other rule is offloaded.
4082 */
04de7dda
RD		 4083 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4084 if (!peer_esw)
4085 goto out;
4086
226f2ca3
VB		 4087 if (flow_flag_test(flow, DUP) &&
4088 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4089 u64 bytes2;
4090 u64 packets2;
4091 u64 lastuse2;
4092
4093 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4094 if (!counter)
4095 goto no_peer_counter;
04de7dda
RD		 4096 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4097
4098 bytes += bytes2;
4099 packets += packets2;
4100 lastuse = max_t(u64, lastuse, lastuse2);
4101 }
4102
316d5f72 4103no_peer_counter:
04de7dda 4104 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4105out:
4b61d3e8 4106 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4107 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4108 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4109errout:
4110 mlx5e_flow_put(priv, flow);
4111 return err;
aad7e08d
AV		 4112}
4113
1fe3e316 4114static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4115 struct netlink_ext_ack *extack)
4116{
4117 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4118 struct mlx5_eswitch *esw;
1fe3e316 4119 u32 rate_mbps = 0;
fcb64c0f 4120 u16 vport_num;
fcb64c0f
EC		 4121 int err;
4122
e401a184
EC		 4123 vport_num = rpriv->rep->vport;
4124 if (vport_num >= MLX5_VPORT_ECPF) {
4125 NL_SET_ERR_MSG_MOD(extack,
4126 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4127 return -EOPNOTSUPP;
4128 }
4129
fcb64c0f
EC		 4130 esw = priv->mdev->priv.eswitch;
4131 /* rate is given in bytes/sec.
4132 * First convert to bits/sec and then round to the nearest mbit/secs.
4133 * mbit means million bits.
4134 * Moreover, if rate is non zero we choose to configure to a minimum of
4135 * 1 mbit/sec.
4136 */
1fe3e316
PP		 4137 if (rate) {
4138 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4139 do_div(rate, 1000000);
4140 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4141 }
4142
2d116e3e 4143 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4144 if (err)
4145 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4146
4147 return err;
4148}
4149
4150static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4151 struct flow_action *flow_action,
4152 struct netlink_ext_ack *extack)
4153{
4154 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4155 const struct flow_action_entry *act;
4156 int err;
4157 int i;
4158
4159 if (!flow_action_has_entries(flow_action)) {
4160 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4161 return -EINVAL;
4162 }
4163
4164 if (!flow_offload_has_one_action(flow_action)) {
4165 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4166 return -EOPNOTSUPP;
4167 }
4168
0885ae1a
A		 4169 if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4170 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 4171 return -EOPNOTSUPP;
0885ae1a 4172 }
319a1d19 4173
fcb64c0f
EC		 4174 flow_action_for_each(i, act, flow_action) {
4175 switch (act->id) {
4176 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4177 if (act->police.rate_pkt_ps) {
4178 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4179 return -EOPNOTSUPP;
4180 }
fcb64c0f
EC		 4181 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4182 if (err)
4183 return err;
4184
4185 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4186 break;
4187 default:
4188 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4189 return -EOPNOTSUPP;
4190 }
4191 }
4192
4193 return 0;
4194}
4195
4196int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4197 struct tc_cls_matchall_offload *ma)
4198{
4199 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4200
7b83355f 4201 if (ma->common.prio != 1) {
fcb64c0f
EC		 4202 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4203 return -EINVAL;
4204 }
4205
4206 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4207}
4208
4209int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4210 struct tc_cls_matchall_offload *ma)
4211{
4212 struct netlink_ext_ack *extack = ma->common.extack;
4213
4214 return apply_police_params(priv, 0, extack);
4215}
4216
4217void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4218 struct tc_cls_matchall_offload *ma)
4219{
4220 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4221 struct rtnl_link_stats64 cur_stats;
4222 u64 dbytes;
4223 u64 dpkts;
4224
4225 cur_stats = priv->stats.vf_vport;
4226 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4227 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4228 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4229 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4230 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4231}
4232
4d8fcf21
AH		 4233static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4234 struct mlx5e_priv *peer_priv)
4235{
4236 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4237 struct mlx5e_hairpin_entry *hpe, *tmp;
4238 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4239 u16 peer_vhca_id;
4240 int bkt;
4241
ab3f3d5e 4242 if (!mlx5e_same_hw_devs(priv, peer_priv))
4d8fcf21
AH		 4243 return;
4244
4245 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4246
b32accda 4247 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4248 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4249 if (refcount_inc_not_zero(&hpe->refcnt))
4250 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4251 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4252
4253 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4254 wait_for_completion(&hpe->res_ready);
4255 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4256 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4257
4258 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4259 }
4260}
4261
4262static int mlx5e_tc_netdev_event(struct notifier_block *this,
4263 unsigned long event, void *ptr)
4264{
4265 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4266 struct mlx5e_flow_steering *fs;
4267 struct mlx5e_priv *peer_priv;
4268 struct mlx5e_tc_table *tc;
4269 struct mlx5e_priv *priv;
4270
4271 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4272 event != NETDEV_UNREGISTER ||
4273 ndev->reg_state == NETREG_REGISTERED)
4274 return NOTIFY_DONE;
4275
4276 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4277 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4278 priv = container_of(fs, struct mlx5e_priv, fs);
4279 peer_priv = netdev_priv(ndev);
4280 if (priv == peer_priv ||
4281 !(priv->netdev->features & NETIF_F_HW_TC))
4282 return NOTIFY_DONE;
4283
4284 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4285
4286 return NOTIFY_DONE;
4287}
4288
6a064674
AL		 4289static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4290{
4291 int tc_grp_size, tc_tbl_size;
4292 u32 max_flow_counter;
4293
4294 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4295 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4296
4297 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4298
4299 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4300 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4301
4302 return tc_tbl_size;
4303}
4304
655dc3d2 4305int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4306{
acff797c 4307 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4308 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4309 struct mapping_ctx *chains_mapping;
6a064674 4310 struct mlx5_chains_attr attr = {};
2198b932 4311 u64 mapping_id;
4d8fcf21 4312 int err;
e8f887ac 4313
b2fdf3d0 4314 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4315 mutex_init(&tc->t_lock);
b32accda 4316 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4317 hash_init(tc->hairpin_tbl);
11c9c548 4318
4d8fcf21
AH		 4319 err = rhashtable_init(&tc->ht, &tc_ht_params);
4320 if (err)
4321 return err;
4322
9ba33339
RD		 4323 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4324
2198b932
RD		 4325 mapping_id = mlx5_query_nic_system_image_guid(dev);
4326
4327 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4328 sizeof(struct mlx5_mapped_obj),
4329 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4330
c9355682
CM		 4331 if (IS_ERR(chains_mapping)) {
4332 err = PTR_ERR(chains_mapping);
4333 goto err_mapping;
4334 }
4335 tc->mapping = chains_mapping;
4336
4337 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4338 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4339 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4340 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4341 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4342 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4343 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4344 attr.mapping = chains_mapping;
6a064674
AL		 4345
4346 tc->chains = mlx5_chains_create(dev, &attr);
4347 if (IS_ERR(tc->chains)) {
4348 err = PTR_ERR(tc->chains);
4349 goto err_chains;
4350 }
4351
f0da4daa 4352 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4353 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4354 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4355
4d8fcf21 4356 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4357 err = register_netdevice_notifier_dev_net(priv->netdev,
4358 &tc->netdevice_nb,
4359 &tc->netdevice_nn);
4360 if (err) {
4d8fcf21
AH		 4361 tc->netdevice_nb.notifier_call = NULL;
4362 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4363 goto err_reg;
4d8fcf21
AH		 4364 }
4365
6a064674
AL		 4366 return 0;
4367
4368err_reg:
aedd133d 4369 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4370 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4371 mlx5_chains_destroy(tc->chains);
4372err_chains:
c9355682
CM		 4373 mapping_destroy(chains_mapping);
4374err_mapping:
6a064674 4375 rhashtable_destroy(&tc->ht);
4d8fcf21 4376 return err;
e8f887ac
AV		 4377}
4378
4379static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4380{
4381 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4382 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4383
961e8979 4384 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4385 kfree(flow);
4386}
4387
655dc3d2 4388void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4389{
acff797c 4390 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4391
4d8fcf21 4392 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4393 unregister_netdevice_notifier_dev_net(priv->netdev,
4394 &tc->netdevice_nb,
4395 &tc->netdevice_nn);
4d8fcf21 4396
b2fdf3d0 4397 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4398 mutex_destroy(&tc->hairpin_tbl_lock);
4399
6a064674 4400 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4401
acff797c 4402 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4403 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4404 tc->t = NULL;
e8f887ac 4405 }
b6fac0b4 4406 mutex_destroy(&tc->t_lock);
6a064674 4407
aedd133d 4408 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4409 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4410 mapping_destroy(tc->mapping);
6a064674 4411 mlx5_chains_destroy(tc->chains);
e8f887ac 4412}
655dc3d2
OG		 4413
4414int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4415{
d7a42ad0 4416 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4417 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4418 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4419 struct mapping_ctx *mapping;
aedd133d
AL		 4420 struct mlx5_eswitch *esw;
4421 struct mlx5e_priv *priv;
2198b932 4422 u64 mapping_id;
aedd133d 4423 int err = 0;
0a7fcb78
PB		 4424
4425 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4426 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4427 priv = netdev_priv(rpriv->netdev);
4428 esw = priv->mdev->priv.eswitch;
0a7fcb78 4429
f0da4daa
CM		 4430 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
4431 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 4432 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4433 esw_chains(esw),
4434 &esw->offloads.mod_hdr,
f0da4daa
CM		 4435 MLX5_FLOW_NAMESPACE_FDB,
4436 uplink_priv->post_act);
4c3844d9 4437
4f4edcc2
AL		 4438 uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
4439
2741f223 4440 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 4441
2198b932
RD		 4442 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
4443
4444 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
4445 sizeof(struct tunnel_match_key),
4446 TUNNEL_INFO_BITS_MASK, true);
4447
0a7fcb78
PB		 4448 if (IS_ERR(mapping)) {
4449 err = PTR_ERR(mapping);
4450 goto err_tun_mapping;
4451 }
4452 uplink_priv->tunnel_mapping = mapping;
4453
3222efd4
VB		 4454 /* Two last values are reserved for stack devices slow path table mark
4455 * and bridge ingress push mark.
4456 */
2198b932 4457 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
3222efd4 4458 sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
0a7fcb78
PB		 4459 if (IS_ERR(mapping)) {
4460 err = PTR_ERR(mapping);
4461 goto err_enc_opts_mapping;
4462 }
4463 uplink_priv->tunnel_enc_opts_mapping = mapping;
4464
4465 err = rhashtable_init(tc_ht, &tc_ht_params);
4466 if (err)
4467 goto err_ht_init;
4468
9ba33339
RD		 4469 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4470
8914add2 4471 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4472 if (IS_ERR(uplink_priv->encap)) {
4473 err = PTR_ERR(uplink_priv->encap);
8914add2 4474 goto err_register_fib_notifier;
2b6c3c1e 4475 }
8914add2 4476
2b6c3c1e 4477 return 0;
0a7fcb78 4478
8914add2
VB		 4479err_register_fib_notifier:
4480 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 4481err_ht_init:
4482 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4483err_enc_opts_mapping:
4484 mapping_destroy(uplink_priv->tunnel_mapping);
4485err_tun_mapping:
0027d70c 4486 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4487 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4488 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4489 netdev_warn(priv->netdev,
4490 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 4491 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 4492 return err;
655dc3d2
OG		 4493}
4494
4495void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4496{
0a7fcb78
PB		 4497 struct mlx5_rep_uplink_priv *uplink_priv;
4498
0a7fcb78 4499 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 4500
8914add2
VB		 4501 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4502 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4503
0a7fcb78
PB		 4504 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4505 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4506
0027d70c 4507 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4508 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4509 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 4510 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 4511}
01252a27 4512
226f2ca3 4513int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4514{
d9ee0491 4515 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4516
4517 return atomic_read(&tc_ht->nelems);
4518}
04de7dda
RD		 4519
4520void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4521{
4522 struct mlx5e_tc_flow *flow, *tmp;
4523
4524 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4525 __mlx5e_tc_del_fdb_peer_flow(flow);
4526}
b4a23329
RD		 4527
4528void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4529{
4530 struct mlx5_rep_uplink_priv *rpriv =
4531 container_of(work, struct mlx5_rep_uplink_priv,
4532 reoffload_flows_work);
4533 struct mlx5e_tc_flow *flow, *tmp;
4534
ad86755b 4535 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4536 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4537 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4538 unready_flow_del(flow);
b4a23329 4539 }
ad86755b 4540 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4541}
e2394a61
VB		 4542
4543static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4544 struct flow_cls_offload *cls_flower,
4545 unsigned long flags)
4546{
4547 switch (cls_flower->command) {
4548 case FLOW_CLS_REPLACE:
4549 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4550 flags);
4551 case FLOW_CLS_DESTROY:
4552 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4553 flags);
4554 case FLOW_CLS_STATS:
4555 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4556 flags);
4557 default:
4558 return -EOPNOTSUPP;
4559 }
4560}
4561
4562int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4563 void *cb_priv)
4564{
ec9457a6 4565 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 4566 struct mlx5e_priv *priv = cb_priv;
4567
2ff349c5
RD		 4568 if (!priv->netdev || !netif_device_present(priv->netdev))
4569 return -EOPNOTSUPP;
4570
ec9457a6
RD		 4571 if (mlx5e_is_uplink_rep(priv))
4572 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
4573 else
4574 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
4575
e2394a61
VB		 4576 switch (type) {
4577 case TC_SETUP_CLSFLOWER:
4578 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
4579 default:
4580 return -EOPNOTSUPP;
4581 }
4582}
c7569097
AL		 4583
4584bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
4585 struct sk_buff *skb)
4586{
4587#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 4588 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 4589 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 4590 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 4591 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 4592 struct tc_skb_ext *tc_skb_ext;
4593 int err;
4594
4595 reg_b = be32_to_cpu(cqe->ft_metadata);
4596
4597 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4598
c9355682 4599 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 4600 if (err) {
4601 netdev_dbg(priv->netdev,
4602 "Couldn't find chain for chain tag: %d, err: %d\n",
4603 chain_tag, err);
4604 return false;
4605 }
4606
a91d98a0
CM		 4607 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
4608 chain = mapped_obj.chain;
9453d45e 4609 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 4610 if (WARN_ON(!tc_skb_ext))
4611 return false;
4612
4613 tc_skb_ext->chain = chain;
aedd133d 4614
ed2fe7ba 4615 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 4616 ESW_ZONE_ID_MASK;
aedd133d
AL		 4617
4618 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
4619 zone_restore_id))
4620 return false;
a91d98a0
CM		 4621 } else {
4622 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
4623 return false;
c7569097
AL		 4624 }
4625#endif /* CONFIG_NET_TC_SKB_EXT */
4626
4627 return true;
4628}
Linux 6.x block layer and io_uring tree(s)