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net/mlx5e: kTLS, Use CHECKSUM_UNNECESSARY for device-offloaded packets
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
f6dfb4c3 42#include <net/arp.h>
3616d08b 43#include <net/ipv6_stubs.h>
f828ca6a 44#include <net/bareudp.h>
d34eb2fc 45#include <net/bonding.h>
e8f887ac 46#include "en.h"
f0da4daa 47#include "en/tc/post_act.h"
1d447a39 48#include "en_rep.h"
768c3667 49#include "en/rep/tc.h"
e2394a61 50#include "en/rep/neigh.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
3f6d08d1 53#include "fs_core.h"
2c81bfd5 54#include "en/port.h"
101f4de9 55#include "en/tc_tun.h"
0a7fcb78 56#include "en/mapping.h"
4c3844d9 57#include "en/tc_ct.h"
b2fdf3d0 58#include "en/mod_hdr.h"
0d9f9647 59#include "en/tc_tun_encap.h"
0027d70c 60#include "en/tc/sample.h"
fad54790 61#include "en/tc/act/act.h"
04de7dda 62#include "lib/devcom.h"
9272e3df 63#include "lib/geneve.h"
ae430332 64#include "lib/fs_chains.h"
7a978759 65#include "diag/en_tc_tracepoint.h"
1fe3e316 66#include <asm/div64.h>
016c8946
JK		 67#include "lag/lag.h"
68#include "lag/mp.h"
e8f887ac 69
acff797c 70#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 71#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 72
8f1e0b97
PB		 73struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
74 [CHAIN_TO_REG] = {
75 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
76 .moffset = 0,
ed2fe7ba 77 .mlen = 16,
8f1e0b97 78 },
10742efc
VB		 79 [VPORT_TO_REG] = {
80 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 81 .moffset = 16,
82 .mlen = 16,
10742efc 83 },
0a7fcb78
PB		 84 [TUNNEL_TO_REG] = {
85 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 86 .moffset = 8,
87 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 88 .soffset = MLX5_BYTE_OFF(fte_match_param,
89 misc_parameters_2.metadata_reg_c_1),
90 },
4c3844d9 91 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 92 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 93 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
94 [MARK_TO_REG] = mark_to_reg_ct,
95 [LABELS_TO_REG] = labels_to_reg_ct,
96 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 97 /* For NIC rules we store the restore metadata directly
c7569097
AL		 98 * into reg_b that is passed to SW since we don't
99 * jump between steering domains.
100 */
101 [NIC_CHAIN_TO_REG] = {
102 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
103 .moffset = 0,
ed2fe7ba 104 .mlen = 16,
c7569097 105 },
aedd133d 106 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 107};
108
9ba33339
RD		 109/* To avoid false lock dependency warning set the tc_ht lock
110 * class different than the lock class of the ht being used when deleting
111 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
112 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
113 * it's different than the ht->mutex here.
114 */
115static struct lock_class_key tc_ht_lock_key;
116
0a7fcb78
PB		 117static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
118
119void
120mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
121 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 122 u32 val,
0a7fcb78
PB		 123 u32 mask)
124{
ed2fe7ba 125 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 126 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 127 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 128 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 129 u32 max_mask = GENMASK(match_len - 1, 0);
130 __be32 curr_mask_be, curr_val_be;
131 u32 curr_mask, curr_val;
0a7fcb78
PB		 132
133 fmask = headers_c + soffset;
134 fval = headers_v + soffset;
135
ed2fe7ba
PB		 136 memcpy(&curr_mask_be, fmask, 4);
137 memcpy(&curr_val_be, fval, 4);
138
139 curr_mask = be32_to_cpu(curr_mask_be);
140 curr_val = be32_to_cpu(curr_val_be);
141
142 //move to correct offset
143 WARN_ON(mask > max_mask);
144 mask <<= moffset;
145 val <<= moffset;
146 max_mask <<= moffset;
147
148 //zero val and mask
149 curr_mask &= ~max_mask;
150 curr_val &= ~max_mask;
0a7fcb78 151
ed2fe7ba
PB		 152 //add current to mask
153 curr_mask |= mask;
154 curr_val |= val;
155
156 //back to be32 and write
157 curr_mask_be = cpu_to_be32(curr_mask);
158 curr_val_be = cpu_to_be32(curr_val);
159
160 memcpy(fmask, &curr_mask_be, 4);
161 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 162
163 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
164}
165
7e36feeb
PB		 166void
167mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
168 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 169 u32 *val,
7e36feeb
PB		 170 u32 *mask)
171{
ed2fe7ba 172 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 173 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 174 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 175 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 176 u32 max_mask = GENMASK(match_len - 1, 0);
177 __be32 curr_mask_be, curr_val_be;
178 u32 curr_mask, curr_val;
7e36feeb
PB		 179
180 fmask = headers_c + soffset;
181 fval = headers_v + soffset;
182
ed2fe7ba
PB		 183 memcpy(&curr_mask_be, fmask, 4);
184 memcpy(&curr_val_be, fval, 4);
185
186 curr_mask = be32_to_cpu(curr_mask_be);
187 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 188
ed2fe7ba
PB		 189 *mask = (curr_mask >> moffset) & max_mask;
190 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 191}
192
0a7fcb78 193int
c7b9038d
VB		 194mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
195 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
196 enum mlx5_flow_namespace_type ns,
197 enum mlx5e_tc_attr_to_reg type,
198 u32 data)
0a7fcb78
PB		 199{
200 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
201 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
202 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
203 char *modact;
204 int err;
205
2c0e5cf5
PB		 206 modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
207 if (IS_ERR(modact))
208 return PTR_ERR(modact);
0a7fcb78
PB		 209
210 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 211 if (mlen == 32)
0a7fcb78
PB		 212 mlen = 0;
213
214 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
215 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 216 MLX5_SET(set_action_in, modact, offset, moffset);
217 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 218 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 219 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 220 mod_hdr_acts->num_actions++;
221
c7b9038d 222 return err;
0a7fcb78
PB		 223}
224
27484f71
AL		 225struct mlx5e_tc_int_port_priv *
226mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
227{
228 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
229 struct mlx5_rep_uplink_priv *uplink_priv;
230 struct mlx5e_rep_priv *uplink_rpriv;
231
232 if (is_mdev_switchdev_mode(priv->mdev)) {
233 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
234 uplink_priv = &uplink_rpriv->uplink_priv;
235
236 return uplink_priv->int_port_priv;
237 }
238
239 return NULL;
240}
241
aedd133d
AL		 242static struct mlx5_tc_ct_priv *
243get_ct_priv(struct mlx5e_priv *priv)
244{
245 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
246 struct mlx5_rep_uplink_priv *uplink_priv;
247 struct mlx5e_rep_priv *uplink_rpriv;
248
e8711402 249 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 250 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
251 uplink_priv = &uplink_rpriv->uplink_priv;
252
253 return uplink_priv->ct_priv;
254 }
255
256 return priv->fs.tc.ct;
257}
258
0027d70c 259static struct mlx5e_tc_psample *
f94d6389
CM		 260get_sample_priv(struct mlx5e_priv *priv)
261{
262 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
263 struct mlx5_rep_uplink_priv *uplink_priv;
264 struct mlx5e_rep_priv *uplink_rpriv;
265
266 if (is_mdev_switchdev_mode(priv->mdev)) {
267 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
268 uplink_priv = &uplink_rpriv->uplink_priv;
269
0027d70c 270 return uplink_priv->tc_psample;
f94d6389
CM		 271 }
272
273 return NULL;
274}
f94d6389 275
aedd133d
AL		 276struct mlx5_flow_handle *
277mlx5_tc_rule_insert(struct mlx5e_priv *priv,
278 struct mlx5_flow_spec *spec,
279 struct mlx5_flow_attr *attr)
280{
281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
282
e8711402 283 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 284 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
285
286 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
287}
288
289void
290mlx5_tc_rule_delete(struct mlx5e_priv *priv,
291 struct mlx5_flow_handle *rule,
292 struct mlx5_flow_attr *attr)
293{
294 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
295
e8711402 296 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 297 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
298
299 return;
300 }
301
302 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
303}
304
c7b9038d
VB		 305int
306mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
307 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
308 enum mlx5_flow_namespace_type ns,
309 enum mlx5e_tc_attr_to_reg type,
310 u32 data)
311{
312 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
313
314 return ret < 0 ? ret : 0;
315}
316
317void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
318 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
319 enum mlx5e_tc_attr_to_reg type,
320 int act_id, u32 data)
321{
322 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
323 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
324 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
325 char *modact;
326
2c0e5cf5 327 modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
c7b9038d
VB		 328
329 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 330 if (mlen == 32)
c7b9038d
VB		 331 mlen = 0;
332
333 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
334 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 335 MLX5_SET(set_action_in, modact, offset, moffset);
336 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 337 MLX5_SET(set_action_in, modact, data, data);
338}
339
77ab67b7
OG		 340struct mlx5e_hairpin {
341 struct mlx5_hairpin *pair;
342
343 struct mlx5_core_dev *func_mdev;
3f6d08d1 344 struct mlx5e_priv *func_priv;
77ab67b7 345 u32 tdn;
a6696735 346 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 347
348 int num_channels;
349 struct mlx5e_rqt indir_rqt;
a6696735 350 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 351 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 352};
353
5c65c564
OG		 354struct mlx5e_hairpin_entry {
355 /* a node of a hash table which keeps all the hairpin entries */
356 struct hlist_node hairpin_hlist;
357
73edca73
VB		 358 /* protects flows list */
359 spinlock_t flows_lock;
5c65c564
OG		 360 /* flows sharing the same hairpin */
361 struct list_head flows;
db76ca24
VB		 362 /* hpe's that were not fully initialized when dead peer update event
363 * function traversed them.
364 */
365 struct list_head dead_peer_wait_list;
5c65c564 366
d8822868 367 u16 peer_vhca_id;
106be53b 368 u8 prio;
5c65c564 369 struct mlx5e_hairpin *hp;
e4f9abbd 370 refcount_t refcnt;
db76ca24 371 struct completion res_ready;
5c65c564
OG		 372};
373
5a7e5bcb
VB		 374static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
375 struct mlx5e_tc_flow *flow);
376
0d9f9647 377struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 378{
379 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
380 return ERR_PTR(-EINVAL);
381 return flow;
382}
383
0d9f9647 384void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 385{
386 if (refcount_dec_and_test(&flow->refcnt)) {
387 mlx5e_tc_del_flow(priv, flow);
c5d326b2 388 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 389 }
390}
391
aedd133d 392bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 393{
394 return flow_flag_test(flow, ESWITCH);
395}
396
67d62ee7 397bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
84179981
PB		 398{
399 return flow_flag_test(flow, FT);
400}
401
0d9f9647 402bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 403{
404 return flow_flag_test(flow, OFFLOADED);
405}
406
e36db1ee 407int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
11c9c548 408{
b2fdf3d0
PB		 409 return mlx5e_is_eswitch_flow(flow) ?
410 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 411}
412
dd58edc3 413static struct mod_hdr_tbl *
b2fdf3d0 414get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 415{
416 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
417
e36db1ee 418 return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
b2fdf3d0 419 &esw->offloads.mod_hdr :
dd58edc3
VB		 420 &priv->fs.tc.mod_hdr;
421}
422
11c9c548
OG		 423static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
424 struct mlx5e_tc_flow *flow,
425 struct mlx5e_tc_flow_parse_attr *parse_attr)
426{
b2fdf3d0
PB		 427 struct mlx5_modify_hdr *modify_hdr;
428 struct mlx5e_mod_hdr_handle *mh;
11c9c548 429
b2fdf3d0 430 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
e36db1ee 431 mlx5e_get_flow_namespace(flow),
b2fdf3d0
PB		 432 &parse_attr->mod_hdr_acts);
433 if (IS_ERR(mh))
434 return PTR_ERR(mh);
11c9c548 435
b2fdf3d0 436 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 437 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 438 flow->mh = mh;
11c9c548
OG		 439
440 return 0;
11c9c548
OG		 441}
442
443static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
444 struct mlx5e_tc_flow *flow)
445{
5a7e5bcb 446 /* flow wasn't fully initialized */
dd58edc3 447 if (!flow->mh)
5a7e5bcb
VB		 448 return;
449
b2fdf3d0
PB		 450 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
451 flow->mh);
dd58edc3 452 flow->mh = NULL;
11c9c548
OG		 453}
454
77ab67b7
OG		 455static
456struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
457{
b1c2f631 458 struct mlx5_core_dev *mdev;
77ab67b7
OG		 459 struct net_device *netdev;
460 struct mlx5e_priv *priv;
461
b1c2f631
DC		 462 netdev = dev_get_by_index(net, ifindex);
463 if (!netdev)
464 return ERR_PTR(-ENODEV);
465
77ab67b7 466 priv = netdev_priv(netdev);
b1c2f631
DC		 467 mdev = priv->mdev;
468 dev_put(netdev);
469
470 /* Mirred tc action holds a refcount on the ifindex net_device (see
471 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
472 * after dev_put(netdev), while we're in the context of adding a tc flow.
473 *
474 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
475 * stored in a hairpin object, which exists until all flows, that refer to it, get
476 * removed.
477 *
478 * On the other hand, after a hairpin object has been created, the peer net_device may
479 * be removed/unbound while there are still some hairpin flows that are using it. This
480 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
481 * NETDEV_UNREGISTER event of the peer net_device.
482 */
483 return mdev;
77ab67b7
OG		 484}
485
486static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
487{
a6696735 488 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 489 int err;
490
a6696735
MM		 491 builder = mlx5e_tir_builder_alloc(false);
492 if (!builder)
493 return -ENOMEM;
494
77ab67b7
OG		 495 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
496 if (err)
a6696735 497 goto out;
77ab67b7 498
a6696735
MM		 499 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
500 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 501 if (err)
502 goto create_tir_err;
503
a6696735
MM		 504out:
505 mlx5e_tir_builder_free(builder);
506 return err;
77ab67b7
OG		 507
508create_tir_err:
509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 510
511 goto out;
77ab67b7
OG		 512}
513
514static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
515{
a6696735 516 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 517 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
518}
519
3f6d08d1
OG		 520static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
521{
3f6d08d1
OG		 522 struct mlx5e_priv *priv = hp->func_priv;
523 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 524 struct mlx5e_rss_params_indir *indir;
525 int err;
3f6d08d1 526
06e9f13a
MM		 527 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
528 if (!indir)
3f6d08d1
OG		 529 return -ENOMEM;
530
43befe99 531 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 532 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 533 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
534 indir);
3f6d08d1 535
06e9f13a 536 kvfree(indir);
3f6d08d1
OG		 537 return err;
538}
539
540static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
541{
542 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 543 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 544 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 545 struct mlx5e_tir_builder *builder;
546 int err = 0;
547
548 builder = mlx5e_tir_builder_alloc(false);
549 if (!builder)
550 return -ENOMEM;
551
43ec0f41 552 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 553
554 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 555 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 556
65d6b6e5 557 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 558
a6696735
MM		 559 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
560 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
561 false);
43ec0f41 562 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 563
a6696735 564 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 565 if (err) {
566 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
567 goto err_destroy_tirs;
568 }
a6696735
MM		 569
570 mlx5e_tir_builder_clear(builder);
3f6d08d1 571 }
3f6d08d1 572
a6696735
MM		 573out:
574 mlx5e_tir_builder_free(builder);
3f6d08d1 575 return err;
a6696735
MM		 576
577err_destroy_tirs:
578 max_tt = tt;
579 for (tt = 0; tt < max_tt; tt++)
580 mlx5e_tir_destroy(&hp->indir_tir[tt]);
581
582 goto out;
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
586{
587 int tt;
588
589 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 590 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 591}
592
593static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
594 struct ttc_params *ttc_params)
595{
596 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
597 int tt;
598
599 memset(ttc_params, 0, sizeof(*ttc_params));
600
bc29764e
MG		 601 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
602 MLX5_FLOW_NAMESPACE_KERNEL);
603 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
604 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
605 ttc_params->dests[tt].tir_num =
606 tt == MLX5_TT_ANY ?
607 mlx5e_tir_get_tirn(&hp->direct_tir) :
608 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
609 }
3f6d08d1 610
3f6d08d1
OG		 611 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
612 ft_attr->prio = MLX5E_TC_PRIO;
613}
614
615static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
616{
617 struct mlx5e_priv *priv = hp->func_priv;
618 struct ttc_params ttc_params;
619 int err;
620
621 err = mlx5e_hairpin_create_indirect_rqt(hp);
622 if (err)
623 return err;
624
625 err = mlx5e_hairpin_create_indirect_tirs(hp);
626 if (err)
627 goto err_create_indirect_tirs;
628
629 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 630 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
631 if (IS_ERR(hp->ttc)) {
632 err = PTR_ERR(hp->ttc);
3f6d08d1 633 goto err_create_ttc_table;
f4b45940 634 }
3f6d08d1
OG		 635
636 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 637 hp->num_channels,
638 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 639
640 return 0;
641
642err_create_ttc_table:
643 mlx5e_hairpin_destroy_indirect_tirs(hp);
644err_create_indirect_tirs:
06e9f13a 645 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 646
647 return err;
648}
649
650static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
651{
f4b45940 652 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 653 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 654 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 655}
656
77ab67b7
OG		 657static struct mlx5e_hairpin *
658mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
659 int peer_ifindex)
660{
661 struct mlx5_core_dev *func_mdev, *peer_mdev;
662 struct mlx5e_hairpin *hp;
663 struct mlx5_hairpin *pair;
664 int err;
665
666 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
667 if (!hp)
668 return ERR_PTR(-ENOMEM);
669
670 func_mdev = priv->mdev;
671 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 672 if (IS_ERR(peer_mdev)) {
673 err = PTR_ERR(peer_mdev);
674 goto create_pair_err;
675 }
77ab67b7
OG		 676
677 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
678 if (IS_ERR(pair)) {
679 err = PTR_ERR(pair);
680 goto create_pair_err;
681 }
682 hp->pair = pair;
683 hp->func_mdev = func_mdev;
3f6d08d1
OG		 684 hp->func_priv = priv;
685 hp->num_channels = params->num_channels;
77ab67b7
OG		 686
687 err = mlx5e_hairpin_create_transport(hp);
688 if (err)
689 goto create_transport_err;
690
3f6d08d1
OG		 691 if (hp->num_channels > 1) {
692 err = mlx5e_hairpin_rss_init(hp);
693 if (err)
694 goto rss_init_err;
695 }
696
77ab67b7
OG		 697 return hp;
698
3f6d08d1
OG		 699rss_init_err:
700 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 701create_transport_err:
702 mlx5_core_hairpin_destroy(hp->pair);
703create_pair_err:
704 kfree(hp);
705 return ERR_PTR(err);
706}
707
708static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
709{
3f6d08d1
OG		 710 if (hp->num_channels > 1)
711 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 712 mlx5e_hairpin_destroy_transport(hp);
713 mlx5_core_hairpin_destroy(hp->pair);
714 kvfree(hp);
715}
716
106be53b
OG		 717static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
718{
719 return (peer_vhca_id << 16 | prio);
720}
721
5c65c564 722static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 723 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 724{
725 struct mlx5e_hairpin_entry *hpe;
106be53b 726 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 727
728 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 729 hairpin_hlist, hash_key) {
e4f9abbd
VB		 730 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
731 refcount_inc(&hpe->refcnt);
5c65c564 732 return hpe;
e4f9abbd 733 }
5c65c564
OG		 734 }
735
736 return NULL;
737}
738
e4f9abbd
VB		 739static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
740 struct mlx5e_hairpin_entry *hpe)
741{
742 /* no more hairpin flows for us, release the hairpin pair */
b32accda 743 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 744 return;
b32accda
VB		 745 hash_del(&hpe->hairpin_hlist);
746 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 747
db76ca24
VB		 748 if (!IS_ERR_OR_NULL(hpe->hp)) {
749 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
750 dev_name(hpe->hp->pair->peer_mdev->device));
751
752 mlx5e_hairpin_destroy(hpe->hp);
753 }
e4f9abbd
VB		 754
755 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 756 kfree(hpe);
757}
758
106be53b
OG		 759#define UNKNOWN_MATCH_PRIO 8
760
761static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 762 struct mlx5_flow_spec *spec, u8 *match_prio,
763 struct netlink_ext_ack *extack)
106be53b
OG		 764{
765 void *headers_c, *headers_v;
766 u8 prio_val, prio_mask = 0;
767 bool vlan_present;
768
769#ifdef CONFIG_MLX5_CORE_EN_DCB
770 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 771 NL_SET_ERR_MSG_MOD(extack,
772 "only PCP trust state supported for hairpin");
106be53b
OG		 773 return -EOPNOTSUPP;
774 }
775#endif
776 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
777 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
778
779 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
780 if (vlan_present) {
781 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
782 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
783 }
784
785 if (!vlan_present || !prio_mask) {
786 prio_val = UNKNOWN_MATCH_PRIO;
787 } else if (prio_mask != 0x7) {
e98bedf5
EB		 788 NL_SET_ERR_MSG_MOD(extack,
789 "masked priority match not supported for hairpin");
106be53b
OG		 790 return -EOPNOTSUPP;
791 }
792
793 *match_prio = prio_val;
794 return 0;
795}
796
5c65c564
OG		 797static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
798 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 799 struct mlx5e_tc_flow_parse_attr *parse_attr,
800 struct netlink_ext_ack *extack)
5c65c564 801{
98b66cb1 802 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 803 struct mlx5_hairpin_params params;
d8822868 804 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 805 struct mlx5e_hairpin_entry *hpe;
806 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 807 u64 link_speed64;
808 u32 link_speed;
106be53b 809 u8 match_prio;
d8822868 810 u16 peer_id;
5c65c564
OG		 811 int err;
812
d8822868 813 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 814 if (IS_ERR(peer_mdev)) {
815 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
816 return PTR_ERR(peer_mdev);
817 }
818
d8822868 819 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 820 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 821 return -EOPNOTSUPP;
822 }
823
d8822868 824 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 825 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
826 extack);
106be53b
OG		 827 if (err)
828 return err;
b32accda
VB		 829
830 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 831 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 832 if (hpe) {
833 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
834 wait_for_completion(&hpe->res_ready);
835
836 if (IS_ERR(hpe->hp)) {
837 err = -EREMOTEIO;
838 goto out_err;
839 }
5c65c564 840 goto attach_flow;
db76ca24 841 }
5c65c564
OG		 842
843 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 844 if (!hpe) {
db76ca24
VB		 845 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
846 return -ENOMEM;
b32accda 847 }
5c65c564 848
73edca73 849 spin_lock_init(&hpe->flows_lock);
5c65c564 850 INIT_LIST_HEAD(&hpe->flows);
db76ca24 851 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 852 hpe->peer_vhca_id = peer_id;
106be53b 853 hpe->prio = match_prio;
e4f9abbd 854 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 855 init_completion(&hpe->res_ready);
856
857 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
858 hash_hairpin_info(peer_id, match_prio));
859 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 860
6cdc686a 861 params.log_data_size = 16;
5c65c564
OG		 862 params.log_data_size = min_t(u8, params.log_data_size,
863 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
864 params.log_data_size = max_t(u8, params.log_data_size,
865 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 866
eb9180f7
OG		 867 params.log_num_packets = params.log_data_size -
868 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
869 params.log_num_packets = min_t(u8, params.log_num_packets,
870 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
871
872 params.q_counter = priv->q_counter;
3f6d08d1 873 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 874 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 875 link_speed = max_t(u32, link_speed, 50000);
876 link_speed64 = link_speed;
877 do_div(link_speed64, 50000);
878 params.num_channels = link_speed64;
879
5c65c564 880 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 881 hpe->hp = hp;
882 complete_all(&hpe->res_ready);
5c65c564
OG		 883 if (IS_ERR(hp)) {
884 err = PTR_ERR(hp);
db76ca24 885 goto out_err;
5c65c564
OG		 886 }
887
eb9180f7 888 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 889 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 890 dev_name(hp->pair->peer_mdev->device),
eb9180f7 891 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 892
5c65c564 893attach_flow:
3f6d08d1 894 if (hpe->hp->num_channels > 1) {
226f2ca3 895 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 896 flow->attr->nic_attr->hairpin_ft =
897 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 898 } else {
a6696735 899 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 900 }
b32accda 901
e4f9abbd 902 flow->hpe = hpe;
73edca73 903 spin_lock(&hpe->flows_lock);
5c65c564 904 list_add(&flow->hairpin, &hpe->flows);
73edca73 905 spin_unlock(&hpe->flows_lock);
3f6d08d1 906
5c65c564
OG		 907 return 0;
908
db76ca24
VB		 909out_err:
910 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 911 return err;
912}
913
914static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
915 struct mlx5e_tc_flow *flow)
916{
5a7e5bcb 917 /* flow wasn't fully initialized */
e4f9abbd 918 if (!flow->hpe)
5a7e5bcb
VB		 919 return;
920
73edca73 921 spin_lock(&flow->hpe->flows_lock);
5c65c564 922 list_del(&flow->hairpin);
73edca73
VB		 923 spin_unlock(&flow->hpe->flows_lock);
924
e4f9abbd
VB		 925 mlx5e_hairpin_put(priv, flow->hpe);
926 flow->hpe = NULL;
5c65c564
OG		 927}
928
08247066
AL		 929struct mlx5_flow_handle *
930mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
931 struct mlx5_flow_spec *spec,
c620b772 932 struct mlx5_flow_attr *attr)
e8f887ac 933{
08247066 934 struct mlx5_flow_context *flow_context = &spec->flow_context;
67d62ee7 935 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c620b772 936 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 937 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 938 struct mlx5_flow_destination dest[2] = {};
66958ed9 939 struct mlx5_flow_act flow_act = {
3bc4b7bf 940 .action = attr->action,
bb0ee7dc 941 .flags = FLOW_ACT_NO_APPEND,
66958ed9 942 };
08247066 943 struct mlx5_flow_handle *rule;
c7569097 944 struct mlx5_flow_table *ft;
08247066 945 int dest_ix = 0;
e8f887ac 946
bb0ee7dc 947 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 948 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 949
aedd133d
AL		 950 if (attr->dest_ft) {
951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
952 dest[dest_ix].ft = attr->dest_ft;
953 dest_ix++;
954 } else if (nic_attr->hairpin_ft) {
08247066 955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 956 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 957 dest_ix++;
c620b772 958 } else if (nic_attr->hairpin_tirn) {
08247066 959 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 960 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 961 dest_ix++;
3f6d08d1
OG		 962 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
963 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 964 if (attr->dest_chain) {
965 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
966 attr->dest_chain, 1,
967 MLX5E_TC_FT_LEVEL);
968 if (IS_ERR(dest[dest_ix].ft))
969 return ERR_CAST(dest[dest_ix].ft);
970 } else {
6783f0a2 971 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 972 }
3f6d08d1 973 dest_ix++;
5c65c564 974 }
aad7e08d 975
c7569097
AL		 976 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
977 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
978 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
979
08247066 980 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 981 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 982 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 983 dest_ix++;
aad7e08d
AV		 984 }
985
08247066 986 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 987 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 988
6a064674
AL		 989 mutex_lock(&tc->t_lock);
990 if (IS_ERR_OR_NULL(tc->t)) {
991 /* Create the root table here if doesn't exist yet */
992 tc->t =
c7569097 993 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 994
995 if (IS_ERR(tc->t)) {
996 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 997 netdev_err(priv->netdev,
998 "Failed to create tc offload table\n");
c7569097
AL		 999 rule = ERR_CAST(priv->fs.tc.t);
1000 goto err_ft_get;
e8f887ac 1001 }
e8f887ac 1002 }
08247066 1003 mutex_unlock(&tc->t_lock);
e8f887ac 1004
aedd133d
AL		 1005 if (attr->chain || attr->prio)
1006 ft = mlx5_chains_get_table(nic_chains,
1007 attr->chain, attr->prio,
1008 MLX5E_TC_FT_LEVEL);
1009 else
1010 ft = attr->ft;
1011
c7569097
AL		 1012 if (IS_ERR(ft)) {
1013 rule = ERR_CAST(ft);
1014 goto err_ft_get;
1015 }
1016
c620b772 1017 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1018 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1019
c7569097 1020 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1021 &flow_act, dest, dest_ix);
1022 if (IS_ERR(rule))
c7569097 1023 goto err_rule;
08247066
AL		 1024
1025 return rule;
c7569097
AL		 1026
1027err_rule:
aedd133d
AL		 1028 if (attr->chain || attr->prio)
1029 mlx5_chains_put_table(nic_chains,
1030 attr->chain, attr->prio,
1031 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1032err_ft_get:
1033 if (attr->dest_chain)
1034 mlx5_chains_put_table(nic_chains,
1035 attr->dest_chain, 1,
1036 MLX5E_TC_FT_LEVEL);
1037
1038 return ERR_CAST(rule);
08247066
AL		 1039}
1040
1041static int
1042mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1043 struct mlx5e_tc_flow *flow,
1044 struct netlink_ext_ack *extack)
1045{
c6cfe113 1046 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1047 struct mlx5_flow_attr *attr = flow->attr;
08247066 1048 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1049 struct mlx5_fc *counter;
08247066
AL		 1050 int err;
1051
c6cfe113
RD		 1052 parse_attr = attr->parse_attr;
1053
08247066
AL		 1054 if (flow_flag_test(flow, HAIRPIN)) {
1055 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1056 if (err)
1057 return err;
1058 }
1059
1060 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1061 counter = mlx5_fc_create(dev, true);
1062 if (IS_ERR(counter))
1063 return PTR_ERR(counter);
1064
1065 attr->counter = counter;
1066 }
1067
1068 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1069 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2c0e5cf5 1070 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
08247066
AL		 1071 if (err)
1072 return err;
1073 }
1074
aedd133d
AL		 1075 if (flow_flag_test(flow, CT))
1076 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1077 attr, &parse_attr->mod_hdr_acts);
1078 else
1079 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1080 attr);
aad7e08d 1081
a2b7189b 1082 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1083}
1084
08247066 1085void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1086 struct mlx5_flow_handle *rule,
1087 struct mlx5_flow_attr *attr)
08247066 1088{
67d62ee7 1089 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c7569097 1090
08247066 1091 mlx5_del_flow_rules(rule);
c7569097 1092
aedd133d
AL		 1093 if (attr->chain || attr->prio)
1094 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1095 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1096
1097 if (attr->dest_chain)
1098 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1099 MLX5E_TC_FT_LEVEL);
08247066
AL		 1100}
1101
d85cdccb
OG		 1102static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1103 struct mlx5e_tc_flow *flow)
1104{
c620b772 1105 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1106 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1107
c7569097
AL		 1108 flow_flag_clear(flow, OFFLOADED);
1109
aedd133d
AL		 1110 if (flow_flag_test(flow, CT))
1111 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1112 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1113 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1114
c7569097
AL		 1115 /* Remove root table if no rules are left to avoid
1116 * extra steering hops.
1117 */
b6fac0b4 1118 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1119 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1120 !IS_ERR_OR_NULL(tc->t)) {
67d62ee7 1121 mlx5_chains_put_table(mlx5e_nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1122 priv->fs.tc.t = NULL;
1123 }
b6fac0b4 1124 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1125
513f8f7f 1126 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1127 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1128
972fe492
RD		 1129 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1130 mlx5_fc_destroy(priv->mdev, attr->counter);
aedd133d 1131
226f2ca3 1132 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1133 mlx5e_hairpin_flow_del(priv, flow);
c620b772 1134
88d97486 1135 kvfree(attr->parse_attr);
c620b772 1136 kfree(flow->attr);
d85cdccb
OG		 1137}
1138
0d9f9647 1139struct mlx5_flow_handle *
6d2a3ed0
OG		 1140mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1141 struct mlx5e_tc_flow *flow,
1142 struct mlx5_flow_spec *spec,
c620b772 1143 struct mlx5_flow_attr *attr)
6d2a3ed0 1144{
1ef3018f 1145 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1146 struct mlx5_flow_handle *rule;
4c3844d9 1147
89e39467
PB		 1148 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1149 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1150
1ef3018f
PB		 1151 if (flow_flag_test(flow, CT)) {
1152 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1153
69e2916e 1154 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1155 flow, spec, attr,
1ef3018f 1156 mod_hdr_acts);
f94d6389 1157 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1158 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1159 mlx5e_tc_get_flow_tun_id(flow));
69e2916e
PB		 1160 } else {
1161 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1162 }
6d2a3ed0 1163
6d2a3ed0
OG		 1164 if (IS_ERR(rule))
1165 return rule;
1166
c620b772 1167 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1168 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1169 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1170 if (flow_flag_test(flow, CT))
1171 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1172 else
1173 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1174 return flow->rule[1];
1175 }
1176 }
1177
6d2a3ed0
OG		 1178 return rule;
1179}
1180
0d9f9647
VB		 1181void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1182 struct mlx5e_tc_flow *flow,
1183 struct mlx5_flow_attr *attr)
6d2a3ed0 1184{
226f2ca3 1185 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1186
89e39467
PB		 1187 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1188 goto offload_rule_0;
1189
c620b772 1190 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1191 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1192
2820110d
CM		 1193 if (flow_flag_test(flow, CT))
1194 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1195 else if (flow_flag_test(flow, SAMPLE))
1196 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
1197 else
89e39467 1198offload_rule_0:
2820110d 1199 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
6d2a3ed0
OG		 1200}
1201
0d9f9647 1202struct mlx5_flow_handle *
5dbe906f
PB		 1203mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1204 struct mlx5e_tc_flow *flow,
178f69b4 1205 struct mlx5_flow_spec *spec)
5dbe906f 1206{
c620b772 1207 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1208 struct mlx5_flow_handle *rule;
1209
c620b772
AL		 1210 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1211 if (!slow_attr)
1212 return ERR_PTR(-ENOMEM);
5dbe906f 1213
c620b772
AL		 1214 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1215 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1216 slow_attr->esw_attr->split_count = 0;
1217 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1218
1219 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1220 if (!IS_ERR(rule))
226f2ca3 1221 flow_flag_set(flow, SLOW);
5dbe906f 1222
c620b772
AL		 1223 kfree(slow_attr);
1224
5dbe906f
PB		 1225 return rule;
1226}
1227
0d9f9647
VB		 1228void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1229 struct mlx5e_tc_flow *flow)
5dbe906f 1230{
c620b772 1231 struct mlx5_flow_attr *slow_attr;
178f69b4 1232
c620b772 1233 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1234 if (!slow_attr) {
1235 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1236 return;
1237 }
c620b772
AL		 1238
1239 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1240 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1241 slow_attr->esw_attr->split_count = 0;
1242 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1243 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1244 flow_flag_clear(flow, SLOW);
c620b772 1245 kfree(slow_attr);
5dbe906f
PB		 1246}
1247
ad86755b
VB		 1248/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1249 * function.
1250 */
1251static void unready_flow_add(struct mlx5e_tc_flow *flow,
1252 struct list_head *unready_flows)
1253{
1254 flow_flag_set(flow, NOT_READY);
1255 list_add_tail(&flow->unready, unready_flows);
1256}
1257
1258/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1259 * function.
1260 */
1261static void unready_flow_del(struct mlx5e_tc_flow *flow)
1262{
1263 list_del(&flow->unready);
1264 flow_flag_clear(flow, NOT_READY);
1265}
1266
b4a23329
RD		 1267static void add_unready_flow(struct mlx5e_tc_flow *flow)
1268{
1269 struct mlx5_rep_uplink_priv *uplink_priv;
1270 struct mlx5e_rep_priv *rpriv;
1271 struct mlx5_eswitch *esw;
1272
1273 esw = flow->priv->mdev->priv.eswitch;
1274 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1275 uplink_priv = &rpriv->uplink_priv;
1276
ad86755b
VB		 1277 mutex_lock(&uplink_priv->unready_flows_lock);
1278 unready_flow_add(flow, &uplink_priv->unready_flows);
1279 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1280}
1281
1282static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1283{
ad86755b
VB		 1284 struct mlx5_rep_uplink_priv *uplink_priv;
1285 struct mlx5e_rep_priv *rpriv;
1286 struct mlx5_eswitch *esw;
1287
1288 esw = flow->priv->mdev->priv.eswitch;
1289 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1290 uplink_priv = &rpriv->uplink_priv;
1291
1292 mutex_lock(&uplink_priv->unready_flows_lock);
1293 unready_flow_del(flow);
1294 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1295}
1296
a508728a 1297bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1298{
1299 struct mlx5_core_dev *out_mdev, *route_mdev;
1300 struct mlx5e_priv *out_priv, *route_priv;
1301
1302 out_priv = netdev_priv(out_dev);
1303 out_mdev = out_priv->mdev;
1304 route_priv = netdev_priv(route_dev);
1305 route_mdev = route_priv->mdev;
1306
1307 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1308 route_mdev->coredev_type != MLX5_COREDEV_VF)
1309 return false;
1310
ab3f3d5e 1311 return mlx5e_same_hw_devs(out_priv, route_priv);
10742efc
VB		 1312}
1313
a508728a 1314int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1315{
1316 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1317 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1318 struct mlx5_core_dev *route_mdev;
1319 struct mlx5_eswitch *esw;
1320 u16 vhca_id;
1321 int err;
1322
1323 out_priv = netdev_priv(out_dev);
1324 esw = out_priv->mdev->priv.eswitch;
1325 route_priv = netdev_priv(route_dev);
1326 route_mdev = route_priv->mdev;
1327
1328 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1329 if (mlx5_lag_is_active(out_priv->mdev)) {
1330 /* In lag case we may get devices from different eswitch instances.
1331 * If we failed to get vport num, it means, mostly, that we on the wrong
1332 * eswitch.
1333 */
1334 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1335 if (err != -ENOENT)
1336 return err;
1337
1338 devcom = out_priv->mdev->priv.devcom;
1339 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1340 if (!esw)
1341 return -ENODEV;
1342 }
1343
10742efc 1344 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1345 if (devcom)
1346 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1347 return err;
1348}
1349
c7b9038d
VB		 1350int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1351 struct mlx5e_tc_flow_parse_attr *parse_attr,
1352 struct mlx5e_tc_flow *flow)
1353{
1354 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1355 struct mlx5_modify_hdr *mod_hdr;
1356
1357 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
e36db1ee 1358 mlx5e_get_flow_namespace(flow),
c7b9038d
VB		 1359 mod_hdr_acts->num_actions,
1360 mod_hdr_acts->actions);
1361 if (IS_ERR(mod_hdr))
1362 return PTR_ERR(mod_hdr);
1363
1364 WARN_ON(flow->attr->modify_hdr);
1365 flow->attr->modify_hdr = mod_hdr;
1366
1367 return 0;
1368}
1369
c83954ab 1370static int
74491de9 1371mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1372 struct mlx5e_tc_flow *flow,
1373 struct netlink_ext_ack *extack)
adb4c123
OG		 1374{
1375 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1376 struct mlx5e_tc_flow_parse_attr *parse_attr;
1377 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1378 bool vf_tun = false, encap_valid = true;
fe7738eb 1379 struct net_device *encap_dev = NULL;
c620b772 1380 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1381 struct mlx5e_rep_priv *rpriv;
1382 struct mlx5e_priv *out_priv;
97a8d29a 1383 struct mlx5_fc *counter;
39ac237c 1384 u32 max_prio, max_chain;
0ad060ee 1385 int err = 0;
f493f155 1386 int out_index;
8b32580d 1387
b16eb3c8
AL		 1388 parse_attr = attr->parse_attr;
1389 esw_attr = attr->esw_attr;
1390
84179981
PB		 1391 /* We check chain range only for tc flows.
1392 * For ft flows, we checked attr->chain was originally 0 and set it to
1393 * FDB_FT_CHAIN which is outside tc range.
1394 * See mlx5e_rep_setup_ft_cb().
1395 */
ae430332 1396 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1397 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1398 NL_SET_ERR_MSG_MOD(extack,
1399 "Requested chain is out of supported range");
8914add2
VB		 1400 err = -EOPNOTSUPP;
1401 goto err_out;
bf07aa73
PB		 1402 }
1403
ae430332 1404 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1405 if (attr->prio > max_prio) {
61644c3d
RD		 1406 NL_SET_ERR_MSG_MOD(extack,
1407 "Requested priority is out of supported range");
8914add2
VB		 1408 err = -EOPNOTSUPP;
1409 goto err_out;
bf07aa73 1410 }
e52c2802 1411
777bb800
VB		 1412 if (flow_flag_test(flow, TUN_RX)) {
1413 err = mlx5e_attach_decap_route(priv, flow);
1414 if (err)
8914add2 1415 goto err_out;
b16eb3c8 1416
5b209d1a
RD		 1417 if (!attr->chain && esw_attr->int_port &&
1418 attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
b16eb3c8
AL		 1419 /* If decap route device is internal port, change the
1420 * source vport value in reg_c0 back to uplink just in
1421 * case the rule performs goto chain > 0. If we have a miss
1422 * on chain > 0 we want the metadata regs to hold the
1423 * chain id so SW will resume handling of this packet
1424 * from the proper chain.
1425 */
1426 u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1427 esw_attr->in_rep->vport);
1428
1429 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1430 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1431 metadata);
1432 if (err)
31108d14 1433 goto err_out;
077cdda7
RD		 1434
1435 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
b16eb3c8 1436 }
777bb800
VB		 1437 }
1438
14e6b038
EC		 1439 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1440 err = mlx5e_attach_decap(priv, flow, extack);
1441 if (err)
8914add2 1442 goto err_out;
14e6b038
EC		 1443 }
1444
166f431e
AL		 1445 if (netif_is_ovs_master(parse_attr->filter_dev)) {
1446 struct mlx5e_tc_int_port *int_port;
1447
1448 if (attr->chain) {
1449 NL_SET_ERR_MSG_MOD(extack,
1450 "Internal port rule is only supported on chain 0");
31108d14
CJ		 1451 err = -EOPNOTSUPP;
1452 goto err_out;
166f431e
AL		 1453 }
1454
1455 if (attr->dest_chain) {
1456 NL_SET_ERR_MSG_MOD(extack,
1457 "Internal port rule offload doesn't support goto action");
31108d14
CJ		 1458 err = -EOPNOTSUPP;
1459 goto err_out;
166f431e
AL		 1460 }
1461
1462 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1463 parse_attr->filter_dev->ifindex,
1464 flow_flag_test(flow, EGRESS) ?
1465 MLX5E_TC_INT_PORT_EGRESS :
1466 MLX5E_TC_INT_PORT_INGRESS);
31108d14
CJ		 1467 if (IS_ERR(int_port)) {
1468 err = PTR_ERR(int_port);
1469 goto err_out;
1470 }
166f431e
AL		 1471
1472 esw_attr->int_port = int_port;
1473 }
1474
f493f155 1475 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1476 struct net_device *out_dev;
8c4dc42b
EB		 1477 int mirred_ifindex;
1478
c620b772 1479 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1480 continue;
1481
7040632d 1482 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1483 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1484 if (!out_dev) {
1485 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1486 err = -ENODEV;
1487 goto err_out;
1488 }
733d4f36 1489 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1490 extack, &encap_dev, &encap_valid);
fe7738eb 1491 dev_put(out_dev);
0ad060ee 1492 if (err)
8914add2 1493 goto err_out;
0ad060ee 1494
8914add2 1495 if (esw_attr->dests[out_index].flags &
100ad4e2
AL		 1496 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1497 !esw_attr->dest_int_port)
8914add2 1498 vf_tun = true;
3c37745e
OG		 1499 out_priv = netdev_priv(encap_dev);
1500 rpriv = out_priv->ppriv;
c620b772
AL		 1501 esw_attr->dests[out_index].rep = rpriv->rep;
1502 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1503 }
1504
7d1a3d08
VB		 1505 if (vf_tun && esw_attr->out_count > 1) {
1506 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1507 err = -EOPNOTSUPP;
1508 goto err_out;
1509 }
1510
8b32580d 1511 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1512 if (err)
8914add2 1513 goto err_out;
adb4c123 1514
d5a3c2b6
RD		 1515 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1516 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1517 if (vf_tun) {
1518 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1519 if (err)
1520 goto err_out;
1521 } else {
1522 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1523 if (err)
1524 goto err_out;
1525 }
d7e75a32
OG		 1526 }
1527
b8aee822 1528 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1529 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1530 if (IS_ERR(counter)) {
1531 err = PTR_ERR(counter);
1532 goto err_out;
1533 }
b8aee822
MB		 1534
1535 attr->counter = counter;
1536 }
1537
0ad060ee
RD		 1538 /* we get here if one of the following takes place:
1539 * (1) there's no error
1540 * (2) there's an encap action and we don't have valid neigh
3c37745e 1541 */
bc1d75fa 1542 if (!encap_valid)
178f69b4 1543 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1544 else
6d2a3ed0 1545 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1546
8914add2
VB		 1547 if (IS_ERR(flow->rule[0])) {
1548 err = PTR_ERR(flow->rule[0]);
1549 goto err_out;
1550 }
1551 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1552
1553 return 0;
8914add2
VB		 1554
1555err_out:
1556 flow_flag_set(flow, FAILED);
1557 return err;
aa0cbbae 1558}
d85cdccb 1559
9272e3df
YK		 1560static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1561{
c620b772 1562 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1563 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1564 spec->match_value,
1565 misc_parameters_3);
1566 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1567 headers_v,
1568 geneve_tlv_option_0_data);
1569
1570 return !!geneve_tlv_opt_0_data;
1571}
1572
d85cdccb
OG		 1573static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1574 struct mlx5e_tc_flow *flow)
1575{
1576 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1577 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1578 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1579 bool vf_tun = false;
f493f155 1580 int out_index;
d85cdccb 1581
777bb800 1582 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1583 mlx5e_put_flow_tunnel_id(flow);
1584
12a240a4 1585 if (flow_flag_test(flow, NOT_READY))
b4a23329 1586 remove_unready_flow(flow);
ef06c9ee 1587
226f2ca3
VB		 1588 if (mlx5e_is_offloaded_flow(flow)) {
1589 if (flow_flag_test(flow, SLOW))
178f69b4 1590 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1591 else
1592 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1593 }
362980ea 1594 complete_all(&flow->del_hw_done);
d85cdccb 1595
9272e3df
YK		 1596 if (mlx5_flow_has_geneve_opt(flow))
1597 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1598
513f8f7f 1599 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1600
777bb800
VB		 1601 if (flow->decap_route)
1602 mlx5e_detach_decap_route(priv, flow);
1603
1604 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2 1605 if (esw_attr->dests[out_index].flags &
100ad4e2
AL		 1606 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1607 !esw_attr->dest_int_port)
8914add2 1608 vf_tun = true;
777bb800 1609 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1610 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1611 kfree(attr->parse_attr->tun_info[out_index]);
1612 }
777bb800 1613 }
d7e75a32 1614
aedd133d 1615 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1616
c7b9038d 1617 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
2c0e5cf5 1618 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1619 if (vf_tun && attr->modify_hdr)
1620 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1621 else
1622 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1623 }
b8aee822
MB		 1624
1625 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1626 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038 1627
166f431e
AL		 1628 if (esw_attr->int_port)
1629 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->int_port);
1630
27484f71
AL		 1631 if (esw_attr->dest_int_port)
1632 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->dest_int_port);
1633
14e6b038
EC		 1634 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1635 mlx5e_detach_decap(priv, flow);
c620b772 1636
88d97486
RD		 1637 kfree(attr->sample_attr);
1638 kvfree(attr->esw_attr->rx_tun_attr);
1639 kvfree(attr->parse_attr);
c620b772 1640 kfree(flow->attr);
d85cdccb
OG		 1641}
1642
0d9f9647 1643struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1644{
c620b772 1645 return flow->attr->counter;
b8aee822
MB		 1646}
1647
6a06c2f7 1648/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1649void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1650{
1651 struct mlx5e_tc_flow *flow, *tmp;
1652
1653 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1654 mlx5e_flow_put(priv, flow);
1655}
1656
04de7dda
RD		 1657static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1658{
1659 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1660
226f2ca3
VB		 1661 if (!flow_flag_test(flow, ESWITCH) ||
1662 !flow_flag_test(flow, DUP))
04de7dda
RD		 1663 return;
1664
1665 mutex_lock(&esw->offloads.peer_mutex);
1666 list_del(&flow->peer);
1667 mutex_unlock(&esw->offloads.peer_mutex);
1668
226f2ca3 1669 flow_flag_clear(flow, DUP);
04de7dda 1670
eb252c3a
RD		 1671 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1672 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1673 kfree(flow->peer_flow);
1674 }
1675
04de7dda
RD		 1676 flow->peer_flow = NULL;
1677}
1678
1679static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1680{
1681 struct mlx5_core_dev *dev = flow->priv->mdev;
1682 struct mlx5_devcom *devcom = dev->priv.devcom;
1683 struct mlx5_eswitch *peer_esw;
1684
1685 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1686 if (!peer_esw)
1687 return;
1688
1689 __mlx5e_tc_del_fdb_peer_flow(flow);
1690 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1691}
1692
e8f887ac 1693static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1694 struct mlx5e_tc_flow *flow)
e8f887ac 1695{
226f2ca3 1696 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1697 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1698 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1699 } else {
d85cdccb 1700 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1701 }
e8f887ac
AV		 1702}
1703
ee950e5d 1704static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1705{
1706 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1707 struct flow_action *flow_action = &rule->action;
1708 const struct flow_action_entry *act;
1709 int i;
1710
ee950e5d
CM		 1711 if (chain)
1712 return false;
1713
0a7fcb78
PB		 1714 flow_action_for_each(i, act, flow_action) {
1715 switch (act->id) {
1716 case FLOW_ACTION_GOTO:
1717 return true;
ee950e5d
CM		 1718 case FLOW_ACTION_SAMPLE:
1719 return true;
0a7fcb78
PB		 1720 default:
1721 continue;
1722 }
1723 }
1724
1725 return false;
1726}
bbd00f7e 1727
0a7fcb78
PB		 1728static int
1729enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1730 struct flow_dissector_key_enc_opts *opts,
1731 struct netlink_ext_ack *extack,
1732 bool *dont_care)
1733{
1734 struct geneve_opt *opt;
1735 int off = 0;
1736
1737 *dont_care = true;
1738
1739 while (opts->len > off) {
1740 opt = (struct geneve_opt *)&opts->data[off];
1741
1742 if (!(*dont_care) || opt->opt_class || opt->type ||
1743 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1744 *dont_care = false;
1745
c51323ee 1746 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1747 opt->type != U8_MAX) {
c50775d0
RD		 1748 NL_SET_ERR_MSG_MOD(extack,
1749 "Partial match of tunnel options in chain > 0 isn't supported");
0a7fcb78
PB		 1750 netdev_warn(priv->netdev,
1751 "Partial match of tunnel options in chain > 0 isn't supported");
1752 return -EOPNOTSUPP;
1753 }
1754 }
1755
1756 off += sizeof(struct geneve_opt) + opt->length * 4;
1757 }
1758
1759 return 0;
1760}
1761
1762#define COPY_DISSECTOR(rule, diss_key, dst)\
1763({ \
1764 struct flow_rule *__rule = (rule);\
1765 typeof(dst) __dst = dst;\
1766\
1767 memcpy(__dst,\
1768 skb_flow_dissector_target(__rule->match.dissector,\
1769 diss_key,\
1770 __rule->match.key),\
1771 sizeof(*__dst));\
1772})
1773
1774static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1775 struct mlx5e_tc_flow *flow,
1776 struct flow_cls_offload *f,
1777 struct net_device *filter_dev)
bbd00f7e 1778{
f9e30088 1779 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1780 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1781 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1782 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1783 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1784 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1785 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1786 struct mlx5e_rep_priv *uplink_rpriv;
1787 struct tunnel_match_key tunnel_key;
1788 bool enc_opts_is_dont_care = true;
1789 u32 tun_id, enc_opts_id = 0;
1790 struct mlx5_eswitch *esw;
1791 u32 value, mask;
8f256622 1792 int err;
2e72eb43 1793
0a7fcb78
PB		 1794 esw = priv->mdev->priv.eswitch;
1795 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1796 uplink_priv = &uplink_rpriv->uplink_priv;
1797
1798 memset(&tunnel_key, 0, sizeof(tunnel_key));
1799 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1800 &tunnel_key.enc_control);
1801 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1802 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1803 &tunnel_key.enc_ipv4);
1804 else
1805 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1806 &tunnel_key.enc_ipv6);
1807 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1808 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1809 &tunnel_key.enc_tp);
1810 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1811 &tunnel_key.enc_key_id);
1812 tunnel_key.filter_ifindex = filter_dev->ifindex;
1813
1814 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1815 if (err)
101f4de9 1816 return err;
bbd00f7e 1817
0a7fcb78
PB		 1818 flow_rule_match_enc_opts(rule, &enc_opts_match);
1819 err = enc_opts_is_dont_care_or_full_match(priv,
1820 enc_opts_match.mask,
1821 extack,
1822 &enc_opts_is_dont_care);
1823 if (err)
1824 goto err_enc_opts;
fe1587a7 1825
0a7fcb78 1826 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1827 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1828 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1829 sizeof(*enc_opts_match.key));
1830 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1831 sizeof(*enc_opts_match.mask));
1832
0a7fcb78 1833 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1834 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1835 if (err)
1836 goto err_enc_opts;
1837 }
fe1587a7 1838
0a7fcb78
PB		 1839 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1840 mask = enc_opts_id ? TUNNEL_ID_MASK :
1841 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1842
0a7fcb78
PB		 1843 if (attr->chain) {
1844 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1845 TUNNEL_TO_REG, value, mask);
1846 } else {
1847 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1848 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1849 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1850 TUNNEL_TO_REG, value);
1851 if (err)
1852 goto err_set;
fe1587a7 1853
0a7fcb78 1854 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1855 }
bbd00f7e 1856
0a7fcb78
PB		 1857 flow->tunnel_id = value;
1858 return 0;
bcef735c 1859
0a7fcb78
PB		 1860err_set:
1861 if (enc_opts_id)
1862 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1863 enc_opts_id);
1864err_enc_opts:
1865 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1866 return err;
1867}
bcef735c 1868
0a7fcb78
PB		 1869static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1870{
1871 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1872 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1873 struct mlx5_rep_uplink_priv *uplink_priv;
1874 struct mlx5e_rep_priv *uplink_rpriv;
1875 struct mlx5_eswitch *esw;
bcef735c 1876
0a7fcb78
PB		 1877 esw = flow->priv->mdev->priv.eswitch;
1878 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1879 uplink_priv = &uplink_rpriv->uplink_priv;
1880
1881 if (tun_id)
1882 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1883 if (enc_opts_id)
1884 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1885 enc_opts_id);
1886}
e98bedf5 1887
4c3844d9
PB		 1888u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1889{
1890 return flow->tunnel_id;
1891}
1892
fca53304
EB		 1893void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1894 struct flow_match_basic *match, bool outer,
1895 void *headers_c, void *headers_v)
1896{
1897 bool ip_version_cap;
1898
1899 ip_version_cap = outer ?
1900 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1901 ft_field_support.outer_ip_version) :
1902 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1903 ft_field_support.inner_ip_version);
1904
1905 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1906 (match->key->n_proto == htons(ETH_P_IP) ||
1907 match->key->n_proto == htons(ETH_P_IPV6))) {
1908 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1909 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1910 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1911 } else {
1912 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1913 ntohs(match->mask->n_proto));
1914 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1915 ntohs(match->key->n_proto));
1916 }
4a5d5d73
EB		 1917}
1918
0d9f9647 1919u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1920{
1921 void *headers_v;
1922 u16 ethertype;
1923 u8 ip_version;
1924
1925 if (outer)
1926 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1927 else
1928 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1929
1930 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1931 /* Return ip_version converted from ethertype anyway */
1932 if (!ip_version) {
1933 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1934 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1935 ip_version = 4;
1936 else if (ethertype == ETH_P_IPV6)
1937 ip_version = 6;
1938 }
1939 return ip_version;
1940}
1941
b6dfff21
PB		 1942/* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
1943 * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
1944 * +---------+----------------------------------------+
1945 * |Arriving | Arriving Outer Header |
1946 * | Inner +---------+---------+---------+----------+
1947 * | Header | Not-ECT | ECT(0) | ECT(1) | CE |
1948 * +---------+---------+---------+---------+----------+
1949 * | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop> |
1950 * | ECT(0) | ECT(0) | ECT(0) | ECT(1) | CE* |
1951 * | ECT(1) | ECT(1) | ECT(1) | ECT(1)* | CE* |
1952 * | CE | CE | CE | CE | CE |
1953 * +---------+---------+---------+---------+----------+
1954 *
1955 * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
1956 * the inner ip_ecn value before hardware decap action.
1957 *
1958 * Cells marked are changed from original inner packet ip_ecn value during decap, and
1959 * so matching those values on inner ip_ecn before decap will fail.
1960 *
1961 * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
1962 * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
1963 * and such we can drop the inner ip_ecn=CE match.
1964 */
1965
1966static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
1967 struct flow_cls_offload *f,
1968 bool *match_inner_ecn)
1969{
1970 u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
1971 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1972 struct netlink_ext_ack *extack = f->common.extack;
1973 struct flow_match_ip match;
1974
1975 *match_inner_ecn = true;
1976
1977 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1978 flow_rule_match_enc_ip(rule, &match);
1979 outer_ecn_key = match.key->tos & INET_ECN_MASK;
1980 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
1981 }
1982
1983 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1984 flow_rule_match_ip(rule, &match);
1985 inner_ecn_key = match.key->tos & INET_ECN_MASK;
1986 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
1987 }
1988
1989 if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
1990 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
1991 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
1992 return -EOPNOTSUPP;
1993 }
1994
1995 if (!outer_ecn_mask) {
1996 if (!inner_ecn_mask)
1997 return 0;
1998
1999 NL_SET_ERR_MSG_MOD(extack,
2000 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2001 netdev_warn(priv->netdev,
2002 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2003 return -EOPNOTSUPP;
2004 }
2005
2006 if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2007 NL_SET_ERR_MSG_MOD(extack,
2008 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2009 netdev_warn(priv->netdev,
2010 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2011 return -EOPNOTSUPP;
2012 }
2013
2014 if (!inner_ecn_mask)
2015 return 0;
2016
2017 /* Both inner and outer have full mask on ecn */
2018
2019 if (outer_ecn_key == INET_ECN_ECT_1) {
2020 /* inner ecn might change by DECAP action */
2021
2022 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2023 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2024 return -EOPNOTSUPP;
2025 }
2026
2027 if (outer_ecn_key != INET_ECN_CE)
2028 return 0;
2029
2030 if (inner_ecn_key != INET_ECN_CE) {
2031 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2032 NL_SET_ERR_MSG_MOD(extack,
2033 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2034 netdev_warn(priv->netdev,
2035 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2036 return -EOPNOTSUPP;
2037 }
2038
2039 /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2040 * drop match on inner ecn
2041 */
2042 *match_inner_ecn = false;
2043
2044 return 0;
2045}
2046
bbd00f7e 2047static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2048 struct mlx5e_tc_flow *flow,
bbd00f7e 2049 struct mlx5_flow_spec *spec,
f9e30088 2050 struct flow_cls_offload *f,
0a7fcb78
PB		 2051 struct net_device *filter_dev,
2052 u8 *match_level,
2053 bool *match_inner)
bbd00f7e 2054{
a508728a 2055 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 2056 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2057 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2058 bool needs_mapping, sets_mapping;
8f256622 2059 int err;
2e72eb43 2060
0885ae1a
A		 2061 if (!mlx5e_is_eswitch_flow(flow)) {
2062 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
0a7fcb78 2063 return -EOPNOTSUPP;
0885ae1a 2064 }
0a7fcb78 2065
c620b772 2066 needs_mapping = !!flow->attr->chain;
ee950e5d 2067 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 2068 *match_inner = !needs_mapping;
2069
2070 if ((needs_mapping || sets_mapping) &&
636bb968 2071 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
c50775d0
RD		 2072 NL_SET_ERR_MSG_MOD(extack,
2073 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2074 netdev_warn(priv->netdev,
636bb968 2075 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2076 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2077 }
2078
c620b772 2079 if (!flow->attr->chain) {
0a7fcb78
PB		 2080 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2081 match_level);
2082 if (err) {
e98bedf5 2083 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2084 "Failed to parse tunnel attributes");
2085 netdev_warn(priv->netdev,
2086 "Failed to parse tunnel attributes");
2087 return err;
e98bedf5
EB		 2088 }
2089
14e6b038
EC		 2090 /* With mpls over udp we decapsulate using packet reformat
2091 * object
2092 */
2093 if (!netif_is_bareudp(filter_dev))
c620b772 2094 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 2095 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2096 if (err)
2097 return err;
2098 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2099 struct mlx5_flow_spec *tmp_spec;
2100
2101 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2102 if (!tmp_spec) {
2103 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2104 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2105 return -ENOMEM;
2106 }
2107 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2108
2109 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2110 if (err) {
2111 kvfree(tmp_spec);
2112 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2113 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2114 return err;
2115 }
2116 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2117 kvfree(tmp_spec);
2118 if (err)
2119 return err;
bcef735c
OG		 2120 }
2121
0a7fcb78
PB		 2122 if (!needs_mapping && !sets_mapping)
2123 return 0;
bbd00f7e 2124
0a7fcb78 2125 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2126}
bbd00f7e 2127
0a7fcb78 2128static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2129{
0a7fcb78
PB		 2130 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2131 inner_headers);
bbd00f7e
HHZ		 2132}
2133
0a7fcb78 2134static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2135{
0a7fcb78
PB		 2136 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2137 inner_headers);
2138}
2139
2140static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2141{
2142 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2143 outer_headers);
2144}
2145
2146static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2147{
2148 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2149 outer_headers);
8377629e
EB		 2150}
2151
8ee72638 2152void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
8377629e
EB		 2153{
2154 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2155 get_match_inner_headers_value(spec) :
2156 get_match_outer_headers_value(spec);
2157}
2158
8ee72638 2159void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
0a7fcb78
PB		 2160{
2161 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2162 get_match_inner_headers_criteria(spec) :
2163 get_match_outer_headers_criteria(spec);
8377629e
EB		 2164}
2165
6d65bc64 2166static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2167 struct flow_cls_offload *f)
2168{
2169 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2170 struct netlink_ext_ack *extack = f->common.extack;
2171 struct net_device *ingress_dev;
2172 struct flow_match_meta match;
2173
2174 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2175 return 0;
2176
2177 flow_rule_match_meta(rule, &match);
e3e0f9b2 2178 if (!match.mask->ingress_ifindex)
2179 return 0;
2180
6d65bc64 2181 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2182 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2183 return -EOPNOTSUPP;
6d65bc64 2184 }
2185
2186 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2187 match.key->ingress_ifindex);
2188 if (!ingress_dev) {
2189 NL_SET_ERR_MSG_MOD(extack,
2190 "Can't find the ingress port to match on");
a683012a 2191 return -ENOENT;
6d65bc64 2192 }
2193
2194 if (ingress_dev != filter_dev) {
2195 NL_SET_ERR_MSG_MOD(extack,
2196 "Can't match on the ingress filter port");
a683012a 2197 return -EOPNOTSUPP;
6d65bc64 2198 }
2199
2200 return 0;
2201}
2202
72046a91
EC		 2203static bool skip_key_basic(struct net_device *filter_dev,
2204 struct flow_cls_offload *f)
2205{
2206 /* When doing mpls over udp decap, the user needs to provide
2207 * MPLS_UC as the protocol in order to be able to match on mpls
2208 * label fields. However, the actual ethertype is IP so we want to
2209 * avoid matching on this, otherwise we'll fail the match.
2210 */
2211 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2212 return true;
2213
2214 return false;
2215}
2216
de0af0bf 2217static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2218 struct mlx5e_tc_flow *flow,
de0af0bf 2219 struct mlx5_flow_spec *spec,
f9e30088 2220 struct flow_cls_offload *f,
54c177ca 2221 struct net_device *filter_dev,
93b3586e 2222 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2223{
e98bedf5 2224 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2225 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2226 outer_headers);
2227 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2228 outer_headers);
699e96dd
JL		 2229 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2230 misc_parameters);
2231 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2232 misc_parameters);
a3222a2d
MD		 2233 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2234 misc_parameters_3);
2235 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2236 misc_parameters_3);
f9e30088 2237 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2238 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2239 enum fs_flow_table_type fs_type;
b6dfff21 2240 bool match_inner_ecn = true;
e3a2b7ed
AV		 2241 u16 addr_type = 0;
2242 u8 ip_proto = 0;
93b3586e 2243 u8 *match_level;
6d65bc64 2244 int err;
e3a2b7ed 2245
afe93f71 2246 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2247 match_level = outer_match_level;
de0af0bf 2248
8f256622 2249 if (dissector->used_keys &
3d144578
VB		 2250 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2251 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2252 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2253 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2254 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2255 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2256 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2257 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2258 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2259 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2260 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2261 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2262 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2263 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2264 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2265 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2266 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2267 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2268 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2269 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2270 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2271 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2272 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2273 dissector->used_keys);
e3a2b7ed
AV		 2274 return -EOPNOTSUPP;
2275 }
2276
075973c7 2277 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2278 bool match_inner = false;
bbd00f7e 2279
0a7fcb78
PB		 2280 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2281 outer_match_level, &match_inner);
2282 if (err)
2283 return err;
2284
2285 if (match_inner) {
2286 /* header pointers should point to the inner headers
2287 * if the packet was decapsulated already.
2288 * outer headers are set by parse_tunnel_attr.
2289 */
2290 match_level = inner_match_level;
2291 headers_c = get_match_inner_headers_criteria(spec);
2292 headers_v = get_match_inner_headers_value(spec);
2293 }
b6dfff21
PB		 2294
2295 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2296 if (err)
2297 return err;
bbd00f7e
HHZ		 2298 }
2299
6d65bc64 2300 err = mlx5e_flower_parse_meta(filter_dev, f);
2301 if (err)
2302 return err;
2303
72046a91
EC		 2304 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2305 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2306 struct flow_match_basic match;
2307
2308 flow_rule_match_basic(rule, &match);
fca53304
EB		 2309 mlx5e_tc_set_ethertype(priv->mdev, &match,
2310 match_level == outer_match_level,
2311 headers_c, headers_v);
e3a2b7ed 2312
8f256622 2313 if (match.mask->n_proto)
d708f902 2314 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2315 }
35a605db
EB		 2316 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2317 is_vlan_dev(filter_dev)) {
2318 struct flow_dissector_key_vlan filter_dev_mask;
2319 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2320 struct flow_match_vlan match;
2321
35a605db
EB		 2322 if (is_vlan_dev(filter_dev)) {
2323 match.key = &filter_dev_key;
2324 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2325 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2326 match.key->vlan_priority = 0;
2327 match.mask = &filter_dev_mask;
2328 memset(match.mask, 0xff, sizeof(*match.mask));
2329 match.mask->vlan_priority = 0;
2330 } else {
2331 flow_rule_match_vlan(rule, &match);
2332 }
8f256622
PNA		 2333 if (match.mask->vlan_id ||
2334 match.mask->vlan_priority ||
2335 match.mask->vlan_tpid) {
2336 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2337 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2338 svlan_tag, 1);
2339 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2340 svlan_tag, 1);
2341 } else {
2342 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2343 cvlan_tag, 1);
2344 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2345 cvlan_tag, 1);
2346 }
095b6cfd 2347
8f256622
PNA		 2348 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2349 match.mask->vlan_id);
2350 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2351 match.key->vlan_id);
358d79a4 2352
8f256622
PNA		 2353 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2354 match.mask->vlan_priority);
2355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2356 match.key->vlan_priority);
54782900 2357
d708f902 2358 *match_level = MLX5_MATCH_L2;
54782900 2359 }
d3a80bb5 2360 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2361 /* cvlan_tag enabled in match criteria and
2362 * disabled in match value means both S & C tags
2363 * don't exist (untagged of both)
2364 */
cee26487 2365 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2366 *match_level = MLX5_MATCH_L2;
54782900
OG		 2367 }
2368
8f256622
PNA		 2369 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2370 struct flow_match_vlan match;
2371
12d5cbf8 2372 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2373 if (match.mask->vlan_id ||
2374 match.mask->vlan_priority ||
2375 match.mask->vlan_tpid) {
afe93f71
RD		 2376 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2377 fs_type)) {
2378 NL_SET_ERR_MSG_MOD(extack,
2379 "Matching on CVLAN is not supported");
2380 return -EOPNOTSUPP;
2381 }
2382
8f256622 2383 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2384 MLX5_SET(fte_match_set_misc, misc_c,
2385 outer_second_svlan_tag, 1);
2386 MLX5_SET(fte_match_set_misc, misc_v,
2387 outer_second_svlan_tag, 1);
2388 } else {
2389 MLX5_SET(fte_match_set_misc, misc_c,
2390 outer_second_cvlan_tag, 1);
2391 MLX5_SET(fte_match_set_misc, misc_v,
2392 outer_second_cvlan_tag, 1);
2393 }
2394
2395 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2396 match.mask->vlan_id);
699e96dd 2397 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2398 match.key->vlan_id);
699e96dd 2399 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2400 match.mask->vlan_priority);
699e96dd 2401 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2402 match.key->vlan_priority);
699e96dd
JL		 2403
2404 *match_level = MLX5_MATCH_L2;
0faddfe6 2405 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2406 }
2407 }
2408
8f256622
PNA		 2409 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2410 struct flow_match_eth_addrs match;
54782900 2411
8f256622 2412 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2413 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2414 dmac_47_16),
8f256622 2415 match.mask->dst);
d3a80bb5
OG		 2416 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2417 dmac_47_16),
8f256622 2418 match.key->dst);
d3a80bb5
OG		 2419
2420 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2421 smac_47_16),
8f256622 2422 match.mask->src);
d3a80bb5
OG		 2423 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2424 smac_47_16),
8f256622 2425 match.key->src);
d3a80bb5 2426
8f256622
PNA		 2427 if (!is_zero_ether_addr(match.mask->src) ||
2428 !is_zero_ether_addr(match.mask->dst))
d708f902 2429 *match_level = MLX5_MATCH_L2;
54782900
OG		 2430 }
2431
8f256622
PNA		 2432 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2433 struct flow_match_control match;
54782900 2434
8f256622
PNA		 2435 flow_rule_match_control(rule, &match);
2436 addr_type = match.key->addr_type;
54782900
OG		 2437
2438 /* the HW doesn't support frag first/later */
0885ae1a
A		 2439 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2440 NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
54782900 2441 return -EOPNOTSUPP;
0885ae1a 2442 }
54782900 2443
8f256622 2444 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2445 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2447 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2448
2449 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2450 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2451 *match_level = MLX5_MATCH_L2;
54782900
OG		 2452 /* *** L2 attributes parsing up to here *** */
2453 else
83621b7d 2454 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2455 }
2456 }
2457
8f256622
PNA		 2458 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2459 struct flow_match_basic match;
2460
2461 flow_rule_match_basic(rule, &match);
2462 ip_proto = match.key->ip_proto;
54782900
OG		 2463
2464 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2465 match.mask->ip_proto);
54782900 2466 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2467 match.key->ip_proto);
54782900 2468
8f256622 2469 if (match.mask->ip_proto)
d708f902 2470 *match_level = MLX5_MATCH_L3;
54782900
OG		 2471 }
2472
e3a2b7ed 2473 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2474 struct flow_match_ipv4_addrs match;
e3a2b7ed 2475
8f256622 2476 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2477 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2478 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2479 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2480 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2481 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2482 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2483 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2484 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2485 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2486 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2487 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2488 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2489
8f256622 2490 if (match.mask->src || match.mask->dst)
d708f902 2491 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2492 }
2493
2494 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2495 struct flow_match_ipv6_addrs match;
e3a2b7ed 2496
8f256622 2497 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2498 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2499 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2500 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2501 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2502 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2503 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2504
2505 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2506 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2507 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2508 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2509 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2510 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2511
8f256622
PNA		 2512 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2513 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2514 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2515 }
2516
8f256622
PNA		 2517 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2518 struct flow_match_ip match;
1f97a526 2519
8f256622 2520 flow_rule_match_ip(rule, &match);
b6dfff21
PB		 2521 if (match_inner_ecn) {
2522 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2523 match.mask->tos & 0x3);
2524 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2525 match.key->tos & 0x3);
2526 }
1f97a526 2527
8f256622
PNA		 2528 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2529 match.mask->tos >> 2);
2530 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2531 match.key->tos >> 2);
1f97a526 2532
8f256622
PNA		 2533 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2534 match.mask->ttl);
2535 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2536 match.key->ttl);
1f97a526 2537
8f256622 2538 if (match.mask->ttl &&
a8ade55f 2539 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2540 ft_field_support.outer_ipv4_ttl)) {
2541 NL_SET_ERR_MSG_MOD(extack,
2542 "Matching on TTL is not supported");
1f97a526 2543 return -EOPNOTSUPP;
e98bedf5 2544 }
a8ade55f 2545
8f256622 2546 if (match.mask->tos || match.mask->ttl)
d708f902 2547 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2548 }
2549
54782900
OG		 2550 /* *** L3 attributes parsing up to here *** */
2551
8f256622
PNA		 2552 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2553 struct flow_match_ports match;
2554
2555 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2556 switch (ip_proto) {
2557 case IPPROTO_TCP:
2558 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2559 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2560 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2561 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2562
2563 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2564 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2565 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2566 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2567 break;
2568
2569 case IPPROTO_UDP:
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2571 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2572 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2573 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2574
2575 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2576 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2577 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2578 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2579 break;
2580 default:
e98bedf5
EB		 2581 NL_SET_ERR_MSG_MOD(extack,
2582 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2583 netdev_err(priv->netdev,
2584 "Only UDP and TCP transport are supported\n");
2585 return -EINVAL;
2586 }
de0af0bf 2587
8f256622 2588 if (match.mask->src || match.mask->dst)
d708f902 2589 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2590 }
2591
8f256622
PNA		 2592 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2593 struct flow_match_tcp match;
e77834ec 2594
8f256622 2595 flow_rule_match_tcp(rule, &match);
e77834ec 2596 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2597 ntohs(match.mask->flags));
e77834ec 2598 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2599 ntohs(match.key->flags));
e77834ec 2600
8f256622 2601 if (match.mask->flags)
d708f902 2602 *match_level = MLX5_MATCH_L4;
e77834ec 2603 }
a3222a2d
MD		 2604 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2605 struct flow_match_icmp match;
e77834ec 2606
a3222a2d
MD		 2607 flow_rule_match_icmp(rule, &match);
2608 switch (ip_proto) {
2609 case IPPROTO_ICMP:
2610 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2611 MLX5_FLEX_PROTO_ICMP)) {
2612 NL_SET_ERR_MSG_MOD(extack,
2613 "Match on Flex protocols for ICMP is not supported");
a3222a2d 2614 return -EOPNOTSUPP;
0885ae1a 2615 }
a3222a2d
MD		 2616 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2617 match.mask->type);
2618 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2619 match.key->type);
2620 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2621 match.mask->code);
2622 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2623 match.key->code);
2624 break;
2625 case IPPROTO_ICMPV6:
2626 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2627 MLX5_FLEX_PROTO_ICMPV6)) {
2628 NL_SET_ERR_MSG_MOD(extack,
2629 "Match on Flex protocols for ICMPV6 is not supported");
a3222a2d 2630 return -EOPNOTSUPP;
0885ae1a 2631 }
a3222a2d
MD		 2632 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2633 match.mask->type);
2634 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2635 match.key->type);
2636 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2637 match.mask->code);
2638 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2639 match.key->code);
2640 break;
2641 default:
2642 NL_SET_ERR_MSG_MOD(extack,
2643 "Code and type matching only with ICMP and ICMPv6");
2644 netdev_err(priv->netdev,
2645 "Code and type matching only with ICMP and ICMPv6\n");
2646 return -EINVAL;
2647 }
2648 if (match.mask->code || match.mask->type) {
2649 *match_level = MLX5_MATCH_L4;
2650 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2651 }
2652 }
39c538d6 2653 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2654 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2655 !netif_is_bareudp(filter_dev)) {
2656 NL_SET_ERR_MSG_MOD(extack,
2657 "Matching on MPLS is supported only for MPLS over UDP");
2658 netdev_err(priv->netdev,
2659 "Matching on MPLS is supported only for MPLS over UDP\n");
2660 return -EOPNOTSUPP;
2661 }
2662
e3a2b7ed
AV		 2663 return 0;
2664}
2665
de0af0bf 2666static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2667 struct mlx5e_tc_flow *flow,
de0af0bf 2668 struct mlx5_flow_spec *spec,
f9e30088 2669 struct flow_cls_offload *f,
54c177ca 2670 struct net_device *filter_dev)
de0af0bf 2671{
93b3586e 2672 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2673 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2674 struct mlx5_core_dev *dev = priv->mdev;
2675 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2676 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2677 struct mlx5_eswitch_rep *rep;
226f2ca3 2678 bool is_eswitch_flow;
de0af0bf
RD		 2679 int err;
2680
93b3586e
HN		 2681 inner_match_level = MLX5_MATCH_NONE;
2682 outer_match_level = MLX5_MATCH_NONE;
2683
0a7fcb78
PB		 2684 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2685 &inner_match_level, &outer_match_level);
93b3586e
HN		 2686 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2687 outer_match_level : inner_match_level;
de0af0bf 2688
226f2ca3
VB		 2689 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2690 if (!err && is_eswitch_flow) {
1d447a39 2691 rep = rpriv->rep;
b05af6aa 2692 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2693 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2694 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2695 NL_SET_ERR_MSG_MOD(extack,
2696 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2697 netdev_warn(priv->netdev,
2698 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2699 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2700 return -EOPNOTSUPP;
2701 }
2702 }
2703
c620b772
AL		 2704 flow->attr->inner_match_level = inner_match_level;
2705 flow->attr->outer_match_level = outer_match_level;
2706
38aa51c1 2707
de0af0bf
RD		 2708 return err;
2709}
2710
d79b6df6
OG		 2711struct mlx5_fields {
2712 u8 field;
88f30bbc
DL		 2713 u8 field_bsize;
2714 u32 field_mask;
d79b6df6 2715 u32 offset;
27c11b6b 2716 u32 match_offset;
d79b6df6
OG		 2717};
2718
88f30bbc
DL		 2719#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2720 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2721 offsetof(struct pedit_headers, field) + (off), \
2722 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2723
2ef86872
EB		 2724/* masked values are the same and there are no rewrites that do not have a
2725 * match.
2726 */
2727#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2728 type matchmaskx = *(type *)(matchmaskp); \
2729 type matchvalx = *(type *)(matchvalp); \
2730 type maskx = *(type *)(maskp); \
2731 type valx = *(type *)(valp); \
2732 \
2733 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2734 matchmaskx)); \
2735})
2736
27c11b6b 2737static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2738 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2739{
2740 bool same = false;
2741
88f30bbc
DL		 2742 switch (bsize) {
2743 case 8:
2ef86872 2744 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2745 break;
88f30bbc 2746 case 16:
2ef86872 2747 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2748 break;
88f30bbc 2749 case 32:
2ef86872 2750 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2751 break;
2752 }
2753
2754 return same;
2755}
a8e4f0c4 2756
d79b6df6 2757static struct mlx5_fields fields[] = {
88f30bbc
DL		 2758 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2759 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2760 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2761 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2762 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2763 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2764
ab9341b5 2765 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2766 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2767 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2768 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2769
2770 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2771 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2772 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2773 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2774 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2775 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2776 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2777 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2778 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2779 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2780 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2781 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2782 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2783 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2784 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2785 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2786 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2787 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2788
88f30bbc
DL		 2789 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2790 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2791 /* in linux iphdr tcp_flags is 8 bits long */
2792 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2793
88f30bbc
DL		 2794 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2795 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2796};
2797
82198d8b
MD		 2798static unsigned long mask_to_le(unsigned long mask, int size)
2799{
2800 __be32 mask_be32;
2801 __be16 mask_be16;
2802
2803 if (size == 32) {
2804 mask_be32 = (__force __be32)(mask);
2805 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2806 } else if (size == 16) {
2807 mask_be32 = (__force __be32)(mask);
2808 mask_be16 = *(__be16 *)&mask_be32;
2809 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2810 }
2811
2812 return mask;
2813}
6ae4a6a5
PB		 2814static int offload_pedit_fields(struct mlx5e_priv *priv,
2815 int namespace,
2816 struct pedit_headers_action *hdrs,
e98bedf5 2817 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2818 u32 *action_flags,
e98bedf5 2819 struct netlink_ext_ack *extack)
d79b6df6
OG		 2820{
2821 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
88f30bbc
DL		 2822 void *headers_c, *headers_v, *action, *vals_p;
2823 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2824 struct mlx5e_tc_mod_hdr_acts *mod_acts;
82198d8b 2825 unsigned long mask, field_mask;
2c0e5cf5
PB		 2826 int i, first, last, next_z;
2827 struct mlx5_fields *f;
88f30bbc
DL		 2828 u8 cmd;
2829
6ae4a6a5 2830 mod_acts = &parse_attr->mod_hdr_acts;
8ee72638
RD		 2831 headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
2832 headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2833
73867881
PNA		 2834 set_masks = &hdrs[0].masks;
2835 add_masks = &hdrs[1].masks;
2836 set_vals = &hdrs[0].vals;
2837 add_vals = &hdrs[1].vals;
d79b6df6 2838
d79b6df6 2839 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2840 bool skip;
2841
d79b6df6
OG		 2842 f = &fields[i];
2843 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2844 s_mask = 0;
2845 a_mask = 0;
d79b6df6
OG		 2846
2847 s_masks_p = (void *)set_masks + f->offset;
2848 a_masks_p = (void *)add_masks + f->offset;
2849
88f30bbc
DL		 2850 s_mask = *s_masks_p & f->field_mask;
2851 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2852
2853 if (!s_mask && !a_mask) /* nothing to offload here */
2854 continue;
2855
2856 if (s_mask && a_mask) {
e98bedf5
EB		 2857 NL_SET_ERR_MSG_MOD(extack,
2858 "can't set and add to the same HW field");
61b6a6c3
CH		 2859 netdev_warn(priv->netdev,
2860 "mlx5: can't set and add to the same HW field (%x)\n",
2861 f->field);
d79b6df6
OG		 2862 return -EOPNOTSUPP;
2863 }
2864
27c11b6b 2865 skip = false;
d79b6df6 2866 if (s_mask) {
27c11b6b
EB		 2867 void *match_mask = headers_c + f->match_offset;
2868 void *match_val = headers_v + f->match_offset;
2869
d79b6df6
OG		 2870 cmd = MLX5_ACTION_TYPE_SET;
2871 mask = s_mask;
2872 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2873 /* don't rewrite if we have a match on the same value */
2874 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2875 match_mask, f->field_bsize))
27c11b6b 2876 skip = true;
d79b6df6 2877 /* clear to denote we consumed this field */
88f30bbc 2878 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2879 } else {
2880 cmd = MLX5_ACTION_TYPE_ADD;
2881 mask = a_mask;
2882 vals_p = (void *)add_vals + f->offset;
27c11b6b 2883 /* add 0 is no change */
88f30bbc 2884 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2885 skip = true;
d79b6df6 2886 /* clear to denote we consumed this field */
88f30bbc 2887 *a_masks_p &= ~f->field_mask;
d79b6df6 2888 }
27c11b6b
EB		 2889 if (skip)
2890 continue;
d79b6df6 2891
82198d8b 2892 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2893
88f30bbc
DL		 2894 first = find_first_bit(&mask, f->field_bsize);
2895 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2896 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2897 if (first < next_z && next_z < last) {
e98bedf5
EB		 2898 NL_SET_ERR_MSG_MOD(extack,
2899 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2900 netdev_warn(priv->netdev,
2901 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2902 mask);
d79b6df6
OG		 2903 return -EOPNOTSUPP;
2904 }
2905
2c0e5cf5
PB		 2906 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
2907 if (IS_ERR(action)) {
6ae4a6a5
PB		 2908 NL_SET_ERR_MSG_MOD(extack,
2909 "too many pedit actions, can't offload");
2910 mlx5_core_warn(priv->mdev,
2911 "mlx5: parsed %d pedit actions, can't do more\n",
2912 mod_acts->num_actions);
2c0e5cf5 2913 return PTR_ERR(action);
6ae4a6a5
PB		 2914 }
2915
d79b6df6
OG		 2916 MLX5_SET(set_action_in, action, action_type, cmd);
2917 MLX5_SET(set_action_in, action, field, f->field);
2918
2919 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2920 int start;
2921
82198d8b
MD		 2922 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2923
88f30bbc 2924 /* if field is bit sized it can start not from first bit */
82198d8b 2925 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2926
2927 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2928 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2929 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2930 }
2931
88f30bbc 2932 if (f->field_bsize == 32)
2b64beba 2933 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2934 else if (f->field_bsize == 16)
2b64beba 2935 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2936 else if (f->field_bsize == 8)
2b64beba 2937 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2938
6ae4a6a5 2939 ++mod_acts->num_actions;
d79b6df6
OG		 2940 }
2941
d79b6df6
OG		 2942 return 0;
2943}
2944
d79b6df6
OG		 2945static const struct pedit_headers zero_masks = {};
2946
c500c86b
PNA		 2947static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2948 struct mlx5e_tc_flow_parse_attr *parse_attr,
2949 struct pedit_headers_action *hdrs,
27c11b6b 2950 u32 *action_flags,
c500c86b
PNA		 2951 struct netlink_ext_ack *extack)
2952{
2953 struct pedit_headers *cmd_masks;
2954 int err;
2955 u8 cmd;
2956
6ae4a6a5
PB		 2957 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2958 action_flags, extack);
d79b6df6
OG		 2959 if (err < 0)
2960 goto out_dealloc_parsed_actions;
2961
2962 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2963 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2964 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2965 NL_SET_ERR_MSG_MOD(extack,
2966 "attempt to offload an unsupported field");
b3a433de 2967 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2968 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2969 16, 1, cmd_masks, sizeof(zero_masks), true);
2970 err = -EOPNOTSUPP;
2971 goto out_dealloc_parsed_actions;
2972 }
2973 }
2974
2975 return 0;
2976
2977out_dealloc_parsed_actions:
2c0e5cf5 2978 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2979 return err;
2980}
2981
8998576b
DL		 2982struct ip_ttl_word {
2983 __u8 ttl;
2984 __u8 protocol;
2985 __sum16 check;
2986};
2987
2988struct ipv6_hoplimit_word {
2989 __be16 payload_len;
2990 __u8 nexthdr;
2991 __u8 hop_limit;
2992};
2993
1836d780
RD		 2994static bool
2995is_action_keys_supported(const struct flow_action_entry *act, bool ct_flow,
2996 bool *modify_ip_header, bool *modify_tuple,
2997 struct netlink_ext_ack *extack)
8998576b
DL		 2998{
2999 u32 mask, offset;
3000 u8 htype;
3001
3002 htype = act->mangle.htype;
3003 offset = act->mangle.offset;
3004 mask = ~act->mangle.mask;
3005 /* For IPv4 & IPv6 header check 4 byte word,
3006 * to determine that modified fields
3007 * are NOT ttl & hop_limit only.
3008 */
3009 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3010 struct ip_ttl_word *ttl_word =
3011 (struct ip_ttl_word *)&mask;
3012
3013 if (offset != offsetof(struct iphdr, ttl) ||
3014 ttl_word->protocol ||
3015 ttl_word->check) {
4c3844d9
PB		 3016 *modify_ip_header = true;
3017 }
3018
7e36feeb
PB		 3019 if (offset >= offsetof(struct iphdr, saddr))
3020 *modify_tuple = true;
3021
3022 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3023 NL_SET_ERR_MSG_MOD(extack,
3024 "can't offload re-write of ipv4 address with action ct");
1836d780 3025 return false;
8998576b
DL		 3026 }
3027 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3028 struct ipv6_hoplimit_word *hoplimit_word =
3029 (struct ipv6_hoplimit_word *)&mask;
3030
3031 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3032 hoplimit_word->payload_len ||
3033 hoplimit_word->nexthdr) {
4c3844d9
PB		 3034 *modify_ip_header = true;
3035 }
3036
7e36feeb
PB		 3037 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3038 *modify_tuple = true;
3039
3040 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3041 NL_SET_ERR_MSG_MOD(extack,
3042 "can't offload re-write of ipv6 address with action ct");
1836d780 3043 return false;
8998576b 3044 }
7e36feeb
PB		 3045 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3046 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3047 *modify_tuple = true;
3048 if (ct_flow) {
3049 NL_SET_ERR_MSG_MOD(extack,
3050 "can't offload re-write of transport header ports with action ct");
1836d780 3051 return false;
7e36feeb 3052 }
8998576b 3053 }
4c3844d9 3054
1836d780 3055 return true;
8998576b
DL		 3056}
3057
96b5b458
DC		 3058static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3059 bool ct_flow, struct netlink_ext_ack *extack,
3060 struct mlx5e_priv *priv,
3061 struct mlx5_flow_spec *spec)
3062{
3063 if (!modify_tuple || ct_clear)
3064 return true;
3065
3066 if (ct_flow) {
3067 NL_SET_ERR_MSG_MOD(extack,
3068 "can't offload tuple modification with non-clear ct()");
3069 netdev_info(priv->netdev,
3070 "can't offload tuple modification with non-clear ct()");
3071 return false;
3072 }
3073
3074 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3075 * (or after clear action), as otherwise, since the tuple is changed,
3076 * we can't restore ct state
3077 */
3078 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3079 NL_SET_ERR_MSG_MOD(extack,
3080 "can't offload tuple modification with ct matches and no ct(clear) action");
3081 netdev_info(priv->netdev,
3082 "can't offload tuple modification with ct matches and no ct(clear) action");
3083 return false;
3084 }
3085
3086 return true;
3087}
3088
3d486ec4
OS		 3089static bool modify_header_match_supported(struct mlx5e_priv *priv,
3090 struct mlx5_flow_spec *spec,
73867881 3091 struct flow_action *flow_action,
4c3844d9 3092 u32 actions, bool ct_flow,
7e36feeb 3093 bool ct_clear,
e98bedf5 3094 struct netlink_ext_ack *extack)
bdd66ac0 3095{
73867881 3096 const struct flow_action_entry *act;
7e36feeb 3097 bool modify_ip_header, modify_tuple;
fca53304 3098 void *headers_c;
bdd66ac0
OG		 3099 void *headers_v;
3100 u16 ethertype;
8998576b 3101 u8 ip_proto;
1836d780 3102 int i;
bdd66ac0 3103
8ee72638
RD		 3104 headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3105 headers_v = mlx5e_get_match_headers_value(actions, spec);
bdd66ac0
OG		 3106 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3107
3108 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3109 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3110 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3111 goto out_ok;
3112
3113 modify_ip_header = false;
7e36feeb 3114 modify_tuple = false;
73867881
PNA		 3115 flow_action_for_each(i, act, flow_action) {
3116 if (act->id != FLOW_ACTION_MANGLE &&
3117 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3118 continue;
3119
1836d780
RD		 3120 if (!is_action_keys_supported(act, ct_flow,
3121 &modify_ip_header,
3122 &modify_tuple, extack))
3123 return false;
bdd66ac0
OG		 3124 }
3125
96b5b458
DC		 3126 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3127 priv, spec))
7e36feeb 3128 return false;
7e36feeb 3129
bdd66ac0 3130 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3131 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3132 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3133 NL_SET_ERR_MSG_MOD(extack,
3134 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3135 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3136 ip_proto);
bdd66ac0
OG		 3137 return false;
3138 }
3139
3140out_ok:
3141 return true;
3142}
3143
9c1d3511
RD		 3144static bool
3145actions_match_supported_fdb(struct mlx5e_priv *priv,
3146 struct mlx5e_tc_flow_parse_attr *parse_attr,
3147 struct mlx5e_tc_flow *flow,
3148 struct netlink_ext_ack *extack)
bdd66ac0 3149{
d4f401d9 3150 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
9c1d3511 3151 bool ct_flow, ct_clear;
bdd66ac0 3152
9c1d3511
RD		 3153 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3154 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3155
d4f401d9
RD		 3156 if (esw_attr->split_count && ct_flow &&
3157 !MLX5_CAP_GEN(esw_attr->in_mdev, reg_c_preserve)) {
9c1d3511
RD		 3158 /* All registers used by ct are cleared when using
3159 * split rules.
3160 */
3161 NL_SET_ERR_MSG_MOD(extack, "Can't offload mirroring with action ct");
3162 return false;
3163 }
3164
d4f401d9
RD		 3165 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3166 NL_SET_ERR_MSG_MOD(extack,
3167 "current firmware doesn't support split rule for port mirroring");
3168 netdev_warn_once(priv->netdev,
3169 "current firmware doesn't support split rule for port mirroring\n");
3170 return false;
3171 }
3172
9c1d3511
RD		 3173 return true;
3174}
3175
3176static bool
3177actions_match_supported(struct mlx5e_priv *priv,
3178 struct flow_action *flow_action,
3179 struct mlx5e_tc_flow_parse_attr *parse_attr,
3180 struct mlx5e_tc_flow *flow,
3181 struct netlink_ext_ack *extack)
3182{
3183 u32 actions = flow->attr->action;
3184 bool ct_flow, ct_clear;
3185
3186 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
c620b772 3187 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
c620b772 3188
6b50cf45
RD		 3189 if (!(actions &
3190 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3191 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
3192 return false;
3193 }
3194
5623ef8a
RD		 3195 if (!(~actions &
3196 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3197 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
3198 return false;
3199 }
3200
a2446bc7
RD		 3201 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3202 actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3203 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
3204 return false;
3205 }
3206
9c1d3511
RD		 3207 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3208 !modify_header_match_supported(priv, &parse_attr->spec, flow_action,
3209 actions, ct_flow, ct_clear, extack))
3210 return false;
bdd66ac0 3211
9c1d3511
RD		 3212 if (mlx5e_is_eswitch_flow(flow) &&
3213 !actions_match_supported_fdb(priv, parse_attr, flow, extack))
3214 return false;
bdd66ac0
OG		 3215
3216 return true;
3217}
3218
32134847
MD		 3219static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3220{
3221 return priv->mdev == peer_priv->mdev;
3222}
3223
ab3f3d5e 3224bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
5c65c564
OG		 3225{
3226 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3227 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3228
3229 fmdev = priv->mdev;
3230 pmdev = peer_priv->mdev;
3231
59c9d35e
AH		 3232 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3233 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3234
816f6706 3235 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3236}
3237
8333d53e
RD		 3238static int
3239parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3240 struct flow_action *flow_action)
3241{
3242 struct netlink_ext_ack *extack = parse_state->extack;
3243 struct mlx5e_tc_flow *flow = parse_state->flow;
3244 struct mlx5_flow_attr *attr = flow->attr;
3245 enum mlx5_flow_namespace_type ns_type;
3246 struct mlx5e_priv *priv = flow->priv;
3247 const struct flow_action_entry *act;
3248 struct mlx5e_tc_act *tc_act;
3249 int err, i;
3250
3251 ns_type = mlx5e_get_flow_namespace(flow);
3252
3253 flow_action_for_each(i, act, flow_action) {
3254 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3255 if (!tc_act) {
3256 NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3257 return -EOPNOTSUPP;
3258 }
3259
3260 if (!tc_act->can_offload(parse_state, act, i))
3261 return -EOPNOTSUPP;
3262
3263 err = tc_act->parse_action(parse_state, act, priv, attr);
3264 if (err)
3265 return err;
3266 }
3267
dd5ab6d1
RD		 3268 flow_action_for_each(i, act, flow_action) {
3269 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3270 if (!tc_act || !tc_act->post_parse ||
3271 !tc_act->can_offload(parse_state, act, i))
3272 continue;
3273
3274 err = tc_act->post_parse(parse_state, priv, attr);
3275 if (err)
3276 return err;
3277 }
3278
8333d53e
RD		 3279 return 0;
3280}
3281
d9581e2f
RD		 3282static int
3283actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
e98bedf5 3284 struct mlx5e_tc_flow *flow,
d9581e2f
RD		 3285 struct mlx5_flow_attr *attr,
3286 struct pedit_headers_action *hdrs,
e98bedf5 3287 struct netlink_ext_ack *extack)
d9581e2f
RD		 3288{
3289 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3290 enum mlx5_flow_namespace_type ns_type;
3291 int err;
3292
3293 if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3294 !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3295 return 0;
3296
e36db1ee 3297 ns_type = mlx5e_get_flow_namespace(flow);
d9581e2f
RD		 3298
3299 err = alloc_tc_pedit_action(priv, ns_type, parse_attr, hdrs,
3300 &attr->action, extack);
3301 if (err)
3302 return err;
3303
d9581e2f
RD		 3304 if (parse_attr->mod_hdr_acts.num_actions > 0)
3305 return 0;
3306
fc3a879a 3307 /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
d9581e2f 3308 attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2c0e5cf5 3309 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d9581e2f
RD		 3310
3311 if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3312 return 0;
3313
3314 if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3315 (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3316 attr->esw_attr->split_count = 0;
3317
3318 return 0;
3319}
3320
df990477
RD		 3321static int
3322flow_action_supported(struct flow_action *flow_action,
3323 struct netlink_ext_ack *extack)
3324{
3325 if (!flow_action_has_entries(flow_action)) {
3326 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3327 return -EINVAL;
3328 }
3329
3330 if (!flow_action_hw_stats_check(flow_action, extack,
3331 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3332 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
3333 return -EOPNOTSUPP;
3334 }
3335
3336 return 0;
3337}
3338
d9581e2f
RD		 3339static int
3340parse_tc_nic_actions(struct mlx5e_priv *priv,
3341 struct flow_action *flow_action,
3342 struct mlx5e_tc_flow *flow,
3343 struct netlink_ext_ack *extack)
e3a2b7ed 3344{
fad54790 3345 struct mlx5e_tc_act_parse_state *parse_state;
c6cfe113 3346 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3347 struct mlx5_flow_attr *attr = flow->attr;
e36db1ee 3348 struct pedit_headers_action *hdrs;
8333d53e 3349 int err;
e3a2b7ed 3350
df990477
RD		 3351 err = flow_action_supported(flow_action, extack);
3352 if (err)
3353 return err;
319a1d19 3354
fad54790 3355 attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3356 parse_attr = attr->parse_attr;
fad54790
RD		 3357 parse_state = &parse_attr->parse_state;
3358 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3359 parse_state->ct_priv = get_ct_priv(priv);
e36db1ee 3360 hdrs = parse_state->hdrs;
e3a2b7ed 3361
8333d53e
RD		 3362 err = parse_tc_actions(parse_state, flow_action);
3363 if (err)
3364 return err;
e3a2b7ed 3365
d9581e2f
RD		 3366 err = actions_prepare_mod_hdr_actions(priv, flow, attr, hdrs, extack);
3367 if (err)
3368 return err;
3369
73867881 3370 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3371 return -EOPNOTSUPP;
3372
e3a2b7ed
AV		 3373 return 0;
3374}
3375
32134847 3376static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3377 struct net_device *peer_netdev)
3378{
3379 struct mlx5e_priv *peer_priv;
3380
3381 peer_priv = netdev_priv(peer_netdev);
3382
3383 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3384 mlx5e_eswitch_vf_rep(priv->netdev) &&
3385 mlx5e_eswitch_vf_rep(peer_netdev) &&
ab3f3d5e 3386 mlx5e_same_hw_devs(priv, peer_priv));
d34eb2fc
OG		 3387}
3388
32134847
MD		 3389static bool same_hw_reps(struct mlx5e_priv *priv,
3390 struct net_device *peer_netdev)
3391{
3392 struct mlx5e_priv *peer_priv;
3393
3394 peer_priv = netdev_priv(peer_netdev);
3395
3396 return mlx5e_eswitch_rep(priv->netdev) &&
3397 mlx5e_eswitch_rep(peer_netdev) &&
ab3f3d5e 3398 mlx5e_same_hw_devs(priv, peer_priv);
32134847
MD		 3399}
3400
3401static bool is_lag_dev(struct mlx5e_priv *priv,
3402 struct net_device *peer_netdev)
3403{
3404 return ((mlx5_lag_is_sriov(priv->mdev) ||
3405 mlx5_lag_is_multipath(priv->mdev)) &&
3406 same_hw_reps(priv, peer_netdev));
3407}
3408
f6dc1264
PB		 3409bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3410 struct net_device *out_dev)
3411{
32134847
MD		 3412 if (is_merged_eswitch_vfs(priv, out_dev))
3413 return true;
3414
3415 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3416 return true;
3417
3418 return mlx5e_eswitch_rep(out_dev) &&
32134847 3419 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3420}
3421
27484f71
AL		 3422int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
3423 struct mlx5_flow_attr *attr,
3424 int ifindex,
3425 enum mlx5e_tc_int_port_type type,
3426 u32 *action,
3427 int out_index)
3428{
3429 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
3430 struct mlx5e_tc_int_port_priv *int_port_priv;
3431 struct mlx5e_tc_flow_parse_attr *parse_attr;
3432 struct mlx5e_tc_int_port *dest_int_port;
3433 int err;
3434
3435 parse_attr = attr->parse_attr;
3436 int_port_priv = mlx5e_get_int_port_priv(priv);
3437
3438 dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
3439 if (IS_ERR(dest_int_port))
3440 return PTR_ERR(dest_int_port);
3441
3442 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
3443 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
3444 mlx5e_tc_int_port_get_metadata(dest_int_port));
3445 if (err) {
3446 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
3447 return err;
3448 }
3449
3450 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3451
3452 esw_attr->dest_int_port = dest_int_port;
3453 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
3454
3455 /* Forward to root fdb for matching against the new source vport */
3456 attr->dest_chain = 0;
3457
3458 return 0;
3459}
3460
8333d53e
RD		 3461static int
3462parse_tc_fdb_actions(struct mlx5e_priv *priv,
3463 struct flow_action *flow_action,
3464 struct mlx5e_tc_flow *flow,
3465 struct netlink_ext_ack *extack)
03a9d11e 3466{
fad54790 3467 struct mlx5e_tc_act_parse_state *parse_state;
c620b772 3468 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3469 struct mlx5_flow_attr *attr = flow->attr;
c620b772 3470 struct mlx5_esw_flow_attr *esw_attr;
e36db1ee 3471 struct pedit_headers_action *hdrs;
8333d53e 3472 int err;
03a9d11e 3473
df990477
RD		 3474 err = flow_action_supported(flow_action, extack);
3475 if (err)
3476 return err;
319a1d19 3477
c620b772
AL		 3478 esw_attr = attr->esw_attr;
3479 parse_attr = attr->parse_attr;
fad54790
RD		 3480 parse_state = &parse_attr->parse_state;
3481 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3482 parse_state->ct_priv = get_ct_priv(priv);
e36db1ee 3483 hdrs = parse_state->hdrs;
c620b772 3484
8333d53e
RD		 3485 err = parse_tc_actions(parse_state, flow_action);
3486 if (err)
3487 return err;
bdd66ac0 3488
166f431e
AL		 3489 /* Forward to/from internal port can only have 1 dest */
3490 if ((netif_is_ovs_master(parse_attr->filter_dev) || esw_attr->dest_int_port) &&
3491 esw_attr->out_count > 1) {
27484f71 3492 NL_SET_ERR_MSG_MOD(extack,
166f431e 3493 "Rules with internal port can have only one destination");
27484f71
AL		 3494 return -EOPNOTSUPP;
3495 }
3496
d9581e2f
RD		 3497 err = actions_prepare_mod_hdr_actions(priv, flow, attr, hdrs, extack);
3498 if (err)
3499 return err;
3500
73867881 3501 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3502 return -EOPNOTSUPP;
3503
31c8eba5 3504 return 0;
03a9d11e
OG		 3505}
3506
226f2ca3 3507static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3508{
226f2ca3 3509 unsigned long __flow_flags = 0;
60bd4af8 3510
226f2ca3
VB		 3511 if (flags & MLX5_TC_FLAG(INGRESS))
3512 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3513 if (flags & MLX5_TC_FLAG(EGRESS))
3514 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3515
226f2ca3
VB		 3516 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3517 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3518 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3519 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3520 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3521 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3522
60bd4af8
OG		 3523 *flow_flags = __flow_flags;
3524}
3525
05866c82
OG		 3526static const struct rhashtable_params tc_ht_params = {
3527 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3528 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3529 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3530 .automatic_shrinking = true,
3531};
3532
226f2ca3
VB		 3533static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3534 unsigned long flags)
05866c82 3535{
655dc3d2
OG		 3536 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3537 struct mlx5e_rep_priv *uplink_rpriv;
3538
226f2ca3 3539 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3540 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3541 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3542 } else /* NIC offload */
655dc3d2 3543 return &priv->fs.tc.ht;
05866c82
OG		 3544}
3545
04de7dda
RD		 3546static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3547{
c620b772
AL		 3548 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3549 struct mlx5_flow_attr *attr = flow->attr;
3550 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3551 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3552 bool act_is_encap = !!(attr->action &
3553 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 3554 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 3555 MLX5_DEVCOM_ESW_OFFLOADS);
3556
10fbb1cd
RD		 3557 if (!esw_paired)
3558 return false;
3559
c620b772
AL		 3560 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
3561 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 3562 (is_rep_ingress || act_is_encap))
3563 return true;
3564
3565 return false;
04de7dda
RD		 3566}
3567
c620b772
AL		 3568struct mlx5_flow_attr *
3569mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
3570{
3571 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
3572 sizeof(struct mlx5_esw_flow_attr) :
3573 sizeof(struct mlx5_nic_flow_attr);
3574 struct mlx5_flow_attr *attr;
3575
3576 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
3577}
3578
a88780a9
RD		 3579static int
3580mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3581 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3582 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3583 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3584{
17091853 3585 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3586 struct mlx5_flow_attr *attr;
3bc4b7bf 3587 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 3588 int err = -ENOMEM;
3589 int out_index;
e3a2b7ed 3590
c620b772 3591 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 3592 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 3593 if (!parse_attr || !flow)
3594 goto err_free;
c620b772
AL		 3595
3596 flow->flags = flow_flags;
3597 flow->cookie = f->cookie;
3598 flow->priv = priv;
3599
e36db1ee 3600 attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
ff7ea04a 3601 if (!attr)
e3a2b7ed 3602 goto err_free;
ff7ea04a 3603
c620b772 3604 flow->attr = attr;
e3a2b7ed 3605
5a7e5bcb
VB		 3606 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3607 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 3608 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 3609 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 3610 refcount_set(&flow->refcnt, 1);
95435ad7 3611 init_completion(&flow->init_done);
362980ea 3612 init_completion(&flow->del_hw_done);
e3a2b7ed 3613
a88780a9
RD		 3614 *__flow = flow;
3615 *__parse_attr = parse_attr;
3616
3617 return 0;
3618
3619err_free:
3620 kfree(flow);
3621 kvfree(parse_attr);
3622 return err;
3623}
3624
c7569097
AL		 3625static void
3626mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
3627 struct mlx5e_tc_flow_parse_attr *parse_attr,
3628 struct flow_cls_offload *f)
3629{
3630 attr->parse_attr = parse_attr;
3631 attr->chain = f->common.chain_index;
3632 attr->prio = f->common.prio;
3633}
3634
988ab9c7 3635static void
c620b772 3636mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 3637 struct mlx5e_priv *priv,
3638 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3639 struct flow_cls_offload *f,
988ab9c7
TZ		 3640 struct mlx5_eswitch_rep *in_rep,
3641 struct mlx5_core_dev *in_mdev)
3642{
3643 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3644 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 3645
c7569097 3646 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 3647
3648 esw_attr->in_rep = in_rep;
3649 esw_attr->in_mdev = in_mdev;
3650
3651 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3652 MLX5_COUNTER_SOURCE_ESWITCH)
3653 esw_attr->counter_dev = in_mdev;
3654 else
3655 esw_attr->counter_dev = priv->mdev;
3656}
3657
71129676 3658static struct mlx5e_tc_flow *
04de7dda 3659__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3660 struct flow_cls_offload *f,
226f2ca3 3661 unsigned long flow_flags,
04de7dda
RD		 3662 struct net_device *filter_dev,
3663 struct mlx5_eswitch_rep *in_rep,
71129676 3664 struct mlx5_core_dev *in_mdev)
a88780a9 3665{
f9e30088 3666 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3667 struct netlink_ext_ack *extack = f->common.extack;
3668 struct mlx5e_tc_flow_parse_attr *parse_attr;
3669 struct mlx5e_tc_flow *flow;
3670 int attr_size, err;
e3a2b7ed 3671
226f2ca3 3672 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3673 attr_size = sizeof(struct mlx5_esw_flow_attr);
3674 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3675 &parse_attr, &flow);
3676 if (err)
3677 goto out;
988ab9c7 3678
d11afc26 3679 parse_attr->filter_dev = filter_dev;
c620b772 3680 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 3681 priv, parse_attr,
3682 f, in_rep, in_mdev);
3683
54c177ca
OS		 3684 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3685 f, filter_dev);
d11afc26
OS		 3686 if (err)
3687 goto err_free;
a88780a9 3688
7e36feeb 3689 /* actions validation depends on parsing the ct matches first */
aedd133d 3690 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 3691 &flow->attr->ct_attr, extack);
a88780a9
RD		 3692 if (err)
3693 goto err_free;
3694
d4bb0531
RD		 3695 /* always set IP version for indirect table handling */
3696 flow->attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3697
70f8019e 3698 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 3699 if (err)
3700 goto err_free;
3701
7040632d 3702 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3703 complete_all(&flow->init_done);
ef06c9ee
RD		 3704 if (err) {
3705 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3706 goto err_free;
3707
b4a23329 3708 add_unready_flow(flow);
ef06c9ee 3709 }
e3a2b7ed 3710
71129676 3711 return flow;
a88780a9
RD		 3712
3713err_free:
5a7e5bcb 3714 mlx5e_flow_put(priv, flow);
a88780a9 3715out:
71129676 3716 return ERR_PTR(err);
a88780a9
RD		 3717}
3718
f9e30088 3719static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3720 struct mlx5e_tc_flow *flow,
226f2ca3 3721 unsigned long flow_flags)
04de7dda
RD		 3722{
3723 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3724 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 3725 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 3726 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3727 struct mlx5e_tc_flow_parse_attr *parse_attr;
3728 struct mlx5e_rep_priv *peer_urpriv;
3729 struct mlx5e_tc_flow *peer_flow;
3730 struct mlx5_core_dev *in_mdev;
3731 int err = 0;
3732
3733 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3734 if (!peer_esw)
3735 return -ENODEV;
3736
3737 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3738 peer_priv = netdev_priv(peer_urpriv->netdev);
3739
3740 /* in_mdev is assigned of which the packet originated from.
3741 * So packets redirected to uplink use the same mdev of the
3742 * original flow and packets redirected from uplink use the
3743 * peer mdev.
3744 */
c620b772 3745 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3746 in_mdev = peer_priv->mdev;
3747 else
3748 in_mdev = priv->mdev;
3749
c620b772 3750 parse_attr = flow->attr->parse_attr;
95dc1902 3751 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 3752 parse_attr->filter_dev,
c620b772 3753 attr->in_rep, in_mdev);
71129676
JG		 3754 if (IS_ERR(peer_flow)) {
3755 err = PTR_ERR(peer_flow);
04de7dda 3756 goto out;
71129676 3757 }
04de7dda
RD		 3758
3759 flow->peer_flow = peer_flow;
226f2ca3 3760 flow_flag_set(flow, DUP);
04de7dda
RD		 3761 mutex_lock(&esw->offloads.peer_mutex);
3762 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3763 mutex_unlock(&esw->offloads.peer_mutex);
3764
3765out:
3766 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3767 return err;
3768}
3769
3770static int
3771mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3772 struct flow_cls_offload *f,
226f2ca3 3773 unsigned long flow_flags,
04de7dda
RD		 3774 struct net_device *filter_dev,
3775 struct mlx5e_tc_flow **__flow)
3776{
3777 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3778 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3779 struct mlx5_core_dev *in_mdev = priv->mdev;
3780 struct mlx5e_tc_flow *flow;
3781 int err;
3782
71129676
JG		 3783 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3784 in_mdev);
3785 if (IS_ERR(flow))
3786 return PTR_ERR(flow);
04de7dda
RD		 3787
3788 if (is_peer_flow_needed(flow)) {
95dc1902 3789 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3790 if (err) {
3791 mlx5e_tc_del_fdb_flow(priv, flow);
3792 goto out;
3793 }
3794 }
3795
3796 *__flow = flow;
3797
3798 return 0;
3799
3800out:
3801 return err;
3802}
3803
a88780a9
RD		 3804static int
3805mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3806 struct flow_cls_offload *f,
226f2ca3 3807 unsigned long flow_flags,
d11afc26 3808 struct net_device *filter_dev,
a88780a9
RD		 3809 struct mlx5e_tc_flow **__flow)
3810{
f9e30088 3811 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3812 struct netlink_ext_ack *extack = f->common.extack;
3813 struct mlx5e_tc_flow_parse_attr *parse_attr;
3814 struct mlx5e_tc_flow *flow;
3815 int attr_size, err;
3816
c7569097
AL		 3817 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
3818 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3819 return -EOPNOTSUPP;
3820 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 3821 return -EOPNOTSUPP;
c7569097 3822 }
bf07aa73 3823
226f2ca3 3824 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3825 attr_size = sizeof(struct mlx5_nic_flow_attr);
3826 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3827 &parse_attr, &flow);
3828 if (err)
3829 goto out;
3830
d11afc26 3831 parse_attr->filter_dev = filter_dev;
c7569097
AL		 3832 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
3833
54c177ca
OS		 3834 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3835 f, filter_dev);
d11afc26
OS		 3836 if (err)
3837 goto err_free;
3838
aedd133d
AL		 3839 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
3840 &flow->attr->ct_attr, extack);
3841 if (err)
3842 goto err_free;
3843
c6cfe113 3844 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3845 if (err)
3846 goto err_free;
3847
c6cfe113 3848 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 3849 if (err)
3850 goto err_free;
3851
226f2ca3 3852 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3853 *__flow = flow;
3854
3855 return 0;
e3a2b7ed 3856
e3a2b7ed 3857err_free:
8914add2 3858 flow_flag_set(flow, FAILED);
2c0e5cf5 3859 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
5a7e5bcb 3860 mlx5e_flow_put(priv, flow);
a88780a9
RD		 3861out:
3862 return err;
3863}
3864
3865static int
3866mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3867 struct flow_cls_offload *f,
226f2ca3 3868 unsigned long flags,
d11afc26 3869 struct net_device *filter_dev,
a88780a9
RD		 3870 struct mlx5e_tc_flow **flow)
3871{
3872 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3873 unsigned long flow_flags;
a88780a9
RD		 3874 int err;
3875
3876 get_flags(flags, &flow_flags);
3877
bf07aa73
PB		 3878 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3879 return -EOPNOTSUPP;
3880
f6455de0 3881 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3882 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3883 filter_dev, flow);
a88780a9 3884 else
d11afc26
OS		 3885 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3886 filter_dev, flow);
a88780a9
RD		 3887
3888 return err;
3889}
3890
553f9328
VP		 3891static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
3892 struct mlx5e_rep_priv *rpriv)
3893{
3894 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 3895 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
3896 * function is called from NIC mode.
553f9328 3897 */
2fb15e72 3898 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 3899}
3900
71d82d2a 3901int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3902 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3903{
3904 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3905 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 3906 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 3907 struct mlx5e_tc_flow *flow;
3908 int err = 0;
3909
7dc84de9
RD		 3910 if (!mlx5_esw_hold(priv->mdev))
3911 return -EAGAIN;
3912
3913 mlx5_esw_get(priv->mdev);
3914
c5d326b2
VB		 3915 rcu_read_lock();
3916 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 3917 if (flow) {
553f9328
VP		 3918 /* Same flow rule offloaded to non-uplink representor sharing tc block,
3919 * just return 0.
3920 */
3921 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 3922 goto rcu_unlock;
553f9328 3923
a88780a9
RD		 3924 NL_SET_ERR_MSG_MOD(extack,
3925 "flow cookie already exists, ignoring");
3926 netdev_warn_once(priv->netdev,
3927 "flow cookie %lx already exists, ignoring\n",
3928 f->cookie);
0e1c1a2f 3929 err = -EEXIST;
c1aea9e1 3930 goto rcu_unlock;
a88780a9 3931 }
c1aea9e1
VB		 3932rcu_unlock:
3933 rcu_read_unlock();
3934 if (flow)
3935 goto out;
a88780a9 3936
7a978759 3937 trace_mlx5e_configure_flower(f);
d11afc26 3938 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3939 if (err)
3940 goto out;
3941
553f9328
VP		 3942 /* Flow rule offloaded to non-uplink representor sharing tc block,
3943 * set the flow's owner dev.
3944 */
3945 if (is_flow_rule_duplicate_allowed(dev, rpriv))
3946 flow->orig_dev = dev;
3947
c5d326b2 3948 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3949 if (err)
3950 goto err_free;
3951
7dc84de9 3952 mlx5_esw_release(priv->mdev);
a88780a9
RD		 3953 return 0;
3954
3955err_free:
5a7e5bcb 3956 mlx5e_flow_put(priv, flow);
a88780a9 3957out:
7dc84de9
RD		 3958 mlx5_esw_put(priv->mdev);
3959 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 3960 return err;
3961}
3962
8f8ae895
OG		 3963static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3964{
226f2ca3
VB		 3965 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3966 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3967
226f2ca3
VB		 3968 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3969 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3970}
3971
71d82d2a 3972int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3973 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3974{
d9ee0491 3975 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3976 struct mlx5e_tc_flow *flow;
c5d326b2 3977 int err;
e3a2b7ed 3978
c5d326b2 3979 rcu_read_lock();
ab818362 3980 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3981 if (!flow || !same_flow_direction(flow, flags)) {
3982 err = -EINVAL;
3983 goto errout;
3984 }
e3a2b7ed 3985
c5d326b2
VB		 3986 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3987 * set.
3988 */
3989 if (flow_flag_test_and_set(flow, DELETED)) {
3990 err = -EINVAL;
3991 goto errout;
3992 }
05866c82 3993 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 3994 rcu_read_unlock();
e3a2b7ed 3995
7a978759 3996 trace_mlx5e_delete_flower(f);
5a7e5bcb 3997 mlx5e_flow_put(priv, flow);
e3a2b7ed 3998
7dc84de9 3999 mlx5_esw_put(priv->mdev);
e3a2b7ed 4000 return 0;
c5d326b2
VB		 4001
4002errout:
4003 rcu_read_unlock();
4004 return err;
e3a2b7ed
AV		 4005}
4006
71d82d2a 4007int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4008 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4009{
04de7dda 4010 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4011 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4012 struct mlx5_eswitch *peer_esw;
aad7e08d 4013 struct mlx5e_tc_flow *flow;
aad7e08d 4014 struct mlx5_fc *counter;
316d5f72
RD		 4015 u64 lastuse = 0;
4016 u64 packets = 0;
4017 u64 bytes = 0;
5a7e5bcb 4018 int err = 0;
aad7e08d 4019
c5d326b2
VB		 4020 rcu_read_lock();
4021 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4022 tc_ht_params));
4023 rcu_read_unlock();
5a7e5bcb
VB		 4024 if (IS_ERR(flow))
4025 return PTR_ERR(flow);
4026
4027 if (!same_flow_direction(flow, flags)) {
4028 err = -EINVAL;
4029 goto errout;
4030 }
aad7e08d 4031
4c3844d9 4032 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4033 counter = mlx5e_tc_get_counter(flow);
4034 if (!counter)
5a7e5bcb 4035 goto errout;
aad7e08d 4036
316d5f72
RD		 4037 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4038 }
aad7e08d 4039
316d5f72
RD		 4040 /* Under multipath it's possible for one rule to be currently
4041 * un-offloaded while the other rule is offloaded.
4042 */
04de7dda
RD		 4043 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4044 if (!peer_esw)
4045 goto out;
4046
226f2ca3
VB		 4047 if (flow_flag_test(flow, DUP) &&
4048 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4049 u64 bytes2;
4050 u64 packets2;
4051 u64 lastuse2;
4052
4053 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4054 if (!counter)
4055 goto no_peer_counter;
04de7dda
RD		 4056 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4057
4058 bytes += bytes2;
4059 packets += packets2;
4060 lastuse = max_t(u64, lastuse, lastuse2);
4061 }
4062
316d5f72 4063no_peer_counter:
04de7dda 4064 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4065out:
4b61d3e8 4066 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4067 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4068 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4069errout:
4070 mlx5e_flow_put(priv, flow);
4071 return err;
aad7e08d
AV		 4072}
4073
1fe3e316 4074static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4075 struct netlink_ext_ack *extack)
4076{
4077 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4078 struct mlx5_eswitch *esw;
1fe3e316 4079 u32 rate_mbps = 0;
fcb64c0f 4080 u16 vport_num;
fcb64c0f
EC		 4081 int err;
4082
e401a184
EC		 4083 vport_num = rpriv->rep->vport;
4084 if (vport_num >= MLX5_VPORT_ECPF) {
4085 NL_SET_ERR_MSG_MOD(extack,
4086 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4087 return -EOPNOTSUPP;
4088 }
4089
fcb64c0f
EC		 4090 esw = priv->mdev->priv.eswitch;
4091 /* rate is given in bytes/sec.
4092 * First convert to bits/sec and then round to the nearest mbit/secs.
4093 * mbit means million bits.
4094 * Moreover, if rate is non zero we choose to configure to a minimum of
4095 * 1 mbit/sec.
4096 */
1fe3e316
PP		 4097 if (rate) {
4098 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4099 do_div(rate, 1000000);
4100 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4101 }
4102
2d116e3e 4103 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4104 if (err)
4105 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4106
4107 return err;
4108}
4109
4110static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4111 struct flow_action *flow_action,
4112 struct netlink_ext_ack *extack)
4113{
4114 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4115 const struct flow_action_entry *act;
4116 int err;
4117 int i;
4118
4119 if (!flow_action_has_entries(flow_action)) {
4120 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4121 return -EINVAL;
4122 }
4123
4124 if (!flow_offload_has_one_action(flow_action)) {
4125 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4126 return -EOPNOTSUPP;
4127 }
4128
0885ae1a
A		 4129 if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4130 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 4131 return -EOPNOTSUPP;
0885ae1a 4132 }
319a1d19 4133
fcb64c0f
EC		 4134 flow_action_for_each(i, act, flow_action) {
4135 switch (act->id) {
4136 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4137 if (act->police.rate_pkt_ps) {
4138 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4139 return -EOPNOTSUPP;
4140 }
fcb64c0f
EC		 4141 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4142 if (err)
4143 return err;
4144
4145 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4146 break;
4147 default:
4148 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4149 return -EOPNOTSUPP;
4150 }
4151 }
4152
4153 return 0;
4154}
4155
4156int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4157 struct tc_cls_matchall_offload *ma)
4158{
4159 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4160
7b83355f 4161 if (ma->common.prio != 1) {
fcb64c0f
EC		 4162 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4163 return -EINVAL;
4164 }
4165
4166 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4167}
4168
4169int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4170 struct tc_cls_matchall_offload *ma)
4171{
4172 struct netlink_ext_ack *extack = ma->common.extack;
4173
4174 return apply_police_params(priv, 0, extack);
4175}
4176
4177void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4178 struct tc_cls_matchall_offload *ma)
4179{
4180 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4181 struct rtnl_link_stats64 cur_stats;
4182 u64 dbytes;
4183 u64 dpkts;
4184
4185 cur_stats = priv->stats.vf_vport;
4186 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4187 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4188 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4189 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4190 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4191}
4192
4d8fcf21
AH		 4193static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4194 struct mlx5e_priv *peer_priv)
4195{
4196 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4197 struct mlx5e_hairpin_entry *hpe, *tmp;
4198 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4199 u16 peer_vhca_id;
4200 int bkt;
4201
ab3f3d5e 4202 if (!mlx5e_same_hw_devs(priv, peer_priv))
4d8fcf21
AH		 4203 return;
4204
4205 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4206
b32accda 4207 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4208 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4209 if (refcount_inc_not_zero(&hpe->refcnt))
4210 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4211 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4212
4213 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4214 wait_for_completion(&hpe->res_ready);
4215 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4216 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4217
4218 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4219 }
4220}
4221
4222static int mlx5e_tc_netdev_event(struct notifier_block *this,
4223 unsigned long event, void *ptr)
4224{
4225 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4226 struct mlx5e_flow_steering *fs;
4227 struct mlx5e_priv *peer_priv;
4228 struct mlx5e_tc_table *tc;
4229 struct mlx5e_priv *priv;
4230
4231 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4232 event != NETDEV_UNREGISTER ||
4233 ndev->reg_state == NETREG_REGISTERED)
4234 return NOTIFY_DONE;
4235
4236 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4237 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4238 priv = container_of(fs, struct mlx5e_priv, fs);
4239 peer_priv = netdev_priv(ndev);
4240 if (priv == peer_priv ||
4241 !(priv->netdev->features & NETIF_F_HW_TC))
4242 return NOTIFY_DONE;
4243
4244 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4245
4246 return NOTIFY_DONE;
4247}
4248
6a064674
AL		 4249static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4250{
4251 int tc_grp_size, tc_tbl_size;
4252 u32 max_flow_counter;
4253
4254 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4255 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4256
4257 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4258
4259 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4260 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4261
4262 return tc_tbl_size;
4263}
4264
655dc3d2 4265int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4266{
acff797c 4267 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4268 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4269 struct mapping_ctx *chains_mapping;
6a064674 4270 struct mlx5_chains_attr attr = {};
2198b932 4271 u64 mapping_id;
4d8fcf21 4272 int err;
e8f887ac 4273
b2fdf3d0 4274 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4275 mutex_init(&tc->t_lock);
b32accda 4276 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4277 hash_init(tc->hairpin_tbl);
11c9c548 4278
4d8fcf21
AH		 4279 err = rhashtable_init(&tc->ht, &tc_ht_params);
4280 if (err)
4281 return err;
4282
9ba33339
RD		 4283 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4284
2198b932
RD		 4285 mapping_id = mlx5_query_nic_system_image_guid(dev);
4286
4287 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4288 sizeof(struct mlx5_mapped_obj),
4289 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4290
c9355682
CM		 4291 if (IS_ERR(chains_mapping)) {
4292 err = PTR_ERR(chains_mapping);
4293 goto err_mapping;
4294 }
4295 tc->mapping = chains_mapping;
4296
4297 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4298 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4299 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4300 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4301 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4302 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4303 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4304 attr.mapping = chains_mapping;
6a064674
AL		 4305
4306 tc->chains = mlx5_chains_create(dev, &attr);
4307 if (IS_ERR(tc->chains)) {
4308 err = PTR_ERR(tc->chains);
4309 goto err_chains;
4310 }
4311
f0da4daa 4312 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4313 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4314 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4315
4d8fcf21 4316 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4317 err = register_netdevice_notifier_dev_net(priv->netdev,
4318 &tc->netdevice_nb,
4319 &tc->netdevice_nn);
4320 if (err) {
4d8fcf21
AH		 4321 tc->netdevice_nb.notifier_call = NULL;
4322 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4323 goto err_reg;
4d8fcf21
AH		 4324 }
4325
6a064674
AL		 4326 return 0;
4327
4328err_reg:
aedd133d 4329 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4330 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4331 mlx5_chains_destroy(tc->chains);
4332err_chains:
c9355682
CM		 4333 mapping_destroy(chains_mapping);
4334err_mapping:
6a064674 4335 rhashtable_destroy(&tc->ht);
4d8fcf21 4336 return err;
e8f887ac
AV		 4337}
4338
4339static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4340{
4341 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4342 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4343
961e8979 4344 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4345 kfree(flow);
4346}
4347
655dc3d2 4348void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4349{
acff797c 4350 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4351
4d8fcf21 4352 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4353 unregister_netdevice_notifier_dev_net(priv->netdev,
4354 &tc->netdevice_nb,
4355 &tc->netdevice_nn);
4d8fcf21 4356
b2fdf3d0 4357 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4358 mutex_destroy(&tc->hairpin_tbl_lock);
4359
6a064674 4360 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4361
acff797c 4362 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4363 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4364 tc->t = NULL;
e8f887ac 4365 }
b6fac0b4 4366 mutex_destroy(&tc->t_lock);
6a064674 4367
aedd133d 4368 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4369 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4370 mapping_destroy(tc->mapping);
6a064674 4371 mlx5_chains_destroy(tc->chains);
e8f887ac 4372}
655dc3d2
OG		 4373
4374int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
4375{
d7a42ad0 4376 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 4377 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 4378 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4379 struct mapping_ctx *mapping;
aedd133d
AL		 4380 struct mlx5_eswitch *esw;
4381 struct mlx5e_priv *priv;
2198b932 4382 u64 mapping_id;
aedd133d 4383 int err = 0;
0a7fcb78
PB		 4384
4385 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 4386 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4387 priv = netdev_priv(rpriv->netdev);
4388 esw = priv->mdev->priv.eswitch;
0a7fcb78 4389
f0da4daa
CM		 4390 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
4391 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 4392 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4393 esw_chains(esw),
4394 &esw->offloads.mod_hdr,
f0da4daa
CM		 4395 MLX5_FLOW_NAMESPACE_FDB,
4396 uplink_priv->post_act);
4c3844d9 4397
4f4edcc2
AL		 4398 uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
4399
2741f223 4400 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 4401
2198b932
RD		 4402 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
4403
4404 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
4405 sizeof(struct tunnel_match_key),
4406 TUNNEL_INFO_BITS_MASK, true);
4407
0a7fcb78
PB		 4408 if (IS_ERR(mapping)) {
4409 err = PTR_ERR(mapping);
4410 goto err_tun_mapping;
4411 }
4412 uplink_priv->tunnel_mapping = mapping;
4413
3222efd4
VB		 4414 /* Two last values are reserved for stack devices slow path table mark
4415 * and bridge ingress push mark.
4416 */
2198b932 4417 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
3222efd4 4418 sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
0a7fcb78
PB		 4419 if (IS_ERR(mapping)) {
4420 err = PTR_ERR(mapping);
4421 goto err_enc_opts_mapping;
4422 }
4423 uplink_priv->tunnel_enc_opts_mapping = mapping;
4424
4425 err = rhashtable_init(tc_ht, &tc_ht_params);
4426 if (err)
4427 goto err_ht_init;
4428
9ba33339
RD		 4429 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4430
8914add2 4431 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4432 if (IS_ERR(uplink_priv->encap)) {
4433 err = PTR_ERR(uplink_priv->encap);
8914add2 4434 goto err_register_fib_notifier;
2b6c3c1e 4435 }
8914add2 4436
2b6c3c1e 4437 return 0;
0a7fcb78 4438
8914add2
VB		 4439err_register_fib_notifier:
4440 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 4441err_ht_init:
4442 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4443err_enc_opts_mapping:
4444 mapping_destroy(uplink_priv->tunnel_mapping);
4445err_tun_mapping:
0027d70c 4446 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4447 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4448 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4449 netdev_warn(priv->netdev,
4450 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 4451 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 4452 return err;
655dc3d2
OG		 4453}
4454
4455void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
4456{
0a7fcb78
PB		 4457 struct mlx5_rep_uplink_priv *uplink_priv;
4458
0a7fcb78 4459 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 4460
8914add2
VB		 4461 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4462 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4463
0a7fcb78
PB		 4464 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4465 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4466
0027d70c 4467 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4468 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4469 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 4470 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 4471}
01252a27 4472
226f2ca3 4473int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4474{
d9ee0491 4475 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4476
4477 return atomic_read(&tc_ht->nelems);
4478}
04de7dda
RD		 4479
4480void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4481{
4482 struct mlx5e_tc_flow *flow, *tmp;
4483
4484 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4485 __mlx5e_tc_del_fdb_peer_flow(flow);
4486}
b4a23329
RD		 4487
4488void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4489{
4490 struct mlx5_rep_uplink_priv *rpriv =
4491 container_of(work, struct mlx5_rep_uplink_priv,
4492 reoffload_flows_work);
4493 struct mlx5e_tc_flow *flow, *tmp;
4494
ad86755b 4495 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4496 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4497 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4498 unready_flow_del(flow);
b4a23329 4499 }
ad86755b 4500 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4501}
e2394a61
VB		 4502
4503static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4504 struct flow_cls_offload *cls_flower,
4505 unsigned long flags)
4506{
4507 switch (cls_flower->command) {
4508 case FLOW_CLS_REPLACE:
4509 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4510 flags);
4511 case FLOW_CLS_DESTROY:
4512 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4513 flags);
4514 case FLOW_CLS_STATS:
4515 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4516 flags);
4517 default:
4518 return -EOPNOTSUPP;
4519 }
4520}
4521
4522int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4523 void *cb_priv)
4524{
ec9457a6 4525 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 4526 struct mlx5e_priv *priv = cb_priv;
4527
2ff349c5
RD		 4528 if (!priv->netdev || !netif_device_present(priv->netdev))
4529 return -EOPNOTSUPP;
4530
ec9457a6
RD		 4531 if (mlx5e_is_uplink_rep(priv))
4532 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
4533 else
4534 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
4535
e2394a61
VB		 4536 switch (type) {
4537 case TC_SETUP_CLSFLOWER:
4538 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
4539 default:
4540 return -EOPNOTSUPP;
4541 }
4542}
c7569097
AL		 4543
4544bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
4545 struct sk_buff *skb)
4546{
4547#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 4548 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 4549 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 4550 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 4551 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 4552 struct tc_skb_ext *tc_skb_ext;
4553 int err;
4554
4555 reg_b = be32_to_cpu(cqe->ft_metadata);
4556
4557 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4558
c9355682 4559 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 4560 if (err) {
4561 netdev_dbg(priv->netdev,
4562 "Couldn't find chain for chain tag: %d, err: %d\n",
4563 chain_tag, err);
4564 return false;
4565 }
4566
a91d98a0
CM		 4567 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
4568 chain = mapped_obj.chain;
9453d45e 4569 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 4570 if (WARN_ON(!tc_skb_ext))
4571 return false;
4572
4573 tc_skb_ext->chain = chain;
aedd133d 4574
ed2fe7ba 4575 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 4576 ESW_ZONE_ID_MASK;
aedd133d
AL		 4577
4578 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
4579 zone_restore_id))
4580 return false;
a91d98a0
CM		 4581 } else {
4582 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
4583 return false;
c7569097
AL		 4584 }
4585#endif /* CONFIG_NET_TC_SKB_EXT */
4586
4587 return true;
4588}
Linux 6.x block layer and io_uring tree(s)