projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx5e: Protect hairpin entry flows list with spinlock
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
5a7e5bcb 41#include <linux/refcount.h>
03a9d11e 42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
f6dfb4c3 47#include <net/arp.h>
3616d08b 48#include <net/ipv6_stubs.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
3f6d08d1 53#include "fs_core.h"
2c81bfd5 54#include "en/port.h"
101f4de9 55#include "en/tc_tun.h"
04de7dda 56#include "lib/devcom.h"
9272e3df 57#include "lib/geneve.h"
e8f887ac 58
3bc4b7bf
OG		 59struct mlx5_nic_flow_attr {
60 u32 action;
61 u32 flow_tag;
2f4fe4ca 62 u32 mod_hdr_id;
5c65c564 63 u32 hairpin_tirn;
38aa51c1 64 u8 match_level;
3f6d08d1 65 struct mlx5_flow_table *hairpin_ft;
b8aee822 66 struct mlx5_fc *counter;
3bc4b7bf
OG		 67};
68
226f2ca3 69#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 70
65ba8fb7 71enum {
226f2ca3
VB		 72 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
73 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
74 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
75 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
76 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
77 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
78 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
79 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
80 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
81 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 82 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
65ba8fb7
OG		 83};
84
e4ad91f2
CM		 85#define MLX5E_TC_MAX_SPLITS 1
86
79baaec7
EB		 87/* Helper struct for accessing a struct containing list_head array.
88 * Containing struct
89 * |- Helper array
90 * [0] Helper item 0
91 * |- list_head item 0
92 * |- index (0)
93 * [1] Helper item 1
94 * |- list_head item 1
95 * |- index (1)
96 * To access the containing struct from one of the list_head items:
97 * 1. Get the helper item from the list_head item using
98 * helper item =
99 * container_of(list_head item, helper struct type, list_head field)
100 * 2. Get the contining struct from the helper item and its index in the array:
101 * containing struct =
102 * container_of(helper item, containing struct type, helper field[index])
103 */
104struct encap_flow_item {
105 struct list_head list;
106 int index;
107};
108
e8f887ac
AV		 109struct mlx5e_tc_flow {
110 struct rhash_head node;
655dc3d2 111 struct mlx5e_priv *priv;
e8f887ac 112 u64 cookie;
226f2ca3 113 unsigned long flags;
e4ad91f2 114 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 115 /* Flow can be associated with multiple encap IDs.
116 * The number of encaps is bounded by the number of supported
117 * destinations.
118 */
119 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 120 struct mlx5e_tc_flow *peer_flow;
11c9c548 121 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
e4f9abbd 122 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 123 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 124 struct list_head peer; /* flows with peer flow */
b4a23329 125 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
5a7e5bcb 126 refcount_t refcnt;
c5d326b2 127 struct rcu_head rcu_head;
3bc4b7bf
OG		 128 union {
129 struct mlx5_esw_flow_attr esw_attr[0];
130 struct mlx5_nic_flow_attr nic_attr[0];
131 };
e8f887ac
AV		 132};
133
17091853 134struct mlx5e_tc_flow_parse_attr {
1f6da306 135 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 136 struct net_device *filter_dev;
17091853 137 struct mlx5_flow_spec spec;
d79b6df6 138 int num_mod_hdr_actions;
218d05ce 139 int max_mod_hdr_actions;
d79b6df6 140 void *mod_hdr_actions;
98b66cb1 141 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 142};
143
acff797c 144#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 145#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 146
77ab67b7
OG		 147struct mlx5e_hairpin {
148 struct mlx5_hairpin *pair;
149
150 struct mlx5_core_dev *func_mdev;
3f6d08d1 151 struct mlx5e_priv *func_priv;
77ab67b7
OG		 152 u32 tdn;
153 u32 tirn;
3f6d08d1
OG		 154
155 int num_channels;
156 struct mlx5e_rqt indir_rqt;
157 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
158 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 159};
160
5c65c564
OG		 161struct mlx5e_hairpin_entry {
162 /* a node of a hash table which keeps all the hairpin entries */
163 struct hlist_node hairpin_hlist;
164
73edca73
VB		 165 /* protects flows list */
166 spinlock_t flows_lock;
5c65c564
OG		 167 /* flows sharing the same hairpin */
168 struct list_head flows;
169
d8822868 170 u16 peer_vhca_id;
106be53b 171 u8 prio;
5c65c564 172 struct mlx5e_hairpin *hp;
e4f9abbd 173 refcount_t refcnt;
5c65c564
OG		 174};
175
11c9c548
OG		 176struct mod_hdr_key {
177 int num_actions;
178 void *actions;
179};
180
181struct mlx5e_mod_hdr_entry {
182 /* a node of a hash table which keeps all the mod_hdr entries */
183 struct hlist_node mod_hdr_hlist;
184
185 /* flows sharing the same mod_hdr entry */
186 struct list_head flows;
187
188 struct mod_hdr_key key;
189
190 u32 mod_hdr_id;
191};
192
193#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
194
5a7e5bcb
VB		 195static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
196 struct mlx5e_tc_flow *flow);
197
198static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
199{
200 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
201 return ERR_PTR(-EINVAL);
202 return flow;
203}
204
205static void mlx5e_flow_put(struct mlx5e_priv *priv,
206 struct mlx5e_tc_flow *flow)
207{
208 if (refcount_dec_and_test(&flow->refcnt)) {
209 mlx5e_tc_del_flow(priv, flow);
c5d326b2 210 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 211 }
212}
213
226f2ca3
VB		 214static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
215{
216 /* Complete all memory stores before setting bit. */
217 smp_mb__before_atomic();
218 set_bit(flag, &flow->flags);
219}
220
221#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
222
c5d326b2
VB		 223static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
224 unsigned long flag)
225{
226 /* test_and_set_bit() provides all necessary barriers */
227 return test_and_set_bit(flag, &flow->flags);
228}
229
230#define flow_flag_test_and_set(flow, flag) \
231 __flow_flag_test_and_set(flow, \
232 MLX5E_TC_FLOW_FLAG_##flag)
233
226f2ca3
VB		 234static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
235{
236 /* Complete all memory stores before clearing bit. */
237 smp_mb__before_atomic();
238 clear_bit(flag, &flow->flags);
239}
240
241#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
242 MLX5E_TC_FLOW_FLAG_##flag)
243
244static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
245{
246 bool ret = test_bit(flag, &flow->flags);
247
248 /* Read fields of flow structure only after checking flags. */
249 smp_mb__after_atomic();
250 return ret;
251}
252
253#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
254 MLX5E_TC_FLOW_FLAG_##flag)
255
256static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
257{
258 return flow_flag_test(flow, ESWITCH);
259}
260
261static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
262{
263 return flow_flag_test(flow, OFFLOADED);
264}
265
11c9c548
OG		 266static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
267{
268 return jhash(key->actions,
269 key->num_actions * MLX5_MH_ACT_SZ, 0);
270}
271
272static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
273 struct mod_hdr_key *b)
274{
275 if (a->num_actions != b->num_actions)
276 return 1;
277
278 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
279}
280
281static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
282 struct mlx5e_tc_flow *flow,
283 struct mlx5e_tc_flow_parse_attr *parse_attr)
284{
285 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
286 int num_actions, actions_size, namespace, err;
226f2ca3 287 bool found = false, is_eswitch_flow;
11c9c548
OG		 288 struct mlx5e_mod_hdr_entry *mh;
289 struct mod_hdr_key key;
11c9c548
OG		 290 u32 hash_key;
291
292 num_actions = parse_attr->num_mod_hdr_actions;
293 actions_size = MLX5_MH_ACT_SZ * num_actions;
294
295 key.actions = parse_attr->mod_hdr_actions;
296 key.num_actions = num_actions;
297
298 hash_key = hash_mod_hdr_info(&key);
299
226f2ca3
VB		 300 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
301 if (is_eswitch_flow) {
11c9c548
OG		 302 namespace = MLX5_FLOW_NAMESPACE_FDB;
303 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
304 mod_hdr_hlist, hash_key) {
305 if (!cmp_mod_hdr_info(&mh->key, &key)) {
306 found = true;
307 break;
308 }
309 }
310 } else {
311 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
312 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
313 mod_hdr_hlist, hash_key) {
314 if (!cmp_mod_hdr_info(&mh->key, &key)) {
315 found = true;
316 break;
317 }
318 }
319 }
320
321 if (found)
322 goto attach_flow;
323
324 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
325 if (!mh)
326 return -ENOMEM;
327
328 mh->key.actions = (void *)mh + sizeof(*mh);
329 memcpy(mh->key.actions, key.actions, actions_size);
330 mh->key.num_actions = num_actions;
331 INIT_LIST_HEAD(&mh->flows);
332
333 err = mlx5_modify_header_alloc(priv->mdev, namespace,
334 mh->key.num_actions,
335 mh->key.actions,
336 &mh->mod_hdr_id);
337 if (err)
338 goto out_err;
339
226f2ca3 340 if (is_eswitch_flow)
11c9c548
OG		 341 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
342 else
343 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
344
345attach_flow:
346 list_add(&flow->mod_hdr, &mh->flows);
226f2ca3 347 if (is_eswitch_flow)
11c9c548
OG		 348 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
349 else
350 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
351
352 return 0;
353
354out_err:
355 kfree(mh);
356 return err;
357}
358
359static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
360 struct mlx5e_tc_flow *flow)
361{
362 struct list_head *next = flow->mod_hdr.next;
363
5a7e5bcb
VB		 364 /* flow wasn't fully initialized */
365 if (list_empty(&flow->mod_hdr))
366 return;
367
11c9c548
OG		 368 list_del(&flow->mod_hdr);
369
370 if (list_empty(next)) {
371 struct mlx5e_mod_hdr_entry *mh;
372
373 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
374
375 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
376 hash_del(&mh->mod_hdr_hlist);
377 kfree(mh);
378 }
379}
380
77ab67b7
OG		 381static
382struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
383{
384 struct net_device *netdev;
385 struct mlx5e_priv *priv;
386
387 netdev = __dev_get_by_index(net, ifindex);
388 priv = netdev_priv(netdev);
389 return priv->mdev;
390}
391
392static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
393{
394 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
395 void *tirc;
396 int err;
397
398 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
399 if (err)
400 goto alloc_tdn_err;
401
402 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
403
404 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 405 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 406 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
407
408 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
409 if (err)
410 goto create_tir_err;
411
412 return 0;
413
414create_tir_err:
415 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
416alloc_tdn_err:
417 return err;
418}
419
420static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
421{
422 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
423 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
424}
425
3f6d08d1
OG		 426static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
427{
428 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
429 struct mlx5e_priv *priv = hp->func_priv;
430 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
431
432 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
433 hp->num_channels);
434
435 for (i = 0; i < sz; i++) {
436 ix = i;
bbeb53b8 437 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 438 ix = mlx5e_bits_invert(i, ilog2(sz));
439 ix = indirection_rqt[ix];
440 rqn = hp->pair->rqn[ix];
441 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
442 }
443}
444
445static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
446{
447 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
448 struct mlx5e_priv *priv = hp->func_priv;
449 struct mlx5_core_dev *mdev = priv->mdev;
450 void *rqtc;
451 u32 *in;
452
453 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
454 in = kvzalloc(inlen, GFP_KERNEL);
455 if (!in)
456 return -ENOMEM;
457
458 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
459
460 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
461 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
462
463 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
464
465 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
466 if (!err)
467 hp->indir_rqt.enabled = true;
468
469 kvfree(in);
470 return err;
471}
472
473static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
474{
475 struct mlx5e_priv *priv = hp->func_priv;
476 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
477 int tt, i, err;
478 void *tirc;
479
480 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 481 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
482
3f6d08d1
OG		 483 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
484 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
485
486 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
487 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
488 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 489 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
490
3f6d08d1
OG		 491 err = mlx5_core_create_tir(hp->func_mdev, in,
492 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
493 if (err) {
494 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
495 goto err_destroy_tirs;
496 }
497 }
498 return 0;
499
500err_destroy_tirs:
501 for (i = 0; i < tt; i++)
502 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
503 return err;
504}
505
506static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
507{
508 int tt;
509
510 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
511 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
512}
513
514static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
515 struct ttc_params *ttc_params)
516{
517 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
518 int tt;
519
520 memset(ttc_params, 0, sizeof(*ttc_params));
521
522 ttc_params->any_tt_tirn = hp->tirn;
523
524 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
525 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
526
527 ft_attr->max_fte = MLX5E_NUM_TT;
528 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
529 ft_attr->prio = MLX5E_TC_PRIO;
530}
531
532static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
533{
534 struct mlx5e_priv *priv = hp->func_priv;
535 struct ttc_params ttc_params;
536 int err;
537
538 err = mlx5e_hairpin_create_indirect_rqt(hp);
539 if (err)
540 return err;
541
542 err = mlx5e_hairpin_create_indirect_tirs(hp);
543 if (err)
544 goto err_create_indirect_tirs;
545
546 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
547 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
548 if (err)
549 goto err_create_ttc_table;
550
551 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
552 hp->num_channels, hp->ttc.ft.t->id);
553
554 return 0;
555
556err_create_ttc_table:
557 mlx5e_hairpin_destroy_indirect_tirs(hp);
558err_create_indirect_tirs:
559 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
560
561 return err;
562}
563
564static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
565{
566 struct mlx5e_priv *priv = hp->func_priv;
567
568 mlx5e_destroy_ttc_table(priv, &hp->ttc);
569 mlx5e_hairpin_destroy_indirect_tirs(hp);
570 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
571}
572
77ab67b7
OG		 573static struct mlx5e_hairpin *
574mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
575 int peer_ifindex)
576{
577 struct mlx5_core_dev *func_mdev, *peer_mdev;
578 struct mlx5e_hairpin *hp;
579 struct mlx5_hairpin *pair;
580 int err;
581
582 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
583 if (!hp)
584 return ERR_PTR(-ENOMEM);
585
586 func_mdev = priv->mdev;
587 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
588
589 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
590 if (IS_ERR(pair)) {
591 err = PTR_ERR(pair);
592 goto create_pair_err;
593 }
594 hp->pair = pair;
595 hp->func_mdev = func_mdev;
3f6d08d1
OG		 596 hp->func_priv = priv;
597 hp->num_channels = params->num_channels;
77ab67b7
OG		 598
599 err = mlx5e_hairpin_create_transport(hp);
600 if (err)
601 goto create_transport_err;
602
3f6d08d1
OG		 603 if (hp->num_channels > 1) {
604 err = mlx5e_hairpin_rss_init(hp);
605 if (err)
606 goto rss_init_err;
607 }
608
77ab67b7
OG		 609 return hp;
610
3f6d08d1
OG		 611rss_init_err:
612 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 613create_transport_err:
614 mlx5_core_hairpin_destroy(hp->pair);
615create_pair_err:
616 kfree(hp);
617 return ERR_PTR(err);
618}
619
620static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
621{
3f6d08d1
OG		 622 if (hp->num_channels > 1)
623 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 624 mlx5e_hairpin_destroy_transport(hp);
625 mlx5_core_hairpin_destroy(hp->pair);
626 kvfree(hp);
627}
628
106be53b
OG		 629static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
630{
631 return (peer_vhca_id << 16 | prio);
632}
633
5c65c564 634static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 635 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 636{
637 struct mlx5e_hairpin_entry *hpe;
106be53b 638 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 639
640 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 641 hairpin_hlist, hash_key) {
e4f9abbd
VB		 642 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
643 refcount_inc(&hpe->refcnt);
5c65c564 644 return hpe;
e4f9abbd 645 }
5c65c564
OG		 646 }
647
648 return NULL;
649}
650
e4f9abbd
VB		 651static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
652 struct mlx5e_hairpin_entry *hpe)
653{
654 /* no more hairpin flows for us, release the hairpin pair */
655 if (!refcount_dec_and_test(&hpe->refcnt))
656 return;
657
658 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
659 dev_name(hpe->hp->pair->peer_mdev->device));
660
661 WARN_ON(!list_empty(&hpe->flows));
662 mlx5e_hairpin_destroy(hpe->hp);
663 hash_del(&hpe->hairpin_hlist);
664 kfree(hpe);
665}
666
106be53b
OG		 667#define UNKNOWN_MATCH_PRIO 8
668
669static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 670 struct mlx5_flow_spec *spec, u8 *match_prio,
671 struct netlink_ext_ack *extack)
106be53b
OG		 672{
673 void *headers_c, *headers_v;
674 u8 prio_val, prio_mask = 0;
675 bool vlan_present;
676
677#ifdef CONFIG_MLX5_CORE_EN_DCB
678 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 679 NL_SET_ERR_MSG_MOD(extack,
680 "only PCP trust state supported for hairpin");
106be53b
OG		 681 return -EOPNOTSUPP;
682 }
683#endif
684 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
685 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
686
687 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
688 if (vlan_present) {
689 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
690 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
691 }
692
693 if (!vlan_present || !prio_mask) {
694 prio_val = UNKNOWN_MATCH_PRIO;
695 } else if (prio_mask != 0x7) {
e98bedf5
EB		 696 NL_SET_ERR_MSG_MOD(extack,
697 "masked priority match not supported for hairpin");
106be53b
OG		 698 return -EOPNOTSUPP;
699 }
700
701 *match_prio = prio_val;
702 return 0;
703}
704
5c65c564
OG		 705static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
706 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 707 struct mlx5e_tc_flow_parse_attr *parse_attr,
708 struct netlink_ext_ack *extack)
5c65c564 709{
98b66cb1 710 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 711 struct mlx5_hairpin_params params;
d8822868 712 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 713 struct mlx5e_hairpin_entry *hpe;
714 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 715 u64 link_speed64;
716 u32 link_speed;
106be53b 717 u8 match_prio;
d8822868 718 u16 peer_id;
5c65c564
OG		 719 int err;
720
d8822868
OG		 721 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
722 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 723 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 724 return -EOPNOTSUPP;
725 }
726
d8822868 727 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 728 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
729 extack);
106be53b
OG		 730 if (err)
731 return err;
732 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 733 if (hpe)
734 goto attach_flow;
735
736 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
737 if (!hpe)
738 return -ENOMEM;
739
73edca73 740 spin_lock_init(&hpe->flows_lock);
5c65c564 741 INIT_LIST_HEAD(&hpe->flows);
d8822868 742 hpe->peer_vhca_id = peer_id;
106be53b 743 hpe->prio = match_prio;
e4f9abbd 744 refcount_set(&hpe->refcnt, 1);
5c65c564
OG		 745
746 params.log_data_size = 15;
747 params.log_data_size = min_t(u8, params.log_data_size,
748 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
749 params.log_data_size = max_t(u8, params.log_data_size,
750 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 751
eb9180f7
OG		 752 params.log_num_packets = params.log_data_size -
753 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
754 params.log_num_packets = min_t(u8, params.log_num_packets,
755 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
756
757 params.q_counter = priv->q_counter;
3f6d08d1 758 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 759 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 760 link_speed = max_t(u32, link_speed, 50000);
761 link_speed64 = link_speed;
762 do_div(link_speed64, 50000);
763 params.num_channels = link_speed64;
764
5c65c564
OG		 765 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
766 if (IS_ERR(hp)) {
767 err = PTR_ERR(hp);
768 goto create_hairpin_err;
769 }
770
eb9180f7 771 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 772 hp->tirn, hp->pair->rqn[0],
773 dev_name(hp->pair->peer_mdev->device),
eb9180f7 774 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 775
776 hpe->hp = hp;
106be53b
OG		 777 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
778 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 779
780attach_flow:
3f6d08d1 781 if (hpe->hp->num_channels > 1) {
226f2ca3 782 flow_flag_set(flow, HAIRPIN_RSS);
3f6d08d1
OG		 783 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
784 } else {
785 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
786 }
e4f9abbd 787 flow->hpe = hpe;
73edca73 788 spin_lock(&hpe->flows_lock);
5c65c564 789 list_add(&flow->hairpin, &hpe->flows);
73edca73 790 spin_unlock(&hpe->flows_lock);
3f6d08d1 791
5c65c564
OG		 792 return 0;
793
794create_hairpin_err:
795 kfree(hpe);
796 return err;
797}
798
799static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
800 struct mlx5e_tc_flow *flow)
801{
5a7e5bcb 802 /* flow wasn't fully initialized */
e4f9abbd 803 if (!flow->hpe)
5a7e5bcb
VB		 804 return;
805
73edca73 806 spin_lock(&flow->hpe->flows_lock);
5c65c564 807 list_del(&flow->hairpin);
73edca73
VB		 808 spin_unlock(&flow->hpe->flows_lock);
809
e4f9abbd
VB		 810 mlx5e_hairpin_put(priv, flow->hpe);
811 flow->hpe = NULL;
5c65c564
OG		 812}
813
c83954ab 814static int
74491de9 815mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 816 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 817 struct mlx5e_tc_flow *flow,
818 struct netlink_ext_ack *extack)
e8f887ac 819{
bb0ee7dc 820 struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context;
aa0cbbae 821 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 822 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 823 struct mlx5_flow_destination dest[2] = {};
66958ed9 824 struct mlx5_flow_act flow_act = {
3bc4b7bf 825 .action = attr->action,
60786f09 826 .reformat_id = 0,
bb0ee7dc 827 .flags = FLOW_ACT_NO_APPEND,
66958ed9 828 };
aad7e08d 829 struct mlx5_fc *counter = NULL;
5c65c564 830 int err, dest_ix = 0;
e8f887ac 831
bb0ee7dc
JL		 832 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
833 flow_context->flow_tag = attr->flow_tag;
834
226f2ca3 835 if (flow_flag_test(flow, HAIRPIN)) {
e98bedf5 836 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
5a7e5bcb
VB		 837 if (err)
838 return err;
839
226f2ca3 840 if (flow_flag_test(flow, HAIRPIN_RSS)) {
3f6d08d1
OG		 841 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
842 dest[dest_ix].ft = attr->hairpin_ft;
843 } else {
5c65c564
OG		 844 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
845 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 846 }
847 dest_ix++;
3f6d08d1
OG		 848 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
849 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
850 dest[dest_ix].ft = priv->fs.vlan.ft.t;
851 dest_ix++;
5c65c564 852 }
aad7e08d 853
5c65c564
OG		 854 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
855 counter = mlx5_fc_create(dev, true);
5a7e5bcb
VB		 856 if (IS_ERR(counter))
857 return PTR_ERR(counter);
858
5c65c564 859 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 860 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 861 dest_ix++;
b8aee822 862 attr->counter = counter;
aad7e08d
AV		 863 }
864
2f4fe4ca 865 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 866 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 867 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 868 kfree(parse_attr->mod_hdr_actions);
c83954ab 869 if (err)
5a7e5bcb 870 return err;
2f4fe4ca
OG		 871 }
872
b6fac0b4 873 mutex_lock(&priv->fs.tc.t_lock);
acff797c 874 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 875 int tc_grp_size, tc_tbl_size;
876 u32 max_flow_counter;
877
878 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
879 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
880
881 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
882
883 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
884 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
885
acff797c
MG		 886 priv->fs.tc.t =
887 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
888 MLX5E_TC_PRIO,
21b9c144 889 tc_tbl_size,
acff797c 890 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 891 MLX5E_TC_FT_LEVEL, 0);
acff797c 892 if (IS_ERR(priv->fs.tc.t)) {
b6fac0b4 893 mutex_unlock(&priv->fs.tc.t_lock);
e98bedf5
EB		 894 NL_SET_ERR_MSG_MOD(extack,
895 "Failed to create tc offload table\n");
e8f887ac
AV		 896 netdev_err(priv->netdev,
897 "Failed to create tc offload table\n");
5a7e5bcb 898 return PTR_ERR(priv->fs.tc.t);
e8f887ac 899 }
e8f887ac
AV		 900 }
901
38aa51c1 902 if (attr->match_level != MLX5_MATCH_NONE)
d4a18e16 903 parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 904
c83954ab
RL		 905 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
906 &flow_act, dest, dest_ix);
b6fac0b4 907 mutex_unlock(&priv->fs.tc.t_lock);
aad7e08d 908
5a7e5bcb
VB		 909 if (IS_ERR(flow->rule[0]))
910 return PTR_ERR(flow->rule[0]);
aad7e08d 911
c83954ab 912 return 0;
e8f887ac
AV		 913}
914
d85cdccb
OG		 915static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
916 struct mlx5e_tc_flow *flow)
917{
513f8f7f 918 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 919 struct mlx5_fc *counter = NULL;
920
b8aee822 921 counter = attr->counter;
5a7e5bcb
VB		 922 if (!IS_ERR_OR_NULL(flow->rule[0]))
923 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 924 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 925
b6fac0b4 926 mutex_lock(&priv->fs.tc.t_lock);
226f2ca3 927 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) {
d85cdccb
OG		 928 mlx5_destroy_flow_table(priv->fs.tc.t);
929 priv->fs.tc.t = NULL;
930 }
b6fac0b4 931 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 932
513f8f7f 933 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 934 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 935
226f2ca3 936 if (flow_flag_test(flow, HAIRPIN))
5c65c564 937 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 938}
939
aa0cbbae 940static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 941 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 942
3c37745e 943static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 944 struct mlx5e_tc_flow *flow,
733d4f36
RD		 945 struct net_device *mirred_dev,
946 int out_index,
8c4dc42b 947 struct netlink_ext_ack *extack,
0ad060ee
RD		 948 struct net_device **encap_dev,
949 bool *encap_valid);
3c37745e 950
6d2a3ed0
OG		 951static struct mlx5_flow_handle *
952mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
953 struct mlx5e_tc_flow *flow,
954 struct mlx5_flow_spec *spec,
955 struct mlx5_esw_flow_attr *attr)
956{
957 struct mlx5_flow_handle *rule;
958
959 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
960 if (IS_ERR(rule))
961 return rule;
962
e85e02ba 963 if (attr->split_count) {
6d2a3ed0
OG		 964 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
965 if (IS_ERR(flow->rule[1])) {
966 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
967 return flow->rule[1];
968 }
969 }
970
6d2a3ed0
OG		 971 return rule;
972}
973
974static void
975mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
976 struct mlx5e_tc_flow *flow,
977 struct mlx5_esw_flow_attr *attr)
978{
226f2ca3 979 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 980
e85e02ba 981 if (attr->split_count)
6d2a3ed0
OG		 982 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
983
984 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
985}
986
5dbe906f
PB		 987static struct mlx5_flow_handle *
988mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
989 struct mlx5e_tc_flow *flow,
990 struct mlx5_flow_spec *spec,
991 struct mlx5_esw_flow_attr *slow_attr)
992{
993 struct mlx5_flow_handle *rule;
994
995 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 996 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 997 slow_attr->split_count = 0;
154e62ab 998 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 999
1000 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1001 if (!IS_ERR(rule))
226f2ca3 1002 flow_flag_set(flow, SLOW);
5dbe906f
PB		 1003
1004 return rule;
1005}
1006
1007static void
1008mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1009 struct mlx5e_tc_flow *flow,
1010 struct mlx5_esw_flow_attr *slow_attr)
1011{
1012 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 1013 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 1014 slow_attr->split_count = 0;
154e62ab 1015 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f 1016 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1017 flow_flag_clear(flow, SLOW);
5dbe906f
PB		 1018}
1019
ad86755b
VB		 1020/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1021 * function.
1022 */
1023static void unready_flow_add(struct mlx5e_tc_flow *flow,
1024 struct list_head *unready_flows)
1025{
1026 flow_flag_set(flow, NOT_READY);
1027 list_add_tail(&flow->unready, unready_flows);
1028}
1029
1030/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1031 * function.
1032 */
1033static void unready_flow_del(struct mlx5e_tc_flow *flow)
1034{
1035 list_del(&flow->unready);
1036 flow_flag_clear(flow, NOT_READY);
1037}
1038
b4a23329
RD		 1039static void add_unready_flow(struct mlx5e_tc_flow *flow)
1040{
1041 struct mlx5_rep_uplink_priv *uplink_priv;
1042 struct mlx5e_rep_priv *rpriv;
1043 struct mlx5_eswitch *esw;
1044
1045 esw = flow->priv->mdev->priv.eswitch;
1046 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1047 uplink_priv = &rpriv->uplink_priv;
1048
ad86755b
VB		 1049 mutex_lock(&uplink_priv->unready_flows_lock);
1050 unready_flow_add(flow, &uplink_priv->unready_flows);
1051 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1052}
1053
1054static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1055{
ad86755b
VB		 1056 struct mlx5_rep_uplink_priv *uplink_priv;
1057 struct mlx5e_rep_priv *rpriv;
1058 struct mlx5_eswitch *esw;
1059
1060 esw = flow->priv->mdev->priv.eswitch;
1061 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1062 uplink_priv = &rpriv->uplink_priv;
1063
1064 mutex_lock(&uplink_priv->unready_flows_lock);
1065 unready_flow_del(flow);
1066 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1067}
1068
c83954ab 1069static int
74491de9 1070mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1071 struct mlx5e_tc_flow *flow,
1072 struct netlink_ext_ack *extack)
adb4c123
OG		 1073{
1074 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 1075 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 1076 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
7040632d 1077 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
bf07aa73 1078 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 1079 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 1080 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1081 struct mlx5e_rep_priv *rpriv;
1082 struct mlx5e_priv *out_priv;
0ad060ee
RD		 1083 bool encap_valid = true;
1084 int err = 0;
f493f155 1085 int out_index;
8b32580d 1086
d14f6f2a
OG		 1087 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
1088 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
1089 return -EOPNOTSUPP;
1090 }
bf07aa73
PB		 1091
1092 if (attr->chain > max_chain) {
1093 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
5a7e5bcb 1094 return -EOPNOTSUPP;
bf07aa73
PB		 1095 }
1096
1097 if (attr->prio > max_prio) {
1098 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
5a7e5bcb 1099 return -EOPNOTSUPP;
bf07aa73 1100 }
e52c2802 1101
f493f155 1102 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1103 int mirred_ifindex;
1104
f493f155
EB		 1105 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1106 continue;
1107
7040632d 1108 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1109 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1110 mirred_ifindex);
733d4f36 1111 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1112 extack, &encap_dev, &encap_valid);
1113 if (err)
5a7e5bcb 1114 return err;
0ad060ee 1115
3c37745e
OG		 1116 out_priv = netdev_priv(encap_dev);
1117 rpriv = out_priv->ppriv;
1cc26d74
EB		 1118 attr->dests[out_index].rep = rpriv->rep;
1119 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1120 }
1121
8b32580d 1122 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1123 if (err)
5a7e5bcb 1124 return err;
adb4c123 1125
d7e75a32 1126 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 1127 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 1128 kfree(parse_attr->mod_hdr_actions);
c83954ab 1129 if (err)
5a7e5bcb 1130 return err;
d7e75a32
OG		 1131 }
1132
b8aee822 1133 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 1134 counter = mlx5_fc_create(attr->counter_dev, true);
5a7e5bcb
VB		 1135 if (IS_ERR(counter))
1136 return PTR_ERR(counter);
b8aee822
MB		 1137
1138 attr->counter = counter;
1139 }
1140
0ad060ee
RD		 1141 /* we get here if one of the following takes place:
1142 * (1) there's no error
1143 * (2) there's an encap action and we don't have valid neigh
3c37745e 1144 */
0ad060ee 1145 if (!encap_valid) {
5dbe906f
PB		 1146 /* continue with goto slow path rule instead */
1147 struct mlx5_esw_flow_attr slow_attr;
1148
1149 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1150 } else {
6d2a3ed0 1151 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1152 }
c83954ab 1153
5a7e5bcb
VB		 1154 if (IS_ERR(flow->rule[0]))
1155 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1156 else
1157 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1158
1159 return 0;
aa0cbbae 1160}
d85cdccb 1161
9272e3df
YK		 1162static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1163{
1164 struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec;
1165 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1166 spec->match_value,
1167 misc_parameters_3);
1168 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1169 headers_v,
1170 geneve_tlv_option_0_data);
1171
1172 return !!geneve_tlv_opt_0_data;
1173}
1174
d85cdccb
OG		 1175static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1176 struct mlx5e_tc_flow *flow)
1177{
1178 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1179 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1180 struct mlx5_esw_flow_attr slow_attr;
f493f155 1181 int out_index;
d85cdccb 1182
226f2ca3 1183 if (flow_flag_test(flow, NOT_READY)) {
b4a23329 1184 remove_unready_flow(flow);
ef06c9ee
RD		 1185 kvfree(attr->parse_attr);
1186 return;
1187 }
1188
226f2ca3
VB		 1189 if (mlx5e_is_offloaded_flow(flow)) {
1190 if (flow_flag_test(flow, SLOW))
5dbe906f
PB		 1191 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1192 else
1193 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1194 }
d85cdccb 1195
9272e3df
YK		 1196 if (mlx5_flow_has_geneve_opt(flow))
1197 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1198
513f8f7f 1199 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1200
f493f155 1201 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1202 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1203 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1204 kvfree(attr->parse_attr);
d7e75a32 1205
513f8f7f 1206 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1207 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1208
1209 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1210 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1211}
1212
232c0013
HHZ		 1213void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1214 struct mlx5e_encap_entry *e)
1215{
3c37745e 1216 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1217 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
5a7e5bcb 1218 struct encap_flow_item *efi, *tmp;
6d2a3ed0
OG		 1219 struct mlx5_flow_handle *rule;
1220 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1221 struct mlx5e_tc_flow *flow;
1222 int err;
1223
54c177ca
OS		 1224 err = mlx5_packet_reformat_alloc(priv->mdev,
1225 e->reformat_type,
60786f09 1226 e->encap_size, e->encap_header,
31ca3648 1227 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1228 &e->encap_id);
232c0013
HHZ		 1229 if (err) {
1230 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1231 err);
1232 return;
1233 }
1234 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1235 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1236
5a7e5bcb 1237 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
8c4dc42b
EB		 1238 bool all_flow_encaps_valid = true;
1239 int i;
1240
79baaec7 1241 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1242 if (IS_ERR(mlx5e_flow_get(flow)))
1243 continue;
1244
3c37745e 1245 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1246 spec = &esw_attr->parse_attr->spec;
1247
8c4dc42b
EB		 1248 esw_attr->dests[efi->index].encap_id = e->encap_id;
1249 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1250 /* Flow can be associated with multiple encap entries.
1251 * Before offloading the flow verify that all of them have
1252 * a valid neighbour.
1253 */
1254 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1255 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1256 continue;
1257 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1258 all_flow_encaps_valid = false;
1259 break;
1260 }
1261 }
1262 /* Do not offload flows with unresolved neighbors */
1263 if (!all_flow_encaps_valid)
5a7e5bcb 1264 goto loop_cont;
5dbe906f 1265 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1266 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1267 if (IS_ERR(rule)) {
1268 err = PTR_ERR(rule);
232c0013
HHZ		 1269 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1270 err);
5a7e5bcb 1271 goto loop_cont;
232c0013 1272 }
5dbe906f
PB		 1273
1274 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
6d2a3ed0 1275 flow->rule[0] = rule;
226f2ca3
VB		 1276 /* was unset when slow path rule removed */
1277 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1278
1279loop_cont:
1280 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1281 }
1282}
1283
1284void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1285 struct mlx5e_encap_entry *e)
1286{
3c37745e 1287 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1288 struct mlx5_esw_flow_attr slow_attr;
5a7e5bcb 1289 struct encap_flow_item *efi, *tmp;
5dbe906f
PB		 1290 struct mlx5_flow_handle *rule;
1291 struct mlx5_flow_spec *spec;
232c0013 1292 struct mlx5e_tc_flow *flow;
5dbe906f 1293 int err;
232c0013 1294
5a7e5bcb 1295 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7 1296 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5a7e5bcb
VB		 1297 if (IS_ERR(mlx5e_flow_get(flow)))
1298 continue;
1299
5dbe906f
PB		 1300 spec = &flow->esw_attr->parse_attr->spec;
1301
1302 /* update from encap rule to slow path rule */
1303 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1304 /* mark the flow's encap dest as non-valid */
1305 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1306
1307 if (IS_ERR(rule)) {
1308 err = PTR_ERR(rule);
1309 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1310 err);
5a7e5bcb 1311 goto loop_cont;
5dbe906f
PB		 1312 }
1313
1314 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
5dbe906f 1315 flow->rule[0] = rule;
226f2ca3
VB		 1316 /* was unset when fast path rule removed */
1317 flow_flag_set(flow, OFFLOADED);
5a7e5bcb
VB		 1318
1319loop_cont:
1320 mlx5e_flow_put(priv, flow);
232c0013
HHZ		 1321 }
1322
61c806da
OG		 1323 /* we know that the encap is valid */
1324 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1325 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1326}
1327
b8aee822
MB		 1328static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1329{
226f2ca3 1330 if (mlx5e_is_eswitch_flow(flow))
b8aee822
MB		 1331 return flow->esw_attr->counter;
1332 else
1333 return flow->nic_attr->counter;
1334}
1335
f6dfb4c3
HHZ		 1336void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1337{
1338 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
f6dfb4c3
HHZ		 1339 struct mlx5e_tc_flow *flow;
1340 struct mlx5e_encap_entry *e;
1341 struct mlx5_fc *counter;
1342 struct neigh_table *tbl;
1343 bool neigh_used = false;
1344 struct neighbour *n;
90bb7692 1345 u64 lastuse;
f6dfb4c3
HHZ		 1346
1347 if (m_neigh->family == AF_INET)
1348 tbl = &arp_tbl;
1349#if IS_ENABLED(CONFIG_IPV6)
1350 else if (m_neigh->family == AF_INET6)
423c9db2 1351 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1352#endif
1353 else
1354 return;
1355
1356 list_for_each_entry(e, &nhe->encap_list, encap_list) {
5a7e5bcb 1357 struct encap_flow_item *efi, *tmp;
f6dfb4c3
HHZ		 1358 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1359 continue;
5a7e5bcb 1360 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1361 flow = container_of(efi, struct mlx5e_tc_flow,
1362 encaps[efi->index]);
5a7e5bcb
VB		 1363 if (IS_ERR(mlx5e_flow_get(flow)))
1364 continue;
1365
226f2ca3 1366 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1367 counter = mlx5e_tc_get_counter(flow);
90bb7692 1368 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3 1369 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
5a7e5bcb 1370 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3
HHZ		 1371 neigh_used = true;
1372 break;
1373 }
1374 }
5a7e5bcb
VB		 1375
1376 mlx5e_flow_put(netdev_priv(e->out_dev), flow);
f6dfb4c3 1377 }
e36d4810
RD		 1378 if (neigh_used)
1379 break;
f6dfb4c3
HHZ		 1380 }
1381
1382 if (neigh_used) {
1383 nhe->reported_lastuse = jiffies;
1384
1385 /* find the relevant neigh according to the cached device and
1386 * dst ip pair
1387 */
1388 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1389 if (!n)
f6dfb4c3 1390 return;
f6dfb4c3
HHZ		 1391
1392 neigh_event_send(n, NULL);
1393 neigh_release(n);
1394 }
1395}
1396
d85cdccb 1397static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1398 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1399{
8c4dc42b 1400 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1401
5a7e5bcb
VB		 1402 /* flow wasn't fully initialized */
1403 if (list_empty(&flow->encaps[out_index].list))
1404 return;
1405
8c4dc42b 1406 list_del(&flow->encaps[out_index].list);
5067b602 1407 if (list_empty(next)) {
c1ae1152 1408 struct mlx5e_encap_entry *e;
5067b602 1409
c1ae1152 1410 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1411 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1412
1413 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1414 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1415
cdc5a7f3 1416 hash_del_rcu(&e->encap_hlist);
232c0013 1417 kfree(e->encap_header);
5067b602
RD		 1418 kfree(e);
1419 }
1420}
1421
04de7dda
RD		 1422static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1423{
1424 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1425
226f2ca3
VB		 1426 if (!flow_flag_test(flow, ESWITCH) ||
1427 !flow_flag_test(flow, DUP))
04de7dda
RD		 1428 return;
1429
1430 mutex_lock(&esw->offloads.peer_mutex);
1431 list_del(&flow->peer);
1432 mutex_unlock(&esw->offloads.peer_mutex);
1433
226f2ca3 1434 flow_flag_clear(flow, DUP);
04de7dda
RD		 1435
1436 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1437 kvfree(flow->peer_flow);
1438 flow->peer_flow = NULL;
1439}
1440
1441static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1442{
1443 struct mlx5_core_dev *dev = flow->priv->mdev;
1444 struct mlx5_devcom *devcom = dev->priv.devcom;
1445 struct mlx5_eswitch *peer_esw;
1446
1447 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1448 if (!peer_esw)
1449 return;
1450
1451 __mlx5e_tc_del_fdb_peer_flow(flow);
1452 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1453}
1454
e8f887ac 1455static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1456 struct mlx5e_tc_flow *flow)
e8f887ac 1457{
226f2ca3 1458 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1459 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1460 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1461 } else {
d85cdccb 1462 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1463 }
e8f887ac
AV		 1464}
1465
bbd00f7e
HHZ		 1466
1467static int parse_tunnel_attr(struct mlx5e_priv *priv,
1468 struct mlx5_flow_spec *spec,
f9e30088 1469 struct flow_cls_offload *f,
6363651d 1470 struct net_device *filter_dev, u8 *match_level)
bbd00f7e 1471{
e98bedf5 1472 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1473 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1474 outer_headers);
1475 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1476 outer_headers);
f9e30088 1477 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1478 int err;
2e72eb43 1479
101f4de9 1480 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
6363651d 1481 headers_c, headers_v, match_level);
54c177ca
OS		 1482 if (err) {
1483 NL_SET_ERR_MSG_MOD(extack,
1484 "failed to parse tunnel attributes");
101f4de9 1485 return err;
bbd00f7e
HHZ		 1486 }
1487
d1bda7ee 1488 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) {
8f256622
PNA		 1489 struct flow_match_ipv4_addrs match;
1490
1491 flow_rule_match_enc_ipv4_addrs(rule, &match);
bbd00f7e
HHZ		 1492 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1493 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1494 ntohl(match.mask->src));
bbd00f7e
HHZ		 1495 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1496 src_ipv4_src_ipv6.ipv4_layout.ipv4,
8f256622 1497 ntohl(match.key->src));
bbd00f7e
HHZ		 1498
1499 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1500 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1501 ntohl(match.mask->dst));
bbd00f7e
HHZ		 1502 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1503 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
8f256622 1504 ntohl(match.key->dst));
bbd00f7e 1505
2e72eb43
OG		 1506 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
d1bda7ee 1508 } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) {
8f256622 1509 struct flow_match_ipv6_addrs match;
19f44401 1510
8f256622 1511 flow_rule_match_enc_ipv6_addrs(rule, &match);
19f44401
OG		 1512 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1513 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1514 &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1515 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1516 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1517 &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1518
1519 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1520 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1521 &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1522 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1523 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1524 &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
19f44401
OG		 1525
1526 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1527 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1528 }
bbd00f7e 1529
8f256622
PNA		 1530 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
1531 struct flow_match_ip match;
bcef735c 1532
8f256622
PNA		 1533 flow_rule_match_enc_ip(rule, &match);
1534 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1535 match.mask->tos & 0x3);
1536 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1537 match.key->tos & 0x3);
bcef735c 1538
8f256622
PNA		 1539 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1540 match.mask->tos >> 2);
1541 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1542 match.key->tos >> 2);
bcef735c 1543
8f256622
PNA		 1544 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1545 match.mask->ttl);
1546 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1547 match.key->ttl);
e98bedf5 1548
8f256622 1549 if (match.mask->ttl &&
e98bedf5
EB		 1550 !MLX5_CAP_ESW_FLOWTABLE_FDB
1551 (priv->mdev,
1552 ft_field_support.outer_ipv4_ttl)) {
1553 NL_SET_ERR_MSG_MOD(extack,
1554 "Matching on TTL is not supported");
1555 return -EOPNOTSUPP;
1556 }
1557
bcef735c
OG		 1558 }
1559
bbd00f7e
HHZ		 1560 /* Enforce DMAC when offloading incoming tunneled flows.
1561 * Flow counters require a match on the DMAC.
1562 */
1563 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1564 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1565 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1566 dmac_47_16), priv->netdev->dev_addr);
1567
1568 /* let software handle IP fragments */
1569 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1570 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1571
1572 return 0;
1573}
1574
8377629e
EB		 1575static void *get_match_headers_criteria(u32 flags,
1576 struct mlx5_flow_spec *spec)
1577{
1578 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1579 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1580 inner_headers) :
1581 MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1582 outer_headers);
1583}
1584
1585static void *get_match_headers_value(u32 flags,
1586 struct mlx5_flow_spec *spec)
1587{
1588 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1589 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1590 inner_headers) :
1591 MLX5_ADDR_OF(fte_match_param, spec->match_value,
1592 outer_headers);
1593}
1594
de0af0bf
RD		 1595static int __parse_cls_flower(struct mlx5e_priv *priv,
1596 struct mlx5_flow_spec *spec,
f9e30088 1597 struct flow_cls_offload *f,
54c177ca 1598 struct net_device *filter_dev,
6363651d 1599 u8 *match_level, u8 *tunnel_match_level)
e3a2b7ed 1600{
e98bedf5 1601 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1602 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1603 outer_headers);
1604 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1605 outer_headers);
699e96dd
JL		 1606 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1607 misc_parameters);
1608 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1609 misc_parameters);
f9e30088 1610 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 1611 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 1612 u16 addr_type = 0;
1613 u8 ip_proto = 0;
1614
d708f902 1615 *match_level = MLX5_MATCH_NONE;
de0af0bf 1616
8f256622 1617 if (dissector->used_keys &
3d144578
VB		 1618 ~(BIT(FLOW_DISSECTOR_KEY_META) |
1619 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 1620 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1621 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1622 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1623 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1624 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1625 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1626 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1627 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1628 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1629 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1630 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1631 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1632 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 1633 BIT(FLOW_DISSECTOR_KEY_IP) |
9272e3df
YK		 1634 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
1635 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS))) {
e98bedf5 1636 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed 1637 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
8f256622 1638 dissector->used_keys);
e3a2b7ed
AV		 1639 return -EOPNOTSUPP;
1640 }
1641
075973c7 1642 if (mlx5e_get_tc_tun(filter_dev)) {
d1bda7ee 1643 if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level))
bbd00f7e 1644 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1645
1646 /* In decap flow, header pointers should point to the inner
1647 * headers, outer header were already set by parse_tunnel_attr
1648 */
8377629e
EB		 1649 headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1650 spec);
1651 headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP,
1652 spec);
bbd00f7e
HHZ		 1653 }
1654
8f256622
PNA		 1655 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1656 struct flow_match_basic match;
1657
1658 flow_rule_match_basic(rule, &match);
d3a80bb5 1659 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
8f256622 1660 ntohs(match.mask->n_proto));
d3a80bb5 1661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
8f256622 1662 ntohs(match.key->n_proto));
e3a2b7ed 1663
8f256622 1664 if (match.mask->n_proto)
d708f902 1665 *match_level = MLX5_MATCH_L2;
e3a2b7ed 1666 }
35a605db
EB		 1667 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
1668 is_vlan_dev(filter_dev)) {
1669 struct flow_dissector_key_vlan filter_dev_mask;
1670 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 1671 struct flow_match_vlan match;
1672
35a605db
EB		 1673 if (is_vlan_dev(filter_dev)) {
1674 match.key = &filter_dev_key;
1675 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
1676 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
1677 match.key->vlan_priority = 0;
1678 match.mask = &filter_dev_mask;
1679 memset(match.mask, 0xff, sizeof(*match.mask));
1680 match.mask->vlan_priority = 0;
1681 } else {
1682 flow_rule_match_vlan(rule, &match);
1683 }
8f256622
PNA		 1684 if (match.mask->vlan_id ||
1685 match.mask->vlan_priority ||
1686 match.mask->vlan_tpid) {
1687 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1688 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1689 svlan_tag, 1);
1690 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1691 svlan_tag, 1);
1692 } else {
1693 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1694 cvlan_tag, 1);
1695 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1696 cvlan_tag, 1);
1697 }
095b6cfd 1698
8f256622
PNA		 1699 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
1700 match.mask->vlan_id);
1701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
1702 match.key->vlan_id);
358d79a4 1703
8f256622
PNA		 1704 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
1705 match.mask->vlan_priority);
1706 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
1707 match.key->vlan_priority);
54782900 1708
d708f902 1709 *match_level = MLX5_MATCH_L2;
54782900 1710 }
d3a80bb5 1711 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1712 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1713 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1714 *match_level = MLX5_MATCH_L2;
54782900
OG		 1715 }
1716
8f256622
PNA		 1717 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
1718 struct flow_match_vlan match;
1719
12d5cbf8 1720 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 1721 if (match.mask->vlan_id ||
1722 match.mask->vlan_priority ||
1723 match.mask->vlan_tpid) {
1724 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 1725 MLX5_SET(fte_match_set_misc, misc_c,
1726 outer_second_svlan_tag, 1);
1727 MLX5_SET(fte_match_set_misc, misc_v,
1728 outer_second_svlan_tag, 1);
1729 } else {
1730 MLX5_SET(fte_match_set_misc, misc_c,
1731 outer_second_cvlan_tag, 1);
1732 MLX5_SET(fte_match_set_misc, misc_v,
1733 outer_second_cvlan_tag, 1);
1734 }
1735
1736 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 1737 match.mask->vlan_id);
699e96dd 1738 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 1739 match.key->vlan_id);
699e96dd 1740 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 1741 match.mask->vlan_priority);
699e96dd 1742 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 1743 match.key->vlan_priority);
699e96dd
JL		 1744
1745 *match_level = MLX5_MATCH_L2;
1746 }
1747 }
1748
8f256622
PNA		 1749 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1750 struct flow_match_eth_addrs match;
54782900 1751
8f256622 1752 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 1753 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1754 dmac_47_16),
8f256622 1755 match.mask->dst);
d3a80bb5
OG		 1756 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1757 dmac_47_16),
8f256622 1758 match.key->dst);
d3a80bb5
OG		 1759
1760 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1761 smac_47_16),
8f256622 1762 match.mask->src);
d3a80bb5
OG		 1763 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1764 smac_47_16),
8f256622 1765 match.key->src);
d3a80bb5 1766
8f256622
PNA		 1767 if (!is_zero_ether_addr(match.mask->src) ||
1768 !is_zero_ether_addr(match.mask->dst))
d708f902 1769 *match_level = MLX5_MATCH_L2;
54782900
OG		 1770 }
1771
8f256622
PNA		 1772 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
1773 struct flow_match_control match;
54782900 1774
8f256622
PNA		 1775 flow_rule_match_control(rule, &match);
1776 addr_type = match.key->addr_type;
54782900
OG		 1777
1778 /* the HW doesn't support frag first/later */
8f256622 1779 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 1780 return -EOPNOTSUPP;
1781
8f256622 1782 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 1783 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1784 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 1785 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 1786
1787 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 1788 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1789 *match_level = MLX5_MATCH_L2;
54782900
OG		 1790 /* *** L2 attributes parsing up to here *** */
1791 else
83621b7d 1792 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1793 }
1794 }
1795
8f256622
PNA		 1796 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
1797 struct flow_match_basic match;
1798
1799 flow_rule_match_basic(rule, &match);
1800 ip_proto = match.key->ip_proto;
54782900
OG		 1801
1802 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 1803 match.mask->ip_proto);
54782900 1804 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 1805 match.key->ip_proto);
54782900 1806
8f256622 1807 if (match.mask->ip_proto)
d708f902 1808 *match_level = MLX5_MATCH_L3;
54782900
OG		 1809 }
1810
e3a2b7ed 1811 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 1812 struct flow_match_ipv4_addrs match;
e3a2b7ed 1813
8f256622 1814 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 1815 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1816 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1817 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1818 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1819 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 1820 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1821 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1822 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1823 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1824 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1825 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 1826 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1827
8f256622 1828 if (match.mask->src || match.mask->dst)
d708f902 1829 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1830 }
1831
1832 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 1833 struct flow_match_ipv6_addrs match;
e3a2b7ed 1834
8f256622 1835 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 1836 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1837 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1838 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 1839 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1840 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 1841 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 1842
1843 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1844 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1845 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 1846 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1847 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 1848 &match.key->dst, sizeof(match.key->dst));
de0af0bf 1849
8f256622
PNA		 1850 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
1851 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 1852 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1853 }
1854
8f256622
PNA		 1855 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
1856 struct flow_match_ip match;
1f97a526 1857
8f256622
PNA		 1858 flow_rule_match_ip(rule, &match);
1859 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
1860 match.mask->tos & 0x3);
1861 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
1862 match.key->tos & 0x3);
1f97a526 1863
8f256622
PNA		 1864 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
1865 match.mask->tos >> 2);
1866 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
1867 match.key->tos >> 2);
1f97a526 1868
8f256622
PNA		 1869 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
1870 match.mask->ttl);
1871 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
1872 match.key->ttl);
1f97a526 1873
8f256622 1874 if (match.mask->ttl &&
a8ade55f 1875 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1876 ft_field_support.outer_ipv4_ttl)) {
1877 NL_SET_ERR_MSG_MOD(extack,
1878 "Matching on TTL is not supported");
1f97a526 1879 return -EOPNOTSUPP;
e98bedf5 1880 }
a8ade55f 1881
8f256622 1882 if (match.mask->tos || match.mask->ttl)
d708f902 1883 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1884 }
1885
54782900
OG		 1886 /* *** L3 attributes parsing up to here *** */
1887
8f256622
PNA		 1888 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
1889 struct flow_match_ports match;
1890
1891 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 1892 switch (ip_proto) {
1893 case IPPROTO_TCP:
1894 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1895 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 1896 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1897 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1898
1899 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1900 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 1901 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1902 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1903 break;
1904
1905 case IPPROTO_UDP:
1906 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1907 udp_sport, ntohs(match.mask->src));
e3a2b7ed 1908 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1909 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 1910
1911 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 1912 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 1913 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 1914 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 1915 break;
1916 default:
e98bedf5
EB		 1917 NL_SET_ERR_MSG_MOD(extack,
1918 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1919 netdev_err(priv->netdev,
1920 "Only UDP and TCP transport are supported\n");
1921 return -EINVAL;
1922 }
de0af0bf 1923
8f256622 1924 if (match.mask->src || match.mask->dst)
d708f902 1925 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1926 }
1927
8f256622
PNA		 1928 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
1929 struct flow_match_tcp match;
e77834ec 1930
8f256622 1931 flow_rule_match_tcp(rule, &match);
e77834ec 1932 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 1933 ntohs(match.mask->flags));
e77834ec 1934 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 1935 ntohs(match.key->flags));
e77834ec 1936
8f256622 1937 if (match.mask->flags)
d708f902 1938 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1939 }
1940
e3a2b7ed
AV		 1941 return 0;
1942}
1943
de0af0bf 1944static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1945 struct mlx5e_tc_flow *flow,
de0af0bf 1946 struct mlx5_flow_spec *spec,
f9e30088 1947 struct flow_cls_offload *f,
54c177ca 1948 struct net_device *filter_dev)
de0af0bf 1949{
e98bedf5 1950 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1951 struct mlx5_core_dev *dev = priv->mdev;
1952 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39 1953 struct mlx5e_rep_priv *rpriv = priv->ppriv;
6363651d 1954 u8 match_level, tunnel_match_level = MLX5_MATCH_NONE;
1d447a39 1955 struct mlx5_eswitch_rep *rep;
226f2ca3 1956 bool is_eswitch_flow;
de0af0bf
RD		 1957 int err;
1958
6363651d 1959 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level);
de0af0bf 1960
226f2ca3
VB		 1961 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
1962 if (!err && is_eswitch_flow) {
1d447a39 1963 rep = rpriv->rep;
b05af6aa 1964 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 1965 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1966 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1967 NL_SET_ERR_MSG_MOD(extack,
1968 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1969 netdev_warn(priv->netdev,
1970 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1971 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1972 return -EOPNOTSUPP;
1973 }
1974 }
1975
226f2ca3 1976 if (is_eswitch_flow) {
38aa51c1 1977 flow->esw_attr->match_level = match_level;
6363651d
OG		 1978 flow->esw_attr->tunnel_match_level = tunnel_match_level;
1979 } else {
38aa51c1 1980 flow->nic_attr->match_level = match_level;
6363651d 1981 }
38aa51c1 1982
de0af0bf
RD		 1983 return err;
1984}
1985
d79b6df6
OG		 1986struct pedit_headers {
1987 struct ethhdr eth;
0eb69bb9 1988 struct vlan_hdr vlan;
d79b6df6
OG		 1989 struct iphdr ip4;
1990 struct ipv6hdr ip6;
1991 struct tcphdr tcp;
1992 struct udphdr udp;
1993};
1994
c500c86b
PNA		 1995struct pedit_headers_action {
1996 struct pedit_headers vals;
1997 struct pedit_headers masks;
1998 u32 pedits;
1999};
2000
d79b6df6 2001static int pedit_header_offsets[] = {
73867881
PNA		 2002 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2003 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2004 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2005 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2006 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2007};
2008
2009#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2010
2011static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2012 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2013{
2014 u32 *curr_pmask, *curr_pval;
2015
c500c86b
PNA		 2016 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2017 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2018
2019 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2020 goto out_err;
2021
2022 *curr_pmask |= mask;
2023 *curr_pval |= (val & mask);
2024
2025 return 0;
2026
2027out_err:
2028 return -EOPNOTSUPP;
2029}
2030
2031struct mlx5_fields {
2032 u8 field;
2033 u8 size;
2034 u32 offset;
27c11b6b 2035 u32 match_offset;
d79b6df6
OG		 2036};
2037
27c11b6b
EB		 2038#define OFFLOAD(fw_field, size, field, off, match_field) \
2039 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \
2040 offsetof(struct pedit_headers, field) + (off), \
2041 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2042
2ef86872
EB		 2043/* masked values are the same and there are no rewrites that do not have a
2044 * match.
2045 */
2046#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2047 type matchmaskx = *(type *)(matchmaskp); \
2048 type matchvalx = *(type *)(matchvalp); \
2049 type maskx = *(type *)(maskp); \
2050 type valx = *(type *)(valp); \
2051 \
2052 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2053 matchmaskx)); \
2054})
2055
27c11b6b
EB		 2056static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
2057 void *matchmaskp, int size)
2058{
2059 bool same = false;
2060
2061 switch (size) {
2062 case sizeof(u8):
2ef86872 2063 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2064 break;
2065 case sizeof(u16):
2ef86872 2066 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2067 break;
2068 case sizeof(u32):
2ef86872 2069 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2070 break;
2071 }
2072
2073 return same;
2074}
a8e4f0c4 2075
d79b6df6 2076static struct mlx5_fields fields[] = {
27c11b6b
EB		 2077 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16),
2078 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0),
2079 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16),
2080 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0),
2081 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype),
2082 OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid),
2083
2084 OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit),
2085 OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2086 OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2087
2088 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0,
2089 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
2090 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0,
2091 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
2092 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0,
2093 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
2094 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0,
2095 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
2096 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0,
2097 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
2098 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0,
2099 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
2100 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0,
2101 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
2102 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0,
2103 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
2104 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit),
2105
2106 OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport),
2107 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport),
2108 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags),
2109
2110 OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport),
2111 OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport),
d79b6df6
OG		 2112};
2113
218d05ce
TZ		 2114/* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at
2115 * max from the SW pedit action. On success, attr->num_mod_hdr_actions
2116 * says how many HW actions were actually parsed.
d79b6df6 2117 */
c500c86b 2118static int offload_pedit_fields(struct pedit_headers_action *hdrs,
e98bedf5 2119 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2120 u32 *action_flags,
e98bedf5 2121 struct netlink_ext_ack *extack)
d79b6df6
OG		 2122{
2123 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
27c11b6b
EB		 2124 void *headers_c = get_match_headers_criteria(*action_flags,
2125 &parse_attr->spec);
2126 void *headers_v = get_match_headers_value(*action_flags,
2127 &parse_attr->spec);
2b64beba 2128 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 2129 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 2130 struct mlx5_fields *f;
2131 u8 cmd, field_bsize;
e3ca4e05 2132 u32 s_mask, a_mask;
d79b6df6 2133 unsigned long mask;
2b64beba
OG		 2134 __be32 mask_be32;
2135 __be16 mask_be16;
d79b6df6
OG		 2136 void *action;
2137
73867881
PNA		 2138 set_masks = &hdrs[0].masks;
2139 add_masks = &hdrs[1].masks;
2140 set_vals = &hdrs[0].vals;
2141 add_vals = &hdrs[1].vals;
d79b6df6
OG		 2142
2143 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
218d05ce
TZ		 2144 action = parse_attr->mod_hdr_actions +
2145 parse_attr->num_mod_hdr_actions * action_size;
2146
2147 max_actions = parse_attr->max_mod_hdr_actions;
2148 nactions = parse_attr->num_mod_hdr_actions;
d79b6df6
OG		 2149
2150 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2151 bool skip;
2152
d79b6df6
OG		 2153 f = &fields[i];
2154 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2155 s_mask = 0;
2156 a_mask = 0;
d79b6df6
OG		 2157
2158 s_masks_p = (void *)set_masks + f->offset;
2159 a_masks_p = (void *)add_masks + f->offset;
2160
2161 memcpy(&s_mask, s_masks_p, f->size);
2162 memcpy(&a_mask, a_masks_p, f->size);
2163
2164 if (!s_mask && !a_mask) /* nothing to offload here */
2165 continue;
2166
2167 if (s_mask && a_mask) {
e98bedf5
EB		 2168 NL_SET_ERR_MSG_MOD(extack,
2169 "can't set and add to the same HW field");
d79b6df6
OG		 2170 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2171 return -EOPNOTSUPP;
2172 }
2173
2174 if (nactions == max_actions) {
e98bedf5
EB		 2175 NL_SET_ERR_MSG_MOD(extack,
2176 "too many pedit actions, can't offload");
d79b6df6
OG		 2177 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
2178 return -EOPNOTSUPP;
2179 }
2180
27c11b6b 2181 skip = false;
d79b6df6 2182 if (s_mask) {
27c11b6b
EB		 2183 void *match_mask = headers_c + f->match_offset;
2184 void *match_val = headers_v + f->match_offset;
2185
d79b6df6
OG		 2186 cmd = MLX5_ACTION_TYPE_SET;
2187 mask = s_mask;
2188 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2189 /* don't rewrite if we have a match on the same value */
2190 if (cmp_val_mask(vals_p, s_masks_p, match_val,
2191 match_mask, f->size))
2192 skip = true;
d79b6df6
OG		 2193 /* clear to denote we consumed this field */
2194 memset(s_masks_p, 0, f->size);
2195 } else {
27c11b6b
EB		 2196 u32 zero = 0;
2197
d79b6df6
OG		 2198 cmd = MLX5_ACTION_TYPE_ADD;
2199 mask = a_mask;
2200 vals_p = (void *)add_vals + f->offset;
27c11b6b
EB		 2201 /* add 0 is no change */
2202 if (!memcmp(vals_p, &zero, f->size))
2203 skip = true;
d79b6df6
OG		 2204 /* clear to denote we consumed this field */
2205 memset(a_masks_p, 0, f->size);
2206 }
27c11b6b
EB		 2207 if (skip)
2208 continue;
d79b6df6 2209
d79b6df6 2210 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2211
2b64beba
OG		 2212 if (field_bsize == 32) {
2213 mask_be32 = *(__be32 *)&mask;
2214 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2215 } else if (field_bsize == 16) {
2216 mask_be16 = *(__be16 *)&mask;
2217 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2218 }
2219
d79b6df6 2220 first = find_first_bit(&mask, field_bsize);
2b64beba 2221 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2222 last = find_last_bit(&mask, field_bsize);
2b64beba 2223 if (first < next_z && next_z < last) {
e98bedf5
EB		 2224 NL_SET_ERR_MSG_MOD(extack,
2225 "rewrite of few sub-fields isn't supported");
2b64beba 2226 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2227 mask);
2228 return -EOPNOTSUPP;
2229 }
2230
2231 MLX5_SET(set_action_in, action, action_type, cmd);
2232 MLX5_SET(set_action_in, action, field, f->field);
2233
2234 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2235 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2236 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2237 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2238 }
2239
2240 if (field_bsize == 32)
2b64beba 2241 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2242 else if (field_bsize == 16)
2b64beba 2243 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2244 else if (field_bsize == 8)
2b64beba 2245 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2246
2247 action += action_size;
2248 nactions++;
2249 }
2250
2251 parse_attr->num_mod_hdr_actions = nactions;
2252 return 0;
2253}
2254
2cc1cb1d
TZ		 2255static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2256 int namespace)
2257{
2258 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2259 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2260 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2261 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2262}
2263
d79b6df6 2264static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
c500c86b
PNA		 2265 struct pedit_headers_action *hdrs,
2266 int namespace,
d79b6df6
OG		 2267 struct mlx5e_tc_flow_parse_attr *parse_attr)
2268{
2269 int nkeys, action_size, max_actions;
2270
c500c86b
PNA		 2271 nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits +
2272 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits;
d79b6df6
OG		 2273 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2274
2cc1cb1d 2275 max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace);
d79b6df6
OG		 2276 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2277 max_actions = min(max_actions, nkeys * 16);
2278
2279 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2280 if (!parse_attr->mod_hdr_actions)
2281 return -ENOMEM;
2282
218d05ce 2283 parse_attr->max_mod_hdr_actions = max_actions;
d79b6df6
OG		 2284 return 0;
2285}
2286
2287static const struct pedit_headers zero_masks = {};
2288
2289static int parse_tc_pedit_action(struct mlx5e_priv *priv,
73867881 2290 const struct flow_action_entry *act, int namespace,
e98bedf5 2291 struct mlx5e_tc_flow_parse_attr *parse_attr,
c500c86b 2292 struct pedit_headers_action *hdrs,
e98bedf5 2293 struct netlink_ext_ack *extack)
d79b6df6 2294{
73867881
PNA		 2295 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2296 int err = -EOPNOTSUPP;
d79b6df6 2297 u32 mask, val, offset;
73867881 2298 u8 htype;
d79b6df6 2299
73867881
PNA		 2300 htype = act->mangle.htype;
2301 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2302
73867881
PNA		 2303 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2304 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2305 goto out_err;
2306 }
d79b6df6 2307
2cc1cb1d
TZ		 2308 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2309 NL_SET_ERR_MSG_MOD(extack,
2310 "The pedit offload action is not supported");
2311 goto out_err;
2312 }
2313
73867881
PNA		 2314 mask = act->mangle.mask;
2315 val = act->mangle.val;
2316 offset = act->mangle.offset;
d79b6df6 2317
73867881
PNA		 2318 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
2319 if (err)
2320 goto out_err;
c500c86b 2321
73867881 2322 hdrs[cmd].pedits++;
d79b6df6 2323
c500c86b
PNA		 2324 return 0;
2325out_err:
2326 return err;
2327}
2328
2329static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2330 struct mlx5e_tc_flow_parse_attr *parse_attr,
2331 struct pedit_headers_action *hdrs,
27c11b6b 2332 u32 *action_flags,
c500c86b
PNA		 2333 struct netlink_ext_ack *extack)
2334{
2335 struct pedit_headers *cmd_masks;
2336 int err;
2337 u8 cmd;
2338
218d05ce 2339 if (!parse_attr->mod_hdr_actions) {
a655fe9f 2340 err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr);
218d05ce
TZ		 2341 if (err)
2342 goto out_err;
2343 }
d79b6df6 2344
27c11b6b 2345 err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack);
d79b6df6
OG		 2346 if (err < 0)
2347 goto out_dealloc_parsed_actions;
2348
2349 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2350 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2351 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2352 NL_SET_ERR_MSG_MOD(extack,
2353 "attempt to offload an unsupported field");
b3a433de 2354 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2355 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2356 16, 1, cmd_masks, sizeof(zero_masks), true);
2357 err = -EOPNOTSUPP;
2358 goto out_dealloc_parsed_actions;
2359 }
2360 }
2361
2362 return 0;
2363
2364out_dealloc_parsed_actions:
2365 kfree(parse_attr->mod_hdr_actions);
2366out_err:
2367 return err;
2368}
2369
e98bedf5
EB		 2370static bool csum_offload_supported(struct mlx5e_priv *priv,
2371 u32 action,
2372 u32 update_flags,
2373 struct netlink_ext_ack *extack)
26c02749
OG		 2374{
2375 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2376 TCA_CSUM_UPDATE_FLAG_UDP;
2377
2378 /* The HW recalcs checksums only if re-writing headers */
2379 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2380 NL_SET_ERR_MSG_MOD(extack,
2381 "TC csum action is only offloaded with pedit");
26c02749
OG		 2382 netdev_warn(priv->netdev,
2383 "TC csum action is only offloaded with pedit\n");
2384 return false;
2385 }
2386
2387 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2388 NL_SET_ERR_MSG_MOD(extack,
2389 "can't offload TC csum action for some header/s");
26c02749
OG		 2390 netdev_warn(priv->netdev,
2391 "can't offload TC csum action for some header/s - flags %#x\n",
2392 update_flags);
2393 return false;
2394 }
2395
2396 return true;
2397}
2398
8998576b
DL		 2399struct ip_ttl_word {
2400 __u8 ttl;
2401 __u8 protocol;
2402 __sum16 check;
2403};
2404
2405struct ipv6_hoplimit_word {
2406 __be16 payload_len;
2407 __u8 nexthdr;
2408 __u8 hop_limit;
2409};
2410
2411static bool is_action_keys_supported(const struct flow_action_entry *act)
2412{
2413 u32 mask, offset;
2414 u8 htype;
2415
2416 htype = act->mangle.htype;
2417 offset = act->mangle.offset;
2418 mask = ~act->mangle.mask;
2419 /* For IPv4 & IPv6 header check 4 byte word,
2420 * to determine that modified fields
2421 * are NOT ttl & hop_limit only.
2422 */
2423 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
2424 struct ip_ttl_word *ttl_word =
2425 (struct ip_ttl_word *)&mask;
2426
2427 if (offset != offsetof(struct iphdr, ttl) ||
2428 ttl_word->protocol ||
2429 ttl_word->check) {
2430 return true;
2431 }
2432 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
2433 struct ipv6_hoplimit_word *hoplimit_word =
2434 (struct ipv6_hoplimit_word *)&mask;
2435
2436 if (offset != offsetof(struct ipv6hdr, payload_len) ||
2437 hoplimit_word->payload_len ||
2438 hoplimit_word->nexthdr) {
2439 return true;
2440 }
2441 }
2442 return false;
2443}
2444
bdd66ac0 2445static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
73867881 2446 struct flow_action *flow_action,
1651925d 2447 u32 actions,
e98bedf5 2448 struct netlink_ext_ack *extack)
bdd66ac0 2449{
73867881 2450 const struct flow_action_entry *act;
bdd66ac0 2451 bool modify_ip_header;
bdd66ac0
OG		 2452 void *headers_v;
2453 u16 ethertype;
8998576b 2454 u8 ip_proto;
73867881 2455 int i;
bdd66ac0 2456
8377629e 2457 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 2458 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2459
2460 /* for non-IP we only re-write MACs, so we're okay */
2461 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2462 goto out_ok;
2463
2464 modify_ip_header = false;
73867881
PNA		 2465 flow_action_for_each(i, act, flow_action) {
2466 if (act->id != FLOW_ACTION_MANGLE &&
2467 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 2468 continue;
2469
8998576b 2470 if (is_action_keys_supported(act)) {
73867881
PNA		 2471 modify_ip_header = true;
2472 break;
bdd66ac0
OG		 2473 }
2474 }
2475
2476 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2477 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2478 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2479 NL_SET_ERR_MSG_MOD(extack,
2480 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2481 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2482 return false;
2483 }
2484
2485out_ok:
2486 return true;
2487}
2488
2489static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 2490 struct flow_action *flow_action,
bdd66ac0 2491 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2492 struct mlx5e_tc_flow *flow,
2493 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2494{
2495 u32 actions;
2496
226f2ca3 2497 if (mlx5e_is_eswitch_flow(flow))
bdd66ac0
OG		 2498 actions = flow->esw_attr->action;
2499 else
2500 actions = flow->nic_attr->action;
2501
226f2ca3 2502 if (flow_flag_test(flow, EGRESS) &&
35a605db 2503 !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) ||
6830b468
TZ		 2504 (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
2505 (actions & MLX5_FLOW_CONTEXT_ACTION_DROP)))
7e29392e
RD		 2506 return false;
2507
bdd66ac0 2508 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
73867881 2509 return modify_header_match_supported(&parse_attr->spec,
a655fe9f 2510 flow_action, actions,
e98bedf5 2511 extack);
bdd66ac0
OG		 2512
2513 return true;
2514}
2515
5c65c564
OG		 2516static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2517{
2518 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2519 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2520
2521 fmdev = priv->mdev;
2522 pmdev = peer_priv->mdev;
2523
59c9d35e
AH		 2524 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2525 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2526
816f6706 2527 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2528}
2529
bdc837ee
EB		 2530static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
2531 const struct flow_action_entry *act,
2532 struct mlx5e_tc_flow_parse_attr *parse_attr,
2533 struct pedit_headers_action *hdrs,
2534 u32 *action, struct netlink_ext_ack *extack)
2535{
2536 u16 mask16 = VLAN_VID_MASK;
2537 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
2538 const struct flow_action_entry pedit_act = {
2539 .id = FLOW_ACTION_MANGLE,
2540 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
2541 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
2542 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
2543 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
2544 };
6fca9d1e 2545 u8 match_prio_mask, match_prio_val;
bf2f3bca 2546 void *headers_c, *headers_v;
bdc837ee
EB		 2547 int err;
2548
bf2f3bca
EB		 2549 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
2550 headers_v = get_match_headers_value(*action, &parse_attr->spec);
2551
2552 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
2553 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
2554 NL_SET_ERR_MSG_MOD(extack,
2555 "VLAN rewrite action must have VLAN protocol match");
2556 return -EOPNOTSUPP;
2557 }
2558
6fca9d1e
EB		 2559 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
2560 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
2561 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
2562 NL_SET_ERR_MSG_MOD(extack,
2563 "Changing VLAN prio is not supported");
bdc837ee
EB		 2564 return -EOPNOTSUPP;
2565 }
2566
2567 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr,
2568 hdrs, NULL);
2569 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2570
2571 return err;
2572}
2573
0bac1194
EB		 2574static int
2575add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
2576 struct mlx5e_tc_flow_parse_attr *parse_attr,
2577 struct pedit_headers_action *hdrs,
2578 u32 *action, struct netlink_ext_ack *extack)
2579{
2580 const struct flow_action_entry prio_tag_act = {
2581 .vlan.vid = 0,
2582 .vlan.prio =
2583 MLX5_GET(fte_match_set_lyr_2_4,
2584 get_match_headers_value(*action,
2585 &parse_attr->spec),
2586 first_prio) &
2587 MLX5_GET(fte_match_set_lyr_2_4,
2588 get_match_headers_criteria(*action,
2589 &parse_attr->spec),
2590 first_prio),
2591 };
2592
2593 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
2594 &prio_tag_act, parse_attr, hdrs, action,
2595 extack);
2596}
2597
73867881
PNA		 2598static int parse_tc_nic_actions(struct mlx5e_priv *priv,
2599 struct flow_action *flow_action,
aa0cbbae 2600 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2601 struct mlx5e_tc_flow *flow,
2602 struct netlink_ext_ack *extack)
e3a2b7ed 2603{
aa0cbbae 2604 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
73867881
PNA		 2605 struct pedit_headers_action hdrs[2] = {};
2606 const struct flow_action_entry *act;
1cab1cd7 2607 u32 action = 0;
244cd96a 2608 int err, i;
e3a2b7ed 2609
73867881 2610 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 2611 return -EINVAL;
2612
3bc4b7bf 2613 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2614
73867881
PNA		 2615 flow_action_for_each(i, act, flow_action) {
2616 switch (act->id) {
2617 case FLOW_ACTION_DROP:
1cab1cd7 2618 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2619 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2620 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2621 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2622 break;
2623 case FLOW_ACTION_MANGLE:
2624 case FLOW_ACTION_ADD:
2625 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
c500c86b 2626 parse_attr, hdrs, extack);
2f4fe4ca
OG		 2627 if (err)
2628 return err;
2629
1cab1cd7
OG		 2630 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2631 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881 2632 break;
bdc837ee
EB		 2633 case FLOW_ACTION_VLAN_MANGLE:
2634 err = add_vlan_rewrite_action(priv,
2635 MLX5_FLOW_NAMESPACE_KERNEL,
2636 act, parse_attr, hdrs,
2637 &action, extack);
2638 if (err)
2639 return err;
2640
2641 break;
73867881 2642 case FLOW_ACTION_CSUM:
1cab1cd7 2643 if (csum_offload_supported(priv, action,
73867881 2644 act->csum_flags,
e98bedf5 2645 extack))
73867881 2646 break;
26c02749
OG		 2647
2648 return -EOPNOTSUPP;
73867881
PNA		 2649 case FLOW_ACTION_REDIRECT: {
2650 struct net_device *peer_dev = act->dev;
5c65c564
OG		 2651
2652 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2653 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2654 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 2655 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 2656 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2657 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2658 } else {
e98bedf5
EB		 2659 NL_SET_ERR_MSG_MOD(extack,
2660 "device is not on same HW, can't offload");
5c65c564
OG		 2661 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2662 peer_dev->name);
2663 return -EINVAL;
2664 }
73867881
PNA		 2665 }
2666 break;
2667 case FLOW_ACTION_MARK: {
2668 u32 mark = act->mark;
e3a2b7ed
AV		 2669
2670 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2671 NL_SET_ERR_MSG_MOD(extack,
2672 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2673 return -EINVAL;
2674 }
2675
3bc4b7bf 2676 attr->flow_tag = mark;
1cab1cd7 2677 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 2678 }
2679 break;
2680 default:
2cc1cb1d
TZ		 2681 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
2682 return -EOPNOTSUPP;
e3a2b7ed 2683 }
e3a2b7ed
AV		 2684 }
2685
c500c86b
PNA		 2686 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
2687 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
2688 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 2689 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 2690 if (err)
2691 return err;
27c11b6b
EB		 2692 /* in case all pedit actions are skipped, remove the MOD_HDR
2693 * flag.
2694 */
e7739a60 2695 if (parse_attr->num_mod_hdr_actions == 0) {
27c11b6b 2696 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60
EB		 2697 kfree(parse_attr->mod_hdr_actions);
2698 }
c500c86b
PNA		 2699 }
2700
1cab1cd7 2701 attr->action = action;
73867881 2702 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 2703 return -EOPNOTSUPP;
2704
e3a2b7ed
AV		 2705 return 0;
2706}
2707
7f1a546e 2708struct encap_key {
1f6da306 2709 const struct ip_tunnel_key *ip_tun_key;
d386939a 2710 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 2711};
2712
2713static inline int cmp_encap_info(struct encap_key *a,
2714 struct encap_key *b)
a54e20b4 2715{
7f1a546e 2716 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 2717 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 2718}
2719
7f1a546e 2720static inline int hash_encap_info(struct encap_key *key)
a54e20b4 2721{
7f1a546e 2722 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 2723 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 2724}
2725
a54e20b4 2726
b1d90e6b
RL		 2727static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2728 struct net_device *peer_netdev)
2729{
2730 struct mlx5e_priv *peer_priv;
2731
2732 peer_priv = netdev_priv(peer_netdev);
2733
2734 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
68931c7d
RD		 2735 mlx5e_eswitch_rep(priv->netdev) &&
2736 mlx5e_eswitch_rep(peer_netdev) &&
2737 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 2738}
2739
32f3671f 2740
f5bc2c5d 2741
a54e20b4 2742static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 2743 struct mlx5e_tc_flow *flow,
733d4f36
RD		 2744 struct net_device *mirred_dev,
2745 int out_index,
8c4dc42b 2746 struct netlink_ext_ack *extack,
0ad060ee
RD		 2747 struct net_device **encap_dev,
2748 bool *encap_valid)
a54e20b4
HHZ		 2749{
2750 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
45247bf2 2751 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
733d4f36 2752 struct mlx5e_tc_flow_parse_attr *parse_attr;
1f6da306 2753 const struct ip_tunnel_info *tun_info;
7f1a546e 2754 struct encap_key key, e_key;
c1ae1152 2755 struct mlx5e_encap_entry *e;
733d4f36 2756 unsigned short family;
a54e20b4
HHZ		 2757 uintptr_t hash_key;
2758 bool found = false;
54c177ca 2759 int err = 0;
a54e20b4 2760
733d4f36 2761 parse_attr = attr->parse_attr;
1f6da306 2762 tun_info = parse_attr->tun_info[out_index];
733d4f36 2763 family = ip_tunnel_info_af(tun_info);
7f1a546e 2764 key.ip_tun_key = &tun_info->key;
d386939a 2765 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 2766 if (!key.tc_tunnel) {
2767 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
2768 return -EOPNOTSUPP;
2769 }
733d4f36 2770
7f1a546e 2771 hash_key = hash_encap_info(&key);
a54e20b4
HHZ		 2772
2773 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2774 encap_hlist, hash_key) {
1f6da306 2775 e_key.ip_tun_key = &e->tun_info->key;
d386939a 2776 e_key.tc_tunnel = e->tunnel;
7f1a546e 2777 if (!cmp_encap_info(&e_key, &key)) {
a54e20b4
HHZ		 2778 found = true;
2779 break;
2780 }
2781 }
2782
b2812089 2783 /* must verify if encap is valid or not */
45247bf2
OG		 2784 if (found)
2785 goto attach_flow;
a54e20b4
HHZ		 2786
2787 e = kzalloc(sizeof(*e), GFP_KERNEL);
2788 if (!e)
2789 return -ENOMEM;
2790
1f6da306 2791 e->tun_info = tun_info;
101f4de9 2792 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2793 if (err)
2794 goto out_err;
2795
a54e20b4
HHZ		 2796 INIT_LIST_HEAD(&e->flows);
2797
ce99f6b9 2798 if (family == AF_INET)
101f4de9 2799 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2800 else if (family == AF_INET6)
101f4de9 2801 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2802
0ad060ee 2803 if (err)
a54e20b4
HHZ		 2804 goto out_err;
2805
a54e20b4
HHZ		 2806 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2807
45247bf2 2808attach_flow:
8c4dc42b
EB		 2809 list_add(&flow->encaps[out_index].list, &e->flows);
2810 flow->encaps[out_index].index = out_index;
45247bf2 2811 *encap_dev = e->out_dev;
8c4dc42b
EB		 2812 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2813 attr->dests[out_index].encap_id = e->encap_id;
2814 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 2815 *encap_valid = true;
8c4dc42b 2816 } else {
0ad060ee 2817 *encap_valid = false;
8c4dc42b 2818 }
45247bf2 2819
232c0013 2820 return err;
a54e20b4
HHZ		 2821
2822out_err:
2823 kfree(e);
2824 return err;
2825}
2826
1482bd3d 2827static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 2828 const struct flow_action_entry *act,
1482bd3d
JL		 2829 struct mlx5_esw_flow_attr *attr,
2830 u32 *action)
2831{
cc495188
JL		 2832 u8 vlan_idx = attr->total_vlan;
2833
2834 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2835 return -EOPNOTSUPP;
2836
73867881
PNA		 2837 switch (act->id) {
2838 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 2839 if (vlan_idx) {
2840 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2841 MLX5_FS_VLAN_DEPTH))
2842 return -EOPNOTSUPP;
2843
2844 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2845 } else {
2846 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2847 }
73867881
PNA		 2848 break;
2849 case FLOW_ACTION_VLAN_PUSH:
2850 attr->vlan_vid[vlan_idx] = act->vlan.vid;
2851 attr->vlan_prio[vlan_idx] = act->vlan.prio;
2852 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 2853 if (!attr->vlan_proto[vlan_idx])
2854 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2855
2856 if (vlan_idx) {
2857 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2858 MLX5_FS_VLAN_DEPTH))
2859 return -EOPNOTSUPP;
2860
2861 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2862 } else {
2863 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 2864 (act->vlan.proto != htons(ETH_P_8021Q) ||
2865 act->vlan.prio))
cc495188
JL		 2866 return -EOPNOTSUPP;
2867
2868 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 2869 }
73867881
PNA		 2870 break;
2871 default:
bdc837ee 2872 return -EINVAL;
1482bd3d
JL		 2873 }
2874
cc495188
JL		 2875 attr->total_vlan = vlan_idx + 1;
2876
1482bd3d
JL		 2877 return 0;
2878}
2879
278748a9
EB		 2880static int add_vlan_push_action(struct mlx5e_priv *priv,
2881 struct mlx5_esw_flow_attr *attr,
2882 struct net_device **out_dev,
2883 u32 *action)
2884{
2885 struct net_device *vlan_dev = *out_dev;
2886 struct flow_action_entry vlan_act = {
2887 .id = FLOW_ACTION_VLAN_PUSH,
2888 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
2889 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
2890 .vlan.prio = 0,
2891 };
2892 int err;
2893
2894 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2895 if (err)
2896 return err;
2897
2898 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
2899 dev_get_iflink(vlan_dev));
2900 if (is_vlan_dev(*out_dev))
2901 err = add_vlan_push_action(priv, attr, out_dev, action);
2902
2903 return err;
2904}
2905
35a605db
EB		 2906static int add_vlan_pop_action(struct mlx5e_priv *priv,
2907 struct mlx5_esw_flow_attr *attr,
2908 u32 *action)
2909{
2910 int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev);
2911 struct flow_action_entry vlan_act = {
2912 .id = FLOW_ACTION_VLAN_POP,
2913 };
2914 int err = 0;
2915
2916 while (nest_level--) {
2917 err = parse_tc_vlan_action(priv, &vlan_act, attr, action);
2918 if (err)
2919 return err;
2920 }
2921
2922 return err;
2923}
2924
f6dc1264
PB		 2925bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
2926 struct net_device *out_dev)
2927{
2928 if (is_merged_eswitch_dev(priv, out_dev))
2929 return true;
2930
2931 return mlx5e_eswitch_rep(out_dev) &&
2932 same_hw_devs(priv, netdev_priv(out_dev));
2933}
2934
73867881
PNA		 2935static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
2936 struct flow_action *flow_action,
e98bedf5
EB		 2937 struct mlx5e_tc_flow *flow,
2938 struct netlink_ext_ack *extack)
03a9d11e 2939{
73867881 2940 struct pedit_headers_action hdrs[2] = {};
bf07aa73 2941 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2942 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
6f9af8ff 2943 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
1d447a39 2944 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881
PNA		 2945 const struct ip_tunnel_info *info = NULL;
2946 const struct flow_action_entry *act;
a54e20b4 2947 bool encap = false;
1cab1cd7 2948 u32 action = 0;
244cd96a 2949 int err, i;
03a9d11e 2950
73867881 2951 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 2952 return -EINVAL;
2953
73867881
PNA		 2954 flow_action_for_each(i, act, flow_action) {
2955 switch (act->id) {
2956 case FLOW_ACTION_DROP:
1cab1cd7
OG		 2957 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2958 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 2959 break;
2960 case FLOW_ACTION_MANGLE:
2961 case FLOW_ACTION_ADD:
2962 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
c500c86b 2963 parse_attr, hdrs, extack);
d7e75a32
OG		 2964 if (err)
2965 return err;
2966
1cab1cd7 2967 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2968 attr->split_count = attr->out_count;
73867881
PNA		 2969 break;
2970 case FLOW_ACTION_CSUM:
1cab1cd7 2971 if (csum_offload_supported(priv, action,
73867881
PNA		 2972 act->csum_flags, extack))
2973 break;
26c02749
OG		 2974
2975 return -EOPNOTSUPP;
73867881
PNA		 2976 case FLOW_ACTION_REDIRECT:
2977 case FLOW_ACTION_MIRRED: {
03a9d11e 2978 struct mlx5e_priv *out_priv;
592d3651 2979 struct net_device *out_dev;
03a9d11e 2980
73867881 2981 out_dev = act->dev;
ef381359
OS		 2982 if (!out_dev) {
2983 /* out_dev is NULL when filters with
2984 * non-existing mirred device are replayed to
2985 * the driver.
2986 */
2987 return -EINVAL;
2988 }
03a9d11e 2989
592d3651 2990 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2991 NL_SET_ERR_MSG_MOD(extack,
2992 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2993 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2994 attr->out_count);
2995 return -EOPNOTSUPP;
2996 }
2997
f493f155
EB		 2998 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2999 MLX5_FLOW_CONTEXT_ACTION_COUNT;
f6dc1264 3000 if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3001 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3002 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
fa833bd5 3003 struct net_device *uplink_upper;
7ba58ba7 3004
fa833bd5
VB		 3005 rcu_read_lock();
3006 uplink_upper =
3007 netdev_master_upper_dev_get_rcu(uplink_dev);
7ba58ba7
RL		 3008 if (uplink_upper &&
3009 netif_is_lag_master(uplink_upper) &&
3010 uplink_upper == out_dev)
3011 out_dev = uplink_dev;
fa833bd5 3012 rcu_read_unlock();
7ba58ba7 3013
278748a9
EB		 3014 if (is_vlan_dev(out_dev)) {
3015 err = add_vlan_push_action(priv, attr,
3016 &out_dev,
3017 &action);
3018 if (err)
3019 return err;
3020 }
f6dc1264 3021
35a605db
EB		 3022 if (is_vlan_dev(parse_attr->filter_dev)) {
3023 err = add_vlan_pop_action(priv, attr,
3024 &action);
3025 if (err)
3026 return err;
3027 }
278748a9 3028
f6dc1264
PB		 3029 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
3030 NL_SET_ERR_MSG_MOD(extack,
3031 "devices are not on same switch HW, can't offload forwarding");
3032 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3033 priv->netdev->name, out_dev->name);
a0646c88 3034 return -EOPNOTSUPP;
f6dc1264 3035 }
a0646c88 3036
a54e20b4 3037 out_priv = netdev_priv(out_dev);
1d447a39 3038 rpriv = out_priv->ppriv;
df65a573
EB		 3039 attr->dests[attr->out_count].rep = rpriv->rep;
3040 attr->dests[attr->out_count].mdev = out_priv->mdev;
3041 attr->out_count++;
a54e20b4 3042 } else if (encap) {
8c4dc42b
EB		 3043 parse_attr->mirred_ifindex[attr->out_count] =
3044 out_dev->ifindex;
1f6da306 3045 parse_attr->tun_info[attr->out_count] = info;
8c4dc42b 3046 encap = false;
f493f155
EB		 3047 attr->dests[attr->out_count].flags |=
3048 MLX5_ESW_DEST_ENCAP;
1cc26d74 3049 attr->out_count++;
df65a573
EB		 3050 /* attr->dests[].rep is resolved when we
3051 * handle encap
3052 */
ef381359
OS		 3053 } else if (parse_attr->filter_dev != priv->netdev) {
3054 /* All mlx5 devices are called to configure
3055 * high level device filters. Therefore, the
3056 * *attempt* to install a filter on invalid
3057 * eswitch should not trigger an explicit error
3058 */
3059 return -EINVAL;
a54e20b4 3060 } else {
e98bedf5
EB		 3061 NL_SET_ERR_MSG_MOD(extack,
3062 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 3063 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
3064 priv->netdev->name, out_dev->name);
3065 return -EINVAL;
3066 }
73867881
PNA		 3067 }
3068 break;
3069 case FLOW_ACTION_TUNNEL_ENCAP:
3070 info = act->tunnel;
a54e20b4
HHZ		 3071 if (info)
3072 encap = true;
3073 else
3074 return -EOPNOTSUPP;
1482bd3d 3075
73867881
PNA		 3076 break;
3077 case FLOW_ACTION_VLAN_PUSH:
3078 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 3079 if (act->id == FLOW_ACTION_VLAN_PUSH &&
3080 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
3081 /* Replace vlan pop+push with vlan modify */
3082 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3083 err = add_vlan_rewrite_action(priv,
3084 MLX5_FLOW_NAMESPACE_FDB,
3085 act, parse_attr, hdrs,
3086 &action, extack);
3087 } else {
3088 err = parse_tc_vlan_action(priv, act, attr, &action);
3089 }
1482bd3d
JL		 3090 if (err)
3091 return err;
3092
bdc837ee
EB		 3093 attr->split_count = attr->out_count;
3094 break;
3095 case FLOW_ACTION_VLAN_MANGLE:
3096 err = add_vlan_rewrite_action(priv,
3097 MLX5_FLOW_NAMESPACE_FDB,
3098 act, parse_attr, hdrs,
3099 &action, extack);
3100 if (err)
3101 return err;
3102
e85e02ba 3103 attr->split_count = attr->out_count;
73867881
PNA		 3104 break;
3105 case FLOW_ACTION_TUNNEL_DECAP:
1cab1cd7 3106 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
73867881
PNA		 3107 break;
3108 case FLOW_ACTION_GOTO: {
3109 u32 dest_chain = act->chain_index;
bf07aa73
PB		 3110 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
3111
3112 if (dest_chain <= attr->chain) {
3113 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
3114 return -EOPNOTSUPP;
3115 }
3116 if (dest_chain > max_chain) {
3117 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
3118 return -EOPNOTSUPP;
3119 }
e88afe75 3120 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73 3121 attr->dest_chain = dest_chain;
73867881
PNA		 3122 break;
3123 }
3124 default:
2cc1cb1d
TZ		 3125 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3126 return -EOPNOTSUPP;
bf07aa73 3127 }
03a9d11e 3128 }
bdd66ac0 3129
0bac1194
EB		 3130 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
3131 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
3132 /* For prio tag mode, replace vlan pop with rewrite vlan prio
3133 * tag rewrite.
3134 */
3135 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3136 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
3137 &action, extack);
3138 if (err)
3139 return err;
3140 }
3141
c500c86b
PNA		 3142 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3143 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 3144 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 3145 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3146 if (err)
3147 return err;
27c11b6b
EB		 3148 /* in case all pedit actions are skipped, remove the MOD_HDR
3149 * flag. we might have set split_count either by pedit or
3150 * pop/push. if there is no pop/push either, reset it too.
3151 */
3152 if (parse_attr->num_mod_hdr_actions == 0) {
3153 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e7739a60 3154 kfree(parse_attr->mod_hdr_actions);
27c11b6b
EB		 3155 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3156 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3157 attr->split_count = 0;
3158 }
c500c86b
PNA		 3159 }
3160
1cab1cd7 3161 attr->action = action;
73867881 3162 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3163 return -EOPNOTSUPP;
3164
e88afe75
OG		 3165 if (attr->dest_chain) {
3166 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3167 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3168 return -EOPNOTSUPP;
3169 }
3170 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3171 }
3172
e85e02ba 3173 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 3174 NL_SET_ERR_MSG_MOD(extack,
3175 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 3176 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
3177 return -EOPNOTSUPP;
3178 }
3179
31c8eba5 3180 return 0;
03a9d11e
OG		 3181}
3182
226f2ca3 3183static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3184{
226f2ca3 3185 unsigned long __flow_flags = 0;
60bd4af8 3186
226f2ca3
VB		 3187 if (flags & MLX5_TC_FLAG(INGRESS))
3188 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3189 if (flags & MLX5_TC_FLAG(EGRESS))
3190 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3191
226f2ca3
VB		 3192 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3193 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3194 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3195 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
d9ee0491 3196
60bd4af8
OG		 3197 *flow_flags = __flow_flags;
3198}
3199
05866c82
OG		 3200static const struct rhashtable_params tc_ht_params = {
3201 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3202 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3203 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3204 .automatic_shrinking = true,
3205};
3206
226f2ca3
VB		 3207static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3208 unsigned long flags)
05866c82 3209{
655dc3d2
OG		 3210 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3211 struct mlx5e_rep_priv *uplink_rpriv;
3212
226f2ca3 3213 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 3214 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 3215 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 3216 } else /* NIC offload */
655dc3d2 3217 return &priv->fs.tc.ht;
05866c82
OG		 3218}
3219
04de7dda
RD		 3220static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3221{
1418ddd9 3222 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
b05af6aa 3223 bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3224 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3225 bool act_is_encap = !!(attr->action &
3226 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
3227 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
3228 MLX5_DEVCOM_ESW_OFFLOADS);
3229
10fbb1cd
RD		 3230 if (!esw_paired)
3231 return false;
3232
3233 if ((mlx5_lag_is_sriov(attr->in_mdev) ||
3234 mlx5_lag_is_multipath(attr->in_mdev)) &&
3235 (is_rep_ingress || act_is_encap))
3236 return true;
3237
3238 return false;
04de7dda
RD		 3239}
3240
a88780a9
RD		 3241static int
3242mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3243 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3244 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3245 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3246{
17091853 3247 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3248 struct mlx5e_tc_flow *flow;
5a7e5bcb 3249 int out_index, err;
e3a2b7ed 3250
65ba8fb7 3251 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3252 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3253 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3254 err = -ENOMEM;
3255 goto err_free;
3256 }
3257
3258 flow->cookie = f->cookie;
65ba8fb7 3259 flow->flags = flow_flags;
655dc3d2 3260 flow->priv = priv;
5a7e5bcb
VB		 3261 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3262 INIT_LIST_HEAD(&flow->encaps[out_index].list);
3263 INIT_LIST_HEAD(&flow->mod_hdr);
3264 INIT_LIST_HEAD(&flow->hairpin);
3265 refcount_set(&flow->refcnt, 1);
e3a2b7ed 3266
a88780a9
RD		 3267 *__flow = flow;
3268 *__parse_attr = parse_attr;
3269
3270 return 0;
3271
3272err_free:
3273 kfree(flow);
3274 kvfree(parse_attr);
3275 return err;
3276}
3277
988ab9c7
TZ		 3278static void
3279mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr,
3280 struct mlx5e_priv *priv,
3281 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3282 struct flow_cls_offload *f,
988ab9c7
TZ		 3283 struct mlx5_eswitch_rep *in_rep,
3284 struct mlx5_core_dev *in_mdev)
3285{
3286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3287
3288 esw_attr->parse_attr = parse_attr;
3289 esw_attr->chain = f->common.chain_index;
3290 esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
3291
3292 esw_attr->in_rep = in_rep;
3293 esw_attr->in_mdev = in_mdev;
3294
3295 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3296 MLX5_COUNTER_SOURCE_ESWITCH)
3297 esw_attr->counter_dev = in_mdev;
3298 else
3299 esw_attr->counter_dev = priv->mdev;
3300}
3301
71129676 3302static struct mlx5e_tc_flow *
04de7dda 3303__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3304 struct flow_cls_offload *f,
226f2ca3 3305 unsigned long flow_flags,
04de7dda
RD		 3306 struct net_device *filter_dev,
3307 struct mlx5_eswitch_rep *in_rep,
71129676 3308 struct mlx5_core_dev *in_mdev)
a88780a9 3309{
f9e30088 3310 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3311 struct netlink_ext_ack *extack = f->common.extack;
3312 struct mlx5e_tc_flow_parse_attr *parse_attr;
3313 struct mlx5e_tc_flow *flow;
3314 int attr_size, err;
e3a2b7ed 3315
226f2ca3 3316 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3317 attr_size = sizeof(struct mlx5_esw_flow_attr);
3318 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3319 &parse_attr, &flow);
3320 if (err)
3321 goto out;
988ab9c7 3322
d11afc26 3323 parse_attr->filter_dev = filter_dev;
988ab9c7
TZ		 3324 mlx5e_flow_esw_attr_init(flow->esw_attr,
3325 priv, parse_attr,
3326 f, in_rep, in_mdev);
3327
54c177ca
OS		 3328 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3329 f, filter_dev);
d11afc26
OS		 3330 if (err)
3331 goto err_free;
a88780a9 3332
6f9af8ff 3333 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3334 if (err)
3335 goto err_free;
3336
7040632d 3337 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
ef06c9ee
RD		 3338 if (err) {
3339 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3340 goto err_free;
3341
b4a23329 3342 add_unready_flow(flow);
ef06c9ee 3343 }
e3a2b7ed 3344
71129676 3345 return flow;
a88780a9
RD		 3346
3347err_free:
5a7e5bcb 3348 mlx5e_flow_put(priv, flow);
a88780a9 3349out:
71129676 3350 return ERR_PTR(err);
a88780a9
RD		 3351}
3352
f9e30088 3353static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3354 struct mlx5e_tc_flow *flow,
226f2ca3 3355 unsigned long flow_flags)
04de7dda
RD		 3356{
3357 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3358 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
3359 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3360 struct mlx5e_tc_flow_parse_attr *parse_attr;
3361 struct mlx5e_rep_priv *peer_urpriv;
3362 struct mlx5e_tc_flow *peer_flow;
3363 struct mlx5_core_dev *in_mdev;
3364 int err = 0;
3365
3366 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3367 if (!peer_esw)
3368 return -ENODEV;
3369
3370 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3371 peer_priv = netdev_priv(peer_urpriv->netdev);
3372
3373 /* in_mdev is assigned of which the packet originated from.
3374 * So packets redirected to uplink use the same mdev of the
3375 * original flow and packets redirected from uplink use the
3376 * peer mdev.
3377 */
b05af6aa 3378 if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3379 in_mdev = peer_priv->mdev;
3380 else
3381 in_mdev = priv->mdev;
3382
3383 parse_attr = flow->esw_attr->parse_attr;
95dc1902 3384 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676
JG		 3385 parse_attr->filter_dev,
3386 flow->esw_attr->in_rep, in_mdev);
3387 if (IS_ERR(peer_flow)) {
3388 err = PTR_ERR(peer_flow);
04de7dda 3389 goto out;
71129676 3390 }
04de7dda
RD		 3391
3392 flow->peer_flow = peer_flow;
226f2ca3 3393 flow_flag_set(flow, DUP);
04de7dda
RD		 3394 mutex_lock(&esw->offloads.peer_mutex);
3395 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3396 mutex_unlock(&esw->offloads.peer_mutex);
3397
3398out:
3399 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3400 return err;
3401}
3402
3403static int
3404mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3405 struct flow_cls_offload *f,
226f2ca3 3406 unsigned long flow_flags,
04de7dda
RD		 3407 struct net_device *filter_dev,
3408 struct mlx5e_tc_flow **__flow)
3409{
3410 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3411 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3412 struct mlx5_core_dev *in_mdev = priv->mdev;
3413 struct mlx5e_tc_flow *flow;
3414 int err;
3415
71129676
JG		 3416 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3417 in_mdev);
3418 if (IS_ERR(flow))
3419 return PTR_ERR(flow);
04de7dda
RD		 3420
3421 if (is_peer_flow_needed(flow)) {
95dc1902 3422 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3423 if (err) {
3424 mlx5e_tc_del_fdb_flow(priv, flow);
3425 goto out;
3426 }
3427 }
3428
3429 *__flow = flow;
3430
3431 return 0;
3432
3433out:
3434 return err;
3435}
3436
a88780a9
RD		 3437static int
3438mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3439 struct flow_cls_offload *f,
226f2ca3 3440 unsigned long flow_flags,
d11afc26 3441 struct net_device *filter_dev,
a88780a9
RD		 3442 struct mlx5e_tc_flow **__flow)
3443{
f9e30088 3444 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3445 struct netlink_ext_ack *extack = f->common.extack;
3446 struct mlx5e_tc_flow_parse_attr *parse_attr;
3447 struct mlx5e_tc_flow *flow;
3448 int attr_size, err;
3449
bf07aa73
PB		 3450 /* multi-chain not supported for NIC rules */
3451 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3452 return -EOPNOTSUPP;
3453
226f2ca3 3454 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3455 attr_size = sizeof(struct mlx5_nic_flow_attr);
3456 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3457 &parse_attr, &flow);
3458 if (err)
3459 goto out;
3460
d11afc26 3461 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 3462 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3463 f, filter_dev);
d11afc26
OS		 3464 if (err)
3465 goto err_free;
3466
73867881 3467 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 3468 if (err)
3469 goto err_free;
3470
3471 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3472 if (err)
3473 goto err_free;
3474
226f2ca3 3475 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3476 kvfree(parse_attr);
3477 *__flow = flow;
3478
3479 return 0;
e3a2b7ed 3480
e3a2b7ed 3481err_free:
5a7e5bcb 3482 mlx5e_flow_put(priv, flow);
17091853 3483 kvfree(parse_attr);
a88780a9
RD		 3484out:
3485 return err;
3486}
3487
3488static int
3489mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3490 struct flow_cls_offload *f,
226f2ca3 3491 unsigned long flags,
d11afc26 3492 struct net_device *filter_dev,
a88780a9
RD		 3493 struct mlx5e_tc_flow **flow)
3494{
3495 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3496 unsigned long flow_flags;
a88780a9
RD		 3497 int err;
3498
3499 get_flags(flags, &flow_flags);
3500
bf07aa73
PB		 3501 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3502 return -EOPNOTSUPP;
3503
f6455de0 3504 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3505 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3506 filter_dev, flow);
a88780a9 3507 else
d11afc26
OS		 3508 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3509 filter_dev, flow);
a88780a9
RD		 3510
3511 return err;
3512}
3513
71d82d2a 3514int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3515 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3516{
3517 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3518 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 3519 struct mlx5e_tc_flow *flow;
3520 int err = 0;
3521
c5d326b2
VB		 3522 rcu_read_lock();
3523 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
3524 rcu_read_unlock();
a88780a9
RD		 3525 if (flow) {
3526 NL_SET_ERR_MSG_MOD(extack,
3527 "flow cookie already exists, ignoring");
3528 netdev_warn_once(priv->netdev,
3529 "flow cookie %lx already exists, ignoring\n",
3530 f->cookie);
0e1c1a2f 3531 err = -EEXIST;
a88780a9
RD		 3532 goto out;
3533 }
3534
d11afc26 3535 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3536 if (err)
3537 goto out;
3538
c5d326b2 3539 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 3540 if (err)
3541 goto err_free;
3542
3543 return 0;
3544
3545err_free:
5a7e5bcb 3546 mlx5e_flow_put(priv, flow);
a88780a9 3547out:
e3a2b7ed
AV		 3548 return err;
3549}
3550
8f8ae895
OG		 3551static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3552{
226f2ca3
VB		 3553 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
3554 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 3555
226f2ca3
VB		 3556 return flow_flag_test(flow, INGRESS) == dir_ingress &&
3557 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 3558}
3559
71d82d2a 3560int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3561 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 3562{
d9ee0491 3563 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3564 struct mlx5e_tc_flow *flow;
c5d326b2 3565 int err;
e3a2b7ed 3566
c5d326b2 3567 rcu_read_lock();
05866c82 3568 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 3569 if (!flow || !same_flow_direction(flow, flags)) {
3570 err = -EINVAL;
3571 goto errout;
3572 }
e3a2b7ed 3573
c5d326b2
VB		 3574 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
3575 * set.
3576 */
3577 if (flow_flag_test_and_set(flow, DELETED)) {
3578 err = -EINVAL;
3579 goto errout;
3580 }
05866c82 3581 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 3582 rcu_read_unlock();
e3a2b7ed 3583
5a7e5bcb 3584 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 3585
3586 return 0;
c5d326b2
VB		 3587
3588errout:
3589 rcu_read_unlock();
3590 return err;
e3a2b7ed
AV		 3591}
3592
71d82d2a 3593int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3594 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 3595{
04de7dda 3596 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3597 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3598 struct mlx5_eswitch *peer_esw;
aad7e08d 3599 struct mlx5e_tc_flow *flow;
aad7e08d 3600 struct mlx5_fc *counter;
316d5f72
RD		 3601 u64 lastuse = 0;
3602 u64 packets = 0;
3603 u64 bytes = 0;
5a7e5bcb 3604 int err = 0;
aad7e08d 3605
c5d326b2
VB		 3606 rcu_read_lock();
3607 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
3608 tc_ht_params));
3609 rcu_read_unlock();
5a7e5bcb
VB		 3610 if (IS_ERR(flow))
3611 return PTR_ERR(flow);
3612
3613 if (!same_flow_direction(flow, flags)) {
3614 err = -EINVAL;
3615 goto errout;
3616 }
aad7e08d 3617
226f2ca3 3618 if (mlx5e_is_offloaded_flow(flow)) {
316d5f72
RD		 3619 counter = mlx5e_tc_get_counter(flow);
3620 if (!counter)
5a7e5bcb 3621 goto errout;
aad7e08d 3622
316d5f72
RD		 3623 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3624 }
aad7e08d 3625
316d5f72
RD		 3626 /* Under multipath it's possible for one rule to be currently
3627 * un-offloaded while the other rule is offloaded.
3628 */
04de7dda
RD		 3629 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3630 if (!peer_esw)
3631 goto out;
3632
226f2ca3
VB		 3633 if (flow_flag_test(flow, DUP) &&
3634 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 3635 u64 bytes2;
3636 u64 packets2;
3637 u64 lastuse2;
3638
3639 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 3640 if (!counter)
3641 goto no_peer_counter;
04de7dda
RD		 3642 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3643
3644 bytes += bytes2;
3645 packets += packets2;
3646 lastuse = max_t(u64, lastuse, lastuse2);
3647 }
3648
316d5f72 3649no_peer_counter:
04de7dda 3650 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 3651out:
3b1903ef 3652 flow_stats_update(&f->stats, bytes, packets, lastuse);
5a7e5bcb
VB		 3653errout:
3654 mlx5e_flow_put(priv, flow);
3655 return err;
aad7e08d
AV		 3656}
3657
fcb64c0f
EC		 3658static int apply_police_params(struct mlx5e_priv *priv, u32 rate,
3659 struct netlink_ext_ack *extack)
3660{
3661 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3662 struct mlx5_eswitch *esw;
3663 u16 vport_num;
3664 u32 rate_mbps;
3665 int err;
3666
3667 esw = priv->mdev->priv.eswitch;
3668 /* rate is given in bytes/sec.
3669 * First convert to bits/sec and then round to the nearest mbit/secs.
3670 * mbit means million bits.
3671 * Moreover, if rate is non zero we choose to configure to a minimum of
3672 * 1 mbit/sec.
3673 */
3674 rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0;
3675 vport_num = rpriv->rep->vport;
3676
3677 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
3678 if (err)
3679 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
3680
3681 return err;
3682}
3683
3684static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
3685 struct flow_action *flow_action,
3686 struct netlink_ext_ack *extack)
3687{
3688 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3689 const struct flow_action_entry *act;
3690 int err;
3691 int i;
3692
3693 if (!flow_action_has_entries(flow_action)) {
3694 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
3695 return -EINVAL;
3696 }
3697
3698 if (!flow_offload_has_one_action(flow_action)) {
3699 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
3700 return -EOPNOTSUPP;
3701 }
3702
3703 flow_action_for_each(i, act, flow_action) {
3704 switch (act->id) {
3705 case FLOW_ACTION_POLICE:
3706 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
3707 if (err)
3708 return err;
3709
3710 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
3711 break;
3712 default:
3713 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
3714 return -EOPNOTSUPP;
3715 }
3716 }
3717
3718 return 0;
3719}
3720
3721int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
3722 struct tc_cls_matchall_offload *ma)
3723{
3724 struct netlink_ext_ack *extack = ma->common.extack;
3725 int prio = TC_H_MAJ(ma->common.prio) >> 16;
3726
3727 if (prio != 1) {
3728 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
3729 return -EINVAL;
3730 }
3731
3732 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
3733}
3734
3735int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
3736 struct tc_cls_matchall_offload *ma)
3737{
3738 struct netlink_ext_ack *extack = ma->common.extack;
3739
3740 return apply_police_params(priv, 0, extack);
3741}
3742
3743void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
3744 struct tc_cls_matchall_offload *ma)
3745{
3746 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3747 struct rtnl_link_stats64 cur_stats;
3748 u64 dbytes;
3749 u64 dpkts;
3750
3751 cur_stats = priv->stats.vf_vport;
3752 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
3753 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
3754 rpriv->prev_vf_vport_stats = cur_stats;
3755 flow_stats_update(&ma->stats, dpkts, dbytes, jiffies);
3756}
3757
4d8fcf21
AH		 3758static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3759 struct mlx5e_priv *peer_priv)
3760{
3761 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3762 struct mlx5e_hairpin_entry *hpe;
3763 u16 peer_vhca_id;
3764 int bkt;
3765
3766 if (!same_hw_devs(priv, peer_priv))
3767 return;
3768
3769 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3770
3771 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3772 if (hpe->peer_vhca_id == peer_vhca_id)
3773 hpe->hp->pair->peer_gone = true;
3774 }
3775}
3776
3777static int mlx5e_tc_netdev_event(struct notifier_block *this,
3778 unsigned long event, void *ptr)
3779{
3780 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3781 struct mlx5e_flow_steering *fs;
3782 struct mlx5e_priv *peer_priv;
3783 struct mlx5e_tc_table *tc;
3784 struct mlx5e_priv *priv;
3785
3786 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3787 event != NETDEV_UNREGISTER ||
3788 ndev->reg_state == NETREG_REGISTERED)
3789 return NOTIFY_DONE;
3790
3791 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3792 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3793 priv = container_of(fs, struct mlx5e_priv, fs);
3794 peer_priv = netdev_priv(ndev);
3795 if (priv == peer_priv ||
3796 !(priv->netdev->features & NETIF_F_HW_TC))
3797 return NOTIFY_DONE;
3798
3799 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3800
3801 return NOTIFY_DONE;
3802}
3803
655dc3d2 3804int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3805{
acff797c 3806 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3807 int err;
e8f887ac 3808
b6fac0b4 3809 mutex_init(&tc->t_lock);
11c9c548 3810 hash_init(tc->mod_hdr_tbl);
5c65c564 3811 hash_init(tc->hairpin_tbl);
11c9c548 3812
4d8fcf21
AH		 3813 err = rhashtable_init(&tc->ht, &tc_ht_params);
3814 if (err)
3815 return err;
3816
3817 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3818 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3819 tc->netdevice_nb.notifier_call = NULL;
3820 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3821 }
3822
3823 return err;
e8f887ac
AV		 3824}
3825
3826static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3827{
3828 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3829 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3830
961e8979 3831 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3832 kfree(flow);
3833}
3834
655dc3d2 3835void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3836{
acff797c 3837 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3838
4d8fcf21
AH		 3839 if (tc->netdevice_nb.notifier_call)
3840 unregister_netdevice_notifier(&tc->netdevice_nb);
3841
d9ee0491 3842 rhashtable_destroy(&tc->ht);
e8f887ac 3843
acff797c
MG		 3844 if (!IS_ERR_OR_NULL(tc->t)) {
3845 mlx5_destroy_flow_table(tc->t);
3846 tc->t = NULL;
e8f887ac 3847 }
b6fac0b4 3848 mutex_destroy(&tc->t_lock);
e8f887ac 3849}
655dc3d2
OG		 3850
3851int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3852{
3853 return rhashtable_init(tc_ht, &tc_ht_params);
3854}
3855
3856void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3857{
3858 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3859}
01252a27 3860
226f2ca3 3861int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 3862{
d9ee0491 3863 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3864
3865 return atomic_read(&tc_ht->nelems);
3866}
04de7dda
RD		 3867
3868void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3869{
3870 struct mlx5e_tc_flow *flow, *tmp;
3871
3872 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3873 __mlx5e_tc_del_fdb_peer_flow(flow);
3874}
b4a23329
RD		 3875
3876void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
3877{
3878 struct mlx5_rep_uplink_priv *rpriv =
3879 container_of(work, struct mlx5_rep_uplink_priv,
3880 reoffload_flows_work);
3881 struct mlx5e_tc_flow *flow, *tmp;
3882
ad86755b 3883 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 3884 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
3885 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 3886 unready_flow_del(flow);
b4a23329 3887 }
ad86755b 3888 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 3889}
Linux 6.x block layer and io_uring tree(s)