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net/mlx5e: Remove redundant match on tunnel destination mac
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed
AV		 36#include <net/pkt_cls.h>
37#include <net/tc_act/tc_gact.h>
12185a9f 38#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 39#include <linux/mlx5/fs.h>
40#include <linux/mlx5/device.h>
41#include <linux/rhashtable.h>
5a7e5bcb 42#include <linux/refcount.h>
db76ca24 43#include <linux/completion.h>
03a9d11e 44#include <net/tc_act/tc_mirred.h>
776b12b6 45#include <net/tc_act/tc_vlan.h>
bbd00f7e 46#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 47#include <net/tc_act/tc_pedit.h>
26c02749 48#include <net/tc_act/tc_csum.h>
14e6b038 49#include <net/tc_act/tc_mpls.h>
f6dfb4c3 50#include <net/arp.h>
3616d08b 51#include <net/ipv6_stubs.h>
f828ca6a 52#include <net/bareudp.h>
d34eb2fc 53#include <net/bonding.h>
e8f887ac 54#include "en.h"
1d447a39 55#include "en_rep.h"
768c3667 56#include "en/rep/tc.h"
e2394a61 57#include "en/rep/neigh.h"
232c0013 58#include "en_tc.h"
03a9d11e 59#include "eswitch.h"
3f6d08d1 60#include "fs_core.h"
2c81bfd5 61#include "en/port.h"
101f4de9 62#include "en/tc_tun.h"
0a7fcb78 63#include "en/mapping.h"
4c3844d9 64#include "en/tc_ct.h"
b2fdf3d0 65#include "en/mod_hdr.h"
04de7dda 66#include "lib/devcom.h"
9272e3df 67#include "lib/geneve.h"
ae430332 68#include "lib/fs_chains.h"
7a978759 69#include "diag/en_tc_tracepoint.h"
1fe3e316 70#include <asm/div64.h>
e8f887ac 71
6a064674 72#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 73#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
226f2ca3 74#define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1)
60bd4af8 75
65ba8fb7 76enum {
226f2ca3
VB		 77 MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT,
78 MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT,
79 MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT,
84179981 80 MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT,
226f2ca3
VB		 81 MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT,
82 MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE,
83 MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1,
84 MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2,
85 MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3,
86 MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4,
87 MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5,
c5d326b2 88 MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6,
4c3844d9 89 MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7,
14e6b038 90 MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8,
65ba8fb7
OG		 91};
92
e4ad91f2
CM		 93#define MLX5E_TC_MAX_SPLITS 1
94
79baaec7
EB		 95/* Helper struct for accessing a struct containing list_head array.
96 * Containing struct
97 * |- Helper array
98 * [0] Helper item 0
99 * |- list_head item 0
100 * |- index (0)
101 * [1] Helper item 1
102 * |- list_head item 1
103 * |- index (1)
104 * To access the containing struct from one of the list_head items:
105 * 1. Get the helper item from the list_head item using
106 * helper item =
107 * container_of(list_head item, helper struct type, list_head field)
108 * 2. Get the contining struct from the helper item and its index in the array:
109 * containing struct =
110 * container_of(helper item, containing struct type, helper field[index])
111 */
112struct encap_flow_item {
948993f2 113 struct mlx5e_encap_entry *e; /* attached encap instance */
79baaec7
EB		 114 struct list_head list;
115 int index;
116};
117
e8f887ac
AV		 118struct mlx5e_tc_flow {
119 struct rhash_head node;
655dc3d2 120 struct mlx5e_priv *priv;
e8f887ac 121 u64 cookie;
226f2ca3 122 unsigned long flags;
e4ad91f2 123 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
14e6b038
EC		 124
125 /* flows sharing the same reformat object - currently mpls decap */
126 struct list_head l3_to_l2_reformat;
127 struct mlx5e_decap_entry *decap_reformat;
128
79baaec7
EB		 129 /* Flow can be associated with multiple encap IDs.
130 * The number of encaps is bounded by the number of supported
131 * destinations.
132 */
133 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 134 struct mlx5e_tc_flow *peer_flow;
b2fdf3d0 135 struct mlx5e_mod_hdr_handle *mh; /* attached mod header instance */
e4f9abbd 136 struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */
5c65c564 137 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 138 struct list_head peer; /* flows with peer flow */
b4a23329 139 struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */
553f9328 140 struct net_device *orig_dev; /* netdev adding flow first */
2a1f1768 141 int tmp_efi_index;
6a06c2f7 142 struct list_head tmp_list; /* temporary flow list used by neigh update */
5a7e5bcb 143 refcount_t refcnt;
c5d326b2 144 struct rcu_head rcu_head;
95435ad7 145 struct completion init_done;
0a7fcb78 146 int tunnel_id; /* the mapped tunnel id of this flow */
c620b772 147 struct mlx5_flow_attr *attr;
e8f887ac
AV		 148};
149
17091853 150struct mlx5e_tc_flow_parse_attr {
1f6da306 151 const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 152 struct net_device *filter_dev;
17091853 153 struct mlx5_flow_spec spec;
6ae4a6a5 154 struct mlx5e_tc_mod_hdr_acts mod_hdr_acts;
98b66cb1 155 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
14e6b038 156 struct ethhdr eth;
17091853
OG		 157};
158
acff797c 159#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 160#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 161
8f1e0b97
PB		 162struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
163 [CHAIN_TO_REG] = {
164 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
165 .moffset = 0,
166 .mlen = 2,
167 },
10742efc
VB		 168 [VPORT_TO_REG] = {
169 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
170 .moffset = 2,
171 .mlen = 2,
172 },
0a7fcb78
PB		 173 [TUNNEL_TO_REG] = {
174 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
d12f4521
PB		 175 .moffset = 1,
176 .mlen = 3,
0a7fcb78
PB		 177 .soffset = MLX5_BYTE_OFF(fte_match_param,
178 misc_parameters_2.metadata_reg_c_1),
179 },
4c3844d9 180 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 181 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 182 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
183 [MARK_TO_REG] = mark_to_reg_ct,
184 [LABELS_TO_REG] = labels_to_reg_ct,
185 [FTEID_TO_REG] = fteid_to_reg_ct,
c7569097
AL		 186 /* For NIC rules we store the retore metadata directly
187 * into reg_b that is passed to SW since we don't
188 * jump between steering domains.
189 */
190 [NIC_CHAIN_TO_REG] = {
191 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
192 .moffset = 0,
193 .mlen = 2,
194 },
aedd133d 195 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 196};
197
9ba33339
RD		 198/* To avoid false lock dependency warning set the tc_ht lock
199 * class different than the lock class of the ht being used when deleting
200 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
201 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
202 * it's different than the ht->mutex here.
203 */
204static struct lock_class_key tc_ht_lock_key;
205
0a7fcb78
PB		 206static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
207
208void
209mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
210 enum mlx5e_tc_attr_to_reg type,
211 u32 data,
212 u32 mask)
213{
214 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
215 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
216 void *headers_c = spec->match_criteria;
217 void *headers_v = spec->match_value;
218 void *fmask, *fval;
219
220 fmask = headers_c + soffset;
221 fval = headers_v + soffset;
222
58ff18e1
SM		 223 mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8));
224 data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8));
0a7fcb78
PB		 225
226 memcpy(fmask, &mask, match_len);
227 memcpy(fval, &data, match_len);
228
229 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
230}
231
7e36feeb
PB		 232void
233mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
234 enum mlx5e_tc_attr_to_reg type,
235 u32 *data,
236 u32 *mask)
237{
238 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
239 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
240 void *headers_c = spec->match_criteria;
241 void *headers_v = spec->match_value;
242 void *fmask, *fval;
243
244 fmask = headers_c + soffset;
245 fval = headers_v + soffset;
246
247 memcpy(mask, fmask, match_len);
248 memcpy(data, fval, match_len);
249
250 *mask = be32_to_cpu((__force __be32)(*mask << (32 - (match_len * 8))));
251 *data = be32_to_cpu((__force __be32)(*data << (32 - (match_len * 8))));
252}
253
0a7fcb78
PB		 254int
255mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
256 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
aedd133d 257 enum mlx5_flow_namespace_type ns,
0a7fcb78
PB		 258 enum mlx5e_tc_attr_to_reg type,
259 u32 data)
260{
261 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
262 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
263 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
264 char *modact;
265 int err;
266
aedd133d 267 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 268 if (err)
269 return err;
270
271 modact = mod_hdr_acts->actions +
272 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
273
274 /* Firmware has 5bit length field and 0 means 32bits */
275 if (mlen == 4)
276 mlen = 0;
277
278 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
279 MLX5_SET(set_action_in, modact, field, mfield);
280 MLX5_SET(set_action_in, modact, offset, moffset * 8);
281 MLX5_SET(set_action_in, modact, length, mlen * 8);
282 MLX5_SET(set_action_in, modact, data, data);
283 mod_hdr_acts->num_actions++;
284
285 return 0;
286}
287
aedd133d
AL		 288static struct mlx5_tc_ct_priv *
289get_ct_priv(struct mlx5e_priv *priv)
290{
291 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
292 struct mlx5_rep_uplink_priv *uplink_priv;
293 struct mlx5e_rep_priv *uplink_rpriv;
294
e8711402 295 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 296 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
297 uplink_priv = &uplink_rpriv->uplink_priv;
298
299 return uplink_priv->ct_priv;
300 }
301
302 return priv->fs.tc.ct;
303}
304
305struct mlx5_flow_handle *
306mlx5_tc_rule_insert(struct mlx5e_priv *priv,
307 struct mlx5_flow_spec *spec,
308 struct mlx5_flow_attr *attr)
309{
310 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
311
e8711402 312 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 313 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
314
315 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
316}
317
318void
319mlx5_tc_rule_delete(struct mlx5e_priv *priv,
320 struct mlx5_flow_handle *rule,
321 struct mlx5_flow_attr *attr)
322{
323 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
324
e8711402 325 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 326 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
327
328 return;
329 }
330
331 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
332}
333
77ab67b7
OG		 334struct mlx5e_hairpin {
335 struct mlx5_hairpin *pair;
336
337 struct mlx5_core_dev *func_mdev;
3f6d08d1 338 struct mlx5e_priv *func_priv;
77ab67b7
OG		 339 u32 tdn;
340 u32 tirn;
3f6d08d1
OG		 341
342 int num_channels;
343 struct mlx5e_rqt indir_rqt;
344 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
345 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 346};
347
5c65c564
OG		 348struct mlx5e_hairpin_entry {
349 /* a node of a hash table which keeps all the hairpin entries */
350 struct hlist_node hairpin_hlist;
351
73edca73
VB		 352 /* protects flows list */
353 spinlock_t flows_lock;
5c65c564
OG		 354 /* flows sharing the same hairpin */
355 struct list_head flows;
db76ca24
VB		 356 /* hpe's that were not fully initialized when dead peer update event
357 * function traversed them.
358 */
359 struct list_head dead_peer_wait_list;
5c65c564 360
d8822868 361 u16 peer_vhca_id;
106be53b 362 u8 prio;
5c65c564 363 struct mlx5e_hairpin *hp;
e4f9abbd 364 refcount_t refcnt;
db76ca24 365 struct completion res_ready;
5c65c564
OG		 366};
367
5a7e5bcb
VB		 368static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
369 struct mlx5e_tc_flow *flow);
370
371static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
372{
373 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
374 return ERR_PTR(-EINVAL);
375 return flow;
376}
377
378static void mlx5e_flow_put(struct mlx5e_priv *priv,
379 struct mlx5e_tc_flow *flow)
380{
381 if (refcount_dec_and_test(&flow->refcnt)) {
382 mlx5e_tc_del_flow(priv, flow);
c5d326b2 383 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 384 }
385}
386
226f2ca3
VB		 387static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag)
388{
389 /* Complete all memory stores before setting bit. */
390 smp_mb__before_atomic();
391 set_bit(flag, &flow->flags);
392}
393
394#define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag)
395
c5d326b2
VB		 396static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow,
397 unsigned long flag)
398{
399 /* test_and_set_bit() provides all necessary barriers */
400 return test_and_set_bit(flag, &flow->flags);
401}
402
403#define flow_flag_test_and_set(flow, flag) \
404 __flow_flag_test_and_set(flow, \
405 MLX5E_TC_FLOW_FLAG_##flag)
406
226f2ca3
VB		 407static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag)
408{
409 /* Complete all memory stores before clearing bit. */
410 smp_mb__before_atomic();
411 clear_bit(flag, &flow->flags);
412}
413
414#define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \
415 MLX5E_TC_FLOW_FLAG_##flag)
416
417static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag)
418{
419 bool ret = test_bit(flag, &flow->flags);
420
421 /* Read fields of flow structure only after checking flags. */
422 smp_mb__after_atomic();
423 return ret;
424}
425
426#define flow_flag_test(flow, flag) __flow_flag_test(flow, \
427 MLX5E_TC_FLOW_FLAG_##flag)
428
aedd133d 429bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 430{
431 return flow_flag_test(flow, ESWITCH);
432}
433
84179981
PB		 434static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
435{
436 return flow_flag_test(flow, FT);
437}
438
226f2ca3
VB		 439static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
440{
441 return flow_flag_test(flow, OFFLOADED);
442}
443
b2fdf3d0 444static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 445{
b2fdf3d0
PB		 446 return mlx5e_is_eswitch_flow(flow) ?
447 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 448}
449
dd58edc3 450static struct mod_hdr_tbl *
b2fdf3d0 451get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 452{
453 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
454
b2fdf3d0
PB		 455 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
456 &esw->offloads.mod_hdr :
dd58edc3
VB		 457 &priv->fs.tc.mod_hdr;
458}
459
11c9c548
OG		 460static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
461 struct mlx5e_tc_flow *flow,
462 struct mlx5e_tc_flow_parse_attr *parse_attr)
463{
b2fdf3d0
PB		 464 struct mlx5_modify_hdr *modify_hdr;
465 struct mlx5e_mod_hdr_handle *mh;
11c9c548 466
b2fdf3d0
PB		 467 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
468 get_flow_name_space(flow),
469 &parse_attr->mod_hdr_acts);
470 if (IS_ERR(mh))
471 return PTR_ERR(mh);
11c9c548 472
b2fdf3d0 473 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 474 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 475 flow->mh = mh;
11c9c548
OG		 476
477 return 0;
11c9c548
OG		 478}
479
480static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
481 struct mlx5e_tc_flow *flow)
482{
5a7e5bcb 483 /* flow wasn't fully initialized */
dd58edc3 484 if (!flow->mh)
5a7e5bcb
VB		 485 return;
486
b2fdf3d0
PB		 487 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
488 flow->mh);
dd58edc3 489 flow->mh = NULL;
11c9c548
OG		 490}
491
77ab67b7
OG		 492static
493struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
494{
495 struct net_device *netdev;
496 struct mlx5e_priv *priv;
497
498 netdev = __dev_get_by_index(net, ifindex);
499 priv = netdev_priv(netdev);
500 return priv->mdev;
501}
502
503static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
504{
e0b4b472 505 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {};
77ab67b7
OG		 506 void *tirc;
507 int err;
508
509 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
510 if (err)
511 goto alloc_tdn_err;
512
513 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
514
515 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 516 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 517 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
518
e0b4b472 519 err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn);
77ab67b7
OG		 520 if (err)
521 goto create_tir_err;
522
523 return 0;
524
525create_tir_err:
526 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
527alloc_tdn_err:
528 return err;
529}
530
531static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
532{
533 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
534 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
535}
536
3f6d08d1
OG		 537static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
538{
539 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
540 struct mlx5e_priv *priv = hp->func_priv;
541 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
542
543 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
544 hp->num_channels);
545
546 for (i = 0; i < sz; i++) {
547 ix = i;
bbeb53b8 548 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 549 ix = mlx5e_bits_invert(i, ilog2(sz));
550 ix = indirection_rqt[ix];
551 rqn = hp->pair->rqn[ix];
552 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
553 }
554}
555
556static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
557{
558 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
559 struct mlx5e_priv *priv = hp->func_priv;
560 struct mlx5_core_dev *mdev = priv->mdev;
561 void *rqtc;
562 u32 *in;
563
564 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
565 in = kvzalloc(inlen, GFP_KERNEL);
566 if (!in)
567 return -ENOMEM;
568
569 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
570
571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
572 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
573
574 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
575
576 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
577 if (!err)
578 hp->indir_rqt.enabled = true;
579
580 kvfree(in);
581 return err;
582}
583
584static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
585{
586 struct mlx5e_priv *priv = hp->func_priv;
587 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
588 int tt, i, err;
589 void *tirc;
590
591 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 592 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
593
3f6d08d1
OG		 594 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
595 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
596
597 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
598 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
599 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 600 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
601
3f6d08d1 602 err = mlx5_core_create_tir(hp->func_mdev, in,
e0b4b472 603 &hp->indir_tirn[tt]);
3f6d08d1
OG		 604 if (err) {
605 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
606 goto err_destroy_tirs;
607 }
608 }
609 return 0;
610
611err_destroy_tirs:
612 for (i = 0; i < tt; i++)
613 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
614 return err;
615}
616
617static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
618{
619 int tt;
620
621 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
622 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
623}
624
625static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
626 struct ttc_params *ttc_params)
627{
628 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
629 int tt;
630
631 memset(ttc_params, 0, sizeof(*ttc_params));
632
633 ttc_params->any_tt_tirn = hp->tirn;
634
635 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
636 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
637
6412bb39 638 ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE;
3f6d08d1
OG		 639 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
640 ft_attr->prio = MLX5E_TC_PRIO;
641}
642
643static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
644{
645 struct mlx5e_priv *priv = hp->func_priv;
646 struct ttc_params ttc_params;
647 int err;
648
649 err = mlx5e_hairpin_create_indirect_rqt(hp);
650 if (err)
651 return err;
652
653 err = mlx5e_hairpin_create_indirect_tirs(hp);
654 if (err)
655 goto err_create_indirect_tirs;
656
657 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
658 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
659 if (err)
660 goto err_create_ttc_table;
661
662 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
663 hp->num_channels, hp->ttc.ft.t->id);
664
665 return 0;
666
667err_create_ttc_table:
668 mlx5e_hairpin_destroy_indirect_tirs(hp);
669err_create_indirect_tirs:
670 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
671
672 return err;
673}
674
675static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
676{
677 struct mlx5e_priv *priv = hp->func_priv;
678
679 mlx5e_destroy_ttc_table(priv, &hp->ttc);
680 mlx5e_hairpin_destroy_indirect_tirs(hp);
681 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
682}
683
77ab67b7
OG		 684static struct mlx5e_hairpin *
685mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
686 int peer_ifindex)
687{
688 struct mlx5_core_dev *func_mdev, *peer_mdev;
689 struct mlx5e_hairpin *hp;
690 struct mlx5_hairpin *pair;
691 int err;
692
693 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
694 if (!hp)
695 return ERR_PTR(-ENOMEM);
696
697 func_mdev = priv->mdev;
698 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
699
700 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
701 if (IS_ERR(pair)) {
702 err = PTR_ERR(pair);
703 goto create_pair_err;
704 }
705 hp->pair = pair;
706 hp->func_mdev = func_mdev;
3f6d08d1
OG		 707 hp->func_priv = priv;
708 hp->num_channels = params->num_channels;
77ab67b7
OG		 709
710 err = mlx5e_hairpin_create_transport(hp);
711 if (err)
712 goto create_transport_err;
713
3f6d08d1
OG		 714 if (hp->num_channels > 1) {
715 err = mlx5e_hairpin_rss_init(hp);
716 if (err)
717 goto rss_init_err;
718 }
719
77ab67b7
OG		 720 return hp;
721
3f6d08d1
OG		 722rss_init_err:
723 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 724create_transport_err:
725 mlx5_core_hairpin_destroy(hp->pair);
726create_pair_err:
727 kfree(hp);
728 return ERR_PTR(err);
729}
730
731static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
732{
3f6d08d1
OG		 733 if (hp->num_channels > 1)
734 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 735 mlx5e_hairpin_destroy_transport(hp);
736 mlx5_core_hairpin_destroy(hp->pair);
737 kvfree(hp);
738}
739
106be53b
OG		 740static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
741{
742 return (peer_vhca_id << 16 | prio);
743}
744
5c65c564 745static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 746 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 747{
748 struct mlx5e_hairpin_entry *hpe;
106be53b 749 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 750
751 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 752 hairpin_hlist, hash_key) {
e4f9abbd
VB		 753 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
754 refcount_inc(&hpe->refcnt);
5c65c564 755 return hpe;
e4f9abbd 756 }
5c65c564
OG		 757 }
758
759 return NULL;
760}
761
e4f9abbd
VB		 762static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
763 struct mlx5e_hairpin_entry *hpe)
764{
765 /* no more hairpin flows for us, release the hairpin pair */
b32accda 766 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 767 return;
b32accda
VB		 768 hash_del(&hpe->hairpin_hlist);
769 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 770
db76ca24
VB		 771 if (!IS_ERR_OR_NULL(hpe->hp)) {
772 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
773 dev_name(hpe->hp->pair->peer_mdev->device));
774
775 mlx5e_hairpin_destroy(hpe->hp);
776 }
e4f9abbd
VB		 777
778 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 779 kfree(hpe);
780}
781
106be53b
OG		 782#define UNKNOWN_MATCH_PRIO 8
783
784static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 785 struct mlx5_flow_spec *spec, u8 *match_prio,
786 struct netlink_ext_ack *extack)
106be53b
OG		 787{
788 void *headers_c, *headers_v;
789 u8 prio_val, prio_mask = 0;
790 bool vlan_present;
791
792#ifdef CONFIG_MLX5_CORE_EN_DCB
793 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 794 NL_SET_ERR_MSG_MOD(extack,
795 "only PCP trust state supported for hairpin");
106be53b
OG		 796 return -EOPNOTSUPP;
797 }
798#endif
799 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
800 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
801
802 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
803 if (vlan_present) {
804 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
805 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
806 }
807
808 if (!vlan_present || !prio_mask) {
809 prio_val = UNKNOWN_MATCH_PRIO;
810 } else if (prio_mask != 0x7) {
e98bedf5
EB		 811 NL_SET_ERR_MSG_MOD(extack,
812 "masked priority match not supported for hairpin");
106be53b
OG		 813 return -EOPNOTSUPP;
814 }
815
816 *match_prio = prio_val;
817 return 0;
818}
819
5c65c564
OG		 820static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
821 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 822 struct mlx5e_tc_flow_parse_attr *parse_attr,
823 struct netlink_ext_ack *extack)
5c65c564 824{
98b66cb1 825 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 826 struct mlx5_hairpin_params params;
d8822868 827 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 828 struct mlx5e_hairpin_entry *hpe;
829 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 830 u64 link_speed64;
831 u32 link_speed;
106be53b 832 u8 match_prio;
d8822868 833 u16 peer_id;
5c65c564
OG		 834 int err;
835
d8822868
OG		 836 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
837 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 838 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 839 return -EOPNOTSUPP;
840 }
841
d8822868 842 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 843 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
844 extack);
106be53b
OG		 845 if (err)
846 return err;
b32accda
VB		 847
848 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 849 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 850 if (hpe) {
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
852 wait_for_completion(&hpe->res_ready);
853
854 if (IS_ERR(hpe->hp)) {
855 err = -EREMOTEIO;
856 goto out_err;
857 }
5c65c564 858 goto attach_flow;
db76ca24 859 }
5c65c564
OG		 860
861 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 862 if (!hpe) {
db76ca24
VB		 863 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
864 return -ENOMEM;
b32accda 865 }
5c65c564 866
73edca73 867 spin_lock_init(&hpe->flows_lock);
5c65c564 868 INIT_LIST_HEAD(&hpe->flows);
db76ca24 869 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 870 hpe->peer_vhca_id = peer_id;
106be53b 871 hpe->prio = match_prio;
e4f9abbd 872 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 873 init_completion(&hpe->res_ready);
874
875 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
876 hash_hairpin_info(peer_id, match_prio));
877 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564
OG		 878
879 params.log_data_size = 15;
880 params.log_data_size = min_t(u8, params.log_data_size,
881 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
882 params.log_data_size = max_t(u8, params.log_data_size,
883 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 884
eb9180f7
OG		 885 params.log_num_packets = params.log_data_size -
886 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
887 params.log_num_packets = min_t(u8, params.log_num_packets,
888 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
889
890 params.q_counter = priv->q_counter;
3f6d08d1 891 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 892 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 893 link_speed = max_t(u32, link_speed, 50000);
894 link_speed64 = link_speed;
895 do_div(link_speed64, 50000);
896 params.num_channels = link_speed64;
897
5c65c564 898 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 899 hpe->hp = hp;
900 complete_all(&hpe->res_ready);
5c65c564
OG		 901 if (IS_ERR(hp)) {
902 err = PTR_ERR(hp);
db76ca24 903 goto out_err;
5c65c564
OG		 904 }
905
eb9180f7 906 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
27b942fb
PP		 907 hp->tirn, hp->pair->rqn[0],
908 dev_name(hp->pair->peer_mdev->device),
eb9180f7 909 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 910
5c65c564 911attach_flow:
3f6d08d1 912 if (hpe->hp->num_channels > 1) {
226f2ca3 913 flow_flag_set(flow, HAIRPIN_RSS);
c620b772 914 flow->attr->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
3f6d08d1 915 } else {
c620b772 916 flow->attr->nic_attr->hairpin_tirn = hpe->hp->tirn;
3f6d08d1 917 }
b32accda 918
e4f9abbd 919 flow->hpe = hpe;
73edca73 920 spin_lock(&hpe->flows_lock);
5c65c564 921 list_add(&flow->hairpin, &hpe->flows);
73edca73 922 spin_unlock(&hpe->flows_lock);
3f6d08d1 923
5c65c564
OG		 924 return 0;
925
db76ca24
VB		 926out_err:
927 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 928 return err;
929}
930
931static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
932 struct mlx5e_tc_flow *flow)
933{
5a7e5bcb 934 /* flow wasn't fully initialized */
e4f9abbd 935 if (!flow->hpe)
5a7e5bcb
VB		 936 return;
937
73edca73 938 spin_lock(&flow->hpe->flows_lock);
5c65c564 939 list_del(&flow->hairpin);
73edca73
VB		 940 spin_unlock(&flow->hpe->flows_lock);
941
e4f9abbd
VB		 942 mlx5e_hairpin_put(priv, flow->hpe);
943 flow->hpe = NULL;
5c65c564
OG		 944}
945
08247066
AL		 946struct mlx5_flow_handle *
947mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
948 struct mlx5_flow_spec *spec,
c620b772 949 struct mlx5_flow_attr *attr)
e8f887ac 950{
08247066 951 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 952 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 953 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 954 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 955 struct mlx5_flow_destination dest[2] = {};
66958ed9 956 struct mlx5_flow_act flow_act = {
3bc4b7bf 957 .action = attr->action,
bb0ee7dc 958 .flags = FLOW_ACT_NO_APPEND,
66958ed9 959 };
08247066 960 struct mlx5_flow_handle *rule;
c7569097 961 struct mlx5_flow_table *ft;
08247066 962 int dest_ix = 0;
e8f887ac 963
bb0ee7dc 964 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 965 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 966
aedd133d
AL		 967 if (attr->dest_ft) {
968 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
969 dest[dest_ix].ft = attr->dest_ft;
970 dest_ix++;
971 } else if (nic_attr->hairpin_ft) {
08247066 972 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 973 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 974 dest_ix++;
c620b772 975 } else if (nic_attr->hairpin_tirn) {
08247066 976 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 977 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 978 dest_ix++;
3f6d08d1
OG		 979 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
980 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 981 if (attr->dest_chain) {
982 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
983 attr->dest_chain, 1,
984 MLX5E_TC_FT_LEVEL);
985 if (IS_ERR(dest[dest_ix].ft))
986 return ERR_CAST(dest[dest_ix].ft);
987 } else {
988 dest[dest_ix].ft = priv->fs.vlan.ft.t;
989 }
3f6d08d1 990 dest_ix++;
5c65c564 991 }
aad7e08d 992
c7569097
AL		 993 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
994 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
995 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
996
08247066 997 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 998 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 999 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 1000 dest_ix++;
aad7e08d
AV		 1001 }
1002
08247066 1003 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 1004 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 1005
6a064674
AL		 1006 mutex_lock(&tc->t_lock);
1007 if (IS_ERR_OR_NULL(tc->t)) {
1008 /* Create the root table here if doesn't exist yet */
1009 tc->t =
c7569097 1010 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 1011
1012 if (IS_ERR(tc->t)) {
1013 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1014 netdev_err(priv->netdev,
1015 "Failed to create tc offload table\n");
c7569097
AL		 1016 rule = ERR_CAST(priv->fs.tc.t);
1017 goto err_ft_get;
e8f887ac 1018 }
e8f887ac 1019 }
08247066 1020 mutex_unlock(&tc->t_lock);
e8f887ac 1021
aedd133d
AL		 1022 if (attr->chain || attr->prio)
1023 ft = mlx5_chains_get_table(nic_chains,
1024 attr->chain, attr->prio,
1025 MLX5E_TC_FT_LEVEL);
1026 else
1027 ft = attr->ft;
1028
c7569097
AL		 1029 if (IS_ERR(ft)) {
1030 rule = ERR_CAST(ft);
1031 goto err_ft_get;
1032 }
1033
c620b772 1034 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1035 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1036
c7569097 1037 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1038 &flow_act, dest, dest_ix);
1039 if (IS_ERR(rule))
c7569097 1040 goto err_rule;
08247066
AL		 1041
1042 return rule;
c7569097
AL		 1043
1044err_rule:
aedd133d
AL		 1045 if (attr->chain || attr->prio)
1046 mlx5_chains_put_table(nic_chains,
1047 attr->chain, attr->prio,
1048 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1049err_ft_get:
1050 if (attr->dest_chain)
1051 mlx5_chains_put_table(nic_chains,
1052 attr->dest_chain, 1,
1053 MLX5E_TC_FT_LEVEL);
1054
1055 return ERR_CAST(rule);
08247066
AL		 1056}
1057
1058static int
1059mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1060 struct mlx5e_tc_flow_parse_attr *parse_attr,
1061 struct mlx5e_tc_flow *flow,
1062 struct netlink_ext_ack *extack)
1063{
c620b772 1064 struct mlx5_flow_attr *attr = flow->attr;
08247066
AL		 1065 struct mlx5_core_dev *dev = priv->mdev;
1066 struct mlx5_fc *counter = NULL;
1067 int err;
1068
1069 if (flow_flag_test(flow, HAIRPIN)) {
1070 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1071 if (err)
1072 return err;
1073 }
1074
1075 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1076 counter = mlx5_fc_create(dev, true);
1077 if (IS_ERR(counter))
1078 return PTR_ERR(counter);
1079
1080 attr->counter = counter;
1081 }
1082
1083 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1084 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1085 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1086 if (err)
1087 return err;
1088 }
1089
aedd133d
AL		 1090 if (flow_flag_test(flow, CT))
1091 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1092 attr, &parse_attr->mod_hdr_acts);
1093 else
1094 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1095 attr);
aad7e08d 1096
a2b7189b 1097 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1098}
1099
08247066 1100void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1101 struct mlx5_flow_handle *rule,
1102 struct mlx5_flow_attr *attr)
08247066 1103{
c7569097
AL		 1104 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1105
08247066 1106 mlx5_del_flow_rules(rule);
c7569097 1107
aedd133d
AL		 1108 if (attr->chain || attr->prio)
1109 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1110 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1111
1112 if (attr->dest_chain)
1113 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1114 MLX5E_TC_FT_LEVEL);
08247066
AL		 1115}
1116
d85cdccb
OG		 1117static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1118 struct mlx5e_tc_flow *flow)
1119{
c620b772 1120 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1121 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1122
c7569097
AL		 1123 flow_flag_clear(flow, OFFLOADED);
1124
aedd133d
AL		 1125 if (flow_flag_test(flow, CT))
1126 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1127 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1128 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1129
c7569097
AL		 1130 /* Remove root table if no rules are left to avoid
1131 * extra steering hops.
1132 */
b6fac0b4 1133 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1134 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1135 !IS_ERR_OR_NULL(tc->t)) {
1136 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1137 priv->fs.tc.t = NULL;
1138 }
b6fac0b4 1139 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1140
aedd133d
AL		 1141 kvfree(attr->parse_attr);
1142
513f8f7f 1143 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1144 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1145
aedd133d
AL		 1146 mlx5_fc_destroy(priv->mdev, attr->counter);
1147
226f2ca3 1148 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1149 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1150
1151 kfree(flow->attr);
d85cdccb
OG		 1152}
1153
aa0cbbae 1154static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1155 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 1156
3c37745e 1157static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 1158 struct mlx5e_tc_flow *flow,
733d4f36
RD		 1159 struct net_device *mirred_dev,
1160 int out_index,
8c4dc42b 1161 struct netlink_ext_ack *extack,
0ad060ee
RD		 1162 struct net_device **encap_dev,
1163 bool *encap_valid);
14e6b038
EC		 1164static int mlx5e_attach_decap(struct mlx5e_priv *priv,
1165 struct mlx5e_tc_flow *flow,
1166 struct netlink_ext_ack *extack);
1167static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1168 struct mlx5e_tc_flow *flow);
3c37745e 1169
6d2a3ed0
OG		 1170static struct mlx5_flow_handle *
1171mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1172 struct mlx5e_tc_flow *flow,
1173 struct mlx5_flow_spec *spec,
c620b772 1174 struct mlx5_flow_attr *attr)
6d2a3ed0 1175{
1ef3018f 1176 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1177 struct mlx5_flow_handle *rule;
4c3844d9 1178
89e39467
PB		 1179 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1180 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1181
1ef3018f
PB		 1182 if (flow_flag_test(flow, CT)) {
1183 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1184
aedd133d
AL		 1185 return mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
1186 flow, spec, attr,
1ef3018f
PB		 1187 mod_hdr_acts);
1188 }
6d2a3ed0
OG		 1189
1190 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1191 if (IS_ERR(rule))
1192 return rule;
1193
c620b772 1194 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1195 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1196 if (IS_ERR(flow->rule[1])) {
1197 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
1198 return flow->rule[1];
1199 }
1200 }
1201
6d2a3ed0
OG		 1202 return rule;
1203}
1204
1205static void
1206mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1207 struct mlx5e_tc_flow *flow,
c620b772 1208 struct mlx5_flow_attr *attr)
6d2a3ed0 1209{
226f2ca3 1210 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1211
89e39467
PB		 1212 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1213 goto offload_rule_0;
1214
4c3844d9 1215 if (flow_flag_test(flow, CT)) {
aedd133d 1216 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1217 return;
1218 }
1219
c620b772 1220 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1221 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1222
89e39467 1223offload_rule_0:
6d2a3ed0
OG		 1224 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1225}
1226
5dbe906f
PB		 1227static struct mlx5_flow_handle *
1228mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1229 struct mlx5e_tc_flow *flow,
178f69b4 1230 struct mlx5_flow_spec *spec)
5dbe906f 1231{
c620b772 1232 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1233 struct mlx5_flow_handle *rule;
1234
c620b772
AL		 1235 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1236 if (!slow_attr)
1237 return ERR_PTR(-ENOMEM);
5dbe906f 1238
c620b772
AL		 1239 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1240 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1241 slow_attr->esw_attr->split_count = 0;
1242 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1243
1244 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1245 if (!IS_ERR(rule))
226f2ca3 1246 flow_flag_set(flow, SLOW);
5dbe906f 1247
c620b772
AL		 1248 kfree(slow_attr);
1249
5dbe906f
PB		 1250 return rule;
1251}
1252
1253static void
1254mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
178f69b4 1255 struct mlx5e_tc_flow *flow)
5dbe906f 1256{
c620b772 1257 struct mlx5_flow_attr *slow_attr;
178f69b4 1258
c620b772 1259 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1260 if (!slow_attr) {
1261 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1262 return;
1263 }
c620b772
AL		 1264
1265 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1266 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1267 slow_attr->esw_attr->split_count = 0;
1268 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1269 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1270 flow_flag_clear(flow, SLOW);
c620b772 1271 kfree(slow_attr);
5dbe906f
PB		 1272}
1273
ad86755b
VB		 1274/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1275 * function.
1276 */
1277static void unready_flow_add(struct mlx5e_tc_flow *flow,
1278 struct list_head *unready_flows)
1279{
1280 flow_flag_set(flow, NOT_READY);
1281 list_add_tail(&flow->unready, unready_flows);
1282}
1283
1284/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1285 * function.
1286 */
1287static void unready_flow_del(struct mlx5e_tc_flow *flow)
1288{
1289 list_del(&flow->unready);
1290 flow_flag_clear(flow, NOT_READY);
1291}
1292
b4a23329
RD		 1293static void add_unready_flow(struct mlx5e_tc_flow *flow)
1294{
1295 struct mlx5_rep_uplink_priv *uplink_priv;
1296 struct mlx5e_rep_priv *rpriv;
1297 struct mlx5_eswitch *esw;
1298
1299 esw = flow->priv->mdev->priv.eswitch;
1300 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1301 uplink_priv = &rpriv->uplink_priv;
1302
ad86755b
VB		 1303 mutex_lock(&uplink_priv->unready_flows_lock);
1304 unready_flow_add(flow, &uplink_priv->unready_flows);
1305 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1306}
1307
1308static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1309{
ad86755b
VB		 1310 struct mlx5_rep_uplink_priv *uplink_priv;
1311 struct mlx5e_rep_priv *rpriv;
1312 struct mlx5_eswitch *esw;
1313
1314 esw = flow->priv->mdev->priv.eswitch;
1315 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1316 uplink_priv = &rpriv->uplink_priv;
1317
1318 mutex_lock(&uplink_priv->unready_flows_lock);
1319 unready_flow_del(flow);
1320 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1321}
1322
10742efc
VB		 1323static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1324
1325static bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1326{
1327 struct mlx5_core_dev *out_mdev, *route_mdev;
1328 struct mlx5e_priv *out_priv, *route_priv;
1329
1330 out_priv = netdev_priv(out_dev);
1331 out_mdev = out_priv->mdev;
1332 route_priv = netdev_priv(route_dev);
1333 route_mdev = route_priv->mdev;
1334
1335 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1336 route_mdev->coredev_type != MLX5_COREDEV_VF)
1337 return false;
1338
1339 return same_hw_devs(out_priv, route_priv);
1340}
1341
1342static int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev,
1343 u16 *vport)
1344{
1345 struct mlx5e_priv *out_priv, *route_priv;
1346 struct mlx5_core_dev *route_mdev;
1347 struct mlx5_eswitch *esw;
1348 u16 vhca_id;
1349 int err;
1350
1351 out_priv = netdev_priv(out_dev);
1352 esw = out_priv->mdev->priv.eswitch;
1353 route_priv = netdev_priv(route_dev);
1354 route_mdev = route_priv->mdev;
1355
1356 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1357 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1358 return err;
1359}
1360
c83954ab 1361static int
74491de9 1362mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1363 struct mlx5e_tc_flow *flow,
1364 struct netlink_ext_ack *extack)
adb4c123
OG		 1365{
1366 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3c37745e 1367 struct net_device *out_dev, *encap_dev = NULL;
c620b772
AL		 1368 struct mlx5e_tc_flow_parse_attr *parse_attr;
1369 struct mlx5_flow_attr *attr = flow->attr;
1370 struct mlx5_esw_flow_attr *esw_attr;
b8aee822 1371 struct mlx5_fc *counter = NULL;
3c37745e
OG		 1372 struct mlx5e_rep_priv *rpriv;
1373 struct mlx5e_priv *out_priv;
0ad060ee 1374 bool encap_valid = true;
39ac237c 1375 u32 max_prio, max_chain;
0ad060ee 1376 int err = 0;
f493f155 1377 int out_index;
8b32580d 1378
84179981
PB		 1379 /* We check chain range only for tc flows.
1380 * For ft flows, we checked attr->chain was originally 0 and set it to
1381 * FDB_FT_CHAIN which is outside tc range.
1382 * See mlx5e_rep_setup_ft_cb().
1383 */
ae430332 1384 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1385 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1386 NL_SET_ERR_MSG_MOD(extack,
1387 "Requested chain is out of supported range");
5a7e5bcb 1388 return -EOPNOTSUPP;
bf07aa73
PB		 1389 }
1390
ae430332 1391 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1392 if (attr->prio > max_prio) {
61644c3d
RD		 1393 NL_SET_ERR_MSG_MOD(extack,
1394 "Requested priority is out of supported range");
5a7e5bcb 1395 return -EOPNOTSUPP;
bf07aa73 1396 }
e52c2802 1397
14e6b038
EC		 1398 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1399 err = mlx5e_attach_decap(priv, flow, extack);
1400 if (err)
1401 return err;
1402 }
1403
c620b772
AL		 1404 parse_attr = attr->parse_attr;
1405 esw_attr = attr->esw_attr;
1406
f493f155 1407 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 1408 int mirred_ifindex;
1409
c620b772 1410 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1411 continue;
1412
7040632d 1413 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
3c37745e 1414 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b 1415 mirred_ifindex);
733d4f36 1416 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee
RD		 1417 extack, &encap_dev, &encap_valid);
1418 if (err)
5a7e5bcb 1419 return err;
0ad060ee 1420
3c37745e
OG		 1421 out_priv = netdev_priv(encap_dev);
1422 rpriv = out_priv->ppriv;
c620b772
AL		 1423 esw_attr->dests[out_index].rep = rpriv->rep;
1424 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1425 }
1426
8b32580d 1427 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1428 if (err)
5a7e5bcb 1429 return err;
adb4c123 1430
d5a3c2b6
RD		 1431 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1432 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
1a9527bb 1433 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
6ae4a6a5 1434 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
c83954ab 1435 if (err)
5a7e5bcb 1436 return err;
d7e75a32
OG		 1437 }
1438
b8aee822 1439 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1440 counter = mlx5_fc_create(esw_attr->counter_dev, true);
5a7e5bcb
VB		 1441 if (IS_ERR(counter))
1442 return PTR_ERR(counter);
b8aee822
MB		 1443
1444 attr->counter = counter;
1445 }
1446
0ad060ee
RD		 1447 /* we get here if one of the following takes place:
1448 * (1) there's no error
1449 * (2) there's an encap action and we don't have valid neigh
3c37745e 1450 */
bc1d75fa 1451 if (!encap_valid)
178f69b4 1452 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1453 else
6d2a3ed0 1454 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1455
5a7e5bcb
VB		 1456 if (IS_ERR(flow->rule[0]))
1457 return PTR_ERR(flow->rule[0]);
226f2ca3
VB		 1458 else
1459 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1460
1461 return 0;
aa0cbbae 1462}
d85cdccb 1463
9272e3df
YK		 1464static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1465{
c620b772 1466 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1467 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1468 spec->match_value,
1469 misc_parameters_3);
1470 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1471 headers_v,
1472 geneve_tlv_option_0_data);
1473
1474 return !!geneve_tlv_opt_0_data;
1475}
1476
d85cdccb
OG		 1477static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1478 struct mlx5e_tc_flow *flow)
1479{
1480 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1481 struct mlx5_flow_attr *attr = flow->attr;
f493f155 1482 int out_index;
d85cdccb 1483
0a7fcb78
PB		 1484 mlx5e_put_flow_tunnel_id(flow);
1485
12a240a4 1486 if (flow_flag_test(flow, NOT_READY))
b4a23329 1487 remove_unready_flow(flow);
ef06c9ee 1488
226f2ca3
VB		 1489 if (mlx5e_is_offloaded_flow(flow)) {
1490 if (flow_flag_test(flow, SLOW))
178f69b4 1491 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1492 else
1493 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1494 }
d85cdccb 1495
9272e3df
YK		 1496 if (mlx5_flow_has_geneve_opt(flow))
1497 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1498
513f8f7f 1499 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1500
f493f155 1501 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
c620b772 1502 if (attr->esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1503 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1504 kfree(attr->parse_attr->tun_info[out_index]);
1505 }
f493f155 1506 kvfree(attr->parse_attr);
d7e75a32 1507
aedd133d 1508 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1509
513f8f7f 1510 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1511 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1512
1513 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
c620b772 1514 mlx5_fc_destroy(attr->esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1515
1516 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1517 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1518
1519 kfree(flow->attr);
d85cdccb
OG		 1520}
1521
232c0013 1522void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
2a1f1768
VB		 1523 struct mlx5e_encap_entry *e,
1524 struct list_head *flow_list)
232c0013 1525{
3c37745e 1526 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
178f69b4 1527 struct mlx5_esw_flow_attr *esw_attr;
6d2a3ed0 1528 struct mlx5_flow_handle *rule;
c620b772 1529 struct mlx5_flow_attr *attr;
6d2a3ed0 1530 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1531 struct mlx5e_tc_flow *flow;
1532 int err;
1533
2b688ea5
MG		 1534 e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
1535 e->reformat_type,
1536 e->encap_size, e->encap_header,
1537 MLX5_FLOW_NAMESPACE_FDB);
1538 if (IS_ERR(e->pkt_reformat)) {
1539 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n",
1540 PTR_ERR(e->pkt_reformat));
232c0013
HHZ		 1541 return;
1542 }
1543 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1544 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1545
2a1f1768 1546 list_for_each_entry(flow, flow_list, tmp_list) {
8c4dc42b
EB		 1547 bool all_flow_encaps_valid = true;
1548 int i;
1549
95435ad7
VB		 1550 if (!mlx5e_is_offloaded_flow(flow))
1551 continue;
c620b772
AL		 1552 attr = flow->attr;
1553 esw_attr = attr->esw_attr;
1554 spec = &attr->parse_attr->spec;
6d2a3ed0 1555
2b688ea5 1556 esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat;
2a1f1768 1557 esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
8c4dc42b
EB		 1558 /* Flow can be associated with multiple encap entries.
1559 * Before offloading the flow verify that all of them have
1560 * a valid neighbour.
1561 */
1562 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1563 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1564 continue;
1565 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1566 all_flow_encaps_valid = false;
1567 break;
1568 }
1569 }
1570 /* Do not offload flows with unresolved neighbors */
1571 if (!all_flow_encaps_valid)
2a1f1768 1572 continue;
5dbe906f 1573 /* update from slow path rule to encap rule */
c620b772 1574 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, attr);
6d2a3ed0
OG		 1575 if (IS_ERR(rule)) {
1576 err = PTR_ERR(rule);
232c0013
HHZ		 1577 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1578 err);
2a1f1768 1579 continue;
232c0013 1580 }
5dbe906f 1581
178f69b4 1582 mlx5e_tc_unoffload_from_slow_path(esw, flow);
6d2a3ed0 1583 flow->rule[0] = rule;
226f2ca3
VB		 1584 /* was unset when slow path rule removed */
1585 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1586 }
1587}
1588
1589void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
2a1f1768
VB		 1590 struct mlx5e_encap_entry *e,
1591 struct list_head *flow_list)
232c0013 1592{
3c37745e 1593 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1594 struct mlx5_esw_flow_attr *esw_attr;
5dbe906f 1595 struct mlx5_flow_handle *rule;
c620b772 1596 struct mlx5_flow_attr *attr;
5dbe906f 1597 struct mlx5_flow_spec *spec;
232c0013 1598 struct mlx5e_tc_flow *flow;
5dbe906f 1599 int err;
232c0013 1600
2a1f1768 1601 list_for_each_entry(flow, flow_list, tmp_list) {
95435ad7
VB		 1602 if (!mlx5e_is_offloaded_flow(flow))
1603 continue;
c620b772
AL		 1604 attr = flow->attr;
1605 esw_attr = attr->esw_attr;
1606 spec = &attr->parse_attr->spec;
5dbe906f
PB		 1607
1608 /* update from encap rule to slow path rule */
178f69b4 1609 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec);
8c4dc42b 1610 /* mark the flow's encap dest as non-valid */
c620b772 1611 esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1612
1613 if (IS_ERR(rule)) {
1614 err = PTR_ERR(rule);
1615 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1616 err);
2a1f1768 1617 continue;
5dbe906f
PB		 1618 }
1619
c620b772 1620 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
5dbe906f 1621 flow->rule[0] = rule;
226f2ca3
VB		 1622 /* was unset when fast path rule removed */
1623 flow_flag_set(flow, OFFLOADED);
232c0013
HHZ		 1624 }
1625
61c806da
OG		 1626 /* we know that the encap is valid */
1627 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
2b688ea5 1628 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
232c0013
HHZ		 1629}
1630
b8aee822
MB		 1631static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1632{
c620b772 1633 return flow->attr->counter;
b8aee822
MB		 1634}
1635
2a1f1768
VB		 1636/* Takes reference to all flows attached to encap and adds the flows to
1637 * flow_list using 'tmp_list' list_head in mlx5e_tc_flow.
1638 */
1639void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list)
1640{
1641 struct encap_flow_item *efi;
1642 struct mlx5e_tc_flow *flow;
1643
1644 list_for_each_entry(efi, &e->flows, list) {
1645 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
1646 if (IS_ERR(mlx5e_flow_get(flow)))
1647 continue;
95435ad7 1648 wait_for_completion(&flow->init_done);
2a1f1768
VB		 1649
1650 flow->tmp_efi_index = efi->index;
1651 list_add(&flow->tmp_list, flow_list);
1652 }
1653}
1654
6a06c2f7 1655/* Iterate over tmp_list of flows attached to flow_list head. */
2a1f1768 1656void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1657{
1658 struct mlx5e_tc_flow *flow, *tmp;
1659
1660 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1661 mlx5e_flow_put(priv, flow);
1662}
1663
ac0d9176
VB		 1664static struct mlx5e_encap_entry *
1665mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe,
1666 struct mlx5e_encap_entry *e)
1667{
1668 struct mlx5e_encap_entry *next = NULL;
1669
1670retry:
1671 rcu_read_lock();
1672
1673 /* find encap with non-zero reference counter value */
1674 for (next = e ?
1675 list_next_or_null_rcu(&nhe->encap_list,
1676 &e->encap_list,
1677 struct mlx5e_encap_entry,
1678 encap_list) :
1679 list_first_or_null_rcu(&nhe->encap_list,
1680 struct mlx5e_encap_entry,
1681 encap_list);
1682 next;
1683 next = list_next_or_null_rcu(&nhe->encap_list,
1684 &next->encap_list,
1685 struct mlx5e_encap_entry,
1686 encap_list))
1687 if (mlx5e_encap_take(next))
1688 break;
1689
1690 rcu_read_unlock();
1691
1692 /* release starting encap */
1693 if (e)
1694 mlx5e_encap_put(netdev_priv(e->out_dev), e);
1695 if (!next)
1696 return next;
1697
1698 /* wait for encap to be fully initialized */
1699 wait_for_completion(&next->res_ready);
1700 /* continue searching if encap entry is not in valid state after completion */
1701 if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) {
1702 e = next;
1703 goto retry;
1704 }
1705
1706 return next;
1707}
1708
f6dfb4c3
HHZ		 1709void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1710{
1711 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
ac0d9176 1712 struct mlx5e_encap_entry *e = NULL;
f6dfb4c3 1713 struct mlx5e_tc_flow *flow;
f6dfb4c3
HHZ		 1714 struct mlx5_fc *counter;
1715 struct neigh_table *tbl;
1716 bool neigh_used = false;
1717 struct neighbour *n;
90bb7692 1718 u64 lastuse;
f6dfb4c3
HHZ		 1719
1720 if (m_neigh->family == AF_INET)
1721 tbl = &arp_tbl;
1722#if IS_ENABLED(CONFIG_IPV6)
1723 else if (m_neigh->family == AF_INET6)
5cc3a8c6 1724 tbl = ipv6_stub->nd_tbl;
f6dfb4c3
HHZ		 1725#endif
1726 else
1727 return;
1728
ac0d9176
VB		 1729 /* mlx5e_get_next_valid_encap() releases previous encap before returning
1730 * next one.
1731 */
1732 while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) {
6a06c2f7 1733 struct mlx5e_priv *priv = netdev_priv(e->out_dev);
5a7e5bcb 1734 struct encap_flow_item *efi, *tmp;
6a06c2f7
VB		 1735 struct mlx5_eswitch *esw;
1736 LIST_HEAD(flow_list);
948993f2 1737
6a06c2f7
VB		 1738 esw = priv->mdev->priv.eswitch;
1739 mutex_lock(&esw->offloads.encap_tbl_lock);
5a7e5bcb 1740 list_for_each_entry_safe(efi, tmp, &e->flows, list) {
79baaec7
EB		 1741 flow = container_of(efi, struct mlx5e_tc_flow,
1742 encaps[efi->index]);
5a7e5bcb
VB		 1743 if (IS_ERR(mlx5e_flow_get(flow)))
1744 continue;
6a06c2f7 1745 list_add(&flow->tmp_list, &flow_list);
5a7e5bcb 1746
226f2ca3 1747 if (mlx5e_is_offloaded_flow(flow)) {
b8aee822 1748 counter = mlx5e_tc_get_counter(flow);
90bb7692 1749 lastuse = mlx5_fc_query_lastuse(counter);
f6dfb4c3
HHZ		 1750 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1751 neigh_used = true;
1752 break;
1753 }
1754 }
1755 }
6a06c2f7 1756 mutex_unlock(&esw->offloads.encap_tbl_lock);
948993f2 1757
6a06c2f7 1758 mlx5e_put_encap_flow_list(priv, &flow_list);
ac0d9176
VB		 1759 if (neigh_used) {
1760 /* release current encap before breaking the loop */
6a06c2f7 1761 mlx5e_encap_put(priv, e);
e36d4810 1762 break;
ac0d9176 1763 }
f6dfb4c3
HHZ		 1764 }
1765
c786fe59
VB		 1766 trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used);
1767
f6dfb4c3
HHZ		 1768 if (neigh_used) {
1769 nhe->reported_lastuse = jiffies;
1770
1771 /* find the relevant neigh according to the cached device and
1772 * dst ip pair
1773 */
1774 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1775 if (!n)
f6dfb4c3 1776 return;
f6dfb4c3
HHZ		 1777
1778 neigh_event_send(n, NULL);
1779 neigh_release(n);
1780 }
1781}
1782
61086f39 1783static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
948993f2 1784{
948993f2 1785 WARN_ON(!list_empty(&e->flows));
948993f2 1786
3c140dd5
VB		 1787 if (e->compl_result > 0) {
1788 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1789
1790 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2b688ea5 1791 mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat);
3c140dd5 1792 }
948993f2 1793
2a4b6526 1794 kfree(e->tun_info);
948993f2 1795 kfree(e->encap_header);
ac0d9176 1796 kfree_rcu(e, rcu);
948993f2
VB		 1797}
1798
14e6b038
EC		 1799static void mlx5e_decap_dealloc(struct mlx5e_priv *priv,
1800 struct mlx5e_decap_entry *d)
1801{
1802 WARN_ON(!list_empty(&d->flows));
1803
1804 if (!d->compl_result)
1805 mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat);
1806
1807 kfree_rcu(d, rcu);
1808}
1809
61086f39
VB		 1810void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e)
1811{
1812 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1813
1814 if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock))
1815 return;
1816 hash_del_rcu(&e->encap_hlist);
1817 mutex_unlock(&esw->offloads.encap_tbl_lock);
1818
1819 mlx5e_encap_dealloc(priv, e);
1820}
1821
14e6b038
EC		 1822static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d)
1823{
1824 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1825
1826 if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock))
1827 return;
1828 hash_del_rcu(&d->hlist);
1829 mutex_unlock(&esw->offloads.decap_tbl_lock);
1830
1831 mlx5e_decap_dealloc(priv, d);
1832}
1833
d85cdccb 1834static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1835 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1836{
61086f39
VB		 1837 struct mlx5e_encap_entry *e = flow->encaps[out_index].e;
1838 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1839
5a7e5bcb 1840 /* flow wasn't fully initialized */
61086f39 1841 if (!e)
5a7e5bcb
VB		 1842 return;
1843
61086f39 1844 mutex_lock(&esw->offloads.encap_tbl_lock);
8c4dc42b 1845 list_del(&flow->encaps[out_index].list);
948993f2 1846 flow->encaps[out_index].e = NULL;
61086f39
VB		 1847 if (!refcount_dec_and_test(&e->refcnt)) {
1848 mutex_unlock(&esw->offloads.encap_tbl_lock);
1849 return;
1850 }
1851 hash_del_rcu(&e->encap_hlist);
1852 mutex_unlock(&esw->offloads.encap_tbl_lock);
1853
1854 mlx5e_encap_dealloc(priv, e);
5067b602
RD		 1855}
1856
14e6b038
EC		 1857static void mlx5e_detach_decap(struct mlx5e_priv *priv,
1858 struct mlx5e_tc_flow *flow)
1859{
1860 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1861 struct mlx5e_decap_entry *d = flow->decap_reformat;
1862
1863 if (!d)
1864 return;
1865
1866 mutex_lock(&esw->offloads.decap_tbl_lock);
1867 list_del(&flow->l3_to_l2_reformat);
1868 flow->decap_reformat = NULL;
1869
1870 if (!refcount_dec_and_test(&d->refcnt)) {
1871 mutex_unlock(&esw->offloads.decap_tbl_lock);
1872 return;
1873 }
1874 hash_del_rcu(&d->hlist);
1875 mutex_unlock(&esw->offloads.decap_tbl_lock);
1876
1877 mlx5e_decap_dealloc(priv, d);
1878}
1879
04de7dda
RD		 1880static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1881{
1882 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1883
226f2ca3
VB		 1884 if (!flow_flag_test(flow, ESWITCH) ||
1885 !flow_flag_test(flow, DUP))
04de7dda
RD		 1886 return;
1887
1888 mutex_lock(&esw->offloads.peer_mutex);
1889 list_del(&flow->peer);
1890 mutex_unlock(&esw->offloads.peer_mutex);
1891
226f2ca3 1892 flow_flag_clear(flow, DUP);
04de7dda 1893
eb252c3a
RD		 1894 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1895 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1896 kfree(flow->peer_flow);
1897 }
1898
04de7dda
RD		 1899 flow->peer_flow = NULL;
1900}
1901
1902static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1903{
1904 struct mlx5_core_dev *dev = flow->priv->mdev;
1905 struct mlx5_devcom *devcom = dev->priv.devcom;
1906 struct mlx5_eswitch *peer_esw;
1907
1908 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1909 if (!peer_esw)
1910 return;
1911
1912 __mlx5e_tc_del_fdb_peer_flow(flow);
1913 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1914}
1915
e8f887ac 1916static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1917 struct mlx5e_tc_flow *flow)
e8f887ac 1918{
226f2ca3 1919 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1920 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1921 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1922 } else {
d85cdccb 1923 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1924 }
e8f887ac
AV		 1925}
1926
0a7fcb78
PB		 1927static int flow_has_tc_fwd_action(struct flow_cls_offload *f)
1928{
1929 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1930 struct flow_action *flow_action = &rule->action;
1931 const struct flow_action_entry *act;
1932 int i;
1933
1934 flow_action_for_each(i, act, flow_action) {
1935 switch (act->id) {
1936 case FLOW_ACTION_GOTO:
1937 return true;
1938 default:
1939 continue;
1940 }
1941 }
1942
1943 return false;
1944}
bbd00f7e 1945
0a7fcb78
PB		 1946static int
1947enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1948 struct flow_dissector_key_enc_opts *opts,
1949 struct netlink_ext_ack *extack,
1950 bool *dont_care)
1951{
1952 struct geneve_opt *opt;
1953 int off = 0;
1954
1955 *dont_care = true;
1956
1957 while (opts->len > off) {
1958 opt = (struct geneve_opt *)&opts->data[off];
1959
1960 if (!(*dont_care) || opt->opt_class || opt->type ||
1961 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1962 *dont_care = false;
1963
c51323ee 1964 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1965 opt->type != U8_MAX) {
0a7fcb78
PB		 1966 NL_SET_ERR_MSG(extack,
1967 "Partial match of tunnel options in chain > 0 isn't supported");
1968 netdev_warn(priv->netdev,
1969 "Partial match of tunnel options in chain > 0 isn't supported");
1970 return -EOPNOTSUPP;
1971 }
1972 }
1973
1974 off += sizeof(struct geneve_opt) + opt->length * 4;
1975 }
1976
1977 return 0;
1978}
1979
1980#define COPY_DISSECTOR(rule, diss_key, dst)\
1981({ \
1982 struct flow_rule *__rule = (rule);\
1983 typeof(dst) __dst = dst;\
1984\
1985 memcpy(__dst,\
1986 skb_flow_dissector_target(__rule->match.dissector,\
1987 diss_key,\
1988 __rule->match.key),\
1989 sizeof(*__dst));\
1990})
1991
1992static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1993 struct mlx5e_tc_flow *flow,
1994 struct flow_cls_offload *f,
1995 struct net_device *filter_dev)
bbd00f7e 1996{
f9e30088 1997 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1998 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1999 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2000 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 2001 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 2002 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 2003 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 2004 struct mlx5e_rep_priv *uplink_rpriv;
2005 struct tunnel_match_key tunnel_key;
2006 bool enc_opts_is_dont_care = true;
2007 u32 tun_id, enc_opts_id = 0;
2008 struct mlx5_eswitch *esw;
2009 u32 value, mask;
8f256622 2010 int err;
2e72eb43 2011
0a7fcb78
PB		 2012 esw = priv->mdev->priv.eswitch;
2013 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2014 uplink_priv = &uplink_rpriv->uplink_priv;
2015
2016 memset(&tunnel_key, 0, sizeof(tunnel_key));
2017 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2018 &tunnel_key.enc_control);
2019 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2020 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2021 &tunnel_key.enc_ipv4);
2022 else
2023 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2024 &tunnel_key.enc_ipv6);
2025 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2026 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2027 &tunnel_key.enc_tp);
2028 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2029 &tunnel_key.enc_key_id);
2030 tunnel_key.filter_ifindex = filter_dev->ifindex;
2031
2032 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2033 if (err)
101f4de9 2034 return err;
bbd00f7e 2035
0a7fcb78
PB		 2036 flow_rule_match_enc_opts(rule, &enc_opts_match);
2037 err = enc_opts_is_dont_care_or_full_match(priv,
2038 enc_opts_match.mask,
2039 extack,
2040 &enc_opts_is_dont_care);
2041 if (err)
2042 goto err_enc_opts;
fe1587a7 2043
0a7fcb78 2044 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 2045 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2046 memcpy(&tun_enc_opts.key, enc_opts_match.key,
2047 sizeof(*enc_opts_match.key));
2048 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2049 sizeof(*enc_opts_match.mask));
2050
0a7fcb78 2051 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 2052 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 2053 if (err)
2054 goto err_enc_opts;
2055 }
fe1587a7 2056
0a7fcb78
PB		 2057 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2058 mask = enc_opts_id ? TUNNEL_ID_MASK :
2059 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 2060
0a7fcb78
PB		 2061 if (attr->chain) {
2062 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2063 TUNNEL_TO_REG, value, mask);
2064 } else {
2065 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2066 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 2067 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 2068 TUNNEL_TO_REG, value);
2069 if (err)
2070 goto err_set;
fe1587a7 2071
0a7fcb78 2072 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 2073 }
bbd00f7e 2074
0a7fcb78
PB		 2075 flow->tunnel_id = value;
2076 return 0;
bcef735c 2077
0a7fcb78
PB		 2078err_set:
2079 if (enc_opts_id)
2080 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2081 enc_opts_id);
2082err_enc_opts:
2083 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2084 return err;
2085}
bcef735c 2086
0a7fcb78
PB		 2087static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2088{
2089 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
2090 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
2091 struct mlx5_rep_uplink_priv *uplink_priv;
2092 struct mlx5e_rep_priv *uplink_rpriv;
2093 struct mlx5_eswitch *esw;
bcef735c 2094
0a7fcb78
PB		 2095 esw = flow->priv->mdev->priv.eswitch;
2096 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2097 uplink_priv = &uplink_rpriv->uplink_priv;
2098
2099 if (tun_id)
2100 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2101 if (enc_opts_id)
2102 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2103 enc_opts_id);
2104}
e98bedf5 2105
4c3844d9
PB		 2106u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
2107{
2108 return flow->tunnel_id;
2109}
2110
fca53304
EB		 2111void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2112 struct flow_match_basic *match, bool outer,
2113 void *headers_c, void *headers_v)
2114{
2115 bool ip_version_cap;
2116
2117 ip_version_cap = outer ?
2118 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2119 ft_field_support.outer_ip_version) :
2120 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2121 ft_field_support.inner_ip_version);
2122
2123 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2124 (match->key->n_proto == htons(ETH_P_IP) ||
2125 match->key->n_proto == htons(ETH_P_IPV6))) {
2126 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2127 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2128 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2129 } else {
2130 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2131 ntohs(match->mask->n_proto));
2132 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2133 ntohs(match->key->n_proto));
2134 }
4a5d5d73
EB		 2135}
2136
bbd00f7e 2137static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2138 struct mlx5e_tc_flow *flow,
bbd00f7e 2139 struct mlx5_flow_spec *spec,
f9e30088 2140 struct flow_cls_offload *f,
0a7fcb78
PB		 2141 struct net_device *filter_dev,
2142 u8 *match_level,
2143 bool *match_inner)
bbd00f7e 2144{
0a7fcb78 2145 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2146 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2147 bool needs_mapping, sets_mapping;
8f256622 2148 int err;
2e72eb43 2149
0a7fcb78
PB		 2150 if (!mlx5e_is_eswitch_flow(flow))
2151 return -EOPNOTSUPP;
2152
c620b772
AL		 2153 needs_mapping = !!flow->attr->chain;
2154 sets_mapping = !flow->attr->chain && flow_has_tc_fwd_action(f);
0a7fcb78
PB		 2155 *match_inner = !needs_mapping;
2156
2157 if ((needs_mapping || sets_mapping) &&
636bb968 2158 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
0a7fcb78 2159 NL_SET_ERR_MSG(extack,
636bb968 2160 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2161 netdev_warn(priv->netdev,
636bb968 2162 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2163 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2164 }
2165
c620b772 2166 if (!flow->attr->chain) {
0a7fcb78
PB		 2167 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2168 match_level);
2169 if (err) {
e98bedf5 2170 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2171 "Failed to parse tunnel attributes");
2172 netdev_warn(priv->netdev,
2173 "Failed to parse tunnel attributes");
2174 return err;
e98bedf5
EB		 2175 }
2176
14e6b038
EC		 2177 /* With mpls over udp we decapsulate using packet reformat
2178 * object
2179 */
2180 if (!netif_is_bareudp(filter_dev))
c620b772 2181 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bcef735c
OG		 2182 }
2183
0a7fcb78
PB		 2184 if (!needs_mapping && !sets_mapping)
2185 return 0;
bbd00f7e 2186
0a7fcb78 2187 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2188}
bbd00f7e 2189
0a7fcb78 2190static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2191{
0a7fcb78
PB		 2192 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2193 inner_headers);
bbd00f7e
HHZ		 2194}
2195
0a7fcb78 2196static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2197{
0a7fcb78
PB		 2198 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2199 inner_headers);
2200}
2201
2202static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2203{
2204 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2205 outer_headers);
2206}
2207
2208static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2209{
2210 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2211 outer_headers);
8377629e
EB		 2212}
2213
2214static void *get_match_headers_value(u32 flags,
2215 struct mlx5_flow_spec *spec)
2216{
2217 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2218 get_match_inner_headers_value(spec) :
2219 get_match_outer_headers_value(spec);
2220}
2221
2222static void *get_match_headers_criteria(u32 flags,
2223 struct mlx5_flow_spec *spec)
2224{
2225 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2226 get_match_inner_headers_criteria(spec) :
2227 get_match_outer_headers_criteria(spec);
8377629e
EB		 2228}
2229
6d65bc64 2230static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2231 struct flow_cls_offload *f)
2232{
2233 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2234 struct netlink_ext_ack *extack = f->common.extack;
2235 struct net_device *ingress_dev;
2236 struct flow_match_meta match;
2237
2238 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2239 return 0;
2240
2241 flow_rule_match_meta(rule, &match);
2242 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2243 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2244 return -EOPNOTSUPP;
6d65bc64 2245 }
2246
2247 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2248 match.key->ingress_ifindex);
2249 if (!ingress_dev) {
2250 NL_SET_ERR_MSG_MOD(extack,
2251 "Can't find the ingress port to match on");
a683012a 2252 return -ENOENT;
6d65bc64 2253 }
2254
2255 if (ingress_dev != filter_dev) {
2256 NL_SET_ERR_MSG_MOD(extack,
2257 "Can't match on the ingress filter port");
a683012a 2258 return -EOPNOTSUPP;
6d65bc64 2259 }
2260
2261 return 0;
2262}
2263
72046a91
EC		 2264static bool skip_key_basic(struct net_device *filter_dev,
2265 struct flow_cls_offload *f)
2266{
2267 /* When doing mpls over udp decap, the user needs to provide
2268 * MPLS_UC as the protocol in order to be able to match on mpls
2269 * label fields. However, the actual ethertype is IP so we want to
2270 * avoid matching on this, otherwise we'll fail the match.
2271 */
2272 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2273 return true;
2274
2275 return false;
2276}
2277
de0af0bf 2278static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2279 struct mlx5e_tc_flow *flow,
de0af0bf 2280 struct mlx5_flow_spec *spec,
f9e30088 2281 struct flow_cls_offload *f,
54c177ca 2282 struct net_device *filter_dev,
93b3586e 2283 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2284{
e98bedf5 2285 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2286 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2287 outer_headers);
2288 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2289 outer_headers);
699e96dd
JL		 2290 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2291 misc_parameters);
2292 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2293 misc_parameters);
f9e30088 2294 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2295 struct flow_dissector *dissector = rule->match.dissector;
e3a2b7ed
AV		 2296 u16 addr_type = 0;
2297 u8 ip_proto = 0;
93b3586e 2298 u8 *match_level;
6d65bc64 2299 int err;
e3a2b7ed 2300
93b3586e 2301 match_level = outer_match_level;
de0af0bf 2302
8f256622 2303 if (dissector->used_keys &
3d144578
VB		 2304 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2305 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2306 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2307 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2308 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2309 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2310 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2311 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2312 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2313 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2314 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2315 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2316 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2317 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2318 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2319 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2320 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2321 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91
EC		 2322 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2323 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2324 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2325 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2326 dissector->used_keys);
e3a2b7ed
AV		 2327 return -EOPNOTSUPP;
2328 }
2329
075973c7 2330 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2331 bool match_inner = false;
bbd00f7e 2332
0a7fcb78
PB		 2333 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2334 outer_match_level, &match_inner);
2335 if (err)
2336 return err;
2337
2338 if (match_inner) {
2339 /* header pointers should point to the inner headers
2340 * if the packet was decapsulated already.
2341 * outer headers are set by parse_tunnel_attr.
2342 */
2343 match_level = inner_match_level;
2344 headers_c = get_match_inner_headers_criteria(spec);
2345 headers_v = get_match_inner_headers_value(spec);
2346 }
bbd00f7e
HHZ		 2347 }
2348
6d65bc64 2349 err = mlx5e_flower_parse_meta(filter_dev, f);
2350 if (err)
2351 return err;
2352
72046a91
EC		 2353 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2354 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2355 struct flow_match_basic match;
2356
2357 flow_rule_match_basic(rule, &match);
fca53304
EB		 2358 mlx5e_tc_set_ethertype(priv->mdev, &match,
2359 match_level == outer_match_level,
2360 headers_c, headers_v);
e3a2b7ed 2361
8f256622 2362 if (match.mask->n_proto)
d708f902 2363 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2364 }
35a605db
EB		 2365 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2366 is_vlan_dev(filter_dev)) {
2367 struct flow_dissector_key_vlan filter_dev_mask;
2368 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2369 struct flow_match_vlan match;
2370
35a605db
EB		 2371 if (is_vlan_dev(filter_dev)) {
2372 match.key = &filter_dev_key;
2373 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2374 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2375 match.key->vlan_priority = 0;
2376 match.mask = &filter_dev_mask;
2377 memset(match.mask, 0xff, sizeof(*match.mask));
2378 match.mask->vlan_priority = 0;
2379 } else {
2380 flow_rule_match_vlan(rule, &match);
2381 }
8f256622
PNA		 2382 if (match.mask->vlan_id ||
2383 match.mask->vlan_priority ||
2384 match.mask->vlan_tpid) {
2385 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2386 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2387 svlan_tag, 1);
2388 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2389 svlan_tag, 1);
2390 } else {
2391 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2392 cvlan_tag, 1);
2393 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2394 cvlan_tag, 1);
2395 }
095b6cfd 2396
8f256622
PNA		 2397 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2398 match.mask->vlan_id);
2399 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2400 match.key->vlan_id);
358d79a4 2401
8f256622
PNA		 2402 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2403 match.mask->vlan_priority);
2404 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2405 match.key->vlan_priority);
54782900 2406
d708f902 2407 *match_level = MLX5_MATCH_L2;
54782900 2408 }
d3a80bb5 2409 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2410 /* cvlan_tag enabled in match criteria and
2411 * disabled in match value means both S & C tags
2412 * don't exist (untagged of both)
2413 */
cee26487 2414 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2415 *match_level = MLX5_MATCH_L2;
54782900
OG		 2416 }
2417
8f256622
PNA		 2418 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2419 struct flow_match_vlan match;
2420
12d5cbf8 2421 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2422 if (match.mask->vlan_id ||
2423 match.mask->vlan_priority ||
2424 match.mask->vlan_tpid) {
2425 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2426 MLX5_SET(fte_match_set_misc, misc_c,
2427 outer_second_svlan_tag, 1);
2428 MLX5_SET(fte_match_set_misc, misc_v,
2429 outer_second_svlan_tag, 1);
2430 } else {
2431 MLX5_SET(fte_match_set_misc, misc_c,
2432 outer_second_cvlan_tag, 1);
2433 MLX5_SET(fte_match_set_misc, misc_v,
2434 outer_second_cvlan_tag, 1);
2435 }
2436
2437 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2438 match.mask->vlan_id);
699e96dd 2439 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2440 match.key->vlan_id);
699e96dd 2441 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2442 match.mask->vlan_priority);
699e96dd 2443 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2444 match.key->vlan_priority);
699e96dd
JL		 2445
2446 *match_level = MLX5_MATCH_L2;
0faddfe6 2447 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2448 }
2449 }
2450
8f256622
PNA		 2451 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2452 struct flow_match_eth_addrs match;
54782900 2453
8f256622 2454 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2455 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2456 dmac_47_16),
8f256622 2457 match.mask->dst);
d3a80bb5
OG		 2458 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2459 dmac_47_16),
8f256622 2460 match.key->dst);
d3a80bb5
OG		 2461
2462 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2463 smac_47_16),
8f256622 2464 match.mask->src);
d3a80bb5
OG		 2465 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2466 smac_47_16),
8f256622 2467 match.key->src);
d3a80bb5 2468
8f256622
PNA		 2469 if (!is_zero_ether_addr(match.mask->src) ||
2470 !is_zero_ether_addr(match.mask->dst))
d708f902 2471 *match_level = MLX5_MATCH_L2;
54782900
OG		 2472 }
2473
8f256622
PNA		 2474 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2475 struct flow_match_control match;
54782900 2476
8f256622
PNA		 2477 flow_rule_match_control(rule, &match);
2478 addr_type = match.key->addr_type;
54782900
OG		 2479
2480 /* the HW doesn't support frag first/later */
8f256622 2481 if (match.mask->flags & FLOW_DIS_FIRST_FRAG)
54782900
OG		 2482 return -EOPNOTSUPP;
2483
8f256622 2484 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2485 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2486 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2487 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2488
2489 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2490 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2491 *match_level = MLX5_MATCH_L2;
54782900
OG		 2492 /* *** L2 attributes parsing up to here *** */
2493 else
83621b7d 2494 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2495 }
2496 }
2497
8f256622
PNA		 2498 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2499 struct flow_match_basic match;
2500
2501 flow_rule_match_basic(rule, &match);
2502 ip_proto = match.key->ip_proto;
54782900
OG		 2503
2504 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2505 match.mask->ip_proto);
54782900 2506 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2507 match.key->ip_proto);
54782900 2508
8f256622 2509 if (match.mask->ip_proto)
d708f902 2510 *match_level = MLX5_MATCH_L3;
54782900
OG		 2511 }
2512
e3a2b7ed 2513 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2514 struct flow_match_ipv4_addrs match;
e3a2b7ed 2515
8f256622 2516 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2517 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2518 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2519 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2520 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2521 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2522 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2523 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2524 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2525 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2526 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2527 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2528 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2529
8f256622 2530 if (match.mask->src || match.mask->dst)
d708f902 2531 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2532 }
2533
2534 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2535 struct flow_match_ipv6_addrs match;
e3a2b7ed 2536
8f256622 2537 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2538 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2539 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2540 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2541 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2542 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2543 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2544
2545 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2546 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2547 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2548 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2549 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2550 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2551
8f256622
PNA		 2552 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2553 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2554 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2555 }
2556
8f256622
PNA		 2557 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2558 struct flow_match_ip match;
1f97a526 2559
8f256622
PNA		 2560 flow_rule_match_ip(rule, &match);
2561 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2562 match.mask->tos & 0x3);
2563 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2564 match.key->tos & 0x3);
1f97a526 2565
8f256622
PNA		 2566 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2567 match.mask->tos >> 2);
2568 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2569 match.key->tos >> 2);
1f97a526 2570
8f256622
PNA		 2571 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2572 match.mask->ttl);
2573 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2574 match.key->ttl);
1f97a526 2575
8f256622 2576 if (match.mask->ttl &&
a8ade55f 2577 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2578 ft_field_support.outer_ipv4_ttl)) {
2579 NL_SET_ERR_MSG_MOD(extack,
2580 "Matching on TTL is not supported");
1f97a526 2581 return -EOPNOTSUPP;
e98bedf5 2582 }
a8ade55f 2583
8f256622 2584 if (match.mask->tos || match.mask->ttl)
d708f902 2585 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2586 }
2587
54782900
OG		 2588 /* *** L3 attributes parsing up to here *** */
2589
8f256622
PNA		 2590 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2591 struct flow_match_ports match;
2592
2593 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2594 switch (ip_proto) {
2595 case IPPROTO_TCP:
2596 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2597 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2598 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2599 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2600
2601 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2602 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2603 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2604 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2605 break;
2606
2607 case IPPROTO_UDP:
2608 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2609 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2610 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2611 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2612
2613 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2614 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2615 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2616 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2617 break;
2618 default:
e98bedf5
EB		 2619 NL_SET_ERR_MSG_MOD(extack,
2620 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2621 netdev_err(priv->netdev,
2622 "Only UDP and TCP transport are supported\n");
2623 return -EINVAL;
2624 }
de0af0bf 2625
8f256622 2626 if (match.mask->src || match.mask->dst)
d708f902 2627 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2628 }
2629
8f256622
PNA		 2630 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2631 struct flow_match_tcp match;
e77834ec 2632
8f256622 2633 flow_rule_match_tcp(rule, &match);
e77834ec 2634 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2635 ntohs(match.mask->flags));
e77834ec 2636 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2637 ntohs(match.key->flags));
e77834ec 2638
8f256622 2639 if (match.mask->flags)
d708f902 2640 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 2641 }
2642
e3a2b7ed
AV		 2643 return 0;
2644}
2645
de0af0bf 2646static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2647 struct mlx5e_tc_flow *flow,
de0af0bf 2648 struct mlx5_flow_spec *spec,
f9e30088 2649 struct flow_cls_offload *f,
54c177ca 2650 struct net_device *filter_dev)
de0af0bf 2651{
93b3586e 2652 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2653 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2654 struct mlx5_core_dev *dev = priv->mdev;
2655 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2656 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2657 struct mlx5_eswitch_rep *rep;
226f2ca3 2658 bool is_eswitch_flow;
de0af0bf
RD		 2659 int err;
2660
93b3586e
HN		 2661 inner_match_level = MLX5_MATCH_NONE;
2662 outer_match_level = MLX5_MATCH_NONE;
2663
0a7fcb78
PB		 2664 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2665 &inner_match_level, &outer_match_level);
93b3586e
HN		 2666 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2667 outer_match_level : inner_match_level;
de0af0bf 2668
226f2ca3
VB		 2669 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2670 if (!err && is_eswitch_flow) {
1d447a39 2671 rep = rpriv->rep;
b05af6aa 2672 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2673 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2674 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2675 NL_SET_ERR_MSG_MOD(extack,
2676 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2677 netdev_warn(priv->netdev,
2678 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2679 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2680 return -EOPNOTSUPP;
2681 }
2682 }
2683
c620b772
AL		 2684 flow->attr->inner_match_level = inner_match_level;
2685 flow->attr->outer_match_level = outer_match_level;
2686
38aa51c1 2687
de0af0bf
RD		 2688 return err;
2689}
2690
d79b6df6
OG		 2691struct pedit_headers {
2692 struct ethhdr eth;
0eb69bb9 2693 struct vlan_hdr vlan;
d79b6df6
OG		 2694 struct iphdr ip4;
2695 struct ipv6hdr ip6;
2696 struct tcphdr tcp;
2697 struct udphdr udp;
2698};
2699
c500c86b
PNA		 2700struct pedit_headers_action {
2701 struct pedit_headers vals;
2702 struct pedit_headers masks;
2703 u32 pedits;
2704};
2705
d79b6df6 2706static int pedit_header_offsets[] = {
73867881
PNA		 2707 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2708 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2709 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2710 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2711 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2712};
2713
2714#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2715
2716static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
c500c86b 2717 struct pedit_headers_action *hdrs)
d79b6df6
OG		 2718{
2719 u32 *curr_pmask, *curr_pval;
2720
c500c86b
PNA		 2721 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2722 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6
OG		 2723
2724 if (*curr_pmask & mask) /* disallow acting twice on the same location */
2725 goto out_err;
2726
2727 *curr_pmask |= mask;
2728 *curr_pval |= (val & mask);
2729
2730 return 0;
2731
2732out_err:
2733 return -EOPNOTSUPP;
2734}
2735
2736struct mlx5_fields {
2737 u8 field;
88f30bbc
DL		 2738 u8 field_bsize;
2739 u32 field_mask;
d79b6df6 2740 u32 offset;
27c11b6b 2741 u32 match_offset;
d79b6df6
OG		 2742};
2743
88f30bbc
DL		 2744#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2745 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2746 offsetof(struct pedit_headers, field) + (off), \
2747 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2748
2ef86872
EB		 2749/* masked values are the same and there are no rewrites that do not have a
2750 * match.
2751 */
2752#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2753 type matchmaskx = *(type *)(matchmaskp); \
2754 type matchvalx = *(type *)(matchvalp); \
2755 type maskx = *(type *)(maskp); \
2756 type valx = *(type *)(valp); \
2757 \
2758 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2759 matchmaskx)); \
2760})
2761
27c11b6b 2762static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2763 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2764{
2765 bool same = false;
2766
88f30bbc
DL		 2767 switch (bsize) {
2768 case 8:
2ef86872 2769 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2770 break;
88f30bbc 2771 case 16:
2ef86872 2772 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2773 break;
88f30bbc 2774 case 32:
2ef86872 2775 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2776 break;
2777 }
2778
2779 return same;
2780}
a8e4f0c4 2781
d79b6df6 2782static struct mlx5_fields fields[] = {
88f30bbc
DL		 2783 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2784 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2785 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2786 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2787 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2788 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2789
ab9341b5 2790 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2791 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2792 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2793 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2794
2795 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2796 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2797 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2798 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2799 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2800 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2801 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2802 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2803 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2804 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2805 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2806 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2807 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2808 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2809 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2810 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2811 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2812 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2813
88f30bbc
DL		 2814 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2815 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2816 /* in linux iphdr tcp_flags is 8 bits long */
2817 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2818
88f30bbc
DL		 2819 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2820 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2821};
2822
82198d8b
MD		 2823static unsigned long mask_to_le(unsigned long mask, int size)
2824{
2825 __be32 mask_be32;
2826 __be16 mask_be16;
2827
2828 if (size == 32) {
2829 mask_be32 = (__force __be32)(mask);
2830 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2831 } else if (size == 16) {
2832 mask_be32 = (__force __be32)(mask);
2833 mask_be16 = *(__be16 *)&mask_be32;
2834 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2835 }
2836
2837 return mask;
2838}
6ae4a6a5
PB		 2839static int offload_pedit_fields(struct mlx5e_priv *priv,
2840 int namespace,
2841 struct pedit_headers_action *hdrs,
e98bedf5 2842 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2843 u32 *action_flags,
e98bedf5 2844 struct netlink_ext_ack *extack)
d79b6df6
OG		 2845{
2846 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2847 int i, action_size, first, last, next_z;
88f30bbc
DL		 2848 void *headers_c, *headers_v, *action, *vals_p;
2849 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2850 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2851 struct mlx5_fields *f;
82198d8b 2852 unsigned long mask, field_mask;
6ae4a6a5 2853 int err;
88f30bbc
DL		 2854 u8 cmd;
2855
6ae4a6a5 2856 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2857 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2858 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2859
73867881
PNA		 2860 set_masks = &hdrs[0].masks;
2861 add_masks = &hdrs[1].masks;
2862 set_vals = &hdrs[0].vals;
2863 add_vals = &hdrs[1].vals;
d79b6df6 2864
d65dbedf 2865 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2866
2867 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2868 bool skip;
2869
d79b6df6
OG		 2870 f = &fields[i];
2871 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2872 s_mask = 0;
2873 a_mask = 0;
d79b6df6
OG		 2874
2875 s_masks_p = (void *)set_masks + f->offset;
2876 a_masks_p = (void *)add_masks + f->offset;
2877
88f30bbc
DL		 2878 s_mask = *s_masks_p & f->field_mask;
2879 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2880
2881 if (!s_mask && !a_mask) /* nothing to offload here */
2882 continue;
2883
2884 if (s_mask && a_mask) {
e98bedf5
EB		 2885 NL_SET_ERR_MSG_MOD(extack,
2886 "can't set and add to the same HW field");
d79b6df6
OG		 2887 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
2888 return -EOPNOTSUPP;
2889 }
2890
27c11b6b 2891 skip = false;
d79b6df6 2892 if (s_mask) {
27c11b6b
EB		 2893 void *match_mask = headers_c + f->match_offset;
2894 void *match_val = headers_v + f->match_offset;
2895
d79b6df6
OG		 2896 cmd = MLX5_ACTION_TYPE_SET;
2897 mask = s_mask;
2898 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2899 /* don't rewrite if we have a match on the same value */
2900 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2901 match_mask, f->field_bsize))
27c11b6b 2902 skip = true;
d79b6df6 2903 /* clear to denote we consumed this field */
88f30bbc 2904 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2905 } else {
2906 cmd = MLX5_ACTION_TYPE_ADD;
2907 mask = a_mask;
2908 vals_p = (void *)add_vals + f->offset;
27c11b6b 2909 /* add 0 is no change */
88f30bbc 2910 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2911 skip = true;
d79b6df6 2912 /* clear to denote we consumed this field */
88f30bbc 2913 *a_masks_p &= ~f->field_mask;
d79b6df6 2914 }
27c11b6b
EB		 2915 if (skip)
2916 continue;
d79b6df6 2917
82198d8b 2918 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2919
88f30bbc
DL		 2920 first = find_first_bit(&mask, f->field_bsize);
2921 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2922 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2923 if (first < next_z && next_z < last) {
e98bedf5
EB		 2924 NL_SET_ERR_MSG_MOD(extack,
2925 "rewrite of few sub-fields isn't supported");
2b64beba 2926 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2927 mask);
2928 return -EOPNOTSUPP;
2929 }
2930
6ae4a6a5
PB		 2931 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2932 if (err) {
2933 NL_SET_ERR_MSG_MOD(extack,
2934 "too many pedit actions, can't offload");
2935 mlx5_core_warn(priv->mdev,
2936 "mlx5: parsed %d pedit actions, can't do more\n",
2937 mod_acts->num_actions);
2938 return err;
2939 }
2940
2941 action = mod_acts->actions +
2942 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2943 MLX5_SET(set_action_in, action, action_type, cmd);
2944 MLX5_SET(set_action_in, action, field, f->field);
2945
2946 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2947 int start;
2948
82198d8b
MD		 2949 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2950
88f30bbc 2951 /* if field is bit sized it can start not from first bit */
82198d8b 2952 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2953
2954 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2955 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2956 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2957 }
2958
88f30bbc 2959 if (f->field_bsize == 32)
2b64beba 2960 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2961 else if (f->field_bsize == 16)
2b64beba 2962 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2963 else if (f->field_bsize == 8)
2b64beba 2964 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2965
6ae4a6a5 2966 ++mod_acts->num_actions;
d79b6df6
OG		 2967 }
2968
d79b6df6
OG		 2969 return 0;
2970}
2971
2cc1cb1d
TZ		 2972static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2973 int namespace)
2974{
2975 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2976 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2977 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2978 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2979}
2980
6ae4a6a5
PB		 2981int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2982 int namespace,
2983 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2984{
6ae4a6a5
PB		 2985 int action_size, new_num_actions, max_hw_actions;
2986 size_t new_sz, old_sz;
2987 void *ret;
d79b6df6 2988
6ae4a6a5
PB		 2989 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2990 return 0;
d79b6df6 2991
d65dbedf 2992 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2993
6ae4a6a5
PB		 2994 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2995 namespace);
2996 new_num_actions = min(max_hw_actions,
2997 mod_hdr_acts->actions ?
2998 mod_hdr_acts->max_actions * 2 : 1);
2999 if (mod_hdr_acts->max_actions == new_num_actions)
3000 return -ENOSPC;
3001
3002 new_sz = action_size * new_num_actions;
3003 old_sz = mod_hdr_acts->max_actions * action_size;
3004 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
3005 if (!ret)
d79b6df6
OG		 3006 return -ENOMEM;
3007
6ae4a6a5
PB		 3008 memset(ret + old_sz, 0, new_sz - old_sz);
3009 mod_hdr_acts->actions = ret;
3010 mod_hdr_acts->max_actions = new_num_actions;
3011
d79b6df6
OG		 3012 return 0;
3013}
3014
6ae4a6a5
PB		 3015void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
3016{
3017 kfree(mod_hdr_acts->actions);
3018 mod_hdr_acts->actions = NULL;
3019 mod_hdr_acts->num_actions = 0;
3020 mod_hdr_acts->max_actions = 0;
3021}
3022
d79b6df6
OG		 3023static const struct pedit_headers zero_masks = {};
3024
582234b4
EC		 3025static int
3026parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
3027 const struct flow_action_entry *act, int namespace,
3028 struct mlx5e_tc_flow_parse_attr *parse_attr,
3029 struct pedit_headers_action *hdrs,
3030 struct netlink_ext_ack *extack)
d79b6df6 3031{
73867881
PNA		 3032 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
3033 int err = -EOPNOTSUPP;
d79b6df6 3034 u32 mask, val, offset;
73867881 3035 u8 htype;
d79b6df6 3036
73867881
PNA		 3037 htype = act->mangle.htype;
3038 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 3039
73867881
PNA		 3040 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
3041 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
3042 goto out_err;
3043 }
d79b6df6 3044
2cc1cb1d
TZ		 3045 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
3046 NL_SET_ERR_MSG_MOD(extack,
3047 "The pedit offload action is not supported");
3048 goto out_err;
3049 }
3050
73867881
PNA		 3051 mask = act->mangle.mask;
3052 val = act->mangle.val;
3053 offset = act->mangle.offset;
d79b6df6 3054
73867881
PNA		 3055 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]);
3056 if (err)
3057 goto out_err;
c500c86b 3058
73867881 3059 hdrs[cmd].pedits++;
d79b6df6 3060
c500c86b
PNA		 3061 return 0;
3062out_err:
3063 return err;
3064}
3065
582234b4
EC		 3066static int
3067parse_pedit_to_reformat(struct mlx5e_priv *priv,
3068 const struct flow_action_entry *act,
3069 struct mlx5e_tc_flow_parse_attr *parse_attr,
3070 struct netlink_ext_ack *extack)
3071{
3072 u32 mask, val, offset;
3073 u32 *p;
3074
3075 if (act->id != FLOW_ACTION_MANGLE)
3076 return -EOPNOTSUPP;
3077
3078 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
3079 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
3080 return -EOPNOTSUPP;
3081 }
3082
3083 mask = ~act->mangle.mask;
3084 val = act->mangle.val;
3085 offset = act->mangle.offset;
3086 p = (u32 *)&parse_attr->eth;
3087 *(p + (offset >> 2)) |= (val & mask);
3088
3089 return 0;
3090}
3091
3092static int parse_tc_pedit_action(struct mlx5e_priv *priv,
3093 const struct flow_action_entry *act, int namespace,
3094 struct mlx5e_tc_flow_parse_attr *parse_attr,
3095 struct pedit_headers_action *hdrs,
3096 struct mlx5e_tc_flow *flow,
3097 struct netlink_ext_ack *extack)
3098{
3099 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
3100 return parse_pedit_to_reformat(priv, act, parse_attr, extack);
3101
3102 return parse_pedit_to_modify_hdr(priv, act, namespace,
3103 parse_attr, hdrs, extack);
3104}
3105
c500c86b
PNA		 3106static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3107 struct mlx5e_tc_flow_parse_attr *parse_attr,
3108 struct pedit_headers_action *hdrs,
27c11b6b 3109 u32 *action_flags,
c500c86b
PNA		 3110 struct netlink_ext_ack *extack)
3111{
3112 struct pedit_headers *cmd_masks;
3113 int err;
3114 u8 cmd;
3115
6ae4a6a5
PB		 3116 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
3117 action_flags, extack);
d79b6df6
OG		 3118 if (err < 0)
3119 goto out_dealloc_parsed_actions;
3120
3121 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 3122 cmd_masks = &hdrs[cmd].masks;
d79b6df6 3123 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 3124 NL_SET_ERR_MSG_MOD(extack,
3125 "attempt to offload an unsupported field");
b3a433de 3126 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3127 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3128 16, 1, cmd_masks, sizeof(zero_masks), true);
3129 err = -EOPNOTSUPP;
3130 goto out_dealloc_parsed_actions;
3131 }
3132 }
3133
3134 return 0;
3135
3136out_dealloc_parsed_actions:
6ae4a6a5 3137 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3138 return err;
3139}
3140
e98bedf5
EB		 3141static bool csum_offload_supported(struct mlx5e_priv *priv,
3142 u32 action,
3143 u32 update_flags,
3144 struct netlink_ext_ack *extack)
26c02749
OG		 3145{
3146 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3147 TCA_CSUM_UPDATE_FLAG_UDP;
3148
3149 /* The HW recalcs checksums only if re-writing headers */
3150 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3151 NL_SET_ERR_MSG_MOD(extack,
3152 "TC csum action is only offloaded with pedit");
26c02749
OG		 3153 netdev_warn(priv->netdev,
3154 "TC csum action is only offloaded with pedit\n");
3155 return false;
3156 }
3157
3158 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3159 NL_SET_ERR_MSG_MOD(extack,
3160 "can't offload TC csum action for some header/s");
26c02749
OG		 3161 netdev_warn(priv->netdev,
3162 "can't offload TC csum action for some header/s - flags %#x\n",
3163 update_flags);
3164 return false;
3165 }
3166
3167 return true;
3168}
3169
8998576b
DL		 3170struct ip_ttl_word {
3171 __u8 ttl;
3172 __u8 protocol;
3173 __sum16 check;
3174};
3175
3176struct ipv6_hoplimit_word {
3177 __be16 payload_len;
3178 __u8 nexthdr;
3179 __u8 hop_limit;
3180};
3181
4c3844d9
PB		 3182static int is_action_keys_supported(const struct flow_action_entry *act,
3183 bool ct_flow, bool *modify_ip_header,
7e36feeb 3184 bool *modify_tuple,
4c3844d9 3185 struct netlink_ext_ack *extack)
8998576b
DL		 3186{
3187 u32 mask, offset;
3188 u8 htype;
3189
3190 htype = act->mangle.htype;
3191 offset = act->mangle.offset;
3192 mask = ~act->mangle.mask;
3193 /* For IPv4 & IPv6 header check 4 byte word,
3194 * to determine that modified fields
3195 * are NOT ttl & hop_limit only.
3196 */
3197 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3198 struct ip_ttl_word *ttl_word =
3199 (struct ip_ttl_word *)&mask;
3200
3201 if (offset != offsetof(struct iphdr, ttl) ||
3202 ttl_word->protocol ||
3203 ttl_word->check) {
4c3844d9
PB		 3204 *modify_ip_header = true;
3205 }
3206
7e36feeb
PB		 3207 if (offset >= offsetof(struct iphdr, saddr))
3208 *modify_tuple = true;
3209
3210 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3211 NL_SET_ERR_MSG_MOD(extack,
3212 "can't offload re-write of ipv4 address with action ct");
3213 return -EOPNOTSUPP;
8998576b
DL		 3214 }
3215 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3216 struct ipv6_hoplimit_word *hoplimit_word =
3217 (struct ipv6_hoplimit_word *)&mask;
3218
3219 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3220 hoplimit_word->payload_len ||
3221 hoplimit_word->nexthdr) {
4c3844d9
PB		 3222 *modify_ip_header = true;
3223 }
3224
7e36feeb
PB		 3225 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3226 *modify_tuple = true;
3227
3228 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3229 NL_SET_ERR_MSG_MOD(extack,
3230 "can't offload re-write of ipv6 address with action ct");
3231 return -EOPNOTSUPP;
8998576b 3232 }
7e36feeb
PB		 3233 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3234 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3235 *modify_tuple = true;
3236 if (ct_flow) {
3237 NL_SET_ERR_MSG_MOD(extack,
3238 "can't offload re-write of transport header ports with action ct");
3239 return -EOPNOTSUPP;
3240 }
8998576b 3241 }
4c3844d9
PB		 3242
3243 return 0;
8998576b
DL		 3244}
3245
3d486ec4
OS		 3246static bool modify_header_match_supported(struct mlx5e_priv *priv,
3247 struct mlx5_flow_spec *spec,
73867881 3248 struct flow_action *flow_action,
4c3844d9 3249 u32 actions, bool ct_flow,
7e36feeb 3250 bool ct_clear,
e98bedf5 3251 struct netlink_ext_ack *extack)
bdd66ac0 3252{
73867881 3253 const struct flow_action_entry *act;
7e36feeb 3254 bool modify_ip_header, modify_tuple;
fca53304 3255 void *headers_c;
bdd66ac0
OG		 3256 void *headers_v;
3257 u16 ethertype;
8998576b 3258 u8 ip_proto;
4c3844d9 3259 int i, err;
bdd66ac0 3260
fca53304 3261 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3262 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3263 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3264
3265 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3266 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3267 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3268 goto out_ok;
3269
3270 modify_ip_header = false;
7e36feeb 3271 modify_tuple = false;
73867881
PNA		 3272 flow_action_for_each(i, act, flow_action) {
3273 if (act->id != FLOW_ACTION_MANGLE &&
3274 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3275 continue;
3276
4c3844d9 3277 err = is_action_keys_supported(act, ct_flow,
7e36feeb
PB		 3278 &modify_ip_header,
3279 &modify_tuple, extack);
4c3844d9
PB		 3280 if (err)
3281 return err;
bdd66ac0
OG		 3282 }
3283
7e36feeb
PB		 3284 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3285 * (or after clear action), as otherwise, since the tuple is changed,
3286 * we can't restore ct state
3287 */
3288 if (!ct_clear && modify_tuple &&
89fbdbae 3289 mlx5_tc_ct_add_no_trk_match(spec)) {
7e36feeb
PB		 3290 NL_SET_ERR_MSG_MOD(extack,
3291 "can't offload tuple modify header with ct matches");
3292 netdev_info(priv->netdev,
3293 "can't offload tuple modify header with ct matches");
3294 return false;
3295 }
3296
bdd66ac0 3297 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3298 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3299 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3300 NL_SET_ERR_MSG_MOD(extack,
3301 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3302 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3303 ip_proto);
bdd66ac0
OG		 3304 return false;
3305 }
3306
3307out_ok:
3308 return true;
3309}
3310
3311static bool actions_match_supported(struct mlx5e_priv *priv,
73867881 3312 struct flow_action *flow_action,
bdd66ac0 3313 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3314 struct mlx5e_tc_flow *flow,
3315 struct netlink_ext_ack *extack)
bdd66ac0 3316{
a7c119bd 3317 bool ct_flow = false, ct_clear = false;
bdd66ac0
OG		 3318 u32 actions;
3319
c620b772
AL		 3320 ct_clear = flow->attr->ct_attr.ct_action &
3321 TCA_CT_ACT_CLEAR;
3322 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3323 actions = flow->attr->action;
3324
4c3844d9 3325 if (mlx5e_is_eswitch_flow(flow)) {
c620b772 3326 if (flow->attr->esw_attr->split_count && ct_flow) {
4c3844d9
PB		 3327 /* All registers used by ct are cleared when using
3328 * split rules.
3329 */
3330 NL_SET_ERR_MSG_MOD(extack,
3331 "Can't offload mirroring with action ct");
49397b80 3332 return false;
4c3844d9 3333 }
4c3844d9 3334 }
bdd66ac0
OG		 3335
3336 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3d486ec4 3337 return modify_header_match_supported(priv, &parse_attr->spec,
a655fe9f 3338 flow_action, actions,
7e36feeb
PB		 3339 ct_flow, ct_clear,
3340 extack);
bdd66ac0
OG		 3341
3342 return true;
3343}
3344
32134847
MD		 3345static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3346{
3347 return priv->mdev == peer_priv->mdev;
3348}
3349
5c65c564
OG		 3350static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3351{
3352 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3353 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3354
3355 fmdev = priv->mdev;
3356 pmdev = peer_priv->mdev;
3357
59c9d35e
AH		 3358 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3359 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3360
816f6706 3361 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3362}
3363
bdc837ee
EB		 3364static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3365 const struct flow_action_entry *act,
3366 struct mlx5e_tc_flow_parse_attr *parse_attr,
3367 struct pedit_headers_action *hdrs,
3368 u32 *action, struct netlink_ext_ack *extack)
3369{
3370 u16 mask16 = VLAN_VID_MASK;
3371 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3372 const struct flow_action_entry pedit_act = {
3373 .id = FLOW_ACTION_MANGLE,
3374 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3375 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3376 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3377 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3378 };
6fca9d1e 3379 u8 match_prio_mask, match_prio_val;
bf2f3bca 3380 void *headers_c, *headers_v;
bdc837ee
EB		 3381 int err;
3382
bf2f3bca
EB		 3383 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3384 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3385
3386 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3387 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3388 NL_SET_ERR_MSG_MOD(extack,
3389 "VLAN rewrite action must have VLAN protocol match");
3390 return -EOPNOTSUPP;
3391 }
3392
6fca9d1e
EB		 3393 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3394 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3395 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3396 NL_SET_ERR_MSG_MOD(extack,
3397 "Changing VLAN prio is not supported");
bdc837ee
EB		 3398 return -EOPNOTSUPP;
3399 }
3400
582234b4 3401 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3402 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3403
3404 return err;
3405}
3406
0bac1194
EB		 3407static int
3408add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3409 struct mlx5e_tc_flow_parse_attr *parse_attr,
3410 struct pedit_headers_action *hdrs,
3411 u32 *action, struct netlink_ext_ack *extack)
3412{
3413 const struct flow_action_entry prio_tag_act = {
3414 .vlan.vid = 0,
3415 .vlan.prio =
3416 MLX5_GET(fte_match_set_lyr_2_4,
3417 get_match_headers_value(*action,
3418 &parse_attr->spec),
3419 first_prio) &
3420 MLX5_GET(fte_match_set_lyr_2_4,
3421 get_match_headers_criteria(*action,
3422 &parse_attr->spec),
3423 first_prio),
3424 };
3425
3426 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3427 &prio_tag_act, parse_attr, hdrs, action,
3428 extack);
3429}
3430
c7569097
AL		 3431static int validate_goto_chain(struct mlx5e_priv *priv,
3432 struct mlx5e_tc_flow *flow,
3433 const struct flow_action_entry *act,
3434 u32 actions,
3435 struct netlink_ext_ack *extack)
3436{
3437 bool is_esw = mlx5e_is_eswitch_flow(flow);
3438 struct mlx5_flow_attr *attr = flow->attr;
3439 bool ft_flow = mlx5e_is_ft_flow(flow);
3440 u32 dest_chain = act->chain_index;
3441 struct mlx5_fs_chains *chains;
3442 struct mlx5_eswitch *esw;
3443 u32 reformat_and_fwd;
3444 u32 max_chain;
3445
3446 esw = priv->mdev->priv.eswitch;
3447 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3448 max_chain = mlx5_chains_get_chain_range(chains);
3449 reformat_and_fwd = is_esw ?
3450 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3451 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3452
3453 if (ft_flow) {
3454 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3455 return -EOPNOTSUPP;
3456 }
3457
3458 if (!mlx5_chains_backwards_supported(chains) &&
3459 dest_chain <= attr->chain) {
3460 NL_SET_ERR_MSG_MOD(extack,
3461 "Goto lower numbered chain isn't supported");
3462 return -EOPNOTSUPP;
3463 }
3464
3465 if (dest_chain > max_chain) {
3466 NL_SET_ERR_MSG_MOD(extack,
3467 "Requested destination chain is out of supported range");
3468 return -EOPNOTSUPP;
3469 }
3470
3471 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3472 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3473 !reformat_and_fwd) {
3474 NL_SET_ERR_MSG_MOD(extack,
3475 "Goto chain is not allowed if action has reformat or decap");
3476 return -EOPNOTSUPP;
3477 }
3478
3479 return 0;
3480}
3481
73867881
PNA		 3482static int parse_tc_nic_actions(struct mlx5e_priv *priv,
3483 struct flow_action *flow_action,
aa0cbbae 3484 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 3485 struct mlx5e_tc_flow *flow,
3486 struct netlink_ext_ack *extack)
e3a2b7ed 3487{
c620b772 3488 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3489 struct pedit_headers_action hdrs[2] = {};
3490 const struct flow_action_entry *act;
c620b772 3491 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3492 u32 action = 0;
244cd96a 3493 int err, i;
e3a2b7ed 3494
73867881 3495 if (!flow_action_has_entries(flow_action))
e3a2b7ed
AV		 3496 return -EINVAL;
3497
53eca1f3
JK		 3498 if (!flow_action_hw_stats_check(flow_action, extack,
3499 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 3500 return -EOPNOTSUPP;
3501
c620b772
AL		 3502 nic_attr = attr->nic_attr;
3503
3504 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 3505
73867881
PNA		 3506 flow_action_for_each(i, act, flow_action) {
3507 switch (act->id) {
15fc92ec
TZ		 3508 case FLOW_ACTION_ACCEPT:
3509 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3510 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3511 break;
73867881 3512 case FLOW_ACTION_DROP:
1cab1cd7 3513 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 3514 if (MLX5_CAP_FLOWTABLE(priv->mdev,
3515 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 3516 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3517 break;
3518 case FLOW_ACTION_MANGLE:
3519 case FLOW_ACTION_ADD:
3520 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3521 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3522 if (err)
3523 return err;
3524
c7569097 3525 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3526 break;
bdc837ee
EB		 3527 case FLOW_ACTION_VLAN_MANGLE:
3528 err = add_vlan_rewrite_action(priv,
3529 MLX5_FLOW_NAMESPACE_KERNEL,
3530 act, parse_attr, hdrs,
3531 &action, extack);
3532 if (err)
3533 return err;
3534
3535 break;
73867881 3536 case FLOW_ACTION_CSUM:
1cab1cd7 3537 if (csum_offload_supported(priv, action,
73867881 3538 act->csum_flags,
e98bedf5 3539 extack))
73867881 3540 break;
26c02749
OG		 3541
3542 return -EOPNOTSUPP;
73867881
PNA		 3543 case FLOW_ACTION_REDIRECT: {
3544 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3545
3546 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3547 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3548 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3549 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3550 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3551 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3552 } else {
e98bedf5
EB		 3553 NL_SET_ERR_MSG_MOD(extack,
3554 "device is not on same HW, can't offload");
5c65c564
OG		 3555 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3556 peer_dev->name);
3557 return -EINVAL;
3558 }
73867881
PNA		 3559 }
3560 break;
3561 case FLOW_ACTION_MARK: {
3562 u32 mark = act->mark;
e3a2b7ed
AV		 3563
3564 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3565 NL_SET_ERR_MSG_MOD(extack,
3566 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 3567 return -EINVAL;
3568 }
3569
c620b772 3570 nic_attr->flow_tag = mark;
1cab1cd7 3571 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3572 }
3573 break;
c7569097
AL		 3574 case FLOW_ACTION_GOTO:
3575 err = validate_goto_chain(priv, flow, act, action,
3576 extack);
3577 if (err)
3578 return err;
3579
3580 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3581 attr->dest_chain = act->chain_index;
3582 break;
aedd133d
AL		 3583 case FLOW_ACTION_CT:
3584 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3585 if (err)
3586 return err;
3587
3588 flow_flag_set(flow, CT);
3589 break;
73867881 3590 default:
2cc1cb1d
TZ		 3591 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
3592 return -EOPNOTSUPP;
e3a2b7ed 3593 }
e3a2b7ed
AV		 3594 }
3595
c500c86b
PNA		 3596 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
3597 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
3598 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL,
27c11b6b 3599 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 3600 if (err)
3601 return err;
27c11b6b
EB		 3602 /* in case all pedit actions are skipped, remove the MOD_HDR
3603 * flag.
3604 */
6ae4a6a5 3605 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 3606 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 3607 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
e7739a60 3608 }
c500c86b
PNA		 3609 }
3610
1cab1cd7 3611 attr->action = action;
c7569097
AL		 3612
3613 if (attr->dest_chain) {
3614 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
3615 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3616 return -EOPNOTSUPP;
3617 }
3618 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3619 }
3620
3621 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3622 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3623
73867881 3624 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3625 return -EOPNOTSUPP;
3626
e3a2b7ed
AV		 3627 return 0;
3628}
3629
7f1a546e 3630struct encap_key {
1f6da306 3631 const struct ip_tunnel_key *ip_tun_key;
d386939a 3632 struct mlx5e_tc_tunnel *tc_tunnel;
7f1a546e
EB		 3633};
3634
3635static inline int cmp_encap_info(struct encap_key *a,
3636 struct encap_key *b)
a54e20b4 3637{
7f1a546e 3638 return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) ||
d386939a 3639 a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type;
a54e20b4
HHZ		 3640}
3641
14e6b038
EC		 3642static inline int cmp_decap_info(struct mlx5e_decap_key *a,
3643 struct mlx5e_decap_key *b)
3644{
3645 return memcmp(&a->key, &b->key, sizeof(b->key));
3646}
3647
7f1a546e 3648static inline int hash_encap_info(struct encap_key *key)
a54e20b4 3649{
7f1a546e 3650 return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key),
d386939a 3651 key->tc_tunnel->tunnel_type);
a54e20b4
HHZ		 3652}
3653
14e6b038
EC		 3654static inline int hash_decap_info(struct mlx5e_decap_key *key)
3655{
3656 return jhash(&key->key, sizeof(key->key), 0);
3657}
a54e20b4 3658
32134847 3659static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3660 struct net_device *peer_netdev)
3661{
3662 struct mlx5e_priv *peer_priv;
3663
3664 peer_priv = netdev_priv(peer_netdev);
3665
3666 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3667 mlx5e_eswitch_vf_rep(priv->netdev) &&
3668 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3669 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3670}
3671
948993f2
VB		 3672bool mlx5e_encap_take(struct mlx5e_encap_entry *e)
3673{
3674 return refcount_inc_not_zero(&e->refcnt);
3675}
3676
14e6b038
EC		 3677static bool mlx5e_decap_take(struct mlx5e_decap_entry *e)
3678{
3679 return refcount_inc_not_zero(&e->refcnt);
3680}
3681
948993f2
VB		 3682static struct mlx5e_encap_entry *
3683mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key,
3684 uintptr_t hash_key)
3685{
3686 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3687 struct mlx5e_encap_entry *e;
3688 struct encap_key e_key;
3689
3690 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
3691 encap_hlist, hash_key) {
3692 e_key.ip_tun_key = &e->tun_info->key;
3693 e_key.tc_tunnel = e->tunnel;
3694 if (!cmp_encap_info(&e_key, key) &&
3695 mlx5e_encap_take(e))
3696 return e;
3697 }
3698
3699 return NULL;
3700}
3701
14e6b038
EC		 3702static struct mlx5e_decap_entry *
3703mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key,
3704 uintptr_t hash_key)
3705{
3706 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3707 struct mlx5e_decap_key r_key;
3708 struct mlx5e_decap_entry *e;
3709
3710 hash_for_each_possible_rcu(esw->offloads.decap_tbl, e,
3711 hlist, hash_key) {
3712 r_key = e->key;
3713 if (!cmp_decap_info(&r_key, key) &&
3714 mlx5e_decap_take(e))
3715 return e;
3716 }
3717 return NULL;
3718}
3719
2a4b6526
VB		 3720static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info)
3721{
3722 size_t tun_size = sizeof(*tun_info) + tun_info->options_len;
3723
3724 return kmemdup(tun_info, tun_size, GFP_KERNEL);
3725}
3726
554fe75c
DL		 3727static bool is_duplicated_encap_entry(struct mlx5e_priv *priv,
3728 struct mlx5e_tc_flow *flow,
3729 int out_index,
3730 struct mlx5e_encap_entry *e,
3731 struct netlink_ext_ack *extack)
3732{
3733 int i;
3734
3735 for (i = 0; i < out_index; i++) {
3736 if (flow->encaps[i].e != e)
3737 continue;
3738 NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action");
3739 netdev_err(priv->netdev, "can't duplicate encap action\n");
3740 return true;
3741 }
3742
3743 return false;
3744}
3745
10742efc
VB		 3746static int mlx5e_set_vf_tunnel(struct mlx5_eswitch *esw,
3747 struct mlx5_flow_attr *attr,
3748 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
3749 struct net_device *out_dev,
3750 int route_dev_ifindex,
3751 int out_index)
3752{
3753 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
3754 struct net_device *route_dev;
3755 u16 vport_num;
3756 int err = 0;
3757 u32 data;
3758
3759 route_dev = dev_get_by_index(dev_net(out_dev), route_dev_ifindex);
3760
3761 if (!route_dev || route_dev->netdev_ops != &mlx5e_netdev_ops ||
3762 !mlx5e_tc_is_vf_tunnel(out_dev, route_dev))
3763 goto out;
3764
3765 err = mlx5e_tc_query_route_vport(out_dev, route_dev, &vport_num);
3766 if (err)
3767 goto out;
3768
3769 attr->dest_chain = 0;
3770 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3771 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
3772 data = mlx5_eswitch_get_vport_metadata_for_set(esw_attr->in_mdev->priv.eswitch,
3773 vport_num);
3774 err = mlx5e_tc_match_to_reg_set(esw->dev, mod_hdr_acts,
3775 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG, data);
3776 if (err)
3777 goto out;
3778
3779out:
3780 if (route_dev)
3781 dev_put(route_dev);
3782 return err;
3783}
3784
a54e20b4 3785static int mlx5e_attach_encap(struct mlx5e_priv *priv,
e98bedf5 3786 struct mlx5e_tc_flow *flow,
733d4f36
RD		 3787 struct net_device *mirred_dev,
3788 int out_index,
8c4dc42b 3789 struct netlink_ext_ack *extack,
0ad060ee
RD		 3790 struct net_device **encap_dev,
3791 bool *encap_valid)
a54e20b4
HHZ		 3792{
3793 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
733d4f36 3794 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3795 struct mlx5_flow_attr *attr = flow->attr;
1f6da306 3796 const struct ip_tunnel_info *tun_info;
948993f2 3797 struct encap_key key;
c1ae1152 3798 struct mlx5e_encap_entry *e;
733d4f36 3799 unsigned short family;
a54e20b4 3800 uintptr_t hash_key;
54c177ca 3801 int err = 0;
a54e20b4 3802
733d4f36 3803 parse_attr = attr->parse_attr;
1f6da306 3804 tun_info = parse_attr->tun_info[out_index];
733d4f36 3805 family = ip_tunnel_info_af(tun_info);
7f1a546e 3806 key.ip_tun_key = &tun_info->key;
d386939a 3807 key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev);
d71f895c
EC		 3808 if (!key.tc_tunnel) {
3809 NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel");
3810 return -EOPNOTSUPP;
3811 }
733d4f36 3812
7f1a546e 3813 hash_key = hash_encap_info(&key);
a54e20b4 3814
61086f39 3815 mutex_lock(&esw->offloads.encap_tbl_lock);
948993f2 3816 e = mlx5e_encap_get(priv, &key, hash_key);
a54e20b4 3817
b2812089 3818 /* must verify if encap is valid or not */
d589e785 3819 if (e) {
554fe75c
DL		 3820 /* Check that entry was not already attached to this flow */
3821 if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) {
3822 err = -EOPNOTSUPP;
3823 goto out_err;
3824 }
3825
d589e785
VB		 3826 mutex_unlock(&esw->offloads.encap_tbl_lock);
3827 wait_for_completion(&e->res_ready);
3828
3829 /* Protect against concurrent neigh update. */
3830 mutex_lock(&esw->offloads.encap_tbl_lock);
3c140dd5 3831 if (e->compl_result < 0) {
d589e785
VB		 3832 err = -EREMOTEIO;
3833 goto out_err;
3834 }
45247bf2 3835 goto attach_flow;
d589e785 3836 }
a54e20b4
HHZ		 3837
3838 e = kzalloc(sizeof(*e), GFP_KERNEL);
61086f39
VB		 3839 if (!e) {
3840 err = -ENOMEM;
3841 goto out_err;
3842 }
a54e20b4 3843
948993f2 3844 refcount_set(&e->refcnt, 1);
d589e785
VB		 3845 init_completion(&e->res_ready);
3846
2a4b6526
VB		 3847 tun_info = dup_tun_info(tun_info);
3848 if (!tun_info) {
3849 err = -ENOMEM;
3850 goto out_err_init;
3851 }
1f6da306 3852 e->tun_info = tun_info;
101f4de9 3853 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
2a4b6526
VB		 3854 if (err)
3855 goto out_err_init;
54c177ca 3856
a54e20b4 3857 INIT_LIST_HEAD(&e->flows);
d589e785
VB		 3858 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
3859 mutex_unlock(&esw->offloads.encap_tbl_lock);
a54e20b4 3860
ce99f6b9 3861 if (family == AF_INET)
101f4de9 3862 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 3863 else if (family == AF_INET6)
101f4de9 3864 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 3865
d589e785
VB		 3866 /* Protect against concurrent neigh update. */
3867 mutex_lock(&esw->offloads.encap_tbl_lock);
3868 complete_all(&e->res_ready);
3869 if (err) {
3870 e->compl_result = err;
a54e20b4 3871 goto out_err;
d589e785 3872 }
3c140dd5 3873 e->compl_result = 1;
a54e20b4 3874
45247bf2 3875attach_flow:
10742efc
VB		 3876 err = mlx5e_set_vf_tunnel(esw, attr, &parse_attr->mod_hdr_acts, e->out_dev,
3877 e->route_dev_ifindex, out_index);
3878 if (err)
3879 goto out_err;
3880
948993f2 3881 flow->encaps[out_index].e = e;
8c4dc42b
EB		 3882 list_add(&flow->encaps[out_index].list, &e->flows);
3883 flow->encaps[out_index].index = out_index;
45247bf2 3884 *encap_dev = e->out_dev;
8c4dc42b 3885 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
c620b772
AL		 3886 attr->esw_attr->dests[out_index].pkt_reformat = e->pkt_reformat;
3887 attr->esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
0ad060ee 3888 *encap_valid = true;
8c4dc42b 3889 } else {
0ad060ee 3890 *encap_valid = false;
8c4dc42b 3891 }
61086f39 3892 mutex_unlock(&esw->offloads.encap_tbl_lock);
45247bf2 3893
232c0013 3894 return err;
a54e20b4
HHZ		 3895
3896out_err:
61086f39 3897 mutex_unlock(&esw->offloads.encap_tbl_lock);
d589e785
VB		 3898 if (e)
3899 mlx5e_encap_put(priv, e);
a54e20b4 3900 return err;
2a4b6526
VB		 3901
3902out_err_init:
3903 mutex_unlock(&esw->offloads.encap_tbl_lock);
3904 kfree(tun_info);
3905 kfree(e);
3906 return err;
a54e20b4
HHZ		 3907}
3908
14e6b038
EC		 3909static int mlx5e_attach_decap(struct mlx5e_priv *priv,
3910 struct mlx5e_tc_flow *flow,
3911 struct netlink_ext_ack *extack)
3912{
3913 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3914 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
14e6b038
EC		 3915 struct mlx5e_tc_flow_parse_attr *parse_attr;
3916 struct mlx5e_decap_entry *d;
3917 struct mlx5e_decap_key key;
3918 uintptr_t hash_key;
28619046 3919 int err = 0;
14e6b038 3920
c620b772 3921 parse_attr = flow->attr->parse_attr;
14e6b038
EC		 3922 if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) {
3923 NL_SET_ERR_MSG_MOD(extack,
3924 "encap header larger than max supported");
3925 return -EOPNOTSUPP;
3926 }
3927
3928 key.key = parse_attr->eth;
3929 hash_key = hash_decap_info(&key);
3930 mutex_lock(&esw->offloads.decap_tbl_lock);
3931 d = mlx5e_decap_get(priv, &key, hash_key);
3932 if (d) {
3933 mutex_unlock(&esw->offloads.decap_tbl_lock);
3934 wait_for_completion(&d->res_ready);
3935 mutex_lock(&esw->offloads.decap_tbl_lock);
3936 if (d->compl_result) {
3937 err = -EREMOTEIO;
3938 goto out_free;
3939 }
3940 goto found;
3941 }
3942
3943 d = kzalloc(sizeof(*d), GFP_KERNEL);
3944 if (!d) {
3945 err = -ENOMEM;
3946 goto out_err;
3947 }
3948
3949 d->key = key;
3950 refcount_set(&d->refcnt, 1);
3951 init_completion(&d->res_ready);
3952 INIT_LIST_HEAD(&d->flows);
3953 hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key);
3954 mutex_unlock(&esw->offloads.decap_tbl_lock);
3955
3956 d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev,
3957 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2,
3958 sizeof(parse_attr->eth),
3959 &parse_attr->eth,
3960 MLX5_FLOW_NAMESPACE_FDB);
3961 if (IS_ERR(d->pkt_reformat)) {
3962 err = PTR_ERR(d->pkt_reformat);
3963 d->compl_result = err;
3964 }
3965 mutex_lock(&esw->offloads.decap_tbl_lock);
3966 complete_all(&d->res_ready);
3967 if (err)
3968 goto out_free;
3969
3970found:
3971 flow->decap_reformat = d;
3972 attr->decap_pkt_reformat = d->pkt_reformat;
3973 list_add(&flow->l3_to_l2_reformat, &d->flows);
3974 mutex_unlock(&esw->offloads.decap_tbl_lock);
3975 return 0;
3976
3977out_free:
3978 mutex_unlock(&esw->offloads.decap_tbl_lock);
3979 mlx5e_decap_put(priv, d);
3980 return err;
3981
3982out_err:
3983 mutex_unlock(&esw->offloads.decap_tbl_lock);
3984 return err;
3985}
3986
1482bd3d 3987static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3988 const struct flow_action_entry *act,
1482bd3d
JL		 3989 struct mlx5_esw_flow_attr *attr,
3990 u32 *action)
3991{
cc495188
JL		 3992 u8 vlan_idx = attr->total_vlan;
3993
3994 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
3995 return -EOPNOTSUPP;
3996
73867881
PNA		 3997 switch (act->id) {
3998 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3999 if (vlan_idx) {
4000 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
4001 MLX5_FS_VLAN_DEPTH))
4002 return -EOPNOTSUPP;
4003
4004 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
4005 } else {
4006 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4007 }
73867881
PNA		 4008 break;
4009 case FLOW_ACTION_VLAN_PUSH:
4010 attr->vlan_vid[vlan_idx] = act->vlan.vid;
4011 attr->vlan_prio[vlan_idx] = act->vlan.prio;
4012 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 4013 if (!attr->vlan_proto[vlan_idx])
4014 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
4015
4016 if (vlan_idx) {
4017 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
4018 MLX5_FS_VLAN_DEPTH))
4019 return -EOPNOTSUPP;
4020
4021 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
4022 } else {
4023 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881
PNA		 4024 (act->vlan.proto != htons(ETH_P_8021Q) ||
4025 act->vlan.prio))
cc495188
JL		 4026 return -EOPNOTSUPP;
4027
4028 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 4029 }
73867881
PNA		 4030 break;
4031 default:
bdc837ee 4032 return -EINVAL;
1482bd3d
JL		 4033 }
4034
cc495188
JL		 4035 attr->total_vlan = vlan_idx + 1;
4036
1482bd3d
JL		 4037 return 0;
4038}
4039
d34eb2fc
OG		 4040static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
4041 struct net_device *out_dev)
4042{
4043 struct net_device *fdb_out_dev = out_dev;
4044 struct net_device *uplink_upper;
4045
4046 rcu_read_lock();
4047 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
4048 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
4049 uplink_upper == out_dev) {
4050 fdb_out_dev = uplink_dev;
4051 } else if (netif_is_lag_master(out_dev)) {
4052 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
4053 if (fdb_out_dev &&
4054 (!mlx5e_eswitch_rep(fdb_out_dev) ||
4055 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
4056 fdb_out_dev = NULL;
4057 }
4058 rcu_read_unlock();
4059 return fdb_out_dev;
4060}
4061
278748a9 4062static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 4063 struct mlx5_flow_attr *attr,
278748a9
EB		 4064 struct net_device **out_dev,
4065 u32 *action)
4066{
4067 struct net_device *vlan_dev = *out_dev;
4068 struct flow_action_entry vlan_act = {
4069 .id = FLOW_ACTION_VLAN_PUSH,
4070 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
4071 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
4072 .vlan.prio = 0,
4073 };
4074 int err;
4075
c620b772 4076 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
278748a9
EB		 4077 if (err)
4078 return err;
4079
4080 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev),
4081 dev_get_iflink(vlan_dev));
4082 if (is_vlan_dev(*out_dev))
4083 err = add_vlan_push_action(priv, attr, out_dev, action);
4084
4085 return err;
4086}
4087
35a605db 4088static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 4089 struct mlx5_flow_attr *attr,
35a605db
EB		 4090 u32 *action)
4091{
35a605db
EB		 4092 struct flow_action_entry vlan_act = {
4093 .id = FLOW_ACTION_VLAN_POP,
4094 };
70f478ca 4095 int nest_level, err = 0;
35a605db 4096
70f478ca
DL		 4097 nest_level = attr->parse_attr->filter_dev->lower_level -
4098 priv->netdev->lower_level;
35a605db 4099 while (nest_level--) {
c620b772 4100 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action);
35a605db
EB		 4101 if (err)
4102 return err;
4103 }
4104
4105 return err;
4106}
4107
32134847
MD		 4108static bool same_hw_reps(struct mlx5e_priv *priv,
4109 struct net_device *peer_netdev)
4110{
4111 struct mlx5e_priv *peer_priv;
4112
4113 peer_priv = netdev_priv(peer_netdev);
4114
4115 return mlx5e_eswitch_rep(priv->netdev) &&
4116 mlx5e_eswitch_rep(peer_netdev) &&
4117 same_hw_devs(priv, peer_priv);
4118}
4119
4120static bool is_lag_dev(struct mlx5e_priv *priv,
4121 struct net_device *peer_netdev)
4122{
4123 return ((mlx5_lag_is_sriov(priv->mdev) ||
4124 mlx5_lag_is_multipath(priv->mdev)) &&
4125 same_hw_reps(priv, peer_netdev));
4126}
4127
f6dc1264
PB		 4128bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4129 struct net_device *out_dev)
4130{
32134847
MD		 4131 if (is_merged_eswitch_vfs(priv, out_dev))
4132 return true;
4133
4134 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 4135 return true;
4136
4137 return mlx5e_eswitch_rep(out_dev) &&
32134847 4138 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 4139}
4140
554fe75c
DL		 4141static bool is_duplicated_output_device(struct net_device *dev,
4142 struct net_device *out_dev,
4143 int *ifindexes, int if_count,
4144 struct netlink_ext_ack *extack)
4145{
4146 int i;
4147
4148 for (i = 0; i < if_count; i++) {
4149 if (ifindexes[i] == out_dev->ifindex) {
4150 NL_SET_ERR_MSG_MOD(extack,
4151 "can't duplicate output to same device");
4152 netdev_err(dev, "can't duplicate output to same device: %s\n",
4153 out_dev->name);
4154 return true;
4155 }
4156 }
4157
4158 return false;
4159}
4160
613f53fe
EC		 4161static int verify_uplink_forwarding(struct mlx5e_priv *priv,
4162 struct mlx5e_tc_flow *flow,
4163 struct net_device *out_dev,
4164 struct netlink_ext_ack *extack)
4165{
c620b772 4166 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 4167 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 4168 struct mlx5e_rep_priv *rep_priv;
4169
4170 /* Forwarding non encapsulated traffic between
4171 * uplink ports is allowed only if
4172 * termination_table_raw_traffic cap is set.
4173 *
c620b772 4174 * Input vport was stored attr->in_rep.
613f53fe
EC		 4175 * In LAG case, *priv* is the private data of
4176 * uplink which may be not the input vport.
4177 */
4178 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
4179
4180 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
4181 mlx5e_eswitch_uplink_rep(out_dev)))
4182 return 0;
4183
4184 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
4185 termination_table_raw_traffic)) {
4186 NL_SET_ERR_MSG_MOD(extack,
4187 "devices are both uplink, can't offload forwarding");
4188 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
4189 priv->netdev->name, out_dev->name);
4190 return -EOPNOTSUPP;
4191 } else if (out_dev != rep_priv->netdev) {
4192 NL_SET_ERR_MSG_MOD(extack,
4193 "devices are not the same uplink, can't offload forwarding");
4194 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
4195 priv->netdev->name, out_dev->name);
4196 return -EOPNOTSUPP;
4197 }
4198 return 0;
4199}
4200
73867881
PNA		 4201static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
4202 struct flow_action *flow_action,
e98bedf5 4203 struct mlx5e_tc_flow *flow,
14e6b038
EC		 4204 struct netlink_ext_ack *extack,
4205 struct net_device *filter_dev)
03a9d11e 4206{
73867881 4207 struct pedit_headers_action hdrs[2] = {};
bf07aa73 4208 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4209 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 4210 struct mlx5e_rep_priv *rpriv = priv->ppriv;
73867881 4211 const struct ip_tunnel_info *info = NULL;
c620b772 4212 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 4213 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 4214 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 4215 const struct flow_action_entry *act;
c620b772 4216 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 4217 bool encap = false, decap = false;
4218 u32 action = attr->action;
554fe75c 4219 int err, i, if_count = 0;
f828ca6a 4220 bool mpls_push = false;
03a9d11e 4221
73867881 4222 if (!flow_action_has_entries(flow_action))
03a9d11e
OG		 4223 return -EINVAL;
4224
53eca1f3
JK		 4225 if (!flow_action_hw_stats_check(flow_action, extack,
4226 FLOW_ACTION_HW_STATS_DELAYED_BIT))
319a1d19
JP		 4227 return -EOPNOTSUPP;
4228
c620b772
AL		 4229 esw_attr = attr->esw_attr;
4230 parse_attr = attr->parse_attr;
4231
73867881
PNA		 4232 flow_action_for_each(i, act, flow_action) {
4233 switch (act->id) {
4234 case FLOW_ACTION_DROP:
1cab1cd7
OG		 4235 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
4236 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 4237 break;
f0288210
EC		 4238 case FLOW_ACTION_TRAP:
4239 if (!flow_offload_has_one_action(flow_action)) {
4240 NL_SET_ERR_MSG_MOD(extack,
4241 "action trap is supported as a sole action only");
4242 return -EOPNOTSUPP;
4243 }
4244 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4245 MLX5_FLOW_CONTEXT_ACTION_COUNT);
4246 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
4247 break;
f828ca6a
EC		 4248 case FLOW_ACTION_MPLS_PUSH:
4249 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
4250 reformat_l2_to_l3_tunnel) ||
4251 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
4252 NL_SET_ERR_MSG_MOD(extack,
4253 "mpls push is supported only for mpls_uc protocol");
4254 return -EOPNOTSUPP;
4255 }
4256 mpls_push = true;
4257 break;
14e6b038
EC		 4258 case FLOW_ACTION_MPLS_POP:
4259 /* we only support mpls pop if it is the first action
4260 * and the filter net device is bareudp. Subsequent
4261 * actions can be pedit and the last can be mirred
4262 * egress redirect.
4263 */
4264 if (i) {
4265 NL_SET_ERR_MSG_MOD(extack,
4266 "mpls pop supported only as first action");
4267 return -EOPNOTSUPP;
4268 }
4269 if (!netif_is_bareudp(filter_dev)) {
4270 NL_SET_ERR_MSG_MOD(extack,
4271 "mpls pop supported only on bareudp devices");
4272 return -EOPNOTSUPP;
4273 }
4274
4275 parse_attr->eth.h_proto = act->mpls_pop.proto;
4276 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
4277 flow_flag_set(flow, L3_TO_L2_DECAP);
4278 break;
73867881
PNA		 4279 case FLOW_ACTION_MANGLE:
4280 case FLOW_ACTION_ADD:
4281 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 4282 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 4283 if (err)
4284 return err;
4285
582234b4
EC		 4286 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
4287 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 4288 esw_attr->split_count = esw_attr->out_count;
582234b4 4289 }
73867881
PNA		 4290 break;
4291 case FLOW_ACTION_CSUM:
1cab1cd7 4292 if (csum_offload_supported(priv, action,
73867881
PNA		 4293 act->csum_flags, extack))
4294 break;
26c02749
OG		 4295
4296 return -EOPNOTSUPP;
73867881
PNA		 4297 case FLOW_ACTION_REDIRECT:
4298 case FLOW_ACTION_MIRRED: {
03a9d11e 4299 struct mlx5e_priv *out_priv;
592d3651 4300 struct net_device *out_dev;
03a9d11e 4301
73867881 4302 out_dev = act->dev;
ef381359
OS		 4303 if (!out_dev) {
4304 /* out_dev is NULL when filters with
4305 * non-existing mirred device are replayed to
4306 * the driver.
4307 */
4308 return -EINVAL;
4309 }
03a9d11e 4310
f828ca6a
EC		 4311 if (mpls_push && !netif_is_bareudp(out_dev)) {
4312 NL_SET_ERR_MSG_MOD(extack,
4313 "mpls is supported only through a bareudp device");
4314 return -EOPNOTSUPP;
4315 }
4316
84179981
PB		 4317 if (ft_flow && out_dev == priv->netdev) {
4318 /* Ignore forward to self rules generated
4319 * by adding both mlx5 devs to the flow table
4320 * block on a normal nft offload setup.
4321 */
4322 return -EOPNOTSUPP;
4323 }
4324
c620b772 4325 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 4326 NL_SET_ERR_MSG_MOD(extack,
4327 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 4328 netdev_warn(priv->netdev,
4329 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 4330 esw_attr->out_count);
592d3651
CM		 4331 return -EOPNOTSUPP;
4332 }
4333
f493f155
EB		 4334 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4335 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 4336 if (encap) {
c620b772 4337 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 4338 out_dev->ifindex;
c620b772
AL		 4339 parse_attr->tun_info[esw_attr->out_count] = dup_tun_info(info);
4340 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 4341 return -ENOMEM;
4342 encap = false;
c620b772 4343 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 4344 MLX5_ESW_DEST_ENCAP;
c620b772 4345 esw_attr->out_count++;
b6a4ac24
VB		 4346 /* attr->dests[].rep is resolved when we
4347 * handle encap
4348 */
4349 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 4350 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4351 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 4352
554fe75c
DL		 4353 if (is_duplicated_output_device(priv->netdev,
4354 out_dev,
4355 ifindexes,
4356 if_count,
4357 extack))
4358 return -EOPNOTSUPP;
4359
4360 ifindexes[if_count] = out_dev->ifindex;
4361 if_count++;
4362
d34eb2fc
OG		 4363 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
4364 if (!out_dev)
4365 return -ENODEV;
7ba58ba7 4366
278748a9
EB		 4367 if (is_vlan_dev(out_dev)) {
4368 err = add_vlan_push_action(priv, attr,
4369 &out_dev,
4370 &action);
4371 if (err)
4372 return err;
4373 }
f6dc1264 4374
35a605db
EB		 4375 if (is_vlan_dev(parse_attr->filter_dev)) {
4376 err = add_vlan_pop_action(priv, attr,
4377 &action);
4378 if (err)
4379 return err;
4380 }
278748a9 4381
613f53fe
EC		 4382 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4383 if (err)
4384 return err;
ffec9702 4385
f6dc1264
PB		 4386 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4387 NL_SET_ERR_MSG_MOD(extack,
4388 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4389 return -EOPNOTSUPP;
f6dc1264 4390 }
a0646c88 4391
a54e20b4 4392 out_priv = netdev_priv(out_dev);
1d447a39 4393 rpriv = out_priv->ppriv;
c620b772
AL		 4394 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4395 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4396 esw_attr->out_count++;
ef381359
OS		 4397 } else if (parse_attr->filter_dev != priv->netdev) {
4398 /* All mlx5 devices are called to configure
4399 * high level device filters. Therefore, the
4400 * *attempt* to install a filter on invalid
4401 * eswitch should not trigger an explicit error
4402 */
4403 return -EINVAL;
a54e20b4 4404 } else {
e98bedf5
EB		 4405 NL_SET_ERR_MSG_MOD(extack,
4406 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4407 netdev_warn(priv->netdev,
4408 "devices %s %s not on same switch HW, can't offload forwarding\n",
4409 priv->netdev->name,
4410 out_dev->name);
03a9d11e
OG		 4411 return -EINVAL;
4412 }
73867881
PNA		 4413 }
4414 break;
4415 case FLOW_ACTION_TUNNEL_ENCAP:
4416 info = act->tunnel;
a54e20b4
HHZ		 4417 if (info)
4418 encap = true;
4419 else
4420 return -EOPNOTSUPP;
1482bd3d 4421
73867881
PNA		 4422 break;
4423 case FLOW_ACTION_VLAN_PUSH:
4424 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4425 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4426 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4427 /* Replace vlan pop+push with vlan modify */
4428 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4429 err = add_vlan_rewrite_action(priv,
4430 MLX5_FLOW_NAMESPACE_FDB,
4431 act, parse_attr, hdrs,
4432 &action, extack);
4433 } else {
c620b772 4434 err = parse_tc_vlan_action(priv, act, esw_attr, &action);
76b496b1 4435 }
1482bd3d
JL		 4436 if (err)
4437 return err;
4438
c620b772 4439 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4440 break;
4441 case FLOW_ACTION_VLAN_MANGLE:
4442 err = add_vlan_rewrite_action(priv,
4443 MLX5_FLOW_NAMESPACE_FDB,
4444 act, parse_attr, hdrs,
4445 &action, extack);
4446 if (err)
4447 return err;
4448
c620b772 4449 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4450 break;
4451 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4452 decap = true;
73867881 4453 break;
2fbbc30d 4454 case FLOW_ACTION_GOTO:
c7569097
AL		 4455 err = validate_goto_chain(priv, flow, act, action,
4456 extack);
2fbbc30d
EC		 4457 if (err)
4458 return err;
bf07aa73 4459
e88afe75 4460 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4461 attr->dest_chain = act->chain_index;
73867881 4462 break;
4c3844d9 4463 case FLOW_ACTION_CT:
aedd133d 4464 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4465 if (err)
4466 return err;
4467
4468 flow_flag_set(flow, CT);
4469 break;
73867881 4470 default:
2cc1cb1d
TZ		 4471 NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported");
4472 return -EOPNOTSUPP;
bf07aa73 4473 }
03a9d11e 4474 }
bdd66ac0 4475
0bac1194
EB		 4476 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4477 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4478 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4479 * tag rewrite.
4480 */
4481 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4482 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4483 &action, extack);
4484 if (err)
4485 return err;
4486 }
4487
c500c86b
PNA		 4488 if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits ||
4489 hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) {
84be899f 4490 err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB,
27c11b6b 4491 parse_attr, hdrs, &action, extack);
c500c86b
PNA		 4492 if (err)
4493 return err;
27c11b6b
EB		 4494 /* in case all pedit actions are skipped, remove the MOD_HDR
4495 * flag. we might have set split_count either by pedit or
4496 * pop/push. if there is no pop/push either, reset it too.
4497 */
6ae4a6a5 4498 if (parse_attr->mod_hdr_acts.num_actions == 0) {
27c11b6b 4499 action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
6ae4a6a5 4500 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
27c11b6b
EB		 4501 if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
4502 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
c620b772 4503 esw_attr->split_count = 0;
27c11b6b 4504 }
c500c86b
PNA		 4505 }
4506
1cab1cd7 4507 attr->action = action;
73867881 4508 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4509 return -EOPNOTSUPP;
4510
e88afe75 4511 if (attr->dest_chain) {
0a7fcb78
PB		 4512 if (decap) {
4513 /* It can be supported if we'll create a mapping for
4514 * the tunnel device only (without tunnel), and set
4515 * this tunnel id with this decap flow.
4516 *
4517 * On restore (miss), we'll just set this saved tunnel
4518 * device.
4519 */
4520
4521 NL_SET_ERR_MSG(extack,
4522 "Decap with goto isn't supported");
4523 netdev_warn(priv->netdev,
4524 "Decap with goto isn't supported");
4525 return -EOPNOTSUPP;
4526 }
4527
e88afe75 4528 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
61644c3d
RD		 4529 NL_SET_ERR_MSG_MOD(extack,
4530 "Mirroring goto chain rules isn't supported");
e88afe75
OG		 4531 return -EOPNOTSUPP;
4532 }
4533 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
4534 }
4535
ae2741e2
VB		 4536 if (!(attr->action &
4537 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
61644c3d
RD		 4538 NL_SET_ERR_MSG_MOD(extack,
4539 "Rule must have at least one forward/drop action");
ae2741e2
VB		 4540 return -EOPNOTSUPP;
4541 }
4542
c620b772 4543 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 4544 NL_SET_ERR_MSG_MOD(extack,
4545 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 4546 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
4547 return -EOPNOTSUPP;
4548 }
4549
31c8eba5 4550 return 0;
03a9d11e
OG		 4551}
4552
226f2ca3 4553static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4554{
226f2ca3 4555 unsigned long __flow_flags = 0;
60bd4af8 4556
226f2ca3
VB		 4557 if (flags & MLX5_TC_FLAG(INGRESS))
4558 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4559 if (flags & MLX5_TC_FLAG(EGRESS))
4560 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4561
226f2ca3
VB		 4562 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4563 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4564 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4565 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4566 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4567 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4568
60bd4af8
OG		 4569 *flow_flags = __flow_flags;
4570}
4571
05866c82
OG		 4572static const struct rhashtable_params tc_ht_params = {
4573 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4574 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4575 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4576 .automatic_shrinking = true,
4577};
4578
226f2ca3
VB		 4579static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4580 unsigned long flags)
05866c82 4581{
655dc3d2
OG		 4582 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4583 struct mlx5e_rep_priv *uplink_rpriv;
4584
226f2ca3 4585 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4586 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4587 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4588 } else /* NIC offload */
655dc3d2 4589 return &priv->fs.tc.ht;
05866c82
OG		 4590}
4591
04de7dda
RD		 4592static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4593{
c620b772
AL		 4594 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4595 struct mlx5_flow_attr *attr = flow->attr;
4596 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4597 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4598 bool act_is_encap = !!(attr->action &
4599 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4600 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4601 MLX5_DEVCOM_ESW_OFFLOADS);
4602
10fbb1cd
RD		 4603 if (!esw_paired)
4604 return false;
4605
c620b772
AL		 4606 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4607 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4608 (is_rep_ingress || act_is_encap))
4609 return true;
4610
4611 return false;
04de7dda
RD		 4612}
4613
c620b772
AL		 4614struct mlx5_flow_attr *
4615mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4616{
4617 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4618 sizeof(struct mlx5_esw_flow_attr) :
4619 sizeof(struct mlx5_nic_flow_attr);
4620 struct mlx5_flow_attr *attr;
4621
4622 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4623}
4624
a88780a9
RD		 4625static int
4626mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4627 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4628 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4629 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4630{
17091853 4631 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4632 struct mlx5_flow_attr *attr;
3bc4b7bf 4633 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4634 int err = -ENOMEM;
4635 int out_index;
e3a2b7ed 4636
c620b772 4637 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4638 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4639 if (!parse_attr || !flow)
4640 goto err_free;
c620b772
AL		 4641
4642 flow->flags = flow_flags;
4643 flow->cookie = f->cookie;
4644 flow->priv = priv;
4645
4646 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4647 if (!attr)
e3a2b7ed 4648 goto err_free;
ff7ea04a 4649
c620b772 4650 flow->attr = attr;
e3a2b7ed 4651
5a7e5bcb
VB		 4652 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4653 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4654 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4655 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4656 refcount_set(&flow->refcnt, 1);
95435ad7 4657 init_completion(&flow->init_done);
e3a2b7ed 4658
a88780a9
RD		 4659 *__flow = flow;
4660 *__parse_attr = parse_attr;
4661
4662 return 0;
4663
4664err_free:
4665 kfree(flow);
4666 kvfree(parse_attr);
4667 return err;
4668}
4669
c7569097
AL		 4670static void
4671mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4672 struct mlx5e_tc_flow_parse_attr *parse_attr,
4673 struct flow_cls_offload *f)
4674{
4675 attr->parse_attr = parse_attr;
4676 attr->chain = f->common.chain_index;
4677 attr->prio = f->common.prio;
4678}
4679
988ab9c7 4680static void
c620b772 4681mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4682 struct mlx5e_priv *priv,
4683 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4684 struct flow_cls_offload *f,
988ab9c7
TZ		 4685 struct mlx5_eswitch_rep *in_rep,
4686 struct mlx5_core_dev *in_mdev)
4687{
4688 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4689 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4690
c7569097 4691 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4692
4693 esw_attr->in_rep = in_rep;
4694 esw_attr->in_mdev = in_mdev;
4695
4696 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4697 MLX5_COUNTER_SOURCE_ESWITCH)
4698 esw_attr->counter_dev = in_mdev;
4699 else
4700 esw_attr->counter_dev = priv->mdev;
4701}
4702
71129676 4703static struct mlx5e_tc_flow *
04de7dda 4704__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4705 struct flow_cls_offload *f,
226f2ca3 4706 unsigned long flow_flags,
04de7dda
RD		 4707 struct net_device *filter_dev,
4708 struct mlx5_eswitch_rep *in_rep,
71129676 4709 struct mlx5_core_dev *in_mdev)
a88780a9 4710{
f9e30088 4711 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4712 struct netlink_ext_ack *extack = f->common.extack;
4713 struct mlx5e_tc_flow_parse_attr *parse_attr;
4714 struct mlx5e_tc_flow *flow;
4715 int attr_size, err;
e3a2b7ed 4716
226f2ca3 4717 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4718 attr_size = sizeof(struct mlx5_esw_flow_attr);
4719 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4720 &parse_attr, &flow);
4721 if (err)
4722 goto out;
988ab9c7 4723
d11afc26 4724 parse_attr->filter_dev = filter_dev;
c620b772 4725 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4726 priv, parse_attr,
4727 f, in_rep, in_mdev);
4728
54c177ca
OS		 4729 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4730 f, filter_dev);
d11afc26
OS		 4731 if (err)
4732 goto err_free;
a88780a9 4733
7e36feeb 4734 /* actions validation depends on parsing the ct matches first */
aedd133d 4735 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4736 &flow->attr->ct_attr, extack);
a88780a9
RD		 4737 if (err)
4738 goto err_free;
4739
7e36feeb 4740 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev);
4c3844d9
PB		 4741 if (err)
4742 goto err_free;
4743
7040632d 4744 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4745 complete_all(&flow->init_done);
ef06c9ee
RD		 4746 if (err) {
4747 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4748 goto err_free;
4749
b4a23329 4750 add_unready_flow(flow);
ef06c9ee 4751 }
e3a2b7ed 4752
71129676 4753 return flow;
a88780a9
RD		 4754
4755err_free:
e68e28b4 4756 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4757 mlx5e_flow_put(priv, flow);
a88780a9 4758out:
71129676 4759 return ERR_PTR(err);
a88780a9
RD		 4760}
4761
f9e30088 4762static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4763 struct mlx5e_tc_flow *flow,
226f2ca3 4764 unsigned long flow_flags)
04de7dda
RD		 4765{
4766 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4767 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4768 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4769 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4770 struct mlx5e_tc_flow_parse_attr *parse_attr;
4771 struct mlx5e_rep_priv *peer_urpriv;
4772 struct mlx5e_tc_flow *peer_flow;
4773 struct mlx5_core_dev *in_mdev;
4774 int err = 0;
4775
4776 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4777 if (!peer_esw)
4778 return -ENODEV;
4779
4780 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4781 peer_priv = netdev_priv(peer_urpriv->netdev);
4782
4783 /* in_mdev is assigned of which the packet originated from.
4784 * So packets redirected to uplink use the same mdev of the
4785 * original flow and packets redirected from uplink use the
4786 * peer mdev.
4787 */
c620b772 4788 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4789 in_mdev = peer_priv->mdev;
4790 else
4791 in_mdev = priv->mdev;
4792
c620b772 4793 parse_attr = flow->attr->parse_attr;
95dc1902 4794 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4795 parse_attr->filter_dev,
c620b772 4796 attr->in_rep, in_mdev);
71129676
JG		 4797 if (IS_ERR(peer_flow)) {
4798 err = PTR_ERR(peer_flow);
04de7dda 4799 goto out;
71129676 4800 }
04de7dda
RD		 4801
4802 flow->peer_flow = peer_flow;
226f2ca3 4803 flow_flag_set(flow, DUP);
04de7dda
RD		 4804 mutex_lock(&esw->offloads.peer_mutex);
4805 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4806 mutex_unlock(&esw->offloads.peer_mutex);
4807
4808out:
4809 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4810 return err;
4811}
4812
4813static int
4814mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4815 struct flow_cls_offload *f,
226f2ca3 4816 unsigned long flow_flags,
04de7dda
RD		 4817 struct net_device *filter_dev,
4818 struct mlx5e_tc_flow **__flow)
4819{
4820 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4821 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4822 struct mlx5_core_dev *in_mdev = priv->mdev;
4823 struct mlx5e_tc_flow *flow;
4824 int err;
4825
71129676
JG		 4826 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4827 in_mdev);
4828 if (IS_ERR(flow))
4829 return PTR_ERR(flow);
04de7dda
RD		 4830
4831 if (is_peer_flow_needed(flow)) {
95dc1902 4832 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4833 if (err) {
4834 mlx5e_tc_del_fdb_flow(priv, flow);
4835 goto out;
4836 }
4837 }
4838
4839 *__flow = flow;
4840
4841 return 0;
4842
4843out:
4844 return err;
4845}
4846
a88780a9
RD		 4847static int
4848mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4849 struct flow_cls_offload *f,
226f2ca3 4850 unsigned long flow_flags,
d11afc26 4851 struct net_device *filter_dev,
a88780a9
RD		 4852 struct mlx5e_tc_flow **__flow)
4853{
f9e30088 4854 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4855 struct netlink_ext_ack *extack = f->common.extack;
4856 struct mlx5e_tc_flow_parse_attr *parse_attr;
4857 struct mlx5e_tc_flow *flow;
4858 int attr_size, err;
4859
c7569097
AL		 4860 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4861 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4862 return -EOPNOTSUPP;
4863 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4864 return -EOPNOTSUPP;
c7569097 4865 }
bf07aa73 4866
226f2ca3 4867 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4868 attr_size = sizeof(struct mlx5_nic_flow_attr);
4869 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4870 &parse_attr, &flow);
4871 if (err)
4872 goto out;
4873
d11afc26 4874 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4875 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4876
54c177ca
OS		 4877 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4878 f, filter_dev);
d11afc26
OS		 4879 if (err)
4880 goto err_free;
4881
aedd133d
AL		 4882 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4883 &flow->attr->ct_attr, extack);
4884 if (err)
4885 goto err_free;
4886
73867881 4887 err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack);
a88780a9
RD		 4888 if (err)
4889 goto err_free;
4890
4891 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
4892 if (err)
4893 goto err_free;
4894
226f2ca3 4895 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4896 *__flow = flow;
4897
4898 return 0;
e3a2b7ed 4899
e3a2b7ed 4900err_free:
e68e28b4 4901 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4902 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4903out:
4904 return err;
4905}
4906
4907static int
4908mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4909 struct flow_cls_offload *f,
226f2ca3 4910 unsigned long flags,
d11afc26 4911 struct net_device *filter_dev,
a88780a9
RD		 4912 struct mlx5e_tc_flow **flow)
4913{
4914 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4915 unsigned long flow_flags;
a88780a9
RD		 4916 int err;
4917
4918 get_flags(flags, &flow_flags);
4919
bf07aa73
PB		 4920 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4921 return -EOPNOTSUPP;
4922
f6455de0 4923 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4924 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4925 filter_dev, flow);
a88780a9 4926 else
d11afc26
OS		 4927 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4928 filter_dev, flow);
a88780a9
RD		 4929
4930 return err;
4931}
4932
553f9328
VP		 4933static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4934 struct mlx5e_rep_priv *rpriv)
4935{
4936 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4937 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4938 * function is called from NIC mode.
553f9328 4939 */
2fb15e72 4940 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4941}
4942
71d82d2a 4943int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4944 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4945{
4946 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4947 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4948 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4949 struct mlx5e_tc_flow *flow;
4950 int err = 0;
4951
c5d326b2
VB		 4952 rcu_read_lock();
4953 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4954 if (flow) {
553f9328
VP		 4955 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4956 * just return 0.
4957 */
4958 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4959 goto rcu_unlock;
553f9328 4960
a88780a9
RD		 4961 NL_SET_ERR_MSG_MOD(extack,
4962 "flow cookie already exists, ignoring");
4963 netdev_warn_once(priv->netdev,
4964 "flow cookie %lx already exists, ignoring\n",
4965 f->cookie);
0e1c1a2f 4966 err = -EEXIST;
c1aea9e1 4967 goto rcu_unlock;
a88780a9 4968 }
c1aea9e1
VB		 4969rcu_unlock:
4970 rcu_read_unlock();
4971 if (flow)
4972 goto out;
a88780a9 4973
7a978759 4974 trace_mlx5e_configure_flower(f);
d11afc26 4975 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4976 if (err)
4977 goto out;
4978
553f9328
VP		 4979 /* Flow rule offloaded to non-uplink representor sharing tc block,
4980 * set the flow's owner dev.
4981 */
4982 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4983 flow->orig_dev = dev;
4984
c5d326b2 4985 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4986 if (err)
4987 goto err_free;
4988
4989 return 0;
4990
4991err_free:
5a7e5bcb 4992 mlx5e_flow_put(priv, flow);
a88780a9 4993out:
e3a2b7ed
AV		 4994 return err;
4995}
4996
8f8ae895
OG		 4997static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4998{
226f2ca3
VB		 4999 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
5000 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 5001
226f2ca3
VB		 5002 return flow_flag_test(flow, INGRESS) == dir_ingress &&
5003 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 5004}
5005
71d82d2a 5006int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 5007 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 5008{
d9ee0491 5009 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 5010 struct mlx5e_tc_flow *flow;
c5d326b2 5011 int err;
e3a2b7ed 5012
c5d326b2 5013 rcu_read_lock();
ab818362 5014 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 5015 if (!flow || !same_flow_direction(flow, flags)) {
5016 err = -EINVAL;
5017 goto errout;
5018 }
e3a2b7ed 5019
c5d326b2
VB		 5020 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
5021 * set.
5022 */
5023 if (flow_flag_test_and_set(flow, DELETED)) {
5024 err = -EINVAL;
5025 goto errout;
5026 }
05866c82 5027 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 5028 rcu_read_unlock();
e3a2b7ed 5029
7a978759 5030 trace_mlx5e_delete_flower(f);
5a7e5bcb 5031 mlx5e_flow_put(priv, flow);
e3a2b7ed
AV		 5032
5033 return 0;
c5d326b2
VB		 5034
5035errout:
5036 rcu_read_unlock();
5037 return err;
e3a2b7ed
AV		 5038}
5039
71d82d2a 5040int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 5041 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 5042{
04de7dda 5043 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 5044 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 5045 struct mlx5_eswitch *peer_esw;
aad7e08d 5046 struct mlx5e_tc_flow *flow;
aad7e08d 5047 struct mlx5_fc *counter;
316d5f72
RD		 5048 u64 lastuse = 0;
5049 u64 packets = 0;
5050 u64 bytes = 0;
5a7e5bcb 5051 int err = 0;
aad7e08d 5052
c5d326b2
VB		 5053 rcu_read_lock();
5054 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
5055 tc_ht_params));
5056 rcu_read_unlock();
5a7e5bcb
VB		 5057 if (IS_ERR(flow))
5058 return PTR_ERR(flow);
5059
5060 if (!same_flow_direction(flow, flags)) {
5061 err = -EINVAL;
5062 goto errout;
5063 }
aad7e08d 5064
4c3844d9 5065 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 5066 counter = mlx5e_tc_get_counter(flow);
5067 if (!counter)
5a7e5bcb 5068 goto errout;
aad7e08d 5069
316d5f72
RD		 5070 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
5071 }
aad7e08d 5072
316d5f72
RD		 5073 /* Under multipath it's possible for one rule to be currently
5074 * un-offloaded while the other rule is offloaded.
5075 */
04de7dda
RD		 5076 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
5077 if (!peer_esw)
5078 goto out;
5079
226f2ca3
VB		 5080 if (flow_flag_test(flow, DUP) &&
5081 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 5082 u64 bytes2;
5083 u64 packets2;
5084 u64 lastuse2;
5085
5086 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 5087 if (!counter)
5088 goto no_peer_counter;
04de7dda
RD		 5089 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
5090
5091 bytes += bytes2;
5092 packets += packets2;
5093 lastuse = max_t(u64, lastuse, lastuse2);
5094 }
5095
316d5f72 5096no_peer_counter:
04de7dda 5097 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 5098out:
4b61d3e8 5099 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 5100 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 5101 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 5102errout:
5103 mlx5e_flow_put(priv, flow);
5104 return err;
aad7e08d
AV		 5105}
5106
1fe3e316 5107static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 5108 struct netlink_ext_ack *extack)
5109{
5110 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5111 struct mlx5_eswitch *esw;
1fe3e316 5112 u32 rate_mbps = 0;
fcb64c0f 5113 u16 vport_num;
fcb64c0f
EC		 5114 int err;
5115
e401a184
EC		 5116 vport_num = rpriv->rep->vport;
5117 if (vport_num >= MLX5_VPORT_ECPF) {
5118 NL_SET_ERR_MSG_MOD(extack,
5119 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5120 return -EOPNOTSUPP;
5121 }
5122
fcb64c0f
EC		 5123 esw = priv->mdev->priv.eswitch;
5124 /* rate is given in bytes/sec.
5125 * First convert to bits/sec and then round to the nearest mbit/secs.
5126 * mbit means million bits.
5127 * Moreover, if rate is non zero we choose to configure to a minimum of
5128 * 1 mbit/sec.
5129 */
1fe3e316
PP		 5130 if (rate) {
5131 rate = (rate * BITS_PER_BYTE) + 500000;
5132 rate_mbps = max_t(u32, do_div(rate, 1000000), 1);
5133 }
5134
fcb64c0f
EC		 5135 err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps);
5136 if (err)
5137 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5138
5139 return err;
5140}
5141
5142static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5143 struct flow_action *flow_action,
5144 struct netlink_ext_ack *extack)
5145{
5146 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5147 const struct flow_action_entry *act;
5148 int err;
5149 int i;
5150
5151 if (!flow_action_has_entries(flow_action)) {
5152 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5153 return -EINVAL;
5154 }
5155
5156 if (!flow_offload_has_one_action(flow_action)) {
5157 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5158 return -EOPNOTSUPP;
5159 }
5160
53eca1f3 5161 if (!flow_action_basic_hw_stats_check(flow_action, extack))
319a1d19
JP		 5162 return -EOPNOTSUPP;
5163
fcb64c0f
EC		 5164 flow_action_for_each(i, act, flow_action) {
5165 switch (act->id) {
5166 case FLOW_ACTION_POLICE:
5167 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5168 if (err)
5169 return err;
5170
5171 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
5172 break;
5173 default:
5174 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5175 return -EOPNOTSUPP;
5176 }
5177 }
5178
5179 return 0;
5180}
5181
5182int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5183 struct tc_cls_matchall_offload *ma)
5184{
b5f814cc 5185 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 5186 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 5187
b5f814cc
EC		 5188 if (!mlx5_esw_qos_enabled(esw)) {
5189 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
5190 return -EOPNOTSUPP;
5191 }
5192
7b83355f 5193 if (ma->common.prio != 1) {
fcb64c0f
EC		 5194 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5195 return -EINVAL;
5196 }
5197
5198 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5199}
5200
5201int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5202 struct tc_cls_matchall_offload *ma)
5203{
5204 struct netlink_ext_ack *extack = ma->common.extack;
5205
5206 return apply_police_params(priv, 0, extack);
5207}
5208
5209void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
5210 struct tc_cls_matchall_offload *ma)
5211{
5212 struct mlx5e_rep_priv *rpriv = priv->ppriv;
5213 struct rtnl_link_stats64 cur_stats;
5214 u64 dbytes;
5215 u64 dpkts;
5216
5217 cur_stats = priv->stats.vf_vport;
5218 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
5219 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
5220 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 5221 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 5222 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 5223}
5224
4d8fcf21
AH		 5225static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5226 struct mlx5e_priv *peer_priv)
5227{
5228 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 5229 struct mlx5e_hairpin_entry *hpe, *tmp;
5230 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 5231 u16 peer_vhca_id;
5232 int bkt;
5233
5234 if (!same_hw_devs(priv, peer_priv))
5235 return;
5236
5237 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5238
b32accda 5239 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 5240 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
5241 if (refcount_inc_not_zero(&hpe->refcnt))
5242 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5243 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5244
5245 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5246 wait_for_completion(&hpe->res_ready);
5247 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
4d8fcf21 5248 hpe->hp->pair->peer_gone = true;
db76ca24
VB		 5249
5250 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 5251 }
5252}
5253
5254static int mlx5e_tc_netdev_event(struct notifier_block *this,
5255 unsigned long event, void *ptr)
5256{
5257 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5258 struct mlx5e_flow_steering *fs;
5259 struct mlx5e_priv *peer_priv;
5260 struct mlx5e_tc_table *tc;
5261 struct mlx5e_priv *priv;
5262
5263 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5264 event != NETDEV_UNREGISTER ||
5265 ndev->reg_state == NETREG_REGISTERED)
5266 return NOTIFY_DONE;
5267
5268 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5269 fs = container_of(tc, struct mlx5e_flow_steering, tc);
5270 priv = container_of(fs, struct mlx5e_priv, fs);
5271 peer_priv = netdev_priv(ndev);
5272 if (priv == peer_priv ||
5273 !(priv->netdev->features & NETIF_F_HW_TC))
5274 return NOTIFY_DONE;
5275
5276 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5277
5278 return NOTIFY_DONE;
5279}
5280
6a064674
AL		 5281static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
5282{
5283 int tc_grp_size, tc_tbl_size;
5284 u32 max_flow_counter;
5285
5286 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
5287 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
5288
5289 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
5290
5291 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
5292 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
5293
5294 return tc_tbl_size;
5295}
5296
655dc3d2 5297int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 5298{
acff797c 5299 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674
AL		 5300 struct mlx5_core_dev *dev = priv->mdev;
5301 struct mlx5_chains_attr attr = {};
4d8fcf21 5302 int err;
e8f887ac 5303
b2fdf3d0 5304 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 5305 mutex_init(&tc->t_lock);
b32accda 5306 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 5307 hash_init(tc->hairpin_tbl);
11c9c548 5308
4d8fcf21
AH		 5309 err = rhashtable_init(&tc->ht, &tc_ht_params);
5310 if (err)
5311 return err;
5312
9ba33339
RD		 5313 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5314
c7569097
AL		 5315 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
5316 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5317 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5318 attr.max_restore_tag = MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5319 }
6a064674
AL		 5320 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5321 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
5322 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5323 attr.default_ft = priv->fs.vlan.ft.t;
5324
5325 tc->chains = mlx5_chains_create(dev, &attr);
5326 if (IS_ERR(tc->chains)) {
5327 err = PTR_ERR(tc->chains);
5328 goto err_chains;
5329 }
5330
aedd133d
AL		 5331 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
5332 MLX5_FLOW_NAMESPACE_KERNEL);
68ec32da
WH		 5333 if (IS_ERR(tc->ct)) {
5334 err = PTR_ERR(tc->ct);
aedd133d 5335 goto err_ct;
68ec32da 5336 }
aedd133d 5337
4d8fcf21 5338 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 5339 err = register_netdevice_notifier_dev_net(priv->netdev,
5340 &tc->netdevice_nb,
5341 &tc->netdevice_nn);
5342 if (err) {
4d8fcf21
AH		 5343 tc->netdevice_nb.notifier_call = NULL;
5344 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5345 goto err_reg;
4d8fcf21
AH		 5346 }
5347
6a064674
AL		 5348 return 0;
5349
5350err_reg:
aedd133d
AL		 5351 mlx5_tc_ct_clean(tc->ct);
5352err_ct:
6a064674
AL		 5353 mlx5_chains_destroy(tc->chains);
5354err_chains:
5355 rhashtable_destroy(&tc->ht);
4d8fcf21 5356 return err;
e8f887ac
AV		 5357}
5358
5359static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5360{
5361 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5362 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5363
961e8979 5364 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5365 kfree(flow);
5366}
5367
655dc3d2 5368void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5369{
acff797c 5370 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5371
4d8fcf21 5372 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5373 unregister_netdevice_notifier_dev_net(priv->netdev,
5374 &tc->netdevice_nb,
5375 &tc->netdevice_nn);
4d8fcf21 5376
b2fdf3d0 5377 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5378 mutex_destroy(&tc->hairpin_tbl_lock);
5379
6a064674 5380 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5381
acff797c 5382 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5383 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5384 tc->t = NULL;
e8f887ac 5385 }
b6fac0b4 5386 mutex_destroy(&tc->t_lock);
6a064674 5387
aedd133d 5388 mlx5_tc_ct_clean(tc->ct);
6a064674 5389 mlx5_chains_destroy(tc->chains);
e8f887ac 5390}
655dc3d2
OG		 5391
5392int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5393{
d7a42ad0 5394 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5395 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5396 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5397 struct mapping_ctx *mapping;
aedd133d
AL		 5398 struct mlx5_eswitch *esw;
5399 struct mlx5e_priv *priv;
5400 int err = 0;
0a7fcb78
PB		 5401
5402 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5403 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5404 priv = netdev_priv(rpriv->netdev);
5405 esw = priv->mdev->priv.eswitch;
0a7fcb78 5406
aedd133d
AL		 5407 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5408 esw_chains(esw),
5409 &esw->offloads.mod_hdr,
5410 MLX5_FLOW_NAMESPACE_FDB);
5411 if (IS_ERR(uplink_priv->ct_priv))
4c3844d9
PB		 5412 goto err_ct;
5413
0a7fcb78
PB		 5414 mapping = mapping_create(sizeof(struct tunnel_match_key),
5415 TUNNEL_INFO_BITS_MASK, true);
5416 if (IS_ERR(mapping)) {
5417 err = PTR_ERR(mapping);
5418 goto err_tun_mapping;
5419 }
5420 uplink_priv->tunnel_mapping = mapping;
5421
5422 mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true);
5423 if (IS_ERR(mapping)) {
5424 err = PTR_ERR(mapping);
5425 goto err_enc_opts_mapping;
5426 }
5427 uplink_priv->tunnel_enc_opts_mapping = mapping;
5428
5429 err = rhashtable_init(tc_ht, &tc_ht_params);
5430 if (err)
5431 goto err_ht_init;
5432
9ba33339
RD		 5433 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5434
0a7fcb78
PB		 5435 return err;
5436
5437err_ht_init:
5438 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5439err_enc_opts_mapping:
5440 mapping_destroy(uplink_priv->tunnel_mapping);
5441err_tun_mapping:
aedd133d 5442 mlx5_tc_ct_clean(uplink_priv->ct_priv);
4c3844d9 5443err_ct:
0a7fcb78
PB		 5444 netdev_warn(priv->netdev,
5445 "Failed to initialize tc (eswitch), err: %d", err);
5446 return err;
655dc3d2
OG		 5447}
5448
5449void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5450{
0a7fcb78
PB		 5451 struct mlx5_rep_uplink_priv *uplink_priv;
5452
655dc3d2 5453 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
0a7fcb78
PB		 5454
5455 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5456
0a7fcb78
PB		 5457 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5458 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5459
aedd133d 5460 mlx5_tc_ct_clean(uplink_priv->ct_priv);
655dc3d2 5461}
01252a27 5462
226f2ca3 5463int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5464{
d9ee0491 5465 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5466
5467 return atomic_read(&tc_ht->nelems);
5468}
04de7dda
RD		 5469
5470void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5471{
5472 struct mlx5e_tc_flow *flow, *tmp;
5473
5474 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5475 __mlx5e_tc_del_fdb_peer_flow(flow);
5476}
b4a23329
RD		 5477
5478void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5479{
5480 struct mlx5_rep_uplink_priv *rpriv =
5481 container_of(work, struct mlx5_rep_uplink_priv,
5482 reoffload_flows_work);
5483 struct mlx5e_tc_flow *flow, *tmp;
5484
ad86755b 5485 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5486 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5487 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5488 unready_flow_del(flow);
b4a23329 5489 }
ad86755b 5490 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5491}
e2394a61
VB		 5492
5493static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5494 struct flow_cls_offload *cls_flower,
5495 unsigned long flags)
5496{
5497 switch (cls_flower->command) {
5498 case FLOW_CLS_REPLACE:
5499 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5500 flags);
5501 case FLOW_CLS_DESTROY:
5502 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5503 flags);
5504 case FLOW_CLS_STATS:
5505 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5506 flags);
5507 default:
5508 return -EOPNOTSUPP;
5509 }
5510}
5511
5512int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5513 void *cb_priv)
5514{
5515 unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD);
5516 struct mlx5e_priv *priv = cb_priv;
5517
5518 switch (type) {
5519 case TC_SETUP_CLSFLOWER:
5520 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5521 default:
5522 return -EOPNOTSUPP;
5523 }
5524}
c7569097
AL		 5525
5526bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5527 struct sk_buff *skb)
5528{
5529#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5530 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5531 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5532 struct mlx5e_tc_table *tc = &priv->fs.tc;
c7569097
AL		 5533 struct tc_skb_ext *tc_skb_ext;
5534 int err;
5535
5536 reg_b = be32_to_cpu(cqe->ft_metadata);
5537
5538 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5539
5540 err = mlx5_get_chain_for_tag(nic_chains(priv), chain_tag, &chain);
5541 if (err) {
5542 netdev_dbg(priv->netdev,
5543 "Couldn't find chain for chain tag: %d, err: %d\n",
5544 chain_tag, err);
5545 return false;
5546 }
5547
5548 if (chain) {
5549 tc_skb_ext = skb_ext_add(skb, TC_SKB_EXT);
5550 if (WARN_ON(!tc_skb_ext))
5551 return false;
5552
5553 tc_skb_ext->chain = chain;
aedd133d
AL		 5554
5555 zone_restore_id = (reg_b >> REG_MAPPING_SHIFT(NIC_ZONE_RESTORE_TO_REG)) &
5556 ZONE_RESTORE_MAX;
5557
5558 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5559 zone_restore_id))
5560 return false;
c7569097
AL		 5561 }
5562#endif /* CONFIG_NET_TC_SKB_EXT */
5563
5564 return true;
5565}
Linux 6.x block layer and io_uring tree(s)