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e8f887ac AV |
1 | /* |
2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e3a2b7ed | 33 | #include <net/flow_dissector.h> |
e2394a61 | 34 | #include <net/flow_offload.h> |
3f7d0eb4 | 35 | #include <net/sch_generic.h> |
e3a2b7ed AV |
36 | #include <net/pkt_cls.h> |
37 | #include <net/tc_act/tc_gact.h> | |
12185a9f | 38 | #include <net/tc_act/tc_skbedit.h> |
e8f887ac AV |
39 | #include <linux/mlx5/fs.h> |
40 | #include <linux/mlx5/device.h> | |
41 | #include <linux/rhashtable.h> | |
5a7e5bcb | 42 | #include <linux/refcount.h> |
db76ca24 | 43 | #include <linux/completion.h> |
03a9d11e | 44 | #include <net/tc_act/tc_mirred.h> |
776b12b6 | 45 | #include <net/tc_act/tc_vlan.h> |
bbd00f7e | 46 | #include <net/tc_act/tc_tunnel_key.h> |
d79b6df6 | 47 | #include <net/tc_act/tc_pedit.h> |
26c02749 | 48 | #include <net/tc_act/tc_csum.h> |
14e6b038 | 49 | #include <net/tc_act/tc_mpls.h> |
f6dfb4c3 | 50 | #include <net/arp.h> |
3616d08b | 51 | #include <net/ipv6_stubs.h> |
f828ca6a | 52 | #include <net/bareudp.h> |
d34eb2fc | 53 | #include <net/bonding.h> |
e8f887ac | 54 | #include "en.h" |
1d447a39 | 55 | #include "en_rep.h" |
768c3667 | 56 | #include "en/rep/tc.h" |
e2394a61 | 57 | #include "en/rep/neigh.h" |
232c0013 | 58 | #include "en_tc.h" |
03a9d11e | 59 | #include "eswitch.h" |
49964352 | 60 | #include "esw/chains.h" |
3f6d08d1 | 61 | #include "fs_core.h" |
2c81bfd5 | 62 | #include "en/port.h" |
101f4de9 | 63 | #include "en/tc_tun.h" |
0a7fcb78 | 64 | #include "en/mapping.h" |
4c3844d9 | 65 | #include "en/tc_ct.h" |
04de7dda | 66 | #include "lib/devcom.h" |
9272e3df | 67 | #include "lib/geneve.h" |
7a978759 | 68 | #include "diag/en_tc_tracepoint.h" |
e8f887ac | 69 | |
d65dbedf | 70 | #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto) |
0a7fcb78 | 71 | |
3bc4b7bf OG |
72 | struct mlx5_nic_flow_attr { |
73 | u32 action; | |
74 | u32 flow_tag; | |
2b688ea5 | 75 | struct mlx5_modify_hdr *modify_hdr; |
5c65c564 | 76 | u32 hairpin_tirn; |
38aa51c1 | 77 | u8 match_level; |
3f6d08d1 | 78 | struct mlx5_flow_table *hairpin_ft; |
b8aee822 | 79 | struct mlx5_fc *counter; |
3bc4b7bf OG |
80 | }; |
81 | ||
226f2ca3 | 82 | #define MLX5E_TC_FLOW_BASE (MLX5E_TC_FLAG_LAST_EXPORTED_BIT + 1) |
60bd4af8 | 83 | |
65ba8fb7 | 84 | enum { |
226f2ca3 VB |
85 | MLX5E_TC_FLOW_FLAG_INGRESS = MLX5E_TC_FLAG_INGRESS_BIT, |
86 | MLX5E_TC_FLOW_FLAG_EGRESS = MLX5E_TC_FLAG_EGRESS_BIT, | |
87 | MLX5E_TC_FLOW_FLAG_ESWITCH = MLX5E_TC_FLAG_ESW_OFFLOAD_BIT, | |
84179981 | 88 | MLX5E_TC_FLOW_FLAG_FT = MLX5E_TC_FLAG_FT_OFFLOAD_BIT, |
226f2ca3 VB |
89 | MLX5E_TC_FLOW_FLAG_NIC = MLX5E_TC_FLAG_NIC_OFFLOAD_BIT, |
90 | MLX5E_TC_FLOW_FLAG_OFFLOADED = MLX5E_TC_FLOW_BASE, | |
91 | MLX5E_TC_FLOW_FLAG_HAIRPIN = MLX5E_TC_FLOW_BASE + 1, | |
92 | MLX5E_TC_FLOW_FLAG_HAIRPIN_RSS = MLX5E_TC_FLOW_BASE + 2, | |
93 | MLX5E_TC_FLOW_FLAG_SLOW = MLX5E_TC_FLOW_BASE + 3, | |
94 | MLX5E_TC_FLOW_FLAG_DUP = MLX5E_TC_FLOW_BASE + 4, | |
95 | MLX5E_TC_FLOW_FLAG_NOT_READY = MLX5E_TC_FLOW_BASE + 5, | |
c5d326b2 | 96 | MLX5E_TC_FLOW_FLAG_DELETED = MLX5E_TC_FLOW_BASE + 6, |
4c3844d9 | 97 | MLX5E_TC_FLOW_FLAG_CT = MLX5E_TC_FLOW_BASE + 7, |
14e6b038 | 98 | MLX5E_TC_FLOW_FLAG_L3_TO_L2_DECAP = MLX5E_TC_FLOW_BASE + 8, |
65ba8fb7 OG |
99 | }; |
100 | ||
e4ad91f2 CM |
101 | #define MLX5E_TC_MAX_SPLITS 1 |
102 | ||
79baaec7 EB |
103 | /* Helper struct for accessing a struct containing list_head array. |
104 | * Containing struct | |
105 | * |- Helper array | |
106 | * [0] Helper item 0 | |
107 | * |- list_head item 0 | |
108 | * |- index (0) | |
109 | * [1] Helper item 1 | |
110 | * |- list_head item 1 | |
111 | * |- index (1) | |
112 | * To access the containing struct from one of the list_head items: | |
113 | * 1. Get the helper item from the list_head item using | |
114 | * helper item = | |
115 | * container_of(list_head item, helper struct type, list_head field) | |
116 | * 2. Get the contining struct from the helper item and its index in the array: | |
117 | * containing struct = | |
118 | * container_of(helper item, containing struct type, helper field[index]) | |
119 | */ | |
120 | struct encap_flow_item { | |
948993f2 | 121 | struct mlx5e_encap_entry *e; /* attached encap instance */ |
79baaec7 EB |
122 | struct list_head list; |
123 | int index; | |
124 | }; | |
125 | ||
e8f887ac AV |
126 | struct mlx5e_tc_flow { |
127 | struct rhash_head node; | |
655dc3d2 | 128 | struct mlx5e_priv *priv; |
e8f887ac | 129 | u64 cookie; |
226f2ca3 | 130 | unsigned long flags; |
e4ad91f2 | 131 | struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1]; |
14e6b038 EC |
132 | |
133 | /* flows sharing the same reformat object - currently mpls decap */ | |
134 | struct list_head l3_to_l2_reformat; | |
135 | struct mlx5e_decap_entry *decap_reformat; | |
136 | ||
79baaec7 EB |
137 | /* Flow can be associated with multiple encap IDs. |
138 | * The number of encaps is bounded by the number of supported | |
139 | * destinations. | |
140 | */ | |
141 | struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS]; | |
04de7dda | 142 | struct mlx5e_tc_flow *peer_flow; |
dd58edc3 | 143 | struct mlx5e_mod_hdr_entry *mh; /* attached mod header instance */ |
11c9c548 | 144 | struct list_head mod_hdr; /* flows sharing the same mod hdr ID */ |
e4f9abbd | 145 | struct mlx5e_hairpin_entry *hpe; /* attached hairpin instance */ |
5c65c564 | 146 | struct list_head hairpin; /* flows sharing the same hairpin */ |
04de7dda | 147 | struct list_head peer; /* flows with peer flow */ |
b4a23329 | 148 | struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */ |
553f9328 | 149 | struct net_device *orig_dev; /* netdev adding flow first */ |
2a1f1768 | 150 | int tmp_efi_index; |
6a06c2f7 | 151 | struct list_head tmp_list; /* temporary flow list used by neigh update */ |
5a7e5bcb | 152 | refcount_t refcnt; |
c5d326b2 | 153 | struct rcu_head rcu_head; |
95435ad7 | 154 | struct completion init_done; |
0a7fcb78 PB |
155 | int tunnel_id; /* the mapped tunnel id of this flow */ |
156 | ||
3bc4b7bf OG |
157 | union { |
158 | struct mlx5_esw_flow_attr esw_attr[0]; | |
159 | struct mlx5_nic_flow_attr nic_attr[0]; | |
160 | }; | |
e8f887ac AV |
161 | }; |
162 | ||
17091853 | 163 | struct mlx5e_tc_flow_parse_attr { |
1f6da306 | 164 | const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS]; |
d11afc26 | 165 | struct net_device *filter_dev; |
17091853 | 166 | struct mlx5_flow_spec spec; |
6ae4a6a5 | 167 | struct mlx5e_tc_mod_hdr_acts mod_hdr_acts; |
98b66cb1 | 168 | int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS]; |
14e6b038 | 169 | struct ethhdr eth; |
17091853 OG |
170 | }; |
171 | ||
acff797c | 172 | #define MLX5E_TC_TABLE_NUM_GROUPS 4 |
b3a433de | 173 | #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16) |
e8f887ac | 174 | |
8f1e0b97 PB |
175 | struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = { |
176 | [CHAIN_TO_REG] = { | |
177 | .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0, | |
178 | .moffset = 0, | |
179 | .mlen = 2, | |
180 | }, | |
0a7fcb78 PB |
181 | [TUNNEL_TO_REG] = { |
182 | .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1, | |
183 | .moffset = 3, | |
184 | .mlen = 1, | |
185 | .soffset = MLX5_BYTE_OFF(fte_match_param, | |
186 | misc_parameters_2.metadata_reg_c_1), | |
187 | }, | |
4c3844d9 PB |
188 | [ZONE_TO_REG] = zone_to_reg_ct, |
189 | [CTSTATE_TO_REG] = ctstate_to_reg_ct, | |
190 | [MARK_TO_REG] = mark_to_reg_ct, | |
191 | [LABELS_TO_REG] = labels_to_reg_ct, | |
192 | [FTEID_TO_REG] = fteid_to_reg_ct, | |
5c6b9460 | 193 | [TUPLEID_TO_REG] = tupleid_to_reg_ct, |
8f1e0b97 PB |
194 | }; |
195 | ||
0a7fcb78 PB |
196 | static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow); |
197 | ||
198 | void | |
199 | mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec, | |
200 | enum mlx5e_tc_attr_to_reg type, | |
201 | u32 data, | |
202 | u32 mask) | |
203 | { | |
204 | int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset; | |
205 | int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen; | |
206 | void *headers_c = spec->match_criteria; | |
207 | void *headers_v = spec->match_value; | |
208 | void *fmask, *fval; | |
209 | ||
210 | fmask = headers_c + soffset; | |
211 | fval = headers_v + soffset; | |
212 | ||
58ff18e1 SM |
213 | mask = (__force u32)(cpu_to_be32(mask)) >> (32 - (match_len * 8)); |
214 | data = (__force u32)(cpu_to_be32(data)) >> (32 - (match_len * 8)); | |
0a7fcb78 PB |
215 | |
216 | memcpy(fmask, &mask, match_len); | |
217 | memcpy(fval, &data, match_len); | |
218 | ||
219 | spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2; | |
220 | } | |
221 | ||
222 | int | |
223 | mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev, | |
224 | struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts, | |
225 | enum mlx5e_tc_attr_to_reg type, | |
226 | u32 data) | |
227 | { | |
228 | int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset; | |
229 | int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield; | |
230 | int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen; | |
231 | char *modact; | |
232 | int err; | |
233 | ||
234 | err = alloc_mod_hdr_actions(mdev, MLX5_FLOW_NAMESPACE_FDB, | |
235 | mod_hdr_acts); | |
236 | if (err) | |
237 | return err; | |
238 | ||
239 | modact = mod_hdr_acts->actions + | |
240 | (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ); | |
241 | ||
242 | /* Firmware has 5bit length field and 0 means 32bits */ | |
243 | if (mlen == 4) | |
244 | mlen = 0; | |
245 | ||
246 | MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET); | |
247 | MLX5_SET(set_action_in, modact, field, mfield); | |
248 | MLX5_SET(set_action_in, modact, offset, moffset * 8); | |
249 | MLX5_SET(set_action_in, modact, length, mlen * 8); | |
250 | MLX5_SET(set_action_in, modact, data, data); | |
251 | mod_hdr_acts->num_actions++; | |
252 | ||
253 | return 0; | |
254 | } | |
255 | ||
77ab67b7 OG |
256 | struct mlx5e_hairpin { |
257 | struct mlx5_hairpin *pair; | |
258 | ||
259 | struct mlx5_core_dev *func_mdev; | |
3f6d08d1 | 260 | struct mlx5e_priv *func_priv; |
77ab67b7 OG |
261 | u32 tdn; |
262 | u32 tirn; | |
3f6d08d1 OG |
263 | |
264 | int num_channels; | |
265 | struct mlx5e_rqt indir_rqt; | |
266 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
267 | struct mlx5e_ttc_table ttc; | |
77ab67b7 OG |
268 | }; |
269 | ||
5c65c564 OG |
270 | struct mlx5e_hairpin_entry { |
271 | /* a node of a hash table which keeps all the hairpin entries */ | |
272 | struct hlist_node hairpin_hlist; | |
273 | ||
73edca73 VB |
274 | /* protects flows list */ |
275 | spinlock_t flows_lock; | |
5c65c564 OG |
276 | /* flows sharing the same hairpin */ |
277 | struct list_head flows; | |
db76ca24 VB |
278 | /* hpe's that were not fully initialized when dead peer update event |
279 | * function traversed them. | |
280 | */ | |
281 | struct list_head dead_peer_wait_list; | |
5c65c564 | 282 | |
d8822868 | 283 | u16 peer_vhca_id; |
106be53b | 284 | u8 prio; |
5c65c564 | 285 | struct mlx5e_hairpin *hp; |
e4f9abbd | 286 | refcount_t refcnt; |
db76ca24 | 287 | struct completion res_ready; |
5c65c564 OG |
288 | }; |
289 | ||
11c9c548 OG |
290 | struct mod_hdr_key { |
291 | int num_actions; | |
292 | void *actions; | |
293 | }; | |
294 | ||
295 | struct mlx5e_mod_hdr_entry { | |
296 | /* a node of a hash table which keeps all the mod_hdr entries */ | |
297 | struct hlist_node mod_hdr_hlist; | |
298 | ||
83a52f0d VB |
299 | /* protects flows list */ |
300 | spinlock_t flows_lock; | |
11c9c548 OG |
301 | /* flows sharing the same mod_hdr entry */ |
302 | struct list_head flows; | |
303 | ||
304 | struct mod_hdr_key key; | |
305 | ||
2b688ea5 | 306 | struct mlx5_modify_hdr *modify_hdr; |
dd58edc3 VB |
307 | |
308 | refcount_t refcnt; | |
a734d007 VB |
309 | struct completion res_ready; |
310 | int compl_result; | |
11c9c548 OG |
311 | }; |
312 | ||
5a7e5bcb VB |
313 | static void mlx5e_tc_del_flow(struct mlx5e_priv *priv, |
314 | struct mlx5e_tc_flow *flow); | |
315 | ||
316 | static struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow) | |
317 | { | |
318 | if (!flow || !refcount_inc_not_zero(&flow->refcnt)) | |
319 | return ERR_PTR(-EINVAL); | |
320 | return flow; | |
321 | } | |
322 | ||
323 | static void mlx5e_flow_put(struct mlx5e_priv *priv, | |
324 | struct mlx5e_tc_flow *flow) | |
325 | { | |
326 | if (refcount_dec_and_test(&flow->refcnt)) { | |
327 | mlx5e_tc_del_flow(priv, flow); | |
c5d326b2 | 328 | kfree_rcu(flow, rcu_head); |
5a7e5bcb VB |
329 | } |
330 | } | |
331 | ||
226f2ca3 VB |
332 | static void __flow_flag_set(struct mlx5e_tc_flow *flow, unsigned long flag) |
333 | { | |
334 | /* Complete all memory stores before setting bit. */ | |
335 | smp_mb__before_atomic(); | |
336 | set_bit(flag, &flow->flags); | |
337 | } | |
338 | ||
339 | #define flow_flag_set(flow, flag) __flow_flag_set(flow, MLX5E_TC_FLOW_FLAG_##flag) | |
340 | ||
c5d326b2 VB |
341 | static bool __flow_flag_test_and_set(struct mlx5e_tc_flow *flow, |
342 | unsigned long flag) | |
343 | { | |
344 | /* test_and_set_bit() provides all necessary barriers */ | |
345 | return test_and_set_bit(flag, &flow->flags); | |
346 | } | |
347 | ||
348 | #define flow_flag_test_and_set(flow, flag) \ | |
349 | __flow_flag_test_and_set(flow, \ | |
350 | MLX5E_TC_FLOW_FLAG_##flag) | |
351 | ||
226f2ca3 VB |
352 | static void __flow_flag_clear(struct mlx5e_tc_flow *flow, unsigned long flag) |
353 | { | |
354 | /* Complete all memory stores before clearing bit. */ | |
355 | smp_mb__before_atomic(); | |
356 | clear_bit(flag, &flow->flags); | |
357 | } | |
358 | ||
359 | #define flow_flag_clear(flow, flag) __flow_flag_clear(flow, \ | |
360 | MLX5E_TC_FLOW_FLAG_##flag) | |
361 | ||
362 | static bool __flow_flag_test(struct mlx5e_tc_flow *flow, unsigned long flag) | |
363 | { | |
364 | bool ret = test_bit(flag, &flow->flags); | |
365 | ||
366 | /* Read fields of flow structure only after checking flags. */ | |
367 | smp_mb__after_atomic(); | |
368 | return ret; | |
369 | } | |
370 | ||
371 | #define flow_flag_test(flow, flag) __flow_flag_test(flow, \ | |
372 | MLX5E_TC_FLOW_FLAG_##flag) | |
373 | ||
374 | static bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow) | |
375 | { | |
376 | return flow_flag_test(flow, ESWITCH); | |
377 | } | |
378 | ||
84179981 PB |
379 | static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow) |
380 | { | |
381 | return flow_flag_test(flow, FT); | |
382 | } | |
383 | ||
226f2ca3 VB |
384 | static bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow) |
385 | { | |
386 | return flow_flag_test(flow, OFFLOADED); | |
387 | } | |
388 | ||
11c9c548 OG |
389 | static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key) |
390 | { | |
391 | return jhash(key->actions, | |
392 | key->num_actions * MLX5_MH_ACT_SZ, 0); | |
393 | } | |
394 | ||
395 | static inline int cmp_mod_hdr_info(struct mod_hdr_key *a, | |
396 | struct mod_hdr_key *b) | |
397 | { | |
398 | if (a->num_actions != b->num_actions) | |
399 | return 1; | |
400 | ||
401 | return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ); | |
402 | } | |
403 | ||
dd58edc3 VB |
404 | static struct mod_hdr_tbl * |
405 | get_mod_hdr_table(struct mlx5e_priv *priv, int namespace) | |
406 | { | |
407 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
408 | ||
409 | return namespace == MLX5_FLOW_NAMESPACE_FDB ? &esw->offloads.mod_hdr : | |
410 | &priv->fs.tc.mod_hdr; | |
411 | } | |
412 | ||
413 | static struct mlx5e_mod_hdr_entry * | |
414 | mlx5e_mod_hdr_get(struct mod_hdr_tbl *tbl, struct mod_hdr_key *key, u32 hash_key) | |
415 | { | |
416 | struct mlx5e_mod_hdr_entry *mh, *found = NULL; | |
417 | ||
418 | hash_for_each_possible(tbl->hlist, mh, mod_hdr_hlist, hash_key) { | |
419 | if (!cmp_mod_hdr_info(&mh->key, key)) { | |
420 | refcount_inc(&mh->refcnt); | |
421 | found = mh; | |
422 | break; | |
423 | } | |
424 | } | |
425 | ||
426 | return found; | |
427 | } | |
428 | ||
429 | static void mlx5e_mod_hdr_put(struct mlx5e_priv *priv, | |
d2faae25 VB |
430 | struct mlx5e_mod_hdr_entry *mh, |
431 | int namespace) | |
dd58edc3 | 432 | { |
d2faae25 VB |
433 | struct mod_hdr_tbl *tbl = get_mod_hdr_table(priv, namespace); |
434 | ||
435 | if (!refcount_dec_and_mutex_lock(&mh->refcnt, &tbl->lock)) | |
dd58edc3 | 436 | return; |
d2faae25 VB |
437 | hash_del(&mh->mod_hdr_hlist); |
438 | mutex_unlock(&tbl->lock); | |
dd58edc3 VB |
439 | |
440 | WARN_ON(!list_empty(&mh->flows)); | |
a734d007 | 441 | if (mh->compl_result > 0) |
2b688ea5 | 442 | mlx5_modify_header_dealloc(priv->mdev, mh->modify_hdr); |
d2faae25 | 443 | |
dd58edc3 VB |
444 | kfree(mh); |
445 | } | |
446 | ||
d2faae25 VB |
447 | static int get_flow_name_space(struct mlx5e_tc_flow *flow) |
448 | { | |
449 | return mlx5e_is_eswitch_flow(flow) ? | |
450 | MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL; | |
451 | } | |
11c9c548 OG |
452 | static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv, |
453 | struct mlx5e_tc_flow *flow, | |
454 | struct mlx5e_tc_flow_parse_attr *parse_attr) | |
455 | { | |
11c9c548 OG |
456 | int num_actions, actions_size, namespace, err; |
457 | struct mlx5e_mod_hdr_entry *mh; | |
dd58edc3 | 458 | struct mod_hdr_tbl *tbl; |
11c9c548 | 459 | struct mod_hdr_key key; |
11c9c548 OG |
460 | u32 hash_key; |
461 | ||
6ae4a6a5 | 462 | num_actions = parse_attr->mod_hdr_acts.num_actions; |
11c9c548 OG |
463 | actions_size = MLX5_MH_ACT_SZ * num_actions; |
464 | ||
6ae4a6a5 | 465 | key.actions = parse_attr->mod_hdr_acts.actions; |
11c9c548 OG |
466 | key.num_actions = num_actions; |
467 | ||
468 | hash_key = hash_mod_hdr_info(&key); | |
469 | ||
d2faae25 | 470 | namespace = get_flow_name_space(flow); |
dd58edc3 | 471 | tbl = get_mod_hdr_table(priv, namespace); |
11c9c548 | 472 | |
d2faae25 | 473 | mutex_lock(&tbl->lock); |
dd58edc3 | 474 | mh = mlx5e_mod_hdr_get(tbl, &key, hash_key); |
a734d007 VB |
475 | if (mh) { |
476 | mutex_unlock(&tbl->lock); | |
477 | wait_for_completion(&mh->res_ready); | |
478 | ||
479 | if (mh->compl_result < 0) { | |
480 | err = -EREMOTEIO; | |
481 | goto attach_header_err; | |
482 | } | |
11c9c548 | 483 | goto attach_flow; |
a734d007 | 484 | } |
11c9c548 OG |
485 | |
486 | mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL); | |
d2faae25 | 487 | if (!mh) { |
a734d007 VB |
488 | mutex_unlock(&tbl->lock); |
489 | return -ENOMEM; | |
d2faae25 | 490 | } |
11c9c548 OG |
491 | |
492 | mh->key.actions = (void *)mh + sizeof(*mh); | |
493 | memcpy(mh->key.actions, key.actions, actions_size); | |
494 | mh->key.num_actions = num_actions; | |
83a52f0d | 495 | spin_lock_init(&mh->flows_lock); |
11c9c548 | 496 | INIT_LIST_HEAD(&mh->flows); |
dd58edc3 | 497 | refcount_set(&mh->refcnt, 1); |
a734d007 VB |
498 | init_completion(&mh->res_ready); |
499 | ||
500 | hash_add(tbl->hlist, &mh->mod_hdr_hlist, hash_key); | |
501 | mutex_unlock(&tbl->lock); | |
11c9c548 | 502 | |
2b688ea5 MG |
503 | mh->modify_hdr = mlx5_modify_header_alloc(priv->mdev, namespace, |
504 | mh->key.num_actions, | |
505 | mh->key.actions); | |
506 | if (IS_ERR(mh->modify_hdr)) { | |
507 | err = PTR_ERR(mh->modify_hdr); | |
a734d007 VB |
508 | mh->compl_result = err; |
509 | goto alloc_header_err; | |
510 | } | |
511 | mh->compl_result = 1; | |
512 | complete_all(&mh->res_ready); | |
11c9c548 OG |
513 | |
514 | attach_flow: | |
dd58edc3 | 515 | flow->mh = mh; |
83a52f0d | 516 | spin_lock(&mh->flows_lock); |
11c9c548 | 517 | list_add(&flow->mod_hdr, &mh->flows); |
83a52f0d | 518 | spin_unlock(&mh->flows_lock); |
d2faae25 | 519 | if (mlx5e_is_eswitch_flow(flow)) |
2b688ea5 | 520 | flow->esw_attr->modify_hdr = mh->modify_hdr; |
11c9c548 | 521 | else |
2b688ea5 | 522 | flow->nic_attr->modify_hdr = mh->modify_hdr; |
11c9c548 OG |
523 | |
524 | return 0; | |
525 | ||
a734d007 VB |
526 | alloc_header_err: |
527 | complete_all(&mh->res_ready); | |
528 | attach_header_err: | |
529 | mlx5e_mod_hdr_put(priv, mh, namespace); | |
11c9c548 OG |
530 | return err; |
531 | } | |
532 | ||
533 | static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv, | |
534 | struct mlx5e_tc_flow *flow) | |
535 | { | |
5a7e5bcb | 536 | /* flow wasn't fully initialized */ |
dd58edc3 | 537 | if (!flow->mh) |
5a7e5bcb VB |
538 | return; |
539 | ||
83a52f0d | 540 | spin_lock(&flow->mh->flows_lock); |
11c9c548 | 541 | list_del(&flow->mod_hdr); |
83a52f0d | 542 | spin_unlock(&flow->mh->flows_lock); |
11c9c548 | 543 | |
d2faae25 | 544 | mlx5e_mod_hdr_put(priv, flow->mh, get_flow_name_space(flow)); |
dd58edc3 | 545 | flow->mh = NULL; |
11c9c548 OG |
546 | } |
547 | ||
77ab67b7 OG |
548 | static |
549 | struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex) | |
550 | { | |
551 | struct net_device *netdev; | |
552 | struct mlx5e_priv *priv; | |
553 | ||
554 | netdev = __dev_get_by_index(net, ifindex); | |
555 | priv = netdev_priv(netdev); | |
556 | return priv->mdev; | |
557 | } | |
558 | ||
559 | static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp) | |
560 | { | |
e0b4b472 | 561 | u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {}; |
77ab67b7 OG |
562 | void *tirc; |
563 | int err; | |
564 | ||
565 | err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn); | |
566 | if (err) | |
567 | goto alloc_tdn_err; | |
568 | ||
569 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
570 | ||
571 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); | |
ddae74ac | 572 | MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]); |
77ab67b7 OG |
573 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); |
574 | ||
e0b4b472 | 575 | err = mlx5_core_create_tir(hp->func_mdev, in, &hp->tirn); |
77ab67b7 OG |
576 | if (err) |
577 | goto create_tir_err; | |
578 | ||
579 | return 0; | |
580 | ||
581 | create_tir_err: | |
582 | mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); | |
583 | alloc_tdn_err: | |
584 | return err; | |
585 | } | |
586 | ||
587 | static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp) | |
588 | { | |
589 | mlx5_core_destroy_tir(hp->func_mdev, hp->tirn); | |
590 | mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); | |
591 | } | |
592 | ||
3f6d08d1 OG |
593 | static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc) |
594 | { | |
595 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn; | |
596 | struct mlx5e_priv *priv = hp->func_priv; | |
597 | int i, ix, sz = MLX5E_INDIR_RQT_SIZE; | |
598 | ||
599 | mlx5e_build_default_indir_rqt(indirection_rqt, sz, | |
600 | hp->num_channels); | |
601 | ||
602 | for (i = 0; i < sz; i++) { | |
603 | ix = i; | |
bbeb53b8 | 604 | if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR) |
3f6d08d1 OG |
605 | ix = mlx5e_bits_invert(i, ilog2(sz)); |
606 | ix = indirection_rqt[ix]; | |
607 | rqn = hp->pair->rqn[ix]; | |
608 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
609 | } | |
610 | } | |
611 | ||
612 | static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp) | |
613 | { | |
614 | int inlen, err, sz = MLX5E_INDIR_RQT_SIZE; | |
615 | struct mlx5e_priv *priv = hp->func_priv; | |
616 | struct mlx5_core_dev *mdev = priv->mdev; | |
617 | void *rqtc; | |
618 | u32 *in; | |
619 | ||
620 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
621 | in = kvzalloc(inlen, GFP_KERNEL); | |
622 | if (!in) | |
623 | return -ENOMEM; | |
624 | ||
625 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
626 | ||
627 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
628 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
629 | ||
630 | mlx5e_hairpin_fill_rqt_rqns(hp, rqtc); | |
631 | ||
632 | err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn); | |
633 | if (!err) | |
634 | hp->indir_rqt.enabled = true; | |
635 | ||
636 | kvfree(in); | |
637 | return err; | |
638 | } | |
639 | ||
640 | static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp) | |
641 | { | |
642 | struct mlx5e_priv *priv = hp->func_priv; | |
643 | u32 in[MLX5_ST_SZ_DW(create_tir_in)]; | |
644 | int tt, i, err; | |
645 | void *tirc; | |
646 | ||
647 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
d930ac79 AL |
648 | struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt); |
649 | ||
3f6d08d1 OG |
650 | memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in)); |
651 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
652 | ||
653 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); | |
654 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
655 | MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn); | |
bbeb53b8 AL |
656 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false); |
657 | ||
3f6d08d1 | 658 | err = mlx5_core_create_tir(hp->func_mdev, in, |
e0b4b472 | 659 | &hp->indir_tirn[tt]); |
3f6d08d1 OG |
660 | if (err) { |
661 | mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err); | |
662 | goto err_destroy_tirs; | |
663 | } | |
664 | } | |
665 | return 0; | |
666 | ||
667 | err_destroy_tirs: | |
668 | for (i = 0; i < tt; i++) | |
669 | mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]); | |
670 | return err; | |
671 | } | |
672 | ||
673 | static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp) | |
674 | { | |
675 | int tt; | |
676 | ||
677 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) | |
678 | mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]); | |
679 | } | |
680 | ||
681 | static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp, | |
682 | struct ttc_params *ttc_params) | |
683 | { | |
684 | struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr; | |
685 | int tt; | |
686 | ||
687 | memset(ttc_params, 0, sizeof(*ttc_params)); | |
688 | ||
689 | ttc_params->any_tt_tirn = hp->tirn; | |
690 | ||
691 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) | |
692 | ttc_params->indir_tirn[tt] = hp->indir_tirn[tt]; | |
693 | ||
6412bb39 | 694 | ft_attr->max_fte = MLX5E_TTC_TABLE_SIZE; |
3f6d08d1 OG |
695 | ft_attr->level = MLX5E_TC_TTC_FT_LEVEL; |
696 | ft_attr->prio = MLX5E_TC_PRIO; | |
697 | } | |
698 | ||
699 | static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp) | |
700 | { | |
701 | struct mlx5e_priv *priv = hp->func_priv; | |
702 | struct ttc_params ttc_params; | |
703 | int err; | |
704 | ||
705 | err = mlx5e_hairpin_create_indirect_rqt(hp); | |
706 | if (err) | |
707 | return err; | |
708 | ||
709 | err = mlx5e_hairpin_create_indirect_tirs(hp); | |
710 | if (err) | |
711 | goto err_create_indirect_tirs; | |
712 | ||
713 | mlx5e_hairpin_set_ttc_params(hp, &ttc_params); | |
714 | err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc); | |
715 | if (err) | |
716 | goto err_create_ttc_table; | |
717 | ||
718 | netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n", | |
719 | hp->num_channels, hp->ttc.ft.t->id); | |
720 | ||
721 | return 0; | |
722 | ||
723 | err_create_ttc_table: | |
724 | mlx5e_hairpin_destroy_indirect_tirs(hp); | |
725 | err_create_indirect_tirs: | |
726 | mlx5e_destroy_rqt(priv, &hp->indir_rqt); | |
727 | ||
728 | return err; | |
729 | } | |
730 | ||
731 | static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp) | |
732 | { | |
733 | struct mlx5e_priv *priv = hp->func_priv; | |
734 | ||
735 | mlx5e_destroy_ttc_table(priv, &hp->ttc); | |
736 | mlx5e_hairpin_destroy_indirect_tirs(hp); | |
737 | mlx5e_destroy_rqt(priv, &hp->indir_rqt); | |
738 | } | |
739 | ||
77ab67b7 OG |
740 | static struct mlx5e_hairpin * |
741 | mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params, | |
742 | int peer_ifindex) | |
743 | { | |
744 | struct mlx5_core_dev *func_mdev, *peer_mdev; | |
745 | struct mlx5e_hairpin *hp; | |
746 | struct mlx5_hairpin *pair; | |
747 | int err; | |
748 | ||
749 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); | |
750 | if (!hp) | |
751 | return ERR_PTR(-ENOMEM); | |
752 | ||
753 | func_mdev = priv->mdev; | |
754 | peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); | |
755 | ||
756 | pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params); | |
757 | if (IS_ERR(pair)) { | |
758 | err = PTR_ERR(pair); | |
759 | goto create_pair_err; | |
760 | } | |
761 | hp->pair = pair; | |
762 | hp->func_mdev = func_mdev; | |
3f6d08d1 OG |
763 | hp->func_priv = priv; |
764 | hp->num_channels = params->num_channels; | |
77ab67b7 OG |
765 | |
766 | err = mlx5e_hairpin_create_transport(hp); | |
767 | if (err) | |
768 | goto create_transport_err; | |
769 | ||
3f6d08d1 OG |
770 | if (hp->num_channels > 1) { |
771 | err = mlx5e_hairpin_rss_init(hp); | |
772 | if (err) | |
773 | goto rss_init_err; | |
774 | } | |
775 | ||
77ab67b7 OG |
776 | return hp; |
777 | ||
3f6d08d1 OG |
778 | rss_init_err: |
779 | mlx5e_hairpin_destroy_transport(hp); | |
77ab67b7 OG |
780 | create_transport_err: |
781 | mlx5_core_hairpin_destroy(hp->pair); | |
782 | create_pair_err: | |
783 | kfree(hp); | |
784 | return ERR_PTR(err); | |
785 | } | |
786 | ||
787 | static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp) | |
788 | { | |
3f6d08d1 OG |
789 | if (hp->num_channels > 1) |
790 | mlx5e_hairpin_rss_cleanup(hp); | |
77ab67b7 OG |
791 | mlx5e_hairpin_destroy_transport(hp); |
792 | mlx5_core_hairpin_destroy(hp->pair); | |
793 | kvfree(hp); | |
794 | } | |
795 | ||
106be53b OG |
796 | static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio) |
797 | { | |
798 | return (peer_vhca_id << 16 | prio); | |
799 | } | |
800 | ||
5c65c564 | 801 | static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv, |
106be53b | 802 | u16 peer_vhca_id, u8 prio) |
5c65c564 OG |
803 | { |
804 | struct mlx5e_hairpin_entry *hpe; | |
106be53b | 805 | u32 hash_key = hash_hairpin_info(peer_vhca_id, prio); |
5c65c564 OG |
806 | |
807 | hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe, | |
106be53b | 808 | hairpin_hlist, hash_key) { |
e4f9abbd VB |
809 | if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) { |
810 | refcount_inc(&hpe->refcnt); | |
5c65c564 | 811 | return hpe; |
e4f9abbd | 812 | } |
5c65c564 OG |
813 | } |
814 | ||
815 | return NULL; | |
816 | } | |
817 | ||
e4f9abbd VB |
818 | static void mlx5e_hairpin_put(struct mlx5e_priv *priv, |
819 | struct mlx5e_hairpin_entry *hpe) | |
820 | { | |
821 | /* no more hairpin flows for us, release the hairpin pair */ | |
b32accda | 822 | if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock)) |
e4f9abbd | 823 | return; |
b32accda VB |
824 | hash_del(&hpe->hairpin_hlist); |
825 | mutex_unlock(&priv->fs.tc.hairpin_tbl_lock); | |
e4f9abbd | 826 | |
db76ca24 VB |
827 | if (!IS_ERR_OR_NULL(hpe->hp)) { |
828 | netdev_dbg(priv->netdev, "del hairpin: peer %s\n", | |
829 | dev_name(hpe->hp->pair->peer_mdev->device)); | |
830 | ||
831 | mlx5e_hairpin_destroy(hpe->hp); | |
832 | } | |
e4f9abbd VB |
833 | |
834 | WARN_ON(!list_empty(&hpe->flows)); | |
e4f9abbd VB |
835 | kfree(hpe); |
836 | } | |
837 | ||
106be53b OG |
838 | #define UNKNOWN_MATCH_PRIO 8 |
839 | ||
840 | static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv, | |
e98bedf5 EB |
841 | struct mlx5_flow_spec *spec, u8 *match_prio, |
842 | struct netlink_ext_ack *extack) | |
106be53b OG |
843 | { |
844 | void *headers_c, *headers_v; | |
845 | u8 prio_val, prio_mask = 0; | |
846 | bool vlan_present; | |
847 | ||
848 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
849 | if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) { | |
e98bedf5 EB |
850 | NL_SET_ERR_MSG_MOD(extack, |
851 | "only PCP trust state supported for hairpin"); | |
106be53b OG |
852 | return -EOPNOTSUPP; |
853 | } | |
854 | #endif | |
855 | headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers); | |
856 | headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); | |
857 | ||
858 | vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag); | |
859 | if (vlan_present) { | |
860 | prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); | |
861 | prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); | |
862 | } | |
863 | ||
864 | if (!vlan_present || !prio_mask) { | |
865 | prio_val = UNKNOWN_MATCH_PRIO; | |
866 | } else if (prio_mask != 0x7) { | |
e98bedf5 EB |
867 | NL_SET_ERR_MSG_MOD(extack, |
868 | "masked priority match not supported for hairpin"); | |
106be53b OG |
869 | return -EOPNOTSUPP; |
870 | } | |
871 | ||
872 | *match_prio = prio_val; | |
873 | return 0; | |
874 | } | |
875 | ||
5c65c564 OG |
876 | static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv, |
877 | struct mlx5e_tc_flow *flow, | |
e98bedf5 EB |
878 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
879 | struct netlink_ext_ack *extack) | |
5c65c564 | 880 | { |
98b66cb1 | 881 | int peer_ifindex = parse_attr->mirred_ifindex[0]; |
5c65c564 | 882 | struct mlx5_hairpin_params params; |
d8822868 | 883 | struct mlx5_core_dev *peer_mdev; |
5c65c564 OG |
884 | struct mlx5e_hairpin_entry *hpe; |
885 | struct mlx5e_hairpin *hp; | |
3f6d08d1 OG |
886 | u64 link_speed64; |
887 | u32 link_speed; | |
106be53b | 888 | u8 match_prio; |
d8822868 | 889 | u16 peer_id; |
5c65c564 OG |
890 | int err; |
891 | ||
d8822868 OG |
892 | peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); |
893 | if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) { | |
e98bedf5 | 894 | NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported"); |
5c65c564 OG |
895 | return -EOPNOTSUPP; |
896 | } | |
897 | ||
d8822868 | 898 | peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id); |
e98bedf5 EB |
899 | err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio, |
900 | extack); | |
106be53b OG |
901 | if (err) |
902 | return err; | |
b32accda VB |
903 | |
904 | mutex_lock(&priv->fs.tc.hairpin_tbl_lock); | |
106be53b | 905 | hpe = mlx5e_hairpin_get(priv, peer_id, match_prio); |
db76ca24 VB |
906 | if (hpe) { |
907 | mutex_unlock(&priv->fs.tc.hairpin_tbl_lock); | |
908 | wait_for_completion(&hpe->res_ready); | |
909 | ||
910 | if (IS_ERR(hpe->hp)) { | |
911 | err = -EREMOTEIO; | |
912 | goto out_err; | |
913 | } | |
5c65c564 | 914 | goto attach_flow; |
db76ca24 | 915 | } |
5c65c564 OG |
916 | |
917 | hpe = kzalloc(sizeof(*hpe), GFP_KERNEL); | |
b32accda | 918 | if (!hpe) { |
db76ca24 VB |
919 | mutex_unlock(&priv->fs.tc.hairpin_tbl_lock); |
920 | return -ENOMEM; | |
b32accda | 921 | } |
5c65c564 | 922 | |
73edca73 | 923 | spin_lock_init(&hpe->flows_lock); |
5c65c564 | 924 | INIT_LIST_HEAD(&hpe->flows); |
db76ca24 | 925 | INIT_LIST_HEAD(&hpe->dead_peer_wait_list); |
d8822868 | 926 | hpe->peer_vhca_id = peer_id; |
106be53b | 927 | hpe->prio = match_prio; |
e4f9abbd | 928 | refcount_set(&hpe->refcnt, 1); |
db76ca24 VB |
929 | init_completion(&hpe->res_ready); |
930 | ||
931 | hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist, | |
932 | hash_hairpin_info(peer_id, match_prio)); | |
933 | mutex_unlock(&priv->fs.tc.hairpin_tbl_lock); | |
5c65c564 OG |
934 | |
935 | params.log_data_size = 15; | |
936 | params.log_data_size = min_t(u8, params.log_data_size, | |
937 | MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz)); | |
938 | params.log_data_size = max_t(u8, params.log_data_size, | |
939 | MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz)); | |
5c65c564 | 940 | |
eb9180f7 OG |
941 | params.log_num_packets = params.log_data_size - |
942 | MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev); | |
943 | params.log_num_packets = min_t(u8, params.log_num_packets, | |
944 | MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets)); | |
945 | ||
946 | params.q_counter = priv->q_counter; | |
3f6d08d1 | 947 | /* set hairpin pair per each 50Gbs share of the link */ |
2c81bfd5 | 948 | mlx5e_port_max_linkspeed(priv->mdev, &link_speed); |
3f6d08d1 OG |
949 | link_speed = max_t(u32, link_speed, 50000); |
950 | link_speed64 = link_speed; | |
951 | do_div(link_speed64, 50000); | |
952 | params.num_channels = link_speed64; | |
953 | ||
5c65c564 | 954 | hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex); |
db76ca24 VB |
955 | hpe->hp = hp; |
956 | complete_all(&hpe->res_ready); | |
5c65c564 OG |
957 | if (IS_ERR(hp)) { |
958 | err = PTR_ERR(hp); | |
db76ca24 | 959 | goto out_err; |
5c65c564 OG |
960 | } |
961 | ||
eb9180f7 | 962 | netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n", |
27b942fb PP |
963 | hp->tirn, hp->pair->rqn[0], |
964 | dev_name(hp->pair->peer_mdev->device), | |
eb9180f7 | 965 | hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets); |
5c65c564 | 966 | |
5c65c564 | 967 | attach_flow: |
3f6d08d1 | 968 | if (hpe->hp->num_channels > 1) { |
226f2ca3 | 969 | flow_flag_set(flow, HAIRPIN_RSS); |
3f6d08d1 OG |
970 | flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t; |
971 | } else { | |
972 | flow->nic_attr->hairpin_tirn = hpe->hp->tirn; | |
973 | } | |
b32accda | 974 | |
e4f9abbd | 975 | flow->hpe = hpe; |
73edca73 | 976 | spin_lock(&hpe->flows_lock); |
5c65c564 | 977 | list_add(&flow->hairpin, &hpe->flows); |
73edca73 | 978 | spin_unlock(&hpe->flows_lock); |
3f6d08d1 | 979 | |
5c65c564 OG |
980 | return 0; |
981 | ||
db76ca24 VB |
982 | out_err: |
983 | mlx5e_hairpin_put(priv, hpe); | |
5c65c564 OG |
984 | return err; |
985 | } | |
986 | ||
987 | static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv, | |
988 | struct mlx5e_tc_flow *flow) | |
989 | { | |
5a7e5bcb | 990 | /* flow wasn't fully initialized */ |
e4f9abbd | 991 | if (!flow->hpe) |
5a7e5bcb VB |
992 | return; |
993 | ||
73edca73 | 994 | spin_lock(&flow->hpe->flows_lock); |
5c65c564 | 995 | list_del(&flow->hairpin); |
73edca73 VB |
996 | spin_unlock(&flow->hpe->flows_lock); |
997 | ||
e4f9abbd VB |
998 | mlx5e_hairpin_put(priv, flow->hpe); |
999 | flow->hpe = NULL; | |
5c65c564 OG |
1000 | } |
1001 | ||
c83954ab | 1002 | static int |
74491de9 | 1003 | mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv, |
17091853 | 1004 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
1005 | struct mlx5e_tc_flow *flow, |
1006 | struct netlink_ext_ack *extack) | |
e8f887ac | 1007 | { |
bb0ee7dc | 1008 | struct mlx5_flow_context *flow_context = &parse_attr->spec.flow_context; |
aa0cbbae | 1009 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
aad7e08d | 1010 | struct mlx5_core_dev *dev = priv->mdev; |
5c65c564 | 1011 | struct mlx5_flow_destination dest[2] = {}; |
66958ed9 | 1012 | struct mlx5_flow_act flow_act = { |
3bc4b7bf | 1013 | .action = attr->action, |
bb0ee7dc | 1014 | .flags = FLOW_ACT_NO_APPEND, |
66958ed9 | 1015 | }; |
aad7e08d | 1016 | struct mlx5_fc *counter = NULL; |
5c65c564 | 1017 | int err, dest_ix = 0; |
e8f887ac | 1018 | |
bb0ee7dc JL |
1019 | flow_context->flags |= FLOW_CONTEXT_HAS_TAG; |
1020 | flow_context->flow_tag = attr->flow_tag; | |
1021 | ||
226f2ca3 | 1022 | if (flow_flag_test(flow, HAIRPIN)) { |
e98bedf5 | 1023 | err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack); |
5a7e5bcb VB |
1024 | if (err) |
1025 | return err; | |
1026 | ||
226f2ca3 | 1027 | if (flow_flag_test(flow, HAIRPIN_RSS)) { |
3f6d08d1 OG |
1028 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; |
1029 | dest[dest_ix].ft = attr->hairpin_ft; | |
1030 | } else { | |
5c65c564 OG |
1031 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR; |
1032 | dest[dest_ix].tir_num = attr->hairpin_tirn; | |
5c65c564 OG |
1033 | } |
1034 | dest_ix++; | |
3f6d08d1 OG |
1035 | } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { |
1036 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
1037 | dest[dest_ix].ft = priv->fs.vlan.ft.t; | |
1038 | dest_ix++; | |
5c65c564 | 1039 | } |
aad7e08d | 1040 | |
5c65c564 OG |
1041 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
1042 | counter = mlx5_fc_create(dev, true); | |
5a7e5bcb VB |
1043 | if (IS_ERR(counter)) |
1044 | return PTR_ERR(counter); | |
1045 | ||
5c65c564 | 1046 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; |
171c7625 | 1047 | dest[dest_ix].counter_id = mlx5_fc_id(counter); |
5c65c564 | 1048 | dest_ix++; |
b8aee822 | 1049 | attr->counter = counter; |
aad7e08d AV |
1050 | } |
1051 | ||
2f4fe4ca | 1052 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { |
3099eb5a | 1053 | err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); |
2b688ea5 | 1054 | flow_act.modify_hdr = attr->modify_hdr; |
6ae4a6a5 | 1055 | dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts); |
c83954ab | 1056 | if (err) |
5a7e5bcb | 1057 | return err; |
2f4fe4ca OG |
1058 | } |
1059 | ||
b6fac0b4 | 1060 | mutex_lock(&priv->fs.tc.t_lock); |
acff797c | 1061 | if (IS_ERR_OR_NULL(priv->fs.tc.t)) { |
61dc7b01 PB |
1062 | struct mlx5_flow_table_attr ft_attr = {}; |
1063 | int tc_grp_size, tc_tbl_size, tc_num_grps; | |
21b9c144 OG |
1064 | u32 max_flow_counter; |
1065 | ||
1066 | max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) | | |
1067 | MLX5_CAP_GEN(dev, max_flow_counter_15_0); | |
1068 | ||
1069 | tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE); | |
1070 | ||
1071 | tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS, | |
1072 | BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size))); | |
61dc7b01 | 1073 | tc_num_grps = MLX5E_TC_TABLE_NUM_GROUPS; |
21b9c144 | 1074 | |
61dc7b01 PB |
1075 | ft_attr.prio = MLX5E_TC_PRIO; |
1076 | ft_attr.max_fte = tc_tbl_size; | |
1077 | ft_attr.level = MLX5E_TC_FT_LEVEL; | |
1078 | ft_attr.autogroup.max_num_groups = tc_num_grps; | |
acff797c MG |
1079 | priv->fs.tc.t = |
1080 | mlx5_create_auto_grouped_flow_table(priv->fs.ns, | |
61dc7b01 | 1081 | &ft_attr); |
acff797c | 1082 | if (IS_ERR(priv->fs.tc.t)) { |
b6fac0b4 | 1083 | mutex_unlock(&priv->fs.tc.t_lock); |
e98bedf5 | 1084 | NL_SET_ERR_MSG_MOD(extack, |
c75a33c8 | 1085 | "Failed to create tc offload table"); |
e8f887ac AV |
1086 | netdev_err(priv->netdev, |
1087 | "Failed to create tc offload table\n"); | |
5a7e5bcb | 1088 | return PTR_ERR(priv->fs.tc.t); |
e8f887ac | 1089 | } |
e8f887ac AV |
1090 | } |
1091 | ||
38aa51c1 | 1092 | if (attr->match_level != MLX5_MATCH_NONE) |
d4a18e16 | 1093 | parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
38aa51c1 | 1094 | |
c83954ab RL |
1095 | flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec, |
1096 | &flow_act, dest, dest_ix); | |
b6fac0b4 | 1097 | mutex_unlock(&priv->fs.tc.t_lock); |
aad7e08d | 1098 | |
a2b7189b | 1099 | return PTR_ERR_OR_ZERO(flow->rule[0]); |
e8f887ac AV |
1100 | } |
1101 | ||
d85cdccb OG |
1102 | static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv, |
1103 | struct mlx5e_tc_flow *flow) | |
1104 | { | |
513f8f7f | 1105 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
d85cdccb OG |
1106 | struct mlx5_fc *counter = NULL; |
1107 | ||
b8aee822 | 1108 | counter = attr->counter; |
5a7e5bcb VB |
1109 | if (!IS_ERR_OR_NULL(flow->rule[0])) |
1110 | mlx5_del_flow_rules(flow->rule[0]); | |
aa0cbbae | 1111 | mlx5_fc_destroy(priv->mdev, counter); |
d85cdccb | 1112 | |
b6fac0b4 | 1113 | mutex_lock(&priv->fs.tc.t_lock); |
226f2ca3 | 1114 | if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) && priv->fs.tc.t) { |
d85cdccb OG |
1115 | mlx5_destroy_flow_table(priv->fs.tc.t); |
1116 | priv->fs.tc.t = NULL; | |
1117 | } | |
b6fac0b4 | 1118 | mutex_unlock(&priv->fs.tc.t_lock); |
2f4fe4ca | 1119 | |
513f8f7f | 1120 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
3099eb5a | 1121 | mlx5e_detach_mod_hdr(priv, flow); |
5c65c564 | 1122 | |
226f2ca3 | 1123 | if (flow_flag_test(flow, HAIRPIN)) |
5c65c564 | 1124 | mlx5e_hairpin_flow_del(priv, flow); |
d85cdccb OG |
1125 | } |
1126 | ||
aa0cbbae | 1127 | static void mlx5e_detach_encap(struct mlx5e_priv *priv, |
8c4dc42b | 1128 | struct mlx5e_tc_flow *flow, int out_index); |
aa0cbbae | 1129 | |
3c37745e | 1130 | static int mlx5e_attach_encap(struct mlx5e_priv *priv, |
e98bedf5 | 1131 | struct mlx5e_tc_flow *flow, |
733d4f36 RD |
1132 | struct net_device *mirred_dev, |
1133 | int out_index, | |
8c4dc42b | 1134 | struct netlink_ext_ack *extack, |
0ad060ee RD |
1135 | struct net_device **encap_dev, |
1136 | bool *encap_valid); | |
14e6b038 EC |
1137 | static int mlx5e_attach_decap(struct mlx5e_priv *priv, |
1138 | struct mlx5e_tc_flow *flow, | |
1139 | struct netlink_ext_ack *extack); | |
1140 | static void mlx5e_detach_decap(struct mlx5e_priv *priv, | |
1141 | struct mlx5e_tc_flow *flow); | |
3c37745e | 1142 | |
6d2a3ed0 OG |
1143 | static struct mlx5_flow_handle * |
1144 | mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw, | |
1145 | struct mlx5e_tc_flow *flow, | |
1146 | struct mlx5_flow_spec *spec, | |
1147 | struct mlx5_esw_flow_attr *attr) | |
1148 | { | |
1ef3018f | 1149 | struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts; |
6d2a3ed0 | 1150 | struct mlx5_flow_handle *rule; |
4c3844d9 | 1151 | |
1ef3018f PB |
1152 | if (flow_flag_test(flow, CT)) { |
1153 | mod_hdr_acts = &attr->parse_attr->mod_hdr_acts; | |
1154 | ||
1155 | return mlx5_tc_ct_flow_offload(flow->priv, flow, spec, attr, | |
1156 | mod_hdr_acts); | |
1157 | } | |
6d2a3ed0 OG |
1158 | |
1159 | rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr); | |
1160 | if (IS_ERR(rule)) | |
1161 | return rule; | |
1162 | ||
e85e02ba | 1163 | if (attr->split_count) { |
6d2a3ed0 OG |
1164 | flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr); |
1165 | if (IS_ERR(flow->rule[1])) { | |
1166 | mlx5_eswitch_del_offloaded_rule(esw, rule, attr); | |
1167 | return flow->rule[1]; | |
1168 | } | |
1169 | } | |
1170 | ||
6d2a3ed0 OG |
1171 | return rule; |
1172 | } | |
1173 | ||
1174 | static void | |
1175 | mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw, | |
1176 | struct mlx5e_tc_flow *flow, | |
4c3844d9 | 1177 | struct mlx5_esw_flow_attr *attr) |
6d2a3ed0 | 1178 | { |
226f2ca3 | 1179 | flow_flag_clear(flow, OFFLOADED); |
6d2a3ed0 | 1180 | |
4c3844d9 PB |
1181 | if (flow_flag_test(flow, CT)) { |
1182 | mlx5_tc_ct_delete_flow(flow->priv, flow, attr); | |
1183 | return; | |
1184 | } | |
1185 | ||
e85e02ba | 1186 | if (attr->split_count) |
6d2a3ed0 OG |
1187 | mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr); |
1188 | ||
1189 | mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr); | |
1190 | } | |
1191 | ||
5dbe906f PB |
1192 | static struct mlx5_flow_handle * |
1193 | mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw, | |
1194 | struct mlx5e_tc_flow *flow, | |
178f69b4 | 1195 | struct mlx5_flow_spec *spec) |
5dbe906f | 1196 | { |
178f69b4 | 1197 | struct mlx5_esw_flow_attr slow_attr; |
5dbe906f PB |
1198 | struct mlx5_flow_handle *rule; |
1199 | ||
178f69b4 EC |
1200 | memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr)); |
1201 | slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1202 | slow_attr.split_count = 0; | |
1203 | slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH; | |
5dbe906f | 1204 | |
178f69b4 | 1205 | rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, &slow_attr); |
5dbe906f | 1206 | if (!IS_ERR(rule)) |
226f2ca3 | 1207 | flow_flag_set(flow, SLOW); |
5dbe906f PB |
1208 | |
1209 | return rule; | |
1210 | } | |
1211 | ||
1212 | static void | |
1213 | mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw, | |
178f69b4 | 1214 | struct mlx5e_tc_flow *flow) |
5dbe906f | 1215 | { |
178f69b4 EC |
1216 | struct mlx5_esw_flow_attr slow_attr; |
1217 | ||
1218 | memcpy(&slow_attr, flow->esw_attr, sizeof(slow_attr)); | |
1219 | slow_attr.action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
1220 | slow_attr.split_count = 0; | |
1221 | slow_attr.flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH; | |
1222 | mlx5e_tc_unoffload_fdb_rules(esw, flow, &slow_attr); | |
226f2ca3 | 1223 | flow_flag_clear(flow, SLOW); |
5dbe906f PB |
1224 | } |
1225 | ||
ad86755b VB |
1226 | /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this |
1227 | * function. | |
1228 | */ | |
1229 | static void unready_flow_add(struct mlx5e_tc_flow *flow, | |
1230 | struct list_head *unready_flows) | |
1231 | { | |
1232 | flow_flag_set(flow, NOT_READY); | |
1233 | list_add_tail(&flow->unready, unready_flows); | |
1234 | } | |
1235 | ||
1236 | /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this | |
1237 | * function. | |
1238 | */ | |
1239 | static void unready_flow_del(struct mlx5e_tc_flow *flow) | |
1240 | { | |
1241 | list_del(&flow->unready); | |
1242 | flow_flag_clear(flow, NOT_READY); | |
1243 | } | |
1244 | ||
b4a23329 RD |
1245 | static void add_unready_flow(struct mlx5e_tc_flow *flow) |
1246 | { | |
1247 | struct mlx5_rep_uplink_priv *uplink_priv; | |
1248 | struct mlx5e_rep_priv *rpriv; | |
1249 | struct mlx5_eswitch *esw; | |
1250 | ||
1251 | esw = flow->priv->mdev->priv.eswitch; | |
1252 | rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); | |
1253 | uplink_priv = &rpriv->uplink_priv; | |
1254 | ||
ad86755b VB |
1255 | mutex_lock(&uplink_priv->unready_flows_lock); |
1256 | unready_flow_add(flow, &uplink_priv->unready_flows); | |
1257 | mutex_unlock(&uplink_priv->unready_flows_lock); | |
b4a23329 RD |
1258 | } |
1259 | ||
1260 | static void remove_unready_flow(struct mlx5e_tc_flow *flow) | |
1261 | { | |
ad86755b VB |
1262 | struct mlx5_rep_uplink_priv *uplink_priv; |
1263 | struct mlx5e_rep_priv *rpriv; | |
1264 | struct mlx5_eswitch *esw; | |
1265 | ||
1266 | esw = flow->priv->mdev->priv.eswitch; | |
1267 | rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); | |
1268 | uplink_priv = &rpriv->uplink_priv; | |
1269 | ||
1270 | mutex_lock(&uplink_priv->unready_flows_lock); | |
1271 | unready_flow_del(flow); | |
1272 | mutex_unlock(&uplink_priv->unready_flows_lock); | |
b4a23329 RD |
1273 | } |
1274 | ||
c83954ab | 1275 | static int |
74491de9 | 1276 | mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv, |
e98bedf5 EB |
1277 | struct mlx5e_tc_flow *flow, |
1278 | struct netlink_ext_ack *extack) | |
adb4c123 OG |
1279 | { |
1280 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
aa0cbbae | 1281 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
7040632d | 1282 | struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; |
3c37745e | 1283 | struct net_device *out_dev, *encap_dev = NULL; |
b8aee822 | 1284 | struct mlx5_fc *counter = NULL; |
3c37745e OG |
1285 | struct mlx5e_rep_priv *rpriv; |
1286 | struct mlx5e_priv *out_priv; | |
0ad060ee | 1287 | bool encap_valid = true; |
39ac237c | 1288 | u32 max_prio, max_chain; |
0ad060ee | 1289 | int err = 0; |
f493f155 | 1290 | int out_index; |
8b32580d | 1291 | |
39ac237c | 1292 | if (!mlx5_esw_chains_prios_supported(esw) && attr->prio != 1) { |
61644c3d RD |
1293 | NL_SET_ERR_MSG_MOD(extack, |
1294 | "E-switch priorities unsupported, upgrade FW"); | |
d14f6f2a OG |
1295 | return -EOPNOTSUPP; |
1296 | } | |
bf07aa73 | 1297 | |
84179981 PB |
1298 | /* We check chain range only for tc flows. |
1299 | * For ft flows, we checked attr->chain was originally 0 and set it to | |
1300 | * FDB_FT_CHAIN which is outside tc range. | |
1301 | * See mlx5e_rep_setup_ft_cb(). | |
1302 | */ | |
39ac237c | 1303 | max_chain = mlx5_esw_chains_get_chain_range(esw); |
84179981 | 1304 | if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) { |
61644c3d RD |
1305 | NL_SET_ERR_MSG_MOD(extack, |
1306 | "Requested chain is out of supported range"); | |
5a7e5bcb | 1307 | return -EOPNOTSUPP; |
bf07aa73 PB |
1308 | } |
1309 | ||
39ac237c | 1310 | max_prio = mlx5_esw_chains_get_prio_range(esw); |
bf07aa73 | 1311 | if (attr->prio > max_prio) { |
61644c3d RD |
1312 | NL_SET_ERR_MSG_MOD(extack, |
1313 | "Requested priority is out of supported range"); | |
5a7e5bcb | 1314 | return -EOPNOTSUPP; |
bf07aa73 | 1315 | } |
e52c2802 | 1316 | |
14e6b038 EC |
1317 | if (flow_flag_test(flow, L3_TO_L2_DECAP)) { |
1318 | err = mlx5e_attach_decap(priv, flow, extack); | |
1319 | if (err) | |
1320 | return err; | |
1321 | } | |
1322 | ||
f493f155 | 1323 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) { |
8c4dc42b EB |
1324 | int mirred_ifindex; |
1325 | ||
f493f155 EB |
1326 | if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)) |
1327 | continue; | |
1328 | ||
7040632d | 1329 | mirred_ifindex = parse_attr->mirred_ifindex[out_index]; |
3c37745e | 1330 | out_dev = __dev_get_by_index(dev_net(priv->netdev), |
8c4dc42b | 1331 | mirred_ifindex); |
733d4f36 | 1332 | err = mlx5e_attach_encap(priv, flow, out_dev, out_index, |
0ad060ee RD |
1333 | extack, &encap_dev, &encap_valid); |
1334 | if (err) | |
5a7e5bcb | 1335 | return err; |
0ad060ee | 1336 | |
3c37745e OG |
1337 | out_priv = netdev_priv(encap_dev); |
1338 | rpriv = out_priv->ppriv; | |
1cc26d74 EB |
1339 | attr->dests[out_index].rep = rpriv->rep; |
1340 | attr->dests[out_index].mdev = out_priv->mdev; | |
3c37745e OG |
1341 | } |
1342 | ||
8b32580d | 1343 | err = mlx5_eswitch_add_vlan_action(esw, attr); |
c83954ab | 1344 | if (err) |
5a7e5bcb | 1345 | return err; |
adb4c123 | 1346 | |
d5a3c2b6 RD |
1347 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR && |
1348 | !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) { | |
1a9527bb | 1349 | err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); |
6ae4a6a5 | 1350 | dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts); |
c83954ab | 1351 | if (err) |
5a7e5bcb | 1352 | return err; |
d7e75a32 OG |
1353 | } |
1354 | ||
b8aee822 | 1355 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
f9392795 | 1356 | counter = mlx5_fc_create(attr->counter_dev, true); |
5a7e5bcb VB |
1357 | if (IS_ERR(counter)) |
1358 | return PTR_ERR(counter); | |
b8aee822 MB |
1359 | |
1360 | attr->counter = counter; | |
1361 | } | |
1362 | ||
0ad060ee RD |
1363 | /* we get here if one of the following takes place: |
1364 | * (1) there's no error | |
1365 | * (2) there's an encap action and we don't have valid neigh | |
3c37745e | 1366 | */ |
bc1d75fa | 1367 | if (!encap_valid) |
178f69b4 | 1368 | flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec); |
bc1d75fa | 1369 | else |
6d2a3ed0 | 1370 | flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr); |
c83954ab | 1371 | |
5a7e5bcb VB |
1372 | if (IS_ERR(flow->rule[0])) |
1373 | return PTR_ERR(flow->rule[0]); | |
226f2ca3 VB |
1374 | else |
1375 | flow_flag_set(flow, OFFLOADED); | |
5dbe906f PB |
1376 | |
1377 | return 0; | |
aa0cbbae | 1378 | } |
d85cdccb | 1379 | |
9272e3df YK |
1380 | static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow) |
1381 | { | |
1382 | struct mlx5_flow_spec *spec = &flow->esw_attr->parse_attr->spec; | |
1383 | void *headers_v = MLX5_ADDR_OF(fte_match_param, | |
1384 | spec->match_value, | |
1385 | misc_parameters_3); | |
1386 | u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3, | |
1387 | headers_v, | |
1388 | geneve_tlv_option_0_data); | |
1389 | ||
1390 | return !!geneve_tlv_opt_0_data; | |
1391 | } | |
1392 | ||
d85cdccb OG |
1393 | static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv, |
1394 | struct mlx5e_tc_flow *flow) | |
1395 | { | |
1396 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
d7e75a32 | 1397 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
f493f155 | 1398 | int out_index; |
d85cdccb | 1399 | |
0a7fcb78 PB |
1400 | mlx5e_put_flow_tunnel_id(flow); |
1401 | ||
226f2ca3 | 1402 | if (flow_flag_test(flow, NOT_READY)) { |
b4a23329 | 1403 | remove_unready_flow(flow); |
ef06c9ee RD |
1404 | kvfree(attr->parse_attr); |
1405 | return; | |
1406 | } | |
1407 | ||
226f2ca3 VB |
1408 | if (mlx5e_is_offloaded_flow(flow)) { |
1409 | if (flow_flag_test(flow, SLOW)) | |
178f69b4 | 1410 | mlx5e_tc_unoffload_from_slow_path(esw, flow); |
5dbe906f PB |
1411 | else |
1412 | mlx5e_tc_unoffload_fdb_rules(esw, flow, attr); | |
1413 | } | |
d85cdccb | 1414 | |
9272e3df YK |
1415 | if (mlx5_flow_has_geneve_opt(flow)) |
1416 | mlx5_geneve_tlv_option_del(priv->mdev->geneve); | |
1417 | ||
513f8f7f | 1418 | mlx5_eswitch_del_vlan_action(esw, attr); |
d85cdccb | 1419 | |
f493f155 | 1420 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) |
2a4b6526 | 1421 | if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) { |
8c4dc42b | 1422 | mlx5e_detach_encap(priv, flow, out_index); |
2a4b6526 VB |
1423 | kfree(attr->parse_attr->tun_info[out_index]); |
1424 | } | |
f493f155 | 1425 | kvfree(attr->parse_attr); |
d7e75a32 | 1426 | |
513f8f7f | 1427 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
1a9527bb | 1428 | mlx5e_detach_mod_hdr(priv, flow); |
b8aee822 MB |
1429 | |
1430 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) | |
f9392795 | 1431 | mlx5_fc_destroy(attr->counter_dev, attr->counter); |
14e6b038 EC |
1432 | |
1433 | if (flow_flag_test(flow, L3_TO_L2_DECAP)) | |
1434 | mlx5e_detach_decap(priv, flow); | |
d85cdccb OG |
1435 | } |
1436 | ||
232c0013 | 1437 | void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv, |
2a1f1768 VB |
1438 | struct mlx5e_encap_entry *e, |
1439 | struct list_head *flow_list) | |
232c0013 | 1440 | { |
3c37745e | 1441 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
178f69b4 | 1442 | struct mlx5_esw_flow_attr *esw_attr; |
6d2a3ed0 OG |
1443 | struct mlx5_flow_handle *rule; |
1444 | struct mlx5_flow_spec *spec; | |
232c0013 HHZ |
1445 | struct mlx5e_tc_flow *flow; |
1446 | int err; | |
1447 | ||
2b688ea5 MG |
1448 | e->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev, |
1449 | e->reformat_type, | |
1450 | e->encap_size, e->encap_header, | |
1451 | MLX5_FLOW_NAMESPACE_FDB); | |
1452 | if (IS_ERR(e->pkt_reformat)) { | |
1453 | mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %lu\n", | |
1454 | PTR_ERR(e->pkt_reformat)); | |
232c0013 HHZ |
1455 | return; |
1456 | } | |
1457 | e->flags |= MLX5_ENCAP_ENTRY_VALID; | |
f6dfb4c3 | 1458 | mlx5e_rep_queue_neigh_stats_work(priv); |
232c0013 | 1459 | |
2a1f1768 | 1460 | list_for_each_entry(flow, flow_list, tmp_list) { |
8c4dc42b EB |
1461 | bool all_flow_encaps_valid = true; |
1462 | int i; | |
1463 | ||
95435ad7 VB |
1464 | if (!mlx5e_is_offloaded_flow(flow)) |
1465 | continue; | |
3c37745e | 1466 | esw_attr = flow->esw_attr; |
6d2a3ed0 OG |
1467 | spec = &esw_attr->parse_attr->spec; |
1468 | ||
2b688ea5 | 1469 | esw_attr->dests[flow->tmp_efi_index].pkt_reformat = e->pkt_reformat; |
2a1f1768 | 1470 | esw_attr->dests[flow->tmp_efi_index].flags |= MLX5_ESW_DEST_ENCAP_VALID; |
8c4dc42b EB |
1471 | /* Flow can be associated with multiple encap entries. |
1472 | * Before offloading the flow verify that all of them have | |
1473 | * a valid neighbour. | |
1474 | */ | |
1475 | for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) { | |
1476 | if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)) | |
1477 | continue; | |
1478 | if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) { | |
1479 | all_flow_encaps_valid = false; | |
1480 | break; | |
1481 | } | |
1482 | } | |
1483 | /* Do not offload flows with unresolved neighbors */ | |
1484 | if (!all_flow_encaps_valid) | |
2a1f1768 | 1485 | continue; |
5dbe906f | 1486 | /* update from slow path rule to encap rule */ |
6d2a3ed0 OG |
1487 | rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr); |
1488 | if (IS_ERR(rule)) { | |
1489 | err = PTR_ERR(rule); | |
232c0013 HHZ |
1490 | mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n", |
1491 | err); | |
2a1f1768 | 1492 | continue; |
232c0013 | 1493 | } |
5dbe906f | 1494 | |
178f69b4 | 1495 | mlx5e_tc_unoffload_from_slow_path(esw, flow); |
6d2a3ed0 | 1496 | flow->rule[0] = rule; |
226f2ca3 VB |
1497 | /* was unset when slow path rule removed */ |
1498 | flow_flag_set(flow, OFFLOADED); | |
232c0013 HHZ |
1499 | } |
1500 | } | |
1501 | ||
1502 | void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv, | |
2a1f1768 VB |
1503 | struct mlx5e_encap_entry *e, |
1504 | struct list_head *flow_list) | |
232c0013 | 1505 | { |
3c37745e | 1506 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
5dbe906f PB |
1507 | struct mlx5_flow_handle *rule; |
1508 | struct mlx5_flow_spec *spec; | |
232c0013 | 1509 | struct mlx5e_tc_flow *flow; |
5dbe906f | 1510 | int err; |
232c0013 | 1511 | |
2a1f1768 | 1512 | list_for_each_entry(flow, flow_list, tmp_list) { |
95435ad7 VB |
1513 | if (!mlx5e_is_offloaded_flow(flow)) |
1514 | continue; | |
5dbe906f PB |
1515 | spec = &flow->esw_attr->parse_attr->spec; |
1516 | ||
1517 | /* update from encap rule to slow path rule */ | |
178f69b4 | 1518 | rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec); |
8c4dc42b | 1519 | /* mark the flow's encap dest as non-valid */ |
2a1f1768 | 1520 | flow->esw_attr->dests[flow->tmp_efi_index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID; |
5dbe906f PB |
1521 | |
1522 | if (IS_ERR(rule)) { | |
1523 | err = PTR_ERR(rule); | |
1524 | mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n", | |
1525 | err); | |
2a1f1768 | 1526 | continue; |
5dbe906f PB |
1527 | } |
1528 | ||
1529 | mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr); | |
5dbe906f | 1530 | flow->rule[0] = rule; |
226f2ca3 VB |
1531 | /* was unset when fast path rule removed */ |
1532 | flow_flag_set(flow, OFFLOADED); | |
232c0013 HHZ |
1533 | } |
1534 | ||
61c806da OG |
1535 | /* we know that the encap is valid */ |
1536 | e->flags &= ~MLX5_ENCAP_ENTRY_VALID; | |
2b688ea5 | 1537 | mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat); |
232c0013 HHZ |
1538 | } |
1539 | ||
b8aee822 MB |
1540 | static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow) |
1541 | { | |
226f2ca3 | 1542 | if (mlx5e_is_eswitch_flow(flow)) |
b8aee822 MB |
1543 | return flow->esw_attr->counter; |
1544 | else | |
1545 | return flow->nic_attr->counter; | |
1546 | } | |
1547 | ||
2a1f1768 VB |
1548 | /* Takes reference to all flows attached to encap and adds the flows to |
1549 | * flow_list using 'tmp_list' list_head in mlx5e_tc_flow. | |
1550 | */ | |
1551 | void mlx5e_take_all_encap_flows(struct mlx5e_encap_entry *e, struct list_head *flow_list) | |
1552 | { | |
1553 | struct encap_flow_item *efi; | |
1554 | struct mlx5e_tc_flow *flow; | |
1555 | ||
1556 | list_for_each_entry(efi, &e->flows, list) { | |
1557 | flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]); | |
1558 | if (IS_ERR(mlx5e_flow_get(flow))) | |
1559 | continue; | |
95435ad7 | 1560 | wait_for_completion(&flow->init_done); |
2a1f1768 VB |
1561 | |
1562 | flow->tmp_efi_index = efi->index; | |
1563 | list_add(&flow->tmp_list, flow_list); | |
1564 | } | |
1565 | } | |
1566 | ||
6a06c2f7 | 1567 | /* Iterate over tmp_list of flows attached to flow_list head. */ |
2a1f1768 | 1568 | void mlx5e_put_encap_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list) |
6a06c2f7 VB |
1569 | { |
1570 | struct mlx5e_tc_flow *flow, *tmp; | |
1571 | ||
1572 | list_for_each_entry_safe(flow, tmp, flow_list, tmp_list) | |
1573 | mlx5e_flow_put(priv, flow); | |
1574 | } | |
1575 | ||
ac0d9176 VB |
1576 | static struct mlx5e_encap_entry * |
1577 | mlx5e_get_next_valid_encap(struct mlx5e_neigh_hash_entry *nhe, | |
1578 | struct mlx5e_encap_entry *e) | |
1579 | { | |
1580 | struct mlx5e_encap_entry *next = NULL; | |
1581 | ||
1582 | retry: | |
1583 | rcu_read_lock(); | |
1584 | ||
1585 | /* find encap with non-zero reference counter value */ | |
1586 | for (next = e ? | |
1587 | list_next_or_null_rcu(&nhe->encap_list, | |
1588 | &e->encap_list, | |
1589 | struct mlx5e_encap_entry, | |
1590 | encap_list) : | |
1591 | list_first_or_null_rcu(&nhe->encap_list, | |
1592 | struct mlx5e_encap_entry, | |
1593 | encap_list); | |
1594 | next; | |
1595 | next = list_next_or_null_rcu(&nhe->encap_list, | |
1596 | &next->encap_list, | |
1597 | struct mlx5e_encap_entry, | |
1598 | encap_list)) | |
1599 | if (mlx5e_encap_take(next)) | |
1600 | break; | |
1601 | ||
1602 | rcu_read_unlock(); | |
1603 | ||
1604 | /* release starting encap */ | |
1605 | if (e) | |
1606 | mlx5e_encap_put(netdev_priv(e->out_dev), e); | |
1607 | if (!next) | |
1608 | return next; | |
1609 | ||
1610 | /* wait for encap to be fully initialized */ | |
1611 | wait_for_completion(&next->res_ready); | |
1612 | /* continue searching if encap entry is not in valid state after completion */ | |
1613 | if (!(next->flags & MLX5_ENCAP_ENTRY_VALID)) { | |
1614 | e = next; | |
1615 | goto retry; | |
1616 | } | |
1617 | ||
1618 | return next; | |
1619 | } | |
1620 | ||
f6dfb4c3 HHZ |
1621 | void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe) |
1622 | { | |
1623 | struct mlx5e_neigh *m_neigh = &nhe->m_neigh; | |
ac0d9176 | 1624 | struct mlx5e_encap_entry *e = NULL; |
f6dfb4c3 | 1625 | struct mlx5e_tc_flow *flow; |
f6dfb4c3 HHZ |
1626 | struct mlx5_fc *counter; |
1627 | struct neigh_table *tbl; | |
1628 | bool neigh_used = false; | |
1629 | struct neighbour *n; | |
90bb7692 | 1630 | u64 lastuse; |
f6dfb4c3 HHZ |
1631 | |
1632 | if (m_neigh->family == AF_INET) | |
1633 | tbl = &arp_tbl; | |
1634 | #if IS_ENABLED(CONFIG_IPV6) | |
1635 | else if (m_neigh->family == AF_INET6) | |
5cc3a8c6 | 1636 | tbl = ipv6_stub->nd_tbl; |
f6dfb4c3 HHZ |
1637 | #endif |
1638 | else | |
1639 | return; | |
1640 | ||
ac0d9176 VB |
1641 | /* mlx5e_get_next_valid_encap() releases previous encap before returning |
1642 | * next one. | |
1643 | */ | |
1644 | while ((e = mlx5e_get_next_valid_encap(nhe, e)) != NULL) { | |
6a06c2f7 | 1645 | struct mlx5e_priv *priv = netdev_priv(e->out_dev); |
5a7e5bcb | 1646 | struct encap_flow_item *efi, *tmp; |
6a06c2f7 VB |
1647 | struct mlx5_eswitch *esw; |
1648 | LIST_HEAD(flow_list); | |
948993f2 | 1649 | |
6a06c2f7 VB |
1650 | esw = priv->mdev->priv.eswitch; |
1651 | mutex_lock(&esw->offloads.encap_tbl_lock); | |
5a7e5bcb | 1652 | list_for_each_entry_safe(efi, tmp, &e->flows, list) { |
79baaec7 EB |
1653 | flow = container_of(efi, struct mlx5e_tc_flow, |
1654 | encaps[efi->index]); | |
5a7e5bcb VB |
1655 | if (IS_ERR(mlx5e_flow_get(flow))) |
1656 | continue; | |
6a06c2f7 | 1657 | list_add(&flow->tmp_list, &flow_list); |
5a7e5bcb | 1658 | |
226f2ca3 | 1659 | if (mlx5e_is_offloaded_flow(flow)) { |
b8aee822 | 1660 | counter = mlx5e_tc_get_counter(flow); |
90bb7692 | 1661 | lastuse = mlx5_fc_query_lastuse(counter); |
f6dfb4c3 HHZ |
1662 | if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) { |
1663 | neigh_used = true; | |
1664 | break; | |
1665 | } | |
1666 | } | |
1667 | } | |
6a06c2f7 | 1668 | mutex_unlock(&esw->offloads.encap_tbl_lock); |
948993f2 | 1669 | |
6a06c2f7 | 1670 | mlx5e_put_encap_flow_list(priv, &flow_list); |
ac0d9176 VB |
1671 | if (neigh_used) { |
1672 | /* release current encap before breaking the loop */ | |
6a06c2f7 | 1673 | mlx5e_encap_put(priv, e); |
e36d4810 | 1674 | break; |
ac0d9176 | 1675 | } |
f6dfb4c3 HHZ |
1676 | } |
1677 | ||
c786fe59 VB |
1678 | trace_mlx5e_tc_update_neigh_used_value(nhe, neigh_used); |
1679 | ||
f6dfb4c3 HHZ |
1680 | if (neigh_used) { |
1681 | nhe->reported_lastuse = jiffies; | |
1682 | ||
1683 | /* find the relevant neigh according to the cached device and | |
1684 | * dst ip pair | |
1685 | */ | |
1686 | n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev); | |
c7f7ba8d | 1687 | if (!n) |
f6dfb4c3 | 1688 | return; |
f6dfb4c3 HHZ |
1689 | |
1690 | neigh_event_send(n, NULL); | |
1691 | neigh_release(n); | |
1692 | } | |
1693 | } | |
1694 | ||
61086f39 | 1695 | static void mlx5e_encap_dealloc(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e) |
948993f2 | 1696 | { |
948993f2 | 1697 | WARN_ON(!list_empty(&e->flows)); |
948993f2 | 1698 | |
3c140dd5 VB |
1699 | if (e->compl_result > 0) { |
1700 | mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e); | |
1701 | ||
1702 | if (e->flags & MLX5_ENCAP_ENTRY_VALID) | |
2b688ea5 | 1703 | mlx5_packet_reformat_dealloc(priv->mdev, e->pkt_reformat); |
3c140dd5 | 1704 | } |
948993f2 | 1705 | |
2a4b6526 | 1706 | kfree(e->tun_info); |
948993f2 | 1707 | kfree(e->encap_header); |
ac0d9176 | 1708 | kfree_rcu(e, rcu); |
948993f2 VB |
1709 | } |
1710 | ||
14e6b038 EC |
1711 | static void mlx5e_decap_dealloc(struct mlx5e_priv *priv, |
1712 | struct mlx5e_decap_entry *d) | |
1713 | { | |
1714 | WARN_ON(!list_empty(&d->flows)); | |
1715 | ||
1716 | if (!d->compl_result) | |
1717 | mlx5_packet_reformat_dealloc(priv->mdev, d->pkt_reformat); | |
1718 | ||
1719 | kfree_rcu(d, rcu); | |
1720 | } | |
1721 | ||
61086f39 VB |
1722 | void mlx5e_encap_put(struct mlx5e_priv *priv, struct mlx5e_encap_entry *e) |
1723 | { | |
1724 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
1725 | ||
1726 | if (!refcount_dec_and_mutex_lock(&e->refcnt, &esw->offloads.encap_tbl_lock)) | |
1727 | return; | |
1728 | hash_del_rcu(&e->encap_hlist); | |
1729 | mutex_unlock(&esw->offloads.encap_tbl_lock); | |
1730 | ||
1731 | mlx5e_encap_dealloc(priv, e); | |
1732 | } | |
1733 | ||
14e6b038 EC |
1734 | static void mlx5e_decap_put(struct mlx5e_priv *priv, struct mlx5e_decap_entry *d) |
1735 | { | |
1736 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
1737 | ||
1738 | if (!refcount_dec_and_mutex_lock(&d->refcnt, &esw->offloads.decap_tbl_lock)) | |
1739 | return; | |
1740 | hash_del_rcu(&d->hlist); | |
1741 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
1742 | ||
1743 | mlx5e_decap_dealloc(priv, d); | |
1744 | } | |
1745 | ||
d85cdccb | 1746 | static void mlx5e_detach_encap(struct mlx5e_priv *priv, |
8c4dc42b | 1747 | struct mlx5e_tc_flow *flow, int out_index) |
d85cdccb | 1748 | { |
61086f39 VB |
1749 | struct mlx5e_encap_entry *e = flow->encaps[out_index].e; |
1750 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
1751 | ||
5a7e5bcb | 1752 | /* flow wasn't fully initialized */ |
61086f39 | 1753 | if (!e) |
5a7e5bcb VB |
1754 | return; |
1755 | ||
61086f39 | 1756 | mutex_lock(&esw->offloads.encap_tbl_lock); |
8c4dc42b | 1757 | list_del(&flow->encaps[out_index].list); |
948993f2 | 1758 | flow->encaps[out_index].e = NULL; |
61086f39 VB |
1759 | if (!refcount_dec_and_test(&e->refcnt)) { |
1760 | mutex_unlock(&esw->offloads.encap_tbl_lock); | |
1761 | return; | |
1762 | } | |
1763 | hash_del_rcu(&e->encap_hlist); | |
1764 | mutex_unlock(&esw->offloads.encap_tbl_lock); | |
1765 | ||
1766 | mlx5e_encap_dealloc(priv, e); | |
5067b602 RD |
1767 | } |
1768 | ||
14e6b038 EC |
1769 | static void mlx5e_detach_decap(struct mlx5e_priv *priv, |
1770 | struct mlx5e_tc_flow *flow) | |
1771 | { | |
1772 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
1773 | struct mlx5e_decap_entry *d = flow->decap_reformat; | |
1774 | ||
1775 | if (!d) | |
1776 | return; | |
1777 | ||
1778 | mutex_lock(&esw->offloads.decap_tbl_lock); | |
1779 | list_del(&flow->l3_to_l2_reformat); | |
1780 | flow->decap_reformat = NULL; | |
1781 | ||
1782 | if (!refcount_dec_and_test(&d->refcnt)) { | |
1783 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
1784 | return; | |
1785 | } | |
1786 | hash_del_rcu(&d->hlist); | |
1787 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
1788 | ||
1789 | mlx5e_decap_dealloc(priv, d); | |
1790 | } | |
1791 | ||
04de7dda RD |
1792 | static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) |
1793 | { | |
1794 | struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch; | |
1795 | ||
226f2ca3 VB |
1796 | if (!flow_flag_test(flow, ESWITCH) || |
1797 | !flow_flag_test(flow, DUP)) | |
04de7dda RD |
1798 | return; |
1799 | ||
1800 | mutex_lock(&esw->offloads.peer_mutex); | |
1801 | list_del(&flow->peer); | |
1802 | mutex_unlock(&esw->offloads.peer_mutex); | |
1803 | ||
226f2ca3 | 1804 | flow_flag_clear(flow, DUP); |
04de7dda | 1805 | |
eb252c3a RD |
1806 | if (refcount_dec_and_test(&flow->peer_flow->refcnt)) { |
1807 | mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow); | |
1808 | kfree(flow->peer_flow); | |
1809 | } | |
1810 | ||
04de7dda RD |
1811 | flow->peer_flow = NULL; |
1812 | } | |
1813 | ||
1814 | static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) | |
1815 | { | |
1816 | struct mlx5_core_dev *dev = flow->priv->mdev; | |
1817 | struct mlx5_devcom *devcom = dev->priv.devcom; | |
1818 | struct mlx5_eswitch *peer_esw; | |
1819 | ||
1820 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
1821 | if (!peer_esw) | |
1822 | return; | |
1823 | ||
1824 | __mlx5e_tc_del_fdb_peer_flow(flow); | |
1825 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
1826 | } | |
1827 | ||
e8f887ac | 1828 | static void mlx5e_tc_del_flow(struct mlx5e_priv *priv, |
961e8979 | 1829 | struct mlx5e_tc_flow *flow) |
e8f887ac | 1830 | { |
226f2ca3 | 1831 | if (mlx5e_is_eswitch_flow(flow)) { |
04de7dda | 1832 | mlx5e_tc_del_fdb_peer_flow(flow); |
d85cdccb | 1833 | mlx5e_tc_del_fdb_flow(priv, flow); |
04de7dda | 1834 | } else { |
d85cdccb | 1835 | mlx5e_tc_del_nic_flow(priv, flow); |
04de7dda | 1836 | } |
e8f887ac AV |
1837 | } |
1838 | ||
0a7fcb78 PB |
1839 | static int flow_has_tc_fwd_action(struct flow_cls_offload *f) |
1840 | { | |
1841 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); | |
1842 | struct flow_action *flow_action = &rule->action; | |
1843 | const struct flow_action_entry *act; | |
1844 | int i; | |
1845 | ||
1846 | flow_action_for_each(i, act, flow_action) { | |
1847 | switch (act->id) { | |
1848 | case FLOW_ACTION_GOTO: | |
1849 | return true; | |
1850 | default: | |
1851 | continue; | |
1852 | } | |
1853 | } | |
1854 | ||
1855 | return false; | |
1856 | } | |
bbd00f7e | 1857 | |
0a7fcb78 PB |
1858 | static int |
1859 | enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv, | |
1860 | struct flow_dissector_key_enc_opts *opts, | |
1861 | struct netlink_ext_ack *extack, | |
1862 | bool *dont_care) | |
1863 | { | |
1864 | struct geneve_opt *opt; | |
1865 | int off = 0; | |
1866 | ||
1867 | *dont_care = true; | |
1868 | ||
1869 | while (opts->len > off) { | |
1870 | opt = (struct geneve_opt *)&opts->data[off]; | |
1871 | ||
1872 | if (!(*dont_care) || opt->opt_class || opt->type || | |
1873 | memchr_inv(opt->opt_data, 0, opt->length * 4)) { | |
1874 | *dont_care = false; | |
1875 | ||
c51323ee | 1876 | if (opt->opt_class != htons(U16_MAX) || |
d7a42ad0 | 1877 | opt->type != U8_MAX) { |
0a7fcb78 PB |
1878 | NL_SET_ERR_MSG(extack, |
1879 | "Partial match of tunnel options in chain > 0 isn't supported"); | |
1880 | netdev_warn(priv->netdev, | |
1881 | "Partial match of tunnel options in chain > 0 isn't supported"); | |
1882 | return -EOPNOTSUPP; | |
1883 | } | |
1884 | } | |
1885 | ||
1886 | off += sizeof(struct geneve_opt) + opt->length * 4; | |
1887 | } | |
1888 | ||
1889 | return 0; | |
1890 | } | |
1891 | ||
1892 | #define COPY_DISSECTOR(rule, diss_key, dst)\ | |
1893 | ({ \ | |
1894 | struct flow_rule *__rule = (rule);\ | |
1895 | typeof(dst) __dst = dst;\ | |
1896 | \ | |
1897 | memcpy(__dst,\ | |
1898 | skb_flow_dissector_target(__rule->match.dissector,\ | |
1899 | diss_key,\ | |
1900 | __rule->match.key),\ | |
1901 | sizeof(*__dst));\ | |
1902 | }) | |
1903 | ||
1904 | static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv, | |
1905 | struct mlx5e_tc_flow *flow, | |
1906 | struct flow_cls_offload *f, | |
1907 | struct net_device *filter_dev) | |
bbd00f7e | 1908 | { |
f9e30088 | 1909 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); |
0a7fcb78 PB |
1910 | struct netlink_ext_ack *extack = f->common.extack; |
1911 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; | |
1912 | struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts; | |
1913 | struct flow_match_enc_opts enc_opts_match; | |
d7a42ad0 | 1914 | struct tunnel_match_enc_opts tun_enc_opts; |
0a7fcb78 PB |
1915 | struct mlx5_rep_uplink_priv *uplink_priv; |
1916 | struct mlx5e_rep_priv *uplink_rpriv; | |
1917 | struct tunnel_match_key tunnel_key; | |
1918 | bool enc_opts_is_dont_care = true; | |
1919 | u32 tun_id, enc_opts_id = 0; | |
1920 | struct mlx5_eswitch *esw; | |
1921 | u32 value, mask; | |
8f256622 | 1922 | int err; |
2e72eb43 | 1923 | |
0a7fcb78 PB |
1924 | esw = priv->mdev->priv.eswitch; |
1925 | uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); | |
1926 | uplink_priv = &uplink_rpriv->uplink_priv; | |
1927 | ||
1928 | memset(&tunnel_key, 0, sizeof(tunnel_key)); | |
1929 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL, | |
1930 | &tunnel_key.enc_control); | |
1931 | if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) | |
1932 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS, | |
1933 | &tunnel_key.enc_ipv4); | |
1934 | else | |
1935 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS, | |
1936 | &tunnel_key.enc_ipv6); | |
1937 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip); | |
1938 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS, | |
1939 | &tunnel_key.enc_tp); | |
1940 | COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID, | |
1941 | &tunnel_key.enc_key_id); | |
1942 | tunnel_key.filter_ifindex = filter_dev->ifindex; | |
1943 | ||
1944 | err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id); | |
1945 | if (err) | |
101f4de9 | 1946 | return err; |
bbd00f7e | 1947 | |
0a7fcb78 PB |
1948 | flow_rule_match_enc_opts(rule, &enc_opts_match); |
1949 | err = enc_opts_is_dont_care_or_full_match(priv, | |
1950 | enc_opts_match.mask, | |
1951 | extack, | |
1952 | &enc_opts_is_dont_care); | |
1953 | if (err) | |
1954 | goto err_enc_opts; | |
fe1587a7 | 1955 | |
0a7fcb78 | 1956 | if (!enc_opts_is_dont_care) { |
d7a42ad0 RD |
1957 | memset(&tun_enc_opts, 0, sizeof(tun_enc_opts)); |
1958 | memcpy(&tun_enc_opts.key, enc_opts_match.key, | |
1959 | sizeof(*enc_opts_match.key)); | |
1960 | memcpy(&tun_enc_opts.mask, enc_opts_match.mask, | |
1961 | sizeof(*enc_opts_match.mask)); | |
1962 | ||
0a7fcb78 | 1963 | err = mapping_add(uplink_priv->tunnel_enc_opts_mapping, |
d7a42ad0 | 1964 | &tun_enc_opts, &enc_opts_id); |
0a7fcb78 PB |
1965 | if (err) |
1966 | goto err_enc_opts; | |
1967 | } | |
fe1587a7 | 1968 | |
0a7fcb78 PB |
1969 | value = tun_id << ENC_OPTS_BITS | enc_opts_id; |
1970 | mask = enc_opts_id ? TUNNEL_ID_MASK : | |
1971 | (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK); | |
fe1587a7 | 1972 | |
0a7fcb78 PB |
1973 | if (attr->chain) { |
1974 | mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec, | |
1975 | TUNNEL_TO_REG, value, mask); | |
1976 | } else { | |
1977 | mod_hdr_acts = &attr->parse_attr->mod_hdr_acts; | |
1978 | err = mlx5e_tc_match_to_reg_set(priv->mdev, | |
1979 | mod_hdr_acts, | |
1980 | TUNNEL_TO_REG, value); | |
1981 | if (err) | |
1982 | goto err_set; | |
fe1587a7 | 1983 | |
0a7fcb78 | 1984 | attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
2e72eb43 | 1985 | } |
bbd00f7e | 1986 | |
0a7fcb78 PB |
1987 | flow->tunnel_id = value; |
1988 | return 0; | |
bcef735c | 1989 | |
0a7fcb78 PB |
1990 | err_set: |
1991 | if (enc_opts_id) | |
1992 | mapping_remove(uplink_priv->tunnel_enc_opts_mapping, | |
1993 | enc_opts_id); | |
1994 | err_enc_opts: | |
1995 | mapping_remove(uplink_priv->tunnel_mapping, tun_id); | |
1996 | return err; | |
1997 | } | |
bcef735c | 1998 | |
0a7fcb78 PB |
1999 | static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow) |
2000 | { | |
2001 | u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK; | |
2002 | u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS; | |
2003 | struct mlx5_rep_uplink_priv *uplink_priv; | |
2004 | struct mlx5e_rep_priv *uplink_rpriv; | |
2005 | struct mlx5_eswitch *esw; | |
bcef735c | 2006 | |
0a7fcb78 PB |
2007 | esw = flow->priv->mdev->priv.eswitch; |
2008 | uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); | |
2009 | uplink_priv = &uplink_rpriv->uplink_priv; | |
2010 | ||
2011 | if (tun_id) | |
2012 | mapping_remove(uplink_priv->tunnel_mapping, tun_id); | |
2013 | if (enc_opts_id) | |
2014 | mapping_remove(uplink_priv->tunnel_enc_opts_mapping, | |
2015 | enc_opts_id); | |
2016 | } | |
e98bedf5 | 2017 | |
4c3844d9 PB |
2018 | u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow) |
2019 | { | |
2020 | return flow->tunnel_id; | |
2021 | } | |
2022 | ||
fca53304 EB |
2023 | void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev, |
2024 | struct flow_match_basic *match, bool outer, | |
2025 | void *headers_c, void *headers_v) | |
2026 | { | |
2027 | bool ip_version_cap; | |
2028 | ||
2029 | ip_version_cap = outer ? | |
2030 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, | |
2031 | ft_field_support.outer_ip_version) : | |
2032 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, | |
2033 | ft_field_support.inner_ip_version); | |
2034 | ||
2035 | if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) && | |
2036 | (match->key->n_proto == htons(ETH_P_IP) || | |
2037 | match->key->n_proto == htons(ETH_P_IPV6))) { | |
2038 | MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version); | |
2039 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, | |
2040 | match->key->n_proto == htons(ETH_P_IP) ? 4 : 6); | |
2041 | } else { | |
2042 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype, | |
2043 | ntohs(match->mask->n_proto)); | |
2044 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, | |
2045 | ntohs(match->key->n_proto)); | |
2046 | } | |
4a5d5d73 EB |
2047 | } |
2048 | ||
bbd00f7e | 2049 | static int parse_tunnel_attr(struct mlx5e_priv *priv, |
0a7fcb78 | 2050 | struct mlx5e_tc_flow *flow, |
bbd00f7e | 2051 | struct mlx5_flow_spec *spec, |
f9e30088 | 2052 | struct flow_cls_offload *f, |
0a7fcb78 PB |
2053 | struct net_device *filter_dev, |
2054 | u8 *match_level, | |
2055 | bool *match_inner) | |
bbd00f7e | 2056 | { |
0a7fcb78 | 2057 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
e98bedf5 | 2058 | struct netlink_ext_ack *extack = f->common.extack; |
0a7fcb78 | 2059 | bool needs_mapping, sets_mapping; |
8f256622 | 2060 | int err; |
2e72eb43 | 2061 | |
0a7fcb78 PB |
2062 | if (!mlx5e_is_eswitch_flow(flow)) |
2063 | return -EOPNOTSUPP; | |
2064 | ||
2065 | needs_mapping = !!flow->esw_attr->chain; | |
2066 | sets_mapping = !flow->esw_attr->chain && flow_has_tc_fwd_action(f); | |
2067 | *match_inner = !needs_mapping; | |
2068 | ||
2069 | if ((needs_mapping || sets_mapping) && | |
636bb968 | 2070 | !mlx5_eswitch_reg_c1_loopback_enabled(esw)) { |
0a7fcb78 | 2071 | NL_SET_ERR_MSG(extack, |
636bb968 | 2072 | "Chains on tunnel devices isn't supported without register loopback support"); |
0a7fcb78 | 2073 | netdev_warn(priv->netdev, |
636bb968 | 2074 | "Chains on tunnel devices isn't supported without register loopback support"); |
0a7fcb78 | 2075 | return -EOPNOTSUPP; |
bbd00f7e HHZ |
2076 | } |
2077 | ||
0a7fcb78 PB |
2078 | if (!flow->esw_attr->chain) { |
2079 | err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f, | |
2080 | match_level); | |
2081 | if (err) { | |
e98bedf5 | 2082 | NL_SET_ERR_MSG_MOD(extack, |
0a7fcb78 PB |
2083 | "Failed to parse tunnel attributes"); |
2084 | netdev_warn(priv->netdev, | |
2085 | "Failed to parse tunnel attributes"); | |
2086 | return err; | |
e98bedf5 EB |
2087 | } |
2088 | ||
14e6b038 EC |
2089 | /* With mpls over udp we decapsulate using packet reformat |
2090 | * object | |
2091 | */ | |
2092 | if (!netif_is_bareudp(filter_dev)) | |
2093 | flow->esw_attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; | |
bcef735c OG |
2094 | } |
2095 | ||
0a7fcb78 PB |
2096 | if (!needs_mapping && !sets_mapping) |
2097 | return 0; | |
bbd00f7e | 2098 | |
0a7fcb78 | 2099 | return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev); |
bbd00f7e | 2100 | } |
bbd00f7e | 2101 | |
0a7fcb78 | 2102 | static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec) |
8377629e | 2103 | { |
0a7fcb78 PB |
2104 | return MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
2105 | inner_headers); | |
bbd00f7e HHZ |
2106 | } |
2107 | ||
0a7fcb78 | 2108 | static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec) |
8377629e | 2109 | { |
0a7fcb78 PB |
2110 | return MLX5_ADDR_OF(fte_match_param, spec->match_value, |
2111 | inner_headers); | |
2112 | } | |
2113 | ||
2114 | static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec) | |
2115 | { | |
2116 | return MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
2117 | outer_headers); | |
2118 | } | |
2119 | ||
2120 | static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec) | |
2121 | { | |
2122 | return MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
2123 | outer_headers); | |
8377629e EB |
2124 | } |
2125 | ||
2126 | static void *get_match_headers_value(u32 flags, | |
2127 | struct mlx5_flow_spec *spec) | |
2128 | { | |
2129 | return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? | |
0a7fcb78 PB |
2130 | get_match_inner_headers_value(spec) : |
2131 | get_match_outer_headers_value(spec); | |
2132 | } | |
2133 | ||
2134 | static void *get_match_headers_criteria(u32 flags, | |
2135 | struct mlx5_flow_spec *spec) | |
2136 | { | |
2137 | return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? | |
2138 | get_match_inner_headers_criteria(spec) : | |
2139 | get_match_outer_headers_criteria(spec); | |
8377629e EB |
2140 | } |
2141 | ||
6d65bc64 | 2142 | static int mlx5e_flower_parse_meta(struct net_device *filter_dev, |
2143 | struct flow_cls_offload *f) | |
2144 | { | |
2145 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); | |
2146 | struct netlink_ext_ack *extack = f->common.extack; | |
2147 | struct net_device *ingress_dev; | |
2148 | struct flow_match_meta match; | |
2149 | ||
2150 | if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META)) | |
2151 | return 0; | |
2152 | ||
2153 | flow_rule_match_meta(rule, &match); | |
2154 | if (match.mask->ingress_ifindex != 0xFFFFFFFF) { | |
2155 | NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask"); | |
a683012a | 2156 | return -EOPNOTSUPP; |
6d65bc64 | 2157 | } |
2158 | ||
2159 | ingress_dev = __dev_get_by_index(dev_net(filter_dev), | |
2160 | match.key->ingress_ifindex); | |
2161 | if (!ingress_dev) { | |
2162 | NL_SET_ERR_MSG_MOD(extack, | |
2163 | "Can't find the ingress port to match on"); | |
a683012a | 2164 | return -ENOENT; |
6d65bc64 | 2165 | } |
2166 | ||
2167 | if (ingress_dev != filter_dev) { | |
2168 | NL_SET_ERR_MSG_MOD(extack, | |
2169 | "Can't match on the ingress filter port"); | |
a683012a | 2170 | return -EOPNOTSUPP; |
6d65bc64 | 2171 | } |
2172 | ||
2173 | return 0; | |
2174 | } | |
2175 | ||
72046a91 EC |
2176 | static bool skip_key_basic(struct net_device *filter_dev, |
2177 | struct flow_cls_offload *f) | |
2178 | { | |
2179 | /* When doing mpls over udp decap, the user needs to provide | |
2180 | * MPLS_UC as the protocol in order to be able to match on mpls | |
2181 | * label fields. However, the actual ethertype is IP so we want to | |
2182 | * avoid matching on this, otherwise we'll fail the match. | |
2183 | */ | |
2184 | if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0) | |
2185 | return true; | |
2186 | ||
2187 | return false; | |
2188 | } | |
2189 | ||
de0af0bf | 2190 | static int __parse_cls_flower(struct mlx5e_priv *priv, |
0a7fcb78 | 2191 | struct mlx5e_tc_flow *flow, |
de0af0bf | 2192 | struct mlx5_flow_spec *spec, |
f9e30088 | 2193 | struct flow_cls_offload *f, |
54c177ca | 2194 | struct net_device *filter_dev, |
93b3586e | 2195 | u8 *inner_match_level, u8 *outer_match_level) |
e3a2b7ed | 2196 | { |
e98bedf5 | 2197 | struct netlink_ext_ack *extack = f->common.extack; |
c5bb1730 MG |
2198 | void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
2199 | outer_headers); | |
2200 | void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
2201 | outer_headers); | |
699e96dd JL |
2202 | void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
2203 | misc_parameters); | |
2204 | void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
2205 | misc_parameters); | |
f9e30088 | 2206 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); |
8f256622 | 2207 | struct flow_dissector *dissector = rule->match.dissector; |
e3a2b7ed AV |
2208 | u16 addr_type = 0; |
2209 | u8 ip_proto = 0; | |
93b3586e | 2210 | u8 *match_level; |
6d65bc64 | 2211 | int err; |
e3a2b7ed | 2212 | |
93b3586e | 2213 | match_level = outer_match_level; |
de0af0bf | 2214 | |
8f256622 | 2215 | if (dissector->used_keys & |
3d144578 VB |
2216 | ~(BIT(FLOW_DISSECTOR_KEY_META) | |
2217 | BIT(FLOW_DISSECTOR_KEY_CONTROL) | | |
e3a2b7ed AV |
2218 | BIT(FLOW_DISSECTOR_KEY_BASIC) | |
2219 | BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | | |
095b6cfd | 2220 | BIT(FLOW_DISSECTOR_KEY_VLAN) | |
699e96dd | 2221 | BIT(FLOW_DISSECTOR_KEY_CVLAN) | |
e3a2b7ed AV |
2222 | BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | |
2223 | BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | | |
bbd00f7e HHZ |
2224 | BIT(FLOW_DISSECTOR_KEY_PORTS) | |
2225 | BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | | |
2226 | BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | | |
2227 | BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | | |
2228 | BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | | |
e77834ec | 2229 | BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | |
fd7da28b | 2230 | BIT(FLOW_DISSECTOR_KEY_TCP) | |
bcef735c | 2231 | BIT(FLOW_DISSECTOR_KEY_IP) | |
4c3844d9 | 2232 | BIT(FLOW_DISSECTOR_KEY_CT) | |
9272e3df | 2233 | BIT(FLOW_DISSECTOR_KEY_ENC_IP) | |
72046a91 EC |
2234 | BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) | |
2235 | BIT(FLOW_DISSECTOR_KEY_MPLS))) { | |
e98bedf5 | 2236 | NL_SET_ERR_MSG_MOD(extack, "Unsupported key"); |
e3a2b7ed | 2237 | netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n", |
8f256622 | 2238 | dissector->used_keys); |
e3a2b7ed AV |
2239 | return -EOPNOTSUPP; |
2240 | } | |
2241 | ||
075973c7 | 2242 | if (mlx5e_get_tc_tun(filter_dev)) { |
0a7fcb78 | 2243 | bool match_inner = false; |
bbd00f7e | 2244 | |
0a7fcb78 PB |
2245 | err = parse_tunnel_attr(priv, flow, spec, f, filter_dev, |
2246 | outer_match_level, &match_inner); | |
2247 | if (err) | |
2248 | return err; | |
2249 | ||
2250 | if (match_inner) { | |
2251 | /* header pointers should point to the inner headers | |
2252 | * if the packet was decapsulated already. | |
2253 | * outer headers are set by parse_tunnel_attr. | |
2254 | */ | |
2255 | match_level = inner_match_level; | |
2256 | headers_c = get_match_inner_headers_criteria(spec); | |
2257 | headers_v = get_match_inner_headers_value(spec); | |
2258 | } | |
bbd00f7e HHZ |
2259 | } |
2260 | ||
6d65bc64 | 2261 | err = mlx5e_flower_parse_meta(filter_dev, f); |
2262 | if (err) | |
2263 | return err; | |
2264 | ||
72046a91 EC |
2265 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) && |
2266 | !skip_key_basic(filter_dev, f)) { | |
8f256622 PNA |
2267 | struct flow_match_basic match; |
2268 | ||
2269 | flow_rule_match_basic(rule, &match); | |
fca53304 EB |
2270 | mlx5e_tc_set_ethertype(priv->mdev, &match, |
2271 | match_level == outer_match_level, | |
2272 | headers_c, headers_v); | |
e3a2b7ed | 2273 | |
8f256622 | 2274 | if (match.mask->n_proto) |
d708f902 | 2275 | *match_level = MLX5_MATCH_L2; |
e3a2b7ed | 2276 | } |
35a605db EB |
2277 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) || |
2278 | is_vlan_dev(filter_dev)) { | |
2279 | struct flow_dissector_key_vlan filter_dev_mask; | |
2280 | struct flow_dissector_key_vlan filter_dev_key; | |
8f256622 PNA |
2281 | struct flow_match_vlan match; |
2282 | ||
35a605db EB |
2283 | if (is_vlan_dev(filter_dev)) { |
2284 | match.key = &filter_dev_key; | |
2285 | match.key->vlan_id = vlan_dev_vlan_id(filter_dev); | |
2286 | match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev); | |
2287 | match.key->vlan_priority = 0; | |
2288 | match.mask = &filter_dev_mask; | |
2289 | memset(match.mask, 0xff, sizeof(*match.mask)); | |
2290 | match.mask->vlan_priority = 0; | |
2291 | } else { | |
2292 | flow_rule_match_vlan(rule, &match); | |
2293 | } | |
8f256622 PNA |
2294 | if (match.mask->vlan_id || |
2295 | match.mask->vlan_priority || | |
2296 | match.mask->vlan_tpid) { | |
2297 | if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { | |
699e96dd JL |
2298 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
2299 | svlan_tag, 1); | |
2300 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2301 | svlan_tag, 1); | |
2302 | } else { | |
2303 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
2304 | cvlan_tag, 1); | |
2305 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
2306 | cvlan_tag, 1); | |
2307 | } | |
095b6cfd | 2308 | |
8f256622 PNA |
2309 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, |
2310 | match.mask->vlan_id); | |
2311 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, | |
2312 | match.key->vlan_id); | |
358d79a4 | 2313 | |
8f256622 PNA |
2314 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, |
2315 | match.mask->vlan_priority); | |
2316 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, | |
2317 | match.key->vlan_priority); | |
54782900 | 2318 | |
d708f902 | 2319 | *match_level = MLX5_MATCH_L2; |
54782900 | 2320 | } |
d3a80bb5 | 2321 | } else if (*match_level != MLX5_MATCH_NONE) { |
fc603294 MB |
2322 | /* cvlan_tag enabled in match criteria and |
2323 | * disabled in match value means both S & C tags | |
2324 | * don't exist (untagged of both) | |
2325 | */ | |
cee26487 | 2326 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1); |
d3a80bb5 | 2327 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
2328 | } |
2329 | ||
8f256622 PNA |
2330 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) { |
2331 | struct flow_match_vlan match; | |
2332 | ||
12d5cbf8 | 2333 | flow_rule_match_cvlan(rule, &match); |
8f256622 PNA |
2334 | if (match.mask->vlan_id || |
2335 | match.mask->vlan_priority || | |
2336 | match.mask->vlan_tpid) { | |
2337 | if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { | |
699e96dd JL |
2338 | MLX5_SET(fte_match_set_misc, misc_c, |
2339 | outer_second_svlan_tag, 1); | |
2340 | MLX5_SET(fte_match_set_misc, misc_v, | |
2341 | outer_second_svlan_tag, 1); | |
2342 | } else { | |
2343 | MLX5_SET(fte_match_set_misc, misc_c, | |
2344 | outer_second_cvlan_tag, 1); | |
2345 | MLX5_SET(fte_match_set_misc, misc_v, | |
2346 | outer_second_cvlan_tag, 1); | |
2347 | } | |
2348 | ||
2349 | MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid, | |
8f256622 | 2350 | match.mask->vlan_id); |
699e96dd | 2351 | MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid, |
8f256622 | 2352 | match.key->vlan_id); |
699e96dd | 2353 | MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio, |
8f256622 | 2354 | match.mask->vlan_priority); |
699e96dd | 2355 | MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio, |
8f256622 | 2356 | match.key->vlan_priority); |
699e96dd JL |
2357 | |
2358 | *match_level = MLX5_MATCH_L2; | |
2359 | } | |
2360 | } | |
2361 | ||
8f256622 PNA |
2362 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
2363 | struct flow_match_eth_addrs match; | |
54782900 | 2364 | |
8f256622 | 2365 | flow_rule_match_eth_addrs(rule, &match); |
d3a80bb5 OG |
2366 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
2367 | dmac_47_16), | |
8f256622 | 2368 | match.mask->dst); |
d3a80bb5 OG |
2369 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2370 | dmac_47_16), | |
8f256622 | 2371 | match.key->dst); |
d3a80bb5 OG |
2372 | |
2373 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, | |
2374 | smac_47_16), | |
8f256622 | 2375 | match.mask->src); |
d3a80bb5 OG |
2376 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2377 | smac_47_16), | |
8f256622 | 2378 | match.key->src); |
d3a80bb5 | 2379 | |
8f256622 PNA |
2380 | if (!is_zero_ether_addr(match.mask->src) || |
2381 | !is_zero_ether_addr(match.mask->dst)) | |
d708f902 | 2382 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
2383 | } |
2384 | ||
8f256622 PNA |
2385 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { |
2386 | struct flow_match_control match; | |
54782900 | 2387 | |
8f256622 PNA |
2388 | flow_rule_match_control(rule, &match); |
2389 | addr_type = match.key->addr_type; | |
54782900 OG |
2390 | |
2391 | /* the HW doesn't support frag first/later */ | |
8f256622 | 2392 | if (match.mask->flags & FLOW_DIS_FIRST_FRAG) |
54782900 OG |
2393 | return -EOPNOTSUPP; |
2394 | ||
8f256622 | 2395 | if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) { |
54782900 OG |
2396 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1); |
2397 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, | |
8f256622 | 2398 | match.key->flags & FLOW_DIS_IS_FRAGMENT); |
54782900 OG |
2399 | |
2400 | /* the HW doesn't need L3 inline to match on frag=no */ | |
8f256622 | 2401 | if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT)) |
83621b7d | 2402 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
2403 | /* *** L2 attributes parsing up to here *** */ |
2404 | else | |
83621b7d | 2405 | *match_level = MLX5_MATCH_L3; |
095b6cfd OG |
2406 | } |
2407 | } | |
2408 | ||
8f256622 PNA |
2409 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { |
2410 | struct flow_match_basic match; | |
2411 | ||
2412 | flow_rule_match_basic(rule, &match); | |
2413 | ip_proto = match.key->ip_proto; | |
54782900 OG |
2414 | |
2415 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, | |
8f256622 | 2416 | match.mask->ip_proto); |
54782900 | 2417 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, |
8f256622 | 2418 | match.key->ip_proto); |
54782900 | 2419 | |
8f256622 | 2420 | if (match.mask->ip_proto) |
d708f902 | 2421 | *match_level = MLX5_MATCH_L3; |
54782900 OG |
2422 | } |
2423 | ||
e3a2b7ed | 2424 | if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { |
8f256622 | 2425 | struct flow_match_ipv4_addrs match; |
e3a2b7ed | 2426 | |
8f256622 | 2427 | flow_rule_match_ipv4_addrs(rule, &match); |
e3a2b7ed AV |
2428 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
2429 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
8f256622 | 2430 | &match.mask->src, sizeof(match.mask->src)); |
e3a2b7ed AV |
2431 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2432 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
8f256622 | 2433 | &match.key->src, sizeof(match.key->src)); |
e3a2b7ed AV |
2434 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
2435 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
8f256622 | 2436 | &match.mask->dst, sizeof(match.mask->dst)); |
e3a2b7ed AV |
2437 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2438 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
8f256622 | 2439 | &match.key->dst, sizeof(match.key->dst)); |
de0af0bf | 2440 | |
8f256622 | 2441 | if (match.mask->src || match.mask->dst) |
d708f902 | 2442 | *match_level = MLX5_MATCH_L3; |
e3a2b7ed AV |
2443 | } |
2444 | ||
2445 | if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { | |
8f256622 | 2446 | struct flow_match_ipv6_addrs match; |
e3a2b7ed | 2447 | |
8f256622 | 2448 | flow_rule_match_ipv6_addrs(rule, &match); |
e3a2b7ed AV |
2449 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
2450 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 2451 | &match.mask->src, sizeof(match.mask->src)); |
e3a2b7ed AV |
2452 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2453 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 2454 | &match.key->src, sizeof(match.key->src)); |
e3a2b7ed AV |
2455 | |
2456 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, | |
2457 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 2458 | &match.mask->dst, sizeof(match.mask->dst)); |
e3a2b7ed AV |
2459 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
2460 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 2461 | &match.key->dst, sizeof(match.key->dst)); |
de0af0bf | 2462 | |
8f256622 PNA |
2463 | if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY || |
2464 | ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY) | |
d708f902 | 2465 | *match_level = MLX5_MATCH_L3; |
e3a2b7ed AV |
2466 | } |
2467 | ||
8f256622 PNA |
2468 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) { |
2469 | struct flow_match_ip match; | |
1f97a526 | 2470 | |
8f256622 PNA |
2471 | flow_rule_match_ip(rule, &match); |
2472 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, | |
2473 | match.mask->tos & 0x3); | |
2474 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, | |
2475 | match.key->tos & 0x3); | |
1f97a526 | 2476 | |
8f256622 PNA |
2477 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, |
2478 | match.mask->tos >> 2); | |
2479 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, | |
2480 | match.key->tos >> 2); | |
1f97a526 | 2481 | |
8f256622 PNA |
2482 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, |
2483 | match.mask->ttl); | |
2484 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, | |
2485 | match.key->ttl); | |
1f97a526 | 2486 | |
8f256622 | 2487 | if (match.mask->ttl && |
a8ade55f | 2488 | !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, |
e98bedf5 EB |
2489 | ft_field_support.outer_ipv4_ttl)) { |
2490 | NL_SET_ERR_MSG_MOD(extack, | |
2491 | "Matching on TTL is not supported"); | |
1f97a526 | 2492 | return -EOPNOTSUPP; |
e98bedf5 | 2493 | } |
a8ade55f | 2494 | |
8f256622 | 2495 | if (match.mask->tos || match.mask->ttl) |
d708f902 | 2496 | *match_level = MLX5_MATCH_L3; |
1f97a526 OG |
2497 | } |
2498 | ||
54782900 OG |
2499 | /* *** L3 attributes parsing up to here *** */ |
2500 | ||
8f256622 PNA |
2501 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { |
2502 | struct flow_match_ports match; | |
2503 | ||
2504 | flow_rule_match_ports(rule, &match); | |
e3a2b7ed AV |
2505 | switch (ip_proto) { |
2506 | case IPPROTO_TCP: | |
2507 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 2508 | tcp_sport, ntohs(match.mask->src)); |
e3a2b7ed | 2509 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 2510 | tcp_sport, ntohs(match.key->src)); |
e3a2b7ed AV |
2511 | |
2512 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 2513 | tcp_dport, ntohs(match.mask->dst)); |
e3a2b7ed | 2514 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 2515 | tcp_dport, ntohs(match.key->dst)); |
e3a2b7ed AV |
2516 | break; |
2517 | ||
2518 | case IPPROTO_UDP: | |
2519 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 2520 | udp_sport, ntohs(match.mask->src)); |
e3a2b7ed | 2521 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 2522 | udp_sport, ntohs(match.key->src)); |
e3a2b7ed AV |
2523 | |
2524 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 2525 | udp_dport, ntohs(match.mask->dst)); |
e3a2b7ed | 2526 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 2527 | udp_dport, ntohs(match.key->dst)); |
e3a2b7ed AV |
2528 | break; |
2529 | default: | |
e98bedf5 EB |
2530 | NL_SET_ERR_MSG_MOD(extack, |
2531 | "Only UDP and TCP transports are supported for L4 matching"); | |
e3a2b7ed AV |
2532 | netdev_err(priv->netdev, |
2533 | "Only UDP and TCP transport are supported\n"); | |
2534 | return -EINVAL; | |
2535 | } | |
de0af0bf | 2536 | |
8f256622 | 2537 | if (match.mask->src || match.mask->dst) |
d708f902 | 2538 | *match_level = MLX5_MATCH_L4; |
e3a2b7ed AV |
2539 | } |
2540 | ||
8f256622 PNA |
2541 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) { |
2542 | struct flow_match_tcp match; | |
e77834ec | 2543 | |
8f256622 | 2544 | flow_rule_match_tcp(rule, &match); |
e77834ec | 2545 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags, |
8f256622 | 2546 | ntohs(match.mask->flags)); |
e77834ec | 2547 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags, |
8f256622 | 2548 | ntohs(match.key->flags)); |
e77834ec | 2549 | |
8f256622 | 2550 | if (match.mask->flags) |
d708f902 | 2551 | *match_level = MLX5_MATCH_L4; |
e77834ec OG |
2552 | } |
2553 | ||
e3a2b7ed AV |
2554 | return 0; |
2555 | } | |
2556 | ||
de0af0bf | 2557 | static int parse_cls_flower(struct mlx5e_priv *priv, |
65ba8fb7 | 2558 | struct mlx5e_tc_flow *flow, |
de0af0bf | 2559 | struct mlx5_flow_spec *spec, |
f9e30088 | 2560 | struct flow_cls_offload *f, |
54c177ca | 2561 | struct net_device *filter_dev) |
de0af0bf | 2562 | { |
93b3586e | 2563 | u8 inner_match_level, outer_match_level, non_tunnel_match_level; |
e98bedf5 | 2564 | struct netlink_ext_ack *extack = f->common.extack; |
de0af0bf RD |
2565 | struct mlx5_core_dev *dev = priv->mdev; |
2566 | struct mlx5_eswitch *esw = dev->priv.eswitch; | |
1d447a39 SM |
2567 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
2568 | struct mlx5_eswitch_rep *rep; | |
226f2ca3 | 2569 | bool is_eswitch_flow; |
de0af0bf RD |
2570 | int err; |
2571 | ||
93b3586e HN |
2572 | inner_match_level = MLX5_MATCH_NONE; |
2573 | outer_match_level = MLX5_MATCH_NONE; | |
2574 | ||
0a7fcb78 PB |
2575 | err = __parse_cls_flower(priv, flow, spec, f, filter_dev, |
2576 | &inner_match_level, &outer_match_level); | |
93b3586e HN |
2577 | non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ? |
2578 | outer_match_level : inner_match_level; | |
de0af0bf | 2579 | |
226f2ca3 VB |
2580 | is_eswitch_flow = mlx5e_is_eswitch_flow(flow); |
2581 | if (!err && is_eswitch_flow) { | |
1d447a39 | 2582 | rep = rpriv->rep; |
b05af6aa | 2583 | if (rep->vport != MLX5_VPORT_UPLINK && |
1d447a39 | 2584 | (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE && |
93b3586e | 2585 | esw->offloads.inline_mode < non_tunnel_match_level)) { |
e98bedf5 EB |
2586 | NL_SET_ERR_MSG_MOD(extack, |
2587 | "Flow is not offloaded due to min inline setting"); | |
de0af0bf RD |
2588 | netdev_warn(priv->netdev, |
2589 | "Flow is not offloaded due to min inline setting, required %d actual %d\n", | |
93b3586e | 2590 | non_tunnel_match_level, esw->offloads.inline_mode); |
de0af0bf RD |
2591 | return -EOPNOTSUPP; |
2592 | } | |
2593 | } | |
2594 | ||
226f2ca3 | 2595 | if (is_eswitch_flow) { |
93b3586e HN |
2596 | flow->esw_attr->inner_match_level = inner_match_level; |
2597 | flow->esw_attr->outer_match_level = outer_match_level; | |
6363651d | 2598 | } else { |
93b3586e | 2599 | flow->nic_attr->match_level = non_tunnel_match_level; |
6363651d | 2600 | } |
38aa51c1 | 2601 | |
de0af0bf RD |
2602 | return err; |
2603 | } | |
2604 | ||
d79b6df6 OG |
2605 | struct pedit_headers { |
2606 | struct ethhdr eth; | |
0eb69bb9 | 2607 | struct vlan_hdr vlan; |
d79b6df6 OG |
2608 | struct iphdr ip4; |
2609 | struct ipv6hdr ip6; | |
2610 | struct tcphdr tcp; | |
2611 | struct udphdr udp; | |
2612 | }; | |
2613 | ||
c500c86b PNA |
2614 | struct pedit_headers_action { |
2615 | struct pedit_headers vals; | |
2616 | struct pedit_headers masks; | |
2617 | u32 pedits; | |
2618 | }; | |
2619 | ||
d79b6df6 | 2620 | static int pedit_header_offsets[] = { |
73867881 PNA |
2621 | [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth), |
2622 | [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4), | |
2623 | [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6), | |
2624 | [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp), | |
2625 | [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp), | |
d79b6df6 OG |
2626 | }; |
2627 | ||
2628 | #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype]) | |
2629 | ||
2630 | static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset, | |
c500c86b | 2631 | struct pedit_headers_action *hdrs) |
d79b6df6 OG |
2632 | { |
2633 | u32 *curr_pmask, *curr_pval; | |
2634 | ||
c500c86b PNA |
2635 | curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset); |
2636 | curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset); | |
d79b6df6 OG |
2637 | |
2638 | if (*curr_pmask & mask) /* disallow acting twice on the same location */ | |
2639 | goto out_err; | |
2640 | ||
2641 | *curr_pmask |= mask; | |
2642 | *curr_pval |= (val & mask); | |
2643 | ||
2644 | return 0; | |
2645 | ||
2646 | out_err: | |
2647 | return -EOPNOTSUPP; | |
2648 | } | |
2649 | ||
2650 | struct mlx5_fields { | |
2651 | u8 field; | |
88f30bbc DL |
2652 | u8 field_bsize; |
2653 | u32 field_mask; | |
d79b6df6 | 2654 | u32 offset; |
27c11b6b | 2655 | u32 match_offset; |
d79b6df6 OG |
2656 | }; |
2657 | ||
88f30bbc DL |
2658 | #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \ |
2659 | {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \ | |
27c11b6b EB |
2660 | offsetof(struct pedit_headers, field) + (off), \ |
2661 | MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)} | |
2662 | ||
2ef86872 EB |
2663 | /* masked values are the same and there are no rewrites that do not have a |
2664 | * match. | |
2665 | */ | |
2666 | #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \ | |
2667 | type matchmaskx = *(type *)(matchmaskp); \ | |
2668 | type matchvalx = *(type *)(matchvalp); \ | |
2669 | type maskx = *(type *)(maskp); \ | |
2670 | type valx = *(type *)(valp); \ | |
2671 | \ | |
2672 | (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \ | |
2673 | matchmaskx)); \ | |
2674 | }) | |
2675 | ||
27c11b6b | 2676 | static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp, |
88f30bbc | 2677 | void *matchmaskp, u8 bsize) |
27c11b6b EB |
2678 | { |
2679 | bool same = false; | |
2680 | ||
88f30bbc DL |
2681 | switch (bsize) { |
2682 | case 8: | |
2ef86872 | 2683 | same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp); |
27c11b6b | 2684 | break; |
88f30bbc | 2685 | case 16: |
2ef86872 | 2686 | same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp); |
27c11b6b | 2687 | break; |
88f30bbc | 2688 | case 32: |
2ef86872 | 2689 | same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp); |
27c11b6b EB |
2690 | break; |
2691 | } | |
2692 | ||
2693 | return same; | |
2694 | } | |
a8e4f0c4 | 2695 | |
d79b6df6 | 2696 | static struct mlx5_fields fields[] = { |
88f30bbc DL |
2697 | OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16), |
2698 | OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0), | |
2699 | OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16), | |
2700 | OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0), | |
2701 | OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype), | |
2702 | OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid), | |
2703 | ||
ab9341b5 | 2704 | OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp), |
88f30bbc DL |
2705 | OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit), |
2706 | OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
2707 | OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
2708 | ||
2709 | OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0, | |
27c11b6b | 2710 | src_ipv4_src_ipv6.ipv6_layout.ipv6[0]), |
88f30bbc | 2711 | OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0, |
27c11b6b | 2712 | src_ipv4_src_ipv6.ipv6_layout.ipv6[4]), |
88f30bbc | 2713 | OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0, |
27c11b6b | 2714 | src_ipv4_src_ipv6.ipv6_layout.ipv6[8]), |
88f30bbc | 2715 | OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0, |
27c11b6b | 2716 | src_ipv4_src_ipv6.ipv6_layout.ipv6[12]), |
88f30bbc | 2717 | OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0, |
27c11b6b | 2718 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]), |
88f30bbc | 2719 | OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0, |
27c11b6b | 2720 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]), |
88f30bbc | 2721 | OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0, |
27c11b6b | 2722 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]), |
88f30bbc | 2723 | OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0, |
27c11b6b | 2724 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]), |
88f30bbc | 2725 | OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit), |
27c11b6b | 2726 | |
88f30bbc DL |
2727 | OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport), |
2728 | OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport), | |
2729 | /* in linux iphdr tcp_flags is 8 bits long */ | |
2730 | OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags), | |
27c11b6b | 2731 | |
88f30bbc DL |
2732 | OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport), |
2733 | OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport), | |
d79b6df6 OG |
2734 | }; |
2735 | ||
6ae4a6a5 PB |
2736 | static int offload_pedit_fields(struct mlx5e_priv *priv, |
2737 | int namespace, | |
2738 | struct pedit_headers_action *hdrs, | |
e98bedf5 | 2739 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
27c11b6b | 2740 | u32 *action_flags, |
e98bedf5 | 2741 | struct netlink_ext_ack *extack) |
d79b6df6 OG |
2742 | { |
2743 | struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals; | |
6ae4a6a5 | 2744 | int i, action_size, first, last, next_z; |
88f30bbc DL |
2745 | void *headers_c, *headers_v, *action, *vals_p; |
2746 | u32 *s_masks_p, *a_masks_p, s_mask, a_mask; | |
6ae4a6a5 | 2747 | struct mlx5e_tc_mod_hdr_acts *mod_acts; |
d79b6df6 | 2748 | struct mlx5_fields *f; |
d79b6df6 | 2749 | unsigned long mask; |
2b64beba OG |
2750 | __be32 mask_be32; |
2751 | __be16 mask_be16; | |
6ae4a6a5 | 2752 | int err; |
88f30bbc DL |
2753 | u8 cmd; |
2754 | ||
6ae4a6a5 | 2755 | mod_acts = &parse_attr->mod_hdr_acts; |
88f30bbc DL |
2756 | headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec); |
2757 | headers_v = get_match_headers_value(*action_flags, &parse_attr->spec); | |
d79b6df6 | 2758 | |
73867881 PNA |
2759 | set_masks = &hdrs[0].masks; |
2760 | add_masks = &hdrs[1].masks; | |
2761 | set_vals = &hdrs[0].vals; | |
2762 | add_vals = &hdrs[1].vals; | |
d79b6df6 | 2763 | |
d65dbedf | 2764 | action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto); |
d79b6df6 OG |
2765 | |
2766 | for (i = 0; i < ARRAY_SIZE(fields); i++) { | |
27c11b6b EB |
2767 | bool skip; |
2768 | ||
d79b6df6 OG |
2769 | f = &fields[i]; |
2770 | /* avoid seeing bits set from previous iterations */ | |
e3ca4e05 OG |
2771 | s_mask = 0; |
2772 | a_mask = 0; | |
d79b6df6 OG |
2773 | |
2774 | s_masks_p = (void *)set_masks + f->offset; | |
2775 | a_masks_p = (void *)add_masks + f->offset; | |
2776 | ||
88f30bbc DL |
2777 | s_mask = *s_masks_p & f->field_mask; |
2778 | a_mask = *a_masks_p & f->field_mask; | |
d79b6df6 OG |
2779 | |
2780 | if (!s_mask && !a_mask) /* nothing to offload here */ | |
2781 | continue; | |
2782 | ||
2783 | if (s_mask && a_mask) { | |
e98bedf5 EB |
2784 | NL_SET_ERR_MSG_MOD(extack, |
2785 | "can't set and add to the same HW field"); | |
d79b6df6 OG |
2786 | printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field); |
2787 | return -EOPNOTSUPP; | |
2788 | } | |
2789 | ||
27c11b6b | 2790 | skip = false; |
d79b6df6 | 2791 | if (s_mask) { |
27c11b6b EB |
2792 | void *match_mask = headers_c + f->match_offset; |
2793 | void *match_val = headers_v + f->match_offset; | |
2794 | ||
d79b6df6 OG |
2795 | cmd = MLX5_ACTION_TYPE_SET; |
2796 | mask = s_mask; | |
2797 | vals_p = (void *)set_vals + f->offset; | |
27c11b6b EB |
2798 | /* don't rewrite if we have a match on the same value */ |
2799 | if (cmp_val_mask(vals_p, s_masks_p, match_val, | |
88f30bbc | 2800 | match_mask, f->field_bsize)) |
27c11b6b | 2801 | skip = true; |
d79b6df6 | 2802 | /* clear to denote we consumed this field */ |
88f30bbc | 2803 | *s_masks_p &= ~f->field_mask; |
d79b6df6 OG |
2804 | } else { |
2805 | cmd = MLX5_ACTION_TYPE_ADD; | |
2806 | mask = a_mask; | |
2807 | vals_p = (void *)add_vals + f->offset; | |
27c11b6b | 2808 | /* add 0 is no change */ |
88f30bbc | 2809 | if ((*(u32 *)vals_p & f->field_mask) == 0) |
27c11b6b | 2810 | skip = true; |
d79b6df6 | 2811 | /* clear to denote we consumed this field */ |
88f30bbc | 2812 | *a_masks_p &= ~f->field_mask; |
d79b6df6 | 2813 | } |
27c11b6b EB |
2814 | if (skip) |
2815 | continue; | |
d79b6df6 | 2816 | |
88f30bbc | 2817 | if (f->field_bsize == 32) { |
58ff18e1 | 2818 | mask_be32 = (__force __be32)(mask); |
2b64beba | 2819 | mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32)); |
88f30bbc | 2820 | } else if (f->field_bsize == 16) { |
58ff18e1 | 2821 | mask_be32 = (__force __be32)(mask); |
404402ab | 2822 | mask_be16 = *(__be16 *)&mask_be32; |
2b64beba OG |
2823 | mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16)); |
2824 | } | |
2825 | ||
88f30bbc DL |
2826 | first = find_first_bit(&mask, f->field_bsize); |
2827 | next_z = find_next_zero_bit(&mask, f->field_bsize, first); | |
2828 | last = find_last_bit(&mask, f->field_bsize); | |
2b64beba | 2829 | if (first < next_z && next_z < last) { |
e98bedf5 EB |
2830 | NL_SET_ERR_MSG_MOD(extack, |
2831 | "rewrite of few sub-fields isn't supported"); | |
2b64beba | 2832 | printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n", |
d79b6df6 OG |
2833 | mask); |
2834 | return -EOPNOTSUPP; | |
2835 | } | |
2836 | ||
6ae4a6a5 PB |
2837 | err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts); |
2838 | if (err) { | |
2839 | NL_SET_ERR_MSG_MOD(extack, | |
2840 | "too many pedit actions, can't offload"); | |
2841 | mlx5_core_warn(priv->mdev, | |
2842 | "mlx5: parsed %d pedit actions, can't do more\n", | |
2843 | mod_acts->num_actions); | |
2844 | return err; | |
2845 | } | |
2846 | ||
2847 | action = mod_acts->actions + | |
2848 | (mod_acts->num_actions * action_size); | |
d79b6df6 OG |
2849 | MLX5_SET(set_action_in, action, action_type, cmd); |
2850 | MLX5_SET(set_action_in, action, field, f->field); | |
2851 | ||
2852 | if (cmd == MLX5_ACTION_TYPE_SET) { | |
88f30bbc DL |
2853 | int start; |
2854 | ||
2855 | /* if field is bit sized it can start not from first bit */ | |
2856 | start = find_first_bit((unsigned long *)&f->field_mask, | |
2857 | f->field_bsize); | |
2858 | ||
2859 | MLX5_SET(set_action_in, action, offset, first - start); | |
d79b6df6 | 2860 | /* length is num of bits to be written, zero means length of 32 */ |
2b64beba | 2861 | MLX5_SET(set_action_in, action, length, (last - first + 1)); |
d79b6df6 OG |
2862 | } |
2863 | ||
88f30bbc | 2864 | if (f->field_bsize == 32) |
2b64beba | 2865 | MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first); |
88f30bbc | 2866 | else if (f->field_bsize == 16) |
2b64beba | 2867 | MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first); |
88f30bbc | 2868 | else if (f->field_bsize == 8) |
2b64beba | 2869 | MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first); |
d79b6df6 | 2870 | |
6ae4a6a5 | 2871 | ++mod_acts->num_actions; |
d79b6df6 OG |
2872 | } |
2873 | ||
d79b6df6 OG |
2874 | return 0; |
2875 | } | |
2876 | ||
2cc1cb1d TZ |
2877 | static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev, |
2878 | int namespace) | |
2879 | { | |
2880 | if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */ | |
2881 | return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions); | |
2882 | else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */ | |
2883 | return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions); | |
2884 | } | |
2885 | ||
6ae4a6a5 PB |
2886 | int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev, |
2887 | int namespace, | |
2888 | struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts) | |
d79b6df6 | 2889 | { |
6ae4a6a5 PB |
2890 | int action_size, new_num_actions, max_hw_actions; |
2891 | size_t new_sz, old_sz; | |
2892 | void *ret; | |
d79b6df6 | 2893 | |
6ae4a6a5 PB |
2894 | if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions) |
2895 | return 0; | |
d79b6df6 | 2896 | |
d65dbedf | 2897 | action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto); |
d79b6df6 | 2898 | |
6ae4a6a5 PB |
2899 | max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev, |
2900 | namespace); | |
2901 | new_num_actions = min(max_hw_actions, | |
2902 | mod_hdr_acts->actions ? | |
2903 | mod_hdr_acts->max_actions * 2 : 1); | |
2904 | if (mod_hdr_acts->max_actions == new_num_actions) | |
2905 | return -ENOSPC; | |
2906 | ||
2907 | new_sz = action_size * new_num_actions; | |
2908 | old_sz = mod_hdr_acts->max_actions * action_size; | |
2909 | ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL); | |
2910 | if (!ret) | |
d79b6df6 OG |
2911 | return -ENOMEM; |
2912 | ||
6ae4a6a5 PB |
2913 | memset(ret + old_sz, 0, new_sz - old_sz); |
2914 | mod_hdr_acts->actions = ret; | |
2915 | mod_hdr_acts->max_actions = new_num_actions; | |
2916 | ||
d79b6df6 OG |
2917 | return 0; |
2918 | } | |
2919 | ||
6ae4a6a5 PB |
2920 | void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts) |
2921 | { | |
2922 | kfree(mod_hdr_acts->actions); | |
2923 | mod_hdr_acts->actions = NULL; | |
2924 | mod_hdr_acts->num_actions = 0; | |
2925 | mod_hdr_acts->max_actions = 0; | |
2926 | } | |
2927 | ||
d79b6df6 OG |
2928 | static const struct pedit_headers zero_masks = {}; |
2929 | ||
582234b4 EC |
2930 | static int |
2931 | parse_pedit_to_modify_hdr(struct mlx5e_priv *priv, | |
2932 | const struct flow_action_entry *act, int namespace, | |
2933 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
2934 | struct pedit_headers_action *hdrs, | |
2935 | struct netlink_ext_ack *extack) | |
d79b6df6 | 2936 | { |
73867881 PNA |
2937 | u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1; |
2938 | int err = -EOPNOTSUPP; | |
d79b6df6 | 2939 | u32 mask, val, offset; |
73867881 | 2940 | u8 htype; |
d79b6df6 | 2941 | |
73867881 PNA |
2942 | htype = act->mangle.htype; |
2943 | err = -EOPNOTSUPP; /* can't be all optimistic */ | |
d79b6df6 | 2944 | |
73867881 PNA |
2945 | if (htype == FLOW_ACT_MANGLE_UNSPEC) { |
2946 | NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded"); | |
2947 | goto out_err; | |
2948 | } | |
d79b6df6 | 2949 | |
2cc1cb1d TZ |
2950 | if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) { |
2951 | NL_SET_ERR_MSG_MOD(extack, | |
2952 | "The pedit offload action is not supported"); | |
2953 | goto out_err; | |
2954 | } | |
2955 | ||
73867881 PNA |
2956 | mask = act->mangle.mask; |
2957 | val = act->mangle.val; | |
2958 | offset = act->mangle.offset; | |
d79b6df6 | 2959 | |
73867881 PNA |
2960 | err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]); |
2961 | if (err) | |
2962 | goto out_err; | |
c500c86b | 2963 | |
73867881 | 2964 | hdrs[cmd].pedits++; |
d79b6df6 | 2965 | |
c500c86b PNA |
2966 | return 0; |
2967 | out_err: | |
2968 | return err; | |
2969 | } | |
2970 | ||
582234b4 EC |
2971 | static int |
2972 | parse_pedit_to_reformat(struct mlx5e_priv *priv, | |
2973 | const struct flow_action_entry *act, | |
2974 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
2975 | struct netlink_ext_ack *extack) | |
2976 | { | |
2977 | u32 mask, val, offset; | |
2978 | u32 *p; | |
2979 | ||
2980 | if (act->id != FLOW_ACTION_MANGLE) | |
2981 | return -EOPNOTSUPP; | |
2982 | ||
2983 | if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) { | |
2984 | NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported"); | |
2985 | return -EOPNOTSUPP; | |
2986 | } | |
2987 | ||
2988 | mask = ~act->mangle.mask; | |
2989 | val = act->mangle.val; | |
2990 | offset = act->mangle.offset; | |
2991 | p = (u32 *)&parse_attr->eth; | |
2992 | *(p + (offset >> 2)) |= (val & mask); | |
2993 | ||
2994 | return 0; | |
2995 | } | |
2996 | ||
2997 | static int parse_tc_pedit_action(struct mlx5e_priv *priv, | |
2998 | const struct flow_action_entry *act, int namespace, | |
2999 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
3000 | struct pedit_headers_action *hdrs, | |
3001 | struct mlx5e_tc_flow *flow, | |
3002 | struct netlink_ext_ack *extack) | |
3003 | { | |
3004 | if (flow && flow_flag_test(flow, L3_TO_L2_DECAP)) | |
3005 | return parse_pedit_to_reformat(priv, act, parse_attr, extack); | |
3006 | ||
3007 | return parse_pedit_to_modify_hdr(priv, act, namespace, | |
3008 | parse_attr, hdrs, extack); | |
3009 | } | |
3010 | ||
c500c86b PNA |
3011 | static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace, |
3012 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
3013 | struct pedit_headers_action *hdrs, | |
27c11b6b | 3014 | u32 *action_flags, |
c500c86b PNA |
3015 | struct netlink_ext_ack *extack) |
3016 | { | |
3017 | struct pedit_headers *cmd_masks; | |
3018 | int err; | |
3019 | u8 cmd; | |
3020 | ||
6ae4a6a5 PB |
3021 | err = offload_pedit_fields(priv, namespace, hdrs, parse_attr, |
3022 | action_flags, extack); | |
d79b6df6 OG |
3023 | if (err < 0) |
3024 | goto out_dealloc_parsed_actions; | |
3025 | ||
3026 | for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) { | |
c500c86b | 3027 | cmd_masks = &hdrs[cmd].masks; |
d79b6df6 | 3028 | if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) { |
e98bedf5 EB |
3029 | NL_SET_ERR_MSG_MOD(extack, |
3030 | "attempt to offload an unsupported field"); | |
b3a433de | 3031 | netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd); |
d79b6df6 OG |
3032 | print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS, |
3033 | 16, 1, cmd_masks, sizeof(zero_masks), true); | |
3034 | err = -EOPNOTSUPP; | |
3035 | goto out_dealloc_parsed_actions; | |
3036 | } | |
3037 | } | |
3038 | ||
3039 | return 0; | |
3040 | ||
3041 | out_dealloc_parsed_actions: | |
6ae4a6a5 | 3042 | dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts); |
d79b6df6 OG |
3043 | return err; |
3044 | } | |
3045 | ||
e98bedf5 EB |
3046 | static bool csum_offload_supported(struct mlx5e_priv *priv, |
3047 | u32 action, | |
3048 | u32 update_flags, | |
3049 | struct netlink_ext_ack *extack) | |
26c02749 OG |
3050 | { |
3051 | u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP | | |
3052 | TCA_CSUM_UPDATE_FLAG_UDP; | |
3053 | ||
3054 | /* The HW recalcs checksums only if re-writing headers */ | |
3055 | if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) { | |
e98bedf5 EB |
3056 | NL_SET_ERR_MSG_MOD(extack, |
3057 | "TC csum action is only offloaded with pedit"); | |
26c02749 OG |
3058 | netdev_warn(priv->netdev, |
3059 | "TC csum action is only offloaded with pedit\n"); | |
3060 | return false; | |
3061 | } | |
3062 | ||
3063 | if (update_flags & ~prot_flags) { | |
e98bedf5 EB |
3064 | NL_SET_ERR_MSG_MOD(extack, |
3065 | "can't offload TC csum action for some header/s"); | |
26c02749 OG |
3066 | netdev_warn(priv->netdev, |
3067 | "can't offload TC csum action for some header/s - flags %#x\n", | |
3068 | update_flags); | |
3069 | return false; | |
3070 | } | |
3071 | ||
3072 | return true; | |
3073 | } | |
3074 | ||
8998576b DL |
3075 | struct ip_ttl_word { |
3076 | __u8 ttl; | |
3077 | __u8 protocol; | |
3078 | __sum16 check; | |
3079 | }; | |
3080 | ||
3081 | struct ipv6_hoplimit_word { | |
3082 | __be16 payload_len; | |
3083 | __u8 nexthdr; | |
3084 | __u8 hop_limit; | |
3085 | }; | |
3086 | ||
4c3844d9 PB |
3087 | static int is_action_keys_supported(const struct flow_action_entry *act, |
3088 | bool ct_flow, bool *modify_ip_header, | |
3089 | struct netlink_ext_ack *extack) | |
8998576b DL |
3090 | { |
3091 | u32 mask, offset; | |
3092 | u8 htype; | |
3093 | ||
3094 | htype = act->mangle.htype; | |
3095 | offset = act->mangle.offset; | |
3096 | mask = ~act->mangle.mask; | |
3097 | /* For IPv4 & IPv6 header check 4 byte word, | |
3098 | * to determine that modified fields | |
3099 | * are NOT ttl & hop_limit only. | |
3100 | */ | |
3101 | if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) { | |
3102 | struct ip_ttl_word *ttl_word = | |
3103 | (struct ip_ttl_word *)&mask; | |
3104 | ||
3105 | if (offset != offsetof(struct iphdr, ttl) || | |
3106 | ttl_word->protocol || | |
3107 | ttl_word->check) { | |
4c3844d9 PB |
3108 | *modify_ip_header = true; |
3109 | } | |
3110 | ||
3111 | if (ct_flow && offset >= offsetof(struct iphdr, saddr)) { | |
3112 | NL_SET_ERR_MSG_MOD(extack, | |
3113 | "can't offload re-write of ipv4 address with action ct"); | |
3114 | return -EOPNOTSUPP; | |
8998576b DL |
3115 | } |
3116 | } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) { | |
3117 | struct ipv6_hoplimit_word *hoplimit_word = | |
3118 | (struct ipv6_hoplimit_word *)&mask; | |
3119 | ||
3120 | if (offset != offsetof(struct ipv6hdr, payload_len) || | |
3121 | hoplimit_word->payload_len || | |
3122 | hoplimit_word->nexthdr) { | |
4c3844d9 PB |
3123 | *modify_ip_header = true; |
3124 | } | |
3125 | ||
3126 | if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr)) { | |
3127 | NL_SET_ERR_MSG_MOD(extack, | |
3128 | "can't offload re-write of ipv6 address with action ct"); | |
3129 | return -EOPNOTSUPP; | |
8998576b | 3130 | } |
4c3844d9 PB |
3131 | } else if (ct_flow && (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP || |
3132 | htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP)) { | |
3133 | NL_SET_ERR_MSG_MOD(extack, | |
3134 | "can't offload re-write of transport header ports with action ct"); | |
3135 | return -EOPNOTSUPP; | |
8998576b | 3136 | } |
4c3844d9 PB |
3137 | |
3138 | return 0; | |
8998576b DL |
3139 | } |
3140 | ||
3d486ec4 OS |
3141 | static bool modify_header_match_supported(struct mlx5e_priv *priv, |
3142 | struct mlx5_flow_spec *spec, | |
73867881 | 3143 | struct flow_action *flow_action, |
4c3844d9 | 3144 | u32 actions, bool ct_flow, |
e98bedf5 | 3145 | struct netlink_ext_ack *extack) |
bdd66ac0 | 3146 | { |
73867881 | 3147 | const struct flow_action_entry *act; |
bdd66ac0 | 3148 | bool modify_ip_header; |
fca53304 | 3149 | void *headers_c; |
bdd66ac0 OG |
3150 | void *headers_v; |
3151 | u16 ethertype; | |
8998576b | 3152 | u8 ip_proto; |
4c3844d9 | 3153 | int i, err; |
bdd66ac0 | 3154 | |
fca53304 | 3155 | headers_c = get_match_headers_criteria(actions, spec); |
8377629e | 3156 | headers_v = get_match_headers_value(actions, spec); |
bdd66ac0 OG |
3157 | ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype); |
3158 | ||
3159 | /* for non-IP we only re-write MACs, so we're okay */ | |
fca53304 EB |
3160 | if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 && |
3161 | ethertype != ETH_P_IP && ethertype != ETH_P_IPV6) | |
bdd66ac0 OG |
3162 | goto out_ok; |
3163 | ||
3164 | modify_ip_header = false; | |
73867881 PNA |
3165 | flow_action_for_each(i, act, flow_action) { |
3166 | if (act->id != FLOW_ACTION_MANGLE && | |
3167 | act->id != FLOW_ACTION_ADD) | |
bdd66ac0 OG |
3168 | continue; |
3169 | ||
4c3844d9 PB |
3170 | err = is_action_keys_supported(act, ct_flow, |
3171 | &modify_ip_header, extack); | |
3172 | if (err) | |
3173 | return err; | |
bdd66ac0 OG |
3174 | } |
3175 | ||
3176 | ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol); | |
1ccef350 JL |
3177 | if (modify_ip_header && ip_proto != IPPROTO_TCP && |
3178 | ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) { | |
e98bedf5 EB |
3179 | NL_SET_ERR_MSG_MOD(extack, |
3180 | "can't offload re-write of non TCP/UDP"); | |
3d486ec4 OS |
3181 | netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n", |
3182 | ip_proto); | |
bdd66ac0 OG |
3183 | return false; |
3184 | } | |
3185 | ||
3186 | out_ok: | |
3187 | return true; | |
3188 | } | |
3189 | ||
3190 | static bool actions_match_supported(struct mlx5e_priv *priv, | |
73867881 | 3191 | struct flow_action *flow_action, |
bdd66ac0 | 3192 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
3193 | struct mlx5e_tc_flow *flow, |
3194 | struct netlink_ext_ack *extack) | |
bdd66ac0 | 3195 | { |
a7c119bd | 3196 | bool ct_flow = false, ct_clear = false; |
bdd66ac0 OG |
3197 | u32 actions; |
3198 | ||
4c3844d9 | 3199 | if (mlx5e_is_eswitch_flow(flow)) { |
bdd66ac0 | 3200 | actions = flow->esw_attr->action; |
a7c119bd PB |
3201 | ct_clear = flow->esw_attr->ct_attr.ct_action & |
3202 | TCA_CT_ACT_CLEAR; | |
3203 | ct_flow = flow_flag_test(flow, CT) && !ct_clear; | |
4c3844d9 PB |
3204 | if (flow->esw_attr->split_count && ct_flow) { |
3205 | /* All registers used by ct are cleared when using | |
3206 | * split rules. | |
3207 | */ | |
3208 | NL_SET_ERR_MSG_MOD(extack, | |
3209 | "Can't offload mirroring with action ct"); | |
49397b80 | 3210 | return false; |
4c3844d9 PB |
3211 | } |
3212 | } else { | |
bdd66ac0 | 3213 | actions = flow->nic_attr->action; |
4c3844d9 | 3214 | } |
bdd66ac0 OG |
3215 | |
3216 | if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) | |
3d486ec4 | 3217 | return modify_header_match_supported(priv, &parse_attr->spec, |
a655fe9f | 3218 | flow_action, actions, |
4c3844d9 | 3219 | ct_flow, extack); |
bdd66ac0 OG |
3220 | |
3221 | return true; | |
3222 | } | |
3223 | ||
32134847 MD |
3224 | static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv) |
3225 | { | |
3226 | return priv->mdev == peer_priv->mdev; | |
3227 | } | |
3228 | ||
5c65c564 OG |
3229 | static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv) |
3230 | { | |
3231 | struct mlx5_core_dev *fmdev, *pmdev; | |
816f6706 | 3232 | u64 fsystem_guid, psystem_guid; |
5c65c564 OG |
3233 | |
3234 | fmdev = priv->mdev; | |
3235 | pmdev = peer_priv->mdev; | |
3236 | ||
59c9d35e AH |
3237 | fsystem_guid = mlx5_query_nic_system_image_guid(fmdev); |
3238 | psystem_guid = mlx5_query_nic_system_image_guid(pmdev); | |
5c65c564 | 3239 | |
816f6706 | 3240 | return (fsystem_guid == psystem_guid); |
5c65c564 OG |
3241 | } |
3242 | ||
bdc837ee EB |
3243 | static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace, |
3244 | const struct flow_action_entry *act, | |
3245 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
3246 | struct pedit_headers_action *hdrs, | |
3247 | u32 *action, struct netlink_ext_ack *extack) | |
3248 | { | |
3249 | u16 mask16 = VLAN_VID_MASK; | |
3250 | u16 val16 = act->vlan.vid & VLAN_VID_MASK; | |
3251 | const struct flow_action_entry pedit_act = { | |
3252 | .id = FLOW_ACTION_MANGLE, | |
3253 | .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH, | |
3254 | .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI), | |
3255 | .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16), | |
3256 | .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16), | |
3257 | }; | |
6fca9d1e | 3258 | u8 match_prio_mask, match_prio_val; |
bf2f3bca | 3259 | void *headers_c, *headers_v; |
bdc837ee EB |
3260 | int err; |
3261 | ||
bf2f3bca EB |
3262 | headers_c = get_match_headers_criteria(*action, &parse_attr->spec); |
3263 | headers_v = get_match_headers_value(*action, &parse_attr->spec); | |
3264 | ||
3265 | if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) && | |
3266 | MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) { | |
3267 | NL_SET_ERR_MSG_MOD(extack, | |
3268 | "VLAN rewrite action must have VLAN protocol match"); | |
3269 | return -EOPNOTSUPP; | |
3270 | } | |
3271 | ||
6fca9d1e EB |
3272 | match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); |
3273 | match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); | |
3274 | if (act->vlan.prio != (match_prio_val & match_prio_mask)) { | |
3275 | NL_SET_ERR_MSG_MOD(extack, | |
3276 | "Changing VLAN prio is not supported"); | |
bdc837ee EB |
3277 | return -EOPNOTSUPP; |
3278 | } | |
3279 | ||
582234b4 | 3280 | err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack); |
bdc837ee EB |
3281 | *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
3282 | ||
3283 | return err; | |
3284 | } | |
3285 | ||
0bac1194 EB |
3286 | static int |
3287 | add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv, | |
3288 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
3289 | struct pedit_headers_action *hdrs, | |
3290 | u32 *action, struct netlink_ext_ack *extack) | |
3291 | { | |
3292 | const struct flow_action_entry prio_tag_act = { | |
3293 | .vlan.vid = 0, | |
3294 | .vlan.prio = | |
3295 | MLX5_GET(fte_match_set_lyr_2_4, | |
3296 | get_match_headers_value(*action, | |
3297 | &parse_attr->spec), | |
3298 | first_prio) & | |
3299 | MLX5_GET(fte_match_set_lyr_2_4, | |
3300 | get_match_headers_criteria(*action, | |
3301 | &parse_attr->spec), | |
3302 | first_prio), | |
3303 | }; | |
3304 | ||
3305 | return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB, | |
3306 | &prio_tag_act, parse_attr, hdrs, action, | |
3307 | extack); | |
3308 | } | |
3309 | ||
73867881 PNA |
3310 | static int parse_tc_nic_actions(struct mlx5e_priv *priv, |
3311 | struct flow_action *flow_action, | |
aa0cbbae | 3312 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
3313 | struct mlx5e_tc_flow *flow, |
3314 | struct netlink_ext_ack *extack) | |
e3a2b7ed | 3315 | { |
aa0cbbae | 3316 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
73867881 PNA |
3317 | struct pedit_headers_action hdrs[2] = {}; |
3318 | const struct flow_action_entry *act; | |
1cab1cd7 | 3319 | u32 action = 0; |
244cd96a | 3320 | int err, i; |
e3a2b7ed | 3321 | |
73867881 | 3322 | if (!flow_action_has_entries(flow_action)) |
e3a2b7ed AV |
3323 | return -EINVAL; |
3324 | ||
53eca1f3 JK |
3325 | if (!flow_action_hw_stats_check(flow_action, extack, |
3326 | FLOW_ACTION_HW_STATS_DELAYED_BIT)) | |
319a1d19 JP |
3327 | return -EOPNOTSUPP; |
3328 | ||
3bc4b7bf | 3329 | attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; |
e3a2b7ed | 3330 | |
73867881 PNA |
3331 | flow_action_for_each(i, act, flow_action) { |
3332 | switch (act->id) { | |
15fc92ec TZ |
3333 | case FLOW_ACTION_ACCEPT: |
3334 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | | |
3335 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
3336 | break; | |
73867881 | 3337 | case FLOW_ACTION_DROP: |
1cab1cd7 | 3338 | action |= MLX5_FLOW_CONTEXT_ACTION_DROP; |
aad7e08d AV |
3339 | if (MLX5_CAP_FLOWTABLE(priv->mdev, |
3340 | flow_table_properties_nic_receive.flow_counter)) | |
1cab1cd7 | 3341 | action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; |
73867881 PNA |
3342 | break; |
3343 | case FLOW_ACTION_MANGLE: | |
3344 | case FLOW_ACTION_ADD: | |
3345 | err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL, | |
582234b4 | 3346 | parse_attr, hdrs, NULL, extack); |
2f4fe4ca OG |
3347 | if (err) |
3348 | return err; | |
3349 | ||
1cab1cd7 OG |
3350 | action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | |
3351 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
73867881 | 3352 | break; |
bdc837ee EB |
3353 | case FLOW_ACTION_VLAN_MANGLE: |
3354 | err = add_vlan_rewrite_action(priv, | |
3355 | MLX5_FLOW_NAMESPACE_KERNEL, | |
3356 | act, parse_attr, hdrs, | |
3357 | &action, extack); | |
3358 | if (err) | |
3359 | return err; | |
3360 | ||
3361 | break; | |
73867881 | 3362 | case FLOW_ACTION_CSUM: |
1cab1cd7 | 3363 | if (csum_offload_supported(priv, action, |
73867881 | 3364 | act->csum_flags, |
e98bedf5 | 3365 | extack)) |
73867881 | 3366 | break; |
26c02749 OG |
3367 | |
3368 | return -EOPNOTSUPP; | |
73867881 PNA |
3369 | case FLOW_ACTION_REDIRECT: { |
3370 | struct net_device *peer_dev = act->dev; | |
5c65c564 OG |
3371 | |
3372 | if (priv->netdev->netdev_ops == peer_dev->netdev_ops && | |
3373 | same_hw_devs(priv, netdev_priv(peer_dev))) { | |
98b66cb1 | 3374 | parse_attr->mirred_ifindex[0] = peer_dev->ifindex; |
226f2ca3 | 3375 | flow_flag_set(flow, HAIRPIN); |
1cab1cd7 OG |
3376 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
3377 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
5c65c564 | 3378 | } else { |
e98bedf5 EB |
3379 | NL_SET_ERR_MSG_MOD(extack, |
3380 | "device is not on same HW, can't offload"); | |
5c65c564 OG |
3381 | netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n", |
3382 | peer_dev->name); | |
3383 | return -EINVAL; | |
3384 | } | |
73867881 PNA |
3385 | } |
3386 | break; | |
3387 | case FLOW_ACTION_MARK: { | |
3388 | u32 mark = act->mark; | |
e3a2b7ed AV |
3389 | |
3390 | if (mark & ~MLX5E_TC_FLOW_ID_MASK) { | |
e98bedf5 EB |
3391 | NL_SET_ERR_MSG_MOD(extack, |
3392 | "Bad flow mark - only 16 bit is supported"); | |
e3a2b7ed AV |
3393 | return -EINVAL; |
3394 | } | |
3395 | ||
3bc4b7bf | 3396 | attr->flow_tag = mark; |
1cab1cd7 | 3397 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
73867881 PNA |
3398 | } |
3399 | break; | |
3400 | default: | |
2cc1cb1d TZ |
3401 | NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); |
3402 | return -EOPNOTSUPP; | |
e3a2b7ed | 3403 | } |
e3a2b7ed AV |
3404 | } |
3405 | ||
c500c86b PNA |
3406 | if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || |
3407 | hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { | |
3408 | err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL, | |
27c11b6b | 3409 | parse_attr, hdrs, &action, extack); |
c500c86b PNA |
3410 | if (err) |
3411 | return err; | |
27c11b6b EB |
3412 | /* in case all pedit actions are skipped, remove the MOD_HDR |
3413 | * flag. | |
3414 | */ | |
6ae4a6a5 | 3415 | if (parse_attr->mod_hdr_acts.num_actions == 0) { |
27c11b6b | 3416 | action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
6ae4a6a5 | 3417 | dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts); |
e7739a60 | 3418 | } |
c500c86b PNA |
3419 | } |
3420 | ||
1cab1cd7 | 3421 | attr->action = action; |
73867881 | 3422 | if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) |
bdd66ac0 OG |
3423 | return -EOPNOTSUPP; |
3424 | ||
e3a2b7ed AV |
3425 | return 0; |
3426 | } | |
3427 | ||
7f1a546e | 3428 | struct encap_key { |
1f6da306 | 3429 | const struct ip_tunnel_key *ip_tun_key; |
d386939a | 3430 | struct mlx5e_tc_tunnel *tc_tunnel; |
7f1a546e EB |
3431 | }; |
3432 | ||
3433 | static inline int cmp_encap_info(struct encap_key *a, | |
3434 | struct encap_key *b) | |
a54e20b4 | 3435 | { |
7f1a546e | 3436 | return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) || |
d386939a | 3437 | a->tc_tunnel->tunnel_type != b->tc_tunnel->tunnel_type; |
a54e20b4 HHZ |
3438 | } |
3439 | ||
14e6b038 EC |
3440 | static inline int cmp_decap_info(struct mlx5e_decap_key *a, |
3441 | struct mlx5e_decap_key *b) | |
3442 | { | |
3443 | return memcmp(&a->key, &b->key, sizeof(b->key)); | |
3444 | } | |
3445 | ||
7f1a546e | 3446 | static inline int hash_encap_info(struct encap_key *key) |
a54e20b4 | 3447 | { |
7f1a546e | 3448 | return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key), |
d386939a | 3449 | key->tc_tunnel->tunnel_type); |
a54e20b4 HHZ |
3450 | } |
3451 | ||
14e6b038 EC |
3452 | static inline int hash_decap_info(struct mlx5e_decap_key *key) |
3453 | { | |
3454 | return jhash(&key->key, sizeof(key->key), 0); | |
3455 | } | |
a54e20b4 | 3456 | |
32134847 | 3457 | static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv, |
b1d90e6b RL |
3458 | struct net_device *peer_netdev) |
3459 | { | |
3460 | struct mlx5e_priv *peer_priv; | |
3461 | ||
3462 | peer_priv = netdev_priv(peer_netdev); | |
3463 | ||
3464 | return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) && | |
32134847 MD |
3465 | mlx5e_eswitch_vf_rep(priv->netdev) && |
3466 | mlx5e_eswitch_vf_rep(peer_netdev) && | |
68931c7d | 3467 | same_hw_devs(priv, peer_priv)); |
b1d90e6b RL |
3468 | } |
3469 | ||
948993f2 VB |
3470 | bool mlx5e_encap_take(struct mlx5e_encap_entry *e) |
3471 | { | |
3472 | return refcount_inc_not_zero(&e->refcnt); | |
3473 | } | |
3474 | ||
14e6b038 EC |
3475 | static bool mlx5e_decap_take(struct mlx5e_decap_entry *e) |
3476 | { | |
3477 | return refcount_inc_not_zero(&e->refcnt); | |
3478 | } | |
3479 | ||
948993f2 VB |
3480 | static struct mlx5e_encap_entry * |
3481 | mlx5e_encap_get(struct mlx5e_priv *priv, struct encap_key *key, | |
3482 | uintptr_t hash_key) | |
3483 | { | |
3484 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
3485 | struct mlx5e_encap_entry *e; | |
3486 | struct encap_key e_key; | |
3487 | ||
3488 | hash_for_each_possible_rcu(esw->offloads.encap_tbl, e, | |
3489 | encap_hlist, hash_key) { | |
3490 | e_key.ip_tun_key = &e->tun_info->key; | |
3491 | e_key.tc_tunnel = e->tunnel; | |
3492 | if (!cmp_encap_info(&e_key, key) && | |
3493 | mlx5e_encap_take(e)) | |
3494 | return e; | |
3495 | } | |
3496 | ||
3497 | return NULL; | |
3498 | } | |
3499 | ||
14e6b038 EC |
3500 | static struct mlx5e_decap_entry * |
3501 | mlx5e_decap_get(struct mlx5e_priv *priv, struct mlx5e_decap_key *key, | |
3502 | uintptr_t hash_key) | |
3503 | { | |
3504 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
3505 | struct mlx5e_decap_key r_key; | |
3506 | struct mlx5e_decap_entry *e; | |
3507 | ||
3508 | hash_for_each_possible_rcu(esw->offloads.decap_tbl, e, | |
3509 | hlist, hash_key) { | |
3510 | r_key = e->key; | |
3511 | if (!cmp_decap_info(&r_key, key) && | |
3512 | mlx5e_decap_take(e)) | |
3513 | return e; | |
3514 | } | |
3515 | return NULL; | |
3516 | } | |
3517 | ||
2a4b6526 VB |
3518 | static struct ip_tunnel_info *dup_tun_info(const struct ip_tunnel_info *tun_info) |
3519 | { | |
3520 | size_t tun_size = sizeof(*tun_info) + tun_info->options_len; | |
3521 | ||
3522 | return kmemdup(tun_info, tun_size, GFP_KERNEL); | |
3523 | } | |
3524 | ||
554fe75c DL |
3525 | static bool is_duplicated_encap_entry(struct mlx5e_priv *priv, |
3526 | struct mlx5e_tc_flow *flow, | |
3527 | int out_index, | |
3528 | struct mlx5e_encap_entry *e, | |
3529 | struct netlink_ext_ack *extack) | |
3530 | { | |
3531 | int i; | |
3532 | ||
3533 | for (i = 0; i < out_index; i++) { | |
3534 | if (flow->encaps[i].e != e) | |
3535 | continue; | |
3536 | NL_SET_ERR_MSG_MOD(extack, "can't duplicate encap action"); | |
3537 | netdev_err(priv->netdev, "can't duplicate encap action\n"); | |
3538 | return true; | |
3539 | } | |
3540 | ||
3541 | return false; | |
3542 | } | |
3543 | ||
a54e20b4 | 3544 | static int mlx5e_attach_encap(struct mlx5e_priv *priv, |
e98bedf5 | 3545 | struct mlx5e_tc_flow *flow, |
733d4f36 RD |
3546 | struct net_device *mirred_dev, |
3547 | int out_index, | |
8c4dc42b | 3548 | struct netlink_ext_ack *extack, |
0ad060ee RD |
3549 | struct net_device **encap_dev, |
3550 | bool *encap_valid) | |
a54e20b4 HHZ |
3551 | { |
3552 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
45247bf2 | 3553 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
733d4f36 | 3554 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
1f6da306 | 3555 | const struct ip_tunnel_info *tun_info; |
948993f2 | 3556 | struct encap_key key; |
c1ae1152 | 3557 | struct mlx5e_encap_entry *e; |
733d4f36 | 3558 | unsigned short family; |
a54e20b4 | 3559 | uintptr_t hash_key; |
54c177ca | 3560 | int err = 0; |
a54e20b4 | 3561 | |
733d4f36 | 3562 | parse_attr = attr->parse_attr; |
1f6da306 | 3563 | tun_info = parse_attr->tun_info[out_index]; |
733d4f36 | 3564 | family = ip_tunnel_info_af(tun_info); |
7f1a546e | 3565 | key.ip_tun_key = &tun_info->key; |
d386939a | 3566 | key.tc_tunnel = mlx5e_get_tc_tun(mirred_dev); |
d71f895c EC |
3567 | if (!key.tc_tunnel) { |
3568 | NL_SET_ERR_MSG_MOD(extack, "Unsupported tunnel"); | |
3569 | return -EOPNOTSUPP; | |
3570 | } | |
733d4f36 | 3571 | |
7f1a546e | 3572 | hash_key = hash_encap_info(&key); |
a54e20b4 | 3573 | |
61086f39 | 3574 | mutex_lock(&esw->offloads.encap_tbl_lock); |
948993f2 | 3575 | e = mlx5e_encap_get(priv, &key, hash_key); |
a54e20b4 | 3576 | |
b2812089 | 3577 | /* must verify if encap is valid or not */ |
d589e785 | 3578 | if (e) { |
554fe75c DL |
3579 | /* Check that entry was not already attached to this flow */ |
3580 | if (is_duplicated_encap_entry(priv, flow, out_index, e, extack)) { | |
3581 | err = -EOPNOTSUPP; | |
3582 | goto out_err; | |
3583 | } | |
3584 | ||
d589e785 VB |
3585 | mutex_unlock(&esw->offloads.encap_tbl_lock); |
3586 | wait_for_completion(&e->res_ready); | |
3587 | ||
3588 | /* Protect against concurrent neigh update. */ | |
3589 | mutex_lock(&esw->offloads.encap_tbl_lock); | |
3c140dd5 | 3590 | if (e->compl_result < 0) { |
d589e785 VB |
3591 | err = -EREMOTEIO; |
3592 | goto out_err; | |
3593 | } | |
45247bf2 | 3594 | goto attach_flow; |
d589e785 | 3595 | } |
a54e20b4 HHZ |
3596 | |
3597 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
61086f39 VB |
3598 | if (!e) { |
3599 | err = -ENOMEM; | |
3600 | goto out_err; | |
3601 | } | |
a54e20b4 | 3602 | |
948993f2 | 3603 | refcount_set(&e->refcnt, 1); |
d589e785 VB |
3604 | init_completion(&e->res_ready); |
3605 | ||
2a4b6526 VB |
3606 | tun_info = dup_tun_info(tun_info); |
3607 | if (!tun_info) { | |
3608 | err = -ENOMEM; | |
3609 | goto out_err_init; | |
3610 | } | |
1f6da306 | 3611 | e->tun_info = tun_info; |
101f4de9 | 3612 | err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack); |
2a4b6526 VB |
3613 | if (err) |
3614 | goto out_err_init; | |
54c177ca | 3615 | |
a54e20b4 | 3616 | INIT_LIST_HEAD(&e->flows); |
d589e785 VB |
3617 | hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key); |
3618 | mutex_unlock(&esw->offloads.encap_tbl_lock); | |
a54e20b4 | 3619 | |
ce99f6b9 | 3620 | if (family == AF_INET) |
101f4de9 | 3621 | err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e); |
ce99f6b9 | 3622 | else if (family == AF_INET6) |
101f4de9 | 3623 | err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e); |
ce99f6b9 | 3624 | |
d589e785 VB |
3625 | /* Protect against concurrent neigh update. */ |
3626 | mutex_lock(&esw->offloads.encap_tbl_lock); | |
3627 | complete_all(&e->res_ready); | |
3628 | if (err) { | |
3629 | e->compl_result = err; | |
a54e20b4 | 3630 | goto out_err; |
d589e785 | 3631 | } |
3c140dd5 | 3632 | e->compl_result = 1; |
a54e20b4 | 3633 | |
45247bf2 | 3634 | attach_flow: |
948993f2 | 3635 | flow->encaps[out_index].e = e; |
8c4dc42b EB |
3636 | list_add(&flow->encaps[out_index].list, &e->flows); |
3637 | flow->encaps[out_index].index = out_index; | |
45247bf2 | 3638 | *encap_dev = e->out_dev; |
8c4dc42b | 3639 | if (e->flags & MLX5_ENCAP_ENTRY_VALID) { |
2b688ea5 | 3640 | attr->dests[out_index].pkt_reformat = e->pkt_reformat; |
8c4dc42b | 3641 | attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID; |
0ad060ee | 3642 | *encap_valid = true; |
8c4dc42b | 3643 | } else { |
0ad060ee | 3644 | *encap_valid = false; |
8c4dc42b | 3645 | } |
61086f39 | 3646 | mutex_unlock(&esw->offloads.encap_tbl_lock); |
45247bf2 | 3647 | |
232c0013 | 3648 | return err; |
a54e20b4 HHZ |
3649 | |
3650 | out_err: | |
61086f39 | 3651 | mutex_unlock(&esw->offloads.encap_tbl_lock); |
d589e785 VB |
3652 | if (e) |
3653 | mlx5e_encap_put(priv, e); | |
a54e20b4 | 3654 | return err; |
2a4b6526 VB |
3655 | |
3656 | out_err_init: | |
3657 | mutex_unlock(&esw->offloads.encap_tbl_lock); | |
3658 | kfree(tun_info); | |
3659 | kfree(e); | |
3660 | return err; | |
a54e20b4 HHZ |
3661 | } |
3662 | ||
14e6b038 EC |
3663 | static int mlx5e_attach_decap(struct mlx5e_priv *priv, |
3664 | struct mlx5e_tc_flow *flow, | |
3665 | struct netlink_ext_ack *extack) | |
3666 | { | |
3667 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
3668 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; | |
3669 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
3670 | struct mlx5e_decap_entry *d; | |
3671 | struct mlx5e_decap_key key; | |
3672 | uintptr_t hash_key; | |
28619046 | 3673 | int err = 0; |
14e6b038 EC |
3674 | |
3675 | parse_attr = attr->parse_attr; | |
3676 | if (sizeof(parse_attr->eth) > MLX5_CAP_ESW(priv->mdev, max_encap_header_size)) { | |
3677 | NL_SET_ERR_MSG_MOD(extack, | |
3678 | "encap header larger than max supported"); | |
3679 | return -EOPNOTSUPP; | |
3680 | } | |
3681 | ||
3682 | key.key = parse_attr->eth; | |
3683 | hash_key = hash_decap_info(&key); | |
3684 | mutex_lock(&esw->offloads.decap_tbl_lock); | |
3685 | d = mlx5e_decap_get(priv, &key, hash_key); | |
3686 | if (d) { | |
3687 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
3688 | wait_for_completion(&d->res_ready); | |
3689 | mutex_lock(&esw->offloads.decap_tbl_lock); | |
3690 | if (d->compl_result) { | |
3691 | err = -EREMOTEIO; | |
3692 | goto out_free; | |
3693 | } | |
3694 | goto found; | |
3695 | } | |
3696 | ||
3697 | d = kzalloc(sizeof(*d), GFP_KERNEL); | |
3698 | if (!d) { | |
3699 | err = -ENOMEM; | |
3700 | goto out_err; | |
3701 | } | |
3702 | ||
3703 | d->key = key; | |
3704 | refcount_set(&d->refcnt, 1); | |
3705 | init_completion(&d->res_ready); | |
3706 | INIT_LIST_HEAD(&d->flows); | |
3707 | hash_add_rcu(esw->offloads.decap_tbl, &d->hlist, hash_key); | |
3708 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
3709 | ||
3710 | d->pkt_reformat = mlx5_packet_reformat_alloc(priv->mdev, | |
3711 | MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2, | |
3712 | sizeof(parse_attr->eth), | |
3713 | &parse_attr->eth, | |
3714 | MLX5_FLOW_NAMESPACE_FDB); | |
3715 | if (IS_ERR(d->pkt_reformat)) { | |
3716 | err = PTR_ERR(d->pkt_reformat); | |
3717 | d->compl_result = err; | |
3718 | } | |
3719 | mutex_lock(&esw->offloads.decap_tbl_lock); | |
3720 | complete_all(&d->res_ready); | |
3721 | if (err) | |
3722 | goto out_free; | |
3723 | ||
3724 | found: | |
3725 | flow->decap_reformat = d; | |
3726 | attr->decap_pkt_reformat = d->pkt_reformat; | |
3727 | list_add(&flow->l3_to_l2_reformat, &d->flows); | |
3728 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
3729 | return 0; | |
3730 | ||
3731 | out_free: | |
3732 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
3733 | mlx5e_decap_put(priv, d); | |
3734 | return err; | |
3735 | ||
3736 | out_err: | |
3737 | mutex_unlock(&esw->offloads.decap_tbl_lock); | |
3738 | return err; | |
3739 | } | |
3740 | ||
1482bd3d | 3741 | static int parse_tc_vlan_action(struct mlx5e_priv *priv, |
73867881 | 3742 | const struct flow_action_entry *act, |
1482bd3d JL |
3743 | struct mlx5_esw_flow_attr *attr, |
3744 | u32 *action) | |
3745 | { | |
cc495188 JL |
3746 | u8 vlan_idx = attr->total_vlan; |
3747 | ||
3748 | if (vlan_idx >= MLX5_FS_VLAN_DEPTH) | |
3749 | return -EOPNOTSUPP; | |
3750 | ||
73867881 PNA |
3751 | switch (act->id) { |
3752 | case FLOW_ACTION_VLAN_POP: | |
cc495188 JL |
3753 | if (vlan_idx) { |
3754 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, | |
3755 | MLX5_FS_VLAN_DEPTH)) | |
3756 | return -EOPNOTSUPP; | |
3757 | ||
3758 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2; | |
3759 | } else { | |
3760 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
3761 | } | |
73867881 PNA |
3762 | break; |
3763 | case FLOW_ACTION_VLAN_PUSH: | |
3764 | attr->vlan_vid[vlan_idx] = act->vlan.vid; | |
3765 | attr->vlan_prio[vlan_idx] = act->vlan.prio; | |
3766 | attr->vlan_proto[vlan_idx] = act->vlan.proto; | |
cc495188 JL |
3767 | if (!attr->vlan_proto[vlan_idx]) |
3768 | attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q); | |
3769 | ||
3770 | if (vlan_idx) { | |
3771 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, | |
3772 | MLX5_FS_VLAN_DEPTH)) | |
3773 | return -EOPNOTSUPP; | |
3774 | ||
3775 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2; | |
3776 | } else { | |
3777 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) && | |
73867881 PNA |
3778 | (act->vlan.proto != htons(ETH_P_8021Q) || |
3779 | act->vlan.prio)) | |
cc495188 JL |
3780 | return -EOPNOTSUPP; |
3781 | ||
3782 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH; | |
1482bd3d | 3783 | } |
73867881 PNA |
3784 | break; |
3785 | default: | |
bdc837ee | 3786 | return -EINVAL; |
1482bd3d JL |
3787 | } |
3788 | ||
cc495188 JL |
3789 | attr->total_vlan = vlan_idx + 1; |
3790 | ||
1482bd3d JL |
3791 | return 0; |
3792 | } | |
3793 | ||
d34eb2fc OG |
3794 | static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev, |
3795 | struct net_device *out_dev) | |
3796 | { | |
3797 | struct net_device *fdb_out_dev = out_dev; | |
3798 | struct net_device *uplink_upper; | |
3799 | ||
3800 | rcu_read_lock(); | |
3801 | uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev); | |
3802 | if (uplink_upper && netif_is_lag_master(uplink_upper) && | |
3803 | uplink_upper == out_dev) { | |
3804 | fdb_out_dev = uplink_dev; | |
3805 | } else if (netif_is_lag_master(out_dev)) { | |
3806 | fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev)); | |
3807 | if (fdb_out_dev && | |
3808 | (!mlx5e_eswitch_rep(fdb_out_dev) || | |
3809 | !netdev_port_same_parent_id(fdb_out_dev, uplink_dev))) | |
3810 | fdb_out_dev = NULL; | |
3811 | } | |
3812 | rcu_read_unlock(); | |
3813 | return fdb_out_dev; | |
3814 | } | |
3815 | ||
278748a9 EB |
3816 | static int add_vlan_push_action(struct mlx5e_priv *priv, |
3817 | struct mlx5_esw_flow_attr *attr, | |
3818 | struct net_device **out_dev, | |
3819 | u32 *action) | |
3820 | { | |
3821 | struct net_device *vlan_dev = *out_dev; | |
3822 | struct flow_action_entry vlan_act = { | |
3823 | .id = FLOW_ACTION_VLAN_PUSH, | |
3824 | .vlan.vid = vlan_dev_vlan_id(vlan_dev), | |
3825 | .vlan.proto = vlan_dev_vlan_proto(vlan_dev), | |
3826 | .vlan.prio = 0, | |
3827 | }; | |
3828 | int err; | |
3829 | ||
3830 | err = parse_tc_vlan_action(priv, &vlan_act, attr, action); | |
3831 | if (err) | |
3832 | return err; | |
3833 | ||
3834 | *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), | |
3835 | dev_get_iflink(vlan_dev)); | |
3836 | if (is_vlan_dev(*out_dev)) | |
3837 | err = add_vlan_push_action(priv, attr, out_dev, action); | |
3838 | ||
3839 | return err; | |
3840 | } | |
3841 | ||
35a605db EB |
3842 | static int add_vlan_pop_action(struct mlx5e_priv *priv, |
3843 | struct mlx5_esw_flow_attr *attr, | |
3844 | u32 *action) | |
3845 | { | |
35a605db EB |
3846 | struct flow_action_entry vlan_act = { |
3847 | .id = FLOW_ACTION_VLAN_POP, | |
3848 | }; | |
70f478ca | 3849 | int nest_level, err = 0; |
35a605db | 3850 | |
70f478ca DL |
3851 | nest_level = attr->parse_attr->filter_dev->lower_level - |
3852 | priv->netdev->lower_level; | |
35a605db EB |
3853 | while (nest_level--) { |
3854 | err = parse_tc_vlan_action(priv, &vlan_act, attr, action); | |
3855 | if (err) | |
3856 | return err; | |
3857 | } | |
3858 | ||
3859 | return err; | |
3860 | } | |
3861 | ||
32134847 MD |
3862 | static bool same_hw_reps(struct mlx5e_priv *priv, |
3863 | struct net_device *peer_netdev) | |
3864 | { | |
3865 | struct mlx5e_priv *peer_priv; | |
3866 | ||
3867 | peer_priv = netdev_priv(peer_netdev); | |
3868 | ||
3869 | return mlx5e_eswitch_rep(priv->netdev) && | |
3870 | mlx5e_eswitch_rep(peer_netdev) && | |
3871 | same_hw_devs(priv, peer_priv); | |
3872 | } | |
3873 | ||
3874 | static bool is_lag_dev(struct mlx5e_priv *priv, | |
3875 | struct net_device *peer_netdev) | |
3876 | { | |
3877 | return ((mlx5_lag_is_sriov(priv->mdev) || | |
3878 | mlx5_lag_is_multipath(priv->mdev)) && | |
3879 | same_hw_reps(priv, peer_netdev)); | |
3880 | } | |
3881 | ||
f6dc1264 PB |
3882 | bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv, |
3883 | struct net_device *out_dev) | |
3884 | { | |
32134847 MD |
3885 | if (is_merged_eswitch_vfs(priv, out_dev)) |
3886 | return true; | |
3887 | ||
3888 | if (is_lag_dev(priv, out_dev)) | |
f6dc1264 PB |
3889 | return true; |
3890 | ||
3891 | return mlx5e_eswitch_rep(out_dev) && | |
32134847 | 3892 | same_port_devs(priv, netdev_priv(out_dev)); |
f6dc1264 PB |
3893 | } |
3894 | ||
554fe75c DL |
3895 | static bool is_duplicated_output_device(struct net_device *dev, |
3896 | struct net_device *out_dev, | |
3897 | int *ifindexes, int if_count, | |
3898 | struct netlink_ext_ack *extack) | |
3899 | { | |
3900 | int i; | |
3901 | ||
3902 | for (i = 0; i < if_count; i++) { | |
3903 | if (ifindexes[i] == out_dev->ifindex) { | |
3904 | NL_SET_ERR_MSG_MOD(extack, | |
3905 | "can't duplicate output to same device"); | |
3906 | netdev_err(dev, "can't duplicate output to same device: %s\n", | |
3907 | out_dev->name); | |
3908 | return true; | |
3909 | } | |
3910 | } | |
3911 | ||
3912 | return false; | |
3913 | } | |
3914 | ||
2fbbc30d EC |
3915 | static int mlx5_validate_goto_chain(struct mlx5_eswitch *esw, |
3916 | struct mlx5e_tc_flow *flow, | |
3917 | const struct flow_action_entry *act, | |
3918 | u32 actions, | |
3919 | struct netlink_ext_ack *extack) | |
3920 | { | |
3921 | u32 max_chain = mlx5_esw_chains_get_chain_range(esw); | |
3922 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; | |
3923 | bool ft_flow = mlx5e_is_ft_flow(flow); | |
3924 | u32 dest_chain = act->chain_index; | |
3925 | ||
3926 | if (ft_flow) { | |
3927 | NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported"); | |
3928 | return -EOPNOTSUPP; | |
3929 | } | |
3930 | ||
3931 | if (!mlx5_esw_chains_backwards_supported(esw) && | |
3932 | dest_chain <= attr->chain) { | |
3933 | NL_SET_ERR_MSG_MOD(extack, | |
3934 | "Goto lower numbered chain isn't supported"); | |
3935 | return -EOPNOTSUPP; | |
3936 | } | |
3937 | if (dest_chain > max_chain) { | |
3938 | NL_SET_ERR_MSG_MOD(extack, | |
3939 | "Requested destination chain is out of supported range"); | |
3940 | return -EOPNOTSUPP; | |
3941 | } | |
3942 | ||
3943 | if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT | | |
3944 | MLX5_FLOW_CONTEXT_ACTION_DECAP) && | |
3945 | !MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, reformat_and_fwd_to_table)) { | |
3946 | NL_SET_ERR_MSG_MOD(extack, | |
3947 | "Goto chain is not allowed if action has reformat or decap"); | |
3948 | return -EOPNOTSUPP; | |
3949 | } | |
3950 | ||
3951 | return 0; | |
3952 | } | |
3953 | ||
613f53fe EC |
3954 | static int verify_uplink_forwarding(struct mlx5e_priv *priv, |
3955 | struct mlx5e_tc_flow *flow, | |
3956 | struct net_device *out_dev, | |
3957 | struct netlink_ext_ack *extack) | |
3958 | { | |
3959 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
3960 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; | |
3961 | struct mlx5e_rep_priv *rep_priv; | |
3962 | ||
3963 | /* Forwarding non encapsulated traffic between | |
3964 | * uplink ports is allowed only if | |
3965 | * termination_table_raw_traffic cap is set. | |
3966 | * | |
3967 | * Input vport was stored esw_attr->in_rep. | |
3968 | * In LAG case, *priv* is the private data of | |
3969 | * uplink which may be not the input vport. | |
3970 | */ | |
3971 | rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep); | |
3972 | ||
3973 | if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) && | |
3974 | mlx5e_eswitch_uplink_rep(out_dev))) | |
3975 | return 0; | |
3976 | ||
3977 | if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev, | |
3978 | termination_table_raw_traffic)) { | |
3979 | NL_SET_ERR_MSG_MOD(extack, | |
3980 | "devices are both uplink, can't offload forwarding"); | |
3981 | pr_err("devices %s %s are both uplink, can't offload forwarding\n", | |
3982 | priv->netdev->name, out_dev->name); | |
3983 | return -EOPNOTSUPP; | |
3984 | } else if (out_dev != rep_priv->netdev) { | |
3985 | NL_SET_ERR_MSG_MOD(extack, | |
3986 | "devices are not the same uplink, can't offload forwarding"); | |
3987 | pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n", | |
3988 | priv->netdev->name, out_dev->name); | |
3989 | return -EOPNOTSUPP; | |
3990 | } | |
3991 | return 0; | |
3992 | } | |
3993 | ||
73867881 PNA |
3994 | static int parse_tc_fdb_actions(struct mlx5e_priv *priv, |
3995 | struct flow_action *flow_action, | |
e98bedf5 | 3996 | struct mlx5e_tc_flow *flow, |
14e6b038 EC |
3997 | struct netlink_ext_ack *extack, |
3998 | struct net_device *filter_dev) | |
03a9d11e | 3999 | { |
73867881 | 4000 | struct pedit_headers_action hdrs[2] = {}; |
bf07aa73 | 4001 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
ecf5bb79 | 4002 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
6f9af8ff | 4003 | struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; |
1d447a39 | 4004 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
73867881 | 4005 | const struct ip_tunnel_info *info = NULL; |
554fe75c | 4006 | int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS]; |
84179981 | 4007 | bool ft_flow = mlx5e_is_ft_flow(flow); |
73867881 | 4008 | const struct flow_action_entry *act; |
0a7fcb78 PB |
4009 | bool encap = false, decap = false; |
4010 | u32 action = attr->action; | |
554fe75c | 4011 | int err, i, if_count = 0; |
f828ca6a | 4012 | bool mpls_push = false; |
03a9d11e | 4013 | |
73867881 | 4014 | if (!flow_action_has_entries(flow_action)) |
03a9d11e OG |
4015 | return -EINVAL; |
4016 | ||
53eca1f3 JK |
4017 | if (!flow_action_hw_stats_check(flow_action, extack, |
4018 | FLOW_ACTION_HW_STATS_DELAYED_BIT)) | |
319a1d19 JP |
4019 | return -EOPNOTSUPP; |
4020 | ||
73867881 PNA |
4021 | flow_action_for_each(i, act, flow_action) { |
4022 | switch (act->id) { | |
4023 | case FLOW_ACTION_DROP: | |
1cab1cd7 OG |
4024 | action |= MLX5_FLOW_CONTEXT_ACTION_DROP | |
4025 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
73867881 | 4026 | break; |
f828ca6a EC |
4027 | case FLOW_ACTION_MPLS_PUSH: |
4028 | if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, | |
4029 | reformat_l2_to_l3_tunnel) || | |
4030 | act->mpls_push.proto != htons(ETH_P_MPLS_UC)) { | |
4031 | NL_SET_ERR_MSG_MOD(extack, | |
4032 | "mpls push is supported only for mpls_uc protocol"); | |
4033 | return -EOPNOTSUPP; | |
4034 | } | |
4035 | mpls_push = true; | |
4036 | break; | |
14e6b038 EC |
4037 | case FLOW_ACTION_MPLS_POP: |
4038 | /* we only support mpls pop if it is the first action | |
4039 | * and the filter net device is bareudp. Subsequent | |
4040 | * actions can be pedit and the last can be mirred | |
4041 | * egress redirect. | |
4042 | */ | |
4043 | if (i) { | |
4044 | NL_SET_ERR_MSG_MOD(extack, | |
4045 | "mpls pop supported only as first action"); | |
4046 | return -EOPNOTSUPP; | |
4047 | } | |
4048 | if (!netif_is_bareudp(filter_dev)) { | |
4049 | NL_SET_ERR_MSG_MOD(extack, | |
4050 | "mpls pop supported only on bareudp devices"); | |
4051 | return -EOPNOTSUPP; | |
4052 | } | |
4053 | ||
4054 | parse_attr->eth.h_proto = act->mpls_pop.proto; | |
4055 | action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT; | |
4056 | flow_flag_set(flow, L3_TO_L2_DECAP); | |
4057 | break; | |
73867881 PNA |
4058 | case FLOW_ACTION_MANGLE: |
4059 | case FLOW_ACTION_ADD: | |
4060 | err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB, | |
582234b4 | 4061 | parse_attr, hdrs, flow, extack); |
d7e75a32 OG |
4062 | if (err) |
4063 | return err; | |
4064 | ||
582234b4 EC |
4065 | if (!flow_flag_test(flow, L3_TO_L2_DECAP)) { |
4066 | action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; | |
4067 | attr->split_count = attr->out_count; | |
4068 | } | |
73867881 PNA |
4069 | break; |
4070 | case FLOW_ACTION_CSUM: | |
1cab1cd7 | 4071 | if (csum_offload_supported(priv, action, |
73867881 PNA |
4072 | act->csum_flags, extack)) |
4073 | break; | |
26c02749 OG |
4074 | |
4075 | return -EOPNOTSUPP; | |
73867881 PNA |
4076 | case FLOW_ACTION_REDIRECT: |
4077 | case FLOW_ACTION_MIRRED: { | |
03a9d11e | 4078 | struct mlx5e_priv *out_priv; |
592d3651 | 4079 | struct net_device *out_dev; |
03a9d11e | 4080 | |
73867881 | 4081 | out_dev = act->dev; |
ef381359 OS |
4082 | if (!out_dev) { |
4083 | /* out_dev is NULL when filters with | |
4084 | * non-existing mirred device are replayed to | |
4085 | * the driver. | |
4086 | */ | |
4087 | return -EINVAL; | |
4088 | } | |
03a9d11e | 4089 | |
f828ca6a EC |
4090 | if (mpls_push && !netif_is_bareudp(out_dev)) { |
4091 | NL_SET_ERR_MSG_MOD(extack, | |
4092 | "mpls is supported only through a bareudp device"); | |
4093 | return -EOPNOTSUPP; | |
4094 | } | |
4095 | ||
84179981 PB |
4096 | if (ft_flow && out_dev == priv->netdev) { |
4097 | /* Ignore forward to self rules generated | |
4098 | * by adding both mlx5 devs to the flow table | |
4099 | * block on a normal nft offload setup. | |
4100 | */ | |
4101 | return -EOPNOTSUPP; | |
4102 | } | |
4103 | ||
592d3651 | 4104 | if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) { |
e98bedf5 EB |
4105 | NL_SET_ERR_MSG_MOD(extack, |
4106 | "can't support more output ports, can't offload forwarding"); | |
4ccd83f4 RD |
4107 | netdev_warn(priv->netdev, |
4108 | "can't support more than %d output ports, can't offload forwarding\n", | |
4109 | attr->out_count); | |
592d3651 CM |
4110 | return -EOPNOTSUPP; |
4111 | } | |
4112 | ||
f493f155 EB |
4113 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
4114 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
b6a4ac24 VB |
4115 | if (encap) { |
4116 | parse_attr->mirred_ifindex[attr->out_count] = | |
4117 | out_dev->ifindex; | |
4118 | parse_attr->tun_info[attr->out_count] = dup_tun_info(info); | |
4119 | if (!parse_attr->tun_info[attr->out_count]) | |
4120 | return -ENOMEM; | |
4121 | encap = false; | |
4122 | attr->dests[attr->out_count].flags |= | |
4123 | MLX5_ESW_DEST_ENCAP; | |
4124 | attr->out_count++; | |
4125 | /* attr->dests[].rep is resolved when we | |
4126 | * handle encap | |
4127 | */ | |
4128 | } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) { | |
7ba58ba7 RL |
4129 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
4130 | struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH); | |
7ba58ba7 | 4131 | |
554fe75c DL |
4132 | if (is_duplicated_output_device(priv->netdev, |
4133 | out_dev, | |
4134 | ifindexes, | |
4135 | if_count, | |
4136 | extack)) | |
4137 | return -EOPNOTSUPP; | |
4138 | ||
4139 | ifindexes[if_count] = out_dev->ifindex; | |
4140 | if_count++; | |
4141 | ||
d34eb2fc OG |
4142 | out_dev = get_fdb_out_dev(uplink_dev, out_dev); |
4143 | if (!out_dev) | |
4144 | return -ENODEV; | |
7ba58ba7 | 4145 | |
278748a9 EB |
4146 | if (is_vlan_dev(out_dev)) { |
4147 | err = add_vlan_push_action(priv, attr, | |
4148 | &out_dev, | |
4149 | &action); | |
4150 | if (err) | |
4151 | return err; | |
4152 | } | |
f6dc1264 | 4153 | |
35a605db EB |
4154 | if (is_vlan_dev(parse_attr->filter_dev)) { |
4155 | err = add_vlan_pop_action(priv, attr, | |
4156 | &action); | |
4157 | if (err) | |
4158 | return err; | |
4159 | } | |
278748a9 | 4160 | |
613f53fe EC |
4161 | err = verify_uplink_forwarding(priv, flow, out_dev, extack); |
4162 | if (err) | |
4163 | return err; | |
ffec9702 | 4164 | |
f6dc1264 PB |
4165 | if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) { |
4166 | NL_SET_ERR_MSG_MOD(extack, | |
4167 | "devices are not on same switch HW, can't offload forwarding"); | |
a0646c88 | 4168 | return -EOPNOTSUPP; |
f6dc1264 | 4169 | } |
a0646c88 | 4170 | |
a54e20b4 | 4171 | out_priv = netdev_priv(out_dev); |
1d447a39 | 4172 | rpriv = out_priv->ppriv; |
df65a573 EB |
4173 | attr->dests[attr->out_count].rep = rpriv->rep; |
4174 | attr->dests[attr->out_count].mdev = out_priv->mdev; | |
4175 | attr->out_count++; | |
ef381359 OS |
4176 | } else if (parse_attr->filter_dev != priv->netdev) { |
4177 | /* All mlx5 devices are called to configure | |
4178 | * high level device filters. Therefore, the | |
4179 | * *attempt* to install a filter on invalid | |
4180 | * eswitch should not trigger an explicit error | |
4181 | */ | |
4182 | return -EINVAL; | |
a54e20b4 | 4183 | } else { |
e98bedf5 EB |
4184 | NL_SET_ERR_MSG_MOD(extack, |
4185 | "devices are not on same switch HW, can't offload forwarding"); | |
4ccd83f4 RD |
4186 | netdev_warn(priv->netdev, |
4187 | "devices %s %s not on same switch HW, can't offload forwarding\n", | |
4188 | priv->netdev->name, | |
4189 | out_dev->name); | |
03a9d11e OG |
4190 | return -EINVAL; |
4191 | } | |
73867881 PNA |
4192 | } |
4193 | break; | |
4194 | case FLOW_ACTION_TUNNEL_ENCAP: | |
4195 | info = act->tunnel; | |
a54e20b4 HHZ |
4196 | if (info) |
4197 | encap = true; | |
4198 | else | |
4199 | return -EOPNOTSUPP; | |
1482bd3d | 4200 | |
73867881 PNA |
4201 | break; |
4202 | case FLOW_ACTION_VLAN_PUSH: | |
4203 | case FLOW_ACTION_VLAN_POP: | |
76b496b1 EB |
4204 | if (act->id == FLOW_ACTION_VLAN_PUSH && |
4205 | (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) { | |
4206 | /* Replace vlan pop+push with vlan modify */ | |
4207 | action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
4208 | err = add_vlan_rewrite_action(priv, | |
4209 | MLX5_FLOW_NAMESPACE_FDB, | |
4210 | act, parse_attr, hdrs, | |
4211 | &action, extack); | |
4212 | } else { | |
4213 | err = parse_tc_vlan_action(priv, act, attr, &action); | |
4214 | } | |
1482bd3d JL |
4215 | if (err) |
4216 | return err; | |
4217 | ||
bdc837ee EB |
4218 | attr->split_count = attr->out_count; |
4219 | break; | |
4220 | case FLOW_ACTION_VLAN_MANGLE: | |
4221 | err = add_vlan_rewrite_action(priv, | |
4222 | MLX5_FLOW_NAMESPACE_FDB, | |
4223 | act, parse_attr, hdrs, | |
4224 | &action, extack); | |
4225 | if (err) | |
4226 | return err; | |
4227 | ||
e85e02ba | 4228 | attr->split_count = attr->out_count; |
73867881 PNA |
4229 | break; |
4230 | case FLOW_ACTION_TUNNEL_DECAP: | |
0a7fcb78 | 4231 | decap = true; |
73867881 | 4232 | break; |
2fbbc30d EC |
4233 | case FLOW_ACTION_GOTO: |
4234 | err = mlx5_validate_goto_chain(esw, flow, act, action, | |
4235 | extack); | |
4236 | if (err) | |
4237 | return err; | |
bf07aa73 | 4238 | |
e88afe75 | 4239 | action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; |
2fbbc30d | 4240 | attr->dest_chain = act->chain_index; |
73867881 | 4241 | break; |
4c3844d9 PB |
4242 | case FLOW_ACTION_CT: |
4243 | err = mlx5_tc_ct_parse_action(priv, attr, act, extack); | |
4244 | if (err) | |
4245 | return err; | |
4246 | ||
4247 | flow_flag_set(flow, CT); | |
4248 | break; | |
73867881 | 4249 | default: |
2cc1cb1d TZ |
4250 | NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); |
4251 | return -EOPNOTSUPP; | |
bf07aa73 | 4252 | } |
03a9d11e | 4253 | } |
bdd66ac0 | 4254 | |
0bac1194 EB |
4255 | if (MLX5_CAP_GEN(esw->dev, prio_tag_required) && |
4256 | action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) { | |
4257 | /* For prio tag mode, replace vlan pop with rewrite vlan prio | |
4258 | * tag rewrite. | |
4259 | */ | |
4260 | action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
4261 | err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs, | |
4262 | &action, extack); | |
4263 | if (err) | |
4264 | return err; | |
4265 | } | |
4266 | ||
c500c86b PNA |
4267 | if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || |
4268 | hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { | |
84be899f | 4269 | err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB, |
27c11b6b | 4270 | parse_attr, hdrs, &action, extack); |
c500c86b PNA |
4271 | if (err) |
4272 | return err; | |
27c11b6b EB |
4273 | /* in case all pedit actions are skipped, remove the MOD_HDR |
4274 | * flag. we might have set split_count either by pedit or | |
4275 | * pop/push. if there is no pop/push either, reset it too. | |
4276 | */ | |
6ae4a6a5 | 4277 | if (parse_attr->mod_hdr_acts.num_actions == 0) { |
27c11b6b | 4278 | action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
6ae4a6a5 | 4279 | dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts); |
27c11b6b EB |
4280 | if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) || |
4281 | (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))) | |
4282 | attr->split_count = 0; | |
4283 | } | |
c500c86b PNA |
4284 | } |
4285 | ||
1cab1cd7 | 4286 | attr->action = action; |
73867881 | 4287 | if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) |
bdd66ac0 OG |
4288 | return -EOPNOTSUPP; |
4289 | ||
e88afe75 | 4290 | if (attr->dest_chain) { |
0a7fcb78 PB |
4291 | if (decap) { |
4292 | /* It can be supported if we'll create a mapping for | |
4293 | * the tunnel device only (without tunnel), and set | |
4294 | * this tunnel id with this decap flow. | |
4295 | * | |
4296 | * On restore (miss), we'll just set this saved tunnel | |
4297 | * device. | |
4298 | */ | |
4299 | ||
4300 | NL_SET_ERR_MSG(extack, | |
4301 | "Decap with goto isn't supported"); | |
4302 | netdev_warn(priv->netdev, | |
4303 | "Decap with goto isn't supported"); | |
4304 | return -EOPNOTSUPP; | |
4305 | } | |
4306 | ||
e88afe75 | 4307 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { |
61644c3d RD |
4308 | NL_SET_ERR_MSG_MOD(extack, |
4309 | "Mirroring goto chain rules isn't supported"); | |
e88afe75 OG |
4310 | return -EOPNOTSUPP; |
4311 | } | |
4312 | attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
4313 | } | |
4314 | ||
ae2741e2 VB |
4315 | if (!(attr->action & |
4316 | (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) { | |
61644c3d RD |
4317 | NL_SET_ERR_MSG_MOD(extack, |
4318 | "Rule must have at least one forward/drop action"); | |
ae2741e2 VB |
4319 | return -EOPNOTSUPP; |
4320 | } | |
4321 | ||
e85e02ba | 4322 | if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) { |
e98bedf5 EB |
4323 | NL_SET_ERR_MSG_MOD(extack, |
4324 | "current firmware doesn't support split rule for port mirroring"); | |
592d3651 CM |
4325 | netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n"); |
4326 | return -EOPNOTSUPP; | |
4327 | } | |
4328 | ||
31c8eba5 | 4329 | return 0; |
03a9d11e OG |
4330 | } |
4331 | ||
226f2ca3 | 4332 | static void get_flags(int flags, unsigned long *flow_flags) |
60bd4af8 | 4333 | { |
226f2ca3 | 4334 | unsigned long __flow_flags = 0; |
60bd4af8 | 4335 | |
226f2ca3 VB |
4336 | if (flags & MLX5_TC_FLAG(INGRESS)) |
4337 | __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS); | |
4338 | if (flags & MLX5_TC_FLAG(EGRESS)) | |
4339 | __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS); | |
60bd4af8 | 4340 | |
226f2ca3 VB |
4341 | if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) |
4342 | __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH); | |
4343 | if (flags & MLX5_TC_FLAG(NIC_OFFLOAD)) | |
4344 | __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC); | |
84179981 PB |
4345 | if (flags & MLX5_TC_FLAG(FT_OFFLOAD)) |
4346 | __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT); | |
d9ee0491 | 4347 | |
60bd4af8 OG |
4348 | *flow_flags = __flow_flags; |
4349 | } | |
4350 | ||
05866c82 OG |
4351 | static const struct rhashtable_params tc_ht_params = { |
4352 | .head_offset = offsetof(struct mlx5e_tc_flow, node), | |
4353 | .key_offset = offsetof(struct mlx5e_tc_flow, cookie), | |
4354 | .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie), | |
4355 | .automatic_shrinking = true, | |
4356 | }; | |
4357 | ||
226f2ca3 VB |
4358 | static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, |
4359 | unsigned long flags) | |
05866c82 | 4360 | { |
655dc3d2 OG |
4361 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
4362 | struct mlx5e_rep_priv *uplink_rpriv; | |
4363 | ||
226f2ca3 | 4364 | if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) { |
655dc3d2 | 4365 | uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); |
ec1366c2 | 4366 | return &uplink_rpriv->uplink_priv.tc_ht; |
d9ee0491 | 4367 | } else /* NIC offload */ |
655dc3d2 | 4368 | return &priv->fs.tc.ht; |
05866c82 OG |
4369 | } |
4370 | ||
04de7dda RD |
4371 | static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow) |
4372 | { | |
1418ddd9 | 4373 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
b05af6aa | 4374 | bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK && |
226f2ca3 | 4375 | flow_flag_test(flow, INGRESS); |
1418ddd9 AH |
4376 | bool act_is_encap = !!(attr->action & |
4377 | MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT); | |
4378 | bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom, | |
4379 | MLX5_DEVCOM_ESW_OFFLOADS); | |
4380 | ||
10fbb1cd RD |
4381 | if (!esw_paired) |
4382 | return false; | |
4383 | ||
4384 | if ((mlx5_lag_is_sriov(attr->in_mdev) || | |
4385 | mlx5_lag_is_multipath(attr->in_mdev)) && | |
4386 | (is_rep_ingress || act_is_encap)) | |
4387 | return true; | |
4388 | ||
4389 | return false; | |
04de7dda RD |
4390 | } |
4391 | ||
a88780a9 RD |
4392 | static int |
4393 | mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size, | |
226f2ca3 | 4394 | struct flow_cls_offload *f, unsigned long flow_flags, |
a88780a9 RD |
4395 | struct mlx5e_tc_flow_parse_attr **__parse_attr, |
4396 | struct mlx5e_tc_flow **__flow) | |
e3a2b7ed | 4397 | { |
17091853 | 4398 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
3bc4b7bf | 4399 | struct mlx5e_tc_flow *flow; |
5a7e5bcb | 4400 | int out_index, err; |
e3a2b7ed | 4401 | |
65ba8fb7 | 4402 | flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL); |
1b9a07ee | 4403 | parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL); |
17091853 | 4404 | if (!parse_attr || !flow) { |
e3a2b7ed AV |
4405 | err = -ENOMEM; |
4406 | goto err_free; | |
4407 | } | |
4408 | ||
4409 | flow->cookie = f->cookie; | |
65ba8fb7 | 4410 | flow->flags = flow_flags; |
655dc3d2 | 4411 | flow->priv = priv; |
5a7e5bcb VB |
4412 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) |
4413 | INIT_LIST_HEAD(&flow->encaps[out_index].list); | |
4414 | INIT_LIST_HEAD(&flow->mod_hdr); | |
4415 | INIT_LIST_HEAD(&flow->hairpin); | |
14e6b038 | 4416 | INIT_LIST_HEAD(&flow->l3_to_l2_reformat); |
5a7e5bcb | 4417 | refcount_set(&flow->refcnt, 1); |
95435ad7 | 4418 | init_completion(&flow->init_done); |
e3a2b7ed | 4419 | |
a88780a9 RD |
4420 | *__flow = flow; |
4421 | *__parse_attr = parse_attr; | |
4422 | ||
4423 | return 0; | |
4424 | ||
4425 | err_free: | |
4426 | kfree(flow); | |
4427 | kvfree(parse_attr); | |
4428 | return err; | |
4429 | } | |
4430 | ||
988ab9c7 TZ |
4431 | static void |
4432 | mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr, | |
4433 | struct mlx5e_priv *priv, | |
4434 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
f9e30088 | 4435 | struct flow_cls_offload *f, |
988ab9c7 TZ |
4436 | struct mlx5_eswitch_rep *in_rep, |
4437 | struct mlx5_core_dev *in_mdev) | |
4438 | { | |
4439 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
4440 | ||
4441 | esw_attr->parse_attr = parse_attr; | |
4442 | esw_attr->chain = f->common.chain_index; | |
ef01adae | 4443 | esw_attr->prio = f->common.prio; |
988ab9c7 TZ |
4444 | |
4445 | esw_attr->in_rep = in_rep; | |
4446 | esw_attr->in_mdev = in_mdev; | |
4447 | ||
4448 | if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) == | |
4449 | MLX5_COUNTER_SOURCE_ESWITCH) | |
4450 | esw_attr->counter_dev = in_mdev; | |
4451 | else | |
4452 | esw_attr->counter_dev = priv->mdev; | |
4453 | } | |
4454 | ||
71129676 | 4455 | static struct mlx5e_tc_flow * |
04de7dda | 4456 | __mlx5e_add_fdb_flow(struct mlx5e_priv *priv, |
f9e30088 | 4457 | struct flow_cls_offload *f, |
226f2ca3 | 4458 | unsigned long flow_flags, |
04de7dda RD |
4459 | struct net_device *filter_dev, |
4460 | struct mlx5_eswitch_rep *in_rep, | |
71129676 | 4461 | struct mlx5_core_dev *in_mdev) |
a88780a9 | 4462 | { |
f9e30088 | 4463 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); |
a88780a9 RD |
4464 | struct netlink_ext_ack *extack = f->common.extack; |
4465 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
4466 | struct mlx5e_tc_flow *flow; | |
4467 | int attr_size, err; | |
e3a2b7ed | 4468 | |
226f2ca3 | 4469 | flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH); |
a88780a9 RD |
4470 | attr_size = sizeof(struct mlx5_esw_flow_attr); |
4471 | err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, | |
4472 | &parse_attr, &flow); | |
4473 | if (err) | |
4474 | goto out; | |
988ab9c7 | 4475 | |
d11afc26 | 4476 | parse_attr->filter_dev = filter_dev; |
988ab9c7 TZ |
4477 | mlx5e_flow_esw_attr_init(flow->esw_attr, |
4478 | priv, parse_attr, | |
4479 | f, in_rep, in_mdev); | |
4480 | ||
54c177ca OS |
4481 | err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, |
4482 | f, filter_dev); | |
d11afc26 OS |
4483 | if (err) |
4484 | goto err_free; | |
a88780a9 | 4485 | |
14e6b038 | 4486 | err = parse_tc_fdb_actions(priv, &rule->action, flow, extack, filter_dev); |
a88780a9 RD |
4487 | if (err) |
4488 | goto err_free; | |
4489 | ||
4c3844d9 PB |
4490 | err = mlx5_tc_ct_parse_match(priv, &parse_attr->spec, f, extack); |
4491 | if (err) | |
4492 | goto err_free; | |
4493 | ||
7040632d | 4494 | err = mlx5e_tc_add_fdb_flow(priv, flow, extack); |
95435ad7 | 4495 | complete_all(&flow->init_done); |
ef06c9ee RD |
4496 | if (err) { |
4497 | if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev))) | |
4498 | goto err_free; | |
4499 | ||
b4a23329 | 4500 | add_unready_flow(flow); |
ef06c9ee | 4501 | } |
e3a2b7ed | 4502 | |
71129676 | 4503 | return flow; |
a88780a9 RD |
4504 | |
4505 | err_free: | |
5a7e5bcb | 4506 | mlx5e_flow_put(priv, flow); |
a88780a9 | 4507 | out: |
71129676 | 4508 | return ERR_PTR(err); |
a88780a9 RD |
4509 | } |
4510 | ||
f9e30088 | 4511 | static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f, |
95dc1902 | 4512 | struct mlx5e_tc_flow *flow, |
226f2ca3 | 4513 | unsigned long flow_flags) |
04de7dda RD |
4514 | { |
4515 | struct mlx5e_priv *priv = flow->priv, *peer_priv; | |
4516 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw; | |
4517 | struct mlx5_devcom *devcom = priv->mdev->priv.devcom; | |
4518 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
4519 | struct mlx5e_rep_priv *peer_urpriv; | |
4520 | struct mlx5e_tc_flow *peer_flow; | |
4521 | struct mlx5_core_dev *in_mdev; | |
4522 | int err = 0; | |
4523 | ||
4524 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
4525 | if (!peer_esw) | |
4526 | return -ENODEV; | |
4527 | ||
4528 | peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH); | |
4529 | peer_priv = netdev_priv(peer_urpriv->netdev); | |
4530 | ||
4531 | /* in_mdev is assigned of which the packet originated from. | |
4532 | * So packets redirected to uplink use the same mdev of the | |
4533 | * original flow and packets redirected from uplink use the | |
4534 | * peer mdev. | |
4535 | */ | |
b05af6aa | 4536 | if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK) |
04de7dda RD |
4537 | in_mdev = peer_priv->mdev; |
4538 | else | |
4539 | in_mdev = priv->mdev; | |
4540 | ||
4541 | parse_attr = flow->esw_attr->parse_attr; | |
95dc1902 | 4542 | peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags, |
71129676 JG |
4543 | parse_attr->filter_dev, |
4544 | flow->esw_attr->in_rep, in_mdev); | |
4545 | if (IS_ERR(peer_flow)) { | |
4546 | err = PTR_ERR(peer_flow); | |
04de7dda | 4547 | goto out; |
71129676 | 4548 | } |
04de7dda RD |
4549 | |
4550 | flow->peer_flow = peer_flow; | |
226f2ca3 | 4551 | flow_flag_set(flow, DUP); |
04de7dda RD |
4552 | mutex_lock(&esw->offloads.peer_mutex); |
4553 | list_add_tail(&flow->peer, &esw->offloads.peer_flows); | |
4554 | mutex_unlock(&esw->offloads.peer_mutex); | |
4555 | ||
4556 | out: | |
4557 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
4558 | return err; | |
4559 | } | |
4560 | ||
4561 | static int | |
4562 | mlx5e_add_fdb_flow(struct mlx5e_priv *priv, | |
f9e30088 | 4563 | struct flow_cls_offload *f, |
226f2ca3 | 4564 | unsigned long flow_flags, |
04de7dda RD |
4565 | struct net_device *filter_dev, |
4566 | struct mlx5e_tc_flow **__flow) | |
4567 | { | |
4568 | struct mlx5e_rep_priv *rpriv = priv->ppriv; | |
4569 | struct mlx5_eswitch_rep *in_rep = rpriv->rep; | |
4570 | struct mlx5_core_dev *in_mdev = priv->mdev; | |
4571 | struct mlx5e_tc_flow *flow; | |
4572 | int err; | |
4573 | ||
71129676 JG |
4574 | flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep, |
4575 | in_mdev); | |
4576 | if (IS_ERR(flow)) | |
4577 | return PTR_ERR(flow); | |
04de7dda RD |
4578 | |
4579 | if (is_peer_flow_needed(flow)) { | |
95dc1902 | 4580 | err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags); |
04de7dda RD |
4581 | if (err) { |
4582 | mlx5e_tc_del_fdb_flow(priv, flow); | |
4583 | goto out; | |
4584 | } | |
4585 | } | |
4586 | ||
4587 | *__flow = flow; | |
4588 | ||
4589 | return 0; | |
4590 | ||
4591 | out: | |
4592 | return err; | |
4593 | } | |
4594 | ||
a88780a9 RD |
4595 | static int |
4596 | mlx5e_add_nic_flow(struct mlx5e_priv *priv, | |
f9e30088 | 4597 | struct flow_cls_offload *f, |
226f2ca3 | 4598 | unsigned long flow_flags, |
d11afc26 | 4599 | struct net_device *filter_dev, |
a88780a9 RD |
4600 | struct mlx5e_tc_flow **__flow) |
4601 | { | |
f9e30088 | 4602 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); |
a88780a9 RD |
4603 | struct netlink_ext_ack *extack = f->common.extack; |
4604 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
4605 | struct mlx5e_tc_flow *flow; | |
4606 | int attr_size, err; | |
4607 | ||
bf07aa73 PB |
4608 | /* multi-chain not supported for NIC rules */ |
4609 | if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common)) | |
4610 | return -EOPNOTSUPP; | |
4611 | ||
226f2ca3 | 4612 | flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC); |
a88780a9 RD |
4613 | attr_size = sizeof(struct mlx5_nic_flow_attr); |
4614 | err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, | |
4615 | &parse_attr, &flow); | |
4616 | if (err) | |
4617 | goto out; | |
4618 | ||
d11afc26 | 4619 | parse_attr->filter_dev = filter_dev; |
54c177ca OS |
4620 | err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, |
4621 | f, filter_dev); | |
d11afc26 OS |
4622 | if (err) |
4623 | goto err_free; | |
4624 | ||
73867881 | 4625 | err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack); |
a88780a9 RD |
4626 | if (err) |
4627 | goto err_free; | |
4628 | ||
4629 | err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack); | |
4630 | if (err) | |
4631 | goto err_free; | |
4632 | ||
226f2ca3 | 4633 | flow_flag_set(flow, OFFLOADED); |
a88780a9 RD |
4634 | kvfree(parse_attr); |
4635 | *__flow = flow; | |
4636 | ||
4637 | return 0; | |
e3a2b7ed | 4638 | |
e3a2b7ed | 4639 | err_free: |
5a7e5bcb | 4640 | mlx5e_flow_put(priv, flow); |
17091853 | 4641 | kvfree(parse_attr); |
a88780a9 RD |
4642 | out: |
4643 | return err; | |
4644 | } | |
4645 | ||
4646 | static int | |
4647 | mlx5e_tc_add_flow(struct mlx5e_priv *priv, | |
f9e30088 | 4648 | struct flow_cls_offload *f, |
226f2ca3 | 4649 | unsigned long flags, |
d11afc26 | 4650 | struct net_device *filter_dev, |
a88780a9 RD |
4651 | struct mlx5e_tc_flow **flow) |
4652 | { | |
4653 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
226f2ca3 | 4654 | unsigned long flow_flags; |
a88780a9 RD |
4655 | int err; |
4656 | ||
4657 | get_flags(flags, &flow_flags); | |
4658 | ||
bf07aa73 PB |
4659 | if (!tc_can_offload_extack(priv->netdev, f->common.extack)) |
4660 | return -EOPNOTSUPP; | |
4661 | ||
f6455de0 | 4662 | if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS) |
d11afc26 OS |
4663 | err = mlx5e_add_fdb_flow(priv, f, flow_flags, |
4664 | filter_dev, flow); | |
a88780a9 | 4665 | else |
d11afc26 OS |
4666 | err = mlx5e_add_nic_flow(priv, f, flow_flags, |
4667 | filter_dev, flow); | |
a88780a9 RD |
4668 | |
4669 | return err; | |
4670 | } | |
4671 | ||
553f9328 VP |
4672 | static bool is_flow_rule_duplicate_allowed(struct net_device *dev, |
4673 | struct mlx5e_rep_priv *rpriv) | |
4674 | { | |
4675 | /* Offloaded flow rule is allowed to duplicate on non-uplink representor | |
4676 | * sharing tc block with other slaves of a lag device. | |
4677 | */ | |
4678 | return netif_is_lag_port(dev) && rpriv->rep->vport != MLX5_VPORT_UPLINK; | |
4679 | } | |
4680 | ||
71d82d2a | 4681 | int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv, |
226f2ca3 | 4682 | struct flow_cls_offload *f, unsigned long flags) |
a88780a9 RD |
4683 | { |
4684 | struct netlink_ext_ack *extack = f->common.extack; | |
d9ee0491 | 4685 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
553f9328 | 4686 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
a88780a9 RD |
4687 | struct mlx5e_tc_flow *flow; |
4688 | int err = 0; | |
4689 | ||
c5d326b2 VB |
4690 | rcu_read_lock(); |
4691 | flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params); | |
4692 | rcu_read_unlock(); | |
a88780a9 | 4693 | if (flow) { |
553f9328 VP |
4694 | /* Same flow rule offloaded to non-uplink representor sharing tc block, |
4695 | * just return 0. | |
4696 | */ | |
4697 | if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev) | |
4698 | goto out; | |
4699 | ||
a88780a9 RD |
4700 | NL_SET_ERR_MSG_MOD(extack, |
4701 | "flow cookie already exists, ignoring"); | |
4702 | netdev_warn_once(priv->netdev, | |
4703 | "flow cookie %lx already exists, ignoring\n", | |
4704 | f->cookie); | |
0e1c1a2f | 4705 | err = -EEXIST; |
a88780a9 RD |
4706 | goto out; |
4707 | } | |
4708 | ||
7a978759 | 4709 | trace_mlx5e_configure_flower(f); |
d11afc26 | 4710 | err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow); |
a88780a9 RD |
4711 | if (err) |
4712 | goto out; | |
4713 | ||
553f9328 VP |
4714 | /* Flow rule offloaded to non-uplink representor sharing tc block, |
4715 | * set the flow's owner dev. | |
4716 | */ | |
4717 | if (is_flow_rule_duplicate_allowed(dev, rpriv)) | |
4718 | flow->orig_dev = dev; | |
4719 | ||
c5d326b2 | 4720 | err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params); |
a88780a9 RD |
4721 | if (err) |
4722 | goto err_free; | |
4723 | ||
4724 | return 0; | |
4725 | ||
4726 | err_free: | |
5a7e5bcb | 4727 | mlx5e_flow_put(priv, flow); |
a88780a9 | 4728 | out: |
e3a2b7ed AV |
4729 | return err; |
4730 | } | |
4731 | ||
8f8ae895 OG |
4732 | static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags) |
4733 | { | |
226f2ca3 VB |
4734 | bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS)); |
4735 | bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS)); | |
8f8ae895 | 4736 | |
226f2ca3 VB |
4737 | return flow_flag_test(flow, INGRESS) == dir_ingress && |
4738 | flow_flag_test(flow, EGRESS) == dir_egress; | |
8f8ae895 OG |
4739 | } |
4740 | ||
71d82d2a | 4741 | int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv, |
226f2ca3 | 4742 | struct flow_cls_offload *f, unsigned long flags) |
e3a2b7ed | 4743 | { |
d9ee0491 | 4744 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
e3a2b7ed | 4745 | struct mlx5e_tc_flow *flow; |
c5d326b2 | 4746 | int err; |
e3a2b7ed | 4747 | |
c5d326b2 | 4748 | rcu_read_lock(); |
ab818362 | 4749 | flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params); |
c5d326b2 VB |
4750 | if (!flow || !same_flow_direction(flow, flags)) { |
4751 | err = -EINVAL; | |
4752 | goto errout; | |
4753 | } | |
e3a2b7ed | 4754 | |
c5d326b2 VB |
4755 | /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag |
4756 | * set. | |
4757 | */ | |
4758 | if (flow_flag_test_and_set(flow, DELETED)) { | |
4759 | err = -EINVAL; | |
4760 | goto errout; | |
4761 | } | |
05866c82 | 4762 | rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params); |
c5d326b2 | 4763 | rcu_read_unlock(); |
e3a2b7ed | 4764 | |
7a978759 | 4765 | trace_mlx5e_delete_flower(f); |
5a7e5bcb | 4766 | mlx5e_flow_put(priv, flow); |
e3a2b7ed AV |
4767 | |
4768 | return 0; | |
c5d326b2 VB |
4769 | |
4770 | errout: | |
4771 | rcu_read_unlock(); | |
4772 | return err; | |
e3a2b7ed AV |
4773 | } |
4774 | ||
71d82d2a | 4775 | int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv, |
226f2ca3 | 4776 | struct flow_cls_offload *f, unsigned long flags) |
aad7e08d | 4777 | { |
04de7dda | 4778 | struct mlx5_devcom *devcom = priv->mdev->priv.devcom; |
d9ee0491 | 4779 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
04de7dda | 4780 | struct mlx5_eswitch *peer_esw; |
aad7e08d | 4781 | struct mlx5e_tc_flow *flow; |
aad7e08d | 4782 | struct mlx5_fc *counter; |
316d5f72 RD |
4783 | u64 lastuse = 0; |
4784 | u64 packets = 0; | |
4785 | u64 bytes = 0; | |
5a7e5bcb | 4786 | int err = 0; |
aad7e08d | 4787 | |
c5d326b2 VB |
4788 | rcu_read_lock(); |
4789 | flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie, | |
4790 | tc_ht_params)); | |
4791 | rcu_read_unlock(); | |
5a7e5bcb VB |
4792 | if (IS_ERR(flow)) |
4793 | return PTR_ERR(flow); | |
4794 | ||
4795 | if (!same_flow_direction(flow, flags)) { | |
4796 | err = -EINVAL; | |
4797 | goto errout; | |
4798 | } | |
aad7e08d | 4799 | |
4c3844d9 | 4800 | if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) { |
316d5f72 RD |
4801 | counter = mlx5e_tc_get_counter(flow); |
4802 | if (!counter) | |
5a7e5bcb | 4803 | goto errout; |
aad7e08d | 4804 | |
316d5f72 RD |
4805 | mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse); |
4806 | } | |
aad7e08d | 4807 | |
316d5f72 RD |
4808 | /* Under multipath it's possible for one rule to be currently |
4809 | * un-offloaded while the other rule is offloaded. | |
4810 | */ | |
04de7dda RD |
4811 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); |
4812 | if (!peer_esw) | |
4813 | goto out; | |
4814 | ||
226f2ca3 VB |
4815 | if (flow_flag_test(flow, DUP) && |
4816 | flow_flag_test(flow->peer_flow, OFFLOADED)) { | |
04de7dda RD |
4817 | u64 bytes2; |
4818 | u64 packets2; | |
4819 | u64 lastuse2; | |
4820 | ||
4821 | counter = mlx5e_tc_get_counter(flow->peer_flow); | |
316d5f72 RD |
4822 | if (!counter) |
4823 | goto no_peer_counter; | |
04de7dda RD |
4824 | mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2); |
4825 | ||
4826 | bytes += bytes2; | |
4827 | packets += packets2; | |
4828 | lastuse = max_t(u64, lastuse, lastuse2); | |
4829 | } | |
4830 | ||
316d5f72 | 4831 | no_peer_counter: |
04de7dda | 4832 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); |
04de7dda | 4833 | out: |
4b61d3e8 | 4834 | flow_stats_update(&f->stats, bytes, packets, 0, lastuse, |
93a129eb | 4835 | FLOW_ACTION_HW_STATS_DELAYED); |
7a978759 | 4836 | trace_mlx5e_stats_flower(f); |
5a7e5bcb VB |
4837 | errout: |
4838 | mlx5e_flow_put(priv, flow); | |
4839 | return err; | |
aad7e08d AV |
4840 | } |
4841 | ||
fcb64c0f EC |
4842 | static int apply_police_params(struct mlx5e_priv *priv, u32 rate, |
4843 | struct netlink_ext_ack *extack) | |
4844 | { | |
4845 | struct mlx5e_rep_priv *rpriv = priv->ppriv; | |
4846 | struct mlx5_eswitch *esw; | |
4847 | u16 vport_num; | |
4848 | u32 rate_mbps; | |
4849 | int err; | |
4850 | ||
e401a184 EC |
4851 | vport_num = rpriv->rep->vport; |
4852 | if (vport_num >= MLX5_VPORT_ECPF) { | |
4853 | NL_SET_ERR_MSG_MOD(extack, | |
4854 | "Ingress rate limit is supported only for Eswitch ports connected to VFs"); | |
4855 | return -EOPNOTSUPP; | |
4856 | } | |
4857 | ||
fcb64c0f EC |
4858 | esw = priv->mdev->priv.eswitch; |
4859 | /* rate is given in bytes/sec. | |
4860 | * First convert to bits/sec and then round to the nearest mbit/secs. | |
4861 | * mbit means million bits. | |
4862 | * Moreover, if rate is non zero we choose to configure to a minimum of | |
4863 | * 1 mbit/sec. | |
4864 | */ | |
4865 | rate_mbps = rate ? max_t(u32, (rate * 8 + 500000) / 1000000, 1) : 0; | |
fcb64c0f EC |
4866 | err = mlx5_esw_modify_vport_rate(esw, vport_num, rate_mbps); |
4867 | if (err) | |
4868 | NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware"); | |
4869 | ||
4870 | return err; | |
4871 | } | |
4872 | ||
4873 | static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv, | |
4874 | struct flow_action *flow_action, | |
4875 | struct netlink_ext_ack *extack) | |
4876 | { | |
4877 | struct mlx5e_rep_priv *rpriv = priv->ppriv; | |
4878 | const struct flow_action_entry *act; | |
4879 | int err; | |
4880 | int i; | |
4881 | ||
4882 | if (!flow_action_has_entries(flow_action)) { | |
4883 | NL_SET_ERR_MSG_MOD(extack, "matchall called with no action"); | |
4884 | return -EINVAL; | |
4885 | } | |
4886 | ||
4887 | if (!flow_offload_has_one_action(flow_action)) { | |
4888 | NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action"); | |
4889 | return -EOPNOTSUPP; | |
4890 | } | |
4891 | ||
53eca1f3 | 4892 | if (!flow_action_basic_hw_stats_check(flow_action, extack)) |
319a1d19 JP |
4893 | return -EOPNOTSUPP; |
4894 | ||
fcb64c0f EC |
4895 | flow_action_for_each(i, act, flow_action) { |
4896 | switch (act->id) { | |
4897 | case FLOW_ACTION_POLICE: | |
4898 | err = apply_police_params(priv, act->police.rate_bytes_ps, extack); | |
4899 | if (err) | |
4900 | return err; | |
4901 | ||
4902 | rpriv->prev_vf_vport_stats = priv->stats.vf_vport; | |
4903 | break; | |
4904 | default: | |
4905 | NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall"); | |
4906 | return -EOPNOTSUPP; | |
4907 | } | |
4908 | } | |
4909 | ||
4910 | return 0; | |
4911 | } | |
4912 | ||
4913 | int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv, | |
4914 | struct tc_cls_matchall_offload *ma) | |
4915 | { | |
b5f814cc | 4916 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
fcb64c0f | 4917 | struct netlink_ext_ack *extack = ma->common.extack; |
fcb64c0f | 4918 | |
b5f814cc EC |
4919 | if (!mlx5_esw_qos_enabled(esw)) { |
4920 | NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device"); | |
4921 | return -EOPNOTSUPP; | |
4922 | } | |
4923 | ||
7b83355f | 4924 | if (ma->common.prio != 1) { |
fcb64c0f EC |
4925 | NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported"); |
4926 | return -EINVAL; | |
4927 | } | |
4928 | ||
4929 | return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack); | |
4930 | } | |
4931 | ||
4932 | int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv, | |
4933 | struct tc_cls_matchall_offload *ma) | |
4934 | { | |
4935 | struct netlink_ext_ack *extack = ma->common.extack; | |
4936 | ||
4937 | return apply_police_params(priv, 0, extack); | |
4938 | } | |
4939 | ||
4940 | void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv, | |
4941 | struct tc_cls_matchall_offload *ma) | |
4942 | { | |
4943 | struct mlx5e_rep_priv *rpriv = priv->ppriv; | |
4944 | struct rtnl_link_stats64 cur_stats; | |
4945 | u64 dbytes; | |
4946 | u64 dpkts; | |
4947 | ||
4948 | cur_stats = priv->stats.vf_vport; | |
4949 | dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets; | |
4950 | dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes; | |
4951 | rpriv->prev_vf_vport_stats = cur_stats; | |
4b61d3e8 | 4952 | flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies, |
93a129eb | 4953 | FLOW_ACTION_HW_STATS_DELAYED); |
fcb64c0f EC |
4954 | } |
4955 | ||
4d8fcf21 AH |
4956 | static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv, |
4957 | struct mlx5e_priv *peer_priv) | |
4958 | { | |
4959 | struct mlx5_core_dev *peer_mdev = peer_priv->mdev; | |
db76ca24 VB |
4960 | struct mlx5e_hairpin_entry *hpe, *tmp; |
4961 | LIST_HEAD(init_wait_list); | |
4d8fcf21 AH |
4962 | u16 peer_vhca_id; |
4963 | int bkt; | |
4964 | ||
4965 | if (!same_hw_devs(priv, peer_priv)) | |
4966 | return; | |
4967 | ||
4968 | peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id); | |
4969 | ||
b32accda | 4970 | mutex_lock(&priv->fs.tc.hairpin_tbl_lock); |
db76ca24 VB |
4971 | hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) |
4972 | if (refcount_inc_not_zero(&hpe->refcnt)) | |
4973 | list_add(&hpe->dead_peer_wait_list, &init_wait_list); | |
4974 | mutex_unlock(&priv->fs.tc.hairpin_tbl_lock); | |
4975 | ||
4976 | list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) { | |
4977 | wait_for_completion(&hpe->res_ready); | |
4978 | if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id) | |
4d8fcf21 | 4979 | hpe->hp->pair->peer_gone = true; |
db76ca24 VB |
4980 | |
4981 | mlx5e_hairpin_put(priv, hpe); | |
4d8fcf21 AH |
4982 | } |
4983 | } | |
4984 | ||
4985 | static int mlx5e_tc_netdev_event(struct notifier_block *this, | |
4986 | unsigned long event, void *ptr) | |
4987 | { | |
4988 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
4989 | struct mlx5e_flow_steering *fs; | |
4990 | struct mlx5e_priv *peer_priv; | |
4991 | struct mlx5e_tc_table *tc; | |
4992 | struct mlx5e_priv *priv; | |
4993 | ||
4994 | if (ndev->netdev_ops != &mlx5e_netdev_ops || | |
4995 | event != NETDEV_UNREGISTER || | |
4996 | ndev->reg_state == NETREG_REGISTERED) | |
4997 | return NOTIFY_DONE; | |
4998 | ||
4999 | tc = container_of(this, struct mlx5e_tc_table, netdevice_nb); | |
5000 | fs = container_of(tc, struct mlx5e_flow_steering, tc); | |
5001 | priv = container_of(fs, struct mlx5e_priv, fs); | |
5002 | peer_priv = netdev_priv(ndev); | |
5003 | if (priv == peer_priv || | |
5004 | !(priv->netdev->features & NETIF_F_HW_TC)) | |
5005 | return NOTIFY_DONE; | |
5006 | ||
5007 | mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv); | |
5008 | ||
5009 | return NOTIFY_DONE; | |
5010 | } | |
5011 | ||
655dc3d2 | 5012 | int mlx5e_tc_nic_init(struct mlx5e_priv *priv) |
e8f887ac | 5013 | { |
acff797c | 5014 | struct mlx5e_tc_table *tc = &priv->fs.tc; |
4d8fcf21 | 5015 | int err; |
e8f887ac | 5016 | |
b6fac0b4 | 5017 | mutex_init(&tc->t_lock); |
d2faae25 | 5018 | mutex_init(&tc->mod_hdr.lock); |
dd58edc3 | 5019 | hash_init(tc->mod_hdr.hlist); |
b32accda | 5020 | mutex_init(&tc->hairpin_tbl_lock); |
5c65c564 | 5021 | hash_init(tc->hairpin_tbl); |
11c9c548 | 5022 | |
4d8fcf21 AH |
5023 | err = rhashtable_init(&tc->ht, &tc_ht_params); |
5024 | if (err) | |
5025 | return err; | |
5026 | ||
5027 | tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event; | |
d48834f9 JP |
5028 | err = register_netdevice_notifier_dev_net(priv->netdev, |
5029 | &tc->netdevice_nb, | |
5030 | &tc->netdevice_nn); | |
5031 | if (err) { | |
4d8fcf21 AH |
5032 | tc->netdevice_nb.notifier_call = NULL; |
5033 | mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n"); | |
5034 | } | |
5035 | ||
5036 | return err; | |
e8f887ac AV |
5037 | } |
5038 | ||
5039 | static void _mlx5e_tc_del_flow(void *ptr, void *arg) | |
5040 | { | |
5041 | struct mlx5e_tc_flow *flow = ptr; | |
655dc3d2 | 5042 | struct mlx5e_priv *priv = flow->priv; |
e8f887ac | 5043 | |
961e8979 | 5044 | mlx5e_tc_del_flow(priv, flow); |
e8f887ac AV |
5045 | kfree(flow); |
5046 | } | |
5047 | ||
655dc3d2 | 5048 | void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) |
e8f887ac | 5049 | { |
acff797c | 5050 | struct mlx5e_tc_table *tc = &priv->fs.tc; |
e8f887ac | 5051 | |
4d8fcf21 | 5052 | if (tc->netdevice_nb.notifier_call) |
d48834f9 JP |
5053 | unregister_netdevice_notifier_dev_net(priv->netdev, |
5054 | &tc->netdevice_nb, | |
5055 | &tc->netdevice_nn); | |
4d8fcf21 | 5056 | |
d2faae25 | 5057 | mutex_destroy(&tc->mod_hdr.lock); |
b32accda VB |
5058 | mutex_destroy(&tc->hairpin_tbl_lock); |
5059 | ||
d9ee0491 | 5060 | rhashtable_destroy(&tc->ht); |
e8f887ac | 5061 | |
acff797c MG |
5062 | if (!IS_ERR_OR_NULL(tc->t)) { |
5063 | mlx5_destroy_flow_table(tc->t); | |
5064 | tc->t = NULL; | |
e8f887ac | 5065 | } |
b6fac0b4 | 5066 | mutex_destroy(&tc->t_lock); |
e8f887ac | 5067 | } |
655dc3d2 OG |
5068 | |
5069 | int mlx5e_tc_esw_init(struct rhashtable *tc_ht) | |
5070 | { | |
d7a42ad0 | 5071 | const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts); |
0a7fcb78 PB |
5072 | struct mlx5_rep_uplink_priv *uplink_priv; |
5073 | struct mlx5e_rep_priv *priv; | |
5074 | struct mapping_ctx *mapping; | |
5075 | int err; | |
5076 | ||
5077 | uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht); | |
5078 | priv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv); | |
5079 | ||
4c3844d9 PB |
5080 | err = mlx5_tc_ct_init(uplink_priv); |
5081 | if (err) | |
5082 | goto err_ct; | |
5083 | ||
0a7fcb78 PB |
5084 | mapping = mapping_create(sizeof(struct tunnel_match_key), |
5085 | TUNNEL_INFO_BITS_MASK, true); | |
5086 | if (IS_ERR(mapping)) { | |
5087 | err = PTR_ERR(mapping); | |
5088 | goto err_tun_mapping; | |
5089 | } | |
5090 | uplink_priv->tunnel_mapping = mapping; | |
5091 | ||
5092 | mapping = mapping_create(sz_enc_opts, ENC_OPTS_BITS_MASK, true); | |
5093 | if (IS_ERR(mapping)) { | |
5094 | err = PTR_ERR(mapping); | |
5095 | goto err_enc_opts_mapping; | |
5096 | } | |
5097 | uplink_priv->tunnel_enc_opts_mapping = mapping; | |
5098 | ||
5099 | err = rhashtable_init(tc_ht, &tc_ht_params); | |
5100 | if (err) | |
5101 | goto err_ht_init; | |
5102 | ||
5103 | return err; | |
5104 | ||
5105 | err_ht_init: | |
5106 | mapping_destroy(uplink_priv->tunnel_enc_opts_mapping); | |
5107 | err_enc_opts_mapping: | |
5108 | mapping_destroy(uplink_priv->tunnel_mapping); | |
5109 | err_tun_mapping: | |
4c3844d9 PB |
5110 | mlx5_tc_ct_clean(uplink_priv); |
5111 | err_ct: | |
0a7fcb78 PB |
5112 | netdev_warn(priv->netdev, |
5113 | "Failed to initialize tc (eswitch), err: %d", err); | |
5114 | return err; | |
655dc3d2 OG |
5115 | } |
5116 | ||
5117 | void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht) | |
5118 | { | |
0a7fcb78 PB |
5119 | struct mlx5_rep_uplink_priv *uplink_priv; |
5120 | ||
655dc3d2 | 5121 | rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL); |
0a7fcb78 PB |
5122 | |
5123 | uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht); | |
5124 | mapping_destroy(uplink_priv->tunnel_enc_opts_mapping); | |
5125 | mapping_destroy(uplink_priv->tunnel_mapping); | |
4c3844d9 PB |
5126 | |
5127 | mlx5_tc_ct_clean(uplink_priv); | |
655dc3d2 | 5128 | } |
01252a27 | 5129 | |
226f2ca3 | 5130 | int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags) |
01252a27 | 5131 | { |
d9ee0491 | 5132 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
01252a27 OG |
5133 | |
5134 | return atomic_read(&tc_ht->nelems); | |
5135 | } | |
04de7dda RD |
5136 | |
5137 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw) | |
5138 | { | |
5139 | struct mlx5e_tc_flow *flow, *tmp; | |
5140 | ||
5141 | list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer) | |
5142 | __mlx5e_tc_del_fdb_peer_flow(flow); | |
5143 | } | |
b4a23329 RD |
5144 | |
5145 | void mlx5e_tc_reoffload_flows_work(struct work_struct *work) | |
5146 | { | |
5147 | struct mlx5_rep_uplink_priv *rpriv = | |
5148 | container_of(work, struct mlx5_rep_uplink_priv, | |
5149 | reoffload_flows_work); | |
5150 | struct mlx5e_tc_flow *flow, *tmp; | |
5151 | ||
ad86755b | 5152 | mutex_lock(&rpriv->unready_flows_lock); |
b4a23329 RD |
5153 | list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) { |
5154 | if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL)) | |
ad86755b | 5155 | unready_flow_del(flow); |
b4a23329 | 5156 | } |
ad86755b | 5157 | mutex_unlock(&rpriv->unready_flows_lock); |
b4a23329 | 5158 | } |
e2394a61 VB |
5159 | |
5160 | static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv, | |
5161 | struct flow_cls_offload *cls_flower, | |
5162 | unsigned long flags) | |
5163 | { | |
5164 | switch (cls_flower->command) { | |
5165 | case FLOW_CLS_REPLACE: | |
5166 | return mlx5e_configure_flower(priv->netdev, priv, cls_flower, | |
5167 | flags); | |
5168 | case FLOW_CLS_DESTROY: | |
5169 | return mlx5e_delete_flower(priv->netdev, priv, cls_flower, | |
5170 | flags); | |
5171 | case FLOW_CLS_STATS: | |
5172 | return mlx5e_stats_flower(priv->netdev, priv, cls_flower, | |
5173 | flags); | |
5174 | default: | |
5175 | return -EOPNOTSUPP; | |
5176 | } | |
5177 | } | |
5178 | ||
5179 | int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, | |
5180 | void *cb_priv) | |
5181 | { | |
5182 | unsigned long flags = MLX5_TC_FLAG(INGRESS) | MLX5_TC_FLAG(NIC_OFFLOAD); | |
5183 | struct mlx5e_priv *priv = cb_priv; | |
5184 | ||
5185 | switch (type) { | |
5186 | case TC_SETUP_CLSFLOWER: | |
5187 | return mlx5e_setup_tc_cls_flower(priv, type_data, flags); | |
5188 | default: | |
5189 | return -EOPNOTSUPP; | |
5190 | } | |
5191 | } |