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net/mlx5e: Add post act offload/unoffload API
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
f6dfb4c3 42#include <net/arp.h>
3616d08b 43#include <net/ipv6_stubs.h>
f828ca6a 44#include <net/bareudp.h>
d34eb2fc 45#include <net/bonding.h>
e8f887ac 46#include "en.h"
f0da4daa 47#include "en/tc/post_act.h"
1d447a39 48#include "en_rep.h"
768c3667 49#include "en/rep/tc.h"
e2394a61 50#include "en/rep/neigh.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
3f6d08d1 53#include "fs_core.h"
2c81bfd5 54#include "en/port.h"
101f4de9 55#include "en/tc_tun.h"
0a7fcb78 56#include "en/mapping.h"
4c3844d9 57#include "en/tc_ct.h"
b2fdf3d0 58#include "en/mod_hdr.h"
0d9f9647 59#include "en/tc_tun_encap.h"
0027d70c 60#include "en/tc/sample.h"
fad54790 61#include "en/tc/act/act.h"
04de7dda 62#include "lib/devcom.h"
9272e3df 63#include "lib/geneve.h"
ae430332 64#include "lib/fs_chains.h"
7a978759 65#include "diag/en_tc_tracepoint.h"
1fe3e316 66#include <asm/div64.h>
016c8946
JK		 67#include "lag/lag.h"
68#include "lag/mp.h"
e8f887ac 69
acff797c 70#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 71#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 72
8f1e0b97
PB		 73struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
74 [CHAIN_TO_REG] = {
75 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
76 .moffset = 0,
ed2fe7ba 77 .mlen = 16,
8f1e0b97 78 },
10742efc
VB		 79 [VPORT_TO_REG] = {
80 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 81 .moffset = 16,
82 .mlen = 16,
10742efc 83 },
0a7fcb78
PB		 84 [TUNNEL_TO_REG] = {
85 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 86 .moffset = 8,
87 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 88 .soffset = MLX5_BYTE_OFF(fte_match_param,
89 misc_parameters_2.metadata_reg_c_1),
90 },
4c3844d9 91 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 92 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 93 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
94 [MARK_TO_REG] = mark_to_reg_ct,
95 [LABELS_TO_REG] = labels_to_reg_ct,
96 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 97 /* For NIC rules we store the restore metadata directly
c7569097
AL		 98 * into reg_b that is passed to SW since we don't
99 * jump between steering domains.
100 */
101 [NIC_CHAIN_TO_REG] = {
102 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
103 .moffset = 0,
ed2fe7ba 104 .mlen = 16,
c7569097 105 },
aedd133d 106 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 107};
108
9ba33339
RD		 109/* To avoid false lock dependency warning set the tc_ht lock
110 * class different than the lock class of the ht being used when deleting
111 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
112 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
113 * it's different than the ht->mutex here.
114 */
115static struct lock_class_key tc_ht_lock_key;
116
0a7fcb78
PB		 117static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
118
119void
120mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
121 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 122 u32 val,
0a7fcb78
PB		 123 u32 mask)
124{
ed2fe7ba 125 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 126 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 127 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 128 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 129 u32 max_mask = GENMASK(match_len - 1, 0);
130 __be32 curr_mask_be, curr_val_be;
131 u32 curr_mask, curr_val;
0a7fcb78
PB		 132
133 fmask = headers_c + soffset;
134 fval = headers_v + soffset;
135
ed2fe7ba
PB		 136 memcpy(&curr_mask_be, fmask, 4);
137 memcpy(&curr_val_be, fval, 4);
138
139 curr_mask = be32_to_cpu(curr_mask_be);
140 curr_val = be32_to_cpu(curr_val_be);
141
142 //move to correct offset
143 WARN_ON(mask > max_mask);
144 mask <<= moffset;
145 val <<= moffset;
146 max_mask <<= moffset;
147
148 //zero val and mask
149 curr_mask &= ~max_mask;
150 curr_val &= ~max_mask;
0a7fcb78 151
ed2fe7ba
PB		 152 //add current to mask
153 curr_mask |= mask;
154 curr_val |= val;
155
156 //back to be32 and write
157 curr_mask_be = cpu_to_be32(curr_mask);
158 curr_val_be = cpu_to_be32(curr_val);
159
160 memcpy(fmask, &curr_mask_be, 4);
161 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 162
163 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
164}
165
7e36feeb
PB		 166void
167mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
168 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 169 u32 *val,
7e36feeb
PB		 170 u32 *mask)
171{
ed2fe7ba 172 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 173 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 174 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 175 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 176 u32 max_mask = GENMASK(match_len - 1, 0);
177 __be32 curr_mask_be, curr_val_be;
178 u32 curr_mask, curr_val;
7e36feeb
PB		 179
180 fmask = headers_c + soffset;
181 fval = headers_v + soffset;
182
ed2fe7ba
PB		 183 memcpy(&curr_mask_be, fmask, 4);
184 memcpy(&curr_val_be, fval, 4);
185
186 curr_mask = be32_to_cpu(curr_mask_be);
187 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 188
ed2fe7ba
PB		 189 *mask = (curr_mask >> moffset) & max_mask;
190 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 191}
192
0a7fcb78 193int
c7b9038d
VB		 194mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
195 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
196 enum mlx5_flow_namespace_type ns,
197 enum mlx5e_tc_attr_to_reg type,
198 u32 data)
0a7fcb78
PB		 199{
200 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
201 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
202 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
203 char *modact;
204 int err;
205
2c0e5cf5
PB		 206 modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
207 if (IS_ERR(modact))
208 return PTR_ERR(modact);
0a7fcb78
PB		 209
210 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 211 if (mlen == 32)
0a7fcb78
PB		 212 mlen = 0;
213
214 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
215 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 216 MLX5_SET(set_action_in, modact, offset, moffset);
217 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 218 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 219 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 220 mod_hdr_acts->num_actions++;
221
c7b9038d 222 return err;
0a7fcb78
PB		 223}
224
27484f71
AL		 225struct mlx5e_tc_int_port_priv *
226mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
227{
228 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
229 struct mlx5_rep_uplink_priv *uplink_priv;
230 struct mlx5e_rep_priv *uplink_rpriv;
231
232 if (is_mdev_switchdev_mode(priv->mdev)) {
233 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
234 uplink_priv = &uplink_rpriv->uplink_priv;
235
236 return uplink_priv->int_port_priv;
237 }
238
239 return NULL;
240}
241
aedd133d
AL		 242static struct mlx5_tc_ct_priv *
243get_ct_priv(struct mlx5e_priv *priv)
244{
245 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
246 struct mlx5_rep_uplink_priv *uplink_priv;
247 struct mlx5e_rep_priv *uplink_rpriv;
248
e8711402 249 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 250 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
251 uplink_priv = &uplink_rpriv->uplink_priv;
252
253 return uplink_priv->ct_priv;
254 }
255
256 return priv->fs.tc.ct;
257}
258
0027d70c 259static struct mlx5e_tc_psample *
f94d6389
CM		 260get_sample_priv(struct mlx5e_priv *priv)
261{
262 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
263 struct mlx5_rep_uplink_priv *uplink_priv;
264 struct mlx5e_rep_priv *uplink_rpriv;
265
266 if (is_mdev_switchdev_mode(priv->mdev)) {
267 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
268 uplink_priv = &uplink_rpriv->uplink_priv;
269
0027d70c 270 return uplink_priv->tc_psample;
f94d6389
CM		 271 }
272
273 return NULL;
274}
f94d6389 275
aedd133d
AL		 276struct mlx5_flow_handle *
277mlx5_tc_rule_insert(struct mlx5e_priv *priv,
278 struct mlx5_flow_spec *spec,
279 struct mlx5_flow_attr *attr)
280{
281 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
282
e8711402 283 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 284 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
285
286 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
287}
288
289void
290mlx5_tc_rule_delete(struct mlx5e_priv *priv,
291 struct mlx5_flow_handle *rule,
292 struct mlx5_flow_attr *attr)
293{
294 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
295
e8711402 296 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d 297 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
aedd133d
AL		 298 return;
299 }
300
301 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
302}
303
84ba8062
RD		 304struct mlx5_flow_handle *
305mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
84ba8062
RD		 306 struct mlx5_flow_spec *spec,
307 struct mlx5_flow_attr *attr)
308{
309 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
84ba8062
RD		 310
311 if (attr->flags & MLX5_ATTR_FLAG_CT) {
312 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts =
313 &attr->parse_attr->mod_hdr_acts;
314
a572c0a7 315 return mlx5_tc_ct_flow_offload(get_ct_priv(priv),
84ba8062
RD		 316 spec, attr,
317 mod_hdr_acts);
318 }
319
320 if (!is_mdev_switchdev_mode(priv->mdev))
321 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
322
323 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
73a3f1bc 324 return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
84ba8062
RD		 325
326 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
327}
328
329void
330mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
a572c0a7 331 struct mlx5_flow_handle *rule,
84ba8062
RD		 332 struct mlx5_flow_attr *attr)
333{
334 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
84ba8062
RD		 335
336 if (attr->flags & MLX5_ATTR_FLAG_CT) {
a572c0a7 337 mlx5_tc_ct_delete_flow(get_ct_priv(priv), attr);
84ba8062
RD		 338 return;
339 }
340
341 if (!is_mdev_switchdev_mode(priv->mdev)) {
342 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
343 return;
344 }
345
346 if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
347 mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
348 return;
349 }
350
351 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
352}
353
c7b9038d
VB		 354int
355mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
356 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
357 enum mlx5_flow_namespace_type ns,
358 enum mlx5e_tc_attr_to_reg type,
359 u32 data)
360{
361 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
362
363 return ret < 0 ? ret : 0;
364}
365
366void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
367 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
368 enum mlx5e_tc_attr_to_reg type,
369 int act_id, u32 data)
370{
371 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
372 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
373 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
374 char *modact;
375
2c0e5cf5 376 modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
c7b9038d
VB		 377
378 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 379 if (mlen == 32)
c7b9038d
VB		 380 mlen = 0;
381
382 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
383 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 384 MLX5_SET(set_action_in, modact, offset, moffset);
385 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 386 MLX5_SET(set_action_in, modact, data, data);
387}
388
77ab67b7
OG		 389struct mlx5e_hairpin {
390 struct mlx5_hairpin *pair;
391
392 struct mlx5_core_dev *func_mdev;
3f6d08d1 393 struct mlx5e_priv *func_priv;
77ab67b7 394 u32 tdn;
a6696735 395 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 396
397 int num_channels;
398 struct mlx5e_rqt indir_rqt;
a6696735 399 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 400 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 401};
402
5c65c564
OG		 403struct mlx5e_hairpin_entry {
404 /* a node of a hash table which keeps all the hairpin entries */
405 struct hlist_node hairpin_hlist;
406
73edca73
VB		 407 /* protects flows list */
408 spinlock_t flows_lock;
5c65c564
OG		 409 /* flows sharing the same hairpin */
410 struct list_head flows;
db76ca24
VB		 411 /* hpe's that were not fully initialized when dead peer update event
412 * function traversed them.
413 */
414 struct list_head dead_peer_wait_list;
5c65c564 415
d8822868 416 u16 peer_vhca_id;
106be53b 417 u8 prio;
5c65c564 418 struct mlx5e_hairpin *hp;
e4f9abbd 419 refcount_t refcnt;
db76ca24 420 struct completion res_ready;
5c65c564
OG		 421};
422
5a7e5bcb
VB		 423static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
424 struct mlx5e_tc_flow *flow);
425
0d9f9647 426struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 427{
428 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
429 return ERR_PTR(-EINVAL);
430 return flow;
431}
432
0d9f9647 433void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 434{
435 if (refcount_dec_and_test(&flow->refcnt)) {
436 mlx5e_tc_del_flow(priv, flow);
c5d326b2 437 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 438 }
439}
440
aedd133d 441bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 442{
443 return flow_flag_test(flow, ESWITCH);
444}
445
67d62ee7 446bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
84179981
PB		 447{
448 return flow_flag_test(flow, FT);
449}
450
0d9f9647 451bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 452{
453 return flow_flag_test(flow, OFFLOADED);
454}
455
e36db1ee 456int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
11c9c548 457{
b2fdf3d0
PB		 458 return mlx5e_is_eswitch_flow(flow) ?
459 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 460}
461
dd58edc3 462static struct mod_hdr_tbl *
b2fdf3d0 463get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 464{
465 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
466
e36db1ee 467 return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
b2fdf3d0 468 &esw->offloads.mod_hdr :
dd58edc3
VB		 469 &priv->fs.tc.mod_hdr;
470}
471
11c9c548
OG		 472static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
473 struct mlx5e_tc_flow *flow,
474 struct mlx5e_tc_flow_parse_attr *parse_attr)
475{
b2fdf3d0
PB		 476 struct mlx5_modify_hdr *modify_hdr;
477 struct mlx5e_mod_hdr_handle *mh;
11c9c548 478
b2fdf3d0 479 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
e36db1ee 480 mlx5e_get_flow_namespace(flow),
b2fdf3d0
PB		 481 &parse_attr->mod_hdr_acts);
482 if (IS_ERR(mh))
483 return PTR_ERR(mh);
11c9c548 484
b2fdf3d0 485 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 486 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 487 flow->mh = mh;
11c9c548
OG		 488
489 return 0;
11c9c548
OG		 490}
491
492static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
493 struct mlx5e_tc_flow *flow)
494{
5a7e5bcb 495 /* flow wasn't fully initialized */
dd58edc3 496 if (!flow->mh)
5a7e5bcb
VB		 497 return;
498
b2fdf3d0
PB		 499 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
500 flow->mh);
dd58edc3 501 flow->mh = NULL;
11c9c548
OG		 502}
503
77ab67b7
OG		 504static
505struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
506{
b1c2f631 507 struct mlx5_core_dev *mdev;
77ab67b7
OG		 508 struct net_device *netdev;
509 struct mlx5e_priv *priv;
510
b1c2f631
DC		 511 netdev = dev_get_by_index(net, ifindex);
512 if (!netdev)
513 return ERR_PTR(-ENODEV);
514
77ab67b7 515 priv = netdev_priv(netdev);
b1c2f631
DC		 516 mdev = priv->mdev;
517 dev_put(netdev);
518
519 /* Mirred tc action holds a refcount on the ifindex net_device (see
520 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
521 * after dev_put(netdev), while we're in the context of adding a tc flow.
522 *
523 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
524 * stored in a hairpin object, which exists until all flows, that refer to it, get
525 * removed.
526 *
527 * On the other hand, after a hairpin object has been created, the peer net_device may
528 * be removed/unbound while there are still some hairpin flows that are using it. This
529 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
530 * NETDEV_UNREGISTER event of the peer net_device.
531 */
532 return mdev;
77ab67b7
OG		 533}
534
535static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
536{
a6696735 537 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 538 int err;
539
a6696735
MM		 540 builder = mlx5e_tir_builder_alloc(false);
541 if (!builder)
542 return -ENOMEM;
543
77ab67b7
OG		 544 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
545 if (err)
a6696735 546 goto out;
77ab67b7 547
a6696735
MM		 548 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
549 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 550 if (err)
551 goto create_tir_err;
552
a6696735
MM		 553out:
554 mlx5e_tir_builder_free(builder);
555 return err;
77ab67b7
OG		 556
557create_tir_err:
558 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 559
560 goto out;
77ab67b7
OG		 561}
562
563static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
564{
a6696735 565 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 566 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
567}
568
3f6d08d1
OG		 569static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
570{
3f6d08d1
OG		 571 struct mlx5e_priv *priv = hp->func_priv;
572 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 573 struct mlx5e_rss_params_indir *indir;
574 int err;
3f6d08d1 575
06e9f13a
MM		 576 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
577 if (!indir)
3f6d08d1
OG		 578 return -ENOMEM;
579
43befe99 580 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 581 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 582 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
583 indir);
3f6d08d1 584
06e9f13a 585 kvfree(indir);
3f6d08d1
OG		 586 return err;
587}
588
589static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
590{
591 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 592 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 593 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 594 struct mlx5e_tir_builder *builder;
595 int err = 0;
596
597 builder = mlx5e_tir_builder_alloc(false);
598 if (!builder)
599 return -ENOMEM;
600
43ec0f41 601 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 602
603 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 604 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 605
65d6b6e5 606 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 607
a6696735
MM		 608 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
609 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
610 false);
43ec0f41 611 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 612
a6696735 613 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 614 if (err) {
615 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
616 goto err_destroy_tirs;
617 }
a6696735
MM		 618
619 mlx5e_tir_builder_clear(builder);
3f6d08d1 620 }
3f6d08d1 621
a6696735
MM		 622out:
623 mlx5e_tir_builder_free(builder);
3f6d08d1 624 return err;
a6696735
MM		 625
626err_destroy_tirs:
627 max_tt = tt;
628 for (tt = 0; tt < max_tt; tt++)
629 mlx5e_tir_destroy(&hp->indir_tir[tt]);
630
631 goto out;
3f6d08d1
OG		 632}
633
634static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
635{
636 int tt;
637
638 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 639 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 640}
641
642static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
643 struct ttc_params *ttc_params)
644{
645 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
646 int tt;
647
648 memset(ttc_params, 0, sizeof(*ttc_params));
649
bc29764e
MG		 650 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
651 MLX5_FLOW_NAMESPACE_KERNEL);
652 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
653 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
654 ttc_params->dests[tt].tir_num =
655 tt == MLX5_TT_ANY ?
656 mlx5e_tir_get_tirn(&hp->direct_tir) :
657 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
658 }
3f6d08d1 659
3f6d08d1
OG		 660 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
661 ft_attr->prio = MLX5E_TC_PRIO;
662}
663
664static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
665{
666 struct mlx5e_priv *priv = hp->func_priv;
667 struct ttc_params ttc_params;
668 int err;
669
670 err = mlx5e_hairpin_create_indirect_rqt(hp);
671 if (err)
672 return err;
673
674 err = mlx5e_hairpin_create_indirect_tirs(hp);
675 if (err)
676 goto err_create_indirect_tirs;
677
678 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 679 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
680 if (IS_ERR(hp->ttc)) {
681 err = PTR_ERR(hp->ttc);
3f6d08d1 682 goto err_create_ttc_table;
f4b45940 683 }
3f6d08d1
OG		 684
685 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 686 hp->num_channels,
687 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 688
689 return 0;
690
691err_create_ttc_table:
692 mlx5e_hairpin_destroy_indirect_tirs(hp);
693err_create_indirect_tirs:
06e9f13a 694 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 695
696 return err;
697}
698
699static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
700{
f4b45940 701 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 702 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 703 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 704}
705
77ab67b7
OG		 706static struct mlx5e_hairpin *
707mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
708 int peer_ifindex)
709{
710 struct mlx5_core_dev *func_mdev, *peer_mdev;
711 struct mlx5e_hairpin *hp;
712 struct mlx5_hairpin *pair;
713 int err;
714
715 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
716 if (!hp)
717 return ERR_PTR(-ENOMEM);
718
719 func_mdev = priv->mdev;
720 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 721 if (IS_ERR(peer_mdev)) {
722 err = PTR_ERR(peer_mdev);
723 goto create_pair_err;
724 }
77ab67b7
OG		 725
726 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
727 if (IS_ERR(pair)) {
728 err = PTR_ERR(pair);
729 goto create_pair_err;
730 }
731 hp->pair = pair;
732 hp->func_mdev = func_mdev;
3f6d08d1
OG		 733 hp->func_priv = priv;
734 hp->num_channels = params->num_channels;
77ab67b7
OG		 735
736 err = mlx5e_hairpin_create_transport(hp);
737 if (err)
738 goto create_transport_err;
739
3f6d08d1
OG		 740 if (hp->num_channels > 1) {
741 err = mlx5e_hairpin_rss_init(hp);
742 if (err)
743 goto rss_init_err;
744 }
745
77ab67b7
OG		 746 return hp;
747
3f6d08d1
OG		 748rss_init_err:
749 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 750create_transport_err:
751 mlx5_core_hairpin_destroy(hp->pair);
752create_pair_err:
753 kfree(hp);
754 return ERR_PTR(err);
755}
756
757static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
758{
3f6d08d1
OG		 759 if (hp->num_channels > 1)
760 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 761 mlx5e_hairpin_destroy_transport(hp);
762 mlx5_core_hairpin_destroy(hp->pair);
763 kvfree(hp);
764}
765
106be53b
OG		 766static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
767{
768 return (peer_vhca_id << 16 | prio);
769}
770
5c65c564 771static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 772 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 773{
774 struct mlx5e_hairpin_entry *hpe;
106be53b 775 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 776
777 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 778 hairpin_hlist, hash_key) {
e4f9abbd
VB		 779 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
780 refcount_inc(&hpe->refcnt);
5c65c564 781 return hpe;
e4f9abbd 782 }
5c65c564
OG		 783 }
784
785 return NULL;
786}
787
e4f9abbd
VB		 788static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
789 struct mlx5e_hairpin_entry *hpe)
790{
791 /* no more hairpin flows for us, release the hairpin pair */
b32accda 792 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 793 return;
b32accda
VB		 794 hash_del(&hpe->hairpin_hlist);
795 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 796
db76ca24
VB		 797 if (!IS_ERR_OR_NULL(hpe->hp)) {
798 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
799 dev_name(hpe->hp->pair->peer_mdev->device));
800
801 mlx5e_hairpin_destroy(hpe->hp);
802 }
e4f9abbd
VB		 803
804 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 805 kfree(hpe);
806}
807
106be53b
OG		 808#define UNKNOWN_MATCH_PRIO 8
809
810static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 811 struct mlx5_flow_spec *spec, u8 *match_prio,
812 struct netlink_ext_ack *extack)
106be53b
OG		 813{
814 void *headers_c, *headers_v;
815 u8 prio_val, prio_mask = 0;
816 bool vlan_present;
817
818#ifdef CONFIG_MLX5_CORE_EN_DCB
819 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 820 NL_SET_ERR_MSG_MOD(extack,
821 "only PCP trust state supported for hairpin");
106be53b
OG		 822 return -EOPNOTSUPP;
823 }
824#endif
825 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
826 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
827
828 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
829 if (vlan_present) {
830 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
831 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
832 }
833
834 if (!vlan_present || !prio_mask) {
835 prio_val = UNKNOWN_MATCH_PRIO;
836 } else if (prio_mask != 0x7) {
e98bedf5
EB		 837 NL_SET_ERR_MSG_MOD(extack,
838 "masked priority match not supported for hairpin");
106be53b
OG		 839 return -EOPNOTSUPP;
840 }
841
842 *match_prio = prio_val;
843 return 0;
844}
845
5c65c564
OG		 846static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
847 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 848 struct mlx5e_tc_flow_parse_attr *parse_attr,
849 struct netlink_ext_ack *extack)
5c65c564 850{
98b66cb1 851 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 852 struct mlx5_hairpin_params params;
d8822868 853 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 854 struct mlx5e_hairpin_entry *hpe;
855 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 856 u64 link_speed64;
857 u32 link_speed;
106be53b 858 u8 match_prio;
d8822868 859 u16 peer_id;
5c65c564
OG		 860 int err;
861
d8822868 862 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 863 if (IS_ERR(peer_mdev)) {
864 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
865 return PTR_ERR(peer_mdev);
866 }
867
d8822868 868 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 869 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 870 return -EOPNOTSUPP;
871 }
872
d8822868 873 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 874 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
875 extack);
106be53b
OG		 876 if (err)
877 return err;
b32accda
VB		 878
879 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 880 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 881 if (hpe) {
882 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
883 wait_for_completion(&hpe->res_ready);
884
885 if (IS_ERR(hpe->hp)) {
886 err = -EREMOTEIO;
887 goto out_err;
888 }
5c65c564 889 goto attach_flow;
db76ca24 890 }
5c65c564
OG		 891
892 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 893 if (!hpe) {
db76ca24
VB		 894 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
895 return -ENOMEM;
b32accda 896 }
5c65c564 897
73edca73 898 spin_lock_init(&hpe->flows_lock);
5c65c564 899 INIT_LIST_HEAD(&hpe->flows);
db76ca24 900 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 901 hpe->peer_vhca_id = peer_id;
106be53b 902 hpe->prio = match_prio;
e4f9abbd 903 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 904 init_completion(&hpe->res_ready);
905
906 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
907 hash_hairpin_info(peer_id, match_prio));
908 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 909
6cdc686a 910 params.log_data_size = 16;
5c65c564
OG		 911 params.log_data_size = min_t(u8, params.log_data_size,
912 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
913 params.log_data_size = max_t(u8, params.log_data_size,
914 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 915
eb9180f7
OG		 916 params.log_num_packets = params.log_data_size -
917 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
918 params.log_num_packets = min_t(u8, params.log_num_packets,
919 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
920
921 params.q_counter = priv->q_counter;
3f6d08d1 922 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 923 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 924 link_speed = max_t(u32, link_speed, 50000);
925 link_speed64 = link_speed;
926 do_div(link_speed64, 50000);
927 params.num_channels = link_speed64;
928
5c65c564 929 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 930 hpe->hp = hp;
931 complete_all(&hpe->res_ready);
5c65c564
OG		 932 if (IS_ERR(hp)) {
933 err = PTR_ERR(hp);
db76ca24 934 goto out_err;
5c65c564
OG		 935 }
936
eb9180f7 937 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 938 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 939 dev_name(hp->pair->peer_mdev->device),
eb9180f7 940 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 941
5c65c564 942attach_flow:
3f6d08d1 943 if (hpe->hp->num_channels > 1) {
226f2ca3 944 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 945 flow->attr->nic_attr->hairpin_ft =
946 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 947 } else {
a6696735 948 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 949 }
b32accda 950
e4f9abbd 951 flow->hpe = hpe;
73edca73 952 spin_lock(&hpe->flows_lock);
5c65c564 953 list_add(&flow->hairpin, &hpe->flows);
73edca73 954 spin_unlock(&hpe->flows_lock);
3f6d08d1 955
5c65c564
OG		 956 return 0;
957
db76ca24
VB		 958out_err:
959 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 960 return err;
961}
962
963static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
964 struct mlx5e_tc_flow *flow)
965{
5a7e5bcb 966 /* flow wasn't fully initialized */
e4f9abbd 967 if (!flow->hpe)
5a7e5bcb
VB		 968 return;
969
73edca73 970 spin_lock(&flow->hpe->flows_lock);
5c65c564 971 list_del(&flow->hairpin);
73edca73
VB		 972 spin_unlock(&flow->hpe->flows_lock);
973
e4f9abbd
VB		 974 mlx5e_hairpin_put(priv, flow->hpe);
975 flow->hpe = NULL;
5c65c564
OG		 976}
977
08247066
AL		 978struct mlx5_flow_handle *
979mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
980 struct mlx5_flow_spec *spec,
c620b772 981 struct mlx5_flow_attr *attr)
e8f887ac 982{
08247066 983 struct mlx5_flow_context *flow_context = &spec->flow_context;
67d62ee7 984 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c620b772 985 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 986 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 987 struct mlx5_flow_destination dest[2] = {};
66958ed9 988 struct mlx5_flow_act flow_act = {
3bc4b7bf 989 .action = attr->action,
bb0ee7dc 990 .flags = FLOW_ACT_NO_APPEND,
66958ed9 991 };
08247066 992 struct mlx5_flow_handle *rule;
c7569097 993 struct mlx5_flow_table *ft;
08247066 994 int dest_ix = 0;
e8f887ac 995
bb0ee7dc 996 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 997 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 998
aedd133d
AL		 999 if (attr->dest_ft) {
1000 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1001 dest[dest_ix].ft = attr->dest_ft;
1002 dest_ix++;
1003 } else if (nic_attr->hairpin_ft) {
08247066 1004 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 1005 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 1006 dest_ix++;
c620b772 1007 } else if (nic_attr->hairpin_tirn) {
08247066 1008 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 1009 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 1010 dest_ix++;
3f6d08d1
OG		 1011 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1012 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 1013 if (attr->dest_chain) {
1014 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1015 attr->dest_chain, 1,
1016 MLX5E_TC_FT_LEVEL);
1017 if (IS_ERR(dest[dest_ix].ft))
1018 return ERR_CAST(dest[dest_ix].ft);
1019 } else {
6783f0a2 1020 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 1021 }
3f6d08d1 1022 dest_ix++;
5c65c564 1023 }
aad7e08d 1024
c7569097
AL		 1025 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1026 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1027 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1028
08247066 1029 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 1030 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 1031 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 1032 dest_ix++;
aad7e08d
AV		 1033 }
1034
08247066 1035 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 1036 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 1037
6a064674
AL		 1038 mutex_lock(&tc->t_lock);
1039 if (IS_ERR_OR_NULL(tc->t)) {
1040 /* Create the root table here if doesn't exist yet */
1041 tc->t =
c7569097 1042 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 1043
1044 if (IS_ERR(tc->t)) {
1045 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 1046 netdev_err(priv->netdev,
1047 "Failed to create tc offload table\n");
c7569097
AL		 1048 rule = ERR_CAST(priv->fs.tc.t);
1049 goto err_ft_get;
e8f887ac 1050 }
e8f887ac 1051 }
08247066 1052 mutex_unlock(&tc->t_lock);
e8f887ac 1053
aedd133d
AL		 1054 if (attr->chain || attr->prio)
1055 ft = mlx5_chains_get_table(nic_chains,
1056 attr->chain, attr->prio,
1057 MLX5E_TC_FT_LEVEL);
1058 else
1059 ft = attr->ft;
1060
c7569097
AL		 1061 if (IS_ERR(ft)) {
1062 rule = ERR_CAST(ft);
1063 goto err_ft_get;
1064 }
1065
c620b772 1066 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1067 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1068
c7569097 1069 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1070 &flow_act, dest, dest_ix);
1071 if (IS_ERR(rule))
c7569097 1072 goto err_rule;
08247066
AL		 1073
1074 return rule;
c7569097
AL		 1075
1076err_rule:
aedd133d
AL		 1077 if (attr->chain || attr->prio)
1078 mlx5_chains_put_table(nic_chains,
1079 attr->chain, attr->prio,
1080 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1081err_ft_get:
1082 if (attr->dest_chain)
1083 mlx5_chains_put_table(nic_chains,
1084 attr->dest_chain, 1,
1085 MLX5E_TC_FT_LEVEL);
1086
1087 return ERR_CAST(rule);
08247066
AL		 1088}
1089
df67ad62
RD		 1090static int
1091alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1092 struct mlx5_flow_attr *attr)
1093
1094{
1095 struct mlx5_fc *counter;
1096
1097 counter = mlx5_fc_create(counter_dev, true);
1098 if (IS_ERR(counter))
1099 return PTR_ERR(counter);
1100
1101 attr->counter = counter;
1102 return 0;
1103}
1104
08247066
AL		 1105static int
1106mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1107 struct mlx5e_tc_flow *flow,
1108 struct netlink_ext_ack *extack)
1109{
c6cfe113 1110 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1111 struct mlx5_flow_attr *attr = flow->attr;
08247066 1112 struct mlx5_core_dev *dev = priv->mdev;
08247066
AL		 1113 int err;
1114
c6cfe113
RD		 1115 parse_attr = attr->parse_attr;
1116
08247066
AL		 1117 if (flow_flag_test(flow, HAIRPIN)) {
1118 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1119 if (err)
1120 return err;
1121 }
1122
1123 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
df67ad62
RD		 1124 err = alloc_flow_attr_counter(dev, attr);
1125 if (err)
1126 return err;
08247066
AL		 1127 }
1128
1129 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1130 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
2c0e5cf5 1131 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
08247066
AL		 1132 if (err)
1133 return err;
1134 }
1135
84ba8062 1136 if (attr->flags & MLX5_ATTR_FLAG_CT)
a572c0a7 1137 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), &parse_attr->spec,
aedd133d
AL		 1138 attr, &parse_attr->mod_hdr_acts);
1139 else
1140 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1141 attr);
aad7e08d 1142
a2b7189b 1143 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1144}
1145
08247066 1146void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1147 struct mlx5_flow_handle *rule,
1148 struct mlx5_flow_attr *attr)
08247066 1149{
67d62ee7 1150 struct mlx5_fs_chains *nic_chains = mlx5e_nic_chains(priv);
c7569097 1151
08247066 1152 mlx5_del_flow_rules(rule);
c7569097 1153
aedd133d
AL		 1154 if (attr->chain || attr->prio)
1155 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1156 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1157
1158 if (attr->dest_chain)
1159 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1160 MLX5E_TC_FT_LEVEL);
08247066
AL		 1161}
1162
d85cdccb
OG		 1163static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1164 struct mlx5e_tc_flow *flow)
1165{
c620b772 1166 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1167 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1168
c7569097
AL		 1169 flow_flag_clear(flow, OFFLOADED);
1170
84ba8062 1171 if (attr->flags & MLX5_ATTR_FLAG_CT)
a572c0a7 1172 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
aedd133d
AL		 1173 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1174 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1175
c7569097
AL		 1176 /* Remove root table if no rules are left to avoid
1177 * extra steering hops.
1178 */
b6fac0b4 1179 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1180 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1181 !IS_ERR_OR_NULL(tc->t)) {
67d62ee7 1182 mlx5_chains_put_table(mlx5e_nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1183 priv->fs.tc.t = NULL;
1184 }
b6fac0b4 1185 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1186
513f8f7f 1187 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1188 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1189
972fe492
RD		 1190 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1191 mlx5_fc_destroy(priv->mdev, attr->counter);
aedd133d 1192
226f2ca3 1193 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1194 mlx5e_hairpin_flow_del(priv, flow);
c620b772 1195
88d97486 1196 kvfree(attr->parse_attr);
c620b772 1197 kfree(flow->attr);
d85cdccb
OG		 1198}
1199
0d9f9647 1200struct mlx5_flow_handle *
6d2a3ed0
OG		 1201mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1202 struct mlx5e_tc_flow *flow,
1203 struct mlx5_flow_spec *spec,
c620b772 1204 struct mlx5_flow_attr *attr)
6d2a3ed0
OG		 1205{
1206 struct mlx5_flow_handle *rule;
4c3844d9 1207
e5d4e1da 1208 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
89e39467
PB		 1209 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1210
a572c0a7 1211 rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
6d2a3ed0 1212
6d2a3ed0
OG		 1213 if (IS_ERR(rule))
1214 return rule;
1215
c620b772 1216 if (attr->esw_attr->split_count) {
6d2a3ed0 1217 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
84ba8062
RD		 1218 if (IS_ERR(flow->rule[1]))
1219 goto err_rule1;
6d2a3ed0
OG		 1220 }
1221
6d2a3ed0 1222 return rule;
84ba8062
RD		 1223
1224err_rule1:
a572c0a7 1225 mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
84ba8062 1226 return flow->rule[1];
6d2a3ed0
OG		 1227}
1228
0d9f9647
VB		 1229void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1230 struct mlx5e_tc_flow *flow,
1231 struct mlx5_flow_attr *attr)
6d2a3ed0 1232{
226f2ca3 1233 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1234
e5d4e1da 1235 if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
84ba8062 1236 return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
89e39467 1237
c620b772 1238 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1239 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1240
a572c0a7 1241 mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
6d2a3ed0
OG		 1242}
1243
0d9f9647 1244struct mlx5_flow_handle *
5dbe906f
PB		 1245mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1246 struct mlx5e_tc_flow *flow,
178f69b4 1247 struct mlx5_flow_spec *spec)
5dbe906f 1248{
c620b772 1249 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1250 struct mlx5_flow_handle *rule;
1251
c620b772
AL		 1252 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1253 if (!slow_attr)
1254 return ERR_PTR(-ENOMEM);
5dbe906f 1255
c620b772
AL		 1256 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1257 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1258 slow_attr->esw_attr->split_count = 0;
e5d4e1da 1259 slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
c620b772
AL		 1260
1261 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1262 if (!IS_ERR(rule))
226f2ca3 1263 flow_flag_set(flow, SLOW);
5dbe906f 1264
c620b772
AL		 1265 kfree(slow_attr);
1266
5dbe906f
PB		 1267 return rule;
1268}
1269
0d9f9647
VB		 1270void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1271 struct mlx5e_tc_flow *flow)
5dbe906f 1272{
c620b772 1273 struct mlx5_flow_attr *slow_attr;
178f69b4 1274
c620b772 1275 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1276 if (!slow_attr) {
1277 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1278 return;
1279 }
c620b772
AL		 1280
1281 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1282 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1283 slow_attr->esw_attr->split_count = 0;
e5d4e1da 1284 slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
c620b772 1285 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1286 flow_flag_clear(flow, SLOW);
c620b772 1287 kfree(slow_attr);
5dbe906f
PB		 1288}
1289
ad86755b
VB		 1290/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1291 * function.
1292 */
1293static void unready_flow_add(struct mlx5e_tc_flow *flow,
1294 struct list_head *unready_flows)
1295{
1296 flow_flag_set(flow, NOT_READY);
1297 list_add_tail(&flow->unready, unready_flows);
1298}
1299
1300/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1301 * function.
1302 */
1303static void unready_flow_del(struct mlx5e_tc_flow *flow)
1304{
1305 list_del(&flow->unready);
1306 flow_flag_clear(flow, NOT_READY);
1307}
1308
b4a23329
RD		 1309static void add_unready_flow(struct mlx5e_tc_flow *flow)
1310{
1311 struct mlx5_rep_uplink_priv *uplink_priv;
1312 struct mlx5e_rep_priv *rpriv;
1313 struct mlx5_eswitch *esw;
1314
1315 esw = flow->priv->mdev->priv.eswitch;
1316 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1317 uplink_priv = &rpriv->uplink_priv;
1318
ad86755b
VB		 1319 mutex_lock(&uplink_priv->unready_flows_lock);
1320 unready_flow_add(flow, &uplink_priv->unready_flows);
1321 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1322}
1323
1324static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1325{
ad86755b
VB		 1326 struct mlx5_rep_uplink_priv *uplink_priv;
1327 struct mlx5e_rep_priv *rpriv;
1328 struct mlx5_eswitch *esw;
1329
1330 esw = flow->priv->mdev->priv.eswitch;
1331 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1332 uplink_priv = &rpriv->uplink_priv;
1333
1334 mutex_lock(&uplink_priv->unready_flows_lock);
1335 unready_flow_del(flow);
1336 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1337}
1338
a508728a 1339bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1340{
1341 struct mlx5_core_dev *out_mdev, *route_mdev;
1342 struct mlx5e_priv *out_priv, *route_priv;
1343
1344 out_priv = netdev_priv(out_dev);
1345 out_mdev = out_priv->mdev;
1346 route_priv = netdev_priv(route_dev);
1347 route_mdev = route_priv->mdev;
1348
1349 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1350 route_mdev->coredev_type != MLX5_COREDEV_VF)
1351 return false;
1352
ab3f3d5e 1353 return mlx5e_same_hw_devs(out_priv, route_priv);
10742efc
VB		 1354}
1355
a508728a 1356int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1357{
1358 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1359 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1360 struct mlx5_core_dev *route_mdev;
1361 struct mlx5_eswitch *esw;
1362 u16 vhca_id;
1363 int err;
1364
1365 out_priv = netdev_priv(out_dev);
1366 esw = out_priv->mdev->priv.eswitch;
1367 route_priv = netdev_priv(route_dev);
1368 route_mdev = route_priv->mdev;
1369
1370 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1371 if (mlx5_lag_is_active(out_priv->mdev)) {
1372 /* In lag case we may get devices from different eswitch instances.
1373 * If we failed to get vport num, it means, mostly, that we on the wrong
1374 * eswitch.
1375 */
1376 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1377 if (err != -ENOENT)
1378 return err;
1379
1380 devcom = out_priv->mdev->priv.devcom;
1381 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1382 if (!esw)
1383 return -ENODEV;
1384 }
1385
10742efc 1386 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1387 if (devcom)
1388 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1389 return err;
1390}
1391
c7b9038d 1392int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
ff993167
RD		 1393 struct mlx5e_tc_flow *flow,
1394 struct mlx5_flow_attr *attr)
c7b9038d 1395{
ff993167 1396 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
c7b9038d
VB		 1397 struct mlx5_modify_hdr *mod_hdr;
1398
1399 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
e36db1ee 1400 mlx5e_get_flow_namespace(flow),
c7b9038d
VB		 1401 mod_hdr_acts->num_actions,
1402 mod_hdr_acts->actions);
1403 if (IS_ERR(mod_hdr))
1404 return PTR_ERR(mod_hdr);
1405
ff993167
RD		 1406 WARN_ON(attr->modify_hdr);
1407 attr->modify_hdr = mod_hdr;
c7b9038d
VB		 1408
1409 return 0;
1410}
1411
39542e23
RD		 1412static int
1413set_encap_dests(struct mlx5e_priv *priv,
1414 struct mlx5e_tc_flow *flow,
c118ebc9 1415 struct mlx5_flow_attr *attr,
39542e23
RD		 1416 struct netlink_ext_ack *extack,
1417 bool *encap_valid,
1418 bool *vf_tun)
1419{
1420 struct mlx5e_tc_flow_parse_attr *parse_attr;
39542e23
RD		 1421 struct mlx5_esw_flow_attr *esw_attr;
1422 struct net_device *encap_dev = NULL;
1423 struct mlx5e_rep_priv *rpriv;
1424 struct mlx5e_priv *out_priv;
1425 int out_index;
1426 int err = 0;
1427
1428 parse_attr = attr->parse_attr;
1429 esw_attr = attr->esw_attr;
1430 *vf_tun = false;
1431 *encap_valid = true;
1432
1433 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1434 struct net_device *out_dev;
1435 int mirred_ifindex;
1436
1437 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1438 continue;
1439
1440 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
1441 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1442 if (!out_dev) {
1443 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1444 err = -ENODEV;
1445 goto out;
1446 }
c118ebc9 1447 err = mlx5e_attach_encap(priv, flow, attr, out_dev, out_index,
39542e23
RD		 1448 extack, &encap_dev, encap_valid);
1449 dev_put(out_dev);
1450 if (err)
1451 goto out;
1452
1453 if (esw_attr->dests[out_index].flags &
1454 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1455 !esw_attr->dest_int_port)
1456 *vf_tun = true;
1457
1458 out_priv = netdev_priv(encap_dev);
1459 rpriv = out_priv->ppriv;
1460 esw_attr->dests[out_index].rep = rpriv->rep;
1461 esw_attr->dests[out_index].mdev = out_priv->mdev;
1462 }
1463
1464 if (*vf_tun && esw_attr->out_count > 1) {
1465 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1466 err = -EOPNOTSUPP;
1467 goto out;
1468 }
1469
1470out:
1471 return err;
1472}
1473
1474static void
1475clean_encap_dests(struct mlx5e_priv *priv,
1476 struct mlx5e_tc_flow *flow,
c118ebc9 1477 struct mlx5_flow_attr *attr,
39542e23
RD		 1478 bool *vf_tun)
1479{
39542e23
RD		 1480 struct mlx5_esw_flow_attr *esw_attr;
1481 int out_index;
1482
1483 esw_attr = attr->esw_attr;
1484 *vf_tun = false;
1485
1486 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
1487 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
1488 continue;
1489
1490 if (esw_attr->dests[out_index].flags &
1491 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE &&
1492 !esw_attr->dest_int_port)
1493 *vf_tun = true;
1494
c118ebc9 1495 mlx5e_detach_encap(priv, flow, attr, out_index);
39542e23
RD		 1496 kfree(attr->parse_attr->tun_info[out_index]);
1497 }
1498}
1499
c83954ab 1500static int
74491de9 1501mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1502 struct mlx5e_tc_flow *flow,
1503 struct netlink_ext_ack *extack)
adb4c123
OG		 1504{
1505 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1506 struct mlx5e_tc_flow_parse_attr *parse_attr;
1507 struct mlx5_flow_attr *attr = flow->attr;
1508 struct mlx5_esw_flow_attr *esw_attr;
39542e23 1509 bool vf_tun, encap_valid;
39ac237c 1510 u32 max_prio, max_chain;
0ad060ee 1511 int err = 0;
8b32580d 1512
b16eb3c8
AL		 1513 parse_attr = attr->parse_attr;
1514 esw_attr = attr->esw_attr;
1515
84179981
PB		 1516 /* We check chain range only for tc flows.
1517 * For ft flows, we checked attr->chain was originally 0 and set it to
1518 * FDB_FT_CHAIN which is outside tc range.
1519 * See mlx5e_rep_setup_ft_cb().
1520 */
ae430332 1521 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1522 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1523 NL_SET_ERR_MSG_MOD(extack,
1524 "Requested chain is out of supported range");
8914add2
VB		 1525 err = -EOPNOTSUPP;
1526 goto err_out;
bf07aa73
PB		 1527 }
1528
ae430332 1529 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1530 if (attr->prio > max_prio) {
61644c3d
RD		 1531 NL_SET_ERR_MSG_MOD(extack,
1532 "Requested priority is out of supported range");
8914add2
VB		 1533 err = -EOPNOTSUPP;
1534 goto err_out;
bf07aa73 1535 }
e52c2802 1536
777bb800
VB		 1537 if (flow_flag_test(flow, TUN_RX)) {
1538 err = mlx5e_attach_decap_route(priv, flow);
1539 if (err)
8914add2 1540 goto err_out;
b16eb3c8 1541
5b209d1a
RD		 1542 if (!attr->chain && esw_attr->int_port &&
1543 attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
b16eb3c8
AL		 1544 /* If decap route device is internal port, change the
1545 * source vport value in reg_c0 back to uplink just in
1546 * case the rule performs goto chain > 0. If we have a miss
1547 * on chain > 0 we want the metadata regs to hold the
1548 * chain id so SW will resume handling of this packet
1549 * from the proper chain.
1550 */
1551 u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1552 esw_attr->in_rep->vport);
1553
1554 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1555 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1556 metadata);
1557 if (err)
31108d14 1558 goto err_out;
077cdda7
RD		 1559
1560 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
b16eb3c8 1561 }
777bb800
VB		 1562 }
1563
14e6b038
EC		 1564 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1565 err = mlx5e_attach_decap(priv, flow, extack);
1566 if (err)
8914add2 1567 goto err_out;
14e6b038
EC		 1568 }
1569
166f431e
AL		 1570 if (netif_is_ovs_master(parse_attr->filter_dev)) {
1571 struct mlx5e_tc_int_port *int_port;
1572
1573 if (attr->chain) {
1574 NL_SET_ERR_MSG_MOD(extack,
1575 "Internal port rule is only supported on chain 0");
31108d14
CJ		 1576 err = -EOPNOTSUPP;
1577 goto err_out;
166f431e
AL		 1578 }
1579
1580 if (attr->dest_chain) {
1581 NL_SET_ERR_MSG_MOD(extack,
1582 "Internal port rule offload doesn't support goto action");
31108d14
CJ		 1583 err = -EOPNOTSUPP;
1584 goto err_out;
166f431e
AL		 1585 }
1586
1587 int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1588 parse_attr->filter_dev->ifindex,
1589 flow_flag_test(flow, EGRESS) ?
1590 MLX5E_TC_INT_PORT_EGRESS :
1591 MLX5E_TC_INT_PORT_INGRESS);
31108d14
CJ		 1592 if (IS_ERR(int_port)) {
1593 err = PTR_ERR(int_port);
1594 goto err_out;
1595 }
166f431e
AL		 1596
1597 esw_attr->int_port = int_port;
1598 }
1599
c118ebc9 1600 err = set_encap_dests(priv, flow, attr, extack, &encap_valid, &vf_tun);
39542e23 1601 if (err)
7d1a3d08 1602 goto err_out;
7d1a3d08 1603
8b32580d 1604 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1605 if (err)
8914add2 1606 goto err_out;
adb4c123 1607
efe6f961 1608 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
8914add2 1609 if (vf_tun) {
ff993167 1610 err = mlx5e_tc_add_flow_mod_hdr(priv, flow, attr);
8914add2
VB		 1611 if (err)
1612 goto err_out;
1613 } else {
1614 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1615 if (err)
1616 goto err_out;
1617 }
d7e75a32
OG		 1618 }
1619
b8aee822 1620 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
df67ad62
RD		 1621 err = alloc_flow_attr_counter(esw_attr->counter_dev, attr);
1622 if (err)
8914add2 1623 goto err_out;
b8aee822
MB		 1624 }
1625
0ad060ee
RD		 1626 /* we get here if one of the following takes place:
1627 * (1) there's no error
1628 * (2) there's an encap action and we don't have valid neigh
3c37745e 1629 */
bc1d75fa 1630 if (!encap_valid)
178f69b4 1631 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1632 else
6d2a3ed0 1633 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1634
8914add2
VB		 1635 if (IS_ERR(flow->rule[0])) {
1636 err = PTR_ERR(flow->rule[0]);
1637 goto err_out;
1638 }
1639 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1640
1641 return 0;
8914add2
VB		 1642
1643err_out:
1644 flow_flag_set(flow, FAILED);
1645 return err;
aa0cbbae 1646}
d85cdccb 1647
9272e3df
YK		 1648static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1649{
c620b772 1650 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1651 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1652 spec->match_value,
1653 misc_parameters_3);
1654 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1655 headers_v,
1656 geneve_tlv_option_0_data);
1657
1658 return !!geneve_tlv_opt_0_data;
1659}
1660
d85cdccb
OG		 1661static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1662 struct mlx5e_tc_flow *flow)
1663{
1664 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1665 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1666 struct mlx5_esw_flow_attr *esw_attr;
39542e23 1667 bool vf_tun;
d85cdccb 1668
777bb800 1669 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1670 mlx5e_put_flow_tunnel_id(flow);
1671
12a240a4 1672 if (flow_flag_test(flow, NOT_READY))
b4a23329 1673 remove_unready_flow(flow);
ef06c9ee 1674
226f2ca3
VB		 1675 if (mlx5e_is_offloaded_flow(flow)) {
1676 if (flow_flag_test(flow, SLOW))
178f69b4 1677 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1678 else
1679 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1680 }
362980ea 1681 complete_all(&flow->del_hw_done);
d85cdccb 1682
9272e3df
YK		 1683 if (mlx5_flow_has_geneve_opt(flow))
1684 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1685
513f8f7f 1686 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1687
777bb800
VB		 1688 if (flow->decap_route)
1689 mlx5e_detach_decap_route(priv, flow);
1690
c118ebc9 1691 clean_encap_dests(priv, flow, attr, &vf_tun);
d7e75a32 1692
aedd133d 1693 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1694
c7b9038d 1695 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
2c0e5cf5 1696 mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1697 if (vf_tun && attr->modify_hdr)
1698 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1699 else
1700 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1701 }
b8aee822
MB		 1702
1703 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1704 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038 1705
166f431e
AL		 1706 if (esw_attr->int_port)
1707 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->int_port);
1708
27484f71
AL		 1709 if (esw_attr->dest_int_port)
1710 mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(priv), esw_attr->dest_int_port);
1711
14e6b038
EC		 1712 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1713 mlx5e_detach_decap(priv, flow);
c620b772 1714
88d97486
RD		 1715 kvfree(attr->esw_attr->rx_tun_attr);
1716 kvfree(attr->parse_attr);
c620b772 1717 kfree(flow->attr);
d85cdccb
OG		 1718}
1719
0d9f9647 1720struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1721{
c620b772 1722 return flow->attr->counter;
b8aee822
MB		 1723}
1724
6a06c2f7 1725/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1726void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1727{
1728 struct mlx5e_tc_flow *flow, *tmp;
1729
1730 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1731 mlx5e_flow_put(priv, flow);
1732}
1733
04de7dda
RD		 1734static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1735{
1736 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1737
226f2ca3
VB		 1738 if (!flow_flag_test(flow, ESWITCH) ||
1739 !flow_flag_test(flow, DUP))
04de7dda
RD		 1740 return;
1741
1742 mutex_lock(&esw->offloads.peer_mutex);
1743 list_del(&flow->peer);
1744 mutex_unlock(&esw->offloads.peer_mutex);
1745
226f2ca3 1746 flow_flag_clear(flow, DUP);
04de7dda 1747
eb252c3a
RD		 1748 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1749 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1750 kfree(flow->peer_flow);
1751 }
1752
04de7dda
RD		 1753 flow->peer_flow = NULL;
1754}
1755
1756static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1757{
1758 struct mlx5_core_dev *dev = flow->priv->mdev;
1759 struct mlx5_devcom *devcom = dev->priv.devcom;
1760 struct mlx5_eswitch *peer_esw;
1761
1762 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1763 if (!peer_esw)
1764 return;
1765
1766 __mlx5e_tc_del_fdb_peer_flow(flow);
1767 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1768}
1769
e8f887ac 1770static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1771 struct mlx5e_tc_flow *flow)
e8f887ac 1772{
226f2ca3 1773 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1774 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1775 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1776 } else {
d85cdccb 1777 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1778 }
e8f887ac
AV		 1779}
1780
ee950e5d 1781static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1782{
1783 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1784 struct flow_action *flow_action = &rule->action;
1785 const struct flow_action_entry *act;
1786 int i;
1787
ee950e5d
CM		 1788 if (chain)
1789 return false;
1790
0a7fcb78
PB		 1791 flow_action_for_each(i, act, flow_action) {
1792 switch (act->id) {
1793 case FLOW_ACTION_GOTO:
1794 return true;
ee950e5d
CM		 1795 case FLOW_ACTION_SAMPLE:
1796 return true;
0a7fcb78
PB		 1797 default:
1798 continue;
1799 }
1800 }
1801
1802 return false;
1803}
bbd00f7e 1804
0a7fcb78
PB		 1805static int
1806enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1807 struct flow_dissector_key_enc_opts *opts,
1808 struct netlink_ext_ack *extack,
1809 bool *dont_care)
1810{
1811 struct geneve_opt *opt;
1812 int off = 0;
1813
1814 *dont_care = true;
1815
1816 while (opts->len > off) {
1817 opt = (struct geneve_opt *)&opts->data[off];
1818
1819 if (!(*dont_care) || opt->opt_class || opt->type ||
1820 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1821 *dont_care = false;
1822
c51323ee 1823 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1824 opt->type != U8_MAX) {
c50775d0
RD		 1825 NL_SET_ERR_MSG_MOD(extack,
1826 "Partial match of tunnel options in chain > 0 isn't supported");
0a7fcb78
PB		 1827 netdev_warn(priv->netdev,
1828 "Partial match of tunnel options in chain > 0 isn't supported");
1829 return -EOPNOTSUPP;
1830 }
1831 }
1832
1833 off += sizeof(struct geneve_opt) + opt->length * 4;
1834 }
1835
1836 return 0;
1837}
1838
1839#define COPY_DISSECTOR(rule, diss_key, dst)\
1840({ \
1841 struct flow_rule *__rule = (rule);\
1842 typeof(dst) __dst = dst;\
1843\
1844 memcpy(__dst,\
1845 skb_flow_dissector_target(__rule->match.dissector,\
1846 diss_key,\
1847 __rule->match.key),\
1848 sizeof(*__dst));\
1849})
1850
1851static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1852 struct mlx5e_tc_flow *flow,
1853 struct flow_cls_offload *f,
1854 struct net_device *filter_dev)
bbd00f7e 1855{
f9e30088 1856 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1857 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1858 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1859 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1860 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1861 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1862 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1863 struct mlx5e_rep_priv *uplink_rpriv;
1864 struct tunnel_match_key tunnel_key;
1865 bool enc_opts_is_dont_care = true;
1866 u32 tun_id, enc_opts_id = 0;
1867 struct mlx5_eswitch *esw;
1868 u32 value, mask;
8f256622 1869 int err;
2e72eb43 1870
0a7fcb78
PB		 1871 esw = priv->mdev->priv.eswitch;
1872 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1873 uplink_priv = &uplink_rpriv->uplink_priv;
1874
1875 memset(&tunnel_key, 0, sizeof(tunnel_key));
1876 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1877 &tunnel_key.enc_control);
1878 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1879 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1880 &tunnel_key.enc_ipv4);
1881 else
1882 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1883 &tunnel_key.enc_ipv6);
1884 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1885 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1886 &tunnel_key.enc_tp);
1887 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1888 &tunnel_key.enc_key_id);
1889 tunnel_key.filter_ifindex = filter_dev->ifindex;
1890
1891 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1892 if (err)
101f4de9 1893 return err;
bbd00f7e 1894
0a7fcb78
PB		 1895 flow_rule_match_enc_opts(rule, &enc_opts_match);
1896 err = enc_opts_is_dont_care_or_full_match(priv,
1897 enc_opts_match.mask,
1898 extack,
1899 &enc_opts_is_dont_care);
1900 if (err)
1901 goto err_enc_opts;
fe1587a7 1902
0a7fcb78 1903 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1904 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1905 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1906 sizeof(*enc_opts_match.key));
1907 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1908 sizeof(*enc_opts_match.mask));
1909
0a7fcb78 1910 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1911 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1912 if (err)
1913 goto err_enc_opts;
1914 }
fe1587a7 1915
0a7fcb78
PB		 1916 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1917 mask = enc_opts_id ? TUNNEL_ID_MASK :
1918 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1919
0a7fcb78
PB		 1920 if (attr->chain) {
1921 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1922 TUNNEL_TO_REG, value, mask);
1923 } else {
1924 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1925 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1926 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1927 TUNNEL_TO_REG, value);
1928 if (err)
1929 goto err_set;
fe1587a7 1930
0a7fcb78 1931 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1932 }
bbd00f7e 1933
73a3f1bc 1934 flow->attr->tunnel_id = value;
0a7fcb78 1935 return 0;
bcef735c 1936
0a7fcb78
PB		 1937err_set:
1938 if (enc_opts_id)
1939 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1940 enc_opts_id);
1941err_enc_opts:
1942 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1943 return err;
1944}
bcef735c 1945
0a7fcb78
PB		 1946static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1947{
73a3f1bc
RD		 1948 u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
1949 u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
0a7fcb78
PB		 1950 struct mlx5_rep_uplink_priv *uplink_priv;
1951 struct mlx5e_rep_priv *uplink_rpriv;
1952 struct mlx5_eswitch *esw;
bcef735c 1953
0a7fcb78
PB		 1954 esw = flow->priv->mdev->priv.eswitch;
1955 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1956 uplink_priv = &uplink_rpriv->uplink_priv;
1957
1958 if (tun_id)
1959 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1960 if (enc_opts_id)
1961 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1962 enc_opts_id);
1963}
e98bedf5 1964
fca53304
EB		 1965void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1966 struct flow_match_basic *match, bool outer,
1967 void *headers_c, void *headers_v)
1968{
1969 bool ip_version_cap;
1970
1971 ip_version_cap = outer ?
1972 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1973 ft_field_support.outer_ip_version) :
1974 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1975 ft_field_support.inner_ip_version);
1976
1977 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1978 (match->key->n_proto == htons(ETH_P_IP) ||
1979 match->key->n_proto == htons(ETH_P_IPV6))) {
1980 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1981 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1982 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1983 } else {
1984 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1985 ntohs(match->mask->n_proto));
1986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1987 ntohs(match->key->n_proto));
1988 }
4a5d5d73
EB		 1989}
1990
0d9f9647 1991u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1992{
1993 void *headers_v;
1994 u16 ethertype;
1995 u8 ip_version;
1996
1997 if (outer)
1998 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1999 else
2000 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2001
2002 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2003 /* Return ip_version converted from ethertype anyway */
2004 if (!ip_version) {
2005 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2006 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2007 ip_version = 4;
2008 else if (ethertype == ETH_P_IPV6)
2009 ip_version = 6;
2010 }
2011 return ip_version;
2012}
2013
b6dfff21
PB		 2014/* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2015 * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2016 * +---------+----------------------------------------+
2017 * |Arriving | Arriving Outer Header |
2018 * | Inner +---------+---------+---------+----------+
2019 * | Header | Not-ECT | ECT(0) | ECT(1) | CE |
2020 * +---------+---------+---------+---------+----------+
2021 * | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop> |
2022 * | ECT(0) | ECT(0) | ECT(0) | ECT(1) | CE* |
2023 * | ECT(1) | ECT(1) | ECT(1) | ECT(1)* | CE* |
2024 * | CE | CE | CE | CE | CE |
2025 * +---------+---------+---------+---------+----------+
2026 *
2027 * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2028 * the inner ip_ecn value before hardware decap action.
2029 *
2030 * Cells marked are changed from original inner packet ip_ecn value during decap, and
2031 * so matching those values on inner ip_ecn before decap will fail.
2032 *
2033 * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2034 * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2035 * and such we can drop the inner ip_ecn=CE match.
2036 */
2037
2038static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2039 struct flow_cls_offload *f,
2040 bool *match_inner_ecn)
2041{
2042 u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2043 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2044 struct netlink_ext_ack *extack = f->common.extack;
2045 struct flow_match_ip match;
2046
2047 *match_inner_ecn = true;
2048
2049 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2050 flow_rule_match_enc_ip(rule, &match);
2051 outer_ecn_key = match.key->tos & INET_ECN_MASK;
2052 outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2053 }
2054
2055 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2056 flow_rule_match_ip(rule, &match);
2057 inner_ecn_key = match.key->tos & INET_ECN_MASK;
2058 inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2059 }
2060
2061 if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2062 NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2063 netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2064 return -EOPNOTSUPP;
2065 }
2066
2067 if (!outer_ecn_mask) {
2068 if (!inner_ecn_mask)
2069 return 0;
2070
2071 NL_SET_ERR_MSG_MOD(extack,
2072 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2073 netdev_warn(priv->netdev,
2074 "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2075 return -EOPNOTSUPP;
2076 }
2077
2078 if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2079 NL_SET_ERR_MSG_MOD(extack,
2080 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2081 netdev_warn(priv->netdev,
2082 "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2083 return -EOPNOTSUPP;
2084 }
2085
2086 if (!inner_ecn_mask)
2087 return 0;
2088
2089 /* Both inner and outer have full mask on ecn */
2090
2091 if (outer_ecn_key == INET_ECN_ECT_1) {
2092 /* inner ecn might change by DECAP action */
2093
2094 NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2095 netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2096 return -EOPNOTSUPP;
2097 }
2098
2099 if (outer_ecn_key != INET_ECN_CE)
2100 return 0;
2101
2102 if (inner_ecn_key != INET_ECN_CE) {
2103 /* Can't happen in software, as packet ecn will be changed to CE after decap */
2104 NL_SET_ERR_MSG_MOD(extack,
2105 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2106 netdev_warn(priv->netdev,
2107 "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2108 return -EOPNOTSUPP;
2109 }
2110
2111 /* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2112 * drop match on inner ecn
2113 */
2114 *match_inner_ecn = false;
2115
2116 return 0;
2117}
2118
bbd00f7e 2119static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 2120 struct mlx5e_tc_flow *flow,
bbd00f7e 2121 struct mlx5_flow_spec *spec,
f9e30088 2122 struct flow_cls_offload *f,
0a7fcb78
PB		 2123 struct net_device *filter_dev,
2124 u8 *match_level,
2125 bool *match_inner)
bbd00f7e 2126{
a508728a 2127 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 2128 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 2129 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 2130 bool needs_mapping, sets_mapping;
8f256622 2131 int err;
2e72eb43 2132
0885ae1a
A		 2133 if (!mlx5e_is_eswitch_flow(flow)) {
2134 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
0a7fcb78 2135 return -EOPNOTSUPP;
0885ae1a 2136 }
0a7fcb78 2137
c620b772 2138 needs_mapping = !!flow->attr->chain;
ee950e5d 2139 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 2140 *match_inner = !needs_mapping;
2141
2142 if ((needs_mapping || sets_mapping) &&
636bb968 2143 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
c50775d0
RD		 2144 NL_SET_ERR_MSG_MOD(extack,
2145 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2146 netdev_warn(priv->netdev,
636bb968 2147 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 2148 return -EOPNOTSUPP;
bbd00f7e
HHZ		 2149 }
2150
c620b772 2151 if (!flow->attr->chain) {
0a7fcb78
PB		 2152 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2153 match_level);
2154 if (err) {
e98bedf5 2155 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 2156 "Failed to parse tunnel attributes");
2157 netdev_warn(priv->netdev,
2158 "Failed to parse tunnel attributes");
2159 return err;
e98bedf5
EB		 2160 }
2161
14e6b038
EC		 2162 /* With mpls over udp we decapsulate using packet reformat
2163 * object
2164 */
2165 if (!netif_is_bareudp(filter_dev))
c620b772 2166 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 2167 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2168 if (err)
2169 return err;
2170 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
2171 struct mlx5_flow_spec *tmp_spec;
2172
2173 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2174 if (!tmp_spec) {
2175 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
2176 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
2177 return -ENOMEM;
2178 }
2179 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2180
2181 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2182 if (err) {
2183 kvfree(tmp_spec);
2184 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2185 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2186 return err;
2187 }
2188 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2189 kvfree(tmp_spec);
2190 if (err)
2191 return err;
bcef735c
OG		 2192 }
2193
0a7fcb78
PB		 2194 if (!needs_mapping && !sets_mapping)
2195 return 0;
bbd00f7e 2196
0a7fcb78 2197 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 2198}
bbd00f7e 2199
0a7fcb78 2200static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 2201{
0a7fcb78
PB		 2202 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2203 inner_headers);
bbd00f7e
HHZ		 2204}
2205
0a7fcb78 2206static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 2207{
0a7fcb78
PB		 2208 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2209 inner_headers);
2210}
2211
2212static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2213{
2214 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2215 outer_headers);
2216}
2217
2218static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2219{
2220 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2221 outer_headers);
8377629e
EB		 2222}
2223
8ee72638 2224void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
8377629e
EB		 2225{
2226 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 2227 get_match_inner_headers_value(spec) :
2228 get_match_outer_headers_value(spec);
2229}
2230
8ee72638 2231void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
0a7fcb78
PB		 2232{
2233 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2234 get_match_inner_headers_criteria(spec) :
2235 get_match_outer_headers_criteria(spec);
8377629e
EB		 2236}
2237
6d65bc64 2238static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2239 struct flow_cls_offload *f)
2240{
2241 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2242 struct netlink_ext_ack *extack = f->common.extack;
2243 struct net_device *ingress_dev;
2244 struct flow_match_meta match;
2245
2246 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2247 return 0;
2248
2249 flow_rule_match_meta(rule, &match);
e3e0f9b2 2250 if (!match.mask->ingress_ifindex)
2251 return 0;
2252
6d65bc64 2253 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2254 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2255 return -EOPNOTSUPP;
6d65bc64 2256 }
2257
2258 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2259 match.key->ingress_ifindex);
2260 if (!ingress_dev) {
2261 NL_SET_ERR_MSG_MOD(extack,
2262 "Can't find the ingress port to match on");
a683012a 2263 return -ENOENT;
6d65bc64 2264 }
2265
2266 if (ingress_dev != filter_dev) {
2267 NL_SET_ERR_MSG_MOD(extack,
2268 "Can't match on the ingress filter port");
a683012a 2269 return -EOPNOTSUPP;
6d65bc64 2270 }
2271
2272 return 0;
2273}
2274
72046a91
EC		 2275static bool skip_key_basic(struct net_device *filter_dev,
2276 struct flow_cls_offload *f)
2277{
2278 /* When doing mpls over udp decap, the user needs to provide
2279 * MPLS_UC as the protocol in order to be able to match on mpls
2280 * label fields. However, the actual ethertype is IP so we want to
2281 * avoid matching on this, otherwise we'll fail the match.
2282 */
2283 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2284 return true;
2285
2286 return false;
2287}
2288
de0af0bf 2289static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2290 struct mlx5e_tc_flow *flow,
de0af0bf 2291 struct mlx5_flow_spec *spec,
f9e30088 2292 struct flow_cls_offload *f,
54c177ca 2293 struct net_device *filter_dev,
93b3586e 2294 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2295{
e98bedf5 2296 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2297 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2298 outer_headers);
2299 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2300 outer_headers);
699e96dd
JL		 2301 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2302 misc_parameters);
2303 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2304 misc_parameters);
a3222a2d
MD		 2305 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2306 misc_parameters_3);
2307 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2308 misc_parameters_3);
f9e30088 2309 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2310 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2311 enum fs_flow_table_type fs_type;
b6dfff21 2312 bool match_inner_ecn = true;
e3a2b7ed
AV		 2313 u16 addr_type = 0;
2314 u8 ip_proto = 0;
93b3586e 2315 u8 *match_level;
6d65bc64 2316 int err;
e3a2b7ed 2317
afe93f71 2318 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2319 match_level = outer_match_level;
de0af0bf 2320
8f256622 2321 if (dissector->used_keys &
3d144578
VB		 2322 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2323 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2324 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2325 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2326 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2327 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2328 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2329 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2330 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2331 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2332 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2333 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2334 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2335 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2336 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2337 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2338 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2339 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2340 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2341 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2342 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2343 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2344 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2345 dissector->used_keys);
e3a2b7ed
AV		 2346 return -EOPNOTSUPP;
2347 }
2348
075973c7 2349 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2350 bool match_inner = false;
bbd00f7e 2351
0a7fcb78
PB		 2352 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2353 outer_match_level, &match_inner);
2354 if (err)
2355 return err;
2356
2357 if (match_inner) {
2358 /* header pointers should point to the inner headers
2359 * if the packet was decapsulated already.
2360 * outer headers are set by parse_tunnel_attr.
2361 */
2362 match_level = inner_match_level;
2363 headers_c = get_match_inner_headers_criteria(spec);
2364 headers_v = get_match_inner_headers_value(spec);
2365 }
b6dfff21
PB		 2366
2367 err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2368 if (err)
2369 return err;
bbd00f7e
HHZ		 2370 }
2371
6d65bc64 2372 err = mlx5e_flower_parse_meta(filter_dev, f);
2373 if (err)
2374 return err;
2375
72046a91
EC		 2376 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2377 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2378 struct flow_match_basic match;
2379
2380 flow_rule_match_basic(rule, &match);
fca53304
EB		 2381 mlx5e_tc_set_ethertype(priv->mdev, &match,
2382 match_level == outer_match_level,
2383 headers_c, headers_v);
e3a2b7ed 2384
8f256622 2385 if (match.mask->n_proto)
d708f902 2386 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2387 }
35a605db
EB		 2388 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2389 is_vlan_dev(filter_dev)) {
2390 struct flow_dissector_key_vlan filter_dev_mask;
2391 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2392 struct flow_match_vlan match;
2393
35a605db
EB		 2394 if (is_vlan_dev(filter_dev)) {
2395 match.key = &filter_dev_key;
2396 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2397 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2398 match.key->vlan_priority = 0;
2399 match.mask = &filter_dev_mask;
2400 memset(match.mask, 0xff, sizeof(*match.mask));
2401 match.mask->vlan_priority = 0;
2402 } else {
2403 flow_rule_match_vlan(rule, &match);
2404 }
8f256622
PNA		 2405 if (match.mask->vlan_id ||
2406 match.mask->vlan_priority ||
2407 match.mask->vlan_tpid) {
2408 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2409 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2410 svlan_tag, 1);
2411 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2412 svlan_tag, 1);
2413 } else {
2414 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2415 cvlan_tag, 1);
2416 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2417 cvlan_tag, 1);
2418 }
095b6cfd 2419
8f256622
PNA		 2420 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2421 match.mask->vlan_id);
2422 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2423 match.key->vlan_id);
358d79a4 2424
8f256622
PNA		 2425 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2426 match.mask->vlan_priority);
2427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2428 match.key->vlan_priority);
54782900 2429
d708f902 2430 *match_level = MLX5_MATCH_L2;
54782900 2431 }
d3a80bb5 2432 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2433 /* cvlan_tag enabled in match criteria and
2434 * disabled in match value means both S & C tags
2435 * don't exist (untagged of both)
2436 */
cee26487 2437 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2438 *match_level = MLX5_MATCH_L2;
54782900
OG		 2439 }
2440
8f256622
PNA		 2441 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2442 struct flow_match_vlan match;
2443
12d5cbf8 2444 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2445 if (match.mask->vlan_id ||
2446 match.mask->vlan_priority ||
2447 match.mask->vlan_tpid) {
afe93f71
RD		 2448 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2449 fs_type)) {
2450 NL_SET_ERR_MSG_MOD(extack,
2451 "Matching on CVLAN is not supported");
2452 return -EOPNOTSUPP;
2453 }
2454
8f256622 2455 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2456 MLX5_SET(fte_match_set_misc, misc_c,
2457 outer_second_svlan_tag, 1);
2458 MLX5_SET(fte_match_set_misc, misc_v,
2459 outer_second_svlan_tag, 1);
2460 } else {
2461 MLX5_SET(fte_match_set_misc, misc_c,
2462 outer_second_cvlan_tag, 1);
2463 MLX5_SET(fte_match_set_misc, misc_v,
2464 outer_second_cvlan_tag, 1);
2465 }
2466
2467 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2468 match.mask->vlan_id);
699e96dd 2469 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2470 match.key->vlan_id);
699e96dd 2471 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2472 match.mask->vlan_priority);
699e96dd 2473 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2474 match.key->vlan_priority);
699e96dd
JL		 2475
2476 *match_level = MLX5_MATCH_L2;
0faddfe6 2477 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2478 }
2479 }
2480
8f256622
PNA		 2481 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2482 struct flow_match_eth_addrs match;
54782900 2483
8f256622 2484 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2485 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2486 dmac_47_16),
8f256622 2487 match.mask->dst);
d3a80bb5
OG		 2488 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2489 dmac_47_16),
8f256622 2490 match.key->dst);
d3a80bb5
OG		 2491
2492 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2493 smac_47_16),
8f256622 2494 match.mask->src);
d3a80bb5
OG		 2495 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2496 smac_47_16),
8f256622 2497 match.key->src);
d3a80bb5 2498
8f256622
PNA		 2499 if (!is_zero_ether_addr(match.mask->src) ||
2500 !is_zero_ether_addr(match.mask->dst))
d708f902 2501 *match_level = MLX5_MATCH_L2;
54782900
OG		 2502 }
2503
8f256622
PNA		 2504 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2505 struct flow_match_control match;
54782900 2506
8f256622
PNA		 2507 flow_rule_match_control(rule, &match);
2508 addr_type = match.key->addr_type;
54782900
OG		 2509
2510 /* the HW doesn't support frag first/later */
0885ae1a
A		 2511 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2512 NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
54782900 2513 return -EOPNOTSUPP;
0885ae1a 2514 }
54782900 2515
8f256622 2516 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2517 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2519 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2520
2521 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2522 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2523 *match_level = MLX5_MATCH_L2;
54782900
OG		 2524 /* *** L2 attributes parsing up to here *** */
2525 else
83621b7d 2526 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2527 }
2528 }
2529
8f256622
PNA		 2530 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2531 struct flow_match_basic match;
2532
2533 flow_rule_match_basic(rule, &match);
2534 ip_proto = match.key->ip_proto;
54782900
OG		 2535
2536 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2537 match.mask->ip_proto);
54782900 2538 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2539 match.key->ip_proto);
54782900 2540
8f256622 2541 if (match.mask->ip_proto)
d708f902 2542 *match_level = MLX5_MATCH_L3;
54782900
OG		 2543 }
2544
e3a2b7ed 2545 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2546 struct flow_match_ipv4_addrs match;
e3a2b7ed 2547
8f256622 2548 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2549 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2550 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2551 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2552 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2553 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2554 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2555 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2556 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2557 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2558 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2559 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2560 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2561
8f256622 2562 if (match.mask->src || match.mask->dst)
d708f902 2563 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2564 }
2565
2566 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2567 struct flow_match_ipv6_addrs match;
e3a2b7ed 2568
8f256622 2569 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2570 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2571 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2572 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2573 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2574 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2575 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2576
2577 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2578 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2579 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2580 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2581 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2582 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2583
8f256622
PNA		 2584 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2585 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2586 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2587 }
2588
8f256622
PNA		 2589 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2590 struct flow_match_ip match;
1f97a526 2591
8f256622 2592 flow_rule_match_ip(rule, &match);
b6dfff21
PB		 2593 if (match_inner_ecn) {
2594 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2595 match.mask->tos & 0x3);
2596 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2597 match.key->tos & 0x3);
2598 }
1f97a526 2599
8f256622
PNA		 2600 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2601 match.mask->tos >> 2);
2602 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2603 match.key->tos >> 2);
1f97a526 2604
8f256622
PNA		 2605 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2606 match.mask->ttl);
2607 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2608 match.key->ttl);
1f97a526 2609
8f256622 2610 if (match.mask->ttl &&
a8ade55f 2611 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2612 ft_field_support.outer_ipv4_ttl)) {
2613 NL_SET_ERR_MSG_MOD(extack,
2614 "Matching on TTL is not supported");
1f97a526 2615 return -EOPNOTSUPP;
e98bedf5 2616 }
a8ade55f 2617
8f256622 2618 if (match.mask->tos || match.mask->ttl)
d708f902 2619 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2620 }
2621
54782900
OG		 2622 /* *** L3 attributes parsing up to here *** */
2623
8f256622
PNA		 2624 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2625 struct flow_match_ports match;
2626
2627 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2628 switch (ip_proto) {
2629 case IPPROTO_TCP:
2630 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2631 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2632 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2633 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2634
2635 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2636 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2637 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2638 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2639 break;
2640
2641 case IPPROTO_UDP:
2642 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2643 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2644 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2645 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2646
2647 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2648 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2649 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2650 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2651 break;
2652 default:
e98bedf5
EB		 2653 NL_SET_ERR_MSG_MOD(extack,
2654 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2655 netdev_err(priv->netdev,
2656 "Only UDP and TCP transport are supported\n");
2657 return -EINVAL;
2658 }
de0af0bf 2659
8f256622 2660 if (match.mask->src || match.mask->dst)
d708f902 2661 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2662 }
2663
8f256622
PNA		 2664 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2665 struct flow_match_tcp match;
e77834ec 2666
8f256622 2667 flow_rule_match_tcp(rule, &match);
e77834ec 2668 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2669 ntohs(match.mask->flags));
e77834ec 2670 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2671 ntohs(match.key->flags));
e77834ec 2672
8f256622 2673 if (match.mask->flags)
d708f902 2674 *match_level = MLX5_MATCH_L4;
e77834ec 2675 }
a3222a2d
MD		 2676 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2677 struct flow_match_icmp match;
e77834ec 2678
a3222a2d
MD		 2679 flow_rule_match_icmp(rule, &match);
2680 switch (ip_proto) {
2681 case IPPROTO_ICMP:
2682 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2683 MLX5_FLEX_PROTO_ICMP)) {
2684 NL_SET_ERR_MSG_MOD(extack,
2685 "Match on Flex protocols for ICMP is not supported");
a3222a2d 2686 return -EOPNOTSUPP;
0885ae1a 2687 }
a3222a2d
MD		 2688 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2689 match.mask->type);
2690 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2691 match.key->type);
2692 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2693 match.mask->code);
2694 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2695 match.key->code);
2696 break;
2697 case IPPROTO_ICMPV6:
2698 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2699 MLX5_FLEX_PROTO_ICMPV6)) {
2700 NL_SET_ERR_MSG_MOD(extack,
2701 "Match on Flex protocols for ICMPV6 is not supported");
a3222a2d 2702 return -EOPNOTSUPP;
0885ae1a 2703 }
a3222a2d
MD		 2704 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2705 match.mask->type);
2706 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2707 match.key->type);
2708 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2709 match.mask->code);
2710 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2711 match.key->code);
2712 break;
2713 default:
2714 NL_SET_ERR_MSG_MOD(extack,
2715 "Code and type matching only with ICMP and ICMPv6");
2716 netdev_err(priv->netdev,
2717 "Code and type matching only with ICMP and ICMPv6\n");
2718 return -EINVAL;
2719 }
2720 if (match.mask->code || match.mask->type) {
2721 *match_level = MLX5_MATCH_L4;
2722 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2723 }
2724 }
39c538d6 2725 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2726 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2727 !netif_is_bareudp(filter_dev)) {
2728 NL_SET_ERR_MSG_MOD(extack,
2729 "Matching on MPLS is supported only for MPLS over UDP");
2730 netdev_err(priv->netdev,
2731 "Matching on MPLS is supported only for MPLS over UDP\n");
2732 return -EOPNOTSUPP;
2733 }
2734
e3a2b7ed
AV		 2735 return 0;
2736}
2737
de0af0bf 2738static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2739 struct mlx5e_tc_flow *flow,
de0af0bf 2740 struct mlx5_flow_spec *spec,
f9e30088 2741 struct flow_cls_offload *f,
54c177ca 2742 struct net_device *filter_dev)
de0af0bf 2743{
93b3586e 2744 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2745 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2746 struct mlx5_core_dev *dev = priv->mdev;
2747 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2748 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2749 struct mlx5_eswitch_rep *rep;
226f2ca3 2750 bool is_eswitch_flow;
de0af0bf
RD		 2751 int err;
2752
93b3586e
HN		 2753 inner_match_level = MLX5_MATCH_NONE;
2754 outer_match_level = MLX5_MATCH_NONE;
2755
0a7fcb78
PB		 2756 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2757 &inner_match_level, &outer_match_level);
93b3586e
HN		 2758 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2759 outer_match_level : inner_match_level;
de0af0bf 2760
226f2ca3
VB		 2761 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2762 if (!err && is_eswitch_flow) {
1d447a39 2763 rep = rpriv->rep;
b05af6aa 2764 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2765 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2766 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2767 NL_SET_ERR_MSG_MOD(extack,
2768 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2769 netdev_warn(priv->netdev,
2770 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2771 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2772 return -EOPNOTSUPP;
2773 }
2774 }
2775
c620b772
AL		 2776 flow->attr->inner_match_level = inner_match_level;
2777 flow->attr->outer_match_level = outer_match_level;
2778
38aa51c1 2779
de0af0bf
RD		 2780 return err;
2781}
2782
d79b6df6
OG		 2783struct mlx5_fields {
2784 u8 field;
88f30bbc
DL		 2785 u8 field_bsize;
2786 u32 field_mask;
d79b6df6 2787 u32 offset;
27c11b6b 2788 u32 match_offset;
d79b6df6
OG		 2789};
2790
88f30bbc
DL		 2791#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2792 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2793 offsetof(struct pedit_headers, field) + (off), \
2794 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2795
2ef86872
EB		 2796/* masked values are the same and there are no rewrites that do not have a
2797 * match.
2798 */
2799#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2800 type matchmaskx = *(type *)(matchmaskp); \
2801 type matchvalx = *(type *)(matchvalp); \
2802 type maskx = *(type *)(maskp); \
2803 type valx = *(type *)(valp); \
2804 \
2805 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2806 matchmaskx)); \
2807})
2808
27c11b6b 2809static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2810 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2811{
2812 bool same = false;
2813
88f30bbc
DL		 2814 switch (bsize) {
2815 case 8:
2ef86872 2816 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2817 break;
88f30bbc 2818 case 16:
2ef86872 2819 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2820 break;
88f30bbc 2821 case 32:
2ef86872 2822 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2823 break;
2824 }
2825
2826 return same;
2827}
a8e4f0c4 2828
d79b6df6 2829static struct mlx5_fields fields[] = {
88f30bbc
DL		 2830 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2831 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2832 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2833 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2834 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2835 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2836
ab9341b5 2837 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2838 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2839 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2840 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2841
2842 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2843 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2844 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2845 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2846 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2847 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2848 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2849 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2850 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2851 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2852 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2853 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2854 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2855 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2856 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2857 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2858 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2859 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2860
88f30bbc
DL		 2861 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2862 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2863 /* in linux iphdr tcp_flags is 8 bits long */
2864 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2865
88f30bbc
DL		 2866 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2867 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2868};
2869
82198d8b
MD		 2870static unsigned long mask_to_le(unsigned long mask, int size)
2871{
2872 __be32 mask_be32;
2873 __be16 mask_be16;
2874
2875 if (size == 32) {
2876 mask_be32 = (__force __be32)(mask);
2877 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2878 } else if (size == 16) {
2879 mask_be32 = (__force __be32)(mask);
2880 mask_be16 = *(__be16 *)&mask_be32;
2881 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2882 }
2883
2884 return mask;
2885}
09bf9792 2886
6ae4a6a5
PB		 2887static int offload_pedit_fields(struct mlx5e_priv *priv,
2888 int namespace,
e98bedf5 2889 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2890 u32 *action_flags,
e98bedf5 2891 struct netlink_ext_ack *extack)
d79b6df6
OG		 2892{
2893 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
09bf9792 2894 struct pedit_headers_action *hdrs = parse_attr->hdrs;
88f30bbc
DL		 2895 void *headers_c, *headers_v, *action, *vals_p;
2896 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2897 struct mlx5e_tc_mod_hdr_acts *mod_acts;
82198d8b 2898 unsigned long mask, field_mask;
2c0e5cf5
PB		 2899 int i, first, last, next_z;
2900 struct mlx5_fields *f;
88f30bbc
DL		 2901 u8 cmd;
2902
6ae4a6a5 2903 mod_acts = &parse_attr->mod_hdr_acts;
8ee72638
RD		 2904 headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
2905 headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2906
73867881
PNA		 2907 set_masks = &hdrs[0].masks;
2908 add_masks = &hdrs[1].masks;
2909 set_vals = &hdrs[0].vals;
2910 add_vals = &hdrs[1].vals;
d79b6df6 2911
d79b6df6 2912 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2913 bool skip;
2914
d79b6df6
OG		 2915 f = &fields[i];
2916 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2917 s_mask = 0;
2918 a_mask = 0;
d79b6df6
OG		 2919
2920 s_masks_p = (void *)set_masks + f->offset;
2921 a_masks_p = (void *)add_masks + f->offset;
2922
88f30bbc
DL		 2923 s_mask = *s_masks_p & f->field_mask;
2924 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2925
2926 if (!s_mask && !a_mask) /* nothing to offload here */
2927 continue;
2928
2929 if (s_mask && a_mask) {
e98bedf5
EB		 2930 NL_SET_ERR_MSG_MOD(extack,
2931 "can't set and add to the same HW field");
61b6a6c3
CH		 2932 netdev_warn(priv->netdev,
2933 "mlx5: can't set and add to the same HW field (%x)\n",
2934 f->field);
d79b6df6
OG		 2935 return -EOPNOTSUPP;
2936 }
2937
27c11b6b 2938 skip = false;
d79b6df6 2939 if (s_mask) {
27c11b6b
EB		 2940 void *match_mask = headers_c + f->match_offset;
2941 void *match_val = headers_v + f->match_offset;
2942
d79b6df6
OG		 2943 cmd = MLX5_ACTION_TYPE_SET;
2944 mask = s_mask;
2945 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2946 /* don't rewrite if we have a match on the same value */
2947 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2948 match_mask, f->field_bsize))
27c11b6b 2949 skip = true;
d79b6df6 2950 /* clear to denote we consumed this field */
88f30bbc 2951 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2952 } else {
2953 cmd = MLX5_ACTION_TYPE_ADD;
2954 mask = a_mask;
2955 vals_p = (void *)add_vals + f->offset;
27c11b6b 2956 /* add 0 is no change */
88f30bbc 2957 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2958 skip = true;
d79b6df6 2959 /* clear to denote we consumed this field */
88f30bbc 2960 *a_masks_p &= ~f->field_mask;
d79b6df6 2961 }
27c11b6b
EB		 2962 if (skip)
2963 continue;
d79b6df6 2964
82198d8b 2965 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2966
88f30bbc
DL		 2967 first = find_first_bit(&mask, f->field_bsize);
2968 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2969 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2970 if (first < next_z && next_z < last) {
e98bedf5
EB		 2971 NL_SET_ERR_MSG_MOD(extack,
2972 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2973 netdev_warn(priv->netdev,
2974 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2975 mask);
d79b6df6
OG		 2976 return -EOPNOTSUPP;
2977 }
2978
2c0e5cf5
PB		 2979 action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
2980 if (IS_ERR(action)) {
6ae4a6a5
PB		 2981 NL_SET_ERR_MSG_MOD(extack,
2982 "too many pedit actions, can't offload");
2983 mlx5_core_warn(priv->mdev,
2984 "mlx5: parsed %d pedit actions, can't do more\n",
2985 mod_acts->num_actions);
2c0e5cf5 2986 return PTR_ERR(action);
6ae4a6a5
PB		 2987 }
2988
d79b6df6
OG		 2989 MLX5_SET(set_action_in, action, action_type, cmd);
2990 MLX5_SET(set_action_in, action, field, f->field);
2991
2992 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2993 int start;
2994
82198d8b
MD		 2995 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2996
88f30bbc 2997 /* if field is bit sized it can start not from first bit */
82198d8b 2998 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2999
3000 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 3001 /* length is num of bits to be written, zero means length of 32 */
2b64beba 3002 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 3003 }
3004
88f30bbc 3005 if (f->field_bsize == 32)
2b64beba 3006 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 3007 else if (f->field_bsize == 16)
2b64beba 3008 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 3009 else if (f->field_bsize == 8)
2b64beba 3010 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 3011
6ae4a6a5 3012 ++mod_acts->num_actions;
d79b6df6
OG		 3013 }
3014
d79b6df6
OG		 3015 return 0;
3016}
3017
d79b6df6
OG		 3018static const struct pedit_headers zero_masks = {};
3019
918ed7bf
RD		 3020static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3021 struct mlx5e_tc_flow_parse_attr *parse_attr,
3022 struct netlink_ext_ack *extack)
c500c86b
PNA		 3023{
3024 struct pedit_headers *cmd_masks;
c500c86b
PNA		 3025 u8 cmd;
3026
d79b6df6 3027 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
09bf9792 3028 cmd_masks = &parse_attr->hdrs[cmd].masks;
d79b6df6 3029 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
09bf9792 3030 NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
b3a433de 3031 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 3032 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3033 16, 1, cmd_masks, sizeof(zero_masks), true);
918ed7bf 3034 return -EOPNOTSUPP;
d79b6df6
OG		 3035 }
3036 }
3037
3038 return 0;
918ed7bf
RD		 3039}
3040
3041static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3042 struct mlx5e_tc_flow_parse_attr *parse_attr,
3043 u32 *action_flags,
3044 struct netlink_ext_ack *extack)
3045{
3046 int err;
3047
3048 err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3049 if (err)
3050 goto out_dealloc_parsed_actions;
3051
3052 err = verify_offload_pedit_fields(priv, parse_attr, extack);
3053 if (err)
3054 goto out_dealloc_parsed_actions;
3055
3056 return 0;
d79b6df6
OG		 3057
3058out_dealloc_parsed_actions:
2c0e5cf5 3059 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 3060 return err;
3061}
3062
8998576b
DL		 3063struct ip_ttl_word {
3064 __u8 ttl;
3065 __u8 protocol;
3066 __sum16 check;
3067};
3068
3069struct ipv6_hoplimit_word {
3070 __be16 payload_len;
3071 __u8 nexthdr;
3072 __u8 hop_limit;
3073};
3074
1836d780
RD		 3075static bool
3076is_action_keys_supported(const struct flow_action_entry *act, bool ct_flow,
3077 bool *modify_ip_header, bool *modify_tuple,
3078 struct netlink_ext_ack *extack)
8998576b
DL		 3079{
3080 u32 mask, offset;
3081 u8 htype;
3082
3083 htype = act->mangle.htype;
3084 offset = act->mangle.offset;
3085 mask = ~act->mangle.mask;
3086 /* For IPv4 & IPv6 header check 4 byte word,
3087 * to determine that modified fields
3088 * are NOT ttl & hop_limit only.
3089 */
3090 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3091 struct ip_ttl_word *ttl_word =
3092 (struct ip_ttl_word *)&mask;
3093
3094 if (offset != offsetof(struct iphdr, ttl) ||
3095 ttl_word->protocol ||
3096 ttl_word->check) {
4c3844d9
PB		 3097 *modify_ip_header = true;
3098 }
3099
7e36feeb
PB		 3100 if (offset >= offsetof(struct iphdr, saddr))
3101 *modify_tuple = true;
3102
3103 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3104 NL_SET_ERR_MSG_MOD(extack,
3105 "can't offload re-write of ipv4 address with action ct");
1836d780 3106 return false;
8998576b
DL		 3107 }
3108 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3109 struct ipv6_hoplimit_word *hoplimit_word =
3110 (struct ipv6_hoplimit_word *)&mask;
3111
3112 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3113 hoplimit_word->payload_len ||
3114 hoplimit_word->nexthdr) {
4c3844d9
PB		 3115 *modify_ip_header = true;
3116 }
3117
7e36feeb
PB		 3118 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3119 *modify_tuple = true;
3120
3121 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3122 NL_SET_ERR_MSG_MOD(extack,
3123 "can't offload re-write of ipv6 address with action ct");
1836d780 3124 return false;
8998576b 3125 }
7e36feeb
PB		 3126 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3127 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3128 *modify_tuple = true;
3129 if (ct_flow) {
3130 NL_SET_ERR_MSG_MOD(extack,
3131 "can't offload re-write of transport header ports with action ct");
1836d780 3132 return false;
7e36feeb 3133 }
8998576b 3134 }
4c3844d9 3135
1836d780 3136 return true;
8998576b
DL		 3137}
3138
96b5b458
DC		 3139static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3140 bool ct_flow, struct netlink_ext_ack *extack,
3141 struct mlx5e_priv *priv,
3142 struct mlx5_flow_spec *spec)
3143{
3144 if (!modify_tuple || ct_clear)
3145 return true;
3146
3147 if (ct_flow) {
3148 NL_SET_ERR_MSG_MOD(extack,
3149 "can't offload tuple modification with non-clear ct()");
3150 netdev_info(priv->netdev,
3151 "can't offload tuple modification with non-clear ct()");
3152 return false;
3153 }
3154
3155 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3156 * (or after clear action), as otherwise, since the tuple is changed,
3157 * we can't restore ct state
3158 */
3159 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3160 NL_SET_ERR_MSG_MOD(extack,
3161 "can't offload tuple modification with ct matches and no ct(clear) action");
3162 netdev_info(priv->netdev,
3163 "can't offload tuple modification with ct matches and no ct(clear) action");
3164 return false;
3165 }
3166
3167 return true;
3168}
3169
3d486ec4
OS		 3170static bool modify_header_match_supported(struct mlx5e_priv *priv,
3171 struct mlx5_flow_spec *spec,
73867881 3172 struct flow_action *flow_action,
4c3844d9 3173 u32 actions, bool ct_flow,
7e36feeb 3174 bool ct_clear,
e98bedf5 3175 struct netlink_ext_ack *extack)
bdd66ac0 3176{
73867881 3177 const struct flow_action_entry *act;
7e36feeb 3178 bool modify_ip_header, modify_tuple;
fca53304 3179 void *headers_c;
bdd66ac0
OG		 3180 void *headers_v;
3181 u16 ethertype;
8998576b 3182 u8 ip_proto;
1836d780 3183 int i;
bdd66ac0 3184
8ee72638
RD		 3185 headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3186 headers_v = mlx5e_get_match_headers_value(actions, spec);
bdd66ac0
OG		 3187 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3188
3189 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3190 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3191 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3192 goto out_ok;
3193
3194 modify_ip_header = false;
7e36feeb 3195 modify_tuple = false;
73867881
PNA		 3196 flow_action_for_each(i, act, flow_action) {
3197 if (act->id != FLOW_ACTION_MANGLE &&
3198 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3199 continue;
3200
1836d780
RD		 3201 if (!is_action_keys_supported(act, ct_flow,
3202 &modify_ip_header,
3203 &modify_tuple, extack))
3204 return false;
bdd66ac0
OG		 3205 }
3206
96b5b458
DC		 3207 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3208 priv, spec))
7e36feeb 3209 return false;
7e36feeb 3210
bdd66ac0 3211 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3212 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3213 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3214 NL_SET_ERR_MSG_MOD(extack,
3215 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3216 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3217 ip_proto);
bdd66ac0
OG		 3218 return false;
3219 }
3220
3221out_ok:
3222 return true;
3223}
3224
9c1d3511
RD		 3225static bool
3226actions_match_supported_fdb(struct mlx5e_priv *priv,
3227 struct mlx5e_tc_flow_parse_attr *parse_attr,
3228 struct mlx5e_tc_flow *flow,
3229 struct netlink_ext_ack *extack)
bdd66ac0 3230{
d4f401d9 3231 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
9c1d3511 3232 bool ct_flow, ct_clear;
bdd66ac0 3233
9c1d3511
RD		 3234 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3235 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3236
d4f401d9
RD		 3237 if (esw_attr->split_count && ct_flow &&
3238 !MLX5_CAP_GEN(esw_attr->in_mdev, reg_c_preserve)) {
9c1d3511
RD		 3239 /* All registers used by ct are cleared when using
3240 * split rules.
3241 */
3242 NL_SET_ERR_MSG_MOD(extack, "Can't offload mirroring with action ct");
3243 return false;
3244 }
3245
d4f401d9
RD		 3246 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3247 NL_SET_ERR_MSG_MOD(extack,
3248 "current firmware doesn't support split rule for port mirroring");
3249 netdev_warn_once(priv->netdev,
3250 "current firmware doesn't support split rule for port mirroring\n");
3251 return false;
3252 }
3253
9c1d3511
RD		 3254 return true;
3255}
3256
3257static bool
3258actions_match_supported(struct mlx5e_priv *priv,
3259 struct flow_action *flow_action,
0610f8dc 3260 u32 actions,
9c1d3511
RD		 3261 struct mlx5e_tc_flow_parse_attr *parse_attr,
3262 struct mlx5e_tc_flow *flow,
3263 struct netlink_ext_ack *extack)
3264{
9c1d3511
RD		 3265 bool ct_flow, ct_clear;
3266
3267 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
c620b772 3268 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
c620b772 3269
6b50cf45
RD		 3270 if (!(actions &
3271 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3272 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
3273 return false;
3274 }
3275
5623ef8a
RD		 3276 if (!(~actions &
3277 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3278 NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
3279 return false;
3280 }
3281
a2446bc7
RD		 3282 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3283 actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3284 NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
3285 return false;
3286 }
3287
9c1d3511
RD		 3288 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3289 !modify_header_match_supported(priv, &parse_attr->spec, flow_action,
3290 actions, ct_flow, ct_clear, extack))
3291 return false;
bdd66ac0 3292
9c1d3511
RD		 3293 if (mlx5e_is_eswitch_flow(flow) &&
3294 !actions_match_supported_fdb(priv, parse_attr, flow, extack))
3295 return false;
bdd66ac0
OG		 3296
3297 return true;
3298}
3299
32134847
MD		 3300static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3301{
3302 return priv->mdev == peer_priv->mdev;
3303}
3304
ab3f3d5e 3305bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
5c65c564
OG		 3306{
3307 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3308 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3309
3310 fmdev = priv->mdev;
3311 pmdev = peer_priv->mdev;
3312
59c9d35e
AH		 3313 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3314 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3315
816f6706 3316 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3317}
3318
8333d53e
RD		 3319static int
3320parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
3321 struct flow_action *flow_action)
3322{
3323 struct netlink_ext_ack *extack = parse_state->extack;
3324 struct mlx5e_tc_flow *flow = parse_state->flow;
3325 struct mlx5_flow_attr *attr = flow->attr;
3326 enum mlx5_flow_namespace_type ns_type;
3327 struct mlx5e_priv *priv = flow->priv;
3328 const struct flow_action_entry *act;
3329 struct mlx5e_tc_act *tc_act;
3330 int err, i;
3331
3332 ns_type = mlx5e_get_flow_namespace(flow);
3333
3334 flow_action_for_each(i, act, flow_action) {
3335 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3336 if (!tc_act) {
3337 NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
3338 return -EOPNOTSUPP;
3339 }
3340
8be9686d 3341 if (!tc_act->can_offload(parse_state, act, i, attr))
8333d53e
RD		 3342 return -EOPNOTSUPP;
3343
3344 err = tc_act->parse_action(parse_state, act, priv, attr);
3345 if (err)
3346 return err;
0610f8dc
RD		 3347
3348 parse_state->actions |= attr->action;
8333d53e
RD		 3349 }
3350
dd5ab6d1
RD		 3351 flow_action_for_each(i, act, flow_action) {
3352 tc_act = mlx5e_tc_act_get(act->id, ns_type);
3353 if (!tc_act || !tc_act->post_parse ||
8be9686d 3354 !tc_act->can_offload(parse_state, act, i, attr))
dd5ab6d1
RD		 3355 continue;
3356
3357 err = tc_act->post_parse(parse_state, priv, attr);
3358 if (err)
3359 return err;
3360 }
3361
8333d53e
RD		 3362 return 0;
3363}
3364
d9581e2f
RD		 3365static int
3366actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
e98bedf5 3367 struct mlx5e_tc_flow *flow,
d9581e2f 3368 struct mlx5_flow_attr *attr,
e98bedf5 3369 struct netlink_ext_ack *extack)
d9581e2f
RD		 3370{
3371 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
09bf9792 3372 struct pedit_headers_action *hdrs = parse_attr->hdrs;
d9581e2f
RD		 3373 enum mlx5_flow_namespace_type ns_type;
3374 int err;
3375
3376 if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3377 !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3378 return 0;
3379
e36db1ee 3380 ns_type = mlx5e_get_flow_namespace(flow);
d9581e2f 3381
09bf9792 3382 err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
d9581e2f
RD		 3383 if (err)
3384 return err;
3385
d9581e2f
RD		 3386 if (parse_attr->mod_hdr_acts.num_actions > 0)
3387 return 0;
3388
fc3a879a 3389 /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
d9581e2f 3390 attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2c0e5cf5 3391 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
d9581e2f
RD		 3392
3393 if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3394 return 0;
3395
3396 if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3397 (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3398 attr->esw_attr->split_count = 0;
3399
3400 return 0;
3401}
3402
df990477
RD		 3403static int
3404flow_action_supported(struct flow_action *flow_action,
3405 struct netlink_ext_ack *extack)
3406{
3407 if (!flow_action_has_entries(flow_action)) {
3408 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
3409 return -EINVAL;
3410 }
3411
3412 if (!flow_action_hw_stats_check(flow_action, extack,
3413 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3414 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
3415 return -EOPNOTSUPP;
3416 }
3417
3418 return 0;
3419}
3420
d9581e2f
RD		 3421static int
3422parse_tc_nic_actions(struct mlx5e_priv *priv,
3423 struct flow_action *flow_action,
3424 struct mlx5e_tc_flow *flow,
3425 struct netlink_ext_ack *extack)
e3a2b7ed 3426{
fad54790 3427 struct mlx5e_tc_act_parse_state *parse_state;
c6cfe113 3428 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3429 struct mlx5_flow_attr *attr = flow->attr;
8333d53e 3430 int err;
e3a2b7ed 3431
df990477
RD		 3432 err = flow_action_supported(flow_action, extack);
3433 if (err)
3434 return err;
319a1d19 3435
fad54790 3436 attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3437 parse_attr = attr->parse_attr;
fad54790
RD		 3438 parse_state = &parse_attr->parse_state;
3439 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3440 parse_state->ct_priv = get_ct_priv(priv);
e3a2b7ed 3441
8333d53e
RD		 3442 err = parse_tc_actions(parse_state, flow_action);
3443 if (err)
3444 return err;
e3a2b7ed 3445
09bf9792 3446 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
d9581e2f
RD		 3447 if (err)
3448 return err;
3449
0610f8dc
RD		 3450 if (!actions_match_supported(priv, flow_action, parse_state->actions,
3451 parse_attr, flow, extack))
bdd66ac0
OG		 3452 return -EOPNOTSUPP;
3453
e3a2b7ed
AV		 3454 return 0;
3455}
3456
32134847 3457static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3458 struct net_device *peer_netdev)
3459{
3460 struct mlx5e_priv *peer_priv;
3461
3462 peer_priv = netdev_priv(peer_netdev);
3463
3464 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3465 mlx5e_eswitch_vf_rep(priv->netdev) &&
3466 mlx5e_eswitch_vf_rep(peer_netdev) &&
ab3f3d5e 3467 mlx5e_same_hw_devs(priv, peer_priv));
d34eb2fc
OG		 3468}
3469
32134847
MD		 3470static bool same_hw_reps(struct mlx5e_priv *priv,
3471 struct net_device *peer_netdev)
3472{
3473 struct mlx5e_priv *peer_priv;
3474
3475 peer_priv = netdev_priv(peer_netdev);
3476
3477 return mlx5e_eswitch_rep(priv->netdev) &&
3478 mlx5e_eswitch_rep(peer_netdev) &&
ab3f3d5e 3479 mlx5e_same_hw_devs(priv, peer_priv);
32134847
MD		 3480}
3481
3482static bool is_lag_dev(struct mlx5e_priv *priv,
3483 struct net_device *peer_netdev)
3484{
3485 return ((mlx5_lag_is_sriov(priv->mdev) ||
3486 mlx5_lag_is_multipath(priv->mdev)) &&
3487 same_hw_reps(priv, peer_netdev));
3488}
3489
f6dc1264
PB		 3490bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3491 struct net_device *out_dev)
3492{
32134847
MD		 3493 if (is_merged_eswitch_vfs(priv, out_dev))
3494 return true;
3495
3496 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3497 return true;
3498
3499 return mlx5e_eswitch_rep(out_dev) &&
32134847 3500 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3501}
3502
27484f71
AL		 3503int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
3504 struct mlx5_flow_attr *attr,
3505 int ifindex,
3506 enum mlx5e_tc_int_port_type type,
3507 u32 *action,
3508 int out_index)
3509{
3510 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
3511 struct mlx5e_tc_int_port_priv *int_port_priv;
3512 struct mlx5e_tc_flow_parse_attr *parse_attr;
3513 struct mlx5e_tc_int_port *dest_int_port;
3514 int err;
3515
3516 parse_attr = attr->parse_attr;
3517 int_port_priv = mlx5e_get_int_port_priv(priv);
3518
3519 dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
3520 if (IS_ERR(dest_int_port))
3521 return PTR_ERR(dest_int_port);
3522
3523 err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
3524 MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
3525 mlx5e_tc_int_port_get_metadata(dest_int_port));
3526 if (err) {
3527 mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
3528 return err;
3529 }
3530
3531 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3532
3533 esw_attr->dest_int_port = dest_int_port;
3534 esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
3535
3536 /* Forward to root fdb for matching against the new source vport */
3537 attr->dest_chain = 0;
3538
3539 return 0;
3540}
3541
8333d53e
RD		 3542static int
3543parse_tc_fdb_actions(struct mlx5e_priv *priv,
3544 struct flow_action *flow_action,
3545 struct mlx5e_tc_flow *flow,
3546 struct netlink_ext_ack *extack)
03a9d11e 3547{
fad54790 3548 struct mlx5e_tc_act_parse_state *parse_state;
c620b772 3549 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3550 struct mlx5_flow_attr *attr = flow->attr;
c620b772 3551 struct mlx5_esw_flow_attr *esw_attr;
8333d53e 3552 int err;
03a9d11e 3553
df990477
RD		 3554 err = flow_action_supported(flow_action, extack);
3555 if (err)
3556 return err;
319a1d19 3557
c620b772
AL		 3558 esw_attr = attr->esw_attr;
3559 parse_attr = attr->parse_attr;
fad54790
RD		 3560 parse_state = &parse_attr->parse_state;
3561 mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
758bc134 3562 parse_state->ct_priv = get_ct_priv(priv);
c620b772 3563
8333d53e
RD		 3564 err = parse_tc_actions(parse_state, flow_action);
3565 if (err)
3566 return err;
bdd66ac0 3567
166f431e
AL		 3568 /* Forward to/from internal port can only have 1 dest */
3569 if ((netif_is_ovs_master(parse_attr->filter_dev) || esw_attr->dest_int_port) &&
3570 esw_attr->out_count > 1) {
27484f71 3571 NL_SET_ERR_MSG_MOD(extack,
166f431e 3572 "Rules with internal port can have only one destination");
27484f71
AL		 3573 return -EOPNOTSUPP;
3574 }
3575
09bf9792 3576 err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
d9581e2f
RD		 3577 if (err)
3578 return err;
3579
0610f8dc
RD		 3580 if (!actions_match_supported(priv, flow_action, parse_state->actions,
3581 parse_attr, flow, extack))
bdd66ac0
OG		 3582 return -EOPNOTSUPP;
3583
31c8eba5 3584 return 0;
03a9d11e
OG		 3585}
3586
226f2ca3 3587static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 3588{
226f2ca3 3589 unsigned long __flow_flags = 0;
60bd4af8 3590
226f2ca3
VB		 3591 if (flags & MLX5_TC_FLAG(INGRESS))
3592 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
3593 if (flags & MLX5_TC_FLAG(EGRESS))
3594 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 3595
226f2ca3
VB		 3596 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
3597 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
3598 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
3599 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 3600 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
3601 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 3602
60bd4af8
OG		 3603 *flow_flags = __flow_flags;
3604}
3605
05866c82
OG		 3606static const struct rhashtable_params tc_ht_params = {
3607 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3608 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3609 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3610 .automatic_shrinking = true,
3611};
3612
226f2ca3
VB		 3613static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
3614 unsigned long flags)
05866c82 3615{
d1a3138f 3616 struct mlx5e_rep_priv *rpriv;
655dc3d2 3617
226f2ca3 3618 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
d1a3138f
PB		 3619 rpriv = priv->ppriv;
3620 return &rpriv->tc_ht;
d9ee0491 3621 } else /* NIC offload */
655dc3d2 3622 return &priv->fs.tc.ht;
05866c82
OG		 3623}
3624
04de7dda
RD		 3625static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
3626{
c620b772
AL		 3627 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3628 struct mlx5_flow_attr *attr = flow->attr;
3629 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 3630 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 3631 bool act_is_encap = !!(attr->action &
3632 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 3633 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 3634 MLX5_DEVCOM_ESW_OFFLOADS);
3635
10fbb1cd
RD		 3636 if (!esw_paired)
3637 return false;
3638
c620b772
AL		 3639 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
3640 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 3641 (is_rep_ingress || act_is_encap))
3642 return true;
3643
3644 return false;
04de7dda
RD		 3645}
3646
c620b772
AL		 3647struct mlx5_flow_attr *
3648mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
3649{
3650 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
3651 sizeof(struct mlx5_esw_flow_attr) :
3652 sizeof(struct mlx5_nic_flow_attr);
3653 struct mlx5_flow_attr *attr;
3654
3655 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
3656}
3657
a88780a9
RD		 3658static int
3659mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 3660 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 3661 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3662 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3663{
17091853 3664 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3665 struct mlx5_flow_attr *attr;
3bc4b7bf 3666 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 3667 int err = -ENOMEM;
3668 int out_index;
e3a2b7ed 3669
c620b772 3670 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 3671 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 3672 if (!parse_attr || !flow)
3673 goto err_free;
c620b772
AL		 3674
3675 flow->flags = flow_flags;
3676 flow->cookie = f->cookie;
3677 flow->priv = priv;
3678
e36db1ee 3679 attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
ff7ea04a 3680 if (!attr)
e3a2b7ed 3681 goto err_free;
ff7ea04a 3682
c620b772 3683 flow->attr = attr;
e3a2b7ed 3684
5a7e5bcb
VB		 3685 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
3686 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 3687 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 3688 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 3689 refcount_set(&flow->refcnt, 1);
95435ad7 3690 init_completion(&flow->init_done);
362980ea 3691 init_completion(&flow->del_hw_done);
e3a2b7ed 3692
a88780a9
RD		 3693 *__flow = flow;
3694 *__parse_attr = parse_attr;
3695
3696 return 0;
3697
3698err_free:
3699 kfree(flow);
3700 kvfree(parse_attr);
3701 return err;
3702}
3703
c7569097
AL		 3704static void
3705mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
3706 struct mlx5e_tc_flow_parse_attr *parse_attr,
3707 struct flow_cls_offload *f)
3708{
3709 attr->parse_attr = parse_attr;
3710 attr->chain = f->common.chain_index;
3711 attr->prio = f->common.prio;
3712}
3713
988ab9c7 3714static void
c620b772 3715mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 3716 struct mlx5e_priv *priv,
3717 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 3718 struct flow_cls_offload *f,
988ab9c7
TZ		 3719 struct mlx5_eswitch_rep *in_rep,
3720 struct mlx5_core_dev *in_mdev)
3721{
3722 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3723 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 3724
c7569097 3725 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 3726
3727 esw_attr->in_rep = in_rep;
3728 esw_attr->in_mdev = in_mdev;
3729
3730 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
3731 MLX5_COUNTER_SOURCE_ESWITCH)
3732 esw_attr->counter_dev = in_mdev;
3733 else
3734 esw_attr->counter_dev = priv->mdev;
3735}
3736
71129676 3737static struct mlx5e_tc_flow *
04de7dda 3738__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3739 struct flow_cls_offload *f,
226f2ca3 3740 unsigned long flow_flags,
04de7dda
RD		 3741 struct net_device *filter_dev,
3742 struct mlx5_eswitch_rep *in_rep,
71129676 3743 struct mlx5_core_dev *in_mdev)
a88780a9 3744{
f9e30088 3745 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3746 struct netlink_ext_ack *extack = f->common.extack;
3747 struct mlx5e_tc_flow_parse_attr *parse_attr;
3748 struct mlx5e_tc_flow *flow;
3749 int attr_size, err;
e3a2b7ed 3750
226f2ca3 3751 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 3752 attr_size = sizeof(struct mlx5_esw_flow_attr);
3753 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3754 &parse_attr, &flow);
3755 if (err)
3756 goto out;
988ab9c7 3757
d11afc26 3758 parse_attr->filter_dev = filter_dev;
c620b772 3759 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 3760 priv, parse_attr,
3761 f, in_rep, in_mdev);
3762
54c177ca
OS		 3763 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3764 f, filter_dev);
d11afc26
OS		 3765 if (err)
3766 goto err_free;
a88780a9 3767
7e36feeb 3768 /* actions validation depends on parsing the ct matches first */
aedd133d 3769 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 3770 &flow->attr->ct_attr, extack);
a88780a9
RD		 3771 if (err)
3772 goto err_free;
3773
d4bb0531
RD		 3774 /* always set IP version for indirect table handling */
3775 flow->attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
3776
70f8019e 3777 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 3778 if (err)
3779 goto err_free;
3780
7040632d 3781 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 3782 complete_all(&flow->init_done);
ef06c9ee
RD		 3783 if (err) {
3784 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
3785 goto err_free;
3786
b4a23329 3787 add_unready_flow(flow);
ef06c9ee 3788 }
e3a2b7ed 3789
71129676 3790 return flow;
a88780a9
RD		 3791
3792err_free:
5a7e5bcb 3793 mlx5e_flow_put(priv, flow);
a88780a9 3794out:
71129676 3795 return ERR_PTR(err);
a88780a9
RD		 3796}
3797
f9e30088 3798static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 3799 struct mlx5e_tc_flow *flow,
226f2ca3 3800 unsigned long flow_flags)
04de7dda
RD		 3801{
3802 struct mlx5e_priv *priv = flow->priv, *peer_priv;
3803 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 3804 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 3805 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
3806 struct mlx5e_tc_flow_parse_attr *parse_attr;
3807 struct mlx5e_rep_priv *peer_urpriv;
3808 struct mlx5e_tc_flow *peer_flow;
3809 struct mlx5_core_dev *in_mdev;
3810 int err = 0;
3811
3812 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3813 if (!peer_esw)
3814 return -ENODEV;
3815
3816 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
3817 peer_priv = netdev_priv(peer_urpriv->netdev);
3818
3819 /* in_mdev is assigned of which the packet originated from.
3820 * So packets redirected to uplink use the same mdev of the
3821 * original flow and packets redirected from uplink use the
3822 * peer mdev.
3823 */
c620b772 3824 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 3825 in_mdev = peer_priv->mdev;
3826 else
3827 in_mdev = priv->mdev;
3828
c620b772 3829 parse_attr = flow->attr->parse_attr;
95dc1902 3830 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 3831 parse_attr->filter_dev,
c620b772 3832 attr->in_rep, in_mdev);
71129676
JG		 3833 if (IS_ERR(peer_flow)) {
3834 err = PTR_ERR(peer_flow);
04de7dda 3835 goto out;
71129676 3836 }
04de7dda
RD		 3837
3838 flow->peer_flow = peer_flow;
226f2ca3 3839 flow_flag_set(flow, DUP);
04de7dda
RD		 3840 mutex_lock(&esw->offloads.peer_mutex);
3841 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
3842 mutex_unlock(&esw->offloads.peer_mutex);
3843
3844out:
3845 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3846 return err;
3847}
3848
3849static int
3850mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 3851 struct flow_cls_offload *f,
226f2ca3 3852 unsigned long flow_flags,
04de7dda
RD		 3853 struct net_device *filter_dev,
3854 struct mlx5e_tc_flow **__flow)
3855{
3856 struct mlx5e_rep_priv *rpriv = priv->ppriv;
3857 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
3858 struct mlx5_core_dev *in_mdev = priv->mdev;
3859 struct mlx5e_tc_flow *flow;
3860 int err;
3861
71129676
JG		 3862 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
3863 in_mdev);
3864 if (IS_ERR(flow))
3865 return PTR_ERR(flow);
04de7dda
RD		 3866
3867 if (is_peer_flow_needed(flow)) {
95dc1902 3868 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 3869 if (err) {
3870 mlx5e_tc_del_fdb_flow(priv, flow);
3871 goto out;
3872 }
3873 }
3874
3875 *__flow = flow;
3876
3877 return 0;
3878
3879out:
3880 return err;
3881}
3882
a88780a9
RD		 3883static int
3884mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 3885 struct flow_cls_offload *f,
226f2ca3 3886 unsigned long flow_flags,
d11afc26 3887 struct net_device *filter_dev,
a88780a9
RD		 3888 struct mlx5e_tc_flow **__flow)
3889{
f9e30088 3890 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 3891 struct netlink_ext_ack *extack = f->common.extack;
3892 struct mlx5e_tc_flow_parse_attr *parse_attr;
3893 struct mlx5e_tc_flow *flow;
3894 int attr_size, err;
3895
c7569097
AL		 3896 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
3897 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3898 return -EOPNOTSUPP;
3899 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 3900 return -EOPNOTSUPP;
c7569097 3901 }
bf07aa73 3902
226f2ca3 3903 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 3904 attr_size = sizeof(struct mlx5_nic_flow_attr);
3905 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3906 &parse_attr, &flow);
3907 if (err)
3908 goto out;
3909
d11afc26 3910 parse_attr->filter_dev = filter_dev;
c7569097
AL		 3911 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
3912
54c177ca
OS		 3913 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
3914 f, filter_dev);
d11afc26
OS		 3915 if (err)
3916 goto err_free;
3917
aedd133d
AL		 3918 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
3919 &flow->attr->ct_attr, extack);
3920 if (err)
3921 goto err_free;
3922
c6cfe113 3923 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 3924 if (err)
3925 goto err_free;
3926
c6cfe113 3927 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 3928 if (err)
3929 goto err_free;
3930
226f2ca3 3931 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 3932 *__flow = flow;
3933
3934 return 0;
e3a2b7ed 3935
e3a2b7ed 3936err_free:
8914add2 3937 flow_flag_set(flow, FAILED);
2c0e5cf5 3938 mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
5a7e5bcb 3939 mlx5e_flow_put(priv, flow);
a88780a9
RD		 3940out:
3941 return err;
3942}
3943
3944static int
3945mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 3946 struct flow_cls_offload *f,
226f2ca3 3947 unsigned long flags,
d11afc26 3948 struct net_device *filter_dev,
a88780a9
RD		 3949 struct mlx5e_tc_flow **flow)
3950{
3951 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 3952 unsigned long flow_flags;
a88780a9
RD		 3953 int err;
3954
3955 get_flags(flags, &flow_flags);
3956
bf07aa73
PB		 3957 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3958 return -EOPNOTSUPP;
3959
f6455de0 3960 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 3961 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
3962 filter_dev, flow);
a88780a9 3963 else
d11afc26
OS		 3964 err = mlx5e_add_nic_flow(priv, f, flow_flags,
3965 filter_dev, flow);
a88780a9
RD		 3966
3967 return err;
3968}
3969
553f9328
VP		 3970static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
3971 struct mlx5e_rep_priv *rpriv)
3972{
3973 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 3974 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
3975 * function is called from NIC mode.
553f9328 3976 */
2fb15e72 3977 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 3978}
3979
71d82d2a 3980int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 3981 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 3982{
3983 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 3984 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 3985 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 3986 struct mlx5e_tc_flow *flow;
3987 int err = 0;
3988
7dc84de9
RD		 3989 if (!mlx5_esw_hold(priv->mdev))
3990 return -EAGAIN;
3991
3992 mlx5_esw_get(priv->mdev);
3993
c5d326b2
VB		 3994 rcu_read_lock();
3995 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 3996 if (flow) {
553f9328
VP		 3997 /* Same flow rule offloaded to non-uplink representor sharing tc block,
3998 * just return 0.
3999 */
4000 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4001 goto rcu_unlock;
553f9328 4002
a88780a9
RD		 4003 NL_SET_ERR_MSG_MOD(extack,
4004 "flow cookie already exists, ignoring");
4005 netdev_warn_once(priv->netdev,
4006 "flow cookie %lx already exists, ignoring\n",
4007 f->cookie);
0e1c1a2f 4008 err = -EEXIST;
c1aea9e1 4009 goto rcu_unlock;
a88780a9 4010 }
c1aea9e1
VB		 4011rcu_unlock:
4012 rcu_read_unlock();
4013 if (flow)
4014 goto out;
a88780a9 4015
7a978759 4016 trace_mlx5e_configure_flower(f);
d11afc26 4017 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4018 if (err)
4019 goto out;
4020
553f9328
VP		 4021 /* Flow rule offloaded to non-uplink representor sharing tc block,
4022 * set the flow's owner dev.
4023 */
4024 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4025 flow->orig_dev = dev;
4026
c5d326b2 4027 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4028 if (err)
4029 goto err_free;
4030
7dc84de9 4031 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4032 return 0;
4033
4034err_free:
5a7e5bcb 4035 mlx5e_flow_put(priv, flow);
a88780a9 4036out:
7dc84de9
RD		 4037 mlx5_esw_put(priv->mdev);
4038 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4039 return err;
4040}
4041
8f8ae895
OG		 4042static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4043{
226f2ca3
VB		 4044 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4045 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4046
226f2ca3
VB		 4047 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4048 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4049}
4050
71d82d2a 4051int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4052 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4053{
d9ee0491 4054 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4055 struct mlx5e_tc_flow *flow;
c5d326b2 4056 int err;
e3a2b7ed 4057
c5d326b2 4058 rcu_read_lock();
ab818362 4059 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4060 if (!flow || !same_flow_direction(flow, flags)) {
4061 err = -EINVAL;
4062 goto errout;
4063 }
e3a2b7ed 4064
c5d326b2
VB		 4065 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4066 * set.
4067 */
4068 if (flow_flag_test_and_set(flow, DELETED)) {
4069 err = -EINVAL;
4070 goto errout;
4071 }
05866c82 4072 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4073 rcu_read_unlock();
e3a2b7ed 4074
7a978759 4075 trace_mlx5e_delete_flower(f);
5a7e5bcb 4076 mlx5e_flow_put(priv, flow);
e3a2b7ed 4077
7dc84de9 4078 mlx5_esw_put(priv->mdev);
e3a2b7ed 4079 return 0;
c5d326b2
VB		 4080
4081errout:
4082 rcu_read_unlock();
4083 return err;
e3a2b7ed
AV		 4084}
4085
71d82d2a 4086int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4087 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4088{
04de7dda 4089 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4090 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4091 struct mlx5_eswitch *peer_esw;
aad7e08d 4092 struct mlx5e_tc_flow *flow;
aad7e08d 4093 struct mlx5_fc *counter;
316d5f72
RD		 4094 u64 lastuse = 0;
4095 u64 packets = 0;
4096 u64 bytes = 0;
5a7e5bcb 4097 int err = 0;
aad7e08d 4098
c5d326b2
VB		 4099 rcu_read_lock();
4100 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4101 tc_ht_params));
4102 rcu_read_unlock();
5a7e5bcb
VB		 4103 if (IS_ERR(flow))
4104 return PTR_ERR(flow);
4105
4106 if (!same_flow_direction(flow, flags)) {
4107 err = -EINVAL;
4108 goto errout;
4109 }
aad7e08d 4110
4c3844d9 4111 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4112 counter = mlx5e_tc_get_counter(flow);
4113 if (!counter)
5a7e5bcb 4114 goto errout;
aad7e08d 4115
316d5f72
RD		 4116 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4117 }
aad7e08d 4118
316d5f72
RD		 4119 /* Under multipath it's possible for one rule to be currently
4120 * un-offloaded while the other rule is offloaded.
4121 */
04de7dda
RD		 4122 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4123 if (!peer_esw)
4124 goto out;
4125
226f2ca3
VB		 4126 if (flow_flag_test(flow, DUP) &&
4127 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4128 u64 bytes2;
4129 u64 packets2;
4130 u64 lastuse2;
4131
4132 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4133 if (!counter)
4134 goto no_peer_counter;
04de7dda
RD		 4135 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4136
4137 bytes += bytes2;
4138 packets += packets2;
4139 lastuse = max_t(u64, lastuse, lastuse2);
4140 }
4141
316d5f72 4142no_peer_counter:
04de7dda 4143 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4144out:
4b61d3e8 4145 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4146 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4147 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4148errout:
4149 mlx5e_flow_put(priv, flow);
4150 return err;
aad7e08d
AV		 4151}
4152
1fe3e316 4153static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4154 struct netlink_ext_ack *extack)
4155{
4156 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4157 struct mlx5_eswitch *esw;
1fe3e316 4158 u32 rate_mbps = 0;
fcb64c0f 4159 u16 vport_num;
fcb64c0f
EC		 4160 int err;
4161
e401a184
EC		 4162 vport_num = rpriv->rep->vport;
4163 if (vport_num >= MLX5_VPORT_ECPF) {
4164 NL_SET_ERR_MSG_MOD(extack,
4165 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4166 return -EOPNOTSUPP;
4167 }
4168
fcb64c0f
EC		 4169 esw = priv->mdev->priv.eswitch;
4170 /* rate is given in bytes/sec.
4171 * First convert to bits/sec and then round to the nearest mbit/secs.
4172 * mbit means million bits.
4173 * Moreover, if rate is non zero we choose to configure to a minimum of
4174 * 1 mbit/sec.
4175 */
1fe3e316
PP		 4176 if (rate) {
4177 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4178 do_div(rate, 1000000);
4179 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4180 }
4181
2d116e3e 4182 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4183 if (err)
4184 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4185
4186 return err;
4187}
4188
4189static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4190 struct flow_action *flow_action,
4191 struct netlink_ext_ack *extack)
4192{
4193 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4194 const struct flow_action_entry *act;
4195 int err;
4196 int i;
4197
4198 if (!flow_action_has_entries(flow_action)) {
4199 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4200 return -EINVAL;
4201 }
4202
4203 if (!flow_offload_has_one_action(flow_action)) {
4204 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4205 return -EOPNOTSUPP;
4206 }
4207
0885ae1a
A		 4208 if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4209 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 4210 return -EOPNOTSUPP;
0885ae1a 4211 }
319a1d19 4212
fcb64c0f
EC		 4213 flow_action_for_each(i, act, flow_action) {
4214 switch (act->id) {
4215 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4216 if (act->police.rate_pkt_ps) {
4217 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4218 return -EOPNOTSUPP;
4219 }
fcb64c0f
EC		 4220 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4221 if (err)
4222 return err;
4223
4224 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4225 break;
4226 default:
4227 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4228 return -EOPNOTSUPP;
4229 }
4230 }
4231
4232 return 0;
4233}
4234
4235int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4236 struct tc_cls_matchall_offload *ma)
4237{
4238 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4239
7b83355f 4240 if (ma->common.prio != 1) {
fcb64c0f
EC		 4241 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4242 return -EINVAL;
4243 }
4244
4245 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4246}
4247
4248int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4249 struct tc_cls_matchall_offload *ma)
4250{
4251 struct netlink_ext_ack *extack = ma->common.extack;
4252
4253 return apply_police_params(priv, 0, extack);
4254}
4255
4256void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4257 struct tc_cls_matchall_offload *ma)
4258{
4259 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4260 struct rtnl_link_stats64 cur_stats;
4261 u64 dbytes;
4262 u64 dpkts;
4263
4264 cur_stats = priv->stats.vf_vport;
4265 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4266 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4267 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4268 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4269 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4270}
4271
4d8fcf21
AH		 4272static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4273 struct mlx5e_priv *peer_priv)
4274{
4275 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4276 struct mlx5e_hairpin_entry *hpe, *tmp;
4277 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4278 u16 peer_vhca_id;
4279 int bkt;
4280
ab3f3d5e 4281 if (!mlx5e_same_hw_devs(priv, peer_priv))
4d8fcf21
AH		 4282 return;
4283
4284 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4285
b32accda 4286 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4287 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4288 if (refcount_inc_not_zero(&hpe->refcnt))
4289 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4290 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4291
4292 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4293 wait_for_completion(&hpe->res_ready);
4294 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4295 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4296
4297 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4298 }
4299}
4300
4301static int mlx5e_tc_netdev_event(struct notifier_block *this,
4302 unsigned long event, void *ptr)
4303{
4304 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4305 struct mlx5e_flow_steering *fs;
4306 struct mlx5e_priv *peer_priv;
4307 struct mlx5e_tc_table *tc;
4308 struct mlx5e_priv *priv;
4309
4310 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4311 event != NETDEV_UNREGISTER ||
4312 ndev->reg_state == NETREG_REGISTERED)
4313 return NOTIFY_DONE;
4314
4315 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4316 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4317 priv = container_of(fs, struct mlx5e_priv, fs);
4318 peer_priv = netdev_priv(ndev);
4319 if (priv == peer_priv ||
4320 !(priv->netdev->features & NETIF_F_HW_TC))
4321 return NOTIFY_DONE;
4322
4323 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4324
4325 return NOTIFY_DONE;
4326}
4327
6a064674
AL		 4328static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4329{
4330 int tc_grp_size, tc_tbl_size;
4331 u32 max_flow_counter;
4332
4333 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4334 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4335
4336 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4337
4338 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4339 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4340
4341 return tc_tbl_size;
4342}
4343
655dc3d2 4344int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4345{
acff797c 4346 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4347 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4348 struct mapping_ctx *chains_mapping;
6a064674 4349 struct mlx5_chains_attr attr = {};
2198b932 4350 u64 mapping_id;
4d8fcf21 4351 int err;
e8f887ac 4352
b2fdf3d0 4353 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4354 mutex_init(&tc->t_lock);
b32accda 4355 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4356 hash_init(tc->hairpin_tbl);
11c9c548 4357
4d8fcf21
AH		 4358 err = rhashtable_init(&tc->ht, &tc_ht_params);
4359 if (err)
4360 return err;
4361
9ba33339
RD		 4362 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4363
2198b932
RD		 4364 mapping_id = mlx5_query_nic_system_image_guid(dev);
4365
4366 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4367 sizeof(struct mlx5_mapped_obj),
4368 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4369
c9355682
CM		 4370 if (IS_ERR(chains_mapping)) {
4371 err = PTR_ERR(chains_mapping);
4372 goto err_mapping;
4373 }
4374 tc->mapping = chains_mapping;
4375
4376 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4377 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4378 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4379 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4380 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4381 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4382 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4383 attr.mapping = chains_mapping;
6a064674
AL		 4384
4385 tc->chains = mlx5_chains_create(dev, &attr);
4386 if (IS_ERR(tc->chains)) {
4387 err = PTR_ERR(tc->chains);
4388 goto err_chains;
4389 }
4390
f0da4daa 4391 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4392 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4393 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4394
4d8fcf21 4395 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4396 err = register_netdevice_notifier_dev_net(priv->netdev,
4397 &tc->netdevice_nb,
4398 &tc->netdevice_nn);
4399 if (err) {
4d8fcf21
AH		 4400 tc->netdevice_nb.notifier_call = NULL;
4401 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 4402 goto err_reg;
4d8fcf21
AH		 4403 }
4404
6a064674
AL		 4405 return 0;
4406
4407err_reg:
aedd133d 4408 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4409 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 4410 mlx5_chains_destroy(tc->chains);
4411err_chains:
c9355682
CM		 4412 mapping_destroy(chains_mapping);
4413err_mapping:
6a064674 4414 rhashtable_destroy(&tc->ht);
4d8fcf21 4415 return err;
e8f887ac
AV		 4416}
4417
4418static void _mlx5e_tc_del_flow(void *ptr, void *arg)
4419{
4420 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 4421 struct mlx5e_priv *priv = flow->priv;
e8f887ac 4422
961e8979 4423 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 4424 kfree(flow);
4425}
4426
655dc3d2 4427void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 4428{
acff797c 4429 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 4430
4d8fcf21 4431 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 4432 unregister_netdevice_notifier_dev_net(priv->netdev,
4433 &tc->netdevice_nb,
4434 &tc->netdevice_nn);
4d8fcf21 4435
b2fdf3d0 4436 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 4437 mutex_destroy(&tc->hairpin_tbl_lock);
4438
6a064674 4439 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 4440
acff797c 4441 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 4442 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 4443 tc->t = NULL;
e8f887ac 4444 }
b6fac0b4 4445 mutex_destroy(&tc->t_lock);
6a064674 4446
aedd133d 4447 mlx5_tc_ct_clean(tc->ct);
f0da4daa 4448 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 4449 mapping_destroy(tc->mapping);
6a064674 4450 mlx5_chains_destroy(tc->chains);
e8f887ac 4451}
655dc3d2 4452
d1a3138f
PB		 4453int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
4454{
4455 int err;
4456
4457 err = rhashtable_init(tc_ht, &tc_ht_params);
4458 if (err)
4459 return err;
4460
4461 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
4462
4463 return 0;
4464}
4465
4466void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
4467{
4468 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
4469}
4470
4471int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
655dc3d2 4472{
d7a42ad0 4473 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
aedd133d 4474 struct mlx5e_rep_priv *rpriv;
0a7fcb78 4475 struct mapping_ctx *mapping;
aedd133d
AL		 4476 struct mlx5_eswitch *esw;
4477 struct mlx5e_priv *priv;
2198b932 4478 u64 mapping_id;
aedd133d 4479 int err = 0;
0a7fcb78 4480
aedd133d
AL		 4481 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
4482 priv = netdev_priv(rpriv->netdev);
4483 esw = priv->mdev->priv.eswitch;
0a7fcb78 4484
f0da4daa
CM		 4485 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
4486 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 4487 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
4488 esw_chains(esw),
4489 &esw->offloads.mod_hdr,
f0da4daa
CM		 4490 MLX5_FLOW_NAMESPACE_FDB,
4491 uplink_priv->post_act);
4c3844d9 4492
4f4edcc2
AL		 4493 uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
4494
2741f223 4495 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 4496
2198b932
RD		 4497 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
4498
4499 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
4500 sizeof(struct tunnel_match_key),
4501 TUNNEL_INFO_BITS_MASK, true);
4502
0a7fcb78
PB		 4503 if (IS_ERR(mapping)) {
4504 err = PTR_ERR(mapping);
4505 goto err_tun_mapping;
4506 }
4507 uplink_priv->tunnel_mapping = mapping;
4508
3222efd4
VB		 4509 /* Two last values are reserved for stack devices slow path table mark
4510 * and bridge ingress push mark.
4511 */
2198b932 4512 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
3222efd4 4513 sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
0a7fcb78
PB		 4514 if (IS_ERR(mapping)) {
4515 err = PTR_ERR(mapping);
4516 goto err_enc_opts_mapping;
4517 }
4518 uplink_priv->tunnel_enc_opts_mapping = mapping;
4519
8914add2 4520 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 4521 if (IS_ERR(uplink_priv->encap)) {
4522 err = PTR_ERR(uplink_priv->encap);
8914add2 4523 goto err_register_fib_notifier;
2b6c3c1e 4524 }
8914add2 4525
2b6c3c1e 4526 return 0;
0a7fcb78 4527
8914add2 4528err_register_fib_notifier:
0a7fcb78
PB		 4529 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4530err_enc_opts_mapping:
4531 mapping_destroy(uplink_priv->tunnel_mapping);
4532err_tun_mapping:
0027d70c 4533 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4534 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4535 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 4536 netdev_warn(priv->netdev,
4537 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 4538 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 4539 return err;
655dc3d2
OG		 4540}
4541
d1a3138f 4542void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
655dc3d2 4543{
8914add2
VB		 4544 mlx5e_tc_tun_cleanup(uplink_priv->encap);
4545
0a7fcb78
PB		 4546 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
4547 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 4548
0027d70c 4549 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
4f4edcc2 4550 mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
aedd133d 4551 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 4552 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 4553}
01252a27 4554
226f2ca3 4555int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 4556{
d9ee0491 4557 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 4558
4559 return atomic_read(&tc_ht->nelems);
4560}
04de7dda
RD		 4561
4562void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
4563{
4564 struct mlx5e_tc_flow *flow, *tmp;
4565
4566 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
4567 __mlx5e_tc_del_fdb_peer_flow(flow);
4568}
b4a23329
RD		 4569
4570void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
4571{
4572 struct mlx5_rep_uplink_priv *rpriv =
4573 container_of(work, struct mlx5_rep_uplink_priv,
4574 reoffload_flows_work);
4575 struct mlx5e_tc_flow *flow, *tmp;
4576
ad86755b 4577 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 4578 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
4579 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 4580 unready_flow_del(flow);
b4a23329 4581 }
ad86755b 4582 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 4583}
e2394a61
VB		 4584
4585static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
4586 struct flow_cls_offload *cls_flower,
4587 unsigned long flags)
4588{
4589 switch (cls_flower->command) {
4590 case FLOW_CLS_REPLACE:
4591 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
4592 flags);
4593 case FLOW_CLS_DESTROY:
4594 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
4595 flags);
4596 case FLOW_CLS_STATS:
4597 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
4598 flags);
4599 default:
4600 return -EOPNOTSUPP;
4601 }
4602}
4603
4604int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
4605 void *cb_priv)
4606{
ec9457a6 4607 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 4608 struct mlx5e_priv *priv = cb_priv;
4609
2ff349c5
RD		 4610 if (!priv->netdev || !netif_device_present(priv->netdev))
4611 return -EOPNOTSUPP;
4612
ec9457a6
RD		 4613 if (mlx5e_is_uplink_rep(priv))
4614 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
4615 else
4616 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
4617
e2394a61
VB		 4618 switch (type) {
4619 case TC_SETUP_CLSFLOWER:
4620 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
4621 default:
4622 return -EOPNOTSUPP;
4623 }
4624}
c7569097
AL		 4625
4626bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
4627 struct sk_buff *skb)
4628{
4629#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 4630 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 4631 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 4632 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 4633 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 4634 struct tc_skb_ext *tc_skb_ext;
4635 int err;
4636
4637 reg_b = be32_to_cpu(cqe->ft_metadata);
4638
4639 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
4640
c9355682 4641 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 4642 if (err) {
4643 netdev_dbg(priv->netdev,
4644 "Couldn't find chain for chain tag: %d, err: %d\n",
4645 chain_tag, err);
4646 return false;
4647 }
4648
a91d98a0
CM		 4649 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
4650 chain = mapped_obj.chain;
9453d45e 4651 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 4652 if (WARN_ON(!tc_skb_ext))
4653 return false;
4654
4655 tc_skb_ext->chain = chain;
aedd133d 4656
ed2fe7ba 4657 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 4658 ESW_ZONE_ID_MASK;
aedd133d
AL		 4659
4660 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
4661 zone_restore_id))
4662 return false;
a91d98a0
CM		 4663 } else {
4664 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
4665 return false;
c7569097
AL		 4666 }
4667#endif /* CONFIG_NET_TC_SKB_EXT */
4668
4669 return true;
4670}
Linux 6.x block layer and io_uring tree(s)