Commit | Line | Data |
---|---|---|
e8f887ac AV |
1 | /* |
2 | * Copyright (c) 2016, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e3a2b7ed | 33 | #include <net/flow_dissector.h> |
3f7d0eb4 | 34 | #include <net/sch_generic.h> |
e3a2b7ed AV |
35 | #include <net/pkt_cls.h> |
36 | #include <net/tc_act/tc_gact.h> | |
12185a9f | 37 | #include <net/tc_act/tc_skbedit.h> |
e8f887ac AV |
38 | #include <linux/mlx5/fs.h> |
39 | #include <linux/mlx5/device.h> | |
40 | #include <linux/rhashtable.h> | |
03a9d11e | 41 | #include <net/tc_act/tc_mirred.h> |
776b12b6 | 42 | #include <net/tc_act/tc_vlan.h> |
bbd00f7e | 43 | #include <net/tc_act/tc_tunnel_key.h> |
d79b6df6 | 44 | #include <net/tc_act/tc_pedit.h> |
26c02749 | 45 | #include <net/tc_act/tc_csum.h> |
f6dfb4c3 | 46 | #include <net/arp.h> |
3616d08b | 47 | #include <net/ipv6_stubs.h> |
e8f887ac | 48 | #include "en.h" |
1d447a39 | 49 | #include "en_rep.h" |
232c0013 | 50 | #include "en_tc.h" |
03a9d11e | 51 | #include "eswitch.h" |
3f6d08d1 | 52 | #include "fs_core.h" |
2c81bfd5 | 53 | #include "en/port.h" |
101f4de9 | 54 | #include "en/tc_tun.h" |
04de7dda | 55 | #include "lib/devcom.h" |
e8f887ac | 56 | |
3bc4b7bf OG |
57 | struct mlx5_nic_flow_attr { |
58 | u32 action; | |
59 | u32 flow_tag; | |
2f4fe4ca | 60 | u32 mod_hdr_id; |
5c65c564 | 61 | u32 hairpin_tirn; |
38aa51c1 | 62 | u8 match_level; |
3f6d08d1 | 63 | struct mlx5_flow_table *hairpin_ft; |
b8aee822 | 64 | struct mlx5_fc *counter; |
3bc4b7bf OG |
65 | }; |
66 | ||
60bd4af8 OG |
67 | #define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1) |
68 | ||
65ba8fb7 | 69 | enum { |
60bd4af8 OG |
70 | MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS, |
71 | MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS, | |
d9ee0491 OG |
72 | MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD, |
73 | MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD, | |
74 | MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE), | |
75 | MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1), | |
76 | MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2), | |
77 | MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3), | |
78 | MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4), | |
ef06c9ee | 79 | MLX5E_TC_FLOW_NOT_READY = BIT(MLX5E_TC_FLOW_BASE + 5), |
65ba8fb7 OG |
80 | }; |
81 | ||
e4ad91f2 CM |
82 | #define MLX5E_TC_MAX_SPLITS 1 |
83 | ||
79baaec7 EB |
84 | /* Helper struct for accessing a struct containing list_head array. |
85 | * Containing struct | |
86 | * |- Helper array | |
87 | * [0] Helper item 0 | |
88 | * |- list_head item 0 | |
89 | * |- index (0) | |
90 | * [1] Helper item 1 | |
91 | * |- list_head item 1 | |
92 | * |- index (1) | |
93 | * To access the containing struct from one of the list_head items: | |
94 | * 1. Get the helper item from the list_head item using | |
95 | * helper item = | |
96 | * container_of(list_head item, helper struct type, list_head field) | |
97 | * 2. Get the contining struct from the helper item and its index in the array: | |
98 | * containing struct = | |
99 | * container_of(helper item, containing struct type, helper field[index]) | |
100 | */ | |
101 | struct encap_flow_item { | |
102 | struct list_head list; | |
103 | int index; | |
104 | }; | |
105 | ||
e8f887ac AV |
106 | struct mlx5e_tc_flow { |
107 | struct rhash_head node; | |
655dc3d2 | 108 | struct mlx5e_priv *priv; |
e8f887ac | 109 | u64 cookie; |
5dbe906f | 110 | u16 flags; |
e4ad91f2 | 111 | struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1]; |
79baaec7 EB |
112 | /* Flow can be associated with multiple encap IDs. |
113 | * The number of encaps is bounded by the number of supported | |
114 | * destinations. | |
115 | */ | |
116 | struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS]; | |
04de7dda | 117 | struct mlx5e_tc_flow *peer_flow; |
11c9c548 | 118 | struct list_head mod_hdr; /* flows sharing the same mod hdr ID */ |
5c65c564 | 119 | struct list_head hairpin; /* flows sharing the same hairpin */ |
04de7dda | 120 | struct list_head peer; /* flows with peer flow */ |
b4a23329 | 121 | struct list_head unready; /* flows not ready to be offloaded (e.g due to missing route) */ |
3bc4b7bf OG |
122 | union { |
123 | struct mlx5_esw_flow_attr esw_attr[0]; | |
124 | struct mlx5_nic_flow_attr nic_attr[0]; | |
125 | }; | |
e8f887ac AV |
126 | }; |
127 | ||
17091853 | 128 | struct mlx5e_tc_flow_parse_attr { |
1f6da306 | 129 | const struct ip_tunnel_info *tun_info[MLX5_MAX_FLOW_FWD_VPORTS]; |
d11afc26 | 130 | struct net_device *filter_dev; |
17091853 | 131 | struct mlx5_flow_spec spec; |
d79b6df6 | 132 | int num_mod_hdr_actions; |
218d05ce | 133 | int max_mod_hdr_actions; |
d79b6df6 | 134 | void *mod_hdr_actions; |
98b66cb1 | 135 | int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS]; |
17091853 OG |
136 | }; |
137 | ||
acff797c | 138 | #define MLX5E_TC_TABLE_NUM_GROUPS 4 |
b3a433de | 139 | #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16) |
e8f887ac | 140 | |
77ab67b7 OG |
141 | struct mlx5e_hairpin { |
142 | struct mlx5_hairpin *pair; | |
143 | ||
144 | struct mlx5_core_dev *func_mdev; | |
3f6d08d1 | 145 | struct mlx5e_priv *func_priv; |
77ab67b7 OG |
146 | u32 tdn; |
147 | u32 tirn; | |
3f6d08d1 OG |
148 | |
149 | int num_channels; | |
150 | struct mlx5e_rqt indir_rqt; | |
151 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
152 | struct mlx5e_ttc_table ttc; | |
77ab67b7 OG |
153 | }; |
154 | ||
5c65c564 OG |
155 | struct mlx5e_hairpin_entry { |
156 | /* a node of a hash table which keeps all the hairpin entries */ | |
157 | struct hlist_node hairpin_hlist; | |
158 | ||
159 | /* flows sharing the same hairpin */ | |
160 | struct list_head flows; | |
161 | ||
d8822868 | 162 | u16 peer_vhca_id; |
106be53b | 163 | u8 prio; |
5c65c564 OG |
164 | struct mlx5e_hairpin *hp; |
165 | }; | |
166 | ||
11c9c548 OG |
167 | struct mod_hdr_key { |
168 | int num_actions; | |
169 | void *actions; | |
170 | }; | |
171 | ||
172 | struct mlx5e_mod_hdr_entry { | |
173 | /* a node of a hash table which keeps all the mod_hdr entries */ | |
174 | struct hlist_node mod_hdr_hlist; | |
175 | ||
176 | /* flows sharing the same mod_hdr entry */ | |
177 | struct list_head flows; | |
178 | ||
179 | struct mod_hdr_key key; | |
180 | ||
181 | u32 mod_hdr_id; | |
182 | }; | |
183 | ||
184 | #define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto) | |
185 | ||
186 | static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key) | |
187 | { | |
188 | return jhash(key->actions, | |
189 | key->num_actions * MLX5_MH_ACT_SZ, 0); | |
190 | } | |
191 | ||
192 | static inline int cmp_mod_hdr_info(struct mod_hdr_key *a, | |
193 | struct mod_hdr_key *b) | |
194 | { | |
195 | if (a->num_actions != b->num_actions) | |
196 | return 1; | |
197 | ||
198 | return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ); | |
199 | } | |
200 | ||
201 | static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv, | |
202 | struct mlx5e_tc_flow *flow, | |
203 | struct mlx5e_tc_flow_parse_attr *parse_attr) | |
204 | { | |
205 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
206 | int num_actions, actions_size, namespace, err; | |
207 | struct mlx5e_mod_hdr_entry *mh; | |
208 | struct mod_hdr_key key; | |
209 | bool found = false; | |
210 | u32 hash_key; | |
211 | ||
212 | num_actions = parse_attr->num_mod_hdr_actions; | |
213 | actions_size = MLX5_MH_ACT_SZ * num_actions; | |
214 | ||
215 | key.actions = parse_attr->mod_hdr_actions; | |
216 | key.num_actions = num_actions; | |
217 | ||
218 | hash_key = hash_mod_hdr_info(&key); | |
219 | ||
220 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { | |
221 | namespace = MLX5_FLOW_NAMESPACE_FDB; | |
222 | hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh, | |
223 | mod_hdr_hlist, hash_key) { | |
224 | if (!cmp_mod_hdr_info(&mh->key, &key)) { | |
225 | found = true; | |
226 | break; | |
227 | } | |
228 | } | |
229 | } else { | |
230 | namespace = MLX5_FLOW_NAMESPACE_KERNEL; | |
231 | hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh, | |
232 | mod_hdr_hlist, hash_key) { | |
233 | if (!cmp_mod_hdr_info(&mh->key, &key)) { | |
234 | found = true; | |
235 | break; | |
236 | } | |
237 | } | |
238 | } | |
239 | ||
240 | if (found) | |
241 | goto attach_flow; | |
242 | ||
243 | mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL); | |
244 | if (!mh) | |
245 | return -ENOMEM; | |
246 | ||
247 | mh->key.actions = (void *)mh + sizeof(*mh); | |
248 | memcpy(mh->key.actions, key.actions, actions_size); | |
249 | mh->key.num_actions = num_actions; | |
250 | INIT_LIST_HEAD(&mh->flows); | |
251 | ||
252 | err = mlx5_modify_header_alloc(priv->mdev, namespace, | |
253 | mh->key.num_actions, | |
254 | mh->key.actions, | |
255 | &mh->mod_hdr_id); | |
256 | if (err) | |
257 | goto out_err; | |
258 | ||
259 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) | |
260 | hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key); | |
261 | else | |
262 | hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key); | |
263 | ||
264 | attach_flow: | |
265 | list_add(&flow->mod_hdr, &mh->flows); | |
266 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) | |
267 | flow->esw_attr->mod_hdr_id = mh->mod_hdr_id; | |
268 | else | |
269 | flow->nic_attr->mod_hdr_id = mh->mod_hdr_id; | |
270 | ||
271 | return 0; | |
272 | ||
273 | out_err: | |
274 | kfree(mh); | |
275 | return err; | |
276 | } | |
277 | ||
278 | static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv, | |
279 | struct mlx5e_tc_flow *flow) | |
280 | { | |
281 | struct list_head *next = flow->mod_hdr.next; | |
282 | ||
283 | list_del(&flow->mod_hdr); | |
284 | ||
285 | if (list_empty(next)) { | |
286 | struct mlx5e_mod_hdr_entry *mh; | |
287 | ||
288 | mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows); | |
289 | ||
290 | mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id); | |
291 | hash_del(&mh->mod_hdr_hlist); | |
292 | kfree(mh); | |
293 | } | |
294 | } | |
295 | ||
77ab67b7 OG |
296 | static |
297 | struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex) | |
298 | { | |
299 | struct net_device *netdev; | |
300 | struct mlx5e_priv *priv; | |
301 | ||
302 | netdev = __dev_get_by_index(net, ifindex); | |
303 | priv = netdev_priv(netdev); | |
304 | return priv->mdev; | |
305 | } | |
306 | ||
307 | static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp) | |
308 | { | |
309 | u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0}; | |
310 | void *tirc; | |
311 | int err; | |
312 | ||
313 | err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn); | |
314 | if (err) | |
315 | goto alloc_tdn_err; | |
316 | ||
317 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
318 | ||
319 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT); | |
ddae74ac | 320 | MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]); |
77ab67b7 OG |
321 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); |
322 | ||
323 | err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn); | |
324 | if (err) | |
325 | goto create_tir_err; | |
326 | ||
327 | return 0; | |
328 | ||
329 | create_tir_err: | |
330 | mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); | |
331 | alloc_tdn_err: | |
332 | return err; | |
333 | } | |
334 | ||
335 | static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp) | |
336 | { | |
337 | mlx5_core_destroy_tir(hp->func_mdev, hp->tirn); | |
338 | mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn); | |
339 | } | |
340 | ||
3f6d08d1 OG |
341 | static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc) |
342 | { | |
343 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn; | |
344 | struct mlx5e_priv *priv = hp->func_priv; | |
345 | int i, ix, sz = MLX5E_INDIR_RQT_SIZE; | |
346 | ||
347 | mlx5e_build_default_indir_rqt(indirection_rqt, sz, | |
348 | hp->num_channels); | |
349 | ||
350 | for (i = 0; i < sz; i++) { | |
351 | ix = i; | |
bbeb53b8 | 352 | if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR) |
3f6d08d1 OG |
353 | ix = mlx5e_bits_invert(i, ilog2(sz)); |
354 | ix = indirection_rqt[ix]; | |
355 | rqn = hp->pair->rqn[ix]; | |
356 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
357 | } | |
358 | } | |
359 | ||
360 | static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp) | |
361 | { | |
362 | int inlen, err, sz = MLX5E_INDIR_RQT_SIZE; | |
363 | struct mlx5e_priv *priv = hp->func_priv; | |
364 | struct mlx5_core_dev *mdev = priv->mdev; | |
365 | void *rqtc; | |
366 | u32 *in; | |
367 | ||
368 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; | |
369 | in = kvzalloc(inlen, GFP_KERNEL); | |
370 | if (!in) | |
371 | return -ENOMEM; | |
372 | ||
373 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
374 | ||
375 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
376 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
377 | ||
378 | mlx5e_hairpin_fill_rqt_rqns(hp, rqtc); | |
379 | ||
380 | err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn); | |
381 | if (!err) | |
382 | hp->indir_rqt.enabled = true; | |
383 | ||
384 | kvfree(in); | |
385 | return err; | |
386 | } | |
387 | ||
388 | static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp) | |
389 | { | |
390 | struct mlx5e_priv *priv = hp->func_priv; | |
391 | u32 in[MLX5_ST_SZ_DW(create_tir_in)]; | |
392 | int tt, i, err; | |
393 | void *tirc; | |
394 | ||
395 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
d930ac79 AL |
396 | struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt); |
397 | ||
3f6d08d1 OG |
398 | memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in)); |
399 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
400 | ||
401 | MLX5_SET(tirc, tirc, transport_domain, hp->tdn); | |
402 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
403 | MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn); | |
bbeb53b8 AL |
404 | mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false); |
405 | ||
3f6d08d1 OG |
406 | err = mlx5_core_create_tir(hp->func_mdev, in, |
407 | MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]); | |
408 | if (err) { | |
409 | mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err); | |
410 | goto err_destroy_tirs; | |
411 | } | |
412 | } | |
413 | return 0; | |
414 | ||
415 | err_destroy_tirs: | |
416 | for (i = 0; i < tt; i++) | |
417 | mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]); | |
418 | return err; | |
419 | } | |
420 | ||
421 | static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp) | |
422 | { | |
423 | int tt; | |
424 | ||
425 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) | |
426 | mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]); | |
427 | } | |
428 | ||
429 | static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp, | |
430 | struct ttc_params *ttc_params) | |
431 | { | |
432 | struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr; | |
433 | int tt; | |
434 | ||
435 | memset(ttc_params, 0, sizeof(*ttc_params)); | |
436 | ||
437 | ttc_params->any_tt_tirn = hp->tirn; | |
438 | ||
439 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) | |
440 | ttc_params->indir_tirn[tt] = hp->indir_tirn[tt]; | |
441 | ||
442 | ft_attr->max_fte = MLX5E_NUM_TT; | |
443 | ft_attr->level = MLX5E_TC_TTC_FT_LEVEL; | |
444 | ft_attr->prio = MLX5E_TC_PRIO; | |
445 | } | |
446 | ||
447 | static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp) | |
448 | { | |
449 | struct mlx5e_priv *priv = hp->func_priv; | |
450 | struct ttc_params ttc_params; | |
451 | int err; | |
452 | ||
453 | err = mlx5e_hairpin_create_indirect_rqt(hp); | |
454 | if (err) | |
455 | return err; | |
456 | ||
457 | err = mlx5e_hairpin_create_indirect_tirs(hp); | |
458 | if (err) | |
459 | goto err_create_indirect_tirs; | |
460 | ||
461 | mlx5e_hairpin_set_ttc_params(hp, &ttc_params); | |
462 | err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc); | |
463 | if (err) | |
464 | goto err_create_ttc_table; | |
465 | ||
466 | netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n", | |
467 | hp->num_channels, hp->ttc.ft.t->id); | |
468 | ||
469 | return 0; | |
470 | ||
471 | err_create_ttc_table: | |
472 | mlx5e_hairpin_destroy_indirect_tirs(hp); | |
473 | err_create_indirect_tirs: | |
474 | mlx5e_destroy_rqt(priv, &hp->indir_rqt); | |
475 | ||
476 | return err; | |
477 | } | |
478 | ||
479 | static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp) | |
480 | { | |
481 | struct mlx5e_priv *priv = hp->func_priv; | |
482 | ||
483 | mlx5e_destroy_ttc_table(priv, &hp->ttc); | |
484 | mlx5e_hairpin_destroy_indirect_tirs(hp); | |
485 | mlx5e_destroy_rqt(priv, &hp->indir_rqt); | |
486 | } | |
487 | ||
77ab67b7 OG |
488 | static struct mlx5e_hairpin * |
489 | mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params, | |
490 | int peer_ifindex) | |
491 | { | |
492 | struct mlx5_core_dev *func_mdev, *peer_mdev; | |
493 | struct mlx5e_hairpin *hp; | |
494 | struct mlx5_hairpin *pair; | |
495 | int err; | |
496 | ||
497 | hp = kzalloc(sizeof(*hp), GFP_KERNEL); | |
498 | if (!hp) | |
499 | return ERR_PTR(-ENOMEM); | |
500 | ||
501 | func_mdev = priv->mdev; | |
502 | peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); | |
503 | ||
504 | pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params); | |
505 | if (IS_ERR(pair)) { | |
506 | err = PTR_ERR(pair); | |
507 | goto create_pair_err; | |
508 | } | |
509 | hp->pair = pair; | |
510 | hp->func_mdev = func_mdev; | |
3f6d08d1 OG |
511 | hp->func_priv = priv; |
512 | hp->num_channels = params->num_channels; | |
77ab67b7 OG |
513 | |
514 | err = mlx5e_hairpin_create_transport(hp); | |
515 | if (err) | |
516 | goto create_transport_err; | |
517 | ||
3f6d08d1 OG |
518 | if (hp->num_channels > 1) { |
519 | err = mlx5e_hairpin_rss_init(hp); | |
520 | if (err) | |
521 | goto rss_init_err; | |
522 | } | |
523 | ||
77ab67b7 OG |
524 | return hp; |
525 | ||
3f6d08d1 OG |
526 | rss_init_err: |
527 | mlx5e_hairpin_destroy_transport(hp); | |
77ab67b7 OG |
528 | create_transport_err: |
529 | mlx5_core_hairpin_destroy(hp->pair); | |
530 | create_pair_err: | |
531 | kfree(hp); | |
532 | return ERR_PTR(err); | |
533 | } | |
534 | ||
535 | static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp) | |
536 | { | |
3f6d08d1 OG |
537 | if (hp->num_channels > 1) |
538 | mlx5e_hairpin_rss_cleanup(hp); | |
77ab67b7 OG |
539 | mlx5e_hairpin_destroy_transport(hp); |
540 | mlx5_core_hairpin_destroy(hp->pair); | |
541 | kvfree(hp); | |
542 | } | |
543 | ||
106be53b OG |
544 | static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio) |
545 | { | |
546 | return (peer_vhca_id << 16 | prio); | |
547 | } | |
548 | ||
5c65c564 | 549 | static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv, |
106be53b | 550 | u16 peer_vhca_id, u8 prio) |
5c65c564 OG |
551 | { |
552 | struct mlx5e_hairpin_entry *hpe; | |
106be53b | 553 | u32 hash_key = hash_hairpin_info(peer_vhca_id, prio); |
5c65c564 OG |
554 | |
555 | hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe, | |
106be53b OG |
556 | hairpin_hlist, hash_key) { |
557 | if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) | |
5c65c564 OG |
558 | return hpe; |
559 | } | |
560 | ||
561 | return NULL; | |
562 | } | |
563 | ||
106be53b OG |
564 | #define UNKNOWN_MATCH_PRIO 8 |
565 | ||
566 | static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv, | |
e98bedf5 EB |
567 | struct mlx5_flow_spec *spec, u8 *match_prio, |
568 | struct netlink_ext_ack *extack) | |
106be53b OG |
569 | { |
570 | void *headers_c, *headers_v; | |
571 | u8 prio_val, prio_mask = 0; | |
572 | bool vlan_present; | |
573 | ||
574 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
575 | if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) { | |
e98bedf5 EB |
576 | NL_SET_ERR_MSG_MOD(extack, |
577 | "only PCP trust state supported for hairpin"); | |
106be53b OG |
578 | return -EOPNOTSUPP; |
579 | } | |
580 | #endif | |
581 | headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers); | |
582 | headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers); | |
583 | ||
584 | vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag); | |
585 | if (vlan_present) { | |
586 | prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); | |
587 | prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); | |
588 | } | |
589 | ||
590 | if (!vlan_present || !prio_mask) { | |
591 | prio_val = UNKNOWN_MATCH_PRIO; | |
592 | } else if (prio_mask != 0x7) { | |
e98bedf5 EB |
593 | NL_SET_ERR_MSG_MOD(extack, |
594 | "masked priority match not supported for hairpin"); | |
106be53b OG |
595 | return -EOPNOTSUPP; |
596 | } | |
597 | ||
598 | *match_prio = prio_val; | |
599 | return 0; | |
600 | } | |
601 | ||
5c65c564 OG |
602 | static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv, |
603 | struct mlx5e_tc_flow *flow, | |
e98bedf5 EB |
604 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
605 | struct netlink_ext_ack *extack) | |
5c65c564 | 606 | { |
98b66cb1 | 607 | int peer_ifindex = parse_attr->mirred_ifindex[0]; |
5c65c564 | 608 | struct mlx5_hairpin_params params; |
d8822868 | 609 | struct mlx5_core_dev *peer_mdev; |
5c65c564 OG |
610 | struct mlx5e_hairpin_entry *hpe; |
611 | struct mlx5e_hairpin *hp; | |
3f6d08d1 OG |
612 | u64 link_speed64; |
613 | u32 link_speed; | |
106be53b | 614 | u8 match_prio; |
d8822868 | 615 | u16 peer_id; |
5c65c564 OG |
616 | int err; |
617 | ||
d8822868 OG |
618 | peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex); |
619 | if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) { | |
e98bedf5 | 620 | NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported"); |
5c65c564 OG |
621 | return -EOPNOTSUPP; |
622 | } | |
623 | ||
d8822868 | 624 | peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id); |
e98bedf5 EB |
625 | err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio, |
626 | extack); | |
106be53b OG |
627 | if (err) |
628 | return err; | |
629 | hpe = mlx5e_hairpin_get(priv, peer_id, match_prio); | |
5c65c564 OG |
630 | if (hpe) |
631 | goto attach_flow; | |
632 | ||
633 | hpe = kzalloc(sizeof(*hpe), GFP_KERNEL); | |
634 | if (!hpe) | |
635 | return -ENOMEM; | |
636 | ||
637 | INIT_LIST_HEAD(&hpe->flows); | |
d8822868 | 638 | hpe->peer_vhca_id = peer_id; |
106be53b | 639 | hpe->prio = match_prio; |
5c65c564 OG |
640 | |
641 | params.log_data_size = 15; | |
642 | params.log_data_size = min_t(u8, params.log_data_size, | |
643 | MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz)); | |
644 | params.log_data_size = max_t(u8, params.log_data_size, | |
645 | MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz)); | |
5c65c564 | 646 | |
eb9180f7 OG |
647 | params.log_num_packets = params.log_data_size - |
648 | MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev); | |
649 | params.log_num_packets = min_t(u8, params.log_num_packets, | |
650 | MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets)); | |
651 | ||
652 | params.q_counter = priv->q_counter; | |
3f6d08d1 | 653 | /* set hairpin pair per each 50Gbs share of the link */ |
2c81bfd5 | 654 | mlx5e_port_max_linkspeed(priv->mdev, &link_speed); |
3f6d08d1 OG |
655 | link_speed = max_t(u32, link_speed, 50000); |
656 | link_speed64 = link_speed; | |
657 | do_div(link_speed64, 50000); | |
658 | params.num_channels = link_speed64; | |
659 | ||
5c65c564 OG |
660 | hp = mlx5e_hairpin_create(priv, ¶ms, peer_ifindex); |
661 | if (IS_ERR(hp)) { | |
662 | err = PTR_ERR(hp); | |
663 | goto create_hairpin_err; | |
664 | } | |
665 | ||
eb9180f7 | 666 | netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n", |
27b942fb PP |
667 | hp->tirn, hp->pair->rqn[0], |
668 | dev_name(hp->pair->peer_mdev->device), | |
eb9180f7 | 669 | hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets); |
5c65c564 OG |
670 | |
671 | hpe->hp = hp; | |
106be53b OG |
672 | hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist, |
673 | hash_hairpin_info(peer_id, match_prio)); | |
5c65c564 OG |
674 | |
675 | attach_flow: | |
3f6d08d1 OG |
676 | if (hpe->hp->num_channels > 1) { |
677 | flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS; | |
678 | flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t; | |
679 | } else { | |
680 | flow->nic_attr->hairpin_tirn = hpe->hp->tirn; | |
681 | } | |
5c65c564 | 682 | list_add(&flow->hairpin, &hpe->flows); |
3f6d08d1 | 683 | |
5c65c564 OG |
684 | return 0; |
685 | ||
686 | create_hairpin_err: | |
687 | kfree(hpe); | |
688 | return err; | |
689 | } | |
690 | ||
691 | static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv, | |
692 | struct mlx5e_tc_flow *flow) | |
693 | { | |
694 | struct list_head *next = flow->hairpin.next; | |
695 | ||
696 | list_del(&flow->hairpin); | |
697 | ||
698 | /* no more hairpin flows for us, release the hairpin pair */ | |
699 | if (list_empty(next)) { | |
700 | struct mlx5e_hairpin_entry *hpe; | |
701 | ||
702 | hpe = list_entry(next, struct mlx5e_hairpin_entry, flows); | |
703 | ||
704 | netdev_dbg(priv->netdev, "del hairpin: peer %s\n", | |
27b942fb | 705 | dev_name(hpe->hp->pair->peer_mdev->device)); |
5c65c564 OG |
706 | |
707 | mlx5e_hairpin_destroy(hpe->hp); | |
708 | hash_del(&hpe->hairpin_hlist); | |
709 | kfree(hpe); | |
710 | } | |
711 | } | |
712 | ||
c83954ab | 713 | static int |
74491de9 | 714 | mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv, |
17091853 | 715 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
716 | struct mlx5e_tc_flow *flow, |
717 | struct netlink_ext_ack *extack) | |
e8f887ac | 718 | { |
aa0cbbae | 719 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
aad7e08d | 720 | struct mlx5_core_dev *dev = priv->mdev; |
5c65c564 | 721 | struct mlx5_flow_destination dest[2] = {}; |
66958ed9 | 722 | struct mlx5_flow_act flow_act = { |
3bc4b7bf OG |
723 | .action = attr->action, |
724 | .flow_tag = attr->flow_tag, | |
60786f09 | 725 | .reformat_id = 0, |
42f7ad67 | 726 | .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND, |
66958ed9 | 727 | }; |
aad7e08d | 728 | struct mlx5_fc *counter = NULL; |
e8f887ac | 729 | bool table_created = false; |
5c65c564 | 730 | int err, dest_ix = 0; |
e8f887ac | 731 | |
3f6d08d1 | 732 | if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) { |
e98bedf5 | 733 | err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack); |
3f6d08d1 | 734 | if (err) { |
3f6d08d1 OG |
735 | goto err_add_hairpin_flow; |
736 | } | |
737 | if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) { | |
738 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
739 | dest[dest_ix].ft = attr->hairpin_ft; | |
740 | } else { | |
5c65c564 OG |
741 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR; |
742 | dest[dest_ix].tir_num = attr->hairpin_tirn; | |
5c65c564 OG |
743 | } |
744 | dest_ix++; | |
3f6d08d1 OG |
745 | } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { |
746 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; | |
747 | dest[dest_ix].ft = priv->fs.vlan.ft.t; | |
748 | dest_ix++; | |
5c65c564 | 749 | } |
aad7e08d | 750 | |
5c65c564 OG |
751 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
752 | counter = mlx5_fc_create(dev, true); | |
753 | if (IS_ERR(counter)) { | |
c83954ab | 754 | err = PTR_ERR(counter); |
5c65c564 OG |
755 | goto err_fc_create; |
756 | } | |
757 | dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER; | |
171c7625 | 758 | dest[dest_ix].counter_id = mlx5_fc_id(counter); |
5c65c564 | 759 | dest_ix++; |
b8aee822 | 760 | attr->counter = counter; |
aad7e08d AV |
761 | } |
762 | ||
2f4fe4ca | 763 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { |
3099eb5a | 764 | err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); |
d7e75a32 | 765 | flow_act.modify_id = attr->mod_hdr_id; |
2f4fe4ca | 766 | kfree(parse_attr->mod_hdr_actions); |
c83954ab | 767 | if (err) |
2f4fe4ca | 768 | goto err_create_mod_hdr_id; |
2f4fe4ca OG |
769 | } |
770 | ||
acff797c | 771 | if (IS_ERR_OR_NULL(priv->fs.tc.t)) { |
21b9c144 OG |
772 | int tc_grp_size, tc_tbl_size; |
773 | u32 max_flow_counter; | |
774 | ||
775 | max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) | | |
776 | MLX5_CAP_GEN(dev, max_flow_counter_15_0); | |
777 | ||
778 | tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE); | |
779 | ||
780 | tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS, | |
781 | BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size))); | |
782 | ||
acff797c MG |
783 | priv->fs.tc.t = |
784 | mlx5_create_auto_grouped_flow_table(priv->fs.ns, | |
785 | MLX5E_TC_PRIO, | |
21b9c144 | 786 | tc_tbl_size, |
acff797c | 787 | MLX5E_TC_TABLE_NUM_GROUPS, |
3f6d08d1 | 788 | MLX5E_TC_FT_LEVEL, 0); |
acff797c | 789 | if (IS_ERR(priv->fs.tc.t)) { |
e98bedf5 EB |
790 | NL_SET_ERR_MSG_MOD(extack, |
791 | "Failed to create tc offload table\n"); | |
e8f887ac AV |
792 | netdev_err(priv->netdev, |
793 | "Failed to create tc offload table\n"); | |
c83954ab | 794 | err = PTR_ERR(priv->fs.tc.t); |
aad7e08d | 795 | goto err_create_ft; |
e8f887ac AV |
796 | } |
797 | ||
798 | table_created = true; | |
799 | } | |
800 | ||
38aa51c1 | 801 | if (attr->match_level != MLX5_MATCH_NONE) |
d4a18e16 | 802 | parse_attr->spec.match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS; |
38aa51c1 | 803 | |
c83954ab RL |
804 | flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec, |
805 | &flow_act, dest, dest_ix); | |
aad7e08d | 806 | |
c83954ab RL |
807 | if (IS_ERR(flow->rule[0])) { |
808 | err = PTR_ERR(flow->rule[0]); | |
aad7e08d | 809 | goto err_add_rule; |
c83954ab | 810 | } |
aad7e08d | 811 | |
c83954ab | 812 | return 0; |
e8f887ac | 813 | |
aad7e08d AV |
814 | err_add_rule: |
815 | if (table_created) { | |
acff797c MG |
816 | mlx5_destroy_flow_table(priv->fs.tc.t); |
817 | priv->fs.tc.t = NULL; | |
e8f887ac | 818 | } |
aad7e08d | 819 | err_create_ft: |
2f4fe4ca | 820 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
3099eb5a | 821 | mlx5e_detach_mod_hdr(priv, flow); |
2f4fe4ca | 822 | err_create_mod_hdr_id: |
aad7e08d | 823 | mlx5_fc_destroy(dev, counter); |
5c65c564 OG |
824 | err_fc_create: |
825 | if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) | |
826 | mlx5e_hairpin_flow_del(priv, flow); | |
827 | err_add_hairpin_flow: | |
c83954ab | 828 | return err; |
e8f887ac AV |
829 | } |
830 | ||
d85cdccb OG |
831 | static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv, |
832 | struct mlx5e_tc_flow *flow) | |
833 | { | |
513f8f7f | 834 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
d85cdccb OG |
835 | struct mlx5_fc *counter = NULL; |
836 | ||
b8aee822 | 837 | counter = attr->counter; |
e4ad91f2 | 838 | mlx5_del_flow_rules(flow->rule[0]); |
aa0cbbae | 839 | mlx5_fc_destroy(priv->mdev, counter); |
d85cdccb | 840 | |
d9ee0491 | 841 | if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) { |
d85cdccb OG |
842 | mlx5_destroy_flow_table(priv->fs.tc.t); |
843 | priv->fs.tc.t = NULL; | |
844 | } | |
2f4fe4ca | 845 | |
513f8f7f | 846 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
3099eb5a | 847 | mlx5e_detach_mod_hdr(priv, flow); |
5c65c564 OG |
848 | |
849 | if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) | |
850 | mlx5e_hairpin_flow_del(priv, flow); | |
d85cdccb OG |
851 | } |
852 | ||
aa0cbbae | 853 | static void mlx5e_detach_encap(struct mlx5e_priv *priv, |
8c4dc42b | 854 | struct mlx5e_tc_flow *flow, int out_index); |
aa0cbbae | 855 | |
3c37745e | 856 | static int mlx5e_attach_encap(struct mlx5e_priv *priv, |
e98bedf5 | 857 | struct mlx5e_tc_flow *flow, |
733d4f36 RD |
858 | struct net_device *mirred_dev, |
859 | int out_index, | |
8c4dc42b | 860 | struct netlink_ext_ack *extack, |
0ad060ee RD |
861 | struct net_device **encap_dev, |
862 | bool *encap_valid); | |
3c37745e | 863 | |
6d2a3ed0 OG |
864 | static struct mlx5_flow_handle * |
865 | mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw, | |
866 | struct mlx5e_tc_flow *flow, | |
867 | struct mlx5_flow_spec *spec, | |
868 | struct mlx5_esw_flow_attr *attr) | |
869 | { | |
870 | struct mlx5_flow_handle *rule; | |
871 | ||
872 | rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr); | |
873 | if (IS_ERR(rule)) | |
874 | return rule; | |
875 | ||
e85e02ba | 876 | if (attr->split_count) { |
6d2a3ed0 OG |
877 | flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr); |
878 | if (IS_ERR(flow->rule[1])) { | |
879 | mlx5_eswitch_del_offloaded_rule(esw, rule, attr); | |
880 | return flow->rule[1]; | |
881 | } | |
882 | } | |
883 | ||
884 | flow->flags |= MLX5E_TC_FLOW_OFFLOADED; | |
885 | return rule; | |
886 | } | |
887 | ||
888 | static void | |
889 | mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw, | |
890 | struct mlx5e_tc_flow *flow, | |
891 | struct mlx5_esw_flow_attr *attr) | |
892 | { | |
893 | flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED; | |
894 | ||
e85e02ba | 895 | if (attr->split_count) |
6d2a3ed0 OG |
896 | mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr); |
897 | ||
898 | mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr); | |
899 | } | |
900 | ||
5dbe906f PB |
901 | static struct mlx5_flow_handle * |
902 | mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw, | |
903 | struct mlx5e_tc_flow *flow, | |
904 | struct mlx5_flow_spec *spec, | |
905 | struct mlx5_esw_flow_attr *slow_attr) | |
906 | { | |
907 | struct mlx5_flow_handle *rule; | |
908 | ||
909 | memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr)); | |
154e62ab | 910 | slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
2be09de7 | 911 | slow_attr->split_count = 0; |
154e62ab | 912 | slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN; |
5dbe906f PB |
913 | |
914 | rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr); | |
915 | if (!IS_ERR(rule)) | |
916 | flow->flags |= MLX5E_TC_FLOW_SLOW; | |
917 | ||
918 | return rule; | |
919 | } | |
920 | ||
921 | static void | |
922 | mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw, | |
923 | struct mlx5e_tc_flow *flow, | |
924 | struct mlx5_esw_flow_attr *slow_attr) | |
925 | { | |
926 | memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr)); | |
154e62ab | 927 | slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
2be09de7 | 928 | slow_attr->split_count = 0; |
154e62ab | 929 | slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN; |
5dbe906f PB |
930 | mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr); |
931 | flow->flags &= ~MLX5E_TC_FLOW_SLOW; | |
932 | } | |
933 | ||
b4a23329 RD |
934 | static void add_unready_flow(struct mlx5e_tc_flow *flow) |
935 | { | |
936 | struct mlx5_rep_uplink_priv *uplink_priv; | |
937 | struct mlx5e_rep_priv *rpriv; | |
938 | struct mlx5_eswitch *esw; | |
939 | ||
940 | esw = flow->priv->mdev->priv.eswitch; | |
941 | rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); | |
942 | uplink_priv = &rpriv->uplink_priv; | |
943 | ||
944 | flow->flags |= MLX5E_TC_FLOW_NOT_READY; | |
945 | list_add_tail(&flow->unready, &uplink_priv->unready_flows); | |
946 | } | |
947 | ||
948 | static void remove_unready_flow(struct mlx5e_tc_flow *flow) | |
949 | { | |
950 | list_del(&flow->unready); | |
951 | flow->flags &= ~MLX5E_TC_FLOW_NOT_READY; | |
952 | } | |
953 | ||
c83954ab | 954 | static int |
74491de9 | 955 | mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv, |
e98bedf5 EB |
956 | struct mlx5e_tc_flow *flow, |
957 | struct netlink_ext_ack *extack) | |
adb4c123 OG |
958 | { |
959 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
bf07aa73 | 960 | u32 max_chain = mlx5_eswitch_get_chain_range(esw); |
aa0cbbae | 961 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
7040632d | 962 | struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; |
bf07aa73 | 963 | u16 max_prio = mlx5_eswitch_get_prio_range(esw); |
3c37745e | 964 | struct net_device *out_dev, *encap_dev = NULL; |
b8aee822 | 965 | struct mlx5_fc *counter = NULL; |
3c37745e OG |
966 | struct mlx5e_rep_priv *rpriv; |
967 | struct mlx5e_priv *out_priv; | |
0ad060ee RD |
968 | bool encap_valid = true; |
969 | int err = 0; | |
f493f155 | 970 | int out_index; |
8b32580d | 971 | |
d14f6f2a OG |
972 | if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) { |
973 | NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW"); | |
974 | return -EOPNOTSUPP; | |
975 | } | |
bf07aa73 PB |
976 | |
977 | if (attr->chain > max_chain) { | |
978 | NL_SET_ERR_MSG(extack, "Requested chain is out of supported range"); | |
979 | err = -EOPNOTSUPP; | |
980 | goto err_max_prio_chain; | |
981 | } | |
982 | ||
983 | if (attr->prio > max_prio) { | |
984 | NL_SET_ERR_MSG(extack, "Requested priority is out of supported range"); | |
985 | err = -EOPNOTSUPP; | |
986 | goto err_max_prio_chain; | |
987 | } | |
e52c2802 | 988 | |
f493f155 | 989 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) { |
8c4dc42b EB |
990 | int mirred_ifindex; |
991 | ||
f493f155 EB |
992 | if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)) |
993 | continue; | |
994 | ||
7040632d | 995 | mirred_ifindex = parse_attr->mirred_ifindex[out_index]; |
3c37745e | 996 | out_dev = __dev_get_by_index(dev_net(priv->netdev), |
8c4dc42b | 997 | mirred_ifindex); |
733d4f36 | 998 | err = mlx5e_attach_encap(priv, flow, out_dev, out_index, |
0ad060ee RD |
999 | extack, &encap_dev, &encap_valid); |
1000 | if (err) | |
c83954ab | 1001 | goto err_attach_encap; |
0ad060ee | 1002 | |
3c37745e OG |
1003 | out_priv = netdev_priv(encap_dev); |
1004 | rpriv = out_priv->ppriv; | |
1cc26d74 EB |
1005 | attr->dests[out_index].rep = rpriv->rep; |
1006 | attr->dests[out_index].mdev = out_priv->mdev; | |
3c37745e OG |
1007 | } |
1008 | ||
8b32580d | 1009 | err = mlx5_eswitch_add_vlan_action(esw, attr); |
c83954ab | 1010 | if (err) |
aa0cbbae | 1011 | goto err_add_vlan; |
adb4c123 | 1012 | |
d7e75a32 | 1013 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) { |
1a9527bb | 1014 | err = mlx5e_attach_mod_hdr(priv, flow, parse_attr); |
d7e75a32 | 1015 | kfree(parse_attr->mod_hdr_actions); |
c83954ab | 1016 | if (err) |
d7e75a32 | 1017 | goto err_mod_hdr; |
d7e75a32 OG |
1018 | } |
1019 | ||
b8aee822 | 1020 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) { |
f9392795 | 1021 | counter = mlx5_fc_create(attr->counter_dev, true); |
b8aee822 | 1022 | if (IS_ERR(counter)) { |
c83954ab | 1023 | err = PTR_ERR(counter); |
b8aee822 MB |
1024 | goto err_create_counter; |
1025 | } | |
1026 | ||
1027 | attr->counter = counter; | |
1028 | } | |
1029 | ||
0ad060ee RD |
1030 | /* we get here if one of the following takes place: |
1031 | * (1) there's no error | |
1032 | * (2) there's an encap action and we don't have valid neigh | |
3c37745e | 1033 | */ |
0ad060ee | 1034 | if (!encap_valid) { |
5dbe906f PB |
1035 | /* continue with goto slow path rule instead */ |
1036 | struct mlx5_esw_flow_attr slow_attr; | |
1037 | ||
1038 | flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr); | |
1039 | } else { | |
6d2a3ed0 | 1040 | flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr); |
3c37745e | 1041 | } |
c83954ab | 1042 | |
5dbe906f PB |
1043 | if (IS_ERR(flow->rule[0])) { |
1044 | err = PTR_ERR(flow->rule[0]); | |
1045 | goto err_add_rule; | |
1046 | } | |
1047 | ||
1048 | return 0; | |
aa0cbbae OG |
1049 | |
1050 | err_add_rule: | |
f9392795 | 1051 | mlx5_fc_destroy(attr->counter_dev, counter); |
b8aee822 | 1052 | err_create_counter: |
513f8f7f | 1053 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
1a9527bb | 1054 | mlx5e_detach_mod_hdr(priv, flow); |
d7e75a32 | 1055 | err_mod_hdr: |
aa0cbbae OG |
1056 | mlx5_eswitch_del_vlan_action(esw, attr); |
1057 | err_add_vlan: | |
f493f155 | 1058 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) |
8c4dc42b EB |
1059 | if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) |
1060 | mlx5e_detach_encap(priv, flow, out_index); | |
3c37745e | 1061 | err_attach_encap: |
bf07aa73 | 1062 | err_max_prio_chain: |
c83954ab | 1063 | return err; |
aa0cbbae | 1064 | } |
d85cdccb OG |
1065 | |
1066 | static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv, | |
1067 | struct mlx5e_tc_flow *flow) | |
1068 | { | |
1069 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
d7e75a32 | 1070 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
5dbe906f | 1071 | struct mlx5_esw_flow_attr slow_attr; |
f493f155 | 1072 | int out_index; |
d85cdccb | 1073 | |
ef06c9ee | 1074 | if (flow->flags & MLX5E_TC_FLOW_NOT_READY) { |
b4a23329 | 1075 | remove_unready_flow(flow); |
ef06c9ee RD |
1076 | kvfree(attr->parse_attr); |
1077 | return; | |
1078 | } | |
1079 | ||
5dbe906f PB |
1080 | if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { |
1081 | if (flow->flags & MLX5E_TC_FLOW_SLOW) | |
1082 | mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr); | |
1083 | else | |
1084 | mlx5e_tc_unoffload_fdb_rules(esw, flow, attr); | |
1085 | } | |
d85cdccb | 1086 | |
513f8f7f | 1087 | mlx5_eswitch_del_vlan_action(esw, attr); |
d85cdccb | 1088 | |
f493f155 | 1089 | for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) |
8c4dc42b EB |
1090 | if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) |
1091 | mlx5e_detach_encap(priv, flow, out_index); | |
f493f155 | 1092 | kvfree(attr->parse_attr); |
d7e75a32 | 1093 | |
513f8f7f | 1094 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
1a9527bb | 1095 | mlx5e_detach_mod_hdr(priv, flow); |
b8aee822 MB |
1096 | |
1097 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) | |
f9392795 | 1098 | mlx5_fc_destroy(attr->counter_dev, attr->counter); |
d85cdccb OG |
1099 | } |
1100 | ||
232c0013 HHZ |
1101 | void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv, |
1102 | struct mlx5e_encap_entry *e) | |
1103 | { | |
3c37745e | 1104 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
5dbe906f | 1105 | struct mlx5_esw_flow_attr slow_attr, *esw_attr; |
6d2a3ed0 OG |
1106 | struct mlx5_flow_handle *rule; |
1107 | struct mlx5_flow_spec *spec; | |
79baaec7 | 1108 | struct encap_flow_item *efi; |
232c0013 HHZ |
1109 | struct mlx5e_tc_flow *flow; |
1110 | int err; | |
1111 | ||
54c177ca OS |
1112 | err = mlx5_packet_reformat_alloc(priv->mdev, |
1113 | e->reformat_type, | |
60786f09 | 1114 | e->encap_size, e->encap_header, |
31ca3648 | 1115 | MLX5_FLOW_NAMESPACE_FDB, |
60786f09 | 1116 | &e->encap_id); |
232c0013 HHZ |
1117 | if (err) { |
1118 | mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n", | |
1119 | err); | |
1120 | return; | |
1121 | } | |
1122 | e->flags |= MLX5_ENCAP_ENTRY_VALID; | |
f6dfb4c3 | 1123 | mlx5e_rep_queue_neigh_stats_work(priv); |
232c0013 | 1124 | |
79baaec7 | 1125 | list_for_each_entry(efi, &e->flows, list) { |
8c4dc42b EB |
1126 | bool all_flow_encaps_valid = true; |
1127 | int i; | |
1128 | ||
79baaec7 | 1129 | flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]); |
3c37745e | 1130 | esw_attr = flow->esw_attr; |
6d2a3ed0 OG |
1131 | spec = &esw_attr->parse_attr->spec; |
1132 | ||
8c4dc42b EB |
1133 | esw_attr->dests[efi->index].encap_id = e->encap_id; |
1134 | esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID; | |
1135 | /* Flow can be associated with multiple encap entries. | |
1136 | * Before offloading the flow verify that all of them have | |
1137 | * a valid neighbour. | |
1138 | */ | |
1139 | for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) { | |
1140 | if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)) | |
1141 | continue; | |
1142 | if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) { | |
1143 | all_flow_encaps_valid = false; | |
1144 | break; | |
1145 | } | |
1146 | } | |
1147 | /* Do not offload flows with unresolved neighbors */ | |
1148 | if (!all_flow_encaps_valid) | |
1149 | continue; | |
5dbe906f | 1150 | /* update from slow path rule to encap rule */ |
6d2a3ed0 OG |
1151 | rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr); |
1152 | if (IS_ERR(rule)) { | |
1153 | err = PTR_ERR(rule); | |
232c0013 HHZ |
1154 | mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n", |
1155 | err); | |
1156 | continue; | |
1157 | } | |
5dbe906f PB |
1158 | |
1159 | mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr); | |
1160 | flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */ | |
6d2a3ed0 | 1161 | flow->rule[0] = rule; |
232c0013 HHZ |
1162 | } |
1163 | } | |
1164 | ||
1165 | void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv, | |
1166 | struct mlx5e_encap_entry *e) | |
1167 | { | |
3c37745e | 1168 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
5dbe906f PB |
1169 | struct mlx5_esw_flow_attr slow_attr; |
1170 | struct mlx5_flow_handle *rule; | |
1171 | struct mlx5_flow_spec *spec; | |
79baaec7 | 1172 | struct encap_flow_item *efi; |
232c0013 | 1173 | struct mlx5e_tc_flow *flow; |
5dbe906f | 1174 | int err; |
232c0013 | 1175 | |
79baaec7 EB |
1176 | list_for_each_entry(efi, &e->flows, list) { |
1177 | flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]); | |
5dbe906f PB |
1178 | spec = &flow->esw_attr->parse_attr->spec; |
1179 | ||
1180 | /* update from encap rule to slow path rule */ | |
1181 | rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr); | |
8c4dc42b EB |
1182 | /* mark the flow's encap dest as non-valid */ |
1183 | flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID; | |
5dbe906f PB |
1184 | |
1185 | if (IS_ERR(rule)) { | |
1186 | err = PTR_ERR(rule); | |
1187 | mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n", | |
1188 | err); | |
1189 | continue; | |
1190 | } | |
1191 | ||
1192 | mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr); | |
1193 | flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */ | |
1194 | flow->rule[0] = rule; | |
232c0013 HHZ |
1195 | } |
1196 | ||
61c806da OG |
1197 | /* we know that the encap is valid */ |
1198 | e->flags &= ~MLX5_ENCAP_ENTRY_VALID; | |
1199 | mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id); | |
232c0013 HHZ |
1200 | } |
1201 | ||
b8aee822 MB |
1202 | static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow) |
1203 | { | |
1204 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) | |
1205 | return flow->esw_attr->counter; | |
1206 | else | |
1207 | return flow->nic_attr->counter; | |
1208 | } | |
1209 | ||
f6dfb4c3 HHZ |
1210 | void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe) |
1211 | { | |
1212 | struct mlx5e_neigh *m_neigh = &nhe->m_neigh; | |
1213 | u64 bytes, packets, lastuse = 0; | |
1214 | struct mlx5e_tc_flow *flow; | |
1215 | struct mlx5e_encap_entry *e; | |
1216 | struct mlx5_fc *counter; | |
1217 | struct neigh_table *tbl; | |
1218 | bool neigh_used = false; | |
1219 | struct neighbour *n; | |
1220 | ||
1221 | if (m_neigh->family == AF_INET) | |
1222 | tbl = &arp_tbl; | |
1223 | #if IS_ENABLED(CONFIG_IPV6) | |
1224 | else if (m_neigh->family == AF_INET6) | |
423c9db2 | 1225 | tbl = &nd_tbl; |
f6dfb4c3 HHZ |
1226 | #endif |
1227 | else | |
1228 | return; | |
1229 | ||
1230 | list_for_each_entry(e, &nhe->encap_list, encap_list) { | |
79baaec7 | 1231 | struct encap_flow_item *efi; |
f6dfb4c3 HHZ |
1232 | if (!(e->flags & MLX5_ENCAP_ENTRY_VALID)) |
1233 | continue; | |
79baaec7 EB |
1234 | list_for_each_entry(efi, &e->flows, list) { |
1235 | flow = container_of(efi, struct mlx5e_tc_flow, | |
1236 | encaps[efi->index]); | |
f6dfb4c3 | 1237 | if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { |
b8aee822 | 1238 | counter = mlx5e_tc_get_counter(flow); |
f6dfb4c3 HHZ |
1239 | mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse); |
1240 | if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) { | |
1241 | neigh_used = true; | |
1242 | break; | |
1243 | } | |
1244 | } | |
1245 | } | |
e36d4810 RD |
1246 | if (neigh_used) |
1247 | break; | |
f6dfb4c3 HHZ |
1248 | } |
1249 | ||
1250 | if (neigh_used) { | |
1251 | nhe->reported_lastuse = jiffies; | |
1252 | ||
1253 | /* find the relevant neigh according to the cached device and | |
1254 | * dst ip pair | |
1255 | */ | |
1256 | n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev); | |
c7f7ba8d | 1257 | if (!n) |
f6dfb4c3 | 1258 | return; |
f6dfb4c3 HHZ |
1259 | |
1260 | neigh_event_send(n, NULL); | |
1261 | neigh_release(n); | |
1262 | } | |
1263 | } | |
1264 | ||
d85cdccb | 1265 | static void mlx5e_detach_encap(struct mlx5e_priv *priv, |
8c4dc42b | 1266 | struct mlx5e_tc_flow *flow, int out_index) |
d85cdccb | 1267 | { |
8c4dc42b | 1268 | struct list_head *next = flow->encaps[out_index].list.next; |
5067b602 | 1269 | |
8c4dc42b | 1270 | list_del(&flow->encaps[out_index].list); |
5067b602 | 1271 | if (list_empty(next)) { |
c1ae1152 | 1272 | struct mlx5e_encap_entry *e; |
5067b602 | 1273 | |
c1ae1152 | 1274 | e = list_entry(next, struct mlx5e_encap_entry, flows); |
232c0013 HHZ |
1275 | mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e); |
1276 | ||
1277 | if (e->flags & MLX5_ENCAP_ENTRY_VALID) | |
60786f09 | 1278 | mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id); |
232c0013 | 1279 | |
cdc5a7f3 | 1280 | hash_del_rcu(&e->encap_hlist); |
232c0013 | 1281 | kfree(e->encap_header); |
5067b602 RD |
1282 | kfree(e); |
1283 | } | |
1284 | } | |
1285 | ||
04de7dda RD |
1286 | static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) |
1287 | { | |
1288 | struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch; | |
1289 | ||
1290 | if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) || | |
1291 | !(flow->flags & MLX5E_TC_FLOW_DUP)) | |
1292 | return; | |
1293 | ||
1294 | mutex_lock(&esw->offloads.peer_mutex); | |
1295 | list_del(&flow->peer); | |
1296 | mutex_unlock(&esw->offloads.peer_mutex); | |
1297 | ||
1298 | flow->flags &= ~MLX5E_TC_FLOW_DUP; | |
1299 | ||
1300 | mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow); | |
1301 | kvfree(flow->peer_flow); | |
1302 | flow->peer_flow = NULL; | |
1303 | } | |
1304 | ||
1305 | static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow) | |
1306 | { | |
1307 | struct mlx5_core_dev *dev = flow->priv->mdev; | |
1308 | struct mlx5_devcom *devcom = dev->priv.devcom; | |
1309 | struct mlx5_eswitch *peer_esw; | |
1310 | ||
1311 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
1312 | if (!peer_esw) | |
1313 | return; | |
1314 | ||
1315 | __mlx5e_tc_del_fdb_peer_flow(flow); | |
1316 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
1317 | } | |
1318 | ||
e8f887ac | 1319 | static void mlx5e_tc_del_flow(struct mlx5e_priv *priv, |
961e8979 | 1320 | struct mlx5e_tc_flow *flow) |
e8f887ac | 1321 | { |
04de7dda RD |
1322 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { |
1323 | mlx5e_tc_del_fdb_peer_flow(flow); | |
d85cdccb | 1324 | mlx5e_tc_del_fdb_flow(priv, flow); |
04de7dda | 1325 | } else { |
d85cdccb | 1326 | mlx5e_tc_del_nic_flow(priv, flow); |
04de7dda | 1327 | } |
e8f887ac AV |
1328 | } |
1329 | ||
bbd00f7e HHZ |
1330 | |
1331 | static int parse_tunnel_attr(struct mlx5e_priv *priv, | |
1332 | struct mlx5_flow_spec *spec, | |
54c177ca | 1333 | struct tc_cls_flower_offload *f, |
6363651d | 1334 | struct net_device *filter_dev, u8 *match_level) |
bbd00f7e | 1335 | { |
e98bedf5 | 1336 | struct netlink_ext_ack *extack = f->common.extack; |
bbd00f7e HHZ |
1337 | void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
1338 | outer_headers); | |
1339 | void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1340 | outer_headers); | |
8f256622 | 1341 | struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); |
8f256622 | 1342 | int err; |
2e72eb43 | 1343 | |
101f4de9 | 1344 | err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f, |
6363651d | 1345 | headers_c, headers_v, match_level); |
54c177ca OS |
1346 | if (err) { |
1347 | NL_SET_ERR_MSG_MOD(extack, | |
1348 | "failed to parse tunnel attributes"); | |
101f4de9 | 1349 | return err; |
bbd00f7e HHZ |
1350 | } |
1351 | ||
d1bda7ee | 1352 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS)) { |
8f256622 PNA |
1353 | struct flow_match_ipv4_addrs match; |
1354 | ||
1355 | flow_rule_match_enc_ipv4_addrs(rule, &match); | |
bbd00f7e HHZ |
1356 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
1357 | src_ipv4_src_ipv6.ipv4_layout.ipv4, | |
8f256622 | 1358 | ntohl(match.mask->src)); |
bbd00f7e HHZ |
1359 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
1360 | src_ipv4_src_ipv6.ipv4_layout.ipv4, | |
8f256622 | 1361 | ntohl(match.key->src)); |
bbd00f7e HHZ |
1362 | |
1363 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
1364 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4, | |
8f256622 | 1365 | ntohl(match.mask->dst)); |
bbd00f7e HHZ |
1366 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
1367 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4, | |
8f256622 | 1368 | ntohl(match.key->dst)); |
bbd00f7e | 1369 | |
2e72eb43 OG |
1370 | MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype); |
1371 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP); | |
d1bda7ee | 1372 | } else if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS)) { |
8f256622 | 1373 | struct flow_match_ipv6_addrs match; |
19f44401 | 1374 | |
8f256622 | 1375 | flow_rule_match_enc_ipv6_addrs(rule, &match); |
19f44401 OG |
1376 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
1377 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1378 | &match.mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); |
19f44401 OG |
1379 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1380 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1381 | &match.key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); |
19f44401 OG |
1382 | |
1383 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, | |
1384 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1385 | &match.mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); |
19f44401 OG |
1386 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1387 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1388 | &match.key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6)); |
19f44401 OG |
1389 | |
1390 | MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype); | |
1391 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6); | |
2e72eb43 | 1392 | } |
bbd00f7e | 1393 | |
8f256622 PNA |
1394 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) { |
1395 | struct flow_match_ip match; | |
bcef735c | 1396 | |
8f256622 PNA |
1397 | flow_rule_match_enc_ip(rule, &match); |
1398 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, | |
1399 | match.mask->tos & 0x3); | |
1400 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, | |
1401 | match.key->tos & 0x3); | |
bcef735c | 1402 | |
8f256622 PNA |
1403 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, |
1404 | match.mask->tos >> 2); | |
1405 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, | |
1406 | match.key->tos >> 2); | |
bcef735c | 1407 | |
8f256622 PNA |
1408 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, |
1409 | match.mask->ttl); | |
1410 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, | |
1411 | match.key->ttl); | |
e98bedf5 | 1412 | |
8f256622 | 1413 | if (match.mask->ttl && |
e98bedf5 EB |
1414 | !MLX5_CAP_ESW_FLOWTABLE_FDB |
1415 | (priv->mdev, | |
1416 | ft_field_support.outer_ipv4_ttl)) { | |
1417 | NL_SET_ERR_MSG_MOD(extack, | |
1418 | "Matching on TTL is not supported"); | |
1419 | return -EOPNOTSUPP; | |
1420 | } | |
1421 | ||
bcef735c OG |
1422 | } |
1423 | ||
bbd00f7e HHZ |
1424 | /* Enforce DMAC when offloading incoming tunneled flows. |
1425 | * Flow counters require a match on the DMAC. | |
1426 | */ | |
1427 | MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16); | |
1428 | MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0); | |
1429 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, | |
1430 | dmac_47_16), priv->netdev->dev_addr); | |
1431 | ||
1432 | /* let software handle IP fragments */ | |
1433 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1); | |
1434 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
8377629e EB |
1439 | static void *get_match_headers_criteria(u32 flags, |
1440 | struct mlx5_flow_spec *spec) | |
1441 | { | |
1442 | return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? | |
1443 | MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1444 | inner_headers) : | |
1445 | MLX5_ADDR_OF(fte_match_param, spec->match_criteria, | |
1446 | outer_headers); | |
1447 | } | |
1448 | ||
1449 | static void *get_match_headers_value(u32 flags, | |
1450 | struct mlx5_flow_spec *spec) | |
1451 | { | |
1452 | return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ? | |
1453 | MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1454 | inner_headers) : | |
1455 | MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1456 | outer_headers); | |
1457 | } | |
1458 | ||
de0af0bf RD |
1459 | static int __parse_cls_flower(struct mlx5e_priv *priv, |
1460 | struct mlx5_flow_spec *spec, | |
1461 | struct tc_cls_flower_offload *f, | |
54c177ca | 1462 | struct net_device *filter_dev, |
6363651d | 1463 | u8 *match_level, u8 *tunnel_match_level) |
e3a2b7ed | 1464 | { |
e98bedf5 | 1465 | struct netlink_ext_ack *extack = f->common.extack; |
c5bb1730 MG |
1466 | void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
1467 | outer_headers); | |
1468 | void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1469 | outer_headers); | |
699e96dd JL |
1470 | void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, |
1471 | misc_parameters); | |
1472 | void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, | |
1473 | misc_parameters); | |
8f256622 PNA |
1474 | struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); |
1475 | struct flow_dissector *dissector = rule->match.dissector; | |
e3a2b7ed AV |
1476 | u16 addr_type = 0; |
1477 | u8 ip_proto = 0; | |
1478 | ||
d708f902 | 1479 | *match_level = MLX5_MATCH_NONE; |
de0af0bf | 1480 | |
8f256622 | 1481 | if (dissector->used_keys & |
e3a2b7ed AV |
1482 | ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | |
1483 | BIT(FLOW_DISSECTOR_KEY_BASIC) | | |
1484 | BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | | |
095b6cfd | 1485 | BIT(FLOW_DISSECTOR_KEY_VLAN) | |
699e96dd | 1486 | BIT(FLOW_DISSECTOR_KEY_CVLAN) | |
e3a2b7ed AV |
1487 | BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | |
1488 | BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | | |
bbd00f7e HHZ |
1489 | BIT(FLOW_DISSECTOR_KEY_PORTS) | |
1490 | BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) | | |
1491 | BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) | | |
1492 | BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) | | |
1493 | BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) | | |
e77834ec | 1494 | BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) | |
fd7da28b | 1495 | BIT(FLOW_DISSECTOR_KEY_TCP) | |
bcef735c OG |
1496 | BIT(FLOW_DISSECTOR_KEY_IP) | |
1497 | BIT(FLOW_DISSECTOR_KEY_ENC_IP))) { | |
e98bedf5 | 1498 | NL_SET_ERR_MSG_MOD(extack, "Unsupported key"); |
e3a2b7ed | 1499 | netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n", |
8f256622 | 1500 | dissector->used_keys); |
e3a2b7ed AV |
1501 | return -EOPNOTSUPP; |
1502 | } | |
1503 | ||
d1bda7ee TZ |
1504 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) || |
1505 | flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) || | |
1506 | flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID) || | |
1507 | flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_PORTS)) { | |
1508 | if (parse_tunnel_attr(priv, spec, f, filter_dev, tunnel_match_level)) | |
bbd00f7e | 1509 | return -EOPNOTSUPP; |
bbd00f7e HHZ |
1510 | |
1511 | /* In decap flow, header pointers should point to the inner | |
1512 | * headers, outer header were already set by parse_tunnel_attr | |
1513 | */ | |
8377629e EB |
1514 | headers_c = get_match_headers_criteria(MLX5_FLOW_CONTEXT_ACTION_DECAP, |
1515 | spec); | |
1516 | headers_v = get_match_headers_value(MLX5_FLOW_CONTEXT_ACTION_DECAP, | |
1517 | spec); | |
bbd00f7e HHZ |
1518 | } |
1519 | ||
8f256622 PNA |
1520 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { |
1521 | struct flow_match_basic match; | |
1522 | ||
1523 | flow_rule_match_basic(rule, &match); | |
d3a80bb5 | 1524 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype, |
8f256622 | 1525 | ntohs(match.mask->n_proto)); |
d3a80bb5 | 1526 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, |
8f256622 | 1527 | ntohs(match.key->n_proto)); |
e3a2b7ed | 1528 | |
8f256622 | 1529 | if (match.mask->n_proto) |
d708f902 | 1530 | *match_level = MLX5_MATCH_L2; |
e3a2b7ed | 1531 | } |
35a605db EB |
1532 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) || |
1533 | is_vlan_dev(filter_dev)) { | |
1534 | struct flow_dissector_key_vlan filter_dev_mask; | |
1535 | struct flow_dissector_key_vlan filter_dev_key; | |
8f256622 PNA |
1536 | struct flow_match_vlan match; |
1537 | ||
35a605db EB |
1538 | if (is_vlan_dev(filter_dev)) { |
1539 | match.key = &filter_dev_key; | |
1540 | match.key->vlan_id = vlan_dev_vlan_id(filter_dev); | |
1541 | match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev); | |
1542 | match.key->vlan_priority = 0; | |
1543 | match.mask = &filter_dev_mask; | |
1544 | memset(match.mask, 0xff, sizeof(*match.mask)); | |
1545 | match.mask->vlan_priority = 0; | |
1546 | } else { | |
1547 | flow_rule_match_vlan(rule, &match); | |
1548 | } | |
8f256622 PNA |
1549 | if (match.mask->vlan_id || |
1550 | match.mask->vlan_priority || | |
1551 | match.mask->vlan_tpid) { | |
1552 | if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { | |
699e96dd JL |
1553 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, |
1554 | svlan_tag, 1); | |
1555 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
1556 | svlan_tag, 1); | |
1557 | } else { | |
1558 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
1559 | cvlan_tag, 1); | |
1560 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, | |
1561 | cvlan_tag, 1); | |
1562 | } | |
095b6cfd | 1563 | |
8f256622 PNA |
1564 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, |
1565 | match.mask->vlan_id); | |
1566 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, | |
1567 | match.key->vlan_id); | |
358d79a4 | 1568 | |
8f256622 PNA |
1569 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, |
1570 | match.mask->vlan_priority); | |
1571 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, | |
1572 | match.key->vlan_priority); | |
54782900 | 1573 | |
d708f902 | 1574 | *match_level = MLX5_MATCH_L2; |
54782900 | 1575 | } |
d3a80bb5 | 1576 | } else if (*match_level != MLX5_MATCH_NONE) { |
cee26487 JL |
1577 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1); |
1578 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1); | |
d3a80bb5 | 1579 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
1580 | } |
1581 | ||
8f256622 PNA |
1582 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) { |
1583 | struct flow_match_vlan match; | |
1584 | ||
12d5cbf8 | 1585 | flow_rule_match_cvlan(rule, &match); |
8f256622 PNA |
1586 | if (match.mask->vlan_id || |
1587 | match.mask->vlan_priority || | |
1588 | match.mask->vlan_tpid) { | |
1589 | if (match.key->vlan_tpid == htons(ETH_P_8021AD)) { | |
699e96dd JL |
1590 | MLX5_SET(fte_match_set_misc, misc_c, |
1591 | outer_second_svlan_tag, 1); | |
1592 | MLX5_SET(fte_match_set_misc, misc_v, | |
1593 | outer_second_svlan_tag, 1); | |
1594 | } else { | |
1595 | MLX5_SET(fte_match_set_misc, misc_c, | |
1596 | outer_second_cvlan_tag, 1); | |
1597 | MLX5_SET(fte_match_set_misc, misc_v, | |
1598 | outer_second_cvlan_tag, 1); | |
1599 | } | |
1600 | ||
1601 | MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid, | |
8f256622 | 1602 | match.mask->vlan_id); |
699e96dd | 1603 | MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid, |
8f256622 | 1604 | match.key->vlan_id); |
699e96dd | 1605 | MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio, |
8f256622 | 1606 | match.mask->vlan_priority); |
699e96dd | 1607 | MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio, |
8f256622 | 1608 | match.key->vlan_priority); |
699e96dd JL |
1609 | |
1610 | *match_level = MLX5_MATCH_L2; | |
1611 | } | |
1612 | } | |
1613 | ||
8f256622 PNA |
1614 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
1615 | struct flow_match_eth_addrs match; | |
54782900 | 1616 | |
8f256622 | 1617 | flow_rule_match_eth_addrs(rule, &match); |
d3a80bb5 OG |
1618 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
1619 | dmac_47_16), | |
8f256622 | 1620 | match.mask->dst); |
d3a80bb5 OG |
1621 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1622 | dmac_47_16), | |
8f256622 | 1623 | match.key->dst); |
d3a80bb5 OG |
1624 | |
1625 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, | |
1626 | smac_47_16), | |
8f256622 | 1627 | match.mask->src); |
d3a80bb5 OG |
1628 | ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1629 | smac_47_16), | |
8f256622 | 1630 | match.key->src); |
d3a80bb5 | 1631 | |
8f256622 PNA |
1632 | if (!is_zero_ether_addr(match.mask->src) || |
1633 | !is_zero_ether_addr(match.mask->dst)) | |
d708f902 | 1634 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
1635 | } |
1636 | ||
8f256622 PNA |
1637 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { |
1638 | struct flow_match_control match; | |
54782900 | 1639 | |
8f256622 PNA |
1640 | flow_rule_match_control(rule, &match); |
1641 | addr_type = match.key->addr_type; | |
54782900 OG |
1642 | |
1643 | /* the HW doesn't support frag first/later */ | |
8f256622 | 1644 | if (match.mask->flags & FLOW_DIS_FIRST_FRAG) |
54782900 OG |
1645 | return -EOPNOTSUPP; |
1646 | ||
8f256622 | 1647 | if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) { |
54782900 OG |
1648 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1); |
1649 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, | |
8f256622 | 1650 | match.key->flags & FLOW_DIS_IS_FRAGMENT); |
54782900 OG |
1651 | |
1652 | /* the HW doesn't need L3 inline to match on frag=no */ | |
8f256622 | 1653 | if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT)) |
83621b7d | 1654 | *match_level = MLX5_MATCH_L2; |
54782900 OG |
1655 | /* *** L2 attributes parsing up to here *** */ |
1656 | else | |
83621b7d | 1657 | *match_level = MLX5_MATCH_L3; |
095b6cfd OG |
1658 | } |
1659 | } | |
1660 | ||
8f256622 PNA |
1661 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { |
1662 | struct flow_match_basic match; | |
1663 | ||
1664 | flow_rule_match_basic(rule, &match); | |
1665 | ip_proto = match.key->ip_proto; | |
54782900 OG |
1666 | |
1667 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol, | |
8f256622 | 1668 | match.mask->ip_proto); |
54782900 | 1669 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, |
8f256622 | 1670 | match.key->ip_proto); |
54782900 | 1671 | |
8f256622 | 1672 | if (match.mask->ip_proto) |
d708f902 | 1673 | *match_level = MLX5_MATCH_L3; |
54782900 OG |
1674 | } |
1675 | ||
e3a2b7ed | 1676 | if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { |
8f256622 | 1677 | struct flow_match_ipv4_addrs match; |
e3a2b7ed | 1678 | |
8f256622 | 1679 | flow_rule_match_ipv4_addrs(rule, &match); |
e3a2b7ed AV |
1680 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
1681 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
8f256622 | 1682 | &match.mask->src, sizeof(match.mask->src)); |
e3a2b7ed AV |
1683 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1684 | src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
8f256622 | 1685 | &match.key->src, sizeof(match.key->src)); |
e3a2b7ed AV |
1686 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
1687 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
8f256622 | 1688 | &match.mask->dst, sizeof(match.mask->dst)); |
e3a2b7ed AV |
1689 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1690 | dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
8f256622 | 1691 | &match.key->dst, sizeof(match.key->dst)); |
de0af0bf | 1692 | |
8f256622 | 1693 | if (match.mask->src || match.mask->dst) |
d708f902 | 1694 | *match_level = MLX5_MATCH_L3; |
e3a2b7ed AV |
1695 | } |
1696 | ||
1697 | if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { | |
8f256622 | 1698 | struct flow_match_ipv6_addrs match; |
e3a2b7ed | 1699 | |
8f256622 | 1700 | flow_rule_match_ipv6_addrs(rule, &match); |
e3a2b7ed AV |
1701 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, |
1702 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1703 | &match.mask->src, sizeof(match.mask->src)); |
e3a2b7ed AV |
1704 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1705 | src_ipv4_src_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1706 | &match.key->src, sizeof(match.key->src)); |
e3a2b7ed AV |
1707 | |
1708 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c, | |
1709 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1710 | &match.mask->dst, sizeof(match.mask->dst)); |
e3a2b7ed AV |
1711 | memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, |
1712 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6), | |
8f256622 | 1713 | &match.key->dst, sizeof(match.key->dst)); |
de0af0bf | 1714 | |
8f256622 PNA |
1715 | if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY || |
1716 | ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY) | |
d708f902 | 1717 | *match_level = MLX5_MATCH_L3; |
e3a2b7ed AV |
1718 | } |
1719 | ||
8f256622 PNA |
1720 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) { |
1721 | struct flow_match_ip match; | |
1f97a526 | 1722 | |
8f256622 PNA |
1723 | flow_rule_match_ip(rule, &match); |
1724 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, | |
1725 | match.mask->tos & 0x3); | |
1726 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, | |
1727 | match.key->tos & 0x3); | |
1f97a526 | 1728 | |
8f256622 PNA |
1729 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, |
1730 | match.mask->tos >> 2); | |
1731 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, | |
1732 | match.key->tos >> 2); | |
1f97a526 | 1733 | |
8f256622 PNA |
1734 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, |
1735 | match.mask->ttl); | |
1736 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, | |
1737 | match.key->ttl); | |
1f97a526 | 1738 | |
8f256622 | 1739 | if (match.mask->ttl && |
a8ade55f | 1740 | !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, |
e98bedf5 EB |
1741 | ft_field_support.outer_ipv4_ttl)) { |
1742 | NL_SET_ERR_MSG_MOD(extack, | |
1743 | "Matching on TTL is not supported"); | |
1f97a526 | 1744 | return -EOPNOTSUPP; |
e98bedf5 | 1745 | } |
a8ade55f | 1746 | |
8f256622 | 1747 | if (match.mask->tos || match.mask->ttl) |
d708f902 | 1748 | *match_level = MLX5_MATCH_L3; |
1f97a526 OG |
1749 | } |
1750 | ||
54782900 OG |
1751 | /* *** L3 attributes parsing up to here *** */ |
1752 | ||
8f256622 PNA |
1753 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { |
1754 | struct flow_match_ports match; | |
1755 | ||
1756 | flow_rule_match_ports(rule, &match); | |
e3a2b7ed AV |
1757 | switch (ip_proto) { |
1758 | case IPPROTO_TCP: | |
1759 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 1760 | tcp_sport, ntohs(match.mask->src)); |
e3a2b7ed | 1761 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 1762 | tcp_sport, ntohs(match.key->src)); |
e3a2b7ed AV |
1763 | |
1764 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 1765 | tcp_dport, ntohs(match.mask->dst)); |
e3a2b7ed | 1766 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 1767 | tcp_dport, ntohs(match.key->dst)); |
e3a2b7ed AV |
1768 | break; |
1769 | ||
1770 | case IPPROTO_UDP: | |
1771 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 1772 | udp_sport, ntohs(match.mask->src)); |
e3a2b7ed | 1773 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 1774 | udp_sport, ntohs(match.key->src)); |
e3a2b7ed AV |
1775 | |
1776 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, | |
8f256622 | 1777 | udp_dport, ntohs(match.mask->dst)); |
e3a2b7ed | 1778 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, |
8f256622 | 1779 | udp_dport, ntohs(match.key->dst)); |
e3a2b7ed AV |
1780 | break; |
1781 | default: | |
e98bedf5 EB |
1782 | NL_SET_ERR_MSG_MOD(extack, |
1783 | "Only UDP and TCP transports are supported for L4 matching"); | |
e3a2b7ed AV |
1784 | netdev_err(priv->netdev, |
1785 | "Only UDP and TCP transport are supported\n"); | |
1786 | return -EINVAL; | |
1787 | } | |
de0af0bf | 1788 | |
8f256622 | 1789 | if (match.mask->src || match.mask->dst) |
d708f902 | 1790 | *match_level = MLX5_MATCH_L4; |
e3a2b7ed AV |
1791 | } |
1792 | ||
8f256622 PNA |
1793 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) { |
1794 | struct flow_match_tcp match; | |
e77834ec | 1795 | |
8f256622 | 1796 | flow_rule_match_tcp(rule, &match); |
e77834ec | 1797 | MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags, |
8f256622 | 1798 | ntohs(match.mask->flags)); |
e77834ec | 1799 | MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags, |
8f256622 | 1800 | ntohs(match.key->flags)); |
e77834ec | 1801 | |
8f256622 | 1802 | if (match.mask->flags) |
d708f902 | 1803 | *match_level = MLX5_MATCH_L4; |
e77834ec OG |
1804 | } |
1805 | ||
e3a2b7ed AV |
1806 | return 0; |
1807 | } | |
1808 | ||
de0af0bf | 1809 | static int parse_cls_flower(struct mlx5e_priv *priv, |
65ba8fb7 | 1810 | struct mlx5e_tc_flow *flow, |
de0af0bf | 1811 | struct mlx5_flow_spec *spec, |
54c177ca OS |
1812 | struct tc_cls_flower_offload *f, |
1813 | struct net_device *filter_dev) | |
de0af0bf | 1814 | { |
e98bedf5 | 1815 | struct netlink_ext_ack *extack = f->common.extack; |
de0af0bf RD |
1816 | struct mlx5_core_dev *dev = priv->mdev; |
1817 | struct mlx5_eswitch *esw = dev->priv.eswitch; | |
1d447a39 | 1818 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
6363651d | 1819 | u8 match_level, tunnel_match_level = MLX5_MATCH_NONE; |
1d447a39 | 1820 | struct mlx5_eswitch_rep *rep; |
de0af0bf RD |
1821 | int err; |
1822 | ||
6363651d | 1823 | err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level, &tunnel_match_level); |
de0af0bf | 1824 | |
1d447a39 SM |
1825 | if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) { |
1826 | rep = rpriv->rep; | |
b05af6aa | 1827 | if (rep->vport != MLX5_VPORT_UPLINK && |
1d447a39 | 1828 | (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE && |
d708f902 | 1829 | esw->offloads.inline_mode < match_level)) { |
e98bedf5 EB |
1830 | NL_SET_ERR_MSG_MOD(extack, |
1831 | "Flow is not offloaded due to min inline setting"); | |
de0af0bf RD |
1832 | netdev_warn(priv->netdev, |
1833 | "Flow is not offloaded due to min inline setting, required %d actual %d\n", | |
d708f902 | 1834 | match_level, esw->offloads.inline_mode); |
de0af0bf RD |
1835 | return -EOPNOTSUPP; |
1836 | } | |
1837 | } | |
1838 | ||
6363651d | 1839 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) { |
38aa51c1 | 1840 | flow->esw_attr->match_level = match_level; |
6363651d OG |
1841 | flow->esw_attr->tunnel_match_level = tunnel_match_level; |
1842 | } else { | |
38aa51c1 | 1843 | flow->nic_attr->match_level = match_level; |
6363651d | 1844 | } |
38aa51c1 | 1845 | |
de0af0bf RD |
1846 | return err; |
1847 | } | |
1848 | ||
d79b6df6 OG |
1849 | struct pedit_headers { |
1850 | struct ethhdr eth; | |
0eb69bb9 | 1851 | struct vlan_hdr vlan; |
d79b6df6 OG |
1852 | struct iphdr ip4; |
1853 | struct ipv6hdr ip6; | |
1854 | struct tcphdr tcp; | |
1855 | struct udphdr udp; | |
1856 | }; | |
1857 | ||
c500c86b PNA |
1858 | struct pedit_headers_action { |
1859 | struct pedit_headers vals; | |
1860 | struct pedit_headers masks; | |
1861 | u32 pedits; | |
1862 | }; | |
1863 | ||
d79b6df6 | 1864 | static int pedit_header_offsets[] = { |
73867881 PNA |
1865 | [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth), |
1866 | [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4), | |
1867 | [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6), | |
1868 | [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp), | |
1869 | [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp), | |
d79b6df6 OG |
1870 | }; |
1871 | ||
1872 | #define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype]) | |
1873 | ||
1874 | static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset, | |
c500c86b | 1875 | struct pedit_headers_action *hdrs) |
d79b6df6 OG |
1876 | { |
1877 | u32 *curr_pmask, *curr_pval; | |
1878 | ||
c500c86b PNA |
1879 | curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset); |
1880 | curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset); | |
d79b6df6 OG |
1881 | |
1882 | if (*curr_pmask & mask) /* disallow acting twice on the same location */ | |
1883 | goto out_err; | |
1884 | ||
1885 | *curr_pmask |= mask; | |
1886 | *curr_pval |= (val & mask); | |
1887 | ||
1888 | return 0; | |
1889 | ||
1890 | out_err: | |
1891 | return -EOPNOTSUPP; | |
1892 | } | |
1893 | ||
1894 | struct mlx5_fields { | |
1895 | u8 field; | |
1896 | u8 size; | |
1897 | u32 offset; | |
27c11b6b | 1898 | u32 match_offset; |
d79b6df6 OG |
1899 | }; |
1900 | ||
27c11b6b EB |
1901 | #define OFFLOAD(fw_field, size, field, off, match_field) \ |
1902 | {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, \ | |
1903 | offsetof(struct pedit_headers, field) + (off), \ | |
1904 | MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)} | |
1905 | ||
2ef86872 EB |
1906 | /* masked values are the same and there are no rewrites that do not have a |
1907 | * match. | |
1908 | */ | |
1909 | #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \ | |
1910 | type matchmaskx = *(type *)(matchmaskp); \ | |
1911 | type matchvalx = *(type *)(matchvalp); \ | |
1912 | type maskx = *(type *)(maskp); \ | |
1913 | type valx = *(type *)(valp); \ | |
1914 | \ | |
1915 | (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \ | |
1916 | matchmaskx)); \ | |
1917 | }) | |
1918 | ||
27c11b6b EB |
1919 | static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp, |
1920 | void *matchmaskp, int size) | |
1921 | { | |
1922 | bool same = false; | |
1923 | ||
1924 | switch (size) { | |
1925 | case sizeof(u8): | |
2ef86872 | 1926 | same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp); |
27c11b6b EB |
1927 | break; |
1928 | case sizeof(u16): | |
2ef86872 | 1929 | same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp); |
27c11b6b EB |
1930 | break; |
1931 | case sizeof(u32): | |
2ef86872 | 1932 | same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp); |
27c11b6b EB |
1933 | break; |
1934 | } | |
1935 | ||
1936 | return same; | |
1937 | } | |
a8e4f0c4 | 1938 | |
d79b6df6 | 1939 | static struct mlx5_fields fields[] = { |
27c11b6b EB |
1940 | OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0, dmac_47_16), |
1941 | OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0, dmac_15_0), | |
1942 | OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0, smac_47_16), | |
1943 | OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0, smac_15_0), | |
1944 | OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0, ethertype), | |
1945 | OFFLOAD(FIRST_VID, 2, vlan.h_vlan_TCI, 0, first_vid), | |
1946 | ||
1947 | OFFLOAD(IP_TTL, 1, ip4.ttl, 0, ttl_hoplimit), | |
1948 | OFFLOAD(SIPV4, 4, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4), | |
1949 | OFFLOAD(DIPV4, 4, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4), | |
1950 | ||
1951 | OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0, | |
1952 | src_ipv4_src_ipv6.ipv6_layout.ipv6[0]), | |
1953 | OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0, | |
1954 | src_ipv4_src_ipv6.ipv6_layout.ipv6[4]), | |
1955 | OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0, | |
1956 | src_ipv4_src_ipv6.ipv6_layout.ipv6[8]), | |
1957 | OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0, | |
1958 | src_ipv4_src_ipv6.ipv6_layout.ipv6[12]), | |
1959 | OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0, | |
1960 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]), | |
1961 | OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0, | |
1962 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]), | |
1963 | OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0, | |
1964 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]), | |
1965 | OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0, | |
1966 | dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]), | |
1967 | OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0, ttl_hoplimit), | |
1968 | ||
1969 | OFFLOAD(TCP_SPORT, 2, tcp.source, 0, tcp_sport), | |
1970 | OFFLOAD(TCP_DPORT, 2, tcp.dest, 0, tcp_dport), | |
1971 | OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5, tcp_flags), | |
1972 | ||
1973 | OFFLOAD(UDP_SPORT, 2, udp.source, 0, udp_sport), | |
1974 | OFFLOAD(UDP_DPORT, 2, udp.dest, 0, udp_dport), | |
d79b6df6 OG |
1975 | }; |
1976 | ||
218d05ce TZ |
1977 | /* On input attr->max_mod_hdr_actions tells how many HW actions can be parsed at |
1978 | * max from the SW pedit action. On success, attr->num_mod_hdr_actions | |
1979 | * says how many HW actions were actually parsed. | |
d79b6df6 | 1980 | */ |
c500c86b | 1981 | static int offload_pedit_fields(struct pedit_headers_action *hdrs, |
e98bedf5 | 1982 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
27c11b6b | 1983 | u32 *action_flags, |
e98bedf5 | 1984 | struct netlink_ext_ack *extack) |
d79b6df6 OG |
1985 | { |
1986 | struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals; | |
27c11b6b EB |
1987 | void *headers_c = get_match_headers_criteria(*action_flags, |
1988 | &parse_attr->spec); | |
1989 | void *headers_v = get_match_headers_value(*action_flags, | |
1990 | &parse_attr->spec); | |
2b64beba | 1991 | int i, action_size, nactions, max_actions, first, last, next_z; |
d79b6df6 | 1992 | void *s_masks_p, *a_masks_p, *vals_p; |
d79b6df6 OG |
1993 | struct mlx5_fields *f; |
1994 | u8 cmd, field_bsize; | |
e3ca4e05 | 1995 | u32 s_mask, a_mask; |
d79b6df6 | 1996 | unsigned long mask; |
2b64beba OG |
1997 | __be32 mask_be32; |
1998 | __be16 mask_be16; | |
d79b6df6 OG |
1999 | void *action; |
2000 | ||
73867881 PNA |
2001 | set_masks = &hdrs[0].masks; |
2002 | add_masks = &hdrs[1].masks; | |
2003 | set_vals = &hdrs[0].vals; | |
2004 | add_vals = &hdrs[1].vals; | |
d79b6df6 OG |
2005 | |
2006 | action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto); | |
218d05ce TZ |
2007 | action = parse_attr->mod_hdr_actions + |
2008 | parse_attr->num_mod_hdr_actions * action_size; | |
2009 | ||
2010 | max_actions = parse_attr->max_mod_hdr_actions; | |
2011 | nactions = parse_attr->num_mod_hdr_actions; | |
d79b6df6 OG |
2012 | |
2013 | for (i = 0; i < ARRAY_SIZE(fields); i++) { | |
27c11b6b EB |
2014 | bool skip; |
2015 | ||
d79b6df6 OG |
2016 | f = &fields[i]; |
2017 | /* avoid seeing bits set from previous iterations */ | |
e3ca4e05 OG |
2018 | s_mask = 0; |
2019 | a_mask = 0; | |
d79b6df6 OG |
2020 | |
2021 | s_masks_p = (void *)set_masks + f->offset; | |
2022 | a_masks_p = (void *)add_masks + f->offset; | |
2023 | ||
2024 | memcpy(&s_mask, s_masks_p, f->size); | |
2025 | memcpy(&a_mask, a_masks_p, f->size); | |
2026 | ||
2027 | if (!s_mask && !a_mask) /* nothing to offload here */ | |
2028 | continue; | |
2029 | ||
2030 | if (s_mask && a_mask) { | |
e98bedf5 EB |
2031 | NL_SET_ERR_MSG_MOD(extack, |
2032 | "can't set and add to the same HW field"); | |
d79b6df6 OG |
2033 | printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field); |
2034 | return -EOPNOTSUPP; | |
2035 | } | |
2036 | ||
2037 | if (nactions == max_actions) { | |
e98bedf5 EB |
2038 | NL_SET_ERR_MSG_MOD(extack, |
2039 | "too many pedit actions, can't offload"); | |
d79b6df6 OG |
2040 | printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions); |
2041 | return -EOPNOTSUPP; | |
2042 | } | |
2043 | ||
27c11b6b | 2044 | skip = false; |
d79b6df6 | 2045 | if (s_mask) { |
27c11b6b EB |
2046 | void *match_mask = headers_c + f->match_offset; |
2047 | void *match_val = headers_v + f->match_offset; | |
2048 | ||
d79b6df6 OG |
2049 | cmd = MLX5_ACTION_TYPE_SET; |
2050 | mask = s_mask; | |
2051 | vals_p = (void *)set_vals + f->offset; | |
27c11b6b EB |
2052 | /* don't rewrite if we have a match on the same value */ |
2053 | if (cmp_val_mask(vals_p, s_masks_p, match_val, | |
2054 | match_mask, f->size)) | |
2055 | skip = true; | |
d79b6df6 OG |
2056 | /* clear to denote we consumed this field */ |
2057 | memset(s_masks_p, 0, f->size); | |
2058 | } else { | |
27c11b6b EB |
2059 | u32 zero = 0; |
2060 | ||
d79b6df6 OG |
2061 | cmd = MLX5_ACTION_TYPE_ADD; |
2062 | mask = a_mask; | |
2063 | vals_p = (void *)add_vals + f->offset; | |
27c11b6b EB |
2064 | /* add 0 is no change */ |
2065 | if (!memcmp(vals_p, &zero, f->size)) | |
2066 | skip = true; | |
d79b6df6 OG |
2067 | /* clear to denote we consumed this field */ |
2068 | memset(a_masks_p, 0, f->size); | |
2069 | } | |
27c11b6b EB |
2070 | if (skip) |
2071 | continue; | |
d79b6df6 | 2072 | |
d79b6df6 | 2073 | field_bsize = f->size * BITS_PER_BYTE; |
e3ca4e05 | 2074 | |
2b64beba OG |
2075 | if (field_bsize == 32) { |
2076 | mask_be32 = *(__be32 *)&mask; | |
2077 | mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32)); | |
2078 | } else if (field_bsize == 16) { | |
2079 | mask_be16 = *(__be16 *)&mask; | |
2080 | mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16)); | |
2081 | } | |
2082 | ||
d79b6df6 | 2083 | first = find_first_bit(&mask, field_bsize); |
2b64beba | 2084 | next_z = find_next_zero_bit(&mask, field_bsize, first); |
d79b6df6 | 2085 | last = find_last_bit(&mask, field_bsize); |
2b64beba | 2086 | if (first < next_z && next_z < last) { |
e98bedf5 EB |
2087 | NL_SET_ERR_MSG_MOD(extack, |
2088 | "rewrite of few sub-fields isn't supported"); | |
2b64beba | 2089 | printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n", |
d79b6df6 OG |
2090 | mask); |
2091 | return -EOPNOTSUPP; | |
2092 | } | |
2093 | ||
2094 | MLX5_SET(set_action_in, action, action_type, cmd); | |
2095 | MLX5_SET(set_action_in, action, field, f->field); | |
2096 | ||
2097 | if (cmd == MLX5_ACTION_TYPE_SET) { | |
2b64beba | 2098 | MLX5_SET(set_action_in, action, offset, first); |
d79b6df6 | 2099 | /* length is num of bits to be written, zero means length of 32 */ |
2b64beba | 2100 | MLX5_SET(set_action_in, action, length, (last - first + 1)); |
d79b6df6 OG |
2101 | } |
2102 | ||
2103 | if (field_bsize == 32) | |
2b64beba | 2104 | MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first); |
d79b6df6 | 2105 | else if (field_bsize == 16) |
2b64beba | 2106 | MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first); |
d79b6df6 | 2107 | else if (field_bsize == 8) |
2b64beba | 2108 | MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first); |
d79b6df6 OG |
2109 | |
2110 | action += action_size; | |
2111 | nactions++; | |
2112 | } | |
2113 | ||
2114 | parse_attr->num_mod_hdr_actions = nactions; | |
2115 | return 0; | |
2116 | } | |
2117 | ||
2cc1cb1d TZ |
2118 | static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev, |
2119 | int namespace) | |
2120 | { | |
2121 | if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */ | |
2122 | return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions); | |
2123 | else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */ | |
2124 | return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions); | |
2125 | } | |
2126 | ||
d79b6df6 | 2127 | static int alloc_mod_hdr_actions(struct mlx5e_priv *priv, |
c500c86b PNA |
2128 | struct pedit_headers_action *hdrs, |
2129 | int namespace, | |
d79b6df6 OG |
2130 | struct mlx5e_tc_flow_parse_attr *parse_attr) |
2131 | { | |
2132 | int nkeys, action_size, max_actions; | |
2133 | ||
c500c86b PNA |
2134 | nkeys = hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits + |
2135 | hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits; | |
d79b6df6 OG |
2136 | action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto); |
2137 | ||
2cc1cb1d | 2138 | max_actions = mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace); |
d79b6df6 OG |
2139 | /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */ |
2140 | max_actions = min(max_actions, nkeys * 16); | |
2141 | ||
2142 | parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL); | |
2143 | if (!parse_attr->mod_hdr_actions) | |
2144 | return -ENOMEM; | |
2145 | ||
218d05ce | 2146 | parse_attr->max_mod_hdr_actions = max_actions; |
d79b6df6 OG |
2147 | return 0; |
2148 | } | |
2149 | ||
2150 | static const struct pedit_headers zero_masks = {}; | |
2151 | ||
2152 | static int parse_tc_pedit_action(struct mlx5e_priv *priv, | |
73867881 | 2153 | const struct flow_action_entry *act, int namespace, |
e98bedf5 | 2154 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
c500c86b | 2155 | struct pedit_headers_action *hdrs, |
e98bedf5 | 2156 | struct netlink_ext_ack *extack) |
d79b6df6 | 2157 | { |
73867881 PNA |
2158 | u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1; |
2159 | int err = -EOPNOTSUPP; | |
d79b6df6 | 2160 | u32 mask, val, offset; |
73867881 | 2161 | u8 htype; |
d79b6df6 | 2162 | |
73867881 PNA |
2163 | htype = act->mangle.htype; |
2164 | err = -EOPNOTSUPP; /* can't be all optimistic */ | |
d79b6df6 | 2165 | |
73867881 PNA |
2166 | if (htype == FLOW_ACT_MANGLE_UNSPEC) { |
2167 | NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded"); | |
2168 | goto out_err; | |
2169 | } | |
d79b6df6 | 2170 | |
2cc1cb1d TZ |
2171 | if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) { |
2172 | NL_SET_ERR_MSG_MOD(extack, | |
2173 | "The pedit offload action is not supported"); | |
2174 | goto out_err; | |
2175 | } | |
2176 | ||
73867881 PNA |
2177 | mask = act->mangle.mask; |
2178 | val = act->mangle.val; | |
2179 | offset = act->mangle.offset; | |
d79b6df6 | 2180 | |
73867881 PNA |
2181 | err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd]); |
2182 | if (err) | |
2183 | goto out_err; | |
c500c86b | 2184 | |
73867881 | 2185 | hdrs[cmd].pedits++; |
d79b6df6 | 2186 | |
c500c86b PNA |
2187 | return 0; |
2188 | out_err: | |
2189 | return err; | |
2190 | } | |
2191 | ||
2192 | static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace, | |
2193 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
2194 | struct pedit_headers_action *hdrs, | |
27c11b6b | 2195 | u32 *action_flags, |
c500c86b PNA |
2196 | struct netlink_ext_ack *extack) |
2197 | { | |
2198 | struct pedit_headers *cmd_masks; | |
2199 | int err; | |
2200 | u8 cmd; | |
2201 | ||
218d05ce | 2202 | if (!parse_attr->mod_hdr_actions) { |
a655fe9f | 2203 | err = alloc_mod_hdr_actions(priv, hdrs, namespace, parse_attr); |
218d05ce TZ |
2204 | if (err) |
2205 | goto out_err; | |
2206 | } | |
d79b6df6 | 2207 | |
27c11b6b | 2208 | err = offload_pedit_fields(hdrs, parse_attr, action_flags, extack); |
d79b6df6 OG |
2209 | if (err < 0) |
2210 | goto out_dealloc_parsed_actions; | |
2211 | ||
2212 | for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) { | |
c500c86b | 2213 | cmd_masks = &hdrs[cmd].masks; |
d79b6df6 | 2214 | if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) { |
e98bedf5 EB |
2215 | NL_SET_ERR_MSG_MOD(extack, |
2216 | "attempt to offload an unsupported field"); | |
b3a433de | 2217 | netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd); |
d79b6df6 OG |
2218 | print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS, |
2219 | 16, 1, cmd_masks, sizeof(zero_masks), true); | |
2220 | err = -EOPNOTSUPP; | |
2221 | goto out_dealloc_parsed_actions; | |
2222 | } | |
2223 | } | |
2224 | ||
2225 | return 0; | |
2226 | ||
2227 | out_dealloc_parsed_actions: | |
2228 | kfree(parse_attr->mod_hdr_actions); | |
2229 | out_err: | |
2230 | return err; | |
2231 | } | |
2232 | ||
e98bedf5 EB |
2233 | static bool csum_offload_supported(struct mlx5e_priv *priv, |
2234 | u32 action, | |
2235 | u32 update_flags, | |
2236 | struct netlink_ext_ack *extack) | |
26c02749 OG |
2237 | { |
2238 | u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP | | |
2239 | TCA_CSUM_UPDATE_FLAG_UDP; | |
2240 | ||
2241 | /* The HW recalcs checksums only if re-writing headers */ | |
2242 | if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) { | |
e98bedf5 EB |
2243 | NL_SET_ERR_MSG_MOD(extack, |
2244 | "TC csum action is only offloaded with pedit"); | |
26c02749 OG |
2245 | netdev_warn(priv->netdev, |
2246 | "TC csum action is only offloaded with pedit\n"); | |
2247 | return false; | |
2248 | } | |
2249 | ||
2250 | if (update_flags & ~prot_flags) { | |
e98bedf5 EB |
2251 | NL_SET_ERR_MSG_MOD(extack, |
2252 | "can't offload TC csum action for some header/s"); | |
26c02749 OG |
2253 | netdev_warn(priv->netdev, |
2254 | "can't offload TC csum action for some header/s - flags %#x\n", | |
2255 | update_flags); | |
2256 | return false; | |
2257 | } | |
2258 | ||
2259 | return true; | |
2260 | } | |
2261 | ||
8998576b DL |
2262 | struct ip_ttl_word { |
2263 | __u8 ttl; | |
2264 | __u8 protocol; | |
2265 | __sum16 check; | |
2266 | }; | |
2267 | ||
2268 | struct ipv6_hoplimit_word { | |
2269 | __be16 payload_len; | |
2270 | __u8 nexthdr; | |
2271 | __u8 hop_limit; | |
2272 | }; | |
2273 | ||
2274 | static bool is_action_keys_supported(const struct flow_action_entry *act) | |
2275 | { | |
2276 | u32 mask, offset; | |
2277 | u8 htype; | |
2278 | ||
2279 | htype = act->mangle.htype; | |
2280 | offset = act->mangle.offset; | |
2281 | mask = ~act->mangle.mask; | |
2282 | /* For IPv4 & IPv6 header check 4 byte word, | |
2283 | * to determine that modified fields | |
2284 | * are NOT ttl & hop_limit only. | |
2285 | */ | |
2286 | if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) { | |
2287 | struct ip_ttl_word *ttl_word = | |
2288 | (struct ip_ttl_word *)&mask; | |
2289 | ||
2290 | if (offset != offsetof(struct iphdr, ttl) || | |
2291 | ttl_word->protocol || | |
2292 | ttl_word->check) { | |
2293 | return true; | |
2294 | } | |
2295 | } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) { | |
2296 | struct ipv6_hoplimit_word *hoplimit_word = | |
2297 | (struct ipv6_hoplimit_word *)&mask; | |
2298 | ||
2299 | if (offset != offsetof(struct ipv6hdr, payload_len) || | |
2300 | hoplimit_word->payload_len || | |
2301 | hoplimit_word->nexthdr) { | |
2302 | return true; | |
2303 | } | |
2304 | } | |
2305 | return false; | |
2306 | } | |
2307 | ||
bdd66ac0 | 2308 | static bool modify_header_match_supported(struct mlx5_flow_spec *spec, |
73867881 | 2309 | struct flow_action *flow_action, |
1651925d | 2310 | u32 actions, |
e98bedf5 | 2311 | struct netlink_ext_ack *extack) |
bdd66ac0 | 2312 | { |
73867881 | 2313 | const struct flow_action_entry *act; |
bdd66ac0 | 2314 | bool modify_ip_header; |
bdd66ac0 OG |
2315 | void *headers_v; |
2316 | u16 ethertype; | |
8998576b | 2317 | u8 ip_proto; |
73867881 | 2318 | int i; |
bdd66ac0 | 2319 | |
8377629e | 2320 | headers_v = get_match_headers_value(actions, spec); |
bdd66ac0 OG |
2321 | ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype); |
2322 | ||
2323 | /* for non-IP we only re-write MACs, so we're okay */ | |
2324 | if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6) | |
2325 | goto out_ok; | |
2326 | ||
2327 | modify_ip_header = false; | |
73867881 PNA |
2328 | flow_action_for_each(i, act, flow_action) { |
2329 | if (act->id != FLOW_ACTION_MANGLE && | |
2330 | act->id != FLOW_ACTION_ADD) | |
bdd66ac0 OG |
2331 | continue; |
2332 | ||
8998576b | 2333 | if (is_action_keys_supported(act)) { |
73867881 PNA |
2334 | modify_ip_header = true; |
2335 | break; | |
bdd66ac0 OG |
2336 | } |
2337 | } | |
2338 | ||
2339 | ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol); | |
1ccef350 JL |
2340 | if (modify_ip_header && ip_proto != IPPROTO_TCP && |
2341 | ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) { | |
e98bedf5 EB |
2342 | NL_SET_ERR_MSG_MOD(extack, |
2343 | "can't offload re-write of non TCP/UDP"); | |
bdd66ac0 OG |
2344 | pr_info("can't offload re-write of ip proto %d\n", ip_proto); |
2345 | return false; | |
2346 | } | |
2347 | ||
2348 | out_ok: | |
2349 | return true; | |
2350 | } | |
2351 | ||
2352 | static bool actions_match_supported(struct mlx5e_priv *priv, | |
73867881 | 2353 | struct flow_action *flow_action, |
bdd66ac0 | 2354 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
2355 | struct mlx5e_tc_flow *flow, |
2356 | struct netlink_ext_ack *extack) | |
bdd66ac0 OG |
2357 | { |
2358 | u32 actions; | |
2359 | ||
2360 | if (flow->flags & MLX5E_TC_FLOW_ESWITCH) | |
2361 | actions = flow->esw_attr->action; | |
2362 | else | |
2363 | actions = flow->nic_attr->action; | |
2364 | ||
7e29392e | 2365 | if (flow->flags & MLX5E_TC_FLOW_EGRESS && |
35a605db EB |
2366 | !((actions & MLX5_FLOW_CONTEXT_ACTION_DECAP) || |
2367 | (actions & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP))) | |
7e29392e RD |
2368 | return false; |
2369 | ||
bdd66ac0 | 2370 | if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) |
73867881 | 2371 | return modify_header_match_supported(&parse_attr->spec, |
a655fe9f | 2372 | flow_action, actions, |
e98bedf5 | 2373 | extack); |
bdd66ac0 OG |
2374 | |
2375 | return true; | |
2376 | } | |
2377 | ||
5c65c564 OG |
2378 | static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv) |
2379 | { | |
2380 | struct mlx5_core_dev *fmdev, *pmdev; | |
816f6706 | 2381 | u64 fsystem_guid, psystem_guid; |
5c65c564 OG |
2382 | |
2383 | fmdev = priv->mdev; | |
2384 | pmdev = peer_priv->mdev; | |
2385 | ||
59c9d35e AH |
2386 | fsystem_guid = mlx5_query_nic_system_image_guid(fmdev); |
2387 | psystem_guid = mlx5_query_nic_system_image_guid(pmdev); | |
5c65c564 | 2388 | |
816f6706 | 2389 | return (fsystem_guid == psystem_guid); |
5c65c564 OG |
2390 | } |
2391 | ||
bdc837ee EB |
2392 | static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace, |
2393 | const struct flow_action_entry *act, | |
2394 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
2395 | struct pedit_headers_action *hdrs, | |
2396 | u32 *action, struct netlink_ext_ack *extack) | |
2397 | { | |
2398 | u16 mask16 = VLAN_VID_MASK; | |
2399 | u16 val16 = act->vlan.vid & VLAN_VID_MASK; | |
2400 | const struct flow_action_entry pedit_act = { | |
2401 | .id = FLOW_ACTION_MANGLE, | |
2402 | .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH, | |
2403 | .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI), | |
2404 | .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16), | |
2405 | .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16), | |
2406 | }; | |
6fca9d1e | 2407 | u8 match_prio_mask, match_prio_val; |
bf2f3bca | 2408 | void *headers_c, *headers_v; |
bdc837ee EB |
2409 | int err; |
2410 | ||
bf2f3bca EB |
2411 | headers_c = get_match_headers_criteria(*action, &parse_attr->spec); |
2412 | headers_v = get_match_headers_value(*action, &parse_attr->spec); | |
2413 | ||
2414 | if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) && | |
2415 | MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) { | |
2416 | NL_SET_ERR_MSG_MOD(extack, | |
2417 | "VLAN rewrite action must have VLAN protocol match"); | |
2418 | return -EOPNOTSUPP; | |
2419 | } | |
2420 | ||
6fca9d1e EB |
2421 | match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio); |
2422 | match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio); | |
2423 | if (act->vlan.prio != (match_prio_val & match_prio_mask)) { | |
2424 | NL_SET_ERR_MSG_MOD(extack, | |
2425 | "Changing VLAN prio is not supported"); | |
bdc837ee EB |
2426 | return -EOPNOTSUPP; |
2427 | } | |
2428 | ||
2429 | err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, | |
2430 | hdrs, NULL); | |
2431 | *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; | |
2432 | ||
2433 | return err; | |
2434 | } | |
2435 | ||
0bac1194 EB |
2436 | static int |
2437 | add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv, | |
2438 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
2439 | struct pedit_headers_action *hdrs, | |
2440 | u32 *action, struct netlink_ext_ack *extack) | |
2441 | { | |
2442 | const struct flow_action_entry prio_tag_act = { | |
2443 | .vlan.vid = 0, | |
2444 | .vlan.prio = | |
2445 | MLX5_GET(fte_match_set_lyr_2_4, | |
2446 | get_match_headers_value(*action, | |
2447 | &parse_attr->spec), | |
2448 | first_prio) & | |
2449 | MLX5_GET(fte_match_set_lyr_2_4, | |
2450 | get_match_headers_criteria(*action, | |
2451 | &parse_attr->spec), | |
2452 | first_prio), | |
2453 | }; | |
2454 | ||
2455 | return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB, | |
2456 | &prio_tag_act, parse_attr, hdrs, action, | |
2457 | extack); | |
2458 | } | |
2459 | ||
73867881 PNA |
2460 | static int parse_tc_nic_actions(struct mlx5e_priv *priv, |
2461 | struct flow_action *flow_action, | |
aa0cbbae | 2462 | struct mlx5e_tc_flow_parse_attr *parse_attr, |
e98bedf5 EB |
2463 | struct mlx5e_tc_flow *flow, |
2464 | struct netlink_ext_ack *extack) | |
e3a2b7ed | 2465 | { |
aa0cbbae | 2466 | struct mlx5_nic_flow_attr *attr = flow->nic_attr; |
73867881 PNA |
2467 | struct pedit_headers_action hdrs[2] = {}; |
2468 | const struct flow_action_entry *act; | |
1cab1cd7 | 2469 | u32 action = 0; |
244cd96a | 2470 | int err, i; |
e3a2b7ed | 2471 | |
73867881 | 2472 | if (!flow_action_has_entries(flow_action)) |
e3a2b7ed AV |
2473 | return -EINVAL; |
2474 | ||
3bc4b7bf | 2475 | attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG; |
e3a2b7ed | 2476 | |
73867881 PNA |
2477 | flow_action_for_each(i, act, flow_action) { |
2478 | switch (act->id) { | |
2479 | case FLOW_ACTION_DROP: | |
1cab1cd7 | 2480 | action |= MLX5_FLOW_CONTEXT_ACTION_DROP; |
aad7e08d AV |
2481 | if (MLX5_CAP_FLOWTABLE(priv->mdev, |
2482 | flow_table_properties_nic_receive.flow_counter)) | |
1cab1cd7 | 2483 | action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; |
73867881 PNA |
2484 | break; |
2485 | case FLOW_ACTION_MANGLE: | |
2486 | case FLOW_ACTION_ADD: | |
2487 | err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL, | |
c500c86b | 2488 | parse_attr, hdrs, extack); |
2f4fe4ca OG |
2489 | if (err) |
2490 | return err; | |
2491 | ||
1cab1cd7 OG |
2492 | action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR | |
2493 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
73867881 | 2494 | break; |
bdc837ee EB |
2495 | case FLOW_ACTION_VLAN_MANGLE: |
2496 | err = add_vlan_rewrite_action(priv, | |
2497 | MLX5_FLOW_NAMESPACE_KERNEL, | |
2498 | act, parse_attr, hdrs, | |
2499 | &action, extack); | |
2500 | if (err) | |
2501 | return err; | |
2502 | ||
2503 | break; | |
73867881 | 2504 | case FLOW_ACTION_CSUM: |
1cab1cd7 | 2505 | if (csum_offload_supported(priv, action, |
73867881 | 2506 | act->csum_flags, |
e98bedf5 | 2507 | extack)) |
73867881 | 2508 | break; |
26c02749 OG |
2509 | |
2510 | return -EOPNOTSUPP; | |
73867881 PNA |
2511 | case FLOW_ACTION_REDIRECT: { |
2512 | struct net_device *peer_dev = act->dev; | |
5c65c564 OG |
2513 | |
2514 | if (priv->netdev->netdev_ops == peer_dev->netdev_ops && | |
2515 | same_hw_devs(priv, netdev_priv(peer_dev))) { | |
98b66cb1 | 2516 | parse_attr->mirred_ifindex[0] = peer_dev->ifindex; |
5c65c564 | 2517 | flow->flags |= MLX5E_TC_FLOW_HAIRPIN; |
1cab1cd7 OG |
2518 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
2519 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
5c65c564 | 2520 | } else { |
e98bedf5 EB |
2521 | NL_SET_ERR_MSG_MOD(extack, |
2522 | "device is not on same HW, can't offload"); | |
5c65c564 OG |
2523 | netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n", |
2524 | peer_dev->name); | |
2525 | return -EINVAL; | |
2526 | } | |
73867881 PNA |
2527 | } |
2528 | break; | |
2529 | case FLOW_ACTION_MARK: { | |
2530 | u32 mark = act->mark; | |
e3a2b7ed AV |
2531 | |
2532 | if (mark & ~MLX5E_TC_FLOW_ID_MASK) { | |
e98bedf5 EB |
2533 | NL_SET_ERR_MSG_MOD(extack, |
2534 | "Bad flow mark - only 16 bit is supported"); | |
e3a2b7ed AV |
2535 | return -EINVAL; |
2536 | } | |
2537 | ||
3bc4b7bf | 2538 | attr->flow_tag = mark; |
1cab1cd7 | 2539 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; |
73867881 PNA |
2540 | } |
2541 | break; | |
2542 | default: | |
2cc1cb1d TZ |
2543 | NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); |
2544 | return -EOPNOTSUPP; | |
e3a2b7ed | 2545 | } |
e3a2b7ed AV |
2546 | } |
2547 | ||
c500c86b PNA |
2548 | if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || |
2549 | hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { | |
2550 | err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_KERNEL, | |
27c11b6b | 2551 | parse_attr, hdrs, &action, extack); |
c500c86b PNA |
2552 | if (err) |
2553 | return err; | |
27c11b6b EB |
2554 | /* in case all pedit actions are skipped, remove the MOD_HDR |
2555 | * flag. | |
2556 | */ | |
e7739a60 | 2557 | if (parse_attr->num_mod_hdr_actions == 0) { |
27c11b6b | 2558 | action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
e7739a60 EB |
2559 | kfree(parse_attr->mod_hdr_actions); |
2560 | } | |
c500c86b PNA |
2561 | } |
2562 | ||
1cab1cd7 | 2563 | attr->action = action; |
73867881 | 2564 | if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) |
bdd66ac0 OG |
2565 | return -EOPNOTSUPP; |
2566 | ||
e3a2b7ed AV |
2567 | return 0; |
2568 | } | |
2569 | ||
7f1a546e | 2570 | struct encap_key { |
1f6da306 | 2571 | const struct ip_tunnel_key *ip_tun_key; |
7f1a546e EB |
2572 | int tunnel_type; |
2573 | }; | |
2574 | ||
2575 | static inline int cmp_encap_info(struct encap_key *a, | |
2576 | struct encap_key *b) | |
a54e20b4 | 2577 | { |
7f1a546e EB |
2578 | return memcmp(a->ip_tun_key, b->ip_tun_key, sizeof(*a->ip_tun_key)) || |
2579 | a->tunnel_type != b->tunnel_type; | |
a54e20b4 HHZ |
2580 | } |
2581 | ||
7f1a546e | 2582 | static inline int hash_encap_info(struct encap_key *key) |
a54e20b4 | 2583 | { |
7f1a546e EB |
2584 | return jhash(key->ip_tun_key, sizeof(*key->ip_tun_key), |
2585 | key->tunnel_type); | |
a54e20b4 HHZ |
2586 | } |
2587 | ||
a54e20b4 | 2588 | |
b1d90e6b RL |
2589 | static bool is_merged_eswitch_dev(struct mlx5e_priv *priv, |
2590 | struct net_device *peer_netdev) | |
2591 | { | |
2592 | struct mlx5e_priv *peer_priv; | |
2593 | ||
2594 | peer_priv = netdev_priv(peer_netdev); | |
2595 | ||
2596 | return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) && | |
68931c7d RD |
2597 | mlx5e_eswitch_rep(priv->netdev) && |
2598 | mlx5e_eswitch_rep(peer_netdev) && | |
2599 | same_hw_devs(priv, peer_priv)); | |
b1d90e6b RL |
2600 | } |
2601 | ||
32f3671f | 2602 | |
f5bc2c5d | 2603 | |
a54e20b4 | 2604 | static int mlx5e_attach_encap(struct mlx5e_priv *priv, |
e98bedf5 | 2605 | struct mlx5e_tc_flow *flow, |
733d4f36 RD |
2606 | struct net_device *mirred_dev, |
2607 | int out_index, | |
8c4dc42b | 2608 | struct netlink_ext_ack *extack, |
0ad060ee RD |
2609 | struct net_device **encap_dev, |
2610 | bool *encap_valid) | |
a54e20b4 HHZ |
2611 | { |
2612 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
45247bf2 | 2613 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
733d4f36 | 2614 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
1f6da306 | 2615 | const struct ip_tunnel_info *tun_info; |
7f1a546e | 2616 | struct encap_key key, e_key; |
c1ae1152 | 2617 | struct mlx5e_encap_entry *e; |
733d4f36 | 2618 | unsigned short family; |
a54e20b4 HHZ |
2619 | uintptr_t hash_key; |
2620 | bool found = false; | |
54c177ca | 2621 | int err = 0; |
a54e20b4 | 2622 | |
733d4f36 | 2623 | parse_attr = attr->parse_attr; |
1f6da306 | 2624 | tun_info = parse_attr->tun_info[out_index]; |
733d4f36 | 2625 | family = ip_tunnel_info_af(tun_info); |
7f1a546e EB |
2626 | key.ip_tun_key = &tun_info->key; |
2627 | key.tunnel_type = mlx5e_tc_tun_get_type(mirred_dev); | |
733d4f36 | 2628 | |
7f1a546e | 2629 | hash_key = hash_encap_info(&key); |
a54e20b4 HHZ |
2630 | |
2631 | hash_for_each_possible_rcu(esw->offloads.encap_tbl, e, | |
2632 | encap_hlist, hash_key) { | |
1f6da306 | 2633 | e_key.ip_tun_key = &e->tun_info->key; |
7f1a546e EB |
2634 | e_key.tunnel_type = e->tunnel_type; |
2635 | if (!cmp_encap_info(&e_key, &key)) { | |
a54e20b4 HHZ |
2636 | found = true; |
2637 | break; | |
2638 | } | |
2639 | } | |
2640 | ||
b2812089 | 2641 | /* must verify if encap is valid or not */ |
45247bf2 OG |
2642 | if (found) |
2643 | goto attach_flow; | |
a54e20b4 HHZ |
2644 | |
2645 | e = kzalloc(sizeof(*e), GFP_KERNEL); | |
2646 | if (!e) | |
2647 | return -ENOMEM; | |
2648 | ||
1f6da306 | 2649 | e->tun_info = tun_info; |
101f4de9 | 2650 | err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack); |
54c177ca OS |
2651 | if (err) |
2652 | goto out_err; | |
2653 | ||
a54e20b4 HHZ |
2654 | INIT_LIST_HEAD(&e->flows); |
2655 | ||
ce99f6b9 | 2656 | if (family == AF_INET) |
101f4de9 | 2657 | err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e); |
ce99f6b9 | 2658 | else if (family == AF_INET6) |
101f4de9 | 2659 | err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e); |
ce99f6b9 | 2660 | |
0ad060ee | 2661 | if (err) |
a54e20b4 HHZ |
2662 | goto out_err; |
2663 | ||
a54e20b4 HHZ |
2664 | hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key); |
2665 | ||
45247bf2 | 2666 | attach_flow: |
8c4dc42b EB |
2667 | list_add(&flow->encaps[out_index].list, &e->flows); |
2668 | flow->encaps[out_index].index = out_index; | |
45247bf2 | 2669 | *encap_dev = e->out_dev; |
8c4dc42b EB |
2670 | if (e->flags & MLX5_ENCAP_ENTRY_VALID) { |
2671 | attr->dests[out_index].encap_id = e->encap_id; | |
2672 | attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID; | |
0ad060ee | 2673 | *encap_valid = true; |
8c4dc42b | 2674 | } else { |
0ad060ee | 2675 | *encap_valid = false; |
8c4dc42b | 2676 | } |
45247bf2 | 2677 | |
232c0013 | 2678 | return err; |
a54e20b4 HHZ |
2679 | |
2680 | out_err: | |
2681 | kfree(e); | |
2682 | return err; | |
2683 | } | |
2684 | ||
1482bd3d | 2685 | static int parse_tc_vlan_action(struct mlx5e_priv *priv, |
73867881 | 2686 | const struct flow_action_entry *act, |
1482bd3d JL |
2687 | struct mlx5_esw_flow_attr *attr, |
2688 | u32 *action) | |
2689 | { | |
cc495188 JL |
2690 | u8 vlan_idx = attr->total_vlan; |
2691 | ||
2692 | if (vlan_idx >= MLX5_FS_VLAN_DEPTH) | |
2693 | return -EOPNOTSUPP; | |
2694 | ||
73867881 PNA |
2695 | switch (act->id) { |
2696 | case FLOW_ACTION_VLAN_POP: | |
cc495188 JL |
2697 | if (vlan_idx) { |
2698 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, | |
2699 | MLX5_FS_VLAN_DEPTH)) | |
2700 | return -EOPNOTSUPP; | |
2701 | ||
2702 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2; | |
2703 | } else { | |
2704 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
2705 | } | |
73867881 PNA |
2706 | break; |
2707 | case FLOW_ACTION_VLAN_PUSH: | |
2708 | attr->vlan_vid[vlan_idx] = act->vlan.vid; | |
2709 | attr->vlan_prio[vlan_idx] = act->vlan.prio; | |
2710 | attr->vlan_proto[vlan_idx] = act->vlan.proto; | |
cc495188 JL |
2711 | if (!attr->vlan_proto[vlan_idx]) |
2712 | attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q); | |
2713 | ||
2714 | if (vlan_idx) { | |
2715 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, | |
2716 | MLX5_FS_VLAN_DEPTH)) | |
2717 | return -EOPNOTSUPP; | |
2718 | ||
2719 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2; | |
2720 | } else { | |
2721 | if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) && | |
73867881 PNA |
2722 | (act->vlan.proto != htons(ETH_P_8021Q) || |
2723 | act->vlan.prio)) | |
cc495188 JL |
2724 | return -EOPNOTSUPP; |
2725 | ||
2726 | *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH; | |
1482bd3d | 2727 | } |
73867881 PNA |
2728 | break; |
2729 | default: | |
bdc837ee | 2730 | return -EINVAL; |
1482bd3d JL |
2731 | } |
2732 | ||
cc495188 JL |
2733 | attr->total_vlan = vlan_idx + 1; |
2734 | ||
1482bd3d JL |
2735 | return 0; |
2736 | } | |
2737 | ||
278748a9 EB |
2738 | static int add_vlan_push_action(struct mlx5e_priv *priv, |
2739 | struct mlx5_esw_flow_attr *attr, | |
2740 | struct net_device **out_dev, | |
2741 | u32 *action) | |
2742 | { | |
2743 | struct net_device *vlan_dev = *out_dev; | |
2744 | struct flow_action_entry vlan_act = { | |
2745 | .id = FLOW_ACTION_VLAN_PUSH, | |
2746 | .vlan.vid = vlan_dev_vlan_id(vlan_dev), | |
2747 | .vlan.proto = vlan_dev_vlan_proto(vlan_dev), | |
2748 | .vlan.prio = 0, | |
2749 | }; | |
2750 | int err; | |
2751 | ||
2752 | err = parse_tc_vlan_action(priv, &vlan_act, attr, action); | |
2753 | if (err) | |
2754 | return err; | |
2755 | ||
2756 | *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), | |
2757 | dev_get_iflink(vlan_dev)); | |
2758 | if (is_vlan_dev(*out_dev)) | |
2759 | err = add_vlan_push_action(priv, attr, out_dev, action); | |
2760 | ||
2761 | return err; | |
2762 | } | |
2763 | ||
35a605db EB |
2764 | static int add_vlan_pop_action(struct mlx5e_priv *priv, |
2765 | struct mlx5_esw_flow_attr *attr, | |
2766 | u32 *action) | |
2767 | { | |
2768 | int nest_level = vlan_get_encap_level(attr->parse_attr->filter_dev); | |
2769 | struct flow_action_entry vlan_act = { | |
2770 | .id = FLOW_ACTION_VLAN_POP, | |
2771 | }; | |
2772 | int err = 0; | |
2773 | ||
2774 | while (nest_level--) { | |
2775 | err = parse_tc_vlan_action(priv, &vlan_act, attr, action); | |
2776 | if (err) | |
2777 | return err; | |
2778 | } | |
2779 | ||
2780 | return err; | |
2781 | } | |
2782 | ||
73867881 PNA |
2783 | static int parse_tc_fdb_actions(struct mlx5e_priv *priv, |
2784 | struct flow_action *flow_action, | |
e98bedf5 EB |
2785 | struct mlx5e_tc_flow *flow, |
2786 | struct netlink_ext_ack *extack) | |
03a9d11e | 2787 | { |
73867881 | 2788 | struct pedit_headers_action hdrs[2] = {}; |
bf07aa73 | 2789 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
ecf5bb79 | 2790 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
6f9af8ff | 2791 | struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr; |
1d447a39 | 2792 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
73867881 PNA |
2793 | const struct ip_tunnel_info *info = NULL; |
2794 | const struct flow_action_entry *act; | |
a54e20b4 | 2795 | bool encap = false; |
1cab1cd7 | 2796 | u32 action = 0; |
244cd96a | 2797 | int err, i; |
03a9d11e | 2798 | |
73867881 | 2799 | if (!flow_action_has_entries(flow_action)) |
03a9d11e OG |
2800 | return -EINVAL; |
2801 | ||
1d447a39 | 2802 | attr->in_rep = rpriv->rep; |
10ff5359 | 2803 | attr->in_mdev = priv->mdev; |
03a9d11e | 2804 | |
73867881 PNA |
2805 | flow_action_for_each(i, act, flow_action) { |
2806 | switch (act->id) { | |
2807 | case FLOW_ACTION_DROP: | |
1cab1cd7 OG |
2808 | action |= MLX5_FLOW_CONTEXT_ACTION_DROP | |
2809 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
73867881 PNA |
2810 | break; |
2811 | case FLOW_ACTION_MANGLE: | |
2812 | case FLOW_ACTION_ADD: | |
2813 | err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB, | |
c500c86b | 2814 | parse_attr, hdrs, extack); |
d7e75a32 OG |
2815 | if (err) |
2816 | return err; | |
2817 | ||
1cab1cd7 | 2818 | action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; |
e85e02ba | 2819 | attr->split_count = attr->out_count; |
73867881 PNA |
2820 | break; |
2821 | case FLOW_ACTION_CSUM: | |
1cab1cd7 | 2822 | if (csum_offload_supported(priv, action, |
73867881 PNA |
2823 | act->csum_flags, extack)) |
2824 | break; | |
26c02749 OG |
2825 | |
2826 | return -EOPNOTSUPP; | |
73867881 PNA |
2827 | case FLOW_ACTION_REDIRECT: |
2828 | case FLOW_ACTION_MIRRED: { | |
03a9d11e | 2829 | struct mlx5e_priv *out_priv; |
592d3651 | 2830 | struct net_device *out_dev; |
03a9d11e | 2831 | |
73867881 | 2832 | out_dev = act->dev; |
ef381359 OS |
2833 | if (!out_dev) { |
2834 | /* out_dev is NULL when filters with | |
2835 | * non-existing mirred device are replayed to | |
2836 | * the driver. | |
2837 | */ | |
2838 | return -EINVAL; | |
2839 | } | |
03a9d11e | 2840 | |
592d3651 | 2841 | if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) { |
e98bedf5 EB |
2842 | NL_SET_ERR_MSG_MOD(extack, |
2843 | "can't support more output ports, can't offload forwarding"); | |
592d3651 CM |
2844 | pr_err("can't support more than %d output ports, can't offload forwarding\n", |
2845 | attr->out_count); | |
2846 | return -EOPNOTSUPP; | |
2847 | } | |
2848 | ||
f493f155 EB |
2849 | action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | |
2850 | MLX5_FLOW_CONTEXT_ACTION_COUNT; | |
6dcfa234 FF |
2851 | if (netdev_port_same_parent_id(priv->netdev, |
2852 | out_dev) || | |
b1d90e6b | 2853 | is_merged_eswitch_dev(priv, out_dev)) { |
7ba58ba7 RL |
2854 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
2855 | struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH); | |
2856 | struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev); | |
2857 | ||
2858 | if (uplink_upper && | |
2859 | netif_is_lag_master(uplink_upper) && | |
2860 | uplink_upper == out_dev) | |
2861 | out_dev = uplink_dev; | |
2862 | ||
278748a9 EB |
2863 | if (is_vlan_dev(out_dev)) { |
2864 | err = add_vlan_push_action(priv, attr, | |
2865 | &out_dev, | |
2866 | &action); | |
2867 | if (err) | |
2868 | return err; | |
2869 | } | |
35a605db EB |
2870 | if (is_vlan_dev(parse_attr->filter_dev)) { |
2871 | err = add_vlan_pop_action(priv, attr, | |
2872 | &action); | |
2873 | if (err) | |
2874 | return err; | |
2875 | } | |
278748a9 | 2876 | |
a0646c88 EB |
2877 | if (!mlx5e_eswitch_rep(out_dev)) |
2878 | return -EOPNOTSUPP; | |
2879 | ||
a54e20b4 | 2880 | out_priv = netdev_priv(out_dev); |
1d447a39 | 2881 | rpriv = out_priv->ppriv; |
df65a573 EB |
2882 | attr->dests[attr->out_count].rep = rpriv->rep; |
2883 | attr->dests[attr->out_count].mdev = out_priv->mdev; | |
2884 | attr->out_count++; | |
a54e20b4 | 2885 | } else if (encap) { |
8c4dc42b EB |
2886 | parse_attr->mirred_ifindex[attr->out_count] = |
2887 | out_dev->ifindex; | |
1f6da306 | 2888 | parse_attr->tun_info[attr->out_count] = info; |
8c4dc42b | 2889 | encap = false; |
f493f155 EB |
2890 | attr->dests[attr->out_count].flags |= |
2891 | MLX5_ESW_DEST_ENCAP; | |
1cc26d74 | 2892 | attr->out_count++; |
df65a573 EB |
2893 | /* attr->dests[].rep is resolved when we |
2894 | * handle encap | |
2895 | */ | |
ef381359 OS |
2896 | } else if (parse_attr->filter_dev != priv->netdev) { |
2897 | /* All mlx5 devices are called to configure | |
2898 | * high level device filters. Therefore, the | |
2899 | * *attempt* to install a filter on invalid | |
2900 | * eswitch should not trigger an explicit error | |
2901 | */ | |
2902 | return -EINVAL; | |
a54e20b4 | 2903 | } else { |
e98bedf5 EB |
2904 | NL_SET_ERR_MSG_MOD(extack, |
2905 | "devices are not on same switch HW, can't offload forwarding"); | |
03a9d11e OG |
2906 | pr_err("devices %s %s not on same switch HW, can't offload forwarding\n", |
2907 | priv->netdev->name, out_dev->name); | |
2908 | return -EINVAL; | |
2909 | } | |
73867881 PNA |
2910 | } |
2911 | break; | |
2912 | case FLOW_ACTION_TUNNEL_ENCAP: | |
2913 | info = act->tunnel; | |
a54e20b4 HHZ |
2914 | if (info) |
2915 | encap = true; | |
2916 | else | |
2917 | return -EOPNOTSUPP; | |
1482bd3d | 2918 | |
73867881 PNA |
2919 | break; |
2920 | case FLOW_ACTION_VLAN_PUSH: | |
2921 | case FLOW_ACTION_VLAN_POP: | |
76b496b1 EB |
2922 | if (act->id == FLOW_ACTION_VLAN_PUSH && |
2923 | (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) { | |
2924 | /* Replace vlan pop+push with vlan modify */ | |
2925 | action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
2926 | err = add_vlan_rewrite_action(priv, | |
2927 | MLX5_FLOW_NAMESPACE_FDB, | |
2928 | act, parse_attr, hdrs, | |
2929 | &action, extack); | |
2930 | } else { | |
2931 | err = parse_tc_vlan_action(priv, act, attr, &action); | |
2932 | } | |
1482bd3d JL |
2933 | if (err) |
2934 | return err; | |
2935 | ||
bdc837ee EB |
2936 | attr->split_count = attr->out_count; |
2937 | break; | |
2938 | case FLOW_ACTION_VLAN_MANGLE: | |
2939 | err = add_vlan_rewrite_action(priv, | |
2940 | MLX5_FLOW_NAMESPACE_FDB, | |
2941 | act, parse_attr, hdrs, | |
2942 | &action, extack); | |
2943 | if (err) | |
2944 | return err; | |
2945 | ||
e85e02ba | 2946 | attr->split_count = attr->out_count; |
73867881 PNA |
2947 | break; |
2948 | case FLOW_ACTION_TUNNEL_DECAP: | |
1cab1cd7 | 2949 | action |= MLX5_FLOW_CONTEXT_ACTION_DECAP; |
73867881 PNA |
2950 | break; |
2951 | case FLOW_ACTION_GOTO: { | |
2952 | u32 dest_chain = act->chain_index; | |
bf07aa73 PB |
2953 | u32 max_chain = mlx5_eswitch_get_chain_range(esw); |
2954 | ||
2955 | if (dest_chain <= attr->chain) { | |
2956 | NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported"); | |
2957 | return -EOPNOTSUPP; | |
2958 | } | |
2959 | if (dest_chain > max_chain) { | |
2960 | NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range"); | |
2961 | return -EOPNOTSUPP; | |
2962 | } | |
e88afe75 | 2963 | action |= MLX5_FLOW_CONTEXT_ACTION_COUNT; |
bf07aa73 | 2964 | attr->dest_chain = dest_chain; |
73867881 PNA |
2965 | break; |
2966 | } | |
2967 | default: | |
2cc1cb1d TZ |
2968 | NL_SET_ERR_MSG_MOD(extack, "The offload action is not supported"); |
2969 | return -EOPNOTSUPP; | |
bf07aa73 | 2970 | } |
03a9d11e | 2971 | } |
bdd66ac0 | 2972 | |
0bac1194 EB |
2973 | if (MLX5_CAP_GEN(esw->dev, prio_tag_required) && |
2974 | action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) { | |
2975 | /* For prio tag mode, replace vlan pop with rewrite vlan prio | |
2976 | * tag rewrite. | |
2977 | */ | |
2978 | action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP; | |
2979 | err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs, | |
2980 | &action, extack); | |
2981 | if (err) | |
2982 | return err; | |
2983 | } | |
2984 | ||
c500c86b PNA |
2985 | if (hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits || |
2986 | hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits) { | |
84be899f | 2987 | err = alloc_tc_pedit_action(priv, MLX5_FLOW_NAMESPACE_FDB, |
27c11b6b | 2988 | parse_attr, hdrs, &action, extack); |
c500c86b PNA |
2989 | if (err) |
2990 | return err; | |
27c11b6b EB |
2991 | /* in case all pedit actions are skipped, remove the MOD_HDR |
2992 | * flag. we might have set split_count either by pedit or | |
2993 | * pop/push. if there is no pop/push either, reset it too. | |
2994 | */ | |
2995 | if (parse_attr->num_mod_hdr_actions == 0) { | |
2996 | action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR; | |
e7739a60 | 2997 | kfree(parse_attr->mod_hdr_actions); |
27c11b6b EB |
2998 | if (!((action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) || |
2999 | (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH))) | |
3000 | attr->split_count = 0; | |
3001 | } | |
c500c86b PNA |
3002 | } |
3003 | ||
1cab1cd7 | 3004 | attr->action = action; |
73867881 | 3005 | if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack)) |
bdd66ac0 OG |
3006 | return -EOPNOTSUPP; |
3007 | ||
e88afe75 OG |
3008 | if (attr->dest_chain) { |
3009 | if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) { | |
3010 | NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported"); | |
3011 | return -EOPNOTSUPP; | |
3012 | } | |
3013 | attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST; | |
3014 | } | |
3015 | ||
e85e02ba | 3016 | if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) { |
e98bedf5 EB |
3017 | NL_SET_ERR_MSG_MOD(extack, |
3018 | "current firmware doesn't support split rule for port mirroring"); | |
592d3651 CM |
3019 | netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n"); |
3020 | return -EOPNOTSUPP; | |
3021 | } | |
3022 | ||
31c8eba5 | 3023 | return 0; |
03a9d11e OG |
3024 | } |
3025 | ||
5dbe906f | 3026 | static void get_flags(int flags, u16 *flow_flags) |
60bd4af8 | 3027 | { |
5dbe906f | 3028 | u16 __flow_flags = 0; |
60bd4af8 OG |
3029 | |
3030 | if (flags & MLX5E_TC_INGRESS) | |
3031 | __flow_flags |= MLX5E_TC_FLOW_INGRESS; | |
3032 | if (flags & MLX5E_TC_EGRESS) | |
3033 | __flow_flags |= MLX5E_TC_FLOW_EGRESS; | |
3034 | ||
d9ee0491 OG |
3035 | if (flags & MLX5E_TC_ESW_OFFLOAD) |
3036 | __flow_flags |= MLX5E_TC_FLOW_ESWITCH; | |
3037 | if (flags & MLX5E_TC_NIC_OFFLOAD) | |
3038 | __flow_flags |= MLX5E_TC_FLOW_NIC; | |
3039 | ||
60bd4af8 OG |
3040 | *flow_flags = __flow_flags; |
3041 | } | |
3042 | ||
05866c82 OG |
3043 | static const struct rhashtable_params tc_ht_params = { |
3044 | .head_offset = offsetof(struct mlx5e_tc_flow, node), | |
3045 | .key_offset = offsetof(struct mlx5e_tc_flow, cookie), | |
3046 | .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie), | |
3047 | .automatic_shrinking = true, | |
3048 | }; | |
3049 | ||
d9ee0491 | 3050 | static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags) |
05866c82 | 3051 | { |
655dc3d2 OG |
3052 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; |
3053 | struct mlx5e_rep_priv *uplink_rpriv; | |
3054 | ||
d9ee0491 | 3055 | if (flags & MLX5E_TC_ESW_OFFLOAD) { |
655dc3d2 | 3056 | uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH); |
ec1366c2 | 3057 | return &uplink_rpriv->uplink_priv.tc_ht; |
d9ee0491 | 3058 | } else /* NIC offload */ |
655dc3d2 | 3059 | return &priv->fs.tc.ht; |
05866c82 OG |
3060 | } |
3061 | ||
04de7dda RD |
3062 | static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow) |
3063 | { | |
1418ddd9 | 3064 | struct mlx5_esw_flow_attr *attr = flow->esw_attr; |
b05af6aa | 3065 | bool is_rep_ingress = attr->in_rep->vport != MLX5_VPORT_UPLINK && |
1418ddd9 AH |
3066 | flow->flags & MLX5E_TC_FLOW_INGRESS; |
3067 | bool act_is_encap = !!(attr->action & | |
3068 | MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT); | |
3069 | bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom, | |
3070 | MLX5_DEVCOM_ESW_OFFLOADS); | |
3071 | ||
10fbb1cd RD |
3072 | if (!esw_paired) |
3073 | return false; | |
3074 | ||
3075 | if ((mlx5_lag_is_sriov(attr->in_mdev) || | |
3076 | mlx5_lag_is_multipath(attr->in_mdev)) && | |
3077 | (is_rep_ingress || act_is_encap)) | |
3078 | return true; | |
3079 | ||
3080 | return false; | |
04de7dda RD |
3081 | } |
3082 | ||
a88780a9 RD |
3083 | static int |
3084 | mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size, | |
5dbe906f | 3085 | struct tc_cls_flower_offload *f, u16 flow_flags, |
a88780a9 RD |
3086 | struct mlx5e_tc_flow_parse_attr **__parse_attr, |
3087 | struct mlx5e_tc_flow **__flow) | |
e3a2b7ed | 3088 | { |
17091853 | 3089 | struct mlx5e_tc_flow_parse_attr *parse_attr; |
3bc4b7bf | 3090 | struct mlx5e_tc_flow *flow; |
a88780a9 | 3091 | int err; |
e3a2b7ed | 3092 | |
65ba8fb7 | 3093 | flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL); |
1b9a07ee | 3094 | parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL); |
17091853 | 3095 | if (!parse_attr || !flow) { |
e3a2b7ed AV |
3096 | err = -ENOMEM; |
3097 | goto err_free; | |
3098 | } | |
3099 | ||
3100 | flow->cookie = f->cookie; | |
65ba8fb7 | 3101 | flow->flags = flow_flags; |
655dc3d2 | 3102 | flow->priv = priv; |
e3a2b7ed | 3103 | |
a88780a9 RD |
3104 | *__flow = flow; |
3105 | *__parse_attr = parse_attr; | |
3106 | ||
3107 | return 0; | |
3108 | ||
3109 | err_free: | |
3110 | kfree(flow); | |
3111 | kvfree(parse_attr); | |
3112 | return err; | |
3113 | } | |
3114 | ||
988ab9c7 TZ |
3115 | static void |
3116 | mlx5e_flow_esw_attr_init(struct mlx5_esw_flow_attr *esw_attr, | |
3117 | struct mlx5e_priv *priv, | |
3118 | struct mlx5e_tc_flow_parse_attr *parse_attr, | |
3119 | struct tc_cls_flower_offload *f, | |
3120 | struct mlx5_eswitch_rep *in_rep, | |
3121 | struct mlx5_core_dev *in_mdev) | |
3122 | { | |
3123 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
3124 | ||
3125 | esw_attr->parse_attr = parse_attr; | |
3126 | esw_attr->chain = f->common.chain_index; | |
3127 | esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16; | |
3128 | ||
3129 | esw_attr->in_rep = in_rep; | |
3130 | esw_attr->in_mdev = in_mdev; | |
3131 | ||
3132 | if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) == | |
3133 | MLX5_COUNTER_SOURCE_ESWITCH) | |
3134 | esw_attr->counter_dev = in_mdev; | |
3135 | else | |
3136 | esw_attr->counter_dev = priv->mdev; | |
3137 | } | |
3138 | ||
71129676 | 3139 | static struct mlx5e_tc_flow * |
04de7dda RD |
3140 | __mlx5e_add_fdb_flow(struct mlx5e_priv *priv, |
3141 | struct tc_cls_flower_offload *f, | |
3142 | u16 flow_flags, | |
3143 | struct net_device *filter_dev, | |
3144 | struct mlx5_eswitch_rep *in_rep, | |
71129676 | 3145 | struct mlx5_core_dev *in_mdev) |
a88780a9 | 3146 | { |
73867881 | 3147 | struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); |
a88780a9 RD |
3148 | struct netlink_ext_ack *extack = f->common.extack; |
3149 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
3150 | struct mlx5e_tc_flow *flow; | |
3151 | int attr_size, err; | |
e3a2b7ed | 3152 | |
a88780a9 RD |
3153 | flow_flags |= MLX5E_TC_FLOW_ESWITCH; |
3154 | attr_size = sizeof(struct mlx5_esw_flow_attr); | |
3155 | err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, | |
3156 | &parse_attr, &flow); | |
3157 | if (err) | |
3158 | goto out; | |
988ab9c7 | 3159 | |
d11afc26 | 3160 | parse_attr->filter_dev = filter_dev; |
988ab9c7 TZ |
3161 | mlx5e_flow_esw_attr_init(flow->esw_attr, |
3162 | priv, parse_attr, | |
3163 | f, in_rep, in_mdev); | |
3164 | ||
54c177ca OS |
3165 | err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, |
3166 | f, filter_dev); | |
d11afc26 OS |
3167 | if (err) |
3168 | goto err_free; | |
a88780a9 | 3169 | |
6f9af8ff | 3170 | err = parse_tc_fdb_actions(priv, &rule->action, flow, extack); |
a88780a9 RD |
3171 | if (err) |
3172 | goto err_free; | |
3173 | ||
7040632d | 3174 | err = mlx5e_tc_add_fdb_flow(priv, flow, extack); |
ef06c9ee RD |
3175 | if (err) { |
3176 | if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev))) | |
3177 | goto err_free; | |
3178 | ||
b4a23329 | 3179 | add_unready_flow(flow); |
ef06c9ee | 3180 | } |
e3a2b7ed | 3181 | |
71129676 | 3182 | return flow; |
a88780a9 RD |
3183 | |
3184 | err_free: | |
3185 | kfree(flow); | |
3186 | kvfree(parse_attr); | |
3187 | out: | |
71129676 | 3188 | return ERR_PTR(err); |
a88780a9 RD |
3189 | } |
3190 | ||
04de7dda | 3191 | static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f, |
95dc1902 RD |
3192 | struct mlx5e_tc_flow *flow, |
3193 | u16 flow_flags) | |
04de7dda RD |
3194 | { |
3195 | struct mlx5e_priv *priv = flow->priv, *peer_priv; | |
3196 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw; | |
3197 | struct mlx5_devcom *devcom = priv->mdev->priv.devcom; | |
3198 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
3199 | struct mlx5e_rep_priv *peer_urpriv; | |
3200 | struct mlx5e_tc_flow *peer_flow; | |
3201 | struct mlx5_core_dev *in_mdev; | |
3202 | int err = 0; | |
3203 | ||
3204 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
3205 | if (!peer_esw) | |
3206 | return -ENODEV; | |
3207 | ||
3208 | peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH); | |
3209 | peer_priv = netdev_priv(peer_urpriv->netdev); | |
3210 | ||
3211 | /* in_mdev is assigned of which the packet originated from. | |
3212 | * So packets redirected to uplink use the same mdev of the | |
3213 | * original flow and packets redirected from uplink use the | |
3214 | * peer mdev. | |
3215 | */ | |
b05af6aa | 3216 | if (flow->esw_attr->in_rep->vport == MLX5_VPORT_UPLINK) |
04de7dda RD |
3217 | in_mdev = peer_priv->mdev; |
3218 | else | |
3219 | in_mdev = priv->mdev; | |
3220 | ||
3221 | parse_attr = flow->esw_attr->parse_attr; | |
95dc1902 | 3222 | peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags, |
71129676 JG |
3223 | parse_attr->filter_dev, |
3224 | flow->esw_attr->in_rep, in_mdev); | |
3225 | if (IS_ERR(peer_flow)) { | |
3226 | err = PTR_ERR(peer_flow); | |
04de7dda | 3227 | goto out; |
71129676 | 3228 | } |
04de7dda RD |
3229 | |
3230 | flow->peer_flow = peer_flow; | |
3231 | flow->flags |= MLX5E_TC_FLOW_DUP; | |
3232 | mutex_lock(&esw->offloads.peer_mutex); | |
3233 | list_add_tail(&flow->peer, &esw->offloads.peer_flows); | |
3234 | mutex_unlock(&esw->offloads.peer_mutex); | |
3235 | ||
3236 | out: | |
3237 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); | |
3238 | return err; | |
3239 | } | |
3240 | ||
3241 | static int | |
3242 | mlx5e_add_fdb_flow(struct mlx5e_priv *priv, | |
3243 | struct tc_cls_flower_offload *f, | |
3244 | u16 flow_flags, | |
3245 | struct net_device *filter_dev, | |
3246 | struct mlx5e_tc_flow **__flow) | |
3247 | { | |
3248 | struct mlx5e_rep_priv *rpriv = priv->ppriv; | |
3249 | struct mlx5_eswitch_rep *in_rep = rpriv->rep; | |
3250 | struct mlx5_core_dev *in_mdev = priv->mdev; | |
3251 | struct mlx5e_tc_flow *flow; | |
3252 | int err; | |
3253 | ||
71129676 JG |
3254 | flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep, |
3255 | in_mdev); | |
3256 | if (IS_ERR(flow)) | |
3257 | return PTR_ERR(flow); | |
04de7dda RD |
3258 | |
3259 | if (is_peer_flow_needed(flow)) { | |
95dc1902 | 3260 | err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags); |
04de7dda RD |
3261 | if (err) { |
3262 | mlx5e_tc_del_fdb_flow(priv, flow); | |
3263 | goto out; | |
3264 | } | |
3265 | } | |
3266 | ||
3267 | *__flow = flow; | |
3268 | ||
3269 | return 0; | |
3270 | ||
3271 | out: | |
3272 | return err; | |
3273 | } | |
3274 | ||
a88780a9 RD |
3275 | static int |
3276 | mlx5e_add_nic_flow(struct mlx5e_priv *priv, | |
3277 | struct tc_cls_flower_offload *f, | |
5dbe906f | 3278 | u16 flow_flags, |
d11afc26 | 3279 | struct net_device *filter_dev, |
a88780a9 RD |
3280 | struct mlx5e_tc_flow **__flow) |
3281 | { | |
73867881 | 3282 | struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); |
a88780a9 RD |
3283 | struct netlink_ext_ack *extack = f->common.extack; |
3284 | struct mlx5e_tc_flow_parse_attr *parse_attr; | |
3285 | struct mlx5e_tc_flow *flow; | |
3286 | int attr_size, err; | |
3287 | ||
bf07aa73 PB |
3288 | /* multi-chain not supported for NIC rules */ |
3289 | if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common)) | |
3290 | return -EOPNOTSUPP; | |
3291 | ||
a88780a9 RD |
3292 | flow_flags |= MLX5E_TC_FLOW_NIC; |
3293 | attr_size = sizeof(struct mlx5_nic_flow_attr); | |
3294 | err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags, | |
3295 | &parse_attr, &flow); | |
3296 | if (err) | |
3297 | goto out; | |
3298 | ||
d11afc26 | 3299 | parse_attr->filter_dev = filter_dev; |
54c177ca OS |
3300 | err = parse_cls_flower(flow->priv, flow, &parse_attr->spec, |
3301 | f, filter_dev); | |
d11afc26 OS |
3302 | if (err) |
3303 | goto err_free; | |
3304 | ||
73867881 | 3305 | err = parse_tc_nic_actions(priv, &rule->action, parse_attr, flow, extack); |
a88780a9 RD |
3306 | if (err) |
3307 | goto err_free; | |
3308 | ||
3309 | err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack); | |
3310 | if (err) | |
3311 | goto err_free; | |
3312 | ||
3313 | flow->flags |= MLX5E_TC_FLOW_OFFLOADED; | |
3314 | kvfree(parse_attr); | |
3315 | *__flow = flow; | |
3316 | ||
3317 | return 0; | |
e3a2b7ed | 3318 | |
e3a2b7ed | 3319 | err_free: |
a88780a9 | 3320 | kfree(flow); |
17091853 | 3321 | kvfree(parse_attr); |
a88780a9 RD |
3322 | out: |
3323 | return err; | |
3324 | } | |
3325 | ||
3326 | static int | |
3327 | mlx5e_tc_add_flow(struct mlx5e_priv *priv, | |
3328 | struct tc_cls_flower_offload *f, | |
3329 | int flags, | |
d11afc26 | 3330 | struct net_device *filter_dev, |
a88780a9 RD |
3331 | struct mlx5e_tc_flow **flow) |
3332 | { | |
3333 | struct mlx5_eswitch *esw = priv->mdev->priv.eswitch; | |
5dbe906f | 3334 | u16 flow_flags; |
a88780a9 RD |
3335 | int err; |
3336 | ||
3337 | get_flags(flags, &flow_flags); | |
3338 | ||
bf07aa73 PB |
3339 | if (!tc_can_offload_extack(priv->netdev, f->common.extack)) |
3340 | return -EOPNOTSUPP; | |
3341 | ||
a88780a9 | 3342 | if (esw && esw->mode == SRIOV_OFFLOADS) |
d11afc26 OS |
3343 | err = mlx5e_add_fdb_flow(priv, f, flow_flags, |
3344 | filter_dev, flow); | |
a88780a9 | 3345 | else |
d11afc26 OS |
3346 | err = mlx5e_add_nic_flow(priv, f, flow_flags, |
3347 | filter_dev, flow); | |
a88780a9 RD |
3348 | |
3349 | return err; | |
3350 | } | |
3351 | ||
71d82d2a | 3352 | int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv, |
a88780a9 RD |
3353 | struct tc_cls_flower_offload *f, int flags) |
3354 | { | |
3355 | struct netlink_ext_ack *extack = f->common.extack; | |
d9ee0491 | 3356 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
a88780a9 RD |
3357 | struct mlx5e_tc_flow *flow; |
3358 | int err = 0; | |
3359 | ||
3360 | flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); | |
3361 | if (flow) { | |
3362 | NL_SET_ERR_MSG_MOD(extack, | |
3363 | "flow cookie already exists, ignoring"); | |
3364 | netdev_warn_once(priv->netdev, | |
3365 | "flow cookie %lx already exists, ignoring\n", | |
3366 | f->cookie); | |
0e1c1a2f | 3367 | err = -EEXIST; |
a88780a9 RD |
3368 | goto out; |
3369 | } | |
3370 | ||
d11afc26 | 3371 | err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow); |
a88780a9 RD |
3372 | if (err) |
3373 | goto out; | |
3374 | ||
3375 | err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params); | |
3376 | if (err) | |
3377 | goto err_free; | |
3378 | ||
3379 | return 0; | |
3380 | ||
3381 | err_free: | |
3382 | mlx5e_tc_del_flow(priv, flow); | |
232c0013 | 3383 | kfree(flow); |
a88780a9 | 3384 | out: |
e3a2b7ed AV |
3385 | return err; |
3386 | } | |
3387 | ||
8f8ae895 OG |
3388 | #define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS) |
3389 | #define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS) | |
3390 | ||
3391 | static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags) | |
3392 | { | |
3393 | if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK)) | |
3394 | return true; | |
3395 | ||
3396 | return false; | |
3397 | } | |
3398 | ||
71d82d2a | 3399 | int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv, |
60bd4af8 | 3400 | struct tc_cls_flower_offload *f, int flags) |
e3a2b7ed | 3401 | { |
d9ee0491 | 3402 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
e3a2b7ed | 3403 | struct mlx5e_tc_flow *flow; |
e3a2b7ed | 3404 | |
05866c82 | 3405 | flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); |
8f8ae895 | 3406 | if (!flow || !same_flow_direction(flow, flags)) |
e3a2b7ed AV |
3407 | return -EINVAL; |
3408 | ||
05866c82 | 3409 | rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params); |
e3a2b7ed | 3410 | |
961e8979 | 3411 | mlx5e_tc_del_flow(priv, flow); |
e3a2b7ed AV |
3412 | |
3413 | kfree(flow); | |
3414 | ||
3415 | return 0; | |
3416 | } | |
3417 | ||
71d82d2a | 3418 | int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv, |
60bd4af8 | 3419 | struct tc_cls_flower_offload *f, int flags) |
aad7e08d | 3420 | { |
04de7dda | 3421 | struct mlx5_devcom *devcom = priv->mdev->priv.devcom; |
d9ee0491 | 3422 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
04de7dda | 3423 | struct mlx5_eswitch *peer_esw; |
aad7e08d | 3424 | struct mlx5e_tc_flow *flow; |
aad7e08d | 3425 | struct mlx5_fc *counter; |
316d5f72 RD |
3426 | u64 lastuse = 0; |
3427 | u64 packets = 0; | |
3428 | u64 bytes = 0; | |
aad7e08d | 3429 | |
05866c82 | 3430 | flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params); |
8f8ae895 | 3431 | if (!flow || !same_flow_direction(flow, flags)) |
aad7e08d AV |
3432 | return -EINVAL; |
3433 | ||
316d5f72 RD |
3434 | if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) { |
3435 | counter = mlx5e_tc_get_counter(flow); | |
3436 | if (!counter) | |
3437 | return 0; | |
aad7e08d | 3438 | |
316d5f72 RD |
3439 | mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse); |
3440 | } | |
aad7e08d | 3441 | |
316d5f72 RD |
3442 | /* Under multipath it's possible for one rule to be currently |
3443 | * un-offloaded while the other rule is offloaded. | |
3444 | */ | |
04de7dda RD |
3445 | peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); |
3446 | if (!peer_esw) | |
3447 | goto out; | |
3448 | ||
3449 | if ((flow->flags & MLX5E_TC_FLOW_DUP) && | |
3450 | (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) { | |
3451 | u64 bytes2; | |
3452 | u64 packets2; | |
3453 | u64 lastuse2; | |
3454 | ||
3455 | counter = mlx5e_tc_get_counter(flow->peer_flow); | |
316d5f72 RD |
3456 | if (!counter) |
3457 | goto no_peer_counter; | |
04de7dda RD |
3458 | mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2); |
3459 | ||
3460 | bytes += bytes2; | |
3461 | packets += packets2; | |
3462 | lastuse = max_t(u64, lastuse, lastuse2); | |
3463 | } | |
3464 | ||
316d5f72 | 3465 | no_peer_counter: |
04de7dda | 3466 | mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS); |
04de7dda | 3467 | out: |
3b1903ef | 3468 | flow_stats_update(&f->stats, bytes, packets, lastuse); |
fed06ee8 | 3469 | |
aad7e08d AV |
3470 | return 0; |
3471 | } | |
3472 | ||
4d8fcf21 AH |
3473 | static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv, |
3474 | struct mlx5e_priv *peer_priv) | |
3475 | { | |
3476 | struct mlx5_core_dev *peer_mdev = peer_priv->mdev; | |
3477 | struct mlx5e_hairpin_entry *hpe; | |
3478 | u16 peer_vhca_id; | |
3479 | int bkt; | |
3480 | ||
3481 | if (!same_hw_devs(priv, peer_priv)) | |
3482 | return; | |
3483 | ||
3484 | peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id); | |
3485 | ||
3486 | hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) { | |
3487 | if (hpe->peer_vhca_id == peer_vhca_id) | |
3488 | hpe->hp->pair->peer_gone = true; | |
3489 | } | |
3490 | } | |
3491 | ||
3492 | static int mlx5e_tc_netdev_event(struct notifier_block *this, | |
3493 | unsigned long event, void *ptr) | |
3494 | { | |
3495 | struct net_device *ndev = netdev_notifier_info_to_dev(ptr); | |
3496 | struct mlx5e_flow_steering *fs; | |
3497 | struct mlx5e_priv *peer_priv; | |
3498 | struct mlx5e_tc_table *tc; | |
3499 | struct mlx5e_priv *priv; | |
3500 | ||
3501 | if (ndev->netdev_ops != &mlx5e_netdev_ops || | |
3502 | event != NETDEV_UNREGISTER || | |
3503 | ndev->reg_state == NETREG_REGISTERED) | |
3504 | return NOTIFY_DONE; | |
3505 | ||
3506 | tc = container_of(this, struct mlx5e_tc_table, netdevice_nb); | |
3507 | fs = container_of(tc, struct mlx5e_flow_steering, tc); | |
3508 | priv = container_of(fs, struct mlx5e_priv, fs); | |
3509 | peer_priv = netdev_priv(ndev); | |
3510 | if (priv == peer_priv || | |
3511 | !(priv->netdev->features & NETIF_F_HW_TC)) | |
3512 | return NOTIFY_DONE; | |
3513 | ||
3514 | mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv); | |
3515 | ||
3516 | return NOTIFY_DONE; | |
3517 | } | |
3518 | ||
655dc3d2 | 3519 | int mlx5e_tc_nic_init(struct mlx5e_priv *priv) |
e8f887ac | 3520 | { |
acff797c | 3521 | struct mlx5e_tc_table *tc = &priv->fs.tc; |
4d8fcf21 | 3522 | int err; |
e8f887ac | 3523 | |
11c9c548 | 3524 | hash_init(tc->mod_hdr_tbl); |
5c65c564 | 3525 | hash_init(tc->hairpin_tbl); |
11c9c548 | 3526 | |
4d8fcf21 AH |
3527 | err = rhashtable_init(&tc->ht, &tc_ht_params); |
3528 | if (err) | |
3529 | return err; | |
3530 | ||
3531 | tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event; | |
3532 | if (register_netdevice_notifier(&tc->netdevice_nb)) { | |
3533 | tc->netdevice_nb.notifier_call = NULL; | |
3534 | mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n"); | |
3535 | } | |
3536 | ||
3537 | return err; | |
e8f887ac AV |
3538 | } |
3539 | ||
3540 | static void _mlx5e_tc_del_flow(void *ptr, void *arg) | |
3541 | { | |
3542 | struct mlx5e_tc_flow *flow = ptr; | |
655dc3d2 | 3543 | struct mlx5e_priv *priv = flow->priv; |
e8f887ac | 3544 | |
961e8979 | 3545 | mlx5e_tc_del_flow(priv, flow); |
e8f887ac AV |
3546 | kfree(flow); |
3547 | } | |
3548 | ||
655dc3d2 | 3549 | void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv) |
e8f887ac | 3550 | { |
acff797c | 3551 | struct mlx5e_tc_table *tc = &priv->fs.tc; |
e8f887ac | 3552 | |
4d8fcf21 AH |
3553 | if (tc->netdevice_nb.notifier_call) |
3554 | unregister_netdevice_notifier(&tc->netdevice_nb); | |
3555 | ||
d9ee0491 | 3556 | rhashtable_destroy(&tc->ht); |
e8f887ac | 3557 | |
acff797c MG |
3558 | if (!IS_ERR_OR_NULL(tc->t)) { |
3559 | mlx5_destroy_flow_table(tc->t); | |
3560 | tc->t = NULL; | |
e8f887ac AV |
3561 | } |
3562 | } | |
655dc3d2 OG |
3563 | |
3564 | int mlx5e_tc_esw_init(struct rhashtable *tc_ht) | |
3565 | { | |
3566 | return rhashtable_init(tc_ht, &tc_ht_params); | |
3567 | } | |
3568 | ||
3569 | void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht) | |
3570 | { | |
3571 | rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL); | |
3572 | } | |
01252a27 | 3573 | |
d9ee0491 | 3574 | int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags) |
01252a27 | 3575 | { |
d9ee0491 | 3576 | struct rhashtable *tc_ht = get_tc_ht(priv, flags); |
01252a27 OG |
3577 | |
3578 | return atomic_read(&tc_ht->nelems); | |
3579 | } | |
04de7dda RD |
3580 | |
3581 | void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw) | |
3582 | { | |
3583 | struct mlx5e_tc_flow *flow, *tmp; | |
3584 | ||
3585 | list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer) | |
3586 | __mlx5e_tc_del_fdb_peer_flow(flow); | |
3587 | } | |
b4a23329 RD |
3588 | |
3589 | void mlx5e_tc_reoffload_flows_work(struct work_struct *work) | |
3590 | { | |
3591 | struct mlx5_rep_uplink_priv *rpriv = | |
3592 | container_of(work, struct mlx5_rep_uplink_priv, | |
3593 | reoffload_flows_work); | |
3594 | struct mlx5e_tc_flow *flow, *tmp; | |
3595 | ||
3596 | rtnl_lock(); | |
3597 | list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) { | |
3598 | if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL)) | |
3599 | remove_unready_flow(flow); | |
3600 | } | |
3601 | rtnl_unlock(); | |
3602 | } |