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net/mlx5e: Use generic name for the forwarding dev pointer
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
e2394a61 34#include <net/flow_offload.h>
3f7d0eb4 35#include <net/sch_generic.h>
e3a2b7ed 36#include <net/pkt_cls.h>
e8f887ac
AV		 37#include <linux/mlx5/fs.h>
38#include <linux/mlx5/device.h>
39#include <linux/rhashtable.h>
5a7e5bcb 40#include <linux/refcount.h>
db76ca24 41#include <linux/completion.h>
fca572f2 42#include <linux/if_macvlan.h>
d79b6df6 43#include <net/tc_act/tc_pedit.h>
26c02749 44#include <net/tc_act/tc_csum.h>
41c2fd94 45#include <net/psample.h>
f6dfb4c3 46#include <net/arp.h>
3616d08b 47#include <net/ipv6_stubs.h>
f828ca6a 48#include <net/bareudp.h>
d34eb2fc 49#include <net/bonding.h>
e8f887ac 50#include "en.h"
f0da4daa 51#include "en/tc/post_act.h"
1d447a39 52#include "en_rep.h"
768c3667 53#include "en/rep/tc.h"
e2394a61 54#include "en/rep/neigh.h"
232c0013 55#include "en_tc.h"
03a9d11e 56#include "eswitch.h"
3f6d08d1 57#include "fs_core.h"
2c81bfd5 58#include "en/port.h"
101f4de9 59#include "en/tc_tun.h"
0a7fcb78 60#include "en/mapping.h"
4c3844d9 61#include "en/tc_ct.h"
b2fdf3d0 62#include "en/mod_hdr.h"
0d9f9647 63#include "en/tc_tun_encap.h"
0027d70c 64#include "en/tc/sample.h"
04de7dda 65#include "lib/devcom.h"
9272e3df 66#include "lib/geneve.h"
ae430332 67#include "lib/fs_chains.h"
7a978759 68#include "diag/en_tc_tracepoint.h"
1fe3e316 69#include <asm/div64.h>
016c8946
JK		 70#include "lag/lag.h"
71#include "lag/mp.h"
e8f887ac 72
6a064674 73#define nic_chains(priv) ((priv)->fs.tc.chains)
d65dbedf 74#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto)
17091853 75
acff797c 76#define MLX5E_TC_TABLE_NUM_GROUPS 4
6a064674 77#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
e8f887ac 78
8f1e0b97
PB		 79struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
80 [CHAIN_TO_REG] = {
81 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
82 .moffset = 0,
ed2fe7ba 83 .mlen = 16,
8f1e0b97 84 },
10742efc
VB		 85 [VPORT_TO_REG] = {
86 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
ed2fe7ba
PB		 87 .moffset = 16,
88 .mlen = 16,
10742efc 89 },
0a7fcb78
PB		 90 [TUNNEL_TO_REG] = {
91 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
ed2fe7ba
PB		 92 .moffset = 8,
93 .mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
0a7fcb78
PB		 94 .soffset = MLX5_BYTE_OFF(fte_match_param,
95 misc_parameters_2.metadata_reg_c_1),
96 },
4c3844d9 97 [ZONE_TO_REG] = zone_to_reg_ct,
a8eb919b 98 [ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
4c3844d9
PB		 99 [CTSTATE_TO_REG] = ctstate_to_reg_ct,
100 [MARK_TO_REG] = mark_to_reg_ct,
101 [LABELS_TO_REG] = labels_to_reg_ct,
102 [FTEID_TO_REG] = fteid_to_reg_ct,
39c538d6 103 /* For NIC rules we store the restore metadata directly
c7569097
AL		 104 * into reg_b that is passed to SW since we don't
105 * jump between steering domains.
106 */
107 [NIC_CHAIN_TO_REG] = {
108 .mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
109 .moffset = 0,
ed2fe7ba 110 .mlen = 16,
c7569097 111 },
aedd133d 112 [NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
8f1e0b97
PB		 113};
114
9ba33339
RD		 115/* To avoid false lock dependency warning set the tc_ht lock
116 * class different than the lock class of the ht being used when deleting
117 * last flow from a group and then deleting a group, we get into del_sw_flow_group()
118 * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
119 * it's different than the ht->mutex here.
120 */
121static struct lock_class_key tc_ht_lock_key;
122
0a7fcb78
PB		 123static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
124
125void
126mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
127 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 128 u32 val,
0a7fcb78
PB		 129 u32 mask)
130{
ed2fe7ba 131 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
0a7fcb78 132 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 133 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
0a7fcb78 134 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 135 u32 max_mask = GENMASK(match_len - 1, 0);
136 __be32 curr_mask_be, curr_val_be;
137 u32 curr_mask, curr_val;
0a7fcb78
PB		 138
139 fmask = headers_c + soffset;
140 fval = headers_v + soffset;
141
ed2fe7ba
PB		 142 memcpy(&curr_mask_be, fmask, 4);
143 memcpy(&curr_val_be, fval, 4);
144
145 curr_mask = be32_to_cpu(curr_mask_be);
146 curr_val = be32_to_cpu(curr_val_be);
147
148 //move to correct offset
149 WARN_ON(mask > max_mask);
150 mask <<= moffset;
151 val <<= moffset;
152 max_mask <<= moffset;
153
154 //zero val and mask
155 curr_mask &= ~max_mask;
156 curr_val &= ~max_mask;
0a7fcb78 157
ed2fe7ba
PB		 158 //add current to mask
159 curr_mask |= mask;
160 curr_val |= val;
161
162 //back to be32 and write
163 curr_mask_be = cpu_to_be32(curr_mask);
164 curr_val_be = cpu_to_be32(curr_val);
165
166 memcpy(fmask, &curr_mask_be, 4);
167 memcpy(fval, &curr_val_be, 4);
0a7fcb78
PB		 168
169 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
170}
171
7e36feeb
PB		 172void
173mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
174 enum mlx5e_tc_attr_to_reg type,
ed2fe7ba 175 u32 *val,
7e36feeb
PB		 176 u32 *mask)
177{
ed2fe7ba 178 void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
7e36feeb 179 int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
ed2fe7ba 180 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
7e36feeb 181 int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
ed2fe7ba
PB		 182 u32 max_mask = GENMASK(match_len - 1, 0);
183 __be32 curr_mask_be, curr_val_be;
184 u32 curr_mask, curr_val;
7e36feeb
PB		 185
186 fmask = headers_c + soffset;
187 fval = headers_v + soffset;
188
ed2fe7ba
PB		 189 memcpy(&curr_mask_be, fmask, 4);
190 memcpy(&curr_val_be, fval, 4);
191
192 curr_mask = be32_to_cpu(curr_mask_be);
193 curr_val = be32_to_cpu(curr_val_be);
7e36feeb 194
ed2fe7ba
PB		 195 *mask = (curr_mask >> moffset) & max_mask;
196 *val = (curr_val >> moffset) & max_mask;
7e36feeb
PB		 197}
198
0a7fcb78 199int
c7b9038d
VB		 200mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
201 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
202 enum mlx5_flow_namespace_type ns,
203 enum mlx5e_tc_attr_to_reg type,
204 u32 data)
0a7fcb78
PB		 205{
206 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
207 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
208 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
209 char *modact;
210 int err;
211
aedd133d 212 err = alloc_mod_hdr_actions(mdev, ns, mod_hdr_acts);
0a7fcb78
PB		 213 if (err)
214 return err;
215
216 modact = mod_hdr_acts->actions +
217 (mod_hdr_acts->num_actions * MLX5_MH_ACT_SZ);
218
219 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 220 if (mlen == 32)
0a7fcb78
PB		 221 mlen = 0;
222
223 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
224 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 225 MLX5_SET(set_action_in, modact, offset, moffset);
226 MLX5_SET(set_action_in, modact, length, mlen);
0a7fcb78 227 MLX5_SET(set_action_in, modact, data, data);
c7b9038d 228 err = mod_hdr_acts->num_actions;
0a7fcb78
PB		 229 mod_hdr_acts->num_actions++;
230
c7b9038d 231 return err;
0a7fcb78
PB		 232}
233
aedd133d
AL		 234static struct mlx5_tc_ct_priv *
235get_ct_priv(struct mlx5e_priv *priv)
236{
237 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
238 struct mlx5_rep_uplink_priv *uplink_priv;
239 struct mlx5e_rep_priv *uplink_rpriv;
240
e8711402 241 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 242 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
243 uplink_priv = &uplink_rpriv->uplink_priv;
244
245 return uplink_priv->ct_priv;
246 }
247
248 return priv->fs.tc.ct;
249}
250
0027d70c 251static struct mlx5e_tc_psample *
f94d6389
CM		 252get_sample_priv(struct mlx5e_priv *priv)
253{
254 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
255 struct mlx5_rep_uplink_priv *uplink_priv;
256 struct mlx5e_rep_priv *uplink_rpriv;
257
258 if (is_mdev_switchdev_mode(priv->mdev)) {
259 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
260 uplink_priv = &uplink_rpriv->uplink_priv;
261
0027d70c 262 return uplink_priv->tc_psample;
f94d6389
CM		 263 }
264
265 return NULL;
266}
f94d6389 267
aedd133d
AL		 268struct mlx5_flow_handle *
269mlx5_tc_rule_insert(struct mlx5e_priv *priv,
270 struct mlx5_flow_spec *spec,
271 struct mlx5_flow_attr *attr)
272{
273 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
274
e8711402 275 if (is_mdev_switchdev_mode(priv->mdev))
aedd133d
AL		 276 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
277
278 return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
279}
280
281void
282mlx5_tc_rule_delete(struct mlx5e_priv *priv,
283 struct mlx5_flow_handle *rule,
284 struct mlx5_flow_attr *attr)
285{
286 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
287
e8711402 288 if (is_mdev_switchdev_mode(priv->mdev)) {
aedd133d
AL		 289 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
290
291 return;
292 }
293
294 mlx5e_del_offloaded_nic_rule(priv, rule, attr);
295}
296
c7b9038d
VB		 297int
298mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
299 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
300 enum mlx5_flow_namespace_type ns,
301 enum mlx5e_tc_attr_to_reg type,
302 u32 data)
303{
304 int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
305
306 return ret < 0 ? ret : 0;
307}
308
309void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
310 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
311 enum mlx5e_tc_attr_to_reg type,
312 int act_id, u32 data)
313{
314 int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
315 int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
316 int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
317 char *modact;
318
319 modact = mod_hdr_acts->actions + (act_id * MLX5_MH_ACT_SZ);
320
321 /* Firmware has 5bit length field and 0 means 32bits */
ed2fe7ba 322 if (mlen == 32)
c7b9038d
VB		 323 mlen = 0;
324
325 MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
326 MLX5_SET(set_action_in, modact, field, mfield);
ed2fe7ba
PB		 327 MLX5_SET(set_action_in, modact, offset, moffset);
328 MLX5_SET(set_action_in, modact, length, mlen);
c7b9038d
VB		 329 MLX5_SET(set_action_in, modact, data, data);
330}
331
77ab67b7
OG		 332struct mlx5e_hairpin {
333 struct mlx5_hairpin *pair;
334
335 struct mlx5_core_dev *func_mdev;
3f6d08d1 336 struct mlx5e_priv *func_priv;
77ab67b7 337 u32 tdn;
a6696735 338 struct mlx5e_tir direct_tir;
3f6d08d1
OG		 339
340 int num_channels;
341 struct mlx5e_rqt indir_rqt;
a6696735 342 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
f4b45940 343 struct mlx5_ttc_table *ttc;
77ab67b7
OG		 344};
345
5c65c564
OG		 346struct mlx5e_hairpin_entry {
347 /* a node of a hash table which keeps all the hairpin entries */
348 struct hlist_node hairpin_hlist;
349
73edca73
VB		 350 /* protects flows list */
351 spinlock_t flows_lock;
5c65c564
OG		 352 /* flows sharing the same hairpin */
353 struct list_head flows;
db76ca24
VB		 354 /* hpe's that were not fully initialized when dead peer update event
355 * function traversed them.
356 */
357 struct list_head dead_peer_wait_list;
5c65c564 358
d8822868 359 u16 peer_vhca_id;
106be53b 360 u8 prio;
5c65c564 361 struct mlx5e_hairpin *hp;
e4f9abbd 362 refcount_t refcnt;
db76ca24 363 struct completion res_ready;
5c65c564
OG		 364};
365
5a7e5bcb
VB		 366static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
367 struct mlx5e_tc_flow *flow);
368
0d9f9647 369struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 370{
371 if (!flow || !refcount_inc_not_zero(&flow->refcnt))
372 return ERR_PTR(-EINVAL);
373 return flow;
374}
375
0d9f9647 376void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
5a7e5bcb
VB		 377{
378 if (refcount_dec_and_test(&flow->refcnt)) {
379 mlx5e_tc_del_flow(priv, flow);
c5d326b2 380 kfree_rcu(flow, rcu_head);
5a7e5bcb
VB		 381 }
382}
383
aedd133d 384bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 385{
386 return flow_flag_test(flow, ESWITCH);
387}
388
84179981
PB		 389static bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
390{
391 return flow_flag_test(flow, FT);
392}
393
0d9f9647 394bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
226f2ca3
VB		 395{
396 return flow_flag_test(flow, OFFLOADED);
397}
398
b2fdf3d0 399static int get_flow_name_space(struct mlx5e_tc_flow *flow)
11c9c548 400{
b2fdf3d0
PB		 401 return mlx5e_is_eswitch_flow(flow) ?
402 MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
11c9c548
OG		 403}
404
dd58edc3 405static struct mod_hdr_tbl *
b2fdf3d0 406get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
dd58edc3
VB		 407{
408 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
409
b2fdf3d0
PB		 410 return get_flow_name_space(flow) == MLX5_FLOW_NAMESPACE_FDB ?
411 &esw->offloads.mod_hdr :
dd58edc3
VB		 412 &priv->fs.tc.mod_hdr;
413}
414
11c9c548
OG		 415static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
416 struct mlx5e_tc_flow *flow,
417 struct mlx5e_tc_flow_parse_attr *parse_attr)
418{
b2fdf3d0
PB		 419 struct mlx5_modify_hdr *modify_hdr;
420 struct mlx5e_mod_hdr_handle *mh;
11c9c548 421
b2fdf3d0
PB		 422 mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
423 get_flow_name_space(flow),
424 &parse_attr->mod_hdr_acts);
425 if (IS_ERR(mh))
426 return PTR_ERR(mh);
11c9c548 427
b2fdf3d0 428 modify_hdr = mlx5e_mod_hdr_get(mh);
c620b772 429 flow->attr->modify_hdr = modify_hdr;
b2fdf3d0 430 flow->mh = mh;
11c9c548
OG		 431
432 return 0;
11c9c548
OG		 433}
434
435static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
436 struct mlx5e_tc_flow *flow)
437{
5a7e5bcb 438 /* flow wasn't fully initialized */
dd58edc3 439 if (!flow->mh)
5a7e5bcb
VB		 440 return;
441
b2fdf3d0
PB		 442 mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
443 flow->mh);
dd58edc3 444 flow->mh = NULL;
11c9c548
OG		 445}
446
77ab67b7
OG		 447static
448struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
449{
b1c2f631 450 struct mlx5_core_dev *mdev;
77ab67b7
OG		 451 struct net_device *netdev;
452 struct mlx5e_priv *priv;
453
b1c2f631
DC		 454 netdev = dev_get_by_index(net, ifindex);
455 if (!netdev)
456 return ERR_PTR(-ENODEV);
457
77ab67b7 458 priv = netdev_priv(netdev);
b1c2f631
DC		 459 mdev = priv->mdev;
460 dev_put(netdev);
461
462 /* Mirred tc action holds a refcount on the ifindex net_device (see
463 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
464 * after dev_put(netdev), while we're in the context of adding a tc flow.
465 *
466 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
467 * stored in a hairpin object, which exists until all flows, that refer to it, get
468 * removed.
469 *
470 * On the other hand, after a hairpin object has been created, the peer net_device may
471 * be removed/unbound while there are still some hairpin flows that are using it. This
472 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
473 * NETDEV_UNREGISTER event of the peer net_device.
474 */
475 return mdev;
77ab67b7
OG		 476}
477
478static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
479{
a6696735 480 struct mlx5e_tir_builder *builder;
77ab67b7
OG		 481 int err;
482
a6696735
MM		 483 builder = mlx5e_tir_builder_alloc(false);
484 if (!builder)
485 return -ENOMEM;
486
77ab67b7
OG		 487 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
488 if (err)
a6696735 489 goto out;
77ab67b7 490
a6696735
MM		 491 mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
492 err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
77ab67b7
OG		 493 if (err)
494 goto create_tir_err;
495
a6696735
MM		 496out:
497 mlx5e_tir_builder_free(builder);
498 return err;
77ab67b7
OG		 499
500create_tir_err:
501 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
a6696735
MM		 502
503 goto out;
77ab67b7
OG		 504}
505
506static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
507{
a6696735 508 mlx5e_tir_destroy(&hp->direct_tir);
77ab67b7
OG		 509 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
510}
511
3f6d08d1
OG		 512static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
513{
3f6d08d1
OG		 514 struct mlx5e_priv *priv = hp->func_priv;
515 struct mlx5_core_dev *mdev = priv->mdev;
06e9f13a
MM		 516 struct mlx5e_rss_params_indir *indir;
517 int err;
3f6d08d1 518
06e9f13a
MM		 519 indir = kvmalloc(sizeof(*indir), GFP_KERNEL);
520 if (!indir)
3f6d08d1
OG		 521 return -ENOMEM;
522
43befe99 523 mlx5e_rss_params_indir_init_uniform(indir, hp->num_channels);
06e9f13a 524 err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, hp->num_channels,
43ec0f41
MM		 525 mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
526 indir);
3f6d08d1 527
06e9f13a 528 kvfree(indir);
3f6d08d1
OG		 529 return err;
530}
531
532static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
533{
534 struct mlx5e_priv *priv = hp->func_priv;
43ec0f41 535 struct mlx5e_rss_params_hash rss_hash;
d443c6f6 536 enum mlx5_traffic_types tt, max_tt;
a6696735
MM		 537 struct mlx5e_tir_builder *builder;
538 int err = 0;
539
540 builder = mlx5e_tir_builder_alloc(false);
541 if (!builder)
542 return -ENOMEM;
543
43ec0f41 544 rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
3f6d08d1
OG		 545
546 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
65d6b6e5 547 struct mlx5e_rss_params_traffic_type rss_tt;
d930ac79 548
65d6b6e5 549 rss_tt = mlx5e_rss_get_default_tt_config(tt);
3f6d08d1 550
a6696735
MM		 551 mlx5e_tir_builder_build_rqt(builder, hp->tdn,
552 mlx5e_rqt_get_rqtn(&hp->indir_rqt),
553 false);
43ec0f41 554 mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
bbeb53b8 555
a6696735 556 err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
3f6d08d1
OG		 557 if (err) {
558 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
559 goto err_destroy_tirs;
560 }
a6696735
MM		 561
562 mlx5e_tir_builder_clear(builder);
3f6d08d1 563 }
3f6d08d1 564
a6696735
MM		 565out:
566 mlx5e_tir_builder_free(builder);
3f6d08d1 567 return err;
a6696735
MM		 568
569err_destroy_tirs:
570 max_tt = tt;
571 for (tt = 0; tt < max_tt; tt++)
572 mlx5e_tir_destroy(&hp->indir_tir[tt]);
573
574 goto out;
3f6d08d1
OG		 575}
576
577static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
578{
579 int tt;
580
581 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
a6696735 582 mlx5e_tir_destroy(&hp->indir_tir[tt]);
3f6d08d1
OG		 583}
584
585static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
586 struct ttc_params *ttc_params)
587{
588 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
589 int tt;
590
591 memset(ttc_params, 0, sizeof(*ttc_params));
592
bc29764e
MG		 593 ttc_params->ns = mlx5_get_flow_namespace(hp->func_mdev,
594 MLX5_FLOW_NAMESPACE_KERNEL);
595 for (tt = 0; tt < MLX5_NUM_TT; tt++) {
596 ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
597 ttc_params->dests[tt].tir_num =
598 tt == MLX5_TT_ANY ?
599 mlx5e_tir_get_tirn(&hp->direct_tir) :
600 mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
601 }
3f6d08d1 602
3f6d08d1
OG		 603 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
604 ft_attr->prio = MLX5E_TC_PRIO;
605}
606
607static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
608{
609 struct mlx5e_priv *priv = hp->func_priv;
610 struct ttc_params ttc_params;
611 int err;
612
613 err = mlx5e_hairpin_create_indirect_rqt(hp);
614 if (err)
615 return err;
616
617 err = mlx5e_hairpin_create_indirect_tirs(hp);
618 if (err)
619 goto err_create_indirect_tirs;
620
621 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
f4b45940
MG		 622 hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
623 if (IS_ERR(hp->ttc)) {
624 err = PTR_ERR(hp->ttc);
3f6d08d1 625 goto err_create_ttc_table;
f4b45940 626 }
3f6d08d1
OG		 627
628 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
f4b45940
MG		 629 hp->num_channels,
630 mlx5_get_ttc_flow_table(priv->fs.ttc)->id);
3f6d08d1
OG		 631
632 return 0;
633
634err_create_ttc_table:
635 mlx5e_hairpin_destroy_indirect_tirs(hp);
636err_create_indirect_tirs:
06e9f13a 637 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 638
639 return err;
640}
641
642static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
643{
f4b45940 644 mlx5_destroy_ttc_table(hp->ttc);
3f6d08d1 645 mlx5e_hairpin_destroy_indirect_tirs(hp);
06e9f13a 646 mlx5e_rqt_destroy(&hp->indir_rqt);
3f6d08d1
OG		 647}
648
77ab67b7
OG		 649static struct mlx5e_hairpin *
650mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
651 int peer_ifindex)
652{
653 struct mlx5_core_dev *func_mdev, *peer_mdev;
654 struct mlx5e_hairpin *hp;
655 struct mlx5_hairpin *pair;
656 int err;
657
658 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
659 if (!hp)
660 return ERR_PTR(-ENOMEM);
661
662 func_mdev = priv->mdev;
663 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 664 if (IS_ERR(peer_mdev)) {
665 err = PTR_ERR(peer_mdev);
666 goto create_pair_err;
667 }
77ab67b7
OG		 668
669 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
670 if (IS_ERR(pair)) {
671 err = PTR_ERR(pair);
672 goto create_pair_err;
673 }
674 hp->pair = pair;
675 hp->func_mdev = func_mdev;
3f6d08d1
OG		 676 hp->func_priv = priv;
677 hp->num_channels = params->num_channels;
77ab67b7
OG		 678
679 err = mlx5e_hairpin_create_transport(hp);
680 if (err)
681 goto create_transport_err;
682
3f6d08d1
OG		 683 if (hp->num_channels > 1) {
684 err = mlx5e_hairpin_rss_init(hp);
685 if (err)
686 goto rss_init_err;
687 }
688
77ab67b7
OG		 689 return hp;
690
3f6d08d1
OG		 691rss_init_err:
692 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 693create_transport_err:
694 mlx5_core_hairpin_destroy(hp->pair);
695create_pair_err:
696 kfree(hp);
697 return ERR_PTR(err);
698}
699
700static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
701{
3f6d08d1
OG		 702 if (hp->num_channels > 1)
703 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 704 mlx5e_hairpin_destroy_transport(hp);
705 mlx5_core_hairpin_destroy(hp->pair);
706 kvfree(hp);
707}
708
106be53b
OG		 709static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
710{
711 return (peer_vhca_id << 16 | prio);
712}
713
5c65c564 714static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 715 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 716{
717 struct mlx5e_hairpin_entry *hpe;
106be53b 718 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 719
720 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b 721 hairpin_hlist, hash_key) {
e4f9abbd
VB		 722 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
723 refcount_inc(&hpe->refcnt);
5c65c564 724 return hpe;
e4f9abbd 725 }
5c65c564
OG		 726 }
727
728 return NULL;
729}
730
e4f9abbd
VB		 731static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
732 struct mlx5e_hairpin_entry *hpe)
733{
734 /* no more hairpin flows for us, release the hairpin pair */
b32accda 735 if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &priv->fs.tc.hairpin_tbl_lock))
e4f9abbd 736 return;
b32accda
VB		 737 hash_del(&hpe->hairpin_hlist);
738 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
e4f9abbd 739
db76ca24
VB		 740 if (!IS_ERR_OR_NULL(hpe->hp)) {
741 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
742 dev_name(hpe->hp->pair->peer_mdev->device));
743
744 mlx5e_hairpin_destroy(hpe->hp);
745 }
e4f9abbd
VB		 746
747 WARN_ON(!list_empty(&hpe->flows));
e4f9abbd
VB		 748 kfree(hpe);
749}
750
106be53b
OG		 751#define UNKNOWN_MATCH_PRIO 8
752
753static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 754 struct mlx5_flow_spec *spec, u8 *match_prio,
755 struct netlink_ext_ack *extack)
106be53b
OG		 756{
757 void *headers_c, *headers_v;
758 u8 prio_val, prio_mask = 0;
759 bool vlan_present;
760
761#ifdef CONFIG_MLX5_CORE_EN_DCB
762 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 763 NL_SET_ERR_MSG_MOD(extack,
764 "only PCP trust state supported for hairpin");
106be53b
OG		 765 return -EOPNOTSUPP;
766 }
767#endif
768 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
769 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
770
771 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
772 if (vlan_present) {
773 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
774 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
775 }
776
777 if (!vlan_present || !prio_mask) {
778 prio_val = UNKNOWN_MATCH_PRIO;
779 } else if (prio_mask != 0x7) {
e98bedf5
EB		 780 NL_SET_ERR_MSG_MOD(extack,
781 "masked priority match not supported for hairpin");
106be53b
OG		 782 return -EOPNOTSUPP;
783 }
784
785 *match_prio = prio_val;
786 return 0;
787}
788
5c65c564
OG		 789static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
790 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 791 struct mlx5e_tc_flow_parse_attr *parse_attr,
792 struct netlink_ext_ack *extack)
5c65c564 793{
98b66cb1 794 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 795 struct mlx5_hairpin_params params;
d8822868 796 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 797 struct mlx5e_hairpin_entry *hpe;
798 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 799 u64 link_speed64;
800 u32 link_speed;
106be53b 801 u8 match_prio;
d8822868 802 u16 peer_id;
5c65c564
OG		 803 int err;
804
d8822868 805 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
b1c2f631
DC		 806 if (IS_ERR(peer_mdev)) {
807 NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
808 return PTR_ERR(peer_mdev);
809 }
810
d8822868 811 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 812 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 813 return -EOPNOTSUPP;
814 }
815
d8822868 816 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 817 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
818 extack);
106be53b
OG		 819 if (err)
820 return err;
b32accda
VB		 821
822 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
106be53b 823 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
db76ca24
VB		 824 if (hpe) {
825 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
826 wait_for_completion(&hpe->res_ready);
827
828 if (IS_ERR(hpe->hp)) {
829 err = -EREMOTEIO;
830 goto out_err;
831 }
5c65c564 832 goto attach_flow;
db76ca24 833 }
5c65c564
OG		 834
835 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
b32accda 836 if (!hpe) {
db76ca24
VB		 837 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
838 return -ENOMEM;
b32accda 839 }
5c65c564 840
73edca73 841 spin_lock_init(&hpe->flows_lock);
5c65c564 842 INIT_LIST_HEAD(&hpe->flows);
db76ca24 843 INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
d8822868 844 hpe->peer_vhca_id = peer_id;
106be53b 845 hpe->prio = match_prio;
e4f9abbd 846 refcount_set(&hpe->refcnt, 1);
db76ca24
VB		 847 init_completion(&hpe->res_ready);
848
849 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
850 hash_hairpin_info(peer_id, match_prio));
851 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
5c65c564 852
6cdc686a 853 params.log_data_size = 16;
5c65c564
OG		 854 params.log_data_size = min_t(u8, params.log_data_size,
855 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
856 params.log_data_size = max_t(u8, params.log_data_size,
857 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 858
eb9180f7
OG		 859 params.log_num_packets = params.log_data_size -
860 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
861 params.log_num_packets = min_t(u8, params.log_num_packets,
862 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
863
864 params.q_counter = priv->q_counter;
3f6d08d1 865 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 866 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 867 link_speed = max_t(u32, link_speed, 50000);
868 link_speed64 = link_speed;
869 do_div(link_speed64, 50000);
870 params.num_channels = link_speed64;
871
5c65c564 872 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
db76ca24
VB		 873 hpe->hp = hp;
874 complete_all(&hpe->res_ready);
5c65c564
OG		 875 if (IS_ERR(hp)) {
876 err = PTR_ERR(hp);
db76ca24 877 goto out_err;
5c65c564
OG		 878 }
879
eb9180f7 880 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
a6696735 881 mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
27b942fb 882 dev_name(hp->pair->peer_mdev->device),
eb9180f7 883 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564 884
5c65c564 885attach_flow:
3f6d08d1 886 if (hpe->hp->num_channels > 1) {
226f2ca3 887 flow_flag_set(flow, HAIRPIN_RSS);
f4b45940
MG		 888 flow->attr->nic_attr->hairpin_ft =
889 mlx5_get_ttc_flow_table(hpe->hp->ttc);
3f6d08d1 890 } else {
a6696735 891 flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
3f6d08d1 892 }
b32accda 893
e4f9abbd 894 flow->hpe = hpe;
73edca73 895 spin_lock(&hpe->flows_lock);
5c65c564 896 list_add(&flow->hairpin, &hpe->flows);
73edca73 897 spin_unlock(&hpe->flows_lock);
3f6d08d1 898
5c65c564
OG		 899 return 0;
900
db76ca24
VB		 901out_err:
902 mlx5e_hairpin_put(priv, hpe);
5c65c564
OG		 903 return err;
904}
905
906static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
907 struct mlx5e_tc_flow *flow)
908{
5a7e5bcb 909 /* flow wasn't fully initialized */
e4f9abbd 910 if (!flow->hpe)
5a7e5bcb
VB		 911 return;
912
73edca73 913 spin_lock(&flow->hpe->flows_lock);
5c65c564 914 list_del(&flow->hairpin);
73edca73
VB		 915 spin_unlock(&flow->hpe->flows_lock);
916
e4f9abbd
VB		 917 mlx5e_hairpin_put(priv, flow->hpe);
918 flow->hpe = NULL;
5c65c564
OG		 919}
920
08247066
AL		 921struct mlx5_flow_handle *
922mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
923 struct mlx5_flow_spec *spec,
c620b772 924 struct mlx5_flow_attr *attr)
e8f887ac 925{
08247066 926 struct mlx5_flow_context *flow_context = &spec->flow_context;
c7569097 927 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
c620b772 928 struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
6a064674 929 struct mlx5e_tc_table *tc = &priv->fs.tc;
5c65c564 930 struct mlx5_flow_destination dest[2] = {};
66958ed9 931 struct mlx5_flow_act flow_act = {
3bc4b7bf 932 .action = attr->action,
bb0ee7dc 933 .flags = FLOW_ACT_NO_APPEND,
66958ed9 934 };
08247066 935 struct mlx5_flow_handle *rule;
c7569097 936 struct mlx5_flow_table *ft;
08247066 937 int dest_ix = 0;
e8f887ac 938
bb0ee7dc 939 flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
c620b772 940 flow_context->flow_tag = nic_attr->flow_tag;
bb0ee7dc 941
aedd133d
AL		 942 if (attr->dest_ft) {
943 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
944 dest[dest_ix].ft = attr->dest_ft;
945 dest_ix++;
946 } else if (nic_attr->hairpin_ft) {
08247066 947 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c620b772 948 dest[dest_ix].ft = nic_attr->hairpin_ft;
08247066 949 dest_ix++;
c620b772 950 } else if (nic_attr->hairpin_tirn) {
08247066 951 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
c620b772 952 dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
5c65c564 953 dest_ix++;
3f6d08d1
OG		 954 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
955 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
c7569097
AL		 956 if (attr->dest_chain) {
957 dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
958 attr->dest_chain, 1,
959 MLX5E_TC_FT_LEVEL);
960 if (IS_ERR(dest[dest_ix].ft))
961 return ERR_CAST(dest[dest_ix].ft);
962 } else {
6783f0a2 963 dest[dest_ix].ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c7569097 964 }
3f6d08d1 965 dest_ix++;
5c65c564 966 }
aad7e08d 967
c7569097
AL		 968 if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
969 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
970 flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
971
08247066 972 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
5c65c564 973 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
08247066 974 dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
5c65c564 975 dest_ix++;
aad7e08d
AV		 976 }
977
08247066 978 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2b688ea5 979 flow_act.modify_hdr = attr->modify_hdr;
2f4fe4ca 980
6a064674
AL		 981 mutex_lock(&tc->t_lock);
982 if (IS_ERR_OR_NULL(tc->t)) {
983 /* Create the root table here if doesn't exist yet */
984 tc->t =
c7569097 985 mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
6a064674
AL		 986
987 if (IS_ERR(tc->t)) {
988 mutex_unlock(&tc->t_lock);
e8f887ac
AV		 989 netdev_err(priv->netdev,
990 "Failed to create tc offload table\n");
c7569097
AL		 991 rule = ERR_CAST(priv->fs.tc.t);
992 goto err_ft_get;
e8f887ac 993 }
e8f887ac 994 }
08247066 995 mutex_unlock(&tc->t_lock);
e8f887ac 996
aedd133d
AL		 997 if (attr->chain || attr->prio)
998 ft = mlx5_chains_get_table(nic_chains,
999 attr->chain, attr->prio,
1000 MLX5E_TC_FT_LEVEL);
1001 else
1002 ft = attr->ft;
1003
c7569097
AL		 1004 if (IS_ERR(ft)) {
1005 rule = ERR_CAST(ft);
1006 goto err_ft_get;
1007 }
1008
c620b772 1009 if (attr->outer_match_level != MLX5_MATCH_NONE)
08247066 1010 spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
38aa51c1 1011
c7569097 1012 rule = mlx5_add_flow_rules(ft, spec,
08247066
AL		 1013 &flow_act, dest, dest_ix);
1014 if (IS_ERR(rule))
c7569097 1015 goto err_rule;
08247066
AL		 1016
1017 return rule;
c7569097
AL		 1018
1019err_rule:
aedd133d
AL		 1020 if (attr->chain || attr->prio)
1021 mlx5_chains_put_table(nic_chains,
1022 attr->chain, attr->prio,
1023 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1024err_ft_get:
1025 if (attr->dest_chain)
1026 mlx5_chains_put_table(nic_chains,
1027 attr->dest_chain, 1,
1028 MLX5E_TC_FT_LEVEL);
1029
1030 return ERR_CAST(rule);
08247066
AL		 1031}
1032
1033static int
1034mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
08247066
AL		 1035 struct mlx5e_tc_flow *flow,
1036 struct netlink_ext_ack *extack)
1037{
c6cfe113 1038 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 1039 struct mlx5_flow_attr *attr = flow->attr;
08247066 1040 struct mlx5_core_dev *dev = priv->mdev;
97a8d29a 1041 struct mlx5_fc *counter;
08247066
AL		 1042 int err;
1043
c6cfe113
RD		 1044 parse_attr = attr->parse_attr;
1045
08247066
AL		 1046 if (flow_flag_test(flow, HAIRPIN)) {
1047 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1048 if (err)
1049 return err;
1050 }
1051
1052 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1053 counter = mlx5_fc_create(dev, true);
1054 if (IS_ERR(counter))
1055 return PTR_ERR(counter);
1056
1057 attr->counter = counter;
1058 }
1059
1060 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1061 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1062 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
1063 if (err)
1064 return err;
1065 }
1066
aedd133d
AL		 1067 if (flow_flag_test(flow, CT))
1068 flow->rule[0] = mlx5_tc_ct_flow_offload(get_ct_priv(priv), flow, &parse_attr->spec,
1069 attr, &parse_attr->mod_hdr_acts);
1070 else
1071 flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec,
1072 attr);
aad7e08d 1073
a2b7189b 1074 return PTR_ERR_OR_ZERO(flow->rule[0]);
e8f887ac
AV		 1075}
1076
08247066 1077void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
c7569097
AL		 1078 struct mlx5_flow_handle *rule,
1079 struct mlx5_flow_attr *attr)
08247066 1080{
c7569097
AL		 1081 struct mlx5_fs_chains *nic_chains = nic_chains(priv);
1082
08247066 1083 mlx5_del_flow_rules(rule);
c7569097 1084
aedd133d
AL		 1085 if (attr->chain || attr->prio)
1086 mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1087 MLX5E_TC_FT_LEVEL);
c7569097
AL		 1088
1089 if (attr->dest_chain)
1090 mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1091 MLX5E_TC_FT_LEVEL);
08247066
AL		 1092}
1093
d85cdccb
OG		 1094static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1095 struct mlx5e_tc_flow *flow)
1096{
c620b772 1097 struct mlx5_flow_attr *attr = flow->attr;
6a064674 1098 struct mlx5e_tc_table *tc = &priv->fs.tc;
d85cdccb 1099
c7569097
AL		 1100 flow_flag_clear(flow, OFFLOADED);
1101
aedd133d
AL		 1102 if (flow_flag_test(flow, CT))
1103 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1104 else if (!IS_ERR_OR_NULL(flow->rule[0]))
1105 mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1106
c7569097
AL		 1107 /* Remove root table if no rules are left to avoid
1108 * extra steering hops.
1109 */
b6fac0b4 1110 mutex_lock(&priv->fs.tc.t_lock);
6a064674
AL		 1111 if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1112 !IS_ERR_OR_NULL(tc->t)) {
1113 mlx5_chains_put_table(nic_chains(priv), 0, 1, MLX5E_TC_FT_LEVEL);
d85cdccb
OG		 1114 priv->fs.tc.t = NULL;
1115 }
b6fac0b4 1116 mutex_unlock(&priv->fs.tc.t_lock);
2f4fe4ca 1117
aedd133d
AL		 1118 kvfree(attr->parse_attr);
1119
513f8f7f 1120 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 1121 mlx5e_detach_mod_hdr(priv, flow);
5c65c564 1122
aedd133d
AL		 1123 mlx5_fc_destroy(priv->mdev, attr->counter);
1124
226f2ca3 1125 if (flow_flag_test(flow, HAIRPIN))
5c65c564 1126 mlx5e_hairpin_flow_del(priv, flow);
c620b772
AL		 1127
1128 kfree(flow->attr);
d85cdccb
OG		 1129}
1130
0d9f9647 1131struct mlx5_flow_handle *
6d2a3ed0
OG		 1132mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1133 struct mlx5e_tc_flow *flow,
1134 struct mlx5_flow_spec *spec,
c620b772 1135 struct mlx5_flow_attr *attr)
6d2a3ed0 1136{
1ef3018f 1137 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
6d2a3ed0 1138 struct mlx5_flow_handle *rule;
4c3844d9 1139
89e39467
PB		 1140 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1141 return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1142
1ef3018f
PB		 1143 if (flow_flag_test(flow, CT)) {
1144 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1145
69e2916e 1146 rule = mlx5_tc_ct_flow_offload(get_ct_priv(flow->priv),
aedd133d 1147 flow, spec, attr,
1ef3018f 1148 mod_hdr_acts);
f94d6389 1149 } else if (flow_flag_test(flow, SAMPLE)) {
ee950e5d
CM		 1150 rule = mlx5e_tc_sample_offload(get_sample_priv(flow->priv), spec, attr,
1151 mlx5e_tc_get_flow_tun_id(flow));
69e2916e
PB		 1152 } else {
1153 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1ef3018f 1154 }
6d2a3ed0 1155
6d2a3ed0
OG		 1156 if (IS_ERR(rule))
1157 return rule;
1158
c620b772 1159 if (attr->esw_attr->split_count) {
6d2a3ed0
OG		 1160 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1161 if (IS_ERR(flow->rule[1])) {
69e2916e
PB		 1162 if (flow_flag_test(flow, CT))
1163 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
1164 else
1165 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
6d2a3ed0
OG		 1166 return flow->rule[1];
1167 }
1168 }
1169
6d2a3ed0
OG		 1170 return rule;
1171}
1172
0d9f9647
VB		 1173void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1174 struct mlx5e_tc_flow *flow,
1175 struct mlx5_flow_attr *attr)
6d2a3ed0 1176{
226f2ca3 1177 flow_flag_clear(flow, OFFLOADED);
6d2a3ed0 1178
89e39467
PB		 1179 if (attr->flags & MLX5_ESW_ATTR_FLAG_SLOW_PATH)
1180 goto offload_rule_0;
1181
4c3844d9 1182 if (flow_flag_test(flow, CT)) {
aedd133d 1183 mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), flow, attr);
4c3844d9
PB		 1184 return;
1185 }
1186
f94d6389 1187 if (flow_flag_test(flow, SAMPLE)) {
0027d70c 1188 mlx5e_tc_sample_unoffload(get_sample_priv(flow->priv), flow->rule[0], attr);
f94d6389
CM		 1189 return;
1190 }
f94d6389 1191
c620b772 1192 if (attr->esw_attr->split_count)
6d2a3ed0
OG		 1193 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1194
89e39467 1195offload_rule_0:
6d2a3ed0
OG		 1196 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1197}
1198
0d9f9647 1199struct mlx5_flow_handle *
5dbe906f
PB		 1200mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1201 struct mlx5e_tc_flow *flow,
178f69b4 1202 struct mlx5_flow_spec *spec)
5dbe906f 1203{
c620b772 1204 struct mlx5_flow_attr *slow_attr;
5dbe906f
PB		 1205 struct mlx5_flow_handle *rule;
1206
c620b772
AL		 1207 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1208 if (!slow_attr)
1209 return ERR_PTR(-ENOMEM);
5dbe906f 1210
c620b772
AL		 1211 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1212 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1213 slow_attr->esw_attr->split_count = 0;
1214 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1215
1216 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
5dbe906f 1217 if (!IS_ERR(rule))
226f2ca3 1218 flow_flag_set(flow, SLOW);
5dbe906f 1219
c620b772
AL		 1220 kfree(slow_attr);
1221
5dbe906f
PB		 1222 return rule;
1223}
1224
0d9f9647
VB		 1225void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1226 struct mlx5e_tc_flow *flow)
5dbe906f 1227{
c620b772 1228 struct mlx5_flow_attr *slow_attr;
178f69b4 1229
c620b772 1230 slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
5efbe617
AL		 1231 if (!slow_attr) {
1232 mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1233 return;
1234 }
c620b772
AL		 1235
1236 memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1237 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1238 slow_attr->esw_attr->split_count = 0;
1239 slow_attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
1240 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
226f2ca3 1241 flow_flag_clear(flow, SLOW);
c620b772 1242 kfree(slow_attr);
5dbe906f
PB		 1243}
1244
ad86755b
VB		 1245/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1246 * function.
1247 */
1248static void unready_flow_add(struct mlx5e_tc_flow *flow,
1249 struct list_head *unready_flows)
1250{
1251 flow_flag_set(flow, NOT_READY);
1252 list_add_tail(&flow->unready, unready_flows);
1253}
1254
1255/* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1256 * function.
1257 */
1258static void unready_flow_del(struct mlx5e_tc_flow *flow)
1259{
1260 list_del(&flow->unready);
1261 flow_flag_clear(flow, NOT_READY);
1262}
1263
b4a23329
RD		 1264static void add_unready_flow(struct mlx5e_tc_flow *flow)
1265{
1266 struct mlx5_rep_uplink_priv *uplink_priv;
1267 struct mlx5e_rep_priv *rpriv;
1268 struct mlx5_eswitch *esw;
1269
1270 esw = flow->priv->mdev->priv.eswitch;
1271 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1272 uplink_priv = &rpriv->uplink_priv;
1273
ad86755b
VB		 1274 mutex_lock(&uplink_priv->unready_flows_lock);
1275 unready_flow_add(flow, &uplink_priv->unready_flows);
1276 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1277}
1278
1279static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1280{
ad86755b
VB		 1281 struct mlx5_rep_uplink_priv *uplink_priv;
1282 struct mlx5e_rep_priv *rpriv;
1283 struct mlx5_eswitch *esw;
1284
1285 esw = flow->priv->mdev->priv.eswitch;
1286 rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1287 uplink_priv = &rpriv->uplink_priv;
1288
1289 mutex_lock(&uplink_priv->unready_flows_lock);
1290 unready_flow_del(flow);
1291 mutex_unlock(&uplink_priv->unready_flows_lock);
b4a23329
RD		 1292}
1293
10742efc
VB		 1294static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv);
1295
a508728a 1296bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
10742efc
VB		 1297{
1298 struct mlx5_core_dev *out_mdev, *route_mdev;
1299 struct mlx5e_priv *out_priv, *route_priv;
1300
1301 out_priv = netdev_priv(out_dev);
1302 out_mdev = out_priv->mdev;
1303 route_priv = netdev_priv(route_dev);
1304 route_mdev = route_priv->mdev;
1305
1306 if (out_mdev->coredev_type != MLX5_COREDEV_PF ||
1307 route_mdev->coredev_type != MLX5_COREDEV_VF)
1308 return false;
1309
1310 return same_hw_devs(out_priv, route_priv);
1311}
1312
a508728a 1313int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
10742efc
VB		 1314{
1315 struct mlx5e_priv *out_priv, *route_priv;
f9d196bd 1316 struct mlx5_devcom *devcom = NULL;
10742efc
VB		 1317 struct mlx5_core_dev *route_mdev;
1318 struct mlx5_eswitch *esw;
1319 u16 vhca_id;
1320 int err;
1321
1322 out_priv = netdev_priv(out_dev);
1323 esw = out_priv->mdev->priv.eswitch;
1324 route_priv = netdev_priv(route_dev);
1325 route_mdev = route_priv->mdev;
1326
1327 vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
f9d196bd
DL		 1328 if (mlx5_lag_is_active(out_priv->mdev)) {
1329 /* In lag case we may get devices from different eswitch instances.
1330 * If we failed to get vport num, it means, mostly, that we on the wrong
1331 * eswitch.
1332 */
1333 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1334 if (err != -ENOENT)
1335 return err;
1336
1337 devcom = out_priv->mdev->priv.devcom;
1338 esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1339 if (!esw)
1340 return -ENODEV;
1341 }
1342
10742efc 1343 err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
f9d196bd
DL		 1344 if (devcom)
1345 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
10742efc
VB		 1346 return err;
1347}
1348
c7b9038d
VB		 1349int mlx5e_tc_add_flow_mod_hdr(struct mlx5e_priv *priv,
1350 struct mlx5e_tc_flow_parse_attr *parse_attr,
1351 struct mlx5e_tc_flow *flow)
1352{
1353 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts = &parse_attr->mod_hdr_acts;
1354 struct mlx5_modify_hdr *mod_hdr;
1355
1356 mod_hdr = mlx5_modify_header_alloc(priv->mdev,
1357 get_flow_name_space(flow),
1358 mod_hdr_acts->num_actions,
1359 mod_hdr_acts->actions);
1360 if (IS_ERR(mod_hdr))
1361 return PTR_ERR(mod_hdr);
1362
1363 WARN_ON(flow->attr->modify_hdr);
1364 flow->attr->modify_hdr = mod_hdr;
1365
1366 return 0;
1367}
1368
c83954ab 1369static int
74491de9 1370mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
e98bedf5
EB		 1371 struct mlx5e_tc_flow *flow,
1372 struct netlink_ext_ack *extack)
adb4c123
OG		 1373{
1374 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772
AL		 1375 struct mlx5e_tc_flow_parse_attr *parse_attr;
1376 struct mlx5_flow_attr *attr = flow->attr;
8914add2 1377 bool vf_tun = false, encap_valid = true;
fe7738eb 1378 struct net_device *encap_dev = NULL;
c620b772 1379 struct mlx5_esw_flow_attr *esw_attr;
3c37745e
OG		 1380 struct mlx5e_rep_priv *rpriv;
1381 struct mlx5e_priv *out_priv;
97a8d29a 1382 struct mlx5_fc *counter;
39ac237c 1383 u32 max_prio, max_chain;
0ad060ee 1384 int err = 0;
f493f155 1385 int out_index;
8b32580d 1386
84179981
PB		 1387 /* We check chain range only for tc flows.
1388 * For ft flows, we checked attr->chain was originally 0 and set it to
1389 * FDB_FT_CHAIN which is outside tc range.
1390 * See mlx5e_rep_setup_ft_cb().
1391 */
ae430332 1392 max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
84179981 1393 if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
61644c3d
RD		 1394 NL_SET_ERR_MSG_MOD(extack,
1395 "Requested chain is out of supported range");
8914add2
VB		 1396 err = -EOPNOTSUPP;
1397 goto err_out;
bf07aa73
PB		 1398 }
1399
ae430332 1400 max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
bf07aa73 1401 if (attr->prio > max_prio) {
61644c3d
RD		 1402 NL_SET_ERR_MSG_MOD(extack,
1403 "Requested priority is out of supported range");
8914add2
VB		 1404 err = -EOPNOTSUPP;
1405 goto err_out;
bf07aa73 1406 }
e52c2802 1407
777bb800
VB		 1408 if (flow_flag_test(flow, TUN_RX)) {
1409 err = mlx5e_attach_decap_route(priv, flow);
1410 if (err)
8914add2 1411 goto err_out;
777bb800
VB		 1412 }
1413
14e6b038
EC		 1414 if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1415 err = mlx5e_attach_decap(priv, flow, extack);
1416 if (err)
8914add2 1417 goto err_out;
14e6b038
EC		 1418 }
1419
c620b772
AL		 1420 parse_attr = attr->parse_attr;
1421 esw_attr = attr->esw_attr;
1422
f493f155 1423 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
fe7738eb 1424 struct net_device *out_dev;
8c4dc42b
EB		 1425 int mirred_ifindex;
1426
c620b772 1427 if (!(esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
f493f155
EB		 1428 continue;
1429
7040632d 1430 mirred_ifindex = parse_attr->mirred_ifindex[out_index];
fe7738eb
DC		 1431 out_dev = dev_get_by_index(dev_net(priv->netdev), mirred_ifindex);
1432 if (!out_dev) {
1433 NL_SET_ERR_MSG_MOD(extack, "Requested mirred device not found");
1434 err = -ENODEV;
1435 goto err_out;
1436 }
733d4f36 1437 err = mlx5e_attach_encap(priv, flow, out_dev, out_index,
0ad060ee 1438 extack, &encap_dev, &encap_valid);
fe7738eb 1439 dev_put(out_dev);
0ad060ee 1440 if (err)
8914add2 1441 goto err_out;
0ad060ee 1442
8914add2
VB		 1443 if (esw_attr->dests[out_index].flags &
1444 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1445 vf_tun = true;
3c37745e
OG		 1446 out_priv = netdev_priv(encap_dev);
1447 rpriv = out_priv->ppriv;
c620b772
AL		 1448 esw_attr->dests[out_index].rep = rpriv->rep;
1449 esw_attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 1450 }
1451
7d1a3d08
VB		 1452 if (vf_tun && esw_attr->out_count > 1) {
1453 NL_SET_ERR_MSG_MOD(extack, "VF tunnel encap with mirroring is not supported");
1454 err = -EOPNOTSUPP;
1455 goto err_out;
1456 }
1457
8b32580d 1458 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 1459 if (err)
8914add2 1460 goto err_out;
adb4c123 1461
d5a3c2b6
RD		 1462 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1463 !(attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR)) {
8914add2
VB		 1464 if (vf_tun) {
1465 err = mlx5e_tc_add_flow_mod_hdr(priv, parse_attr, flow);
1466 if (err)
1467 goto err_out;
1468 } else {
1469 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
1470 if (err)
1471 goto err_out;
1472 }
d7e75a32
OG		 1473 }
1474
b8aee822 1475 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
c620b772 1476 counter = mlx5_fc_create(esw_attr->counter_dev, true);
8914add2
VB		 1477 if (IS_ERR(counter)) {
1478 err = PTR_ERR(counter);
1479 goto err_out;
1480 }
b8aee822
MB		 1481
1482 attr->counter = counter;
1483 }
1484
0ad060ee
RD		 1485 /* we get here if one of the following takes place:
1486 * (1) there's no error
1487 * (2) there's an encap action and we don't have valid neigh
3c37745e 1488 */
bc1d75fa 1489 if (!encap_valid)
178f69b4 1490 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
bc1d75fa 1491 else
6d2a3ed0 1492 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
c83954ab 1493
8914add2
VB		 1494 if (IS_ERR(flow->rule[0])) {
1495 err = PTR_ERR(flow->rule[0]);
1496 goto err_out;
1497 }
1498 flow_flag_set(flow, OFFLOADED);
5dbe906f
PB		 1499
1500 return 0;
8914add2
VB		 1501
1502err_out:
1503 flow_flag_set(flow, FAILED);
1504 return err;
aa0cbbae 1505}
d85cdccb 1506
9272e3df
YK		 1507static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
1508{
c620b772 1509 struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
9272e3df
YK		 1510 void *headers_v = MLX5_ADDR_OF(fte_match_param,
1511 spec->match_value,
1512 misc_parameters_3);
1513 u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
1514 headers_v,
1515 geneve_tlv_option_0_data);
1516
1517 return !!geneve_tlv_opt_0_data;
1518}
1519
d85cdccb
OG		 1520static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1521 struct mlx5e_tc_flow *flow)
1522{
1523 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 1524 struct mlx5_flow_attr *attr = flow->attr;
777bb800 1525 struct mlx5_esw_flow_attr *esw_attr;
8914add2 1526 bool vf_tun = false;
f493f155 1527 int out_index;
d85cdccb 1528
777bb800 1529 esw_attr = attr->esw_attr;
0a7fcb78
PB		 1530 mlx5e_put_flow_tunnel_id(flow);
1531
12a240a4 1532 if (flow_flag_test(flow, NOT_READY))
b4a23329 1533 remove_unready_flow(flow);
ef06c9ee 1534
226f2ca3
VB		 1535 if (mlx5e_is_offloaded_flow(flow)) {
1536 if (flow_flag_test(flow, SLOW))
178f69b4 1537 mlx5e_tc_unoffload_from_slow_path(esw, flow);
5dbe906f
PB		 1538 else
1539 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1540 }
d85cdccb 1541
9272e3df
YK		 1542 if (mlx5_flow_has_geneve_opt(flow))
1543 mlx5_geneve_tlv_option_del(priv->mdev->geneve);
1544
513f8f7f 1545 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1546
777bb800
VB		 1547 if (flow->decap_route)
1548 mlx5e_detach_decap_route(priv, flow);
1549
1550 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8914add2
VB		 1551 if (esw_attr->dests[out_index].flags &
1552 MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE)
1553 vf_tun = true;
777bb800 1554 if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP) {
8c4dc42b 1555 mlx5e_detach_encap(priv, flow, out_index);
2a4b6526
VB		 1556 kfree(attr->parse_attr->tun_info[out_index]);
1557 }
777bb800 1558 }
d7e75a32 1559
aedd133d 1560 mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
4c8594ad 1561
c7b9038d
VB		 1562 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1563 dealloc_mod_hdr_actions(&attr->parse_attr->mod_hdr_acts);
8914add2
VB		 1564 if (vf_tun && attr->modify_hdr)
1565 mlx5_modify_header_dealloc(priv->mdev, attr->modify_hdr);
1566 else
1567 mlx5e_detach_mod_hdr(priv, flow);
c7b9038d 1568 }
bcd6740c 1569 kfree(attr->sample_attr);
8914add2
VB		 1570 kvfree(attr->parse_attr);
1571 kvfree(attr->esw_attr->rx_tun_attr);
b8aee822
MB		 1572
1573 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
777bb800 1574 mlx5_fc_destroy(esw_attr->counter_dev, attr->counter);
14e6b038
EC		 1575
1576 if (flow_flag_test(flow, L3_TO_L2_DECAP))
1577 mlx5e_detach_decap(priv, flow);
c620b772
AL		 1578
1579 kfree(flow->attr);
d85cdccb
OG		 1580}
1581
0d9f9647 1582struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
b8aee822 1583{
c620b772 1584 return flow->attr->counter;
b8aee822
MB		 1585}
1586
6a06c2f7 1587/* Iterate over tmp_list of flows attached to flow_list head. */
021905f8 1588void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
6a06c2f7
VB		 1589{
1590 struct mlx5e_tc_flow *flow, *tmp;
1591
1592 list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
1593 mlx5e_flow_put(priv, flow);
1594}
1595
04de7dda
RD		 1596static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1597{
1598 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1599
226f2ca3
VB		 1600 if (!flow_flag_test(flow, ESWITCH) ||
1601 !flow_flag_test(flow, DUP))
04de7dda
RD		 1602 return;
1603
1604 mutex_lock(&esw->offloads.peer_mutex);
1605 list_del(&flow->peer);
1606 mutex_unlock(&esw->offloads.peer_mutex);
1607
226f2ca3 1608 flow_flag_clear(flow, DUP);
04de7dda 1609
eb252c3a
RD		 1610 if (refcount_dec_and_test(&flow->peer_flow->refcnt)) {
1611 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1612 kfree(flow->peer_flow);
1613 }
1614
04de7dda
RD		 1615 flow->peer_flow = NULL;
1616}
1617
1618static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1619{
1620 struct mlx5_core_dev *dev = flow->priv->mdev;
1621 struct mlx5_devcom *devcom = dev->priv.devcom;
1622 struct mlx5_eswitch *peer_esw;
1623
1624 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1625 if (!peer_esw)
1626 return;
1627
1628 __mlx5e_tc_del_fdb_peer_flow(flow);
1629 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1630}
1631
e8f887ac 1632static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1633 struct mlx5e_tc_flow *flow)
e8f887ac 1634{
226f2ca3 1635 if (mlx5e_is_eswitch_flow(flow)) {
04de7dda 1636 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1637 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1638 } else {
d85cdccb 1639 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1640 }
e8f887ac
AV		 1641}
1642
ee950e5d 1643static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
0a7fcb78
PB		 1644{
1645 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
1646 struct flow_action *flow_action = &rule->action;
1647 const struct flow_action_entry *act;
1648 int i;
1649
ee950e5d
CM		 1650 if (chain)
1651 return false;
1652
0a7fcb78
PB		 1653 flow_action_for_each(i, act, flow_action) {
1654 switch (act->id) {
1655 case FLOW_ACTION_GOTO:
1656 return true;
ee950e5d
CM		 1657 case FLOW_ACTION_SAMPLE:
1658 return true;
0a7fcb78
PB		 1659 default:
1660 continue;
1661 }
1662 }
1663
1664 return false;
1665}
bbd00f7e 1666
0a7fcb78
PB		 1667static int
1668enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
1669 struct flow_dissector_key_enc_opts *opts,
1670 struct netlink_ext_ack *extack,
1671 bool *dont_care)
1672{
1673 struct geneve_opt *opt;
1674 int off = 0;
1675
1676 *dont_care = true;
1677
1678 while (opts->len > off) {
1679 opt = (struct geneve_opt *)&opts->data[off];
1680
1681 if (!(*dont_care) || opt->opt_class || opt->type ||
1682 memchr_inv(opt->opt_data, 0, opt->length * 4)) {
1683 *dont_care = false;
1684
c51323ee 1685 if (opt->opt_class != htons(U16_MAX) ||
d7a42ad0 1686 opt->type != U8_MAX) {
c50775d0
RD		 1687 NL_SET_ERR_MSG_MOD(extack,
1688 "Partial match of tunnel options in chain > 0 isn't supported");
0a7fcb78
PB		 1689 netdev_warn(priv->netdev,
1690 "Partial match of tunnel options in chain > 0 isn't supported");
1691 return -EOPNOTSUPP;
1692 }
1693 }
1694
1695 off += sizeof(struct geneve_opt) + opt->length * 4;
1696 }
1697
1698 return 0;
1699}
1700
1701#define COPY_DISSECTOR(rule, diss_key, dst)\
1702({ \
1703 struct flow_rule *__rule = (rule);\
1704 typeof(dst) __dst = dst;\
1705\
1706 memcpy(__dst,\
1707 skb_flow_dissector_target(__rule->match.dissector,\
1708 diss_key,\
1709 __rule->match.key),\
1710 sizeof(*__dst));\
1711})
1712
1713static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
1714 struct mlx5e_tc_flow *flow,
1715 struct flow_cls_offload *f,
1716 struct net_device *filter_dev)
bbd00f7e 1717{
f9e30088 1718 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
0a7fcb78 1719 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78
PB		 1720 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
1721 struct flow_match_enc_opts enc_opts_match;
d7a42ad0 1722 struct tunnel_match_enc_opts tun_enc_opts;
0a7fcb78 1723 struct mlx5_rep_uplink_priv *uplink_priv;
c620b772 1724 struct mlx5_flow_attr *attr = flow->attr;
0a7fcb78
PB		 1725 struct mlx5e_rep_priv *uplink_rpriv;
1726 struct tunnel_match_key tunnel_key;
1727 bool enc_opts_is_dont_care = true;
1728 u32 tun_id, enc_opts_id = 0;
1729 struct mlx5_eswitch *esw;
1730 u32 value, mask;
8f256622 1731 int err;
2e72eb43 1732
0a7fcb78
PB		 1733 esw = priv->mdev->priv.eswitch;
1734 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1735 uplink_priv = &uplink_rpriv->uplink_priv;
1736
1737 memset(&tunnel_key, 0, sizeof(tunnel_key));
1738 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
1739 &tunnel_key.enc_control);
1740 if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
1741 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1742 &tunnel_key.enc_ipv4);
1743 else
1744 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1745 &tunnel_key.enc_ipv6);
1746 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
1747 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
1748 &tunnel_key.enc_tp);
1749 COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
1750 &tunnel_key.enc_key_id);
1751 tunnel_key.filter_ifindex = filter_dev->ifindex;
1752
1753 err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
1754 if (err)
101f4de9 1755 return err;
bbd00f7e 1756
0a7fcb78
PB		 1757 flow_rule_match_enc_opts(rule, &enc_opts_match);
1758 err = enc_opts_is_dont_care_or_full_match(priv,
1759 enc_opts_match.mask,
1760 extack,
1761 &enc_opts_is_dont_care);
1762 if (err)
1763 goto err_enc_opts;
fe1587a7 1764
0a7fcb78 1765 if (!enc_opts_is_dont_care) {
d7a42ad0
RD		 1766 memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
1767 memcpy(&tun_enc_opts.key, enc_opts_match.key,
1768 sizeof(*enc_opts_match.key));
1769 memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
1770 sizeof(*enc_opts_match.mask));
1771
0a7fcb78 1772 err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
d7a42ad0 1773 &tun_enc_opts, &enc_opts_id);
0a7fcb78
PB		 1774 if (err)
1775 goto err_enc_opts;
1776 }
fe1587a7 1777
0a7fcb78
PB		 1778 value = tun_id << ENC_OPTS_BITS | enc_opts_id;
1779 mask = enc_opts_id ? TUNNEL_ID_MASK :
1780 (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
fe1587a7 1781
0a7fcb78
PB		 1782 if (attr->chain) {
1783 mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
1784 TUNNEL_TO_REG, value, mask);
1785 } else {
1786 mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
1787 err = mlx5e_tc_match_to_reg_set(priv->mdev,
aedd133d 1788 mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
0a7fcb78
PB		 1789 TUNNEL_TO_REG, value);
1790 if (err)
1791 goto err_set;
fe1587a7 1792
0a7fcb78 1793 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2e72eb43 1794 }
bbd00f7e 1795
0a7fcb78
PB		 1796 flow->tunnel_id = value;
1797 return 0;
bcef735c 1798
0a7fcb78
PB		 1799err_set:
1800 if (enc_opts_id)
1801 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1802 enc_opts_id);
1803err_enc_opts:
1804 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1805 return err;
1806}
bcef735c 1807
0a7fcb78
PB		 1808static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
1809{
1810 u32 enc_opts_id = flow->tunnel_id & ENC_OPTS_BITS_MASK;
1811 u32 tun_id = flow->tunnel_id >> ENC_OPTS_BITS;
1812 struct mlx5_rep_uplink_priv *uplink_priv;
1813 struct mlx5e_rep_priv *uplink_rpriv;
1814 struct mlx5_eswitch *esw;
bcef735c 1815
0a7fcb78
PB		 1816 esw = flow->priv->mdev->priv.eswitch;
1817 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1818 uplink_priv = &uplink_rpriv->uplink_priv;
1819
1820 if (tun_id)
1821 mapping_remove(uplink_priv->tunnel_mapping, tun_id);
1822 if (enc_opts_id)
1823 mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
1824 enc_opts_id);
1825}
e98bedf5 1826
4c3844d9
PB		 1827u32 mlx5e_tc_get_flow_tun_id(struct mlx5e_tc_flow *flow)
1828{
1829 return flow->tunnel_id;
1830}
1831
fca53304
EB		 1832void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
1833 struct flow_match_basic *match, bool outer,
1834 void *headers_c, void *headers_v)
1835{
1836 bool ip_version_cap;
1837
1838 ip_version_cap = outer ?
1839 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1840 ft_field_support.outer_ip_version) :
1841 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1842 ft_field_support.inner_ip_version);
1843
1844 if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
1845 (match->key->n_proto == htons(ETH_P_IP) ||
1846 match->key->n_proto == htons(ETH_P_IPV6))) {
1847 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
1848 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
1849 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
1850 } else {
1851 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1852 ntohs(match->mask->n_proto));
1853 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1854 ntohs(match->key->n_proto));
1855 }
4a5d5d73
EB		 1856}
1857
0d9f9647 1858u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
a508728a
VB		 1859{
1860 void *headers_v;
1861 u16 ethertype;
1862 u8 ip_version;
1863
1864 if (outer)
1865 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1866 else
1867 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
1868
1869 ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
1870 /* Return ip_version converted from ethertype anyway */
1871 if (!ip_version) {
1872 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1873 if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
1874 ip_version = 4;
1875 else if (ethertype == ETH_P_IPV6)
1876 ip_version = 6;
1877 }
1878 return ip_version;
1879}
1880
bbd00f7e 1881static int parse_tunnel_attr(struct mlx5e_priv *priv,
0a7fcb78 1882 struct mlx5e_tc_flow *flow,
bbd00f7e 1883 struct mlx5_flow_spec *spec,
f9e30088 1884 struct flow_cls_offload *f,
0a7fcb78
PB		 1885 struct net_device *filter_dev,
1886 u8 *match_level,
1887 bool *match_inner)
bbd00f7e 1888{
a508728a 1889 struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
0a7fcb78 1890 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
e98bedf5 1891 struct netlink_ext_ack *extack = f->common.extack;
0a7fcb78 1892 bool needs_mapping, sets_mapping;
8f256622 1893 int err;
2e72eb43 1894
0885ae1a
A		 1895 if (!mlx5e_is_eswitch_flow(flow)) {
1896 NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
0a7fcb78 1897 return -EOPNOTSUPP;
0885ae1a 1898 }
0a7fcb78 1899
c620b772 1900 needs_mapping = !!flow->attr->chain;
ee950e5d 1901 sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
0a7fcb78
PB		 1902 *match_inner = !needs_mapping;
1903
1904 if ((needs_mapping || sets_mapping) &&
636bb968 1905 !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
c50775d0
RD		 1906 NL_SET_ERR_MSG_MOD(extack,
1907 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1908 netdev_warn(priv->netdev,
636bb968 1909 "Chains on tunnel devices isn't supported without register loopback support");
0a7fcb78 1910 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1911 }
1912
c620b772 1913 if (!flow->attr->chain) {
0a7fcb78
PB		 1914 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1915 match_level);
1916 if (err) {
e98bedf5 1917 NL_SET_ERR_MSG_MOD(extack,
0a7fcb78
PB		 1918 "Failed to parse tunnel attributes");
1919 netdev_warn(priv->netdev,
1920 "Failed to parse tunnel attributes");
1921 return err;
e98bedf5
EB		 1922 }
1923
14e6b038
EC		 1924 /* With mpls over udp we decapsulate using packet reformat
1925 * object
1926 */
1927 if (!netif_is_bareudp(filter_dev))
c620b772 1928 flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
a508728a
VB		 1929 err = mlx5e_tc_set_attr_rx_tun(flow, spec);
1930 if (err)
1931 return err;
1932 } else if (tunnel && tunnel->tunnel_type == MLX5E_TC_TUNNEL_TYPE_VXLAN) {
1933 struct mlx5_flow_spec *tmp_spec;
1934
1935 tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
1936 if (!tmp_spec) {
1937 NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for vxlan tmp spec");
1938 netdev_warn(priv->netdev, "Failed to allocate memory for vxlan tmp spec");
1939 return -ENOMEM;
1940 }
1941 memcpy(tmp_spec, spec, sizeof(*tmp_spec));
1942
1943 err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
1944 if (err) {
1945 kvfree(tmp_spec);
1946 NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
1947 netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
1948 return err;
1949 }
1950 err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
1951 kvfree(tmp_spec);
1952 if (err)
1953 return err;
bcef735c
OG		 1954 }
1955
0a7fcb78
PB		 1956 if (!needs_mapping && !sets_mapping)
1957 return 0;
bbd00f7e 1958
0a7fcb78 1959 return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
bbd00f7e 1960}
bbd00f7e 1961
0a7fcb78 1962static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
8377629e 1963{
0a7fcb78
PB		 1964 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1965 inner_headers);
bbd00f7e
HHZ		 1966}
1967
0a7fcb78 1968static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
8377629e 1969{
0a7fcb78
PB		 1970 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1971 inner_headers);
1972}
1973
1974static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
1975{
1976 return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1977 outer_headers);
1978}
1979
1980static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
1981{
1982 return MLX5_ADDR_OF(fte_match_param, spec->match_value,
1983 outer_headers);
8377629e
EB		 1984}
1985
1986static void *get_match_headers_value(u32 flags,
1987 struct mlx5_flow_spec *spec)
1988{
1989 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
0a7fcb78
PB		 1990 get_match_inner_headers_value(spec) :
1991 get_match_outer_headers_value(spec);
1992}
1993
1994static void *get_match_headers_criteria(u32 flags,
1995 struct mlx5_flow_spec *spec)
1996{
1997 return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
1998 get_match_inner_headers_criteria(spec) :
1999 get_match_outer_headers_criteria(spec);
8377629e
EB		 2000}
2001
6d65bc64 2002static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2003 struct flow_cls_offload *f)
2004{
2005 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2006 struct netlink_ext_ack *extack = f->common.extack;
2007 struct net_device *ingress_dev;
2008 struct flow_match_meta match;
2009
2010 if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2011 return 0;
2012
2013 flow_rule_match_meta(rule, &match);
e3e0f9b2 2014 if (!match.mask->ingress_ifindex)
2015 return 0;
2016
6d65bc64 2017 if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2018 NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
a683012a 2019 return -EOPNOTSUPP;
6d65bc64 2020 }
2021
2022 ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2023 match.key->ingress_ifindex);
2024 if (!ingress_dev) {
2025 NL_SET_ERR_MSG_MOD(extack,
2026 "Can't find the ingress port to match on");
a683012a 2027 return -ENOENT;
6d65bc64 2028 }
2029
2030 if (ingress_dev != filter_dev) {
2031 NL_SET_ERR_MSG_MOD(extack,
2032 "Can't match on the ingress filter port");
a683012a 2033 return -EOPNOTSUPP;
6d65bc64 2034 }
2035
2036 return 0;
2037}
2038
72046a91
EC		 2039static bool skip_key_basic(struct net_device *filter_dev,
2040 struct flow_cls_offload *f)
2041{
2042 /* When doing mpls over udp decap, the user needs to provide
2043 * MPLS_UC as the protocol in order to be able to match on mpls
2044 * label fields. However, the actual ethertype is IP so we want to
2045 * avoid matching on this, otherwise we'll fail the match.
2046 */
2047 if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2048 return true;
2049
2050 return false;
2051}
2052
de0af0bf 2053static int __parse_cls_flower(struct mlx5e_priv *priv,
0a7fcb78 2054 struct mlx5e_tc_flow *flow,
de0af0bf 2055 struct mlx5_flow_spec *spec,
f9e30088 2056 struct flow_cls_offload *f,
54c177ca 2057 struct net_device *filter_dev,
93b3586e 2058 u8 *inner_match_level, u8 *outer_match_level)
e3a2b7ed 2059{
e98bedf5 2060 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 2061 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2062 outer_headers);
2063 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2064 outer_headers);
699e96dd
JL		 2065 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2066 misc_parameters);
2067 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2068 misc_parameters);
a3222a2d
MD		 2069 void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2070 misc_parameters_3);
2071 void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2072 misc_parameters_3);
f9e30088 2073 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
8f256622 2074 struct flow_dissector *dissector = rule->match.dissector;
afe93f71 2075 enum fs_flow_table_type fs_type;
e3a2b7ed
AV		 2076 u16 addr_type = 0;
2077 u8 ip_proto = 0;
93b3586e 2078 u8 *match_level;
6d65bc64 2079 int err;
e3a2b7ed 2080
afe93f71 2081 fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
93b3586e 2082 match_level = outer_match_level;
de0af0bf 2083
8f256622 2084 if (dissector->used_keys &
3d144578
VB		 2085 ~(BIT(FLOW_DISSECTOR_KEY_META) |
2086 BIT(FLOW_DISSECTOR_KEY_CONTROL) |
e3a2b7ed
AV		 2087 BIT(FLOW_DISSECTOR_KEY_BASIC) |
2088 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 2089 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 2090 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 2091 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2092 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 2093 BIT(FLOW_DISSECTOR_KEY_PORTS) |
2094 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2095 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2096 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2097 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 2098 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 2099 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c 2100 BIT(FLOW_DISSECTOR_KEY_IP) |
4c3844d9 2101 BIT(FLOW_DISSECTOR_KEY_CT) |
9272e3df 2102 BIT(FLOW_DISSECTOR_KEY_ENC_IP) |
72046a91 2103 BIT(FLOW_DISSECTOR_KEY_ENC_OPTS) |
a3222a2d 2104 BIT(FLOW_DISSECTOR_KEY_ICMP) |
72046a91 2105 BIT(FLOW_DISSECTOR_KEY_MPLS))) {
e98bedf5 2106 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
48470a90
MD		 2107 netdev_dbg(priv->netdev, "Unsupported key used: 0x%x\n",
2108 dissector->used_keys);
e3a2b7ed
AV		 2109 return -EOPNOTSUPP;
2110 }
2111
075973c7 2112 if (mlx5e_get_tc_tun(filter_dev)) {
0a7fcb78 2113 bool match_inner = false;
bbd00f7e 2114
0a7fcb78
PB		 2115 err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2116 outer_match_level, &match_inner);
2117 if (err)
2118 return err;
2119
2120 if (match_inner) {
2121 /* header pointers should point to the inner headers
2122 * if the packet was decapsulated already.
2123 * outer headers are set by parse_tunnel_attr.
2124 */
2125 match_level = inner_match_level;
2126 headers_c = get_match_inner_headers_criteria(spec);
2127 headers_v = get_match_inner_headers_value(spec);
2128 }
bbd00f7e
HHZ		 2129 }
2130
6d65bc64 2131 err = mlx5e_flower_parse_meta(filter_dev, f);
2132 if (err)
2133 return err;
2134
72046a91
EC		 2135 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2136 !skip_key_basic(filter_dev, f)) {
8f256622
PNA		 2137 struct flow_match_basic match;
2138
2139 flow_rule_match_basic(rule, &match);
fca53304
EB		 2140 mlx5e_tc_set_ethertype(priv->mdev, &match,
2141 match_level == outer_match_level,
2142 headers_c, headers_v);
e3a2b7ed 2143
8f256622 2144 if (match.mask->n_proto)
d708f902 2145 *match_level = MLX5_MATCH_L2;
e3a2b7ed 2146 }
35a605db
EB		 2147 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2148 is_vlan_dev(filter_dev)) {
2149 struct flow_dissector_key_vlan filter_dev_mask;
2150 struct flow_dissector_key_vlan filter_dev_key;
8f256622
PNA		 2151 struct flow_match_vlan match;
2152
35a605db
EB		 2153 if (is_vlan_dev(filter_dev)) {
2154 match.key = &filter_dev_key;
2155 match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2156 match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2157 match.key->vlan_priority = 0;
2158 match.mask = &filter_dev_mask;
2159 memset(match.mask, 0xff, sizeof(*match.mask));
2160 match.mask->vlan_priority = 0;
2161 } else {
2162 flow_rule_match_vlan(rule, &match);
2163 }
8f256622
PNA		 2164 if (match.mask->vlan_id ||
2165 match.mask->vlan_priority ||
2166 match.mask->vlan_tpid) {
2167 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2168 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2169 svlan_tag, 1);
2170 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2171 svlan_tag, 1);
2172 } else {
2173 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2174 cvlan_tag, 1);
2175 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2176 cvlan_tag, 1);
2177 }
095b6cfd 2178
8f256622
PNA		 2179 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2180 match.mask->vlan_id);
2181 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2182 match.key->vlan_id);
358d79a4 2183
8f256622
PNA		 2184 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2185 match.mask->vlan_priority);
2186 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2187 match.key->vlan_priority);
54782900 2188
d708f902 2189 *match_level = MLX5_MATCH_L2;
54782900 2190 }
d3a80bb5 2191 } else if (*match_level != MLX5_MATCH_NONE) {
fc603294
MB		 2192 /* cvlan_tag enabled in match criteria and
2193 * disabled in match value means both S & C tags
2194 * don't exist (untagged of both)
2195 */
cee26487 2196 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 2197 *match_level = MLX5_MATCH_L2;
54782900
OG		 2198 }
2199
8f256622
PNA		 2200 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2201 struct flow_match_vlan match;
2202
12d5cbf8 2203 flow_rule_match_cvlan(rule, &match);
8f256622
PNA		 2204 if (match.mask->vlan_id ||
2205 match.mask->vlan_priority ||
2206 match.mask->vlan_tpid) {
afe93f71
RD		 2207 if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2208 fs_type)) {
2209 NL_SET_ERR_MSG_MOD(extack,
2210 "Matching on CVLAN is not supported");
2211 return -EOPNOTSUPP;
2212 }
2213
8f256622 2214 if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
699e96dd
JL		 2215 MLX5_SET(fte_match_set_misc, misc_c,
2216 outer_second_svlan_tag, 1);
2217 MLX5_SET(fte_match_set_misc, misc_v,
2218 outer_second_svlan_tag, 1);
2219 } else {
2220 MLX5_SET(fte_match_set_misc, misc_c,
2221 outer_second_cvlan_tag, 1);
2222 MLX5_SET(fte_match_set_misc, misc_v,
2223 outer_second_cvlan_tag, 1);
2224 }
2225
2226 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
8f256622 2227 match.mask->vlan_id);
699e96dd 2228 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
8f256622 2229 match.key->vlan_id);
699e96dd 2230 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
8f256622 2231 match.mask->vlan_priority);
699e96dd 2232 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
8f256622 2233 match.key->vlan_priority);
699e96dd
JL		 2234
2235 *match_level = MLX5_MATCH_L2;
0faddfe6 2236 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
699e96dd
JL		 2237 }
2238 }
2239
8f256622
PNA		 2240 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2241 struct flow_match_eth_addrs match;
54782900 2242
8f256622 2243 flow_rule_match_eth_addrs(rule, &match);
d3a80bb5
OG		 2244 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2245 dmac_47_16),
8f256622 2246 match.mask->dst);
d3a80bb5
OG		 2247 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2248 dmac_47_16),
8f256622 2249 match.key->dst);
d3a80bb5
OG		 2250
2251 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2252 smac_47_16),
8f256622 2253 match.mask->src);
d3a80bb5
OG		 2254 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2255 smac_47_16),
8f256622 2256 match.key->src);
d3a80bb5 2257
8f256622
PNA		 2258 if (!is_zero_ether_addr(match.mask->src) ||
2259 !is_zero_ether_addr(match.mask->dst))
d708f902 2260 *match_level = MLX5_MATCH_L2;
54782900
OG		 2261 }
2262
8f256622
PNA		 2263 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2264 struct flow_match_control match;
54782900 2265
8f256622
PNA		 2266 flow_rule_match_control(rule, &match);
2267 addr_type = match.key->addr_type;
54782900
OG		 2268
2269 /* the HW doesn't support frag first/later */
0885ae1a
A		 2270 if (match.mask->flags & FLOW_DIS_FIRST_FRAG) {
2271 NL_SET_ERR_MSG_MOD(extack, "Match on frag first/later is not supported");
54782900 2272 return -EOPNOTSUPP;
0885ae1a 2273 }
54782900 2274
8f256622 2275 if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
54782900
OG		 2276 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2277 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8f256622 2278 match.key->flags & FLOW_DIS_IS_FRAGMENT);
54782900
OG		 2279
2280 /* the HW doesn't need L3 inline to match on frag=no */
8f256622 2281 if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 2282 *match_level = MLX5_MATCH_L2;
54782900
OG		 2283 /* *** L2 attributes parsing up to here *** */
2284 else
83621b7d 2285 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 2286 }
2287 }
2288
8f256622
PNA		 2289 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2290 struct flow_match_basic match;
2291
2292 flow_rule_match_basic(rule, &match);
2293 ip_proto = match.key->ip_proto;
54782900
OG		 2294
2295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
8f256622 2296 match.mask->ip_proto);
54782900 2297 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8f256622 2298 match.key->ip_proto);
54782900 2299
8f256622 2300 if (match.mask->ip_proto)
d708f902 2301 *match_level = MLX5_MATCH_L3;
54782900
OG		 2302 }
2303
e3a2b7ed 2304 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
8f256622 2305 struct flow_match_ipv4_addrs match;
e3a2b7ed 2306
8f256622 2307 flow_rule_match_ipv4_addrs(rule, &match);
e3a2b7ed
AV		 2308 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2309 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2310 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2311 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2312 src_ipv4_src_ipv6.ipv4_layout.ipv4),
8f256622 2313 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2314 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2315 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2316 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2317 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2318 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
8f256622 2319 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2320
8f256622 2321 if (match.mask->src || match.mask->dst)
d708f902 2322 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2323 }
2324
2325 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
8f256622 2326 struct flow_match_ipv6_addrs match;
e3a2b7ed 2327
8f256622 2328 flow_rule_match_ipv6_addrs(rule, &match);
e3a2b7ed
AV		 2329 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2330 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2331 &match.mask->src, sizeof(match.mask->src));
e3a2b7ed
AV		 2332 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2333 src_ipv4_src_ipv6.ipv6_layout.ipv6),
8f256622 2334 &match.key->src, sizeof(match.key->src));
e3a2b7ed
AV		 2335
2336 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2337 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2338 &match.mask->dst, sizeof(match.mask->dst));
e3a2b7ed
AV		 2339 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2340 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
8f256622 2341 &match.key->dst, sizeof(match.key->dst));
de0af0bf 2342
8f256622
PNA		 2343 if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2344 ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
d708f902 2345 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 2346 }
2347
8f256622
PNA		 2348 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2349 struct flow_match_ip match;
1f97a526 2350
8f256622
PNA		 2351 flow_rule_match_ip(rule, &match);
2352 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
2353 match.mask->tos & 0x3);
2354 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
2355 match.key->tos & 0x3);
1f97a526 2356
8f256622
PNA		 2357 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
2358 match.mask->tos >> 2);
2359 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
2360 match.key->tos >> 2);
1f97a526 2361
8f256622
PNA		 2362 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
2363 match.mask->ttl);
2364 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
2365 match.key->ttl);
1f97a526 2366
8f256622 2367 if (match.mask->ttl &&
a8ade55f 2368 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 2369 ft_field_support.outer_ipv4_ttl)) {
2370 NL_SET_ERR_MSG_MOD(extack,
2371 "Matching on TTL is not supported");
1f97a526 2372 return -EOPNOTSUPP;
e98bedf5 2373 }
a8ade55f 2374
8f256622 2375 if (match.mask->tos || match.mask->ttl)
d708f902 2376 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 2377 }
2378
54782900
OG		 2379 /* *** L3 attributes parsing up to here *** */
2380
8f256622
PNA		 2381 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
2382 struct flow_match_ports match;
2383
2384 flow_rule_match_ports(rule, &match);
e3a2b7ed
AV		 2385 switch (ip_proto) {
2386 case IPPROTO_TCP:
2387 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2388 tcp_sport, ntohs(match.mask->src));
e3a2b7ed 2389 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2390 tcp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2391
2392 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2393 tcp_dport, ntohs(match.mask->dst));
e3a2b7ed 2394 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2395 tcp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2396 break;
2397
2398 case IPPROTO_UDP:
2399 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2400 udp_sport, ntohs(match.mask->src));
e3a2b7ed 2401 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2402 udp_sport, ntohs(match.key->src));
e3a2b7ed
AV		 2403
2404 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
8f256622 2405 udp_dport, ntohs(match.mask->dst));
e3a2b7ed 2406 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
8f256622 2407 udp_dport, ntohs(match.key->dst));
e3a2b7ed
AV		 2408 break;
2409 default:
e98bedf5
EB		 2410 NL_SET_ERR_MSG_MOD(extack,
2411 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 2412 netdev_err(priv->netdev,
2413 "Only UDP and TCP transport are supported\n");
2414 return -EINVAL;
2415 }
de0af0bf 2416
8f256622 2417 if (match.mask->src || match.mask->dst)
d708f902 2418 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 2419 }
2420
8f256622
PNA		 2421 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
2422 struct flow_match_tcp match;
e77834ec 2423
8f256622 2424 flow_rule_match_tcp(rule, &match);
e77834ec 2425 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
8f256622 2426 ntohs(match.mask->flags));
e77834ec 2427 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8f256622 2428 ntohs(match.key->flags));
e77834ec 2429
8f256622 2430 if (match.mask->flags)
d708f902 2431 *match_level = MLX5_MATCH_L4;
e77834ec 2432 }
a3222a2d
MD		 2433 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
2434 struct flow_match_icmp match;
e77834ec 2435
a3222a2d
MD		 2436 flow_rule_match_icmp(rule, &match);
2437 switch (ip_proto) {
2438 case IPPROTO_ICMP:
2439 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2440 MLX5_FLEX_PROTO_ICMP)) {
2441 NL_SET_ERR_MSG_MOD(extack,
2442 "Match on Flex protocols for ICMP is not supported");
a3222a2d 2443 return -EOPNOTSUPP;
0885ae1a 2444 }
a3222a2d
MD		 2445 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
2446 match.mask->type);
2447 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
2448 match.key->type);
2449 MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
2450 match.mask->code);
2451 MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
2452 match.key->code);
2453 break;
2454 case IPPROTO_ICMPV6:
2455 if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
0885ae1a
A		 2456 MLX5_FLEX_PROTO_ICMPV6)) {
2457 NL_SET_ERR_MSG_MOD(extack,
2458 "Match on Flex protocols for ICMPV6 is not supported");
a3222a2d 2459 return -EOPNOTSUPP;
0885ae1a 2460 }
a3222a2d
MD		 2461 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
2462 match.mask->type);
2463 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
2464 match.key->type);
2465 MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
2466 match.mask->code);
2467 MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
2468 match.key->code);
2469 break;
2470 default:
2471 NL_SET_ERR_MSG_MOD(extack,
2472 "Code and type matching only with ICMP and ICMPv6");
2473 netdev_err(priv->netdev,
2474 "Code and type matching only with ICMP and ICMPv6\n");
2475 return -EINVAL;
2476 }
2477 if (match.mask->code || match.mask->type) {
2478 *match_level = MLX5_MATCH_L4;
2479 spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
2480 }
2481 }
39c538d6 2482 /* Currently supported only for MPLS over UDP */
7d6c86e3
AH		 2483 if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
2484 !netif_is_bareudp(filter_dev)) {
2485 NL_SET_ERR_MSG_MOD(extack,
2486 "Matching on MPLS is supported only for MPLS over UDP");
2487 netdev_err(priv->netdev,
2488 "Matching on MPLS is supported only for MPLS over UDP\n");
2489 return -EOPNOTSUPP;
2490 }
2491
e3a2b7ed
AV		 2492 return 0;
2493}
2494
de0af0bf 2495static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 2496 struct mlx5e_tc_flow *flow,
de0af0bf 2497 struct mlx5_flow_spec *spec,
f9e30088 2498 struct flow_cls_offload *f,
54c177ca 2499 struct net_device *filter_dev)
de0af0bf 2500{
93b3586e 2501 u8 inner_match_level, outer_match_level, non_tunnel_match_level;
e98bedf5 2502 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 2503 struct mlx5_core_dev *dev = priv->mdev;
2504 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 2505 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2506 struct mlx5_eswitch_rep *rep;
226f2ca3 2507 bool is_eswitch_flow;
de0af0bf
RD		 2508 int err;
2509
93b3586e
HN		 2510 inner_match_level = MLX5_MATCH_NONE;
2511 outer_match_level = MLX5_MATCH_NONE;
2512
0a7fcb78
PB		 2513 err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
2514 &inner_match_level, &outer_match_level);
93b3586e
HN		 2515 non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
2516 outer_match_level : inner_match_level;
de0af0bf 2517
226f2ca3
VB		 2518 is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
2519 if (!err && is_eswitch_flow) {
1d447a39 2520 rep = rpriv->rep;
b05af6aa 2521 if (rep->vport != MLX5_VPORT_UPLINK &&
1d447a39 2522 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
93b3586e 2523 esw->offloads.inline_mode < non_tunnel_match_level)) {
e98bedf5
EB		 2524 NL_SET_ERR_MSG_MOD(extack,
2525 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 2526 netdev_warn(priv->netdev,
2527 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
93b3586e 2528 non_tunnel_match_level, esw->offloads.inline_mode);
de0af0bf
RD		 2529 return -EOPNOTSUPP;
2530 }
2531 }
2532
c620b772
AL		 2533 flow->attr->inner_match_level = inner_match_level;
2534 flow->attr->outer_match_level = outer_match_level;
2535
38aa51c1 2536
de0af0bf
RD		 2537 return err;
2538}
2539
d79b6df6
OG		 2540struct pedit_headers {
2541 struct ethhdr eth;
0eb69bb9 2542 struct vlan_hdr vlan;
d79b6df6
OG		 2543 struct iphdr ip4;
2544 struct ipv6hdr ip6;
2545 struct tcphdr tcp;
2546 struct udphdr udp;
2547};
2548
c500c86b
PNA		 2549struct pedit_headers_action {
2550 struct pedit_headers vals;
2551 struct pedit_headers masks;
2552 u32 pedits;
2553};
2554
d79b6df6 2555static int pedit_header_offsets[] = {
73867881
PNA		 2556 [FLOW_ACT_MANGLE_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
2557 [FLOW_ACT_MANGLE_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
2558 [FLOW_ACT_MANGLE_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
2559 [FLOW_ACT_MANGLE_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
2560 [FLOW_ACT_MANGLE_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
d79b6df6
OG		 2561};
2562
2563#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
2564
2565static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
0885ae1a
A		 2566 struct pedit_headers_action *hdrs,
2567 struct netlink_ext_ack *extack)
d79b6df6
OG		 2568{
2569 u32 *curr_pmask, *curr_pval;
2570
c500c86b
PNA		 2571 curr_pmask = (u32 *)(pedit_header(&hdrs->masks, hdr_type) + offset);
2572 curr_pval = (u32 *)(pedit_header(&hdrs->vals, hdr_type) + offset);
d79b6df6 2573
0885ae1a
A		 2574 if (*curr_pmask & mask) { /* disallow acting twice on the same location */
2575 NL_SET_ERR_MSG_MOD(extack,
2576 "curr_pmask and new mask same. Acting twice on same location");
d79b6df6 2577 goto out_err;
0885ae1a 2578 }
d79b6df6
OG		 2579
2580 *curr_pmask |= mask;
2581 *curr_pval |= (val & mask);
2582
2583 return 0;
2584
2585out_err:
2586 return -EOPNOTSUPP;
2587}
2588
2589struct mlx5_fields {
2590 u8 field;
88f30bbc
DL		 2591 u8 field_bsize;
2592 u32 field_mask;
d79b6df6 2593 u32 offset;
27c11b6b 2594 u32 match_offset;
d79b6df6
OG		 2595};
2596
88f30bbc
DL		 2597#define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
2598 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
27c11b6b
EB		 2599 offsetof(struct pedit_headers, field) + (off), \
2600 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
2601
2ef86872
EB		 2602/* masked values are the same and there are no rewrites that do not have a
2603 * match.
2604 */
2605#define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
2606 type matchmaskx = *(type *)(matchmaskp); \
2607 type matchvalx = *(type *)(matchvalp); \
2608 type maskx = *(type *)(maskp); \
2609 type valx = *(type *)(valp); \
2610 \
2611 (valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
2612 matchmaskx)); \
2613})
2614
27c11b6b 2615static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
88f30bbc 2616 void *matchmaskp, u8 bsize)
27c11b6b
EB		 2617{
2618 bool same = false;
2619
88f30bbc
DL		 2620 switch (bsize) {
2621 case 8:
2ef86872 2622 same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2623 break;
88f30bbc 2624 case 16:
2ef86872 2625 same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
27c11b6b 2626 break;
88f30bbc 2627 case 32:
2ef86872 2628 same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
27c11b6b
EB		 2629 break;
2630 }
2631
2632 return same;
2633}
a8e4f0c4 2634
d79b6df6 2635static struct mlx5_fields fields[] = {
88f30bbc
DL		 2636 OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
2637 OFFLOAD(DMAC_15_0, 16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
2638 OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
2639 OFFLOAD(SMAC_15_0, 16, U16_MAX, eth.h_source[4], 0, smac_15_0),
2640 OFFLOAD(ETHERTYPE, 16, U16_MAX, eth.h_proto, 0, ethertype),
2641 OFFLOAD(FIRST_VID, 16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
2642
ab9341b5 2643 OFFLOAD(IP_DSCP, 8, 0xfc, ip4.tos, 0, ip_dscp),
88f30bbc
DL		 2644 OFFLOAD(IP_TTL, 8, U8_MAX, ip4.ttl, 0, ttl_hoplimit),
2645 OFFLOAD(SIPV4, 32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
2646 OFFLOAD(DIPV4, 32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2647
2648 OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
27c11b6b 2649 src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2650 OFFLOAD(SIPV6_95_64, 32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
27c11b6b 2651 src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2652 OFFLOAD(SIPV6_63_32, 32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
27c11b6b 2653 src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2654 OFFLOAD(SIPV6_31_0, 32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
27c11b6b 2655 src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2656 OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
27c11b6b 2657 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
88f30bbc 2658 OFFLOAD(DIPV6_95_64, 32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
27c11b6b 2659 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
88f30bbc 2660 OFFLOAD(DIPV6_63_32, 32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
27c11b6b 2661 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
88f30bbc 2662 OFFLOAD(DIPV6_31_0, 32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
27c11b6b 2663 dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
88f30bbc 2664 OFFLOAD(IPV6_HOPLIMIT, 8, U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
748cde9a 2665 OFFLOAD(IP_DSCP, 16, 0xc00f, ip6, 0, ip_dscp),
27c11b6b 2666
88f30bbc
DL		 2667 OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source, 0, tcp_sport),
2668 OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest, 0, tcp_dport),
2669 /* in linux iphdr tcp_flags is 8 bits long */
2670 OFFLOAD(TCP_FLAGS, 8, U8_MAX, tcp.ack_seq, 5, tcp_flags),
27c11b6b 2671
88f30bbc
DL		 2672 OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
2673 OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest, 0, udp_dport),
d79b6df6
OG		 2674};
2675
82198d8b
MD		 2676static unsigned long mask_to_le(unsigned long mask, int size)
2677{
2678 __be32 mask_be32;
2679 __be16 mask_be16;
2680
2681 if (size == 32) {
2682 mask_be32 = (__force __be32)(mask);
2683 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2684 } else if (size == 16) {
2685 mask_be32 = (__force __be32)(mask);
2686 mask_be16 = *(__be16 *)&mask_be32;
2687 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2688 }
2689
2690 return mask;
2691}
6ae4a6a5
PB		 2692static int offload_pedit_fields(struct mlx5e_priv *priv,
2693 int namespace,
2694 struct pedit_headers_action *hdrs,
e98bedf5 2695 struct mlx5e_tc_flow_parse_attr *parse_attr,
27c11b6b 2696 u32 *action_flags,
e98bedf5 2697 struct netlink_ext_ack *extack)
d79b6df6
OG		 2698{
2699 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
6ae4a6a5 2700 int i, action_size, first, last, next_z;
88f30bbc
DL		 2701 void *headers_c, *headers_v, *action, *vals_p;
2702 u32 *s_masks_p, *a_masks_p, s_mask, a_mask;
6ae4a6a5 2703 struct mlx5e_tc_mod_hdr_acts *mod_acts;
d79b6df6 2704 struct mlx5_fields *f;
82198d8b 2705 unsigned long mask, field_mask;
6ae4a6a5 2706 int err;
88f30bbc
DL		 2707 u8 cmd;
2708
6ae4a6a5 2709 mod_acts = &parse_attr->mod_hdr_acts;
88f30bbc
DL		 2710 headers_c = get_match_headers_criteria(*action_flags, &parse_attr->spec);
2711 headers_v = get_match_headers_value(*action_flags, &parse_attr->spec);
d79b6df6 2712
73867881
PNA		 2713 set_masks = &hdrs[0].masks;
2714 add_masks = &hdrs[1].masks;
2715 set_vals = &hdrs[0].vals;
2716 add_vals = &hdrs[1].vals;
d79b6df6 2717
d65dbedf 2718 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6
OG		 2719
2720 for (i = 0; i < ARRAY_SIZE(fields); i++) {
27c11b6b
EB		 2721 bool skip;
2722
d79b6df6
OG		 2723 f = &fields[i];
2724 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 2725 s_mask = 0;
2726 a_mask = 0;
d79b6df6
OG		 2727
2728 s_masks_p = (void *)set_masks + f->offset;
2729 a_masks_p = (void *)add_masks + f->offset;
2730
88f30bbc
DL		 2731 s_mask = *s_masks_p & f->field_mask;
2732 a_mask = *a_masks_p & f->field_mask;
d79b6df6
OG		 2733
2734 if (!s_mask && !a_mask) /* nothing to offload here */
2735 continue;
2736
2737 if (s_mask && a_mask) {
e98bedf5
EB		 2738 NL_SET_ERR_MSG_MOD(extack,
2739 "can't set and add to the same HW field");
61b6a6c3
CH		 2740 netdev_warn(priv->netdev,
2741 "mlx5: can't set and add to the same HW field (%x)\n",
2742 f->field);
d79b6df6
OG		 2743 return -EOPNOTSUPP;
2744 }
2745
27c11b6b 2746 skip = false;
d79b6df6 2747 if (s_mask) {
27c11b6b
EB		 2748 void *match_mask = headers_c + f->match_offset;
2749 void *match_val = headers_v + f->match_offset;
2750
d79b6df6
OG		 2751 cmd = MLX5_ACTION_TYPE_SET;
2752 mask = s_mask;
2753 vals_p = (void *)set_vals + f->offset;
27c11b6b
EB		 2754 /* don't rewrite if we have a match on the same value */
2755 if (cmp_val_mask(vals_p, s_masks_p, match_val,
88f30bbc 2756 match_mask, f->field_bsize))
27c11b6b 2757 skip = true;
d79b6df6 2758 /* clear to denote we consumed this field */
88f30bbc 2759 *s_masks_p &= ~f->field_mask;
d79b6df6
OG		 2760 } else {
2761 cmd = MLX5_ACTION_TYPE_ADD;
2762 mask = a_mask;
2763 vals_p = (void *)add_vals + f->offset;
27c11b6b 2764 /* add 0 is no change */
88f30bbc 2765 if ((*(u32 *)vals_p & f->field_mask) == 0)
27c11b6b 2766 skip = true;
d79b6df6 2767 /* clear to denote we consumed this field */
88f30bbc 2768 *a_masks_p &= ~f->field_mask;
d79b6df6 2769 }
27c11b6b
EB		 2770 if (skip)
2771 continue;
d79b6df6 2772
82198d8b 2773 mask = mask_to_le(mask, f->field_bsize);
2b64beba 2774
88f30bbc
DL		 2775 first = find_first_bit(&mask, f->field_bsize);
2776 next_z = find_next_zero_bit(&mask, f->field_bsize, first);
2777 last = find_last_bit(&mask, f->field_bsize);
2b64beba 2778 if (first < next_z && next_z < last) {
e98bedf5
EB		 2779 NL_SET_ERR_MSG_MOD(extack,
2780 "rewrite of few sub-fields isn't supported");
61b6a6c3
CH		 2781 netdev_warn(priv->netdev,
2782 "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
2783 mask);
d79b6df6
OG		 2784 return -EOPNOTSUPP;
2785 }
2786
6ae4a6a5
PB		 2787 err = alloc_mod_hdr_actions(priv->mdev, namespace, mod_acts);
2788 if (err) {
2789 NL_SET_ERR_MSG_MOD(extack,
2790 "too many pedit actions, can't offload");
2791 mlx5_core_warn(priv->mdev,
2792 "mlx5: parsed %d pedit actions, can't do more\n",
2793 mod_acts->num_actions);
2794 return err;
2795 }
2796
2797 action = mod_acts->actions +
2798 (mod_acts->num_actions * action_size);
d79b6df6
OG		 2799 MLX5_SET(set_action_in, action, action_type, cmd);
2800 MLX5_SET(set_action_in, action, field, f->field);
2801
2802 if (cmd == MLX5_ACTION_TYPE_SET) {
88f30bbc
DL		 2803 int start;
2804
82198d8b
MD		 2805 field_mask = mask_to_le(f->field_mask, f->field_bsize);
2806
88f30bbc 2807 /* if field is bit sized it can start not from first bit */
82198d8b 2808 start = find_first_bit(&field_mask, f->field_bsize);
88f30bbc
DL		 2809
2810 MLX5_SET(set_action_in, action, offset, first - start);
d79b6df6 2811 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2812 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2813 }
2814
88f30bbc 2815 if (f->field_bsize == 32)
2b64beba 2816 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
88f30bbc 2817 else if (f->field_bsize == 16)
2b64beba 2818 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
88f30bbc 2819 else if (f->field_bsize == 8)
2b64beba 2820 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6 2821
6ae4a6a5 2822 ++mod_acts->num_actions;
d79b6df6
OG		 2823 }
2824
d79b6df6
OG		 2825 return 0;
2826}
2827
2cc1cb1d
TZ		 2828static int mlx5e_flow_namespace_max_modify_action(struct mlx5_core_dev *mdev,
2829 int namespace)
2830{
2831 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2832 return MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, max_modify_header_actions);
2833 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2834 return MLX5_CAP_FLOWTABLE_NIC_RX(mdev, max_modify_header_actions);
2835}
2836
6ae4a6a5
PB		 2837int alloc_mod_hdr_actions(struct mlx5_core_dev *mdev,
2838 int namespace,
2839 struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
d79b6df6 2840{
6ae4a6a5
PB		 2841 int action_size, new_num_actions, max_hw_actions;
2842 size_t new_sz, old_sz;
2843 void *ret;
d79b6df6 2844
6ae4a6a5
PB		 2845 if (mod_hdr_acts->num_actions < mod_hdr_acts->max_actions)
2846 return 0;
d79b6df6 2847
d65dbedf 2848 action_size = MLX5_UN_SZ_BYTES(set_add_copy_action_in_auto);
d79b6df6 2849
6ae4a6a5
PB		 2850 max_hw_actions = mlx5e_flow_namespace_max_modify_action(mdev,
2851 namespace);
2852 new_num_actions = min(max_hw_actions,
2853 mod_hdr_acts->actions ?
2854 mod_hdr_acts->max_actions * 2 : 1);
2855 if (mod_hdr_acts->max_actions == new_num_actions)
2856 return -ENOSPC;
2857
2858 new_sz = action_size * new_num_actions;
2859 old_sz = mod_hdr_acts->max_actions * action_size;
2860 ret = krealloc(mod_hdr_acts->actions, new_sz, GFP_KERNEL);
2861 if (!ret)
d79b6df6
OG		 2862 return -ENOMEM;
2863
6ae4a6a5
PB		 2864 memset(ret + old_sz, 0, new_sz - old_sz);
2865 mod_hdr_acts->actions = ret;
2866 mod_hdr_acts->max_actions = new_num_actions;
2867
d79b6df6
OG		 2868 return 0;
2869}
2870
6ae4a6a5
PB		 2871void dealloc_mod_hdr_actions(struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts)
2872{
2873 kfree(mod_hdr_acts->actions);
2874 mod_hdr_acts->actions = NULL;
2875 mod_hdr_acts->num_actions = 0;
2876 mod_hdr_acts->max_actions = 0;
2877}
2878
d79b6df6
OG		 2879static const struct pedit_headers zero_masks = {};
2880
582234b4
EC		 2881static int
2882parse_pedit_to_modify_hdr(struct mlx5e_priv *priv,
2883 const struct flow_action_entry *act, int namespace,
2884 struct mlx5e_tc_flow_parse_attr *parse_attr,
2885 struct pedit_headers_action *hdrs,
2886 struct netlink_ext_ack *extack)
d79b6df6 2887{
73867881
PNA		 2888 u8 cmd = (act->id == FLOW_ACTION_MANGLE) ? 0 : 1;
2889 int err = -EOPNOTSUPP;
d79b6df6 2890 u32 mask, val, offset;
73867881 2891 u8 htype;
d79b6df6 2892
73867881
PNA		 2893 htype = act->mangle.htype;
2894 err = -EOPNOTSUPP; /* can't be all optimistic */
d79b6df6 2895
73867881
PNA		 2896 if (htype == FLOW_ACT_MANGLE_UNSPEC) {
2897 NL_SET_ERR_MSG_MOD(extack, "legacy pedit isn't offloaded");
2898 goto out_err;
2899 }
d79b6df6 2900
2cc1cb1d
TZ		 2901 if (!mlx5e_flow_namespace_max_modify_action(priv->mdev, namespace)) {
2902 NL_SET_ERR_MSG_MOD(extack,
2903 "The pedit offload action is not supported");
2904 goto out_err;
2905 }
2906
73867881
PNA		 2907 mask = act->mangle.mask;
2908 val = act->mangle.val;
2909 offset = act->mangle.offset;
d79b6df6 2910
0885ae1a 2911 err = set_pedit_val(htype, ~mask, val, offset, &hdrs[cmd], extack);
73867881
PNA		 2912 if (err)
2913 goto out_err;
c500c86b 2914
73867881 2915 hdrs[cmd].pedits++;
d79b6df6 2916
c500c86b
PNA		 2917 return 0;
2918out_err:
2919 return err;
2920}
2921
582234b4 2922static int
1cc35b70 2923parse_pedit_to_reformat(const struct flow_action_entry *act,
582234b4
EC		 2924 struct mlx5e_tc_flow_parse_attr *parse_attr,
2925 struct netlink_ext_ack *extack)
2926{
2927 u32 mask, val, offset;
2928 u32 *p;
2929
0885ae1a
A		 2930 if (act->id != FLOW_ACTION_MANGLE) {
2931 NL_SET_ERR_MSG_MOD(extack, "Unsupported action id");
582234b4 2932 return -EOPNOTSUPP;
0885ae1a 2933 }
582234b4
EC		 2934
2935 if (act->mangle.htype != FLOW_ACT_MANGLE_HDR_TYPE_ETH) {
2936 NL_SET_ERR_MSG_MOD(extack, "Only Ethernet modification is supported");
2937 return -EOPNOTSUPP;
2938 }
2939
2940 mask = ~act->mangle.mask;
2941 val = act->mangle.val;
2942 offset = act->mangle.offset;
2943 p = (u32 *)&parse_attr->eth;
2944 *(p + (offset >> 2)) |= (val & mask);
2945
2946 return 0;
2947}
2948
2949static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2950 const struct flow_action_entry *act, int namespace,
2951 struct mlx5e_tc_flow_parse_attr *parse_attr,
2952 struct pedit_headers_action *hdrs,
2953 struct mlx5e_tc_flow *flow,
2954 struct netlink_ext_ack *extack)
2955{
2956 if (flow && flow_flag_test(flow, L3_TO_L2_DECAP))
1cc35b70 2957 return parse_pedit_to_reformat(act, parse_attr, extack);
582234b4
EC		 2958
2959 return parse_pedit_to_modify_hdr(priv, act, namespace,
2960 parse_attr, hdrs, extack);
2961}
2962
c500c86b
PNA		 2963static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
2964 struct mlx5e_tc_flow_parse_attr *parse_attr,
2965 struct pedit_headers_action *hdrs,
27c11b6b 2966 u32 *action_flags,
c500c86b
PNA		 2967 struct netlink_ext_ack *extack)
2968{
2969 struct pedit_headers *cmd_masks;
2970 int err;
2971 u8 cmd;
2972
6ae4a6a5
PB		 2973 err = offload_pedit_fields(priv, namespace, hdrs, parse_attr,
2974 action_flags, extack);
d79b6df6
OG		 2975 if (err < 0)
2976 goto out_dealloc_parsed_actions;
2977
2978 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
c500c86b 2979 cmd_masks = &hdrs[cmd].masks;
d79b6df6 2980 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2981 NL_SET_ERR_MSG_MOD(extack,
2982 "attempt to offload an unsupported field");
b3a433de 2983 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2984 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2985 16, 1, cmd_masks, sizeof(zero_masks), true);
2986 err = -EOPNOTSUPP;
2987 goto out_dealloc_parsed_actions;
2988 }
2989 }
2990
2991 return 0;
2992
2993out_dealloc_parsed_actions:
6ae4a6a5 2994 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
d79b6df6
OG		 2995 return err;
2996}
2997
e98bedf5
EB		 2998static bool csum_offload_supported(struct mlx5e_priv *priv,
2999 u32 action,
3000 u32 update_flags,
3001 struct netlink_ext_ack *extack)
26c02749
OG		 3002{
3003 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
3004 TCA_CSUM_UPDATE_FLAG_UDP;
3005
3006 /* The HW recalcs checksums only if re-writing headers */
3007 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 3008 NL_SET_ERR_MSG_MOD(extack,
3009 "TC csum action is only offloaded with pedit");
26c02749
OG		 3010 netdev_warn(priv->netdev,
3011 "TC csum action is only offloaded with pedit\n");
3012 return false;
3013 }
3014
3015 if (update_flags & ~prot_flags) {
e98bedf5
EB		 3016 NL_SET_ERR_MSG_MOD(extack,
3017 "can't offload TC csum action for some header/s");
26c02749
OG		 3018 netdev_warn(priv->netdev,
3019 "can't offload TC csum action for some header/s - flags %#x\n",
3020 update_flags);
3021 return false;
3022 }
3023
3024 return true;
3025}
3026
8998576b
DL		 3027struct ip_ttl_word {
3028 __u8 ttl;
3029 __u8 protocol;
3030 __sum16 check;
3031};
3032
3033struct ipv6_hoplimit_word {
3034 __be16 payload_len;
3035 __u8 nexthdr;
3036 __u8 hop_limit;
3037};
3038
1836d780
RD		 3039static bool
3040is_action_keys_supported(const struct flow_action_entry *act, bool ct_flow,
3041 bool *modify_ip_header, bool *modify_tuple,
3042 struct netlink_ext_ack *extack)
8998576b
DL		 3043{
3044 u32 mask, offset;
3045 u8 htype;
3046
3047 htype = act->mangle.htype;
3048 offset = act->mangle.offset;
3049 mask = ~act->mangle.mask;
3050 /* For IPv4 & IPv6 header check 4 byte word,
3051 * to determine that modified fields
3052 * are NOT ttl & hop_limit only.
3053 */
3054 if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3055 struct ip_ttl_word *ttl_word =
3056 (struct ip_ttl_word *)&mask;
3057
3058 if (offset != offsetof(struct iphdr, ttl) ||
3059 ttl_word->protocol ||
3060 ttl_word->check) {
4c3844d9
PB		 3061 *modify_ip_header = true;
3062 }
3063
7e36feeb
PB		 3064 if (offset >= offsetof(struct iphdr, saddr))
3065 *modify_tuple = true;
3066
3067 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3068 NL_SET_ERR_MSG_MOD(extack,
3069 "can't offload re-write of ipv4 address with action ct");
1836d780 3070 return false;
8998576b
DL		 3071 }
3072 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3073 struct ipv6_hoplimit_word *hoplimit_word =
3074 (struct ipv6_hoplimit_word *)&mask;
3075
3076 if (offset != offsetof(struct ipv6hdr, payload_len) ||
3077 hoplimit_word->payload_len ||
3078 hoplimit_word->nexthdr) {
4c3844d9
PB		 3079 *modify_ip_header = true;
3080 }
3081
7e36feeb
PB		 3082 if (ct_flow && offset >= offsetof(struct ipv6hdr, saddr))
3083 *modify_tuple = true;
3084
3085 if (ct_flow && *modify_tuple) {
4c3844d9
PB		 3086 NL_SET_ERR_MSG_MOD(extack,
3087 "can't offload re-write of ipv6 address with action ct");
1836d780 3088 return false;
8998576b 3089 }
7e36feeb
PB		 3090 } else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_TCP ||
3091 htype == FLOW_ACT_MANGLE_HDR_TYPE_UDP) {
3092 *modify_tuple = true;
3093 if (ct_flow) {
3094 NL_SET_ERR_MSG_MOD(extack,
3095 "can't offload re-write of transport header ports with action ct");
1836d780 3096 return false;
7e36feeb 3097 }
8998576b 3098 }
4c3844d9 3099
1836d780 3100 return true;
8998576b
DL		 3101}
3102
96b5b458
DC		 3103static bool modify_tuple_supported(bool modify_tuple, bool ct_clear,
3104 bool ct_flow, struct netlink_ext_ack *extack,
3105 struct mlx5e_priv *priv,
3106 struct mlx5_flow_spec *spec)
3107{
3108 if (!modify_tuple || ct_clear)
3109 return true;
3110
3111 if (ct_flow) {
3112 NL_SET_ERR_MSG_MOD(extack,
3113 "can't offload tuple modification with non-clear ct()");
3114 netdev_info(priv->netdev,
3115 "can't offload tuple modification with non-clear ct()");
3116 return false;
3117 }
3118
3119 /* Add ct_state=-trk match so it will be offloaded for non ct flows
3120 * (or after clear action), as otherwise, since the tuple is changed,
3121 * we can't restore ct state
3122 */
3123 if (mlx5_tc_ct_add_no_trk_match(spec)) {
3124 NL_SET_ERR_MSG_MOD(extack,
3125 "can't offload tuple modification with ct matches and no ct(clear) action");
3126 netdev_info(priv->netdev,
3127 "can't offload tuple modification with ct matches and no ct(clear) action");
3128 return false;
3129 }
3130
3131 return true;
3132}
3133
3d486ec4
OS		 3134static bool modify_header_match_supported(struct mlx5e_priv *priv,
3135 struct mlx5_flow_spec *spec,
73867881 3136 struct flow_action *flow_action,
4c3844d9 3137 u32 actions, bool ct_flow,
7e36feeb 3138 bool ct_clear,
e98bedf5 3139 struct netlink_ext_ack *extack)
bdd66ac0 3140{
73867881 3141 const struct flow_action_entry *act;
7e36feeb 3142 bool modify_ip_header, modify_tuple;
fca53304 3143 void *headers_c;
bdd66ac0
OG		 3144 void *headers_v;
3145 u16 ethertype;
8998576b 3146 u8 ip_proto;
1836d780 3147 int i;
bdd66ac0 3148
fca53304 3149 headers_c = get_match_headers_criteria(actions, spec);
8377629e 3150 headers_v = get_match_headers_value(actions, spec);
bdd66ac0
OG		 3151 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3152
3153 /* for non-IP we only re-write MACs, so we're okay */
fca53304
EB		 3154 if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3155 ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
bdd66ac0
OG		 3156 goto out_ok;
3157
3158 modify_ip_header = false;
7e36feeb 3159 modify_tuple = false;
73867881
PNA		 3160 flow_action_for_each(i, act, flow_action) {
3161 if (act->id != FLOW_ACTION_MANGLE &&
3162 act->id != FLOW_ACTION_ADD)
bdd66ac0
OG		 3163 continue;
3164
1836d780
RD		 3165 if (!is_action_keys_supported(act, ct_flow,
3166 &modify_ip_header,
3167 &modify_tuple, extack))
3168 return false;
bdd66ac0
OG		 3169 }
3170
96b5b458
DC		 3171 if (!modify_tuple_supported(modify_tuple, ct_clear, ct_flow, extack,
3172 priv, spec))
7e36feeb 3173 return false;
7e36feeb 3174
bdd66ac0 3175 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 3176 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3177 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 3178 NL_SET_ERR_MSG_MOD(extack,
3179 "can't offload re-write of non TCP/UDP");
3d486ec4
OS		 3180 netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3181 ip_proto);
bdd66ac0
OG		 3182 return false;
3183 }
3184
3185out_ok:
3186 return true;
3187}
3188
9c1d3511
RD		 3189static bool
3190actions_match_supported_fdb(struct mlx5e_priv *priv,
3191 struct mlx5e_tc_flow_parse_attr *parse_attr,
3192 struct mlx5e_tc_flow *flow,
3193 struct netlink_ext_ack *extack)
bdd66ac0 3194{
d4f401d9 3195 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
9c1d3511 3196 bool ct_flow, ct_clear;
bdd66ac0 3197
9c1d3511
RD		 3198 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
3199 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
3200
d4f401d9
RD		 3201 if (esw_attr->split_count && ct_flow &&
3202 !MLX5_CAP_GEN(esw_attr->in_mdev, reg_c_preserve)) {
9c1d3511
RD		 3203 /* All registers used by ct are cleared when using
3204 * split rules.
3205 */
3206 NL_SET_ERR_MSG_MOD(extack, "Can't offload mirroring with action ct");
3207 return false;
3208 }
3209
d4f401d9
RD		 3210 if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3211 NL_SET_ERR_MSG_MOD(extack,
3212 "current firmware doesn't support split rule for port mirroring");
3213 netdev_warn_once(priv->netdev,
3214 "current firmware doesn't support split rule for port mirroring\n");
3215 return false;
3216 }
3217
9c1d3511
RD		 3218 return true;
3219}
3220
3221static bool
3222actions_match_supported(struct mlx5e_priv *priv,
3223 struct flow_action *flow_action,
3224 struct mlx5e_tc_flow_parse_attr *parse_attr,
3225 struct mlx5e_tc_flow *flow,
3226 struct netlink_ext_ack *extack)
3227{
3228 u32 actions = flow->attr->action;
3229 bool ct_flow, ct_clear;
3230
3231 ct_clear = flow->attr->ct_attr.ct_action & TCA_CT_ACT_CLEAR;
c620b772 3232 ct_flow = flow_flag_test(flow, CT) && !ct_clear;
c620b772 3233
6b50cf45
RD		 3234 if (!(actions &
3235 (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
3236 NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
3237 return false;
3238 }
3239
9c1d3511
RD		 3240 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3241 !modify_header_match_supported(priv, &parse_attr->spec, flow_action,
3242 actions, ct_flow, ct_clear, extack))
3243 return false;
bdd66ac0 3244
9c1d3511
RD		 3245 if (mlx5e_is_eswitch_flow(flow) &&
3246 !actions_match_supported_fdb(priv, parse_attr, flow, extack))
3247 return false;
bdd66ac0
OG		 3248
3249 return true;
3250}
3251
32134847
MD		 3252static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3253{
3254 return priv->mdev == peer_priv->mdev;
3255}
3256
5c65c564
OG		 3257static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3258{
3259 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 3260 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 3261
3262 fmdev = priv->mdev;
3263 pmdev = peer_priv->mdev;
3264
59c9d35e
AH		 3265 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3266 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 3267
816f6706 3268 return (fsystem_guid == psystem_guid);
5c65c564
OG		 3269}
3270
bb569657
AL		 3271static bool same_vf_reps(struct mlx5e_priv *priv,
3272 struct net_device *out_dev)
3273{
3274 return mlx5e_eswitch_vf_rep(priv->netdev) &&
3275 priv->netdev == out_dev;
3276}
3277
bdc837ee
EB		 3278static int add_vlan_rewrite_action(struct mlx5e_priv *priv, int namespace,
3279 const struct flow_action_entry *act,
3280 struct mlx5e_tc_flow_parse_attr *parse_attr,
3281 struct pedit_headers_action *hdrs,
3282 u32 *action, struct netlink_ext_ack *extack)
3283{
3284 u16 mask16 = VLAN_VID_MASK;
3285 u16 val16 = act->vlan.vid & VLAN_VID_MASK;
3286 const struct flow_action_entry pedit_act = {
3287 .id = FLOW_ACTION_MANGLE,
3288 .mangle.htype = FLOW_ACT_MANGLE_HDR_TYPE_ETH,
3289 .mangle.offset = offsetof(struct vlan_ethhdr, h_vlan_TCI),
3290 .mangle.mask = ~(u32)be16_to_cpu(*(__be16 *)&mask16),
3291 .mangle.val = (u32)be16_to_cpu(*(__be16 *)&val16),
3292 };
6fca9d1e 3293 u8 match_prio_mask, match_prio_val;
bf2f3bca 3294 void *headers_c, *headers_v;
bdc837ee
EB		 3295 int err;
3296
bf2f3bca
EB		 3297 headers_c = get_match_headers_criteria(*action, &parse_attr->spec);
3298 headers_v = get_match_headers_value(*action, &parse_attr->spec);
3299
3300 if (!(MLX5_GET(fte_match_set_lyr_2_4, headers_c, cvlan_tag) &&
3301 MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag))) {
3302 NL_SET_ERR_MSG_MOD(extack,
3303 "VLAN rewrite action must have VLAN protocol match");
3304 return -EOPNOTSUPP;
3305 }
3306
6fca9d1e
EB		 3307 match_prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
3308 match_prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
3309 if (act->vlan.prio != (match_prio_val & match_prio_mask)) {
3310 NL_SET_ERR_MSG_MOD(extack,
3311 "Changing VLAN prio is not supported");
bdc837ee
EB		 3312 return -EOPNOTSUPP;
3313 }
3314
582234b4 3315 err = parse_tc_pedit_action(priv, &pedit_act, namespace, parse_attr, hdrs, NULL, extack);
bdc837ee
EB		 3316 *action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3317
3318 return err;
3319}
3320
0bac1194
EB		 3321static int
3322add_vlan_prio_tag_rewrite_action(struct mlx5e_priv *priv,
3323 struct mlx5e_tc_flow_parse_attr *parse_attr,
3324 struct pedit_headers_action *hdrs,
3325 u32 *action, struct netlink_ext_ack *extack)
3326{
3327 const struct flow_action_entry prio_tag_act = {
3328 .vlan.vid = 0,
3329 .vlan.prio =
3330 MLX5_GET(fte_match_set_lyr_2_4,
3331 get_match_headers_value(*action,
3332 &parse_attr->spec),
3333 first_prio) &
3334 MLX5_GET(fte_match_set_lyr_2_4,
3335 get_match_headers_criteria(*action,
3336 &parse_attr->spec),
3337 first_prio),
3338 };
3339
3340 return add_vlan_rewrite_action(priv, MLX5_FLOW_NAMESPACE_FDB,
3341 &prio_tag_act, parse_attr, hdrs, action,
3342 extack);
3343}
3344
c7569097
AL		 3345static int validate_goto_chain(struct mlx5e_priv *priv,
3346 struct mlx5e_tc_flow *flow,
3347 const struct flow_action_entry *act,
3348 u32 actions,
3349 struct netlink_ext_ack *extack)
3350{
3351 bool is_esw = mlx5e_is_eswitch_flow(flow);
3352 struct mlx5_flow_attr *attr = flow->attr;
3353 bool ft_flow = mlx5e_is_ft_flow(flow);
3354 u32 dest_chain = act->chain_index;
3355 struct mlx5_fs_chains *chains;
3356 struct mlx5_eswitch *esw;
3357 u32 reformat_and_fwd;
3358 u32 max_chain;
3359
3360 esw = priv->mdev->priv.eswitch;
3361 chains = is_esw ? esw_chains(esw) : nic_chains(priv);
3362 max_chain = mlx5_chains_get_chain_range(chains);
3363 reformat_and_fwd = is_esw ?
3364 MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, reformat_and_fwd_to_table) :
3365 MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, reformat_and_fwd_to_table);
3366
3367 if (ft_flow) {
3368 NL_SET_ERR_MSG_MOD(extack, "Goto action is not supported");
3369 return -EOPNOTSUPP;
3370 }
3371
3372 if (!mlx5_chains_backwards_supported(chains) &&
3373 dest_chain <= attr->chain) {
3374 NL_SET_ERR_MSG_MOD(extack,
3375 "Goto lower numbered chain isn't supported");
3376 return -EOPNOTSUPP;
3377 }
3378
3379 if (dest_chain > max_chain) {
3380 NL_SET_ERR_MSG_MOD(extack,
3381 "Requested destination chain is out of supported range");
3382 return -EOPNOTSUPP;
3383 }
3384
3385 if (actions & (MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
3386 MLX5_FLOW_CONTEXT_ACTION_DECAP) &&
3387 !reformat_and_fwd) {
3388 NL_SET_ERR_MSG_MOD(extack,
3389 "Goto chain is not allowed if action has reformat or decap");
3390 return -EOPNOTSUPP;
3391 }
3392
3393 return 0;
3394}
3395
d9581e2f
RD		 3396static int
3397actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
e98bedf5 3398 struct mlx5e_tc_flow *flow,
d9581e2f
RD		 3399 struct mlx5_flow_attr *attr,
3400 struct pedit_headers_action *hdrs,
e98bedf5 3401 struct netlink_ext_ack *extack)
d9581e2f
RD		 3402{
3403 struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3404 enum mlx5_flow_namespace_type ns_type;
3405 int err;
3406
3407 if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3408 !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3409 return 0;
3410
3411 ns_type = get_flow_name_space(flow);
3412
3413 err = alloc_tc_pedit_action(priv, ns_type, parse_attr, hdrs,
3414 &attr->action, extack);
3415 if (err)
3416 return err;
3417
3418 /* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3419 if (parse_attr->mod_hdr_acts.num_actions > 0)
3420 return 0;
3421
3422 attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3423 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
3424
3425 if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3426 return 0;
3427
3428 if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3429 (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3430 attr->esw_attr->split_count = 0;
3431
3432 return 0;
3433}
3434
3435static int
3436parse_tc_nic_actions(struct mlx5e_priv *priv,
3437 struct flow_action *flow_action,
3438 struct mlx5e_tc_flow *flow,
3439 struct netlink_ext_ack *extack)
e3a2b7ed 3440{
c6cfe113 3441 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 3442 struct mlx5_flow_attr *attr = flow->attr;
73867881
PNA		 3443 struct pedit_headers_action hdrs[2] = {};
3444 const struct flow_action_entry *act;
c620b772 3445 struct mlx5_nic_flow_attr *nic_attr;
1cab1cd7 3446 u32 action = 0;
244cd96a 3447 int err, i;
e3a2b7ed 3448
0885ae1a
A		 3449 if (!flow_action_has_entries(flow_action)) {
3450 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
e3a2b7ed 3451 return -EINVAL;
0885ae1a 3452 }
e3a2b7ed 3453
53eca1f3 3454 if (!flow_action_hw_stats_check(flow_action, extack,
0885ae1a
A		 3455 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3456 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 3457 return -EOPNOTSUPP;
0885ae1a 3458 }
319a1d19 3459
c620b772 3460 nic_attr = attr->nic_attr;
c620b772 3461 nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
c6cfe113 3462 parse_attr = attr->parse_attr;
e3a2b7ed 3463
73867881
PNA		 3464 flow_action_for_each(i, act, flow_action) {
3465 switch (act->id) {
15fc92ec
TZ		 3466 case FLOW_ACTION_ACCEPT:
3467 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3468 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3469 break;
73867881 3470 case FLOW_ACTION_DROP:
950b4df9
RD		 3471 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3472 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881
PNA		 3473 break;
3474 case FLOW_ACTION_MANGLE:
3475 case FLOW_ACTION_ADD:
3476 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_KERNEL,
582234b4 3477 parse_attr, hdrs, NULL, extack);
2f4fe4ca
OG		 3478 if (err)
3479 return err;
3480
c7569097 3481 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
73867881 3482 break;
bdc837ee
EB		 3483 case FLOW_ACTION_VLAN_MANGLE:
3484 err = add_vlan_rewrite_action(priv,
3485 MLX5_FLOW_NAMESPACE_KERNEL,
3486 act, parse_attr, hdrs,
3487 &action, extack);
3488 if (err)
3489 return err;
3490
3491 break;
73867881 3492 case FLOW_ACTION_CSUM:
1cab1cd7 3493 if (csum_offload_supported(priv, action,
73867881 3494 act->csum_flags,
e98bedf5 3495 extack))
73867881 3496 break;
26c02749
OG		 3497
3498 return -EOPNOTSUPP;
73867881
PNA		 3499 case FLOW_ACTION_REDIRECT: {
3500 struct net_device *peer_dev = act->dev;
5c65c564
OG		 3501
3502 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
3503 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 3504 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
226f2ca3 3505 flow_flag_set(flow, HAIRPIN);
1cab1cd7
OG		 3506 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3507 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 3508 } else {
e98bedf5
EB		 3509 NL_SET_ERR_MSG_MOD(extack,
3510 "device is not on same HW, can't offload");
5c65c564
OG		 3511 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
3512 peer_dev->name);
25f150f4 3513 return -EOPNOTSUPP;
5c65c564 3514 }
73867881
PNA		 3515 }
3516 break;
3517 case FLOW_ACTION_MARK: {
3518 u32 mark = act->mark;
e3a2b7ed
AV		 3519
3520 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 3521 NL_SET_ERR_MSG_MOD(extack,
3522 "Bad flow mark - only 16 bit is supported");
25f150f4 3523 return -EOPNOTSUPP;
e3a2b7ed
AV		 3524 }
3525
c620b772 3526 nic_attr->flow_tag = mark;
1cab1cd7 3527 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
73867881
PNA		 3528 }
3529 break;
c7569097
AL		 3530 case FLOW_ACTION_GOTO:
3531 err = validate_goto_chain(priv, flow, act, action,
3532 extack);
3533 if (err)
3534 return err;
3535
7f8770c7
RD		 3536 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3537 MLX5_FLOW_CONTEXT_ACTION_COUNT;
c7569097
AL		 3538 attr->dest_chain = act->chain_index;
3539 break;
aedd133d
AL		 3540 case FLOW_ACTION_CT:
3541 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
3542 if (err)
3543 return err;
3544
3545 flow_flag_set(flow, CT);
3546 break;
73867881 3547 default:
0885ae1a
A		 3548 NL_SET_ERR_MSG_MOD(extack,
3549 "The offload action is not supported in NIC action");
2cc1cb1d 3550 return -EOPNOTSUPP;
e3a2b7ed 3551 }
e3a2b7ed
AV		 3552 }
3553
1cab1cd7 3554 attr->action = action;
c7569097 3555
7f8770c7
RD		 3556 if (attr->dest_chain && parse_attr->mirred_ifindex[0]) {
3557 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
3558 return -EOPNOTSUPP;
c7569097
AL		 3559 }
3560
d9581e2f
RD		 3561 err = actions_prepare_mod_hdr_actions(priv, flow, attr, hdrs, extack);
3562 if (err)
3563 return err;
3564
73867881 3565 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 3566 return -EOPNOTSUPP;
3567
e3a2b7ed
AV		 3568 return 0;
3569}
3570
32134847 3571static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
b1d90e6b
RL		 3572 struct net_device *peer_netdev)
3573{
3574 struct mlx5e_priv *peer_priv;
3575
3576 peer_priv = netdev_priv(peer_netdev);
3577
3578 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
32134847
MD		 3579 mlx5e_eswitch_vf_rep(priv->netdev) &&
3580 mlx5e_eswitch_vf_rep(peer_netdev) &&
68931c7d 3581 same_hw_devs(priv, peer_priv));
b1d90e6b
RL		 3582}
3583
1482bd3d 3584static int parse_tc_vlan_action(struct mlx5e_priv *priv,
73867881 3585 const struct flow_action_entry *act,
1482bd3d 3586 struct mlx5_esw_flow_attr *attr,
0885ae1a
A		 3587 u32 *action,
3588 struct netlink_ext_ack *extack)
1482bd3d 3589{
cc495188
JL		 3590 u8 vlan_idx = attr->total_vlan;
3591
0885ae1a
A		 3592 if (vlan_idx >= MLX5_FS_VLAN_DEPTH) {
3593 NL_SET_ERR_MSG_MOD(extack, "Total vlans used is greater than supported");
cc495188 3594 return -EOPNOTSUPP;
0885ae1a 3595 }
cc495188 3596
73867881
PNA		 3597 switch (act->id) {
3598 case FLOW_ACTION_VLAN_POP:
cc495188
JL		 3599 if (vlan_idx) {
3600 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
0885ae1a
A		 3601 MLX5_FS_VLAN_DEPTH)) {
3602 NL_SET_ERR_MSG_MOD(extack,
3603 "vlan pop action is not supported");
cc495188 3604 return -EOPNOTSUPP;
0885ae1a 3605 }
cc495188
JL		 3606
3607 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
3608 } else {
3609 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
3610 }
73867881
PNA		 3611 break;
3612 case FLOW_ACTION_VLAN_PUSH:
3613 attr->vlan_vid[vlan_idx] = act->vlan.vid;
3614 attr->vlan_prio[vlan_idx] = act->vlan.prio;
3615 attr->vlan_proto[vlan_idx] = act->vlan.proto;
cc495188
JL		 3616 if (!attr->vlan_proto[vlan_idx])
3617 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
3618
3619 if (vlan_idx) {
3620 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
0885ae1a
A		 3621 MLX5_FS_VLAN_DEPTH)) {
3622 NL_SET_ERR_MSG_MOD(extack,
3623 "vlan push action is not supported for vlan depth > 1");
cc495188 3624 return -EOPNOTSUPP;
0885ae1a 3625 }
cc495188
JL		 3626
3627 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
3628 } else {
3629 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
73867881 3630 (act->vlan.proto != htons(ETH_P_8021Q) ||
0885ae1a
A		 3631 act->vlan.prio)) {
3632 NL_SET_ERR_MSG_MOD(extack,
3633 "vlan push action is not supported");
cc495188 3634 return -EOPNOTSUPP;
0885ae1a 3635 }
cc495188
JL		 3636
3637 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d 3638 }
73867881
PNA		 3639 break;
3640 default:
0885ae1a 3641 NL_SET_ERR_MSG_MOD(extack, "Unexpected action id for VLAN");
bdc837ee 3642 return -EINVAL;
1482bd3d
JL		 3643 }
3644
cc495188
JL		 3645 attr->total_vlan = vlan_idx + 1;
3646
1482bd3d
JL		 3647 return 0;
3648}
3649
d34eb2fc
OG		 3650static struct net_device *get_fdb_out_dev(struct net_device *uplink_dev,
3651 struct net_device *out_dev)
3652{
3653 struct net_device *fdb_out_dev = out_dev;
3654 struct net_device *uplink_upper;
3655
3656 rcu_read_lock();
3657 uplink_upper = netdev_master_upper_dev_get_rcu(uplink_dev);
3658 if (uplink_upper && netif_is_lag_master(uplink_upper) &&
3659 uplink_upper == out_dev) {
3660 fdb_out_dev = uplink_dev;
3661 } else if (netif_is_lag_master(out_dev)) {
3662 fdb_out_dev = bond_option_active_slave_get_rcu(netdev_priv(out_dev));
3663 if (fdb_out_dev &&
3664 (!mlx5e_eswitch_rep(fdb_out_dev) ||
3665 !netdev_port_same_parent_id(fdb_out_dev, uplink_dev)))
3666 fdb_out_dev = NULL;
3667 }
3668 rcu_read_unlock();
3669 return fdb_out_dev;
3670}
3671
278748a9 3672static int add_vlan_push_action(struct mlx5e_priv *priv,
c620b772 3673 struct mlx5_flow_attr *attr,
278748a9 3674 struct net_device **out_dev,
0885ae1a
A		 3675 u32 *action,
3676 struct netlink_ext_ack *extack)
278748a9
EB		 3677{
3678 struct net_device *vlan_dev = *out_dev;
3679 struct flow_action_entry vlan_act = {
3680 .id = FLOW_ACTION_VLAN_PUSH,
3681 .vlan.vid = vlan_dev_vlan_id(vlan_dev),
3682 .vlan.proto = vlan_dev_vlan_proto(vlan_dev),
3683 .vlan.prio = 0,
3684 };
3685 int err;
3686
0885ae1a 3687 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action, extack);
278748a9
EB		 3688 if (err)
3689 return err;
3690
dca59f4a
DC		 3691 rcu_read_lock();
3692 *out_dev = dev_get_by_index_rcu(dev_net(vlan_dev), dev_get_iflink(vlan_dev));
3693 rcu_read_unlock();
3694 if (!*out_dev)
3695 return -ENODEV;
3696
278748a9 3697 if (is_vlan_dev(*out_dev))
0885ae1a 3698 err = add_vlan_push_action(priv, attr, out_dev, action, extack);
278748a9
EB		 3699
3700 return err;
3701}
3702
35a605db 3703static int add_vlan_pop_action(struct mlx5e_priv *priv,
c620b772 3704 struct mlx5_flow_attr *attr,
0885ae1a
A		 3705 u32 *action,
3706 struct netlink_ext_ack *extack)
35a605db 3707{
35a605db
EB		 3708 struct flow_action_entry vlan_act = {
3709 .id = FLOW_ACTION_VLAN_POP,
3710 };
70f478ca 3711 int nest_level, err = 0;
35a605db 3712
70f478ca
DL		 3713 nest_level = attr->parse_attr->filter_dev->lower_level -
3714 priv->netdev->lower_level;
35a605db 3715 while (nest_level--) {
0885ae1a 3716 err = parse_tc_vlan_action(priv, &vlan_act, attr->esw_attr, action, extack);
35a605db
EB		 3717 if (err)
3718 return err;
3719 }
3720
3721 return err;
3722}
3723
32134847
MD		 3724static bool same_hw_reps(struct mlx5e_priv *priv,
3725 struct net_device *peer_netdev)
3726{
3727 struct mlx5e_priv *peer_priv;
3728
3729 peer_priv = netdev_priv(peer_netdev);
3730
3731 return mlx5e_eswitch_rep(priv->netdev) &&
3732 mlx5e_eswitch_rep(peer_netdev) &&
3733 same_hw_devs(priv, peer_priv);
3734}
3735
3736static bool is_lag_dev(struct mlx5e_priv *priv,
3737 struct net_device *peer_netdev)
3738{
3739 return ((mlx5_lag_is_sriov(priv->mdev) ||
3740 mlx5_lag_is_multipath(priv->mdev)) &&
3741 same_hw_reps(priv, peer_netdev));
3742}
3743
f6dc1264
PB		 3744bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
3745 struct net_device *out_dev)
3746{
32134847
MD		 3747 if (is_merged_eswitch_vfs(priv, out_dev))
3748 return true;
3749
3750 if (is_lag_dev(priv, out_dev))
f6dc1264
PB		 3751 return true;
3752
3753 return mlx5e_eswitch_rep(out_dev) &&
32134847 3754 same_port_devs(priv, netdev_priv(out_dev));
f6dc1264
PB		 3755}
3756
554fe75c
DL		 3757static bool is_duplicated_output_device(struct net_device *dev,
3758 struct net_device *out_dev,
3759 int *ifindexes, int if_count,
3760 struct netlink_ext_ack *extack)
3761{
3762 int i;
3763
3764 for (i = 0; i < if_count; i++) {
3765 if (ifindexes[i] == out_dev->ifindex) {
3766 NL_SET_ERR_MSG_MOD(extack,
3767 "can't duplicate output to same device");
3768 netdev_err(dev, "can't duplicate output to same device: %s\n",
3769 out_dev->name);
3770 return true;
3771 }
3772 }
3773
3774 return false;
3775}
3776
613f53fe
EC		 3777static int verify_uplink_forwarding(struct mlx5e_priv *priv,
3778 struct mlx5e_tc_flow *flow,
3779 struct net_device *out_dev,
3780 struct netlink_ext_ack *extack)
3781{
c620b772 3782 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
613f53fe 3783 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
613f53fe
EC		 3784 struct mlx5e_rep_priv *rep_priv;
3785
3786 /* Forwarding non encapsulated traffic between
3787 * uplink ports is allowed only if
3788 * termination_table_raw_traffic cap is set.
3789 *
c620b772 3790 * Input vport was stored attr->in_rep.
613f53fe
EC		 3791 * In LAG case, *priv* is the private data of
3792 * uplink which may be not the input vport.
3793 */
3794 rep_priv = mlx5e_rep_to_rep_priv(attr->in_rep);
3795
3796 if (!(mlx5e_eswitch_uplink_rep(rep_priv->netdev) &&
3797 mlx5e_eswitch_uplink_rep(out_dev)))
3798 return 0;
3799
3800 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(esw->dev,
3801 termination_table_raw_traffic)) {
3802 NL_SET_ERR_MSG_MOD(extack,
3803 "devices are both uplink, can't offload forwarding");
3804 pr_err("devices %s %s are both uplink, can't offload forwarding\n",
3805 priv->netdev->name, out_dev->name);
3806 return -EOPNOTSUPP;
3807 } else if (out_dev != rep_priv->netdev) {
3808 NL_SET_ERR_MSG_MOD(extack,
3809 "devices are not the same uplink, can't offload forwarding");
3810 pr_err("devices %s %s are both uplink but not the same, can't offload forwarding\n",
3811 priv->netdev->name, out_dev->name);
3812 return -EOPNOTSUPP;
3813 }
3814 return 0;
3815}
3816
73867881
PNA		 3817static int parse_tc_fdb_actions(struct mlx5e_priv *priv,
3818 struct flow_action *flow_action,
e98bedf5 3819 struct mlx5e_tc_flow *flow,
70f8019e 3820 struct netlink_ext_ack *extack)
03a9d11e 3821{
73867881 3822 struct pedit_headers_action hdrs[2] = {};
bf07aa73 3823 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 3824 struct mlx5e_tc_flow_parse_attr *parse_attr;
1d447a39 3825 struct mlx5e_rep_priv *rpriv = priv->ppriv;
bcd6740c 3826 struct mlx5e_sample_attr sample_attr = {};
73867881 3827 const struct ip_tunnel_info *info = NULL;
c620b772 3828 struct mlx5_flow_attr *attr = flow->attr;
554fe75c 3829 int ifindexes[MLX5_MAX_FLOW_FWD_VPORTS];
84179981 3830 bool ft_flow = mlx5e_is_ft_flow(flow);
73867881 3831 const struct flow_action_entry *act;
c620b772 3832 struct mlx5_esw_flow_attr *esw_attr;
0a7fcb78
PB		 3833 bool encap = false, decap = false;
3834 u32 action = attr->action;
554fe75c 3835 int err, i, if_count = 0;
f828ca6a 3836 bool mpls_push = false;
03a9d11e 3837
0885ae1a
A		 3838 if (!flow_action_has_entries(flow_action)) {
3839 NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
03a9d11e 3840 return -EINVAL;
0885ae1a 3841 }
03a9d11e 3842
53eca1f3 3843 if (!flow_action_hw_stats_check(flow_action, extack,
0885ae1a
A		 3844 FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
3845 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 3846 return -EOPNOTSUPP;
0885ae1a 3847 }
319a1d19 3848
c620b772
AL		 3849 esw_attr = attr->esw_attr;
3850 parse_attr = attr->parse_attr;
3851
73867881
PNA		 3852 flow_action_for_each(i, act, flow_action) {
3853 switch (act->id) {
6ba2e2b3
VB		 3854 case FLOW_ACTION_ACCEPT:
3855 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3856 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3857 attr->flags |= MLX5_ESW_ATTR_FLAG_ACCEPT;
3858 break;
73867881 3859 case FLOW_ACTION_DROP:
1cab1cd7
OG		 3860 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
3861 MLX5_FLOW_CONTEXT_ACTION_COUNT;
73867881 3862 break;
f0288210
EC		 3863 case FLOW_ACTION_TRAP:
3864 if (!flow_offload_has_one_action(flow_action)) {
3865 NL_SET_ERR_MSG_MOD(extack,
3866 "action trap is supported as a sole action only");
3867 return -EOPNOTSUPP;
3868 }
3869 action |= (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3870 MLX5_FLOW_CONTEXT_ACTION_COUNT);
3871 attr->flags |= MLX5_ESW_ATTR_FLAG_SLOW_PATH;
3872 break;
f828ca6a
EC		 3873 case FLOW_ACTION_MPLS_PUSH:
3874 if (!MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3875 reformat_l2_to_l3_tunnel) ||
3876 act->mpls_push.proto != htons(ETH_P_MPLS_UC)) {
3877 NL_SET_ERR_MSG_MOD(extack,
3878 "mpls push is supported only for mpls_uc protocol");
3879 return -EOPNOTSUPP;
3880 }
3881 mpls_push = true;
3882 break;
14e6b038
EC		 3883 case FLOW_ACTION_MPLS_POP:
3884 /* we only support mpls pop if it is the first action
3885 * and the filter net device is bareudp. Subsequent
3886 * actions can be pedit and the last can be mirred
3887 * egress redirect.
3888 */
3889 if (i) {
3890 NL_SET_ERR_MSG_MOD(extack,
3891 "mpls pop supported only as first action");
3892 return -EOPNOTSUPP;
3893 }
70f8019e 3894 if (!netif_is_bareudp(parse_attr->filter_dev)) {
14e6b038
EC		 3895 NL_SET_ERR_MSG_MOD(extack,
3896 "mpls pop supported only on bareudp devices");
3897 return -EOPNOTSUPP;
3898 }
3899
3900 parse_attr->eth.h_proto = act->mpls_pop.proto;
3901 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
3902 flow_flag_set(flow, L3_TO_L2_DECAP);
3903 break;
73867881
PNA		 3904 case FLOW_ACTION_MANGLE:
3905 case FLOW_ACTION_ADD:
3906 err = parse_tc_pedit_action(priv, act, MLX5_FLOW_NAMESPACE_FDB,
582234b4 3907 parse_attr, hdrs, flow, extack);
d7e75a32
OG		 3908 if (err)
3909 return err;
3910
582234b4
EC		 3911 if (!flow_flag_test(flow, L3_TO_L2_DECAP)) {
3912 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
c620b772 3913 esw_attr->split_count = esw_attr->out_count;
582234b4 3914 }
73867881
PNA		 3915 break;
3916 case FLOW_ACTION_CSUM:
1cab1cd7 3917 if (csum_offload_supported(priv, action,
73867881
PNA		 3918 act->csum_flags, extack))
3919 break;
26c02749
OG		 3920
3921 return -EOPNOTSUPP;
73867881
PNA		 3922 case FLOW_ACTION_REDIRECT:
3923 case FLOW_ACTION_MIRRED: {
03a9d11e 3924 struct mlx5e_priv *out_priv;
592d3651 3925 struct net_device *out_dev;
03a9d11e 3926
73867881 3927 out_dev = act->dev;
ef381359
OS		 3928 if (!out_dev) {
3929 /* out_dev is NULL when filters with
3930 * non-existing mirred device are replayed to
3931 * the driver.
3932 */
3933 return -EINVAL;
3934 }
03a9d11e 3935
f828ca6a
EC		 3936 if (mpls_push && !netif_is_bareudp(out_dev)) {
3937 NL_SET_ERR_MSG_MOD(extack,
3938 "mpls is supported only through a bareudp device");
3939 return -EOPNOTSUPP;
3940 }
3941
84179981
PB		 3942 if (ft_flow && out_dev == priv->netdev) {
3943 /* Ignore forward to self rules generated
3944 * by adding both mlx5 devs to the flow table
3945 * block on a normal nft offload setup.
3946 */
3947 return -EOPNOTSUPP;
3948 }
3949
c620b772 3950 if (esw_attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 3951 NL_SET_ERR_MSG_MOD(extack,
3952 "can't support more output ports, can't offload forwarding");
4ccd83f4
RD		 3953 netdev_warn(priv->netdev,
3954 "can't support more than %d output ports, can't offload forwarding\n",
c620b772 3955 esw_attr->out_count);
592d3651
CM		 3956 return -EOPNOTSUPP;
3957 }
3958
f493f155
EB		 3959 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
3960 MLX5_FLOW_CONTEXT_ACTION_COUNT;
b6a4ac24 3961 if (encap) {
c620b772 3962 parse_attr->mirred_ifindex[esw_attr->out_count] =
b6a4ac24 3963 out_dev->ifindex;
0d9f9647
VB		 3964 parse_attr->tun_info[esw_attr->out_count] =
3965 mlx5e_dup_tun_info(info);
c620b772 3966 if (!parse_attr->tun_info[esw_attr->out_count])
b6a4ac24
VB		 3967 return -ENOMEM;
3968 encap = false;
c620b772 3969 esw_attr->dests[esw_attr->out_count].flags |=
b6a4ac24 3970 MLX5_ESW_DEST_ENCAP;
c620b772 3971 esw_attr->out_count++;
b6a4ac24
VB		 3972 /* attr->dests[].rep is resolved when we
3973 * handle encap
3974 */
3975 } else if (netdev_port_same_parent_id(priv->netdev, out_dev)) {
7ba58ba7
RL		 3976 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3977 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
7ba58ba7 3978
554fe75c
DL		 3979 if (is_duplicated_output_device(priv->netdev,
3980 out_dev,
3981 ifindexes,
3982 if_count,
3983 extack))
3984 return -EOPNOTSUPP;
3985
3986 ifindexes[if_count] = out_dev->ifindex;
3987 if_count++;
3988
d34eb2fc
OG		 3989 out_dev = get_fdb_out_dev(uplink_dev, out_dev);
3990 if (!out_dev)
3991 return -ENODEV;
7ba58ba7 3992
278748a9
EB		 3993 if (is_vlan_dev(out_dev)) {
3994 err = add_vlan_push_action(priv, attr,
3995 &out_dev,
0885ae1a 3996 &action, extack);
278748a9
EB		 3997 if (err)
3998 return err;
3999 }
f6dc1264 4000
35a605db
EB		 4001 if (is_vlan_dev(parse_attr->filter_dev)) {
4002 err = add_vlan_pop_action(priv, attr,
0885ae1a 4003 &action, extack);
35a605db
EB		 4004 if (err)
4005 return err;
4006 }
278748a9 4007
fca572f2
DC		 4008 if (netif_is_macvlan(out_dev))
4009 out_dev = macvlan_dev_real_dev(out_dev);
4010
613f53fe
EC		 4011 err = verify_uplink_forwarding(priv, flow, out_dev, extack);
4012 if (err)
4013 return err;
ffec9702 4014
f6dc1264
PB		 4015 if (!mlx5e_is_valid_eswitch_fwd_dev(priv, out_dev)) {
4016 NL_SET_ERR_MSG_MOD(extack,
4017 "devices are not on same switch HW, can't offload forwarding");
a0646c88 4018 return -EOPNOTSUPP;
f6dc1264 4019 }
a0646c88 4020
bb569657
AL		 4021 if (same_vf_reps(priv, out_dev)) {
4022 NL_SET_ERR_MSG_MOD(extack,
4023 "can't forward from a VF to itself");
4024 return -EOPNOTSUPP;
4025 }
4026
a54e20b4 4027 out_priv = netdev_priv(out_dev);
1d447a39 4028 rpriv = out_priv->ppriv;
c620b772
AL		 4029 esw_attr->dests[esw_attr->out_count].rep = rpriv->rep;
4030 esw_attr->dests[esw_attr->out_count].mdev = out_priv->mdev;
4031 esw_attr->out_count++;
ef381359
OS		 4032 } else if (parse_attr->filter_dev != priv->netdev) {
4033 /* All mlx5 devices are called to configure
4034 * high level device filters. Therefore, the
4035 * *attempt* to install a filter on invalid
4036 * eswitch should not trigger an explicit error
4037 */
4038 return -EINVAL;
a54e20b4 4039 } else {
e98bedf5
EB		 4040 NL_SET_ERR_MSG_MOD(extack,
4041 "devices are not on same switch HW, can't offload forwarding");
4ccd83f4
RD		 4042 netdev_warn(priv->netdev,
4043 "devices %s %s not on same switch HW, can't offload forwarding\n",
4044 priv->netdev->name,
4045 out_dev->name);
25f150f4 4046 return -EOPNOTSUPP;
03a9d11e 4047 }
73867881
PNA		 4048 }
4049 break;
4050 case FLOW_ACTION_TUNNEL_ENCAP:
4051 info = act->tunnel;
0885ae1a 4052 if (info) {
a54e20b4 4053 encap = true;
0885ae1a
A		 4054 } else {
4055 NL_SET_ERR_MSG_MOD(extack,
4056 "Zero tunnel attributes is not supported");
a54e20b4 4057 return -EOPNOTSUPP;
0885ae1a 4058 }
1482bd3d 4059
73867881
PNA		 4060 break;
4061 case FLOW_ACTION_VLAN_PUSH:
4062 case FLOW_ACTION_VLAN_POP:
76b496b1
EB		 4063 if (act->id == FLOW_ACTION_VLAN_PUSH &&
4064 (action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP)) {
4065 /* Replace vlan pop+push with vlan modify */
4066 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4067 err = add_vlan_rewrite_action(priv,
4068 MLX5_FLOW_NAMESPACE_FDB,
4069 act, parse_attr, hdrs,
4070 &action, extack);
4071 } else {
0885ae1a 4072 err = parse_tc_vlan_action(priv, act, esw_attr, &action, extack);
76b496b1 4073 }
1482bd3d
JL		 4074 if (err)
4075 return err;
4076
c620b772 4077 esw_attr->split_count = esw_attr->out_count;
bdc837ee
EB		 4078 break;
4079 case FLOW_ACTION_VLAN_MANGLE:
4080 err = add_vlan_rewrite_action(priv,
4081 MLX5_FLOW_NAMESPACE_FDB,
4082 act, parse_attr, hdrs,
4083 &action, extack);
4084 if (err)
4085 return err;
4086
c620b772 4087 esw_attr->split_count = esw_attr->out_count;
73867881
PNA		 4088 break;
4089 case FLOW_ACTION_TUNNEL_DECAP:
0a7fcb78 4090 decap = true;
73867881 4091 break;
2fbbc30d 4092 case FLOW_ACTION_GOTO:
c7569097
AL		 4093 err = validate_goto_chain(priv, flow, act, action,
4094 extack);
2fbbc30d
EC		 4095 if (err)
4096 return err;
bf07aa73 4097
7f8770c7
RD		 4098 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
4099 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2fbbc30d 4100 attr->dest_chain = act->chain_index;
73867881 4101 break;
4c3844d9 4102 case FLOW_ACTION_CT:
41c2fd94
CM		 4103 if (flow_flag_test(flow, SAMPLE)) {
4104 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4105 return -EOPNOTSUPP;
4106 }
aedd133d 4107 err = mlx5_tc_ct_parse_action(get_ct_priv(priv), attr, act, extack);
4c3844d9
PB		 4108 if (err)
4109 return err;
4110
4111 flow_flag_set(flow, CT);
69e2916e 4112 esw_attr->split_count = esw_attr->out_count;
4c3844d9 4113 break;
41c2fd94
CM		 4114 case FLOW_ACTION_SAMPLE:
4115 if (flow_flag_test(flow, CT)) {
4116 NL_SET_ERR_MSG_MOD(extack, "Sample action with connection tracking is not supported");
4117 return -EOPNOTSUPP;
4118 }
bcd6740c
CM		 4119 sample_attr.rate = act->sample.rate;
4120 sample_attr.group_num = act->sample.psample_group->group_num;
41c2fd94 4121 if (act->sample.truncate)
bcd6740c 4122 sample_attr.trunc_size = act->sample.trunc_size;
41c2fd94
CM		 4123 flow_flag_set(flow, SAMPLE);
4124 break;
73867881 4125 default:
0885ae1a
A		 4126 NL_SET_ERR_MSG_MOD(extack,
4127 "The offload action is not supported in FDB action");
2cc1cb1d 4128 return -EOPNOTSUPP;
bf07aa73 4129 }
03a9d11e 4130 }
bdd66ac0 4131
a508728a
VB		 4132 /* always set IP version for indirect table handling */
4133 attr->ip_version = mlx5e_tc_get_ip_version(&parse_attr->spec, true);
4134
0bac1194
EB		 4135 if (MLX5_CAP_GEN(esw->dev, prio_tag_required) &&
4136 action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) {
4137 /* For prio tag mode, replace vlan pop with rewrite vlan prio
4138 * tag rewrite.
4139 */
4140 action &= ~MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
4141 err = add_vlan_prio_tag_rewrite_action(priv, parse_attr, hdrs,
4142 &action, extack);
4143 if (err)
4144 return err;
4145 }
4146
1cab1cd7 4147 attr->action = action;
d9581e2f
RD		 4148
4149 err = actions_prepare_mod_hdr_actions(priv, flow, attr, hdrs, extack);
4150 if (err)
4151 return err;
4152
73867881 4153 if (!actions_match_supported(priv, flow_action, parse_attr, flow, extack))
bdd66ac0
OG		 4154 return -EOPNOTSUPP;
4155
7f8770c7
RD		 4156 if (attr->dest_chain && decap) {
4157 /* It can be supported if we'll create a mapping for
4158 * the tunnel device only (without tunnel), and set
4159 * this tunnel id with this decap flow.
4160 *
4161 * On restore (miss), we'll just set this saved tunnel
4162 * device.
4163 */
0a7fcb78 4164
7f8770c7
RD		 4165 NL_SET_ERR_MSG(extack, "Decap with goto isn't supported");
4166 netdev_warn(priv->netdev, "Decap with goto isn't supported");
4167 return -EOPNOTSUPP;
e88afe75
OG		 4168 }
4169
41c2fd94
CM		 4170 /* Allocate sample attribute only when there is a sample action and
4171 * no errors after parsing.
4172 */
4173 if (flow_flag_test(flow, SAMPLE)) {
bcd6740c
CM		 4174 attr->sample_attr = kzalloc(sizeof(*attr->sample_attr), GFP_KERNEL);
4175 if (!attr->sample_attr)
41c2fd94 4176 return -ENOMEM;
bcd6740c 4177 *attr->sample_attr = sample_attr;
41c2fd94
CM		 4178 }
4179
31c8eba5 4180 return 0;
03a9d11e
OG		 4181}
4182
226f2ca3 4183static void get_flags(int flags, unsigned long *flow_flags)
60bd4af8 4184{
226f2ca3 4185 unsigned long __flow_flags = 0;
60bd4af8 4186
226f2ca3
VB		 4187 if (flags & MLX5_TC_FLAG(INGRESS))
4188 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4189 if (flags & MLX5_TC_FLAG(EGRESS))
4190 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
60bd4af8 4191
226f2ca3
VB		 4192 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4193 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4194 if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4195 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
84179981
PB		 4196 if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4197 __flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
d9ee0491 4198
60bd4af8
OG		 4199 *flow_flags = __flow_flags;
4200}
4201
05866c82
OG		 4202static const struct rhashtable_params tc_ht_params = {
4203 .head_offset = offsetof(struct mlx5e_tc_flow, node),
4204 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4205 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4206 .automatic_shrinking = true,
4207};
4208
226f2ca3
VB		 4209static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4210 unsigned long flags)
05866c82 4211{
655dc3d2
OG		 4212 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4213 struct mlx5e_rep_priv *uplink_rpriv;
4214
226f2ca3 4215 if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
655dc3d2 4216 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 4217 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 4218 } else /* NIC offload */
655dc3d2 4219 return &priv->fs.tc.ht;
05866c82
OG		 4220}
4221
04de7dda
RD		 4222static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4223{
c620b772
AL		 4224 struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4225 struct mlx5_flow_attr *attr = flow->attr;
4226 bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
226f2ca3 4227 flow_flag_test(flow, INGRESS);
1418ddd9
AH		 4228 bool act_is_encap = !!(attr->action &
4229 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
c620b772 4230 bool esw_paired = mlx5_devcom_is_paired(esw_attr->in_mdev->priv.devcom,
1418ddd9
AH		 4231 MLX5_DEVCOM_ESW_OFFLOADS);
4232
10fbb1cd
RD		 4233 if (!esw_paired)
4234 return false;
4235
c620b772
AL		 4236 if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4237 mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
10fbb1cd
RD		 4238 (is_rep_ingress || act_is_encap))
4239 return true;
4240
4241 return false;
04de7dda
RD		 4242}
4243
c620b772
AL		 4244struct mlx5_flow_attr *
4245mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4246{
4247 u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB) ?
4248 sizeof(struct mlx5_esw_flow_attr) :
4249 sizeof(struct mlx5_nic_flow_attr);
4250 struct mlx5_flow_attr *attr;
4251
4252 return kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4253}
4254
a88780a9
RD		 4255static int
4256mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
226f2ca3 4257 struct flow_cls_offload *f, unsigned long flow_flags,
a88780a9
RD		 4258 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4259 struct mlx5e_tc_flow **__flow)
e3a2b7ed 4260{
17091853 4261 struct mlx5e_tc_flow_parse_attr *parse_attr;
c620b772 4262 struct mlx5_flow_attr *attr;
3bc4b7bf 4263 struct mlx5e_tc_flow *flow;
ff7ea04a
GS		 4264 int err = -ENOMEM;
4265 int out_index;
e3a2b7ed 4266
c620b772 4267 flow = kzalloc(sizeof(*flow), GFP_KERNEL);
1b9a07ee 4268 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
ff7ea04a
GS		 4269 if (!parse_attr || !flow)
4270 goto err_free;
c620b772
AL		 4271
4272 flow->flags = flow_flags;
4273 flow->cookie = f->cookie;
4274 flow->priv = priv;
4275
4276 attr = mlx5_alloc_flow_attr(get_flow_name_space(flow));
ff7ea04a 4277 if (!attr)
e3a2b7ed 4278 goto err_free;
ff7ea04a 4279
c620b772 4280 flow->attr = attr;
e3a2b7ed 4281
5a7e5bcb
VB		 4282 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4283 INIT_LIST_HEAD(&flow->encaps[out_index].list);
5a7e5bcb 4284 INIT_LIST_HEAD(&flow->hairpin);
14e6b038 4285 INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
5a7e5bcb 4286 refcount_set(&flow->refcnt, 1);
95435ad7 4287 init_completion(&flow->init_done);
e3a2b7ed 4288
a88780a9
RD		 4289 *__flow = flow;
4290 *__parse_attr = parse_attr;
4291
4292 return 0;
4293
4294err_free:
4295 kfree(flow);
4296 kvfree(parse_attr);
4297 return err;
4298}
4299
c7569097
AL		 4300static void
4301mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4302 struct mlx5e_tc_flow_parse_attr *parse_attr,
4303 struct flow_cls_offload *f)
4304{
4305 attr->parse_attr = parse_attr;
4306 attr->chain = f->common.chain_index;
4307 attr->prio = f->common.prio;
4308}
4309
988ab9c7 4310static void
c620b772 4311mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
988ab9c7
TZ		 4312 struct mlx5e_priv *priv,
4313 struct mlx5e_tc_flow_parse_attr *parse_attr,
f9e30088 4314 struct flow_cls_offload *f,
988ab9c7
TZ		 4315 struct mlx5_eswitch_rep *in_rep,
4316 struct mlx5_core_dev *in_mdev)
4317{
4318 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
c620b772 4319 struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
988ab9c7 4320
c7569097 4321 mlx5e_flow_attr_init(attr, parse_attr, f);
988ab9c7
TZ		 4322
4323 esw_attr->in_rep = in_rep;
4324 esw_attr->in_mdev = in_mdev;
4325
4326 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4327 MLX5_COUNTER_SOURCE_ESWITCH)
4328 esw_attr->counter_dev = in_mdev;
4329 else
4330 esw_attr->counter_dev = priv->mdev;
4331}
4332
71129676 4333static struct mlx5e_tc_flow *
04de7dda 4334__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4335 struct flow_cls_offload *f,
226f2ca3 4336 unsigned long flow_flags,
04de7dda
RD		 4337 struct net_device *filter_dev,
4338 struct mlx5_eswitch_rep *in_rep,
71129676 4339 struct mlx5_core_dev *in_mdev)
a88780a9 4340{
f9e30088 4341 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4342 struct netlink_ext_ack *extack = f->common.extack;
4343 struct mlx5e_tc_flow_parse_attr *parse_attr;
4344 struct mlx5e_tc_flow *flow;
4345 int attr_size, err;
e3a2b7ed 4346
226f2ca3 4347 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
a88780a9
RD		 4348 attr_size = sizeof(struct mlx5_esw_flow_attr);
4349 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4350 &parse_attr, &flow);
4351 if (err)
4352 goto out;
988ab9c7 4353
d11afc26 4354 parse_attr->filter_dev = filter_dev;
c620b772 4355 mlx5e_flow_esw_attr_init(flow->attr,
988ab9c7
TZ		 4356 priv, parse_attr,
4357 f, in_rep, in_mdev);
4358
54c177ca
OS		 4359 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4360 f, filter_dev);
d11afc26
OS		 4361 if (err)
4362 goto err_free;
a88780a9 4363
7e36feeb 4364 /* actions validation depends on parsing the ct matches first */
aedd133d 4365 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
c620b772 4366 &flow->attr->ct_attr, extack);
a88780a9
RD		 4367 if (err)
4368 goto err_free;
4369
70f8019e 4370 err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4c3844d9
PB		 4371 if (err)
4372 goto err_free;
4373
7040632d 4374 err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
95435ad7 4375 complete_all(&flow->init_done);
ef06c9ee
RD		 4376 if (err) {
4377 if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4378 goto err_free;
4379
b4a23329 4380 add_unready_flow(flow);
ef06c9ee 4381 }
e3a2b7ed 4382
71129676 4383 return flow;
a88780a9
RD		 4384
4385err_free:
5a7e5bcb 4386 mlx5e_flow_put(priv, flow);
a88780a9 4387out:
71129676 4388 return ERR_PTR(err);
a88780a9
RD		 4389}
4390
f9e30088 4391static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
95dc1902 4392 struct mlx5e_tc_flow *flow,
226f2ca3 4393 unsigned long flow_flags)
04de7dda
RD		 4394{
4395 struct mlx5e_priv *priv = flow->priv, *peer_priv;
4396 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
c620b772 4397 struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
04de7dda
RD		 4398 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
4399 struct mlx5e_tc_flow_parse_attr *parse_attr;
4400 struct mlx5e_rep_priv *peer_urpriv;
4401 struct mlx5e_tc_flow *peer_flow;
4402 struct mlx5_core_dev *in_mdev;
4403 int err = 0;
4404
4405 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4406 if (!peer_esw)
4407 return -ENODEV;
4408
4409 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4410 peer_priv = netdev_priv(peer_urpriv->netdev);
4411
4412 /* in_mdev is assigned of which the packet originated from.
4413 * So packets redirected to uplink use the same mdev of the
4414 * original flow and packets redirected from uplink use the
4415 * peer mdev.
4416 */
c620b772 4417 if (attr->in_rep->vport == MLX5_VPORT_UPLINK)
04de7dda
RD		 4418 in_mdev = peer_priv->mdev;
4419 else
4420 in_mdev = priv->mdev;
4421
c620b772 4422 parse_attr = flow->attr->parse_attr;
95dc1902 4423 peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
71129676 4424 parse_attr->filter_dev,
c620b772 4425 attr->in_rep, in_mdev);
71129676
JG		 4426 if (IS_ERR(peer_flow)) {
4427 err = PTR_ERR(peer_flow);
04de7dda 4428 goto out;
71129676 4429 }
04de7dda
RD		 4430
4431 flow->peer_flow = peer_flow;
226f2ca3 4432 flow_flag_set(flow, DUP);
04de7dda
RD		 4433 mutex_lock(&esw->offloads.peer_mutex);
4434 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
4435 mutex_unlock(&esw->offloads.peer_mutex);
4436
4437out:
4438 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4439 return err;
4440}
4441
4442static int
4443mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
f9e30088 4444 struct flow_cls_offload *f,
226f2ca3 4445 unsigned long flow_flags,
04de7dda
RD		 4446 struct net_device *filter_dev,
4447 struct mlx5e_tc_flow **__flow)
4448{
4449 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4450 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4451 struct mlx5_core_dev *in_mdev = priv->mdev;
4452 struct mlx5e_tc_flow *flow;
4453 int err;
4454
71129676
JG		 4455 flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4456 in_mdev);
4457 if (IS_ERR(flow))
4458 return PTR_ERR(flow);
04de7dda
RD		 4459
4460 if (is_peer_flow_needed(flow)) {
95dc1902 4461 err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags);
04de7dda
RD		 4462 if (err) {
4463 mlx5e_tc_del_fdb_flow(priv, flow);
4464 goto out;
4465 }
4466 }
4467
4468 *__flow = flow;
4469
4470 return 0;
4471
4472out:
4473 return err;
4474}
4475
a88780a9
RD		 4476static int
4477mlx5e_add_nic_flow(struct mlx5e_priv *priv,
f9e30088 4478 struct flow_cls_offload *f,
226f2ca3 4479 unsigned long flow_flags,
d11afc26 4480 struct net_device *filter_dev,
a88780a9
RD		 4481 struct mlx5e_tc_flow **__flow)
4482{
f9e30088 4483 struct flow_rule *rule = flow_cls_offload_flow_rule(f);
a88780a9
RD		 4484 struct netlink_ext_ack *extack = f->common.extack;
4485 struct mlx5e_tc_flow_parse_attr *parse_attr;
4486 struct mlx5e_tc_flow *flow;
4487 int attr_size, err;
4488
c7569097
AL		 4489 if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4490 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4491 return -EOPNOTSUPP;
4492 } else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
bf07aa73 4493 return -EOPNOTSUPP;
c7569097 4494 }
bf07aa73 4495
226f2ca3 4496 flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
a88780a9
RD		 4497 attr_size = sizeof(struct mlx5_nic_flow_attr);
4498 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4499 &parse_attr, &flow);
4500 if (err)
4501 goto out;
4502
d11afc26 4503 parse_attr->filter_dev = filter_dev;
c7569097
AL		 4504 mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4505
54c177ca
OS		 4506 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4507 f, filter_dev);
d11afc26
OS		 4508 if (err)
4509 goto err_free;
4510
aedd133d
AL		 4511 err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4512 &flow->attr->ct_attr, extack);
4513 if (err)
4514 goto err_free;
4515
c6cfe113 4516 err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
a88780a9
RD		 4517 if (err)
4518 goto err_free;
4519
c6cfe113 4520 err = mlx5e_tc_add_nic_flow(priv, flow, extack);
a88780a9
RD		 4521 if (err)
4522 goto err_free;
4523
226f2ca3 4524 flow_flag_set(flow, OFFLOADED);
a88780a9
RD		 4525 *__flow = flow;
4526
4527 return 0;
e3a2b7ed 4528
e3a2b7ed 4529err_free:
8914add2 4530 flow_flag_set(flow, FAILED);
e68e28b4 4531 dealloc_mod_hdr_actions(&parse_attr->mod_hdr_acts);
5a7e5bcb 4532 mlx5e_flow_put(priv, flow);
a88780a9
RD		 4533out:
4534 return err;
4535}
4536
4537static int
4538mlx5e_tc_add_flow(struct mlx5e_priv *priv,
f9e30088 4539 struct flow_cls_offload *f,
226f2ca3 4540 unsigned long flags,
d11afc26 4541 struct net_device *filter_dev,
a88780a9
RD		 4542 struct mlx5e_tc_flow **flow)
4543{
4544 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
226f2ca3 4545 unsigned long flow_flags;
a88780a9
RD		 4546 int err;
4547
4548 get_flags(flags, &flow_flags);
4549
bf07aa73
PB		 4550 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4551 return -EOPNOTSUPP;
4552
f6455de0 4553 if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
d11afc26
OS		 4554 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4555 filter_dev, flow);
a88780a9 4556 else
d11afc26
OS		 4557 err = mlx5e_add_nic_flow(priv, f, flow_flags,
4558 filter_dev, flow);
a88780a9
RD		 4559
4560 return err;
4561}
4562
553f9328
VP		 4563static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4564 struct mlx5e_rep_priv *rpriv)
4565{
4566 /* Offloaded flow rule is allowed to duplicate on non-uplink representor
2fb15e72
VB		 4567 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4568 * function is called from NIC mode.
553f9328 4569 */
2fb15e72 4570 return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
553f9328
VP		 4571}
4572
71d82d2a 4573int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4574 struct flow_cls_offload *f, unsigned long flags)
a88780a9
RD		 4575{
4576 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 4577 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
553f9328 4578 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a88780a9
RD		 4579 struct mlx5e_tc_flow *flow;
4580 int err = 0;
4581
7dc84de9
RD		 4582 if (!mlx5_esw_hold(priv->mdev))
4583 return -EAGAIN;
4584
4585 mlx5_esw_get(priv->mdev);
4586
c5d326b2
VB		 4587 rcu_read_lock();
4588 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
a88780a9 4589 if (flow) {
553f9328
VP		 4590 /* Same flow rule offloaded to non-uplink representor sharing tc block,
4591 * just return 0.
4592 */
4593 if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
c1aea9e1 4594 goto rcu_unlock;
553f9328 4595
a88780a9
RD		 4596 NL_SET_ERR_MSG_MOD(extack,
4597 "flow cookie already exists, ignoring");
4598 netdev_warn_once(priv->netdev,
4599 "flow cookie %lx already exists, ignoring\n",
4600 f->cookie);
0e1c1a2f 4601 err = -EEXIST;
c1aea9e1 4602 goto rcu_unlock;
a88780a9 4603 }
c1aea9e1
VB		 4604rcu_unlock:
4605 rcu_read_unlock();
4606 if (flow)
4607 goto out;
a88780a9 4608
7a978759 4609 trace_mlx5e_configure_flower(f);
d11afc26 4610 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 4611 if (err)
4612 goto out;
4613
553f9328
VP		 4614 /* Flow rule offloaded to non-uplink representor sharing tc block,
4615 * set the flow's owner dev.
4616 */
4617 if (is_flow_rule_duplicate_allowed(dev, rpriv))
4618 flow->orig_dev = dev;
4619
c5d326b2 4620 err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
a88780a9
RD		 4621 if (err)
4622 goto err_free;
4623
7dc84de9 4624 mlx5_esw_release(priv->mdev);
a88780a9
RD		 4625 return 0;
4626
4627err_free:
5a7e5bcb 4628 mlx5e_flow_put(priv, flow);
a88780a9 4629out:
7dc84de9
RD		 4630 mlx5_esw_put(priv->mdev);
4631 mlx5_esw_release(priv->mdev);
e3a2b7ed
AV		 4632 return err;
4633}
4634
8f8ae895
OG		 4635static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4636{
226f2ca3
VB		 4637 bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4638 bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
8f8ae895 4639
226f2ca3
VB		 4640 return flow_flag_test(flow, INGRESS) == dir_ingress &&
4641 flow_flag_test(flow, EGRESS) == dir_egress;
8f8ae895
OG		 4642}
4643
71d82d2a 4644int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4645 struct flow_cls_offload *f, unsigned long flags)
e3a2b7ed 4646{
d9ee0491 4647 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 4648 struct mlx5e_tc_flow *flow;
c5d326b2 4649 int err;
e3a2b7ed 4650
c5d326b2 4651 rcu_read_lock();
ab818362 4652 flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
c5d326b2
VB		 4653 if (!flow || !same_flow_direction(flow, flags)) {
4654 err = -EINVAL;
4655 goto errout;
4656 }
e3a2b7ed 4657
c5d326b2
VB		 4658 /* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4659 * set.
4660 */
4661 if (flow_flag_test_and_set(flow, DELETED)) {
4662 err = -EINVAL;
4663 goto errout;
4664 }
05866c82 4665 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
c5d326b2 4666 rcu_read_unlock();
e3a2b7ed 4667
7a978759 4668 trace_mlx5e_delete_flower(f);
5a7e5bcb 4669 mlx5e_flow_put(priv, flow);
e3a2b7ed 4670
7dc84de9 4671 mlx5_esw_put(priv->mdev);
e3a2b7ed 4672 return 0;
c5d326b2
VB		 4673
4674errout:
4675 rcu_read_unlock();
4676 return err;
e3a2b7ed
AV		 4677}
4678
71d82d2a 4679int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
226f2ca3 4680 struct flow_cls_offload *f, unsigned long flags)
aad7e08d 4681{
04de7dda 4682 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 4683 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 4684 struct mlx5_eswitch *peer_esw;
aad7e08d 4685 struct mlx5e_tc_flow *flow;
aad7e08d 4686 struct mlx5_fc *counter;
316d5f72
RD		 4687 u64 lastuse = 0;
4688 u64 packets = 0;
4689 u64 bytes = 0;
5a7e5bcb 4690 int err = 0;
aad7e08d 4691
c5d326b2
VB		 4692 rcu_read_lock();
4693 flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4694 tc_ht_params));
4695 rcu_read_unlock();
5a7e5bcb
VB		 4696 if (IS_ERR(flow))
4697 return PTR_ERR(flow);
4698
4699 if (!same_flow_direction(flow, flags)) {
4700 err = -EINVAL;
4701 goto errout;
4702 }
aad7e08d 4703
4c3844d9 4704 if (mlx5e_is_offloaded_flow(flow) || flow_flag_test(flow, CT)) {
316d5f72
RD		 4705 counter = mlx5e_tc_get_counter(flow);
4706 if (!counter)
5a7e5bcb 4707 goto errout;
aad7e08d 4708
316d5f72
RD		 4709 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4710 }
aad7e08d 4711
316d5f72
RD		 4712 /* Under multipath it's possible for one rule to be currently
4713 * un-offloaded while the other rule is offloaded.
4714 */
04de7dda
RD		 4715 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
4716 if (!peer_esw)
4717 goto out;
4718
226f2ca3
VB		 4719 if (flow_flag_test(flow, DUP) &&
4720 flow_flag_test(flow->peer_flow, OFFLOADED)) {
04de7dda
RD		 4721 u64 bytes2;
4722 u64 packets2;
4723 u64 lastuse2;
4724
4725 counter = mlx5e_tc_get_counter(flow->peer_flow);
316d5f72
RD		 4726 if (!counter)
4727 goto no_peer_counter;
04de7dda
RD		 4728 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
4729
4730 bytes += bytes2;
4731 packets += packets2;
4732 lastuse = max_t(u64, lastuse, lastuse2);
4733 }
4734
316d5f72 4735no_peer_counter:
04de7dda 4736 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
04de7dda 4737out:
4b61d3e8 4738 flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
93a129eb 4739 FLOW_ACTION_HW_STATS_DELAYED);
7a978759 4740 trace_mlx5e_stats_flower(f);
5a7e5bcb
VB		 4741errout:
4742 mlx5e_flow_put(priv, flow);
4743 return err;
aad7e08d
AV		 4744}
4745
1fe3e316 4746static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
fcb64c0f
EC		 4747 struct netlink_ext_ack *extack)
4748{
4749 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4750 struct mlx5_eswitch *esw;
1fe3e316 4751 u32 rate_mbps = 0;
fcb64c0f 4752 u16 vport_num;
fcb64c0f
EC		 4753 int err;
4754
e401a184
EC		 4755 vport_num = rpriv->rep->vport;
4756 if (vport_num >= MLX5_VPORT_ECPF) {
4757 NL_SET_ERR_MSG_MOD(extack,
4758 "Ingress rate limit is supported only for Eswitch ports connected to VFs");
4759 return -EOPNOTSUPP;
4760 }
4761
fcb64c0f
EC		 4762 esw = priv->mdev->priv.eswitch;
4763 /* rate is given in bytes/sec.
4764 * First convert to bits/sec and then round to the nearest mbit/secs.
4765 * mbit means million bits.
4766 * Moreover, if rate is non zero we choose to configure to a minimum of
4767 * 1 mbit/sec.
4768 */
1fe3e316
PP		 4769 if (rate) {
4770 rate = (rate * BITS_PER_BYTE) + 500000;
8b90d897
PP		 4771 do_div(rate, 1000000);
4772 rate_mbps = max_t(u32, rate, 1);
1fe3e316
PP		 4773 }
4774
2d116e3e 4775 err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
fcb64c0f
EC		 4776 if (err)
4777 NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
4778
4779 return err;
4780}
4781
4782static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
4783 struct flow_action *flow_action,
4784 struct netlink_ext_ack *extack)
4785{
4786 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4787 const struct flow_action_entry *act;
4788 int err;
4789 int i;
4790
4791 if (!flow_action_has_entries(flow_action)) {
4792 NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
4793 return -EINVAL;
4794 }
4795
4796 if (!flow_offload_has_one_action(flow_action)) {
4797 NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
4798 return -EOPNOTSUPP;
4799 }
4800
0885ae1a
A		 4801 if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
4802 NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
319a1d19 4803 return -EOPNOTSUPP;
0885ae1a 4804 }
319a1d19 4805
fcb64c0f
EC		 4806 flow_action_for_each(i, act, flow_action) {
4807 switch (act->id) {
4808 case FLOW_ACTION_POLICE:
6a56e199
BZ		 4809 if (act->police.rate_pkt_ps) {
4810 NL_SET_ERR_MSG_MOD(extack, "QoS offload not support packets per second");
4811 return -EOPNOTSUPP;
4812 }
fcb64c0f
EC		 4813 err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
4814 if (err)
4815 return err;
4816
4817 rpriv->prev_vf_vport_stats = priv->stats.vf_vport;
4818 break;
4819 default:
4820 NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
4821 return -EOPNOTSUPP;
4822 }
4823 }
4824
4825 return 0;
4826}
4827
4828int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
4829 struct tc_cls_matchall_offload *ma)
4830{
b5f814cc 4831 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
fcb64c0f 4832 struct netlink_ext_ack *extack = ma->common.extack;
fcb64c0f 4833
b5f814cc
EC		 4834 if (!mlx5_esw_qos_enabled(esw)) {
4835 NL_SET_ERR_MSG_MOD(extack, "QoS is not supported on this device");
4836 return -EOPNOTSUPP;
4837 }
4838
7b83355f 4839 if (ma->common.prio != 1) {
fcb64c0f
EC		 4840 NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
4841 return -EINVAL;
4842 }
4843
4844 return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
4845}
4846
4847int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
4848 struct tc_cls_matchall_offload *ma)
4849{
4850 struct netlink_ext_ack *extack = ma->common.extack;
4851
4852 return apply_police_params(priv, 0, extack);
4853}
4854
4855void mlx5e_tc_stats_matchall(struct mlx5e_priv *priv,
4856 struct tc_cls_matchall_offload *ma)
4857{
4858 struct mlx5e_rep_priv *rpriv = priv->ppriv;
4859 struct rtnl_link_stats64 cur_stats;
4860 u64 dbytes;
4861 u64 dpkts;
4862
4863 cur_stats = priv->stats.vf_vport;
4864 dpkts = cur_stats.rx_packets - rpriv->prev_vf_vport_stats.rx_packets;
4865 dbytes = cur_stats.rx_bytes - rpriv->prev_vf_vport_stats.rx_bytes;
4866 rpriv->prev_vf_vport_stats = cur_stats;
4b61d3e8 4867 flow_stats_update(&ma->stats, dbytes, dpkts, 0, jiffies,
93a129eb 4868 FLOW_ACTION_HW_STATS_DELAYED);
fcb64c0f
EC		 4869}
4870
4d8fcf21
AH		 4871static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
4872 struct mlx5e_priv *peer_priv)
4873{
4874 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
db76ca24
VB		 4875 struct mlx5e_hairpin_entry *hpe, *tmp;
4876 LIST_HEAD(init_wait_list);
4d8fcf21
AH		 4877 u16 peer_vhca_id;
4878 int bkt;
4879
4880 if (!same_hw_devs(priv, peer_priv))
4881 return;
4882
4883 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
4884
b32accda 4885 mutex_lock(&priv->fs.tc.hairpin_tbl_lock);
db76ca24
VB		 4886 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist)
4887 if (refcount_inc_not_zero(&hpe->refcnt))
4888 list_add(&hpe->dead_peer_wait_list, &init_wait_list);
4889 mutex_unlock(&priv->fs.tc.hairpin_tbl_lock);
4890
4891 list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
4892 wait_for_completion(&hpe->res_ready);
4893 if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
a3e5fd93 4894 mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
db76ca24
VB		 4895
4896 mlx5e_hairpin_put(priv, hpe);
4d8fcf21
AH		 4897 }
4898}
4899
4900static int mlx5e_tc_netdev_event(struct notifier_block *this,
4901 unsigned long event, void *ptr)
4902{
4903 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
4904 struct mlx5e_flow_steering *fs;
4905 struct mlx5e_priv *peer_priv;
4906 struct mlx5e_tc_table *tc;
4907 struct mlx5e_priv *priv;
4908
4909 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
4910 event != NETDEV_UNREGISTER ||
4911 ndev->reg_state == NETREG_REGISTERED)
4912 return NOTIFY_DONE;
4913
4914 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
4915 fs = container_of(tc, struct mlx5e_flow_steering, tc);
4916 priv = container_of(fs, struct mlx5e_priv, fs);
4917 peer_priv = netdev_priv(ndev);
4918 if (priv == peer_priv ||
4919 !(priv->netdev->features & NETIF_F_HW_TC))
4920 return NOTIFY_DONE;
4921
4922 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
4923
4924 return NOTIFY_DONE;
4925}
4926
6a064674
AL		 4927static int mlx5e_tc_nic_get_ft_size(struct mlx5_core_dev *dev)
4928{
4929 int tc_grp_size, tc_tbl_size;
4930 u32 max_flow_counter;
4931
4932 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
4933 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
4934
4935 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
4936
4937 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
4938 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
4939
4940 return tc_tbl_size;
4941}
4942
655dc3d2 4943int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 4944{
acff797c 4945 struct mlx5e_tc_table *tc = &priv->fs.tc;
6a064674 4946 struct mlx5_core_dev *dev = priv->mdev;
c9355682 4947 struct mapping_ctx *chains_mapping;
6a064674 4948 struct mlx5_chains_attr attr = {};
2198b932 4949 u64 mapping_id;
4d8fcf21 4950 int err;
e8f887ac 4951
b2fdf3d0 4952 mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
b6fac0b4 4953 mutex_init(&tc->t_lock);
b32accda 4954 mutex_init(&tc->hairpin_tbl_lock);
5c65c564 4955 hash_init(tc->hairpin_tbl);
11c9c548 4956
4d8fcf21
AH		 4957 err = rhashtable_init(&tc->ht, &tc_ht_params);
4958 if (err)
4959 return err;
4960
9ba33339
RD		 4961 lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
4962
2198b932
RD		 4963 mapping_id = mlx5_query_nic_system_image_guid(dev);
4964
4965 chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
4966 sizeof(struct mlx5_mapped_obj),
4967 MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
4968
c9355682
CM		 4969 if (IS_ERR(chains_mapping)) {
4970 err = PTR_ERR(chains_mapping);
4971 goto err_mapping;
4972 }
4973 tc->mapping = chains_mapping;
4974
4975 if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
c7569097
AL		 4976 attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
4977 MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
6a064674
AL		 4978 attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
4979 attr.max_ft_sz = mlx5e_tc_nic_get_ft_size(dev);
4980 attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
6783f0a2 4981 attr.default_ft = mlx5e_vlan_get_flowtable(priv->fs.vlan);
c9355682 4982 attr.mapping = chains_mapping;
6a064674
AL		 4983
4984 tc->chains = mlx5_chains_create(dev, &attr);
4985 if (IS_ERR(tc->chains)) {
4986 err = PTR_ERR(tc->chains);
4987 goto err_chains;
4988 }
4989
f0da4daa 4990 tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
aedd133d 4991 tc->ct = mlx5_tc_ct_init(priv, tc->chains, &priv->fs.tc.mod_hdr,
f0da4daa 4992 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
aedd133d 4993
4d8fcf21 4994 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
d48834f9
JP		 4995 err = register_netdevice_notifier_dev_net(priv->netdev,
4996 &tc->netdevice_nb,
4997 &tc->netdevice_nn);
4998 if (err) {
4d8fcf21
AH		 4999 tc->netdevice_nb.notifier_call = NULL;
5000 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
6a064674 5001 goto err_reg;
4d8fcf21
AH		 5002 }
5003
6a064674
AL		 5004 return 0;
5005
5006err_reg:
aedd133d 5007 mlx5_tc_ct_clean(tc->ct);
f0da4daa 5008 mlx5e_tc_post_act_destroy(tc->post_act);
6a064674
AL		 5009 mlx5_chains_destroy(tc->chains);
5010err_chains:
c9355682
CM		 5011 mapping_destroy(chains_mapping);
5012err_mapping:
6a064674 5013 rhashtable_destroy(&tc->ht);
4d8fcf21 5014 return err;
e8f887ac
AV		 5015}
5016
5017static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5018{
5019 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 5020 struct mlx5e_priv *priv = flow->priv;
e8f887ac 5021
961e8979 5022 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 5023 kfree(flow);
5024}
5025
655dc3d2 5026void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 5027{
acff797c 5028 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 5029
4d8fcf21 5030 if (tc->netdevice_nb.notifier_call)
d48834f9
JP		 5031 unregister_netdevice_notifier_dev_net(priv->netdev,
5032 &tc->netdevice_nb,
5033 &tc->netdevice_nn);
4d8fcf21 5034
b2fdf3d0 5035 mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
b32accda
VB		 5036 mutex_destroy(&tc->hairpin_tbl_lock);
5037
6a064674 5038 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 5039
acff797c 5040 if (!IS_ERR_OR_NULL(tc->t)) {
6a064674 5041 mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
acff797c 5042 tc->t = NULL;
e8f887ac 5043 }
b6fac0b4 5044 mutex_destroy(&tc->t_lock);
6a064674 5045
aedd133d 5046 mlx5_tc_ct_clean(tc->ct);
f0da4daa 5047 mlx5e_tc_post_act_destroy(tc->post_act);
c9355682 5048 mapping_destroy(tc->mapping);
6a064674 5049 mlx5_chains_destroy(tc->chains);
e8f887ac 5050}
655dc3d2
OG		 5051
5052int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
5053{
d7a42ad0 5054 const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
0a7fcb78 5055 struct mlx5_rep_uplink_priv *uplink_priv;
aedd133d 5056 struct mlx5e_rep_priv *rpriv;
0a7fcb78 5057 struct mapping_ctx *mapping;
aedd133d
AL		 5058 struct mlx5_eswitch *esw;
5059 struct mlx5e_priv *priv;
2198b932 5060 u64 mapping_id;
aedd133d 5061 int err = 0;
0a7fcb78
PB		 5062
5063 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d
AL		 5064 rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5065 priv = netdev_priv(rpriv->netdev);
5066 esw = priv->mdev->priv.eswitch;
0a7fcb78 5067
f0da4daa
CM		 5068 uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5069 MLX5_FLOW_NAMESPACE_FDB);
aedd133d
AL		 5070 uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5071 esw_chains(esw),
5072 &esw->offloads.mod_hdr,
f0da4daa
CM		 5073 MLX5_FLOW_NAMESPACE_FDB,
5074 uplink_priv->post_act);
4c3844d9 5075
2741f223 5076 uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
2a9ab10a 5077
2198b932
RD		 5078 mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5079
5080 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5081 sizeof(struct tunnel_match_key),
5082 TUNNEL_INFO_BITS_MASK, true);
5083
0a7fcb78
PB		 5084 if (IS_ERR(mapping)) {
5085 err = PTR_ERR(mapping);
5086 goto err_tun_mapping;
5087 }
5088 uplink_priv->tunnel_mapping = mapping;
5089
3222efd4
VB		 5090 /* Two last values are reserved for stack devices slow path table mark
5091 * and bridge ingress push mark.
5092 */
2198b932 5093 mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
3222efd4 5094 sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
0a7fcb78
PB		 5095 if (IS_ERR(mapping)) {
5096 err = PTR_ERR(mapping);
5097 goto err_enc_opts_mapping;
5098 }
5099 uplink_priv->tunnel_enc_opts_mapping = mapping;
5100
5101 err = rhashtable_init(tc_ht, &tc_ht_params);
5102 if (err)
5103 goto err_ht_init;
5104
9ba33339
RD		 5105 lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5106
8914add2 5107 uplink_priv->encap = mlx5e_tc_tun_init(priv);
2b6c3c1e
WY		 5108 if (IS_ERR(uplink_priv->encap)) {
5109 err = PTR_ERR(uplink_priv->encap);
8914add2 5110 goto err_register_fib_notifier;
2b6c3c1e 5111 }
8914add2 5112
2b6c3c1e 5113 return 0;
0a7fcb78 5114
8914add2
VB		 5115err_register_fib_notifier:
5116 rhashtable_destroy(tc_ht);
0a7fcb78
PB		 5117err_ht_init:
5118 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5119err_enc_opts_mapping:
5120 mapping_destroy(uplink_priv->tunnel_mapping);
5121err_tun_mapping:
0027d70c 5122 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5123 mlx5_tc_ct_clean(uplink_priv->ct_priv);
0a7fcb78
PB		 5124 netdev_warn(priv->netdev,
5125 "Failed to initialize tc (eswitch), err: %d", err);
f0da4daa 5126 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
0a7fcb78 5127 return err;
655dc3d2
OG		 5128}
5129
5130void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
5131{
0a7fcb78
PB		 5132 struct mlx5_rep_uplink_priv *uplink_priv;
5133
0a7fcb78 5134 uplink_priv = container_of(tc_ht, struct mlx5_rep_uplink_priv, tc_ht);
aedd133d 5135
8914add2
VB		 5136 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5137 mlx5e_tc_tun_cleanup(uplink_priv->encap);
5138
0a7fcb78
PB		 5139 mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5140 mapping_destroy(uplink_priv->tunnel_mapping);
4c3844d9 5141
0027d70c 5142 mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
aedd133d 5143 mlx5_tc_ct_clean(uplink_priv->ct_priv);
f0da4daa 5144 mlx5e_tc_post_act_destroy(uplink_priv->post_act);
655dc3d2 5145}
01252a27 5146
226f2ca3 5147int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
01252a27 5148{
d9ee0491 5149 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 5150
5151 return atomic_read(&tc_ht->nelems);
5152}
04de7dda
RD		 5153
5154void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5155{
5156 struct mlx5e_tc_flow *flow, *tmp;
5157
5158 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
5159 __mlx5e_tc_del_fdb_peer_flow(flow);
5160}
b4a23329
RD		 5161
5162void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5163{
5164 struct mlx5_rep_uplink_priv *rpriv =
5165 container_of(work, struct mlx5_rep_uplink_priv,
5166 reoffload_flows_work);
5167 struct mlx5e_tc_flow *flow, *tmp;
5168
ad86755b 5169 mutex_lock(&rpriv->unready_flows_lock);
b4a23329
RD		 5170 list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5171 if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
ad86755b 5172 unready_flow_del(flow);
b4a23329 5173 }
ad86755b 5174 mutex_unlock(&rpriv->unready_flows_lock);
b4a23329 5175}
e2394a61
VB		 5176
5177static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5178 struct flow_cls_offload *cls_flower,
5179 unsigned long flags)
5180{
5181 switch (cls_flower->command) {
5182 case FLOW_CLS_REPLACE:
5183 return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5184 flags);
5185 case FLOW_CLS_DESTROY:
5186 return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5187 flags);
5188 case FLOW_CLS_STATS:
5189 return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5190 flags);
5191 default:
5192 return -EOPNOTSUPP;
5193 }
5194}
5195
5196int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5197 void *cb_priv)
5198{
ec9457a6 5199 unsigned long flags = MLX5_TC_FLAG(INGRESS);
e2394a61
VB		 5200 struct mlx5e_priv *priv = cb_priv;
5201
2ff349c5
RD		 5202 if (!priv->netdev || !netif_device_present(priv->netdev))
5203 return -EOPNOTSUPP;
5204
ec9457a6
RD		 5205 if (mlx5e_is_uplink_rep(priv))
5206 flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5207 else
5208 flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5209
e2394a61
VB		 5210 switch (type) {
5211 case TC_SETUP_CLSFLOWER:
5212 return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5213 default:
5214 return -EOPNOTSUPP;
5215 }
5216}
c7569097
AL		 5217
5218bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe,
5219 struct sk_buff *skb)
5220{
5221#if IS_ENABLED(CONFIG_NET_TC_SKB_EXT)
aedd133d 5222 u32 chain = 0, chain_tag, reg_b, zone_restore_id;
c7569097 5223 struct mlx5e_priv *priv = netdev_priv(skb->dev);
aedd133d 5224 struct mlx5e_tc_table *tc = &priv->fs.tc;
a91d98a0 5225 struct mlx5_mapped_obj mapped_obj;
c7569097
AL		 5226 struct tc_skb_ext *tc_skb_ext;
5227 int err;
5228
5229 reg_b = be32_to_cpu(cqe->ft_metadata);
5230
5231 chain_tag = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5232
c9355682 5233 err = mapping_find(tc->mapping, chain_tag, &mapped_obj);
c7569097
AL		 5234 if (err) {
5235 netdev_dbg(priv->netdev,
5236 "Couldn't find chain for chain tag: %d, err: %d\n",
5237 chain_tag, err);
5238 return false;
5239 }
5240
a91d98a0
CM		 5241 if (mapped_obj.type == MLX5_MAPPED_OBJ_CHAIN) {
5242 chain = mapped_obj.chain;
9453d45e 5243 tc_skb_ext = tc_skb_ext_alloc(skb);
c7569097
AL		 5244 if (WARN_ON(!tc_skb_ext))
5245 return false;
5246
5247 tc_skb_ext->chain = chain;
aedd133d 5248
ed2fe7ba 5249 zone_restore_id = (reg_b >> REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
48d216e5 5250 ESW_ZONE_ID_MASK;
aedd133d
AL		 5251
5252 if (!mlx5e_tc_ct_restore_flow(tc->ct, skb,
5253 zone_restore_id))
5254 return false;
a91d98a0
CM		 5255 } else {
5256 netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5257 return false;
c7569097
AL		 5258 }
5259#endif /* CONFIG_NET_TC_SKB_EXT */
5260
5261 return true;
5262}
Linux 6.x block layer and io_uring tree(s)