projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'drm-fixes-for-v4.14-rc4' of git://people.freedesktop.org/~airlied/linux
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_stats.h
CommitLineData
9218b44d
GP		 1/*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32#ifndef __MLX5_EN_STATS_H__
33#define __MLX5_EN_STATS_H__
34
35#define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \
36 (*(u64 *)((char *)ptr + dsc[i].offset))
37#define MLX5E_READ_CTR64_BE(ptr, dsc, i) \
38 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
39#define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \
40 (*(u32 *)((char *)ptr + dsc[i].offset))
41#define MLX5E_READ_CTR32_BE(ptr, dsc, i) \
0f7f3481 42 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
9218b44d
GP		 43
44#define MLX5E_DECLARE_STAT(type, fld) #fld, offsetof(type, fld)
bfe6d8d1
GP		 45#define MLX5E_DECLARE_RX_STAT(type, fld) "rx%d_"#fld, offsetof(type, fld)
46#define MLX5E_DECLARE_TX_STAT(type, fld) "tx%d_"#fld, offsetof(type, fld)
9218b44d
GP		 47
48struct counter_desc {
bfe6d8d1 49 char format[ETH_GSTRING_LEN];
9da5106c 50 size_t offset; /* Byte offset */
9218b44d
GP		 51};
52
53struct mlx5e_sw_stats {
54 u64 rx_packets;
55 u64 rx_bytes;
56 u64 tx_packets;
57 u64 tx_bytes;
bfe6d8d1
GP		 58 u64 tx_tso_packets;
59 u64 tx_tso_bytes;
60 u64 tx_tso_inner_packets;
61 u64 tx_tso_inner_bytes;
62 u64 rx_lro_packets;
63 u64 rx_lro_bytes;
64 u64 rx_csum_unnecessary;
9218b44d 65 u64 rx_csum_none;
bfe6d8d1
GP		 66 u64 rx_csum_complete;
67 u64 rx_csum_unnecessary_inner;
86994156 68 u64 rx_xdp_drop;
b5503b99
SM		 69 u64 rx_xdp_tx;
70 u64 rx_xdp_tx_full;
603e1f5b 71 u64 tx_csum_none;
bfe6d8d1
GP		 72 u64 tx_csum_partial;
73 u64 tx_csum_partial_inner;
9218b44d
GP		 74 u64 tx_queue_stopped;
75 u64 tx_queue_wake;
76 u64 tx_queue_dropped;
c8cf78fe 77 u64 tx_xmit_more;
9218b44d
GP		 78 u64 rx_wqe_err;
79 u64 rx_mpwqe_filler;
9218b44d 80 u64 rx_buff_alloc_err;
7219ab34
TT		 81 u64 rx_cqe_compress_blks;
82 u64 rx_cqe_compress_pkts;
accd5883 83 u64 rx_page_reuse;
4415a031
TT		 84 u64 rx_cache_reuse;
85 u64 rx_cache_full;
86 u64 rx_cache_empty;
87 u64 rx_cache_busy;
70871f1e 88 u64 rx_cache_waive;
121fcdc8
GP		 89
90 /* Special handling counters */
bfe6d8d1 91 u64 link_down_events_phy;
9218b44d
GP		 92};
93
94static const struct counter_desc sw_stats_desc[] = {
95 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_packets) },
96 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_bytes) },
97 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_packets) },
98 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_bytes) },
bfe6d8d1
GP		 99 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_packets) },
100 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_bytes) },
101 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_packets) },
102 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_tso_inner_bytes) },
103 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_packets) },
104 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_lro_bytes) },
105 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary) },
9218b44d 106 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_none) },
bfe6d8d1
GP		 107 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_complete) },
108 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_csum_unnecessary_inner) },
86994156 109 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_drop) },
b5503b99
SM		 110 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx) },
111 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_xdp_tx_full) },
603e1f5b 112 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_none) },
bfe6d8d1
GP		 113 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial) },
114 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_csum_partial_inner) },
9218b44d
GP		 115 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_stopped) },
116 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_wake) },
117 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_queue_dropped) },
c8cf78fe 118 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, tx_xmit_more) },
9218b44d
GP		 119 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_wqe_err) },
120 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_mpwqe_filler) },
9218b44d 121 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_buff_alloc_err) },
7219ab34
TT		 122 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_blks) },
123 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cqe_compress_pkts) },
accd5883 124 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_page_reuse) },
4415a031
TT		 125 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_reuse) },
126 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_full) },
127 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_empty) },
128 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_busy) },
70871f1e 129 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, rx_cache_waive) },
bfe6d8d1 130 { MLX5E_DECLARE_STAT(struct mlx5e_sw_stats, link_down_events_phy) },
9218b44d
GP		 131};
132
133struct mlx5e_qcounter_stats {
134 u32 rx_out_of_buffer;
135};
136
137static const struct counter_desc q_stats_desc[] = {
138 { MLX5E_DECLARE_STAT(struct mlx5e_qcounter_stats, rx_out_of_buffer) },
139};
140
141#define VPORT_COUNTER_OFF(c) MLX5_BYTE_OFF(query_vport_counter_out, c)
142#define VPORT_COUNTER_GET(vstats, c) MLX5_GET64(query_vport_counter_out, \
143 vstats->query_vport_out, c)
144
145struct mlx5e_vport_stats {
146 __be64 query_vport_out[MLX5_ST_SZ_QW(query_vport_counter_out)];
147};
148
149static const struct counter_desc vport_stats_desc[] = {
8075cb72 150 { "rx_vport_unicast_packets",
9218b44d 151 VPORT_COUNTER_OFF(received_eth_unicast.packets) },
8075cb72
GP		 152 { "rx_vport_unicast_bytes",
153 VPORT_COUNTER_OFF(received_eth_unicast.octets) },
154 { "tx_vport_unicast_packets",
9218b44d 155 VPORT_COUNTER_OFF(transmitted_eth_unicast.packets) },
8075cb72 156 { "tx_vport_unicast_bytes",
9218b44d 157 VPORT_COUNTER_OFF(transmitted_eth_unicast.octets) },
8075cb72 158 { "rx_vport_multicast_packets",
9218b44d 159 VPORT_COUNTER_OFF(received_eth_multicast.packets) },
8075cb72 160 { "rx_vport_multicast_bytes",
9218b44d 161 VPORT_COUNTER_OFF(received_eth_multicast.octets) },
8075cb72 162 { "tx_vport_multicast_packets",
9218b44d 163 VPORT_COUNTER_OFF(transmitted_eth_multicast.packets) },
8075cb72 164 { "tx_vport_multicast_bytes",
9218b44d 165 VPORT_COUNTER_OFF(transmitted_eth_multicast.octets) },
8075cb72 166 { "rx_vport_broadcast_packets",
9218b44d 167 VPORT_COUNTER_OFF(received_eth_broadcast.packets) },
8075cb72 168 { "rx_vport_broadcast_bytes",
9218b44d 169 VPORT_COUNTER_OFF(received_eth_broadcast.octets) },
8075cb72 170 { "tx_vport_broadcast_packets",
9218b44d 171 VPORT_COUNTER_OFF(transmitted_eth_broadcast.packets) },
8075cb72 172 { "tx_vport_broadcast_bytes",
9218b44d 173 VPORT_COUNTER_OFF(transmitted_eth_broadcast.octets) },
fe6b9bd9
GP		 174 { "rx_vport_rdma_unicast_packets",
175 VPORT_COUNTER_OFF(received_ib_unicast.packets) },
176 { "rx_vport_rdma_unicast_bytes",
177 VPORT_COUNTER_OFF(received_ib_unicast.octets) },
178 { "tx_vport_rdma_unicast_packets",
179 VPORT_COUNTER_OFF(transmitted_ib_unicast.packets) },
180 { "tx_vport_rdma_unicast_bytes",
181 VPORT_COUNTER_OFF(transmitted_ib_unicast.octets) },
182 { "rx_vport_rdma_multicast_packets",
183 VPORT_COUNTER_OFF(received_ib_multicast.packets) },
184 { "rx_vport_rdma_multicast_bytes",
185 VPORT_COUNTER_OFF(received_ib_multicast.octets) },
186 { "tx_vport_rdma_multicast_packets",
187 VPORT_COUNTER_OFF(transmitted_ib_multicast.packets) },
188 { "tx_vport_rdma_multicast_bytes",
189 VPORT_COUNTER_OFF(transmitted_ib_multicast.octets) },
9218b44d
GP		 190};
191
192#define PPORT_802_3_OFF(c) \
193 MLX5_BYTE_OFF(ppcnt_reg, \
194 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
195#define PPORT_802_3_GET(pstats, c) \
196 MLX5_GET64(ppcnt_reg, pstats->IEEE_802_3_counters, \
197 counter_set.eth_802_3_cntrs_grp_data_layout.c##_high)
198#define PPORT_2863_OFF(c) \
199 MLX5_BYTE_OFF(ppcnt_reg, \
200 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
201#define PPORT_2863_GET(pstats, c) \
202 MLX5_GET64(ppcnt_reg, pstats->RFC_2863_counters, \
203 counter_set.eth_2863_cntrs_grp_data_layout.c##_high)
204#define PPORT_2819_OFF(c) \
205 MLX5_BYTE_OFF(ppcnt_reg, \
206 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
207#define PPORT_2819_GET(pstats, c) \
208 MLX5_GET64(ppcnt_reg, pstats->RFC_2819_counters, \
209 counter_set.eth_2819_cntrs_grp_data_layout.c##_high)
5db0a4f6
GP		 210#define PPORT_PHY_STATISTICAL_OFF(c) \
211 MLX5_BYTE_OFF(ppcnt_reg, \
212 counter_set.phys_layer_statistical_cntrs.c##_high)
213#define PPORT_PHY_STATISTICAL_GET(pstats, c) \
214 MLX5_GET64(ppcnt_reg, (pstats)->phy_statistical_counters, \
215 counter_set.phys_layer_statistical_cntrs.c##_high)
cf678570
GP		 216#define PPORT_PER_PRIO_OFF(c) \
217 MLX5_BYTE_OFF(ppcnt_reg, \
218 counter_set.eth_per_prio_grp_data_layout.c##_high)
219#define PPORT_PER_PRIO_GET(pstats, prio, c) \
220 MLX5_GET64(ppcnt_reg, pstats->per_prio_counters[prio], \
221 counter_set.eth_per_prio_grp_data_layout.c##_high)
222#define NUM_PPORT_PRIO 8
068aef33
GP		 223#define PPORT_ETH_EXT_OFF(c) \
224 MLX5_BYTE_OFF(ppcnt_reg, \
225 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
226#define PPORT_ETH_EXT_GET(pstats, c) \
227 MLX5_GET64(ppcnt_reg, (pstats)->eth_ext_counters, \
228 counter_set.eth_extended_cntrs_grp_data_layout.c##_high)
9218b44d
GP		 229
230struct mlx5e_pport_stats {
231 __be64 IEEE_802_3_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
232 __be64 RFC_2863_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
233 __be64 RFC_2819_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
cf678570 234 __be64 per_prio_counters[NUM_PPORT_PRIO][MLX5_ST_SZ_QW(ppcnt_reg)];
121fcdc8 235 __be64 phy_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
5db0a4f6 236 __be64 phy_statistical_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
068aef33 237 __be64 eth_ext_counters[MLX5_ST_SZ_QW(ppcnt_reg)];
9218b44d
GP		 238};
239
240static const struct counter_desc pport_802_3_stats_desc[] = {
bfe6d8d1
GP		 241 { "tx_packets_phy", PPORT_802_3_OFF(a_frames_transmitted_ok) },
242 { "rx_packets_phy", PPORT_802_3_OFF(a_frames_received_ok) },
243 { "rx_crc_errors_phy", PPORT_802_3_OFF(a_frame_check_sequence_errors) },
244 { "tx_bytes_phy", PPORT_802_3_OFF(a_octets_transmitted_ok) },
245 { "rx_bytes_phy", PPORT_802_3_OFF(a_octets_received_ok) },
246 { "tx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_xmitted_ok) },
247 { "tx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_xmitted_ok) },
248 { "rx_multicast_phy", PPORT_802_3_OFF(a_multicast_frames_received_ok) },
249 { "rx_broadcast_phy", PPORT_802_3_OFF(a_broadcast_frames_received_ok) },
250 { "rx_in_range_len_errors_phy", PPORT_802_3_OFF(a_in_range_length_errors) },
251 { "rx_out_of_range_len_phy", PPORT_802_3_OFF(a_out_of_range_length_field) },
252 { "rx_oversize_pkts_phy", PPORT_802_3_OFF(a_frame_too_long_errors) },
253 { "rx_symbol_err_phy", PPORT_802_3_OFF(a_symbol_error_during_carrier) },
254 { "tx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_transmitted) },
255 { "rx_mac_control_phy", PPORT_802_3_OFF(a_mac_control_frames_received) },
256 { "rx_unsupported_op_phy", PPORT_802_3_OFF(a_unsupported_opcodes_received) },
257 { "rx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_received) },
258 { "tx_pause_ctrl_phy", PPORT_802_3_OFF(a_pause_mac_ctrl_frames_transmitted) },
9218b44d
GP		 259};
260
261static const struct counter_desc pport_2863_stats_desc[] = {
bfe6d8d1
GP		 262 { "rx_discards_phy", PPORT_2863_OFF(if_in_discards) },
263 { "tx_discards_phy", PPORT_2863_OFF(if_out_discards) },
264 { "tx_errors_phy", PPORT_2863_OFF(if_out_errors) },
9218b44d
GP		 265};
266
267static const struct counter_desc pport_2819_stats_desc[] = {
bfe6d8d1
GP		 268 { "rx_undersize_pkts_phy", PPORT_2819_OFF(ether_stats_undersize_pkts) },
269 { "rx_fragments_phy", PPORT_2819_OFF(ether_stats_fragments) },
270 { "rx_jabbers_phy", PPORT_2819_OFF(ether_stats_jabbers) },
271 { "rx_64_bytes_phy", PPORT_2819_OFF(ether_stats_pkts64octets) },
272 { "rx_65_to_127_bytes_phy", PPORT_2819_OFF(ether_stats_pkts65to127octets) },
273 { "rx_128_to_255_bytes_phy", PPORT_2819_OFF(ether_stats_pkts128to255octets) },
274 { "rx_256_to_511_bytes_phy", PPORT_2819_OFF(ether_stats_pkts256to511octets) },
275 { "rx_512_to_1023_bytes_phy", PPORT_2819_OFF(ether_stats_pkts512to1023octets) },
276 { "rx_1024_to_1518_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1024to1518octets) },
277 { "rx_1519_to_2047_bytes_phy", PPORT_2819_OFF(ether_stats_pkts1519to2047octets) },
278 { "rx_2048_to_4095_bytes_phy", PPORT_2819_OFF(ether_stats_pkts2048to4095octets) },
279 { "rx_4096_to_8191_bytes_phy", PPORT_2819_OFF(ether_stats_pkts4096to8191octets) },
280 { "rx_8192_to_10239_bytes_phy", PPORT_2819_OFF(ether_stats_pkts8192to10239octets) },
9218b44d
GP		 281};
282
5db0a4f6 283static const struct counter_desc pport_phy_statistical_stats_desc[] = {
ebc88870 284 { "rx_pcs_symbol_err_phy", PPORT_PHY_STATISTICAL_OFF(phy_symbol_errors) },
5db0a4f6
GP		 285 { "rx_corrected_bits_phy", PPORT_PHY_STATISTICAL_OFF(phy_corrected_bits) },
286};
287
cf678570 288static const struct counter_desc pport_per_prio_traffic_stats_desc[] = {
bfe6d8d1
GP		 289 { "rx_prio%d_bytes", PPORT_PER_PRIO_OFF(rx_octets) },
290 { "rx_prio%d_packets", PPORT_PER_PRIO_OFF(rx_frames) },
291 { "tx_prio%d_bytes", PPORT_PER_PRIO_OFF(tx_octets) },
292 { "tx_prio%d_packets", PPORT_PER_PRIO_OFF(tx_frames) },
cf678570
GP		 293};
294
295static const struct counter_desc pport_per_prio_pfc_stats_desc[] = {
e989d5a5
GP		 296 /* %s is "global" or "prio{i}" */
297 { "rx_%s_pause", PPORT_PER_PRIO_OFF(rx_pause) },
298 { "rx_%s_pause_duration", PPORT_PER_PRIO_OFF(rx_pause_duration) },
299 { "tx_%s_pause", PPORT_PER_PRIO_OFF(tx_pause) },
300 { "tx_%s_pause_duration", PPORT_PER_PRIO_OFF(tx_pause_duration) },
301 { "rx_%s_pause_transition", PPORT_PER_PRIO_OFF(rx_pause_transition) },
cf678570
GP		 302};
303
068aef33
GP		 304static const struct counter_desc pport_eth_ext_stats_desc[] = {
305 { "rx_buffer_passed_thres_phy", PPORT_ETH_EXT_OFF(rx_buffer_almost_full) },
306};
307
0f7f3481
GP		 308#define PCIE_PERF_OFF(c) \
309 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c)
310#define PCIE_PERF_GET(pcie_stats, c) \
311 MLX5_GET(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
312 counter_set.pcie_perf_cntrs_grp_data_layout.c)
313
efae7f78
EBE		 314#define PCIE_PERF_OFF64(c) \
315 MLX5_BYTE_OFF(mpcnt_reg, counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
316#define PCIE_PERF_GET64(pcie_stats, c) \
317 MLX5_GET64(mpcnt_reg, (pcie_stats)->pcie_perf_counters, \
318 counter_set.pcie_perf_cntrs_grp_data_layout.c##_high)
319
0f7f3481
GP		 320struct mlx5e_pcie_stats {
321 __be64 pcie_perf_counters[MLX5_ST_SZ_QW(mpcnt_reg)];
322};
323
324static const struct counter_desc pcie_perf_stats_desc[] = {
325 { "rx_pci_signal_integrity", PCIE_PERF_OFF(rx_errors) },
326 { "tx_pci_signal_integrity", PCIE_PERF_OFF(tx_errors) },
327};
328
efae7f78
EBE		 329static const struct counter_desc pcie_perf_stats_desc64[] = {
330 { "outbound_pci_buffer_overflow", PCIE_PERF_OFF64(tx_overflow_buffer_pkt) },
331};
332
73e90646
GP		 333static const struct counter_desc pcie_perf_stall_stats_desc[] = {
334 { "outbound_pci_stalled_rd", PCIE_PERF_OFF(outbound_stalled_reads) },
335 { "outbound_pci_stalled_wr", PCIE_PERF_OFF(outbound_stalled_writes) },
336 { "outbound_pci_stalled_rd_events", PCIE_PERF_OFF(outbound_stalled_reads_events) },
337 { "outbound_pci_stalled_wr_events", PCIE_PERF_OFF(outbound_stalled_writes_events) },
338};
339
9218b44d
GP		 340struct mlx5e_rq_stats {
341 u64 packets;
342 u64 bytes;
bfe6d8d1 343 u64 csum_complete;
603e1f5b 344 u64 csum_unnecessary;
bfe6d8d1 345 u64 csum_unnecessary_inner;
1b223dd3 346 u64 csum_none;
9218b44d
GP		 347 u64 lro_packets;
348 u64 lro_bytes;
86994156 349 u64 xdp_drop;
b5503b99
SM		 350 u64 xdp_tx;
351 u64 xdp_tx_full;
9218b44d
GP		 352 u64 wqe_err;
353 u64 mpwqe_filler;
9218b44d 354 u64 buff_alloc_err;
7219ab34
TT		 355 u64 cqe_compress_blks;
356 u64 cqe_compress_pkts;
accd5883 357 u64 page_reuse;
4415a031
TT		 358 u64 cache_reuse;
359 u64 cache_full;
360 u64 cache_empty;
361 u64 cache_busy;
70871f1e 362 u64 cache_waive;
9218b44d
GP		 363};
364
365static const struct counter_desc rq_stats_desc[] = {
bfe6d8d1
GP		 366 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, packets) },
367 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, bytes) },
368 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_complete) },
603e1f5b 369 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary) },
bfe6d8d1
GP		 370 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_unnecessary_inner) },
371 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, csum_none) },
86994156 372 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_drop) },
b5503b99
SM		 373 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx) },
374 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, xdp_tx_full) },
bfe6d8d1
GP		 375 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_packets) },
376 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, lro_bytes) },
377 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, wqe_err) },
378 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, mpwqe_filler) },
bfe6d8d1
GP		 379 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, buff_alloc_err) },
380 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_blks) },
381 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cqe_compress_pkts) },
accd5883 382 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, page_reuse) },
4415a031
TT		 383 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_reuse) },
384 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_full) },
385 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_empty) },
386 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_busy) },
70871f1e 387 { MLX5E_DECLARE_RX_STAT(struct mlx5e_rq_stats, cache_waive) },
9218b44d
GP		 388};
389
390struct mlx5e_sq_stats {
391 /* commonly accessed in data path */
392 u64 packets;
393 u64 bytes;
c8cf78fe 394 u64 xmit_more;
9218b44d
GP		 395 u64 tso_packets;
396 u64 tso_bytes;
397 u64 tso_inner_packets;
398 u64 tso_inner_bytes;
603e1f5b 399 u64 csum_partial;
bfe6d8d1 400 u64 csum_partial_inner;
9218b44d
GP		 401 u64 nop;
402 /* less likely accessed in data path */
bfe6d8d1 403 u64 csum_none;
9218b44d
GP		 404 u64 stopped;
405 u64 wake;
406 u64 dropped;
407};
408
409static const struct counter_desc sq_stats_desc[] = {
bfe6d8d1
GP		 410 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, packets) },
411 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, bytes) },
412 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_packets) },
413 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_bytes) },
414 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_packets) },
415 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, tso_inner_bytes) },
603e1f5b 416 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial) },
bfe6d8d1
GP		 417 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_partial_inner) },
418 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, nop) },
419 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, csum_none) },
420 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, stopped) },
421 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, wake) },
422 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, dropped) },
c8cf78fe 423 { MLX5E_DECLARE_TX_STAT(struct mlx5e_sq_stats, xmit_more) },
9218b44d
GP		 424};
425
426#define NUM_SW_COUNTERS ARRAY_SIZE(sw_stats_desc)
427#define NUM_Q_COUNTERS ARRAY_SIZE(q_stats_desc)
428#define NUM_VPORT_COUNTERS ARRAY_SIZE(vport_stats_desc)
429#define NUM_PPORT_802_3_COUNTERS ARRAY_SIZE(pport_802_3_stats_desc)
430#define NUM_PPORT_2863_COUNTERS ARRAY_SIZE(pport_2863_stats_desc)
431#define NUM_PPORT_2819_COUNTERS ARRAY_SIZE(pport_2819_stats_desc)
5db0a4f6
GP		 432#define NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) \
433 (ARRAY_SIZE(pport_phy_statistical_stats_desc) * \
434 MLX5_CAP_PCAM_FEATURE((priv)->mdev, ppcnt_statistical_group))
0f7f3481
GP		 435#define NUM_PCIE_PERF_COUNTERS(priv) \
436 (ARRAY_SIZE(pcie_perf_stats_desc) * \
437 MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_performance_group))
efae7f78
EBE		 438#define NUM_PCIE_PERF_COUNTERS64(priv) \
439 (ARRAY_SIZE(pcie_perf_stats_desc64) * \
440 MLX5_CAP_MCAM_FEATURE((priv)->mdev, tx_overflow_buffer_pkt))
73e90646
GP		 441#define NUM_PCIE_PERF_STALL_COUNTERS(priv) \
442 (ARRAY_SIZE(pcie_perf_stall_stats_desc) * \
443 MLX5_CAP_MCAM_FEATURE((priv)->mdev, pcie_outbound_stalled))
cf678570
GP		 444#define NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS \
445 ARRAY_SIZE(pport_per_prio_traffic_stats_desc)
446#define NUM_PPORT_PER_PRIO_PFC_COUNTERS \
447 ARRAY_SIZE(pport_per_prio_pfc_stats_desc)
068aef33
GP		 448#define NUM_PPORT_ETH_EXT_COUNTERS(priv) \
449 (ARRAY_SIZE(pport_eth_ext_stats_desc) * \
450 MLX5_CAP_PCAM_FEATURE((priv)->mdev, rx_buffer_fullness_counters))
5db0a4f6 451#define NUM_PPORT_COUNTERS(priv) (NUM_PPORT_802_3_COUNTERS + \
9218b44d 452 NUM_PPORT_2863_COUNTERS + \
cf678570 453 NUM_PPORT_2819_COUNTERS + \
5db0a4f6 454 NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv) + \
cf678570 455 NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS * \
068aef33
GP		 456 NUM_PPORT_PRIO + \
457 NUM_PPORT_ETH_EXT_COUNTERS(priv))
73e90646 458#define NUM_PCIE_COUNTERS(priv) (NUM_PCIE_PERF_COUNTERS(priv) + \
efae7f78 459 NUM_PCIE_PERF_COUNTERS64(priv) +\
73e90646 460 NUM_PCIE_PERF_STALL_COUNTERS(priv))
9218b44d
GP		 461#define NUM_RQ_STATS ARRAY_SIZE(rq_stats_desc)
462#define NUM_SQ_STATS ARRAY_SIZE(sq_stats_desc)
463
464struct mlx5e_stats {
465 struct mlx5e_sw_stats sw;
466 struct mlx5e_qcounter_stats qcnt;
467 struct mlx5e_vport_stats vport;
468 struct mlx5e_pport_stats pport;
370bad0f 469 struct rtnl_link_stats64 vf_vport;
0f7f3481 470 struct mlx5e_pcie_stats pcie;
9218b44d
GP		 471};
472
bedb7c90 473static const struct counter_desc mlx5e_pme_status_desc[] = {
bedb7c90
HN		 474 { "module_unplug", 8 },
475};
476
477static const struct counter_desc mlx5e_pme_error_desc[] = {
f729860a
HN		 478 { "module_bus_stuck", 16 }, /* bus stuck (I2C or data shorted) */
479 { "module_high_temp", 48 }, /* high temperature */
bedb7c90 480 { "module_bad_shorted", 56 }, /* bad or shorted cable/module */
bedb7c90
HN		 481};
482
9218b44d 483#endif /* __MLX5_EN_STATS_H__ */
Linux 6.x block layer and io_uring tree(s)