Commit | Line | Data |
---|---|---|
e586b3b0 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
18bcf742 | 33 | #include <linux/prefetch.h> |
e586b3b0 AV |
34 | #include <linux/ip.h> |
35 | #include <linux/ipv6.h> | |
36 | #include <linux/tcp.h> | |
a67edbf4 | 37 | #include <linux/bpf_trace.h> |
7ae92ae5 | 38 | #include <net/busy_poll.h> |
8babd44d | 39 | #include <net/ip6_checksum.h> |
60bbf7ee | 40 | #include <net/page_pool.h> |
e586b3b0 | 41 | #include "en.h" |
12185a9f | 42 | #include "en_tc.h" |
f5f82476 | 43 | #include "eswitch.h" |
1d447a39 | 44 | #include "en_rep.h" |
4301ba7b | 45 | #include "ipoib/ipoib.h" |
899a59d3 | 46 | #include "en_accel/ipsec_rxtx.h" |
7c39afb3 | 47 | #include "lib/clock.h" |
e586b3b0 | 48 | |
7c39afb3 | 49 | static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) |
ef9814de | 50 | { |
7c39afb3 | 51 | return config->rx_filter == HWTSTAMP_FILTER_ALL; |
ef9814de EBE |
52 | } |
53 | ||
7219ab34 TT |
54 | static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, |
55 | void *data) | |
56 | { | |
ddf385e3 | 57 | u32 ci = mlx5_cqwq_ctr2ix(&cq->wq, cqcc); |
7219ab34 TT |
58 | |
59 | memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); | |
60 | } | |
61 | ||
62 | static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, | |
63 | struct mlx5e_cq *cq, u32 cqcc) | |
64 | { | |
65 | mlx5e_read_cqe_slot(cq, cqcc, &cq->title); | |
66 | cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); | |
67 | cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); | |
68 | rq->stats.cqe_compress_blks++; | |
69 | } | |
70 | ||
71 | static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) | |
72 | { | |
73 | mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); | |
74 | cq->mini_arr_idx = 0; | |
75 | } | |
76 | ||
77 | static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) | |
78 | { | |
ddf385e3 TT |
79 | struct mlx5_cqwq *wq = &cq->wq; |
80 | ||
81 | u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1; | |
82 | u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc); | |
83 | u32 wq_sz = mlx5_cqwq_get_size(wq); | |
7219ab34 TT |
84 | u32 ci_top = min_t(u32, wq_sz, ci + n); |
85 | ||
86 | for (; ci < ci_top; ci++, n--) { | |
87 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); | |
88 | ||
89 | cqe->op_own = op_own; | |
90 | } | |
91 | ||
92 | if (unlikely(ci == wq_sz)) { | |
93 | op_own = !op_own; | |
94 | for (ci = 0; ci < n; ci++) { | |
95 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); | |
96 | ||
97 | cqe->op_own = op_own; | |
98 | } | |
99 | } | |
100 | } | |
101 | ||
102 | static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, | |
103 | struct mlx5e_cq *cq, u32 cqcc) | |
104 | { | |
7219ab34 TT |
105 | cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; |
106 | cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; | |
107 | cq->title.op_own &= 0xf0; | |
388ca8be | 108 | cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz); |
7219ab34 TT |
109 | cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); |
110 | ||
36154be4 TT |
111 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
112 | cq->decmprs_wqe_counter += | |
113 | mpwrq_get_cqe_consumed_strides(&cq->title); | |
114 | else | |
115 | cq->decmprs_wqe_counter = | |
ddf385e3 | 116 | mlx5_wq_ll_ctr2ix(&rq->wq, cq->decmprs_wqe_counter + 1); |
7219ab34 TT |
117 | } |
118 | ||
119 | static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, | |
120 | struct mlx5e_cq *cq, u32 cqcc) | |
121 | { | |
122 | mlx5e_decompress_cqe(rq, cq, cqcc); | |
123 | cq->title.rss_hash_type = 0; | |
124 | cq->title.rss_hash_result = 0; | |
125 | } | |
126 | ||
127 | static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, | |
128 | struct mlx5e_cq *cq, | |
129 | int update_owner_only, | |
130 | int budget_rem) | |
131 | { | |
132 | u32 cqcc = cq->wq.cc + update_owner_only; | |
133 | u32 cqe_count; | |
134 | u32 i; | |
135 | ||
136 | cqe_count = min_t(u32, cq->decmprs_left, budget_rem); | |
137 | ||
138 | for (i = update_owner_only; i < cqe_count; | |
139 | i++, cq->mini_arr_idx++, cqcc++) { | |
d9d9f156 | 140 | if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) |
7219ab34 TT |
141 | mlx5e_read_mini_arr_slot(cq, cqcc); |
142 | ||
143 | mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); | |
144 | rq->handle_rx_cqe(rq, &cq->title); | |
145 | } | |
146 | mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); | |
147 | cq->wq.cc = cqcc; | |
148 | cq->decmprs_left -= cqe_count; | |
149 | rq->stats.cqe_compress_pkts += cqe_count; | |
150 | ||
151 | return cqe_count; | |
152 | } | |
153 | ||
154 | static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, | |
155 | struct mlx5e_cq *cq, | |
156 | int budget_rem) | |
157 | { | |
158 | mlx5e_read_title_slot(rq, cq, cq->wq.cc); | |
159 | mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); | |
160 | mlx5e_decompress_cqe(rq, cq, cq->wq.cc); | |
161 | rq->handle_rx_cqe(rq, &cq->title); | |
162 | cq->mini_arr_idx++; | |
163 | ||
164 | return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; | |
165 | } | |
166 | ||
1bfecfca SM |
167 | #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) |
168 | ||
accd5883 TT |
169 | static inline bool mlx5e_page_is_reserved(struct page *page) |
170 | { | |
70871f1e | 171 | return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); |
accd5883 TT |
172 | } |
173 | ||
1bfecfca SM |
174 | static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, |
175 | struct mlx5e_dma_info *dma_info) | |
e586b3b0 | 176 | { |
1bfecfca SM |
177 | struct mlx5e_page_cache *cache = &rq->page_cache; |
178 | u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); | |
e586b3b0 | 179 | |
1bfecfca SM |
180 | if (tail_next == cache->head) { |
181 | rq->stats.cache_full++; | |
182 | return false; | |
183 | } | |
e586b3b0 | 184 | |
70871f1e TT |
185 | if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { |
186 | rq->stats.cache_waive++; | |
e048fc50 | 187 | return false; |
70871f1e | 188 | } |
e048fc50 | 189 | |
1bfecfca SM |
190 | cache->page_cache[cache->tail] = *dma_info; |
191 | cache->tail = tail_next; | |
192 | return true; | |
193 | } | |
e586b3b0 | 194 | |
1bfecfca SM |
195 | static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, |
196 | struct mlx5e_dma_info *dma_info) | |
197 | { | |
198 | struct mlx5e_page_cache *cache = &rq->page_cache; | |
199 | ||
200 | if (unlikely(cache->head == cache->tail)) { | |
201 | rq->stats.cache_empty++; | |
202 | return false; | |
203 | } | |
204 | ||
205 | if (page_ref_count(cache->page_cache[cache->head].page) != 1) { | |
206 | rq->stats.cache_busy++; | |
207 | return false; | |
208 | } | |
e586b3b0 | 209 | |
1bfecfca SM |
210 | *dma_info = cache->page_cache[cache->head]; |
211 | cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); | |
212 | rq->stats.cache_reuse++; | |
e586b3b0 | 213 | |
1bfecfca SM |
214 | dma_sync_single_for_device(rq->pdev, dma_info->addr, |
215 | RQ_PAGE_SIZE(rq), | |
216 | DMA_FROM_DEVICE); | |
217 | return true; | |
218 | } | |
219 | ||
220 | static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, | |
221 | struct mlx5e_dma_info *dma_info) | |
222 | { | |
1bfecfca SM |
223 | if (mlx5e_rx_cache_get(rq, dma_info)) |
224 | return 0; | |
225 | ||
60bbf7ee | 226 | dma_info->page = page_pool_dev_alloc_pages(rq->page_pool); |
2e50b261 | 227 | if (unlikely(!dma_info->page)) |
1bfecfca SM |
228 | return -ENOMEM; |
229 | ||
2e50b261 | 230 | dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, |
b5503b99 | 231 | RQ_PAGE_SIZE(rq), rq->buff.map_dir); |
1bfecfca | 232 | if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { |
2e50b261 IK |
233 | put_page(dma_info->page); |
234 | dma_info->page = NULL; | |
1bfecfca SM |
235 | return -ENOMEM; |
236 | } | |
e586b3b0 AV |
237 | |
238 | return 0; | |
1bfecfca SM |
239 | } |
240 | ||
5168d732 JDB |
241 | static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, |
242 | struct mlx5e_dma_info *dma_info) | |
243 | { | |
244 | dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), | |
245 | rq->buff.map_dir); | |
246 | } | |
247 | ||
1bfecfca SM |
248 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
249 | bool recycle) | |
250 | { | |
60bbf7ee JDB |
251 | if (likely(recycle)) { |
252 | if (mlx5e_rx_cache_put(rq, dma_info)) | |
253 | return; | |
254 | ||
255 | mlx5e_page_dma_unmap(rq, dma_info); | |
256 | page_pool_recycle_direct(rq->page_pool, dma_info->page); | |
257 | } else { | |
258 | mlx5e_page_dma_unmap(rq, dma_info); | |
259 | put_page(dma_info->page); | |
260 | } | |
1bfecfca SM |
261 | } |
262 | ||
accd5883 TT |
263 | static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, |
264 | struct mlx5e_wqe_frag_info *wi) | |
265 | { | |
266 | return rq->wqe.page_reuse && wi->di.page && | |
267 | (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && | |
268 | !mlx5e_page_is_reserved(wi->di.page); | |
269 | } | |
270 | ||
7cc6d77b | 271 | static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) |
1bfecfca | 272 | { |
accd5883 | 273 | struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; |
e586b3b0 | 274 | |
accd5883 TT |
275 | /* check if page exists, hence can be reused */ |
276 | if (!wi->di.page) { | |
277 | if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) | |
278 | return -ENOMEM; | |
279 | wi->offset = 0; | |
280 | } | |
e586b3b0 | 281 | |
b45d8b50 | 282 | wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); |
1bfecfca | 283 | return 0; |
e586b3b0 AV |
284 | } |
285 | ||
accd5883 TT |
286 | static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, |
287 | struct mlx5e_wqe_frag_info *wi) | |
288 | { | |
289 | mlx5e_page_release(rq, &wi->di, true); | |
290 | wi->di.page = NULL; | |
291 | } | |
292 | ||
293 | static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, | |
294 | struct mlx5e_wqe_frag_info *wi) | |
295 | { | |
296 | if (mlx5e_page_reuse(rq, wi)) { | |
297 | rq->stats.page_reuse++; | |
298 | return; | |
299 | } | |
300 | ||
301 | mlx5e_free_rx_wqe(rq, wi); | |
302 | } | |
303 | ||
6cd392a0 DJ |
304 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) |
305 | { | |
accd5883 | 306 | struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; |
6cd392a0 | 307 | |
accd5883 TT |
308 | if (wi->di.page) |
309 | mlx5e_free_rx_wqe(rq, wi); | |
6cd392a0 DJ |
310 | } |
311 | ||
7e426671 TT |
312 | static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, |
313 | struct sk_buff *skb, | |
9f9e9cd5 TT |
314 | struct mlx5e_dma_info *di, |
315 | u32 frag_offset, u32 len) | |
bc77b240 | 316 | { |
89e89f7a | 317 | unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); |
bc77b240 | 318 | |
d9d9f156 | 319 | dma_sync_single_for_cpu(rq->pdev, |
9f9e9cd5 | 320 | di->addr + frag_offset, |
bc77b240 | 321 | len, DMA_FROM_DEVICE); |
9f9e9cd5 | 322 | page_ref_inc(di->page); |
bc77b240 | 323 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, |
9f9e9cd5 | 324 | di->page, frag_offset, len, truesize); |
bc77b240 TT |
325 | } |
326 | ||
327 | static inline void | |
7e426671 TT |
328 | mlx5e_copy_skb_header_mpwqe(struct device *pdev, |
329 | struct sk_buff *skb, | |
9f9e9cd5 TT |
330 | struct mlx5e_dma_info *dma_info, |
331 | u32 offset, u32 headlen) | |
bc77b240 TT |
332 | { |
333 | u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); | |
bc77b240 TT |
334 | unsigned int len; |
335 | ||
336 | /* Aligning len to sizeof(long) optimizes memcpy performance */ | |
337 | len = ALIGN(headlen_pg, sizeof(long)); | |
338 | dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, | |
339 | DMA_FROM_DEVICE); | |
24fd07ab TT |
340 | skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len); |
341 | ||
bc77b240 TT |
342 | if (unlikely(offset + headlen > PAGE_SIZE)) { |
343 | dma_info++; | |
344 | headlen_pg = len; | |
345 | len = ALIGN(headlen - headlen_pg, sizeof(long)); | |
346 | dma_sync_single_for_cpu(pdev, dma_info->addr, len, | |
347 | DMA_FROM_DEVICE); | |
348 | skb_copy_to_linear_data_offset(skb, headlen_pg, | |
349 | page_address(dma_info->page), | |
350 | len); | |
351 | } | |
bc77b240 TT |
352 | } |
353 | ||
18187fb2 | 354 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) |
bc77b240 | 355 | { |
22f45398 TT |
356 | const bool no_xdp_xmit = |
357 | bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); | |
22f45398 | 358 | struct mlx5e_dma_info *dma_info = wi->umr.dma_info; |
18187fb2 | 359 | int i; |
bc77b240 | 360 | |
9f9e9cd5 | 361 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) |
22f45398 TT |
362 | if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) |
363 | mlx5e_page_release(rq, &dma_info[i], true); | |
18187fb2 | 364 | } |
bc77b240 | 365 | |
18187fb2 TT |
366 | static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) |
367 | { | |
368 | struct mlx5_wq_ll *wq = &rq->wq; | |
369 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); | |
7e426671 | 370 | |
18187fb2 TT |
371 | rq->mpwqe.umr_in_progress = false; |
372 | ||
373 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
374 | ||
375 | /* ensure wqes are visible to device before updating doorbell record */ | |
376 | dma_wmb(); | |
377 | ||
378 | mlx5_wq_ll_update_db_record(wq); | |
bc77b240 TT |
379 | } |
380 | ||
ab966d7e TT |
381 | static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq) |
382 | { | |
383 | return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; | |
384 | } | |
385 | ||
3a2f7033 TT |
386 | static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq, |
387 | struct mlx5_wq_cyc *wq, | |
388 | u16 pi, u16 frag_pi) | |
043dc78e TT |
389 | { |
390 | struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi]; | |
3a2f7033 | 391 | u8 nnops = mlx5_wq_cyc_get_frag_size(wq) - frag_pi; |
043dc78e TT |
392 | |
393 | edge_wi = wi + nnops; | |
394 | ||
3a2f7033 | 395 | /* fill sq frag edge with nops to avoid wqe wrapping two pages */ |
043dc78e TT |
396 | for (; wi < edge_wi; wi++) { |
397 | wi->opcode = MLX5_OPCODE_NOP; | |
398 | mlx5e_post_nop(wq, sq->sqn, &sq->pc); | |
399 | } | |
400 | } | |
401 | ||
18187fb2 | 402 | static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) |
bc77b240 | 403 | { |
21c59685 | 404 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; |
4c2af5cc | 405 | struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; |
18187fb2 TT |
406 | struct mlx5e_icosq *sq = &rq->channel->icosq; |
407 | struct mlx5_wq_cyc *wq = &sq->wq; | |
ea3886ca | 408 | struct mlx5e_umr_wqe *umr_wqe; |
b8a98a4c | 409 | u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1); |
3a2f7033 | 410 | u16 pi, frag_pi; |
043dc78e | 411 | int err; |
bc77b240 TT |
412 | int i; |
413 | ||
043dc78e | 414 | pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
3a2f7033 | 415 | frag_pi = mlx5_wq_cyc_ctr2fragix(wq, sq->pc); |
043dc78e | 416 | |
3a2f7033 TT |
417 | if (unlikely(frag_pi + MLX5E_UMR_WQEBBS > mlx5_wq_cyc_get_frag_size(wq))) { |
418 | mlx5e_fill_icosq_frag_edge(sq, wq, pi, frag_pi); | |
043dc78e | 419 | pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
ea3886ca TT |
420 | } |
421 | ||
422 | umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
ab966d7e TT |
423 | if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2)) |
424 | memcpy(umr_wqe, &rq->mpwqe.umr_wqe, | |
425 | offsetof(struct mlx5e_umr_wqe, inline_mtts)); | |
426 | ||
4c2af5cc | 427 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { |
a5a0c590 | 428 | err = mlx5e_page_alloc_mapped(rq, dma_info); |
7e426671 | 429 | if (unlikely(err)) |
bc77b240 | 430 | goto err_unmap; |
ea3886ca | 431 | umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR); |
bc77b240 TT |
432 | } |
433 | ||
22f45398 | 434 | bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
bc77b240 | 435 | wi->consumed_strides = 0; |
bc77b240 | 436 | |
18187fb2 TT |
437 | rq->mpwqe.umr_in_progress = true; |
438 | ||
ea3886ca | 439 | umr_wqe->ctrl.opmod_idx_opcode = |
18187fb2 TT |
440 | cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | |
441 | MLX5_OPCODE_UMR); | |
b8a98a4c | 442 | umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset); |
18187fb2 TT |
443 | |
444 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; | |
ea3886ca TT |
445 | sq->pc += MLX5E_UMR_WQEBBS; |
446 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl); | |
18187fb2 | 447 | |
bc77b240 TT |
448 | return 0; |
449 | ||
450 | err_unmap: | |
451 | while (--i >= 0) { | |
4c2af5cc | 452 | dma_info--; |
4415a031 | 453 | mlx5e_page_release(rq, dma_info, true); |
bc77b240 | 454 | } |
18187fb2 | 455 | rq->stats.buff_alloc_err++; |
bc77b240 | 456 | |
7e426671 | 457 | return err; |
bc77b240 TT |
458 | } |
459 | ||
6cd392a0 DJ |
460 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) |
461 | { | |
21c59685 | 462 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; |
6cd392a0 | 463 | |
7e426671 | 464 | mlx5e_free_rx_mpwqe(rq, wi); |
6cd392a0 DJ |
465 | } |
466 | ||
e586b3b0 AV |
467 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) |
468 | { | |
469 | struct mlx5_wq_ll *wq = &rq->wq; | |
4b7dfc99 | 470 | int err; |
e586b3b0 | 471 | |
0e5c04f6 | 472 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
e586b3b0 AV |
473 | return false; |
474 | ||
4b7dfc99 TT |
475 | if (mlx5_wq_ll_is_full(wq)) |
476 | return false; | |
477 | ||
4b7dfc99 | 478 | do { |
e586b3b0 AV |
479 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); |
480 | ||
7cc6d77b | 481 | err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); |
54984407 | 482 | if (unlikely(err)) { |
7e426671 | 483 | rq->stats.buff_alloc_err++; |
e586b3b0 | 484 | break; |
54984407 | 485 | } |
e586b3b0 AV |
486 | |
487 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
4b7dfc99 | 488 | } while (!mlx5_wq_ll_is_full(wq)); |
e586b3b0 AV |
489 | |
490 | /* ensure wqes are visible to device before updating doorbell record */ | |
491 | dma_wmb(); | |
492 | ||
493 | mlx5_wq_ll_update_db_record(wq); | |
494 | ||
4b7dfc99 | 495 | return !!err; |
e586b3b0 AV |
496 | } |
497 | ||
7cc6d77b TT |
498 | static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, |
499 | struct mlx5e_icosq *sq, | |
500 | struct mlx5e_rq *rq, | |
3b56f7b2 | 501 | struct mlx5_cqe64 *cqe) |
7cc6d77b TT |
502 | { |
503 | struct mlx5_wq_cyc *wq = &sq->wq; | |
ddf385e3 | 504 | u16 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter)); |
7cc6d77b TT |
505 | struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; |
506 | ||
507 | mlx5_cqwq_pop(&cq->wq); | |
7cc6d77b TT |
508 | |
509 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { | |
cd4a87df GP |
510 | netdev_WARN_ONCE(cq->channel->netdev, |
511 | "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own); | |
7cc6d77b TT |
512 | return; |
513 | } | |
514 | ||
515 | if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { | |
516 | mlx5e_post_rx_mpwqe(rq); | |
517 | return; | |
518 | } | |
519 | ||
520 | if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) | |
cd4a87df GP |
521 | netdev_WARN_ONCE(cq->channel->netdev, |
522 | "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode); | |
7cc6d77b TT |
523 | } |
524 | ||
525 | static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) | |
526 | { | |
527 | struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); | |
528 | struct mlx5_cqe64 *cqe; | |
7cc6d77b | 529 | |
0e5c04f6 | 530 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
7cc6d77b TT |
531 | return; |
532 | ||
533 | cqe = mlx5_cqwq_get_cqe(&cq->wq); | |
534 | if (likely(!cqe)) | |
535 | return; | |
536 | ||
7cc6d77b | 537 | /* by design, there's only a single cqe */ |
3b56f7b2 | 538 | mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); |
7cc6d77b TT |
539 | |
540 | mlx5_cqwq_update_db_record(&cq->wq); | |
7cc6d77b TT |
541 | } |
542 | ||
543 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) | |
544 | { | |
545 | struct mlx5_wq_ll *wq = &rq->wq; | |
546 | ||
0e5c04f6 | 547 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
7cc6d77b TT |
548 | return false; |
549 | ||
550 | mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); | |
551 | ||
552 | if (mlx5_wq_ll_is_full(wq)) | |
553 | return false; | |
554 | ||
555 | if (!rq->mpwqe.umr_in_progress) | |
556 | mlx5e_alloc_rx_mpwqe(rq, wq->head); | |
557 | ||
e4d86a4a | 558 | return false; |
7cc6d77b TT |
559 | } |
560 | ||
8babd44d GP |
561 | static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) |
562 | { | |
563 | u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); | |
564 | u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || | |
565 | (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); | |
566 | ||
567 | tcp->check = 0; | |
568 | tcp->psh = get_cqe_lro_tcppsh(cqe); | |
569 | ||
570 | if (tcp_ack) { | |
571 | tcp->ack = 1; | |
572 | tcp->ack_seq = cqe->lro_ack_seq_num; | |
573 | tcp->window = cqe->lro_tcp_win; | |
574 | } | |
575 | } | |
576 | ||
461017cb TT |
577 | static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, |
578 | u32 cqe_bcnt) | |
e586b3b0 | 579 | { |
cd17d230 | 580 | struct ethhdr *eth = (struct ethhdr *)(skb->data); |
e586b3b0 | 581 | struct tcphdr *tcp; |
cd17d230 | 582 | int network_depth = 0; |
8babd44d | 583 | __wsum check; |
cd17d230 GP |
584 | __be16 proto; |
585 | u16 tot_len; | |
604acb19 | 586 | void *ip_p; |
e586b3b0 | 587 | |
cd17d230 | 588 | proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); |
e586b3b0 | 589 | |
cd17d230 | 590 | tot_len = cqe_bcnt - network_depth; |
604acb19 | 591 | ip_p = skb->data + network_depth; |
cd17d230 GP |
592 | |
593 | if (proto == htons(ETH_P_IP)) { | |
604acb19 | 594 | struct iphdr *ipv4 = ip_p; |
e586b3b0 | 595 | |
604acb19 TT |
596 | tcp = ip_p + sizeof(struct iphdr); |
597 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; | |
e586b3b0 | 598 | |
e586b3b0 AV |
599 | ipv4->ttl = cqe->lro_min_ttl; |
600 | ipv4->tot_len = cpu_to_be16(tot_len); | |
601 | ipv4->check = 0; | |
602 | ipv4->check = ip_fast_csum((unsigned char *)ipv4, | |
603 | ipv4->ihl); | |
8babd44d GP |
604 | |
605 | mlx5e_lro_update_tcp_hdr(cqe, tcp); | |
606 | check = csum_partial(tcp, tcp->doff * 4, | |
607 | csum_unfold((__force __sum16)cqe->check_sum)); | |
608 | /* Almost done, don't forget the pseudo header */ | |
609 | tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, | |
610 | tot_len - sizeof(struct iphdr), | |
611 | IPPROTO_TCP, check); | |
e586b3b0 | 612 | } else { |
8babd44d | 613 | u16 payload_len = tot_len - sizeof(struct ipv6hdr); |
604acb19 TT |
614 | struct ipv6hdr *ipv6 = ip_p; |
615 | ||
616 | tcp = ip_p + sizeof(struct ipv6hdr); | |
617 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; | |
618 | ||
e586b3b0 | 619 | ipv6->hop_limit = cqe->lro_min_ttl; |
8babd44d GP |
620 | ipv6->payload_len = cpu_to_be16(payload_len); |
621 | ||
622 | mlx5e_lro_update_tcp_hdr(cqe, tcp); | |
623 | check = csum_partial(tcp, tcp->doff * 4, | |
624 | csum_unfold((__force __sum16)cqe->check_sum)); | |
625 | /* Almost done, don't forget the pseudo header */ | |
626 | tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, | |
627 | IPPROTO_TCP, check); | |
604acb19 | 628 | } |
e586b3b0 AV |
629 | } |
630 | ||
631 | static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, | |
632 | struct sk_buff *skb) | |
633 | { | |
634 | u8 cht = cqe->rss_hash_type; | |
635 | int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : | |
636 | (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : | |
637 | PKT_HASH_TYPE_NONE; | |
638 | skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); | |
639 | } | |
640 | ||
f938daee | 641 | static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth) |
bbceefce AS |
642 | { |
643 | __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; | |
644 | ||
f938daee | 645 | ethertype = __vlan_get_protocol(skb, ethertype, network_depth); |
bbceefce AS |
646 | return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); |
647 | } | |
648 | ||
649 | static inline void mlx5e_handle_csum(struct net_device *netdev, | |
650 | struct mlx5_cqe64 *cqe, | |
651 | struct mlx5e_rq *rq, | |
5f6d12d1 MF |
652 | struct sk_buff *skb, |
653 | bool lro) | |
bbceefce | 654 | { |
f938daee GP |
655 | int network_depth = 0; |
656 | ||
bbceefce AS |
657 | if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) |
658 | goto csum_none; | |
659 | ||
5f6d12d1 | 660 | if (lro) { |
bbceefce | 661 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
603e1f5b | 662 | rq->stats.csum_unnecessary++; |
1b223dd3 SM |
663 | return; |
664 | } | |
665 | ||
63a612f9 | 666 | if (likely(is_last_ethertype_ip(skb, &network_depth))) { |
bbceefce | 667 | skb->ip_summed = CHECKSUM_COMPLETE; |
ecf842f6 | 668 | skb->csum = csum_unfold((__force __sum16)cqe->check_sum); |
f938daee GP |
669 | if (network_depth > ETH_HLEN) |
670 | /* CQE csum is calculated from the IP header and does | |
671 | * not cover VLAN headers (if present). This will add | |
672 | * the checksum manually. | |
673 | */ | |
674 | skb->csum = csum_partial(skb->data + ETH_HLEN, | |
675 | network_depth - ETH_HLEN, | |
676 | skb->csum); | |
bfe6d8d1 | 677 | rq->stats.csum_complete++; |
1b223dd3 | 678 | return; |
bbceefce AS |
679 | } |
680 | ||
1b223dd3 SM |
681 | if (likely((cqe->hds_ip_ext & CQE_L3_OK) && |
682 | (cqe->hds_ip_ext & CQE_L4_OK))) { | |
683 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
684 | if (cqe_is_tunneled(cqe)) { | |
685 | skb->csum_level = 1; | |
686 | skb->encapsulation = 1; | |
bfe6d8d1 | 687 | rq->stats.csum_unnecessary_inner++; |
603e1f5b | 688 | return; |
1b223dd3 | 689 | } |
603e1f5b | 690 | rq->stats.csum_unnecessary++; |
1b223dd3 SM |
691 | return; |
692 | } | |
bbceefce AS |
693 | csum_none: |
694 | skb->ip_summed = CHECKSUM_NONE; | |
695 | rq->stats.csum_none++; | |
696 | } | |
697 | ||
e586b3b0 | 698 | static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, |
461017cb | 699 | u32 cqe_bcnt, |
e586b3b0 AV |
700 | struct mlx5e_rq *rq, |
701 | struct sk_buff *skb) | |
702 | { | |
bd206fd5 | 703 | u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; |
e586b3b0 | 704 | struct net_device *netdev = rq->netdev; |
e586b3b0 | 705 | |
f938daee | 706 | skb->mac_len = ETH_HLEN; |
e586b3b0 | 707 | if (lro_num_seg > 1) { |
461017cb | 708 | mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); |
d9a40271 | 709 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); |
8ab7e2ae GP |
710 | /* Subtract one since we already counted this as one |
711 | * "regular" packet in mlx5e_complete_rx_cqe() | |
712 | */ | |
713 | rq->stats.packets += lro_num_seg - 1; | |
e586b3b0 AV |
714 | rq->stats.lro_packets++; |
715 | rq->stats.lro_bytes += cqe_bcnt; | |
716 | } | |
717 | ||
7c39afb3 FD |
718 | if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) |
719 | skb_hwtstamps(skb)->hwtstamp = | |
720 | mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); | |
ef9814de | 721 | |
e586b3b0 AV |
722 | skb_record_rx_queue(skb, rq->ix); |
723 | ||
724 | if (likely(netdev->features & NETIF_F_RXHASH)) | |
725 | mlx5e_skb_set_hash(cqe, skb); | |
726 | ||
f24686e8 | 727 | if (cqe_has_vlan(cqe)) { |
e586b3b0 AV |
728 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
729 | be16_to_cpu(cqe->vlan_info)); | |
f24686e8 GP |
730 | rq->stats.removed_vlan_packets++; |
731 | } | |
12185a9f AV |
732 | |
733 | skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; | |
e20a0db3 SM |
734 | |
735 | mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); | |
736 | skb->protocol = eth_type_trans(skb, netdev); | |
e586b3b0 AV |
737 | } |
738 | ||
461017cb TT |
739 | static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, |
740 | struct mlx5_cqe64 *cqe, | |
741 | u32 cqe_bcnt, | |
742 | struct sk_buff *skb) | |
743 | { | |
744 | rq->stats.packets++; | |
745 | rq->stats.bytes += cqe_bcnt; | |
746 | mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); | |
461017cb TT |
747 | } |
748 | ||
31391048 | 749 | static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) |
35b510e2 SM |
750 | { |
751 | struct mlx5_wq_cyc *wq = &sq->wq; | |
752 | struct mlx5e_tx_wqe *wqe; | |
ddf385e3 | 753 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc - 1); /* last pi */ |
35b510e2 SM |
754 | |
755 | wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
756 | ||
864b2d71 | 757 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); |
35b510e2 SM |
758 | } |
759 | ||
a67edbf4 | 760 | static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, |
b5503b99 | 761 | struct mlx5e_dma_info *di, |
d8bec2b2 | 762 | const struct xdp_buff *xdp) |
b5503b99 | 763 | { |
31391048 | 764 | struct mlx5e_xdpsq *sq = &rq->xdpsq; |
b5503b99 | 765 | struct mlx5_wq_cyc *wq = &sq->wq; |
ddf385e3 | 766 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
b5503b99 | 767 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
b5503b99 SM |
768 | |
769 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
770 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
771 | struct mlx5_wqe_data_seg *dseg; | |
772 | ||
d8bec2b2 | 773 | ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; |
b70149dd | 774 | dma_addr_t dma_addr = di->addr + data_offset; |
d8bec2b2 MKL |
775 | unsigned int dma_len = xdp->data_end - xdp->data; |
776 | ||
2239185c SM |
777 | prefetchw(wqe); |
778 | ||
472a1e44 | 779 | if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) { |
d8bec2b2 | 780 | rq->stats.xdp_drop++; |
a67edbf4 | 781 | return false; |
d8bec2b2 | 782 | } |
b5503b99 | 783 | |
864b2d71 | 784 | if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { |
31391048 | 785 | if (sq->db.doorbell) { |
35b510e2 SM |
786 | /* SQ is full, ring doorbell */ |
787 | mlx5e_xmit_xdp_doorbell(sq); | |
31391048 | 788 | sq->db.doorbell = false; |
35b510e2 | 789 | } |
b5503b99 | 790 | rq->stats.xdp_tx_full++; |
a67edbf4 | 791 | return false; |
b5503b99 SM |
792 | } |
793 | ||
2239185c | 794 | dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); |
b5503b99 | 795 | |
2239185c | 796 | cseg->fm_ce_se = 0; |
b5503b99 | 797 | |
b70149dd | 798 | dseg = (struct mlx5_wqe_data_seg *)eseg + 1; |
2239185c | 799 | |
b70149dd SM |
800 | /* copy the inline part if required */ |
801 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
802 | memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); | |
803 | eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); | |
804 | dma_len -= MLX5E_XDP_MIN_INLINE; | |
805 | dma_addr += MLX5E_XDP_MIN_INLINE; | |
b70149dd SM |
806 | dseg++; |
807 | } | |
b5503b99 SM |
808 | |
809 | /* write the dma part */ | |
810 | dseg->addr = cpu_to_be64(dma_addr); | |
811 | dseg->byte_count = cpu_to_be32(dma_len); | |
b5503b99 SM |
812 | |
813 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); | |
b5503b99 | 814 | |
accd5883 TT |
815 | /* move page to reference to sq responsibility, |
816 | * and mark so it's not put back in page-cache. | |
817 | */ | |
121e8927 | 818 | __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */ |
31391048 | 819 | sq->db.di[pi] = *di; |
2239185c | 820 | sq->pc++; |
b5503b99 | 821 | |
31391048 | 822 | sq->db.doorbell = true; |
accd5883 | 823 | |
b5503b99 | 824 | rq->stats.xdp_tx++; |
a67edbf4 | 825 | return true; |
b5503b99 SM |
826 | } |
827 | ||
828 | /* returns true if packet was consumed by xdp */ | |
efb6d7a2 TT |
829 | static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq, |
830 | struct mlx5e_dma_info *di, | |
831 | void *va, u16 *rx_headroom, u32 *len) | |
86994156 | 832 | { |
5168d732 | 833 | struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); |
86994156 | 834 | struct xdp_buff xdp; |
b5503b99 | 835 | u32 act; |
5168d732 | 836 | int err; |
b5503b99 SM |
837 | |
838 | if (!prog) | |
839 | return false; | |
86994156 | 840 | |
d8bec2b2 | 841 | xdp.data = va + *rx_headroom; |
de8f3a83 | 842 | xdp_set_data_meta_invalid(&xdp); |
d8bec2b2 MKL |
843 | xdp.data_end = xdp.data + *len; |
844 | xdp.data_hard_start = va; | |
0ddf5432 | 845 | xdp.rxq = &rq->xdp_rxq; |
d8bec2b2 | 846 | |
b5503b99 SM |
847 | act = bpf_prog_run_xdp(prog, &xdp); |
848 | switch (act) { | |
849 | case XDP_PASS: | |
d8bec2b2 MKL |
850 | *rx_headroom = xdp.data - xdp.data_hard_start; |
851 | *len = xdp.data_end - xdp.data; | |
b5503b99 SM |
852 | return false; |
853 | case XDP_TX: | |
a67edbf4 DB |
854 | if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) |
855 | trace_xdp_exception(rq->netdev, prog, act); | |
b5503b99 | 856 | return true; |
5168d732 JDB |
857 | case XDP_REDIRECT: |
858 | /* When XDP enabled then page-refcnt==1 here */ | |
859 | err = xdp_do_redirect(rq->netdev, &xdp, prog); | |
860 | if (!err) { | |
861 | __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); | |
862 | rq->xdpsq.db.redirect_flush = true; | |
863 | mlx5e_page_dma_unmap(rq, di); | |
864 | } | |
865 | return true; | |
b5503b99 SM |
866 | default: |
867 | bpf_warn_invalid_xdp_action(act); | |
868 | case XDP_ABORTED: | |
a67edbf4 | 869 | trace_xdp_exception(rq->netdev, prog, act); |
b5503b99 SM |
870 | case XDP_DROP: |
871 | rq->stats.xdp_drop++; | |
b5503b99 SM |
872 | return true; |
873 | } | |
86994156 RS |
874 | } |
875 | ||
619a8f2a TT |
876 | static inline |
877 | struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, | |
878 | u32 frag_size, u16 headroom, | |
879 | u32 cqe_bcnt) | |
880 | { | |
881 | struct sk_buff *skb = build_skb(va, frag_size); | |
882 | ||
883 | if (unlikely(!skb)) { | |
884 | rq->stats.buff_alloc_err++; | |
885 | return NULL; | |
886 | } | |
887 | ||
888 | skb_reserve(skb, headroom); | |
889 | skb_put(skb, cqe_bcnt); | |
890 | ||
891 | return skb; | |
892 | } | |
893 | ||
8515c581 OG |
894 | static inline |
895 | struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
accd5883 | 896 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) |
2f48af12 | 897 | { |
accd5883 | 898 | struct mlx5e_dma_info *di = &wi->di; |
b45d8b50 | 899 | u16 rx_headroom = rq->buff.headroom; |
1bfecfca | 900 | struct sk_buff *skb; |
b5503b99 | 901 | void *va, *data; |
366cbf2f | 902 | bool consumed; |
78aedd32 | 903 | u32 frag_size; |
2f48af12 | 904 | |
accd5883 | 905 | va = page_address(di->page) + wi->offset; |
d8bec2b2 | 906 | data = va + rx_headroom; |
accd5883 | 907 | frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); |
2f48af12 | 908 | |
bd658dda TT |
909 | dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, |
910 | frag_size, DMA_FROM_DEVICE); | |
03993094 | 911 | prefetchw(va); /* xdp_frame data area */ |
b5503b99 | 912 | prefetch(data); |
accd5883 | 913 | wi->offset += frag_size; |
2f48af12 TT |
914 | |
915 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
916 | rq->stats.wqe_err++; | |
8515c581 | 917 | return NULL; |
2f48af12 TT |
918 | } |
919 | ||
366cbf2f | 920 | rcu_read_lock(); |
d8bec2b2 | 921 | consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); |
366cbf2f DB |
922 | rcu_read_unlock(); |
923 | if (consumed) | |
8515c581 | 924 | return NULL; /* page/packet was consumed by XDP */ |
86994156 | 925 | |
619a8f2a TT |
926 | skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); |
927 | if (unlikely(!skb)) | |
8515c581 | 928 | return NULL; |
1bfecfca | 929 | |
accd5883 | 930 | /* queue up for recycling/reuse */ |
1bfecfca | 931 | page_ref_inc(di->page); |
1bfecfca | 932 | |
8515c581 OG |
933 | return skb; |
934 | } | |
935 | ||
936 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
937 | { | |
accd5883 | 938 | struct mlx5e_wqe_frag_info *wi; |
8515c581 OG |
939 | struct mlx5e_rx_wqe *wqe; |
940 | __be16 wqe_counter_be; | |
941 | struct sk_buff *skb; | |
942 | u16 wqe_counter; | |
943 | u32 cqe_bcnt; | |
944 | ||
945 | wqe_counter_be = cqe->wqe_counter; | |
946 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
947 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 948 | wi = &rq->wqe.frag_info[wqe_counter]; |
8515c581 OG |
949 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
950 | ||
accd5883 TT |
951 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
952 | if (!skb) { | |
953 | /* probably for XDP */ | |
121e8927 | 954 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { |
accd5883 | 955 | wi->di.page = NULL; |
accd5883 TT |
956 | /* do not return page to cache, it will be returned on XDP_TX completion */ |
957 | goto wq_ll_pop; | |
958 | } | |
959 | /* probably an XDP_DROP, save the page-reuse checks */ | |
960 | mlx5e_free_rx_wqe(rq, wi); | |
8515c581 | 961 | goto wq_ll_pop; |
accd5883 | 962 | } |
8515c581 | 963 | |
461017cb | 964 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); |
8515c581 | 965 | napi_gro_receive(rq->cq.napi, skb); |
2f48af12 | 966 | |
accd5883 | 967 | mlx5e_free_rx_wqe_reuse(rq, wi); |
2f48af12 TT |
968 | wq_ll_pop: |
969 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
970 | &wqe->next.next_wqe_index); | |
971 | } | |
972 | ||
e80541ec | 973 | #ifdef CONFIG_MLX5_ESWITCH |
f5f82476 OG |
974 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
975 | { | |
976 | struct net_device *netdev = rq->netdev; | |
977 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1d447a39 SM |
978 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
979 | struct mlx5_eswitch_rep *rep = rpriv->rep; | |
accd5883 | 980 | struct mlx5e_wqe_frag_info *wi; |
f5f82476 OG |
981 | struct mlx5e_rx_wqe *wqe; |
982 | struct sk_buff *skb; | |
983 | __be16 wqe_counter_be; | |
984 | u16 wqe_counter; | |
985 | u32 cqe_bcnt; | |
986 | ||
987 | wqe_counter_be = cqe->wqe_counter; | |
988 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
989 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 990 | wi = &rq->wqe.frag_info[wqe_counter]; |
f5f82476 OG |
991 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
992 | ||
accd5883 TT |
993 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
994 | if (!skb) { | |
121e8927 | 995 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { |
accd5883 | 996 | wi->di.page = NULL; |
accd5883 TT |
997 | /* do not return page to cache, it will be returned on XDP_TX completion */ |
998 | goto wq_ll_pop; | |
999 | } | |
1000 | /* probably an XDP_DROP, save the page-reuse checks */ | |
1001 | mlx5e_free_rx_wqe(rq, wi); | |
f5f82476 | 1002 | goto wq_ll_pop; |
accd5883 | 1003 | } |
f5f82476 OG |
1004 | |
1005 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
1006 | ||
1007 | if (rep->vlan && skb_vlan_tag_present(skb)) | |
1008 | skb_vlan_pop(skb); | |
1009 | ||
1010 | napi_gro_receive(rq->cq.napi, skb); | |
1011 | ||
accd5883 | 1012 | mlx5e_free_rx_wqe_reuse(rq, wi); |
f5f82476 OG |
1013 | wq_ll_pop: |
1014 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
1015 | &wqe->next.next_wqe_index); | |
1016 | } | |
e80541ec | 1017 | #endif |
f5f82476 | 1018 | |
619a8f2a TT |
1019 | struct sk_buff * |
1020 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
1021 | u16 cqe_bcnt, u32 head_offset, u32 page_idx) | |
bc77b240 | 1022 | { |
bc77b240 | 1023 | u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); |
9f9e9cd5 | 1024 | struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; |
bc77b240 | 1025 | u32 frag_offset = head_offset + headlen; |
9f9e9cd5 TT |
1026 | u32 byte_cnt = cqe_bcnt - headlen; |
1027 | struct mlx5e_dma_info *head_di = di; | |
619a8f2a TT |
1028 | struct sk_buff *skb; |
1029 | ||
1030 | skb = napi_alloc_skb(rq->cq.napi, | |
1031 | ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long))); | |
1032 | if (unlikely(!skb)) { | |
1033 | rq->stats.buff_alloc_err++; | |
1034 | return NULL; | |
1035 | } | |
1036 | ||
1037 | prefetchw(skb->data); | |
bc77b240 | 1038 | |
bc77b240 | 1039 | if (unlikely(frag_offset >= PAGE_SIZE)) { |
9f9e9cd5 | 1040 | di++; |
bc77b240 TT |
1041 | frag_offset -= PAGE_SIZE; |
1042 | } | |
bc77b240 TT |
1043 | |
1044 | while (byte_cnt) { | |
1045 | u32 pg_consumed_bytes = | |
1046 | min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); | |
1047 | ||
9f9e9cd5 | 1048 | mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset, |
7e426671 | 1049 | pg_consumed_bytes); |
bc77b240 TT |
1050 | byte_cnt -= pg_consumed_bytes; |
1051 | frag_offset = 0; | |
9f9e9cd5 | 1052 | di++; |
bc77b240 TT |
1053 | } |
1054 | /* copy header */ | |
9f9e9cd5 | 1055 | mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di, |
7e426671 | 1056 | head_offset, headlen); |
bc77b240 TT |
1057 | /* skb linear part was allocated with headlen and aligned to long */ |
1058 | skb->tail += headlen; | |
1059 | skb->len += headlen; | |
619a8f2a TT |
1060 | |
1061 | return skb; | |
1062 | } | |
1063 | ||
1064 | struct sk_buff * | |
1065 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
1066 | u16 cqe_bcnt, u32 head_offset, u32 page_idx) | |
1067 | { | |
1068 | struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; | |
1069 | u16 rx_headroom = rq->buff.headroom; | |
22f45398 | 1070 | u32 cqe_bcnt32 = cqe_bcnt; |
619a8f2a TT |
1071 | struct sk_buff *skb; |
1072 | void *va, *data; | |
1073 | u32 frag_size; | |
22f45398 | 1074 | bool consumed; |
619a8f2a TT |
1075 | |
1076 | va = page_address(di->page) + head_offset; | |
1077 | data = va + rx_headroom; | |
22f45398 | 1078 | frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32); |
619a8f2a TT |
1079 | |
1080 | dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset, | |
1081 | frag_size, DMA_FROM_DEVICE); | |
1082 | prefetch(data); | |
22f45398 TT |
1083 | |
1084 | rcu_read_lock(); | |
1085 | consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32); | |
1086 | rcu_read_unlock(); | |
1087 | if (consumed) { | |
1088 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) | |
1089 | __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */ | |
1090 | return NULL; /* page/packet was consumed by XDP */ | |
1091 | } | |
1092 | ||
1093 | skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32); | |
619a8f2a TT |
1094 | if (unlikely(!skb)) |
1095 | return NULL; | |
1096 | ||
1097 | /* queue up for recycling/reuse */ | |
9f9e9cd5 | 1098 | page_ref_inc(di->page); |
619a8f2a TT |
1099 | |
1100 | return skb; | |
bc77b240 TT |
1101 | } |
1102 | ||
461017cb TT |
1103 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
1104 | { | |
1105 | u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); | |
461017cb | 1106 | u16 wqe_id = be16_to_cpu(cqe->wqe_id); |
21c59685 | 1107 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; |
619a8f2a TT |
1108 | u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); |
1109 | u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; | |
1110 | u32 head_offset = wqe_offset & (PAGE_SIZE - 1); | |
1111 | u32 page_idx = wqe_offset >> PAGE_SHIFT; | |
1112 | struct mlx5e_rx_wqe *wqe; | |
461017cb | 1113 | struct sk_buff *skb; |
461017cb | 1114 | u16 cqe_bcnt; |
461017cb TT |
1115 | |
1116 | wi->consumed_strides += cstrides; | |
1117 | ||
1118 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
1119 | rq->stats.wqe_err++; | |
1120 | goto mpwrq_cqe_out; | |
1121 | } | |
1122 | ||
1123 | if (unlikely(mpwrq_is_filler_cqe(cqe))) { | |
1124 | rq->stats.mpwqe_filler++; | |
1125 | goto mpwrq_cqe_out; | |
1126 | } | |
1127 | ||
461017cb | 1128 | cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); |
461017cb | 1129 | |
619a8f2a TT |
1130 | skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset, |
1131 | page_idx); | |
22f45398 | 1132 | if (!skb) |
619a8f2a TT |
1133 | goto mpwrq_cqe_out; |
1134 | ||
461017cb | 1135 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); |
8515c581 | 1136 | napi_gro_receive(rq->cq.napi, skb); |
461017cb TT |
1137 | |
1138 | mpwrq_cqe_out: | |
b45d8b50 | 1139 | if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) |
461017cb TT |
1140 | return; |
1141 | ||
619a8f2a | 1142 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); |
7e426671 | 1143 | mlx5e_free_rx_mpwqe(rq, wi); |
461017cb TT |
1144 | mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); |
1145 | } | |
1146 | ||
44fb6fbb | 1147 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) |
e586b3b0 | 1148 | { |
e3391054 | 1149 | struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); |
4b7dfc99 TT |
1150 | struct mlx5e_xdpsq *xdpsq; |
1151 | struct mlx5_cqe64 *cqe; | |
7219ab34 | 1152 | int work_done = 0; |
e586b3b0 | 1153 | |
0e5c04f6 | 1154 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
6cd392a0 DJ |
1155 | return 0; |
1156 | ||
7219ab34 TT |
1157 | if (cq->decmprs_left) |
1158 | work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); | |
1159 | ||
4b7dfc99 TT |
1160 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
1161 | if (!cqe) | |
1162 | return 0; | |
e586b3b0 | 1163 | |
4b7dfc99 | 1164 | xdpsq = &rq->xdpsq; |
e586b3b0 | 1165 | |
4b7dfc99 | 1166 | do { |
7219ab34 TT |
1167 | if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { |
1168 | work_done += | |
1169 | mlx5e_decompress_cqes_start(rq, cq, | |
1170 | budget - work_done); | |
1171 | continue; | |
1172 | } | |
1173 | ||
a1f5a1a8 AS |
1174 | mlx5_cqwq_pop(&cq->wq); |
1175 | ||
2f48af12 | 1176 | rq->handle_rx_cqe(rq, cqe); |
4b7dfc99 | 1177 | } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); |
e586b3b0 | 1178 | |
31391048 | 1179 | if (xdpsq->db.doorbell) { |
31871f87 | 1180 | mlx5e_xmit_xdp_doorbell(xdpsq); |
31391048 | 1181 | xdpsq->db.doorbell = false; |
35b510e2 SM |
1182 | } |
1183 | ||
5168d732 JDB |
1184 | if (xdpsq->db.redirect_flush) { |
1185 | xdp_do_flush_map(); | |
1186 | xdpsq->db.redirect_flush = false; | |
1187 | } | |
1188 | ||
e586b3b0 AV |
1189 | mlx5_cqwq_update_db_record(&cq->wq); |
1190 | ||
1191 | /* ensure cq space is freed before enabling more cqes */ | |
1192 | wmb(); | |
1193 | ||
44fb6fbb | 1194 | return work_done; |
e586b3b0 | 1195 | } |
1c4bf940 SM |
1196 | |
1197 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) | |
1198 | { | |
31391048 | 1199 | struct mlx5e_xdpsq *sq; |
4b7dfc99 | 1200 | struct mlx5_cqe64 *cqe; |
31871f87 | 1201 | struct mlx5e_rq *rq; |
1c4bf940 SM |
1202 | u16 sqcc; |
1203 | int i; | |
1204 | ||
31391048 | 1205 | sq = container_of(cq, struct mlx5e_xdpsq, cq); |
1c4bf940 | 1206 | |
0e5c04f6 | 1207 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
1c4bf940 SM |
1208 | return false; |
1209 | ||
4b7dfc99 TT |
1210 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
1211 | if (!cqe) | |
1212 | return false; | |
1213 | ||
31871f87 SM |
1214 | rq = container_of(sq, struct mlx5e_rq, xdpsq); |
1215 | ||
1c4bf940 SM |
1216 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), |
1217 | * otherwise a cq overrun may occur | |
1218 | */ | |
1219 | sqcc = sq->cc; | |
1220 | ||
4b7dfc99 TT |
1221 | i = 0; |
1222 | do { | |
1c4bf940 SM |
1223 | u16 wqe_counter; |
1224 | bool last_wqe; | |
1225 | ||
1c4bf940 SM |
1226 | mlx5_cqwq_pop(&cq->wq); |
1227 | ||
1228 | wqe_counter = be16_to_cpu(cqe->wqe_counter); | |
1229 | ||
1230 | do { | |
1c4bf940 SM |
1231 | struct mlx5e_dma_info *di; |
1232 | u16 ci; | |
1233 | ||
1234 | last_wqe = (sqcc == wqe_counter); | |
1235 | ||
ddf385e3 | 1236 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc); |
31391048 | 1237 | di = &sq->db.di[ci]; |
1c4bf940 | 1238 | |
2239185c | 1239 | sqcc++; |
1c4bf940 | 1240 | /* Recycle RX page */ |
31871f87 | 1241 | mlx5e_page_release(rq, di, true); |
1c4bf940 | 1242 | } while (!last_wqe); |
4b7dfc99 | 1243 | } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); |
1c4bf940 SM |
1244 | |
1245 | mlx5_cqwq_update_db_record(&cq->wq); | |
1246 | ||
1247 | /* ensure cq space is freed before enabling more cqes */ | |
1248 | wmb(); | |
1249 | ||
1250 | sq->cc = sqcc; | |
1251 | return (i == MLX5E_TX_CQ_POLL_BUDGET); | |
1252 | } | |
1253 | ||
31391048 | 1254 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) |
1c4bf940 | 1255 | { |
31871f87 | 1256 | struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); |
1c4bf940 SM |
1257 | struct mlx5e_dma_info *di; |
1258 | u16 ci; | |
1259 | ||
1260 | while (sq->cc != sq->pc) { | |
ddf385e3 | 1261 | ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sq->cc); |
31391048 | 1262 | di = &sq->db.di[ci]; |
2239185c | 1263 | sq->cc++; |
1c4bf940 | 1264 | |
31871f87 | 1265 | mlx5e_page_release(rq, di, false); |
1c4bf940 SM |
1266 | } |
1267 | } | |
9d6bd752 SM |
1268 | |
1269 | #ifdef CONFIG_MLX5_CORE_IPOIB | |
1270 | ||
1271 | #define MLX5_IB_GRH_DGID_OFFSET 24 | |
9d6bd752 SM |
1272 | #define MLX5_GID_SIZE 16 |
1273 | ||
1274 | static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, | |
1275 | struct mlx5_cqe64 *cqe, | |
1276 | u32 cqe_bcnt, | |
1277 | struct sk_buff *skb) | |
1278 | { | |
36e564b7 | 1279 | struct hwtstamp_config *tstamp; |
7e7f4780 | 1280 | struct net_device *netdev; |
36e564b7 | 1281 | struct mlx5e_priv *priv; |
b57fe691 | 1282 | char *pseudo_header; |
7e7f4780 | 1283 | u32 qpn; |
9d6bd752 SM |
1284 | u8 *dgid; |
1285 | u8 g; | |
1286 | ||
7e7f4780 AV |
1287 | qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; |
1288 | netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); | |
1289 | ||
1290 | /* No mapping present, cannot process SKB. This might happen if a child | |
1291 | * interface is going down while having unprocessed CQEs on parent RQ | |
1292 | */ | |
1293 | if (unlikely(!netdev)) { | |
1294 | /* TODO: add drop counters support */ | |
1295 | skb->dev = NULL; | |
1296 | pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); | |
1297 | return; | |
1298 | } | |
1299 | ||
36e564b7 FD |
1300 | priv = mlx5i_epriv(netdev); |
1301 | tstamp = &priv->tstamp; | |
1302 | ||
9d6bd752 SM |
1303 | g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; |
1304 | dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; | |
1305 | if ((!g) || dgid[0] != 0xff) | |
1306 | skb->pkt_type = PACKET_HOST; | |
1307 | else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) | |
1308 | skb->pkt_type = PACKET_BROADCAST; | |
1309 | else | |
1310 | skb->pkt_type = PACKET_MULTICAST; | |
1311 | ||
1312 | /* TODO: IB/ipoib: Allow mcast packets from other VFs | |
1313 | * 68996a6e760e5c74654723eeb57bf65628ae87f4 | |
1314 | */ | |
1315 | ||
1316 | skb_pull(skb, MLX5_IB_GRH_BYTES); | |
1317 | ||
1318 | skb->protocol = *((__be16 *)(skb->data)); | |
1319 | ||
1320 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1321 | skb->csum = csum_unfold((__force __sum16)cqe->check_sum); | |
1322 | ||
36e564b7 | 1323 | if (unlikely(mlx5e_rx_hw_stamp(tstamp))) |
7c39afb3 FD |
1324 | skb_hwtstamps(skb)->hwtstamp = |
1325 | mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); | |
3844b07e | 1326 | |
9d6bd752 SM |
1327 | skb_record_rx_queue(skb, rq->ix); |
1328 | ||
1329 | if (likely(netdev->features & NETIF_F_RXHASH)) | |
1330 | mlx5e_skb_set_hash(cqe, skb); | |
1331 | ||
b57fe691 ES |
1332 | /* 20 bytes of ipoib header and 4 for encap existing */ |
1333 | pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); | |
1334 | memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); | |
9d6bd752 | 1335 | skb_reset_mac_header(skb); |
b57fe691 | 1336 | skb_pull(skb, MLX5_IPOIB_HARD_LEN); |
9d6bd752 SM |
1337 | |
1338 | skb->dev = netdev; | |
1339 | ||
1340 | rq->stats.csum_complete++; | |
1341 | rq->stats.packets++; | |
1342 | rq->stats.bytes += cqe_bcnt; | |
1343 | } | |
1344 | ||
1345 | void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
1346 | { | |
accd5883 | 1347 | struct mlx5e_wqe_frag_info *wi; |
9d6bd752 SM |
1348 | struct mlx5e_rx_wqe *wqe; |
1349 | __be16 wqe_counter_be; | |
1350 | struct sk_buff *skb; | |
1351 | u16 wqe_counter; | |
1352 | u32 cqe_bcnt; | |
1353 | ||
1354 | wqe_counter_be = cqe->wqe_counter; | |
1355 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
1356 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 1357 | wi = &rq->wqe.frag_info[wqe_counter]; |
9d6bd752 SM |
1358 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
1359 | ||
accd5883 | 1360 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
9d6bd752 | 1361 | if (!skb) |
accd5883 | 1362 | goto wq_free_wqe; |
9d6bd752 SM |
1363 | |
1364 | mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
7e7f4780 AV |
1365 | if (unlikely(!skb->dev)) { |
1366 | dev_kfree_skb_any(skb); | |
1367 | goto wq_free_wqe; | |
1368 | } | |
9d6bd752 SM |
1369 | napi_gro_receive(rq->cq.napi, skb); |
1370 | ||
accd5883 TT |
1371 | wq_free_wqe: |
1372 | mlx5e_free_rx_wqe_reuse(rq, wi); | |
9d6bd752 SM |
1373 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, |
1374 | &wqe->next.next_wqe_index); | |
1375 | } | |
1376 | ||
1377 | #endif /* CONFIG_MLX5_CORE_IPOIB */ | |
899a59d3 IT |
1378 | |
1379 | #ifdef CONFIG_MLX5_EN_IPSEC | |
1380 | ||
1381 | void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
1382 | { | |
1383 | struct mlx5e_wqe_frag_info *wi; | |
1384 | struct mlx5e_rx_wqe *wqe; | |
1385 | __be16 wqe_counter_be; | |
1386 | struct sk_buff *skb; | |
1387 | u16 wqe_counter; | |
1388 | u32 cqe_bcnt; | |
1389 | ||
1390 | wqe_counter_be = cqe->wqe_counter; | |
1391 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
1392 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
1393 | wi = &rq->wqe.frag_info[wqe_counter]; | |
1394 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); | |
1395 | ||
1396 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); | |
1397 | if (unlikely(!skb)) { | |
1398 | /* a DROP, save the page-reuse checks */ | |
1399 | mlx5e_free_rx_wqe(rq, wi); | |
1400 | goto wq_ll_pop; | |
1401 | } | |
1402 | skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); | |
1403 | if (unlikely(!skb)) { | |
1404 | mlx5e_free_rx_wqe(rq, wi); | |
1405 | goto wq_ll_pop; | |
1406 | } | |
1407 | ||
1408 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
1409 | napi_gro_receive(rq->cq.napi, skb); | |
1410 | ||
1411 | mlx5e_free_rx_wqe_reuse(rq, wi); | |
1412 | wq_ll_pop: | |
1413 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
1414 | &wqe->next.next_wqe_index); | |
1415 | } | |
1416 | ||
1417 | #endif /* CONFIG_MLX5_EN_IPSEC */ |