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e586b3b0 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
18bcf742 | 33 | #include <linux/prefetch.h> |
e586b3b0 AV |
34 | #include <linux/ip.h> |
35 | #include <linux/ipv6.h> | |
36 | #include <linux/tcp.h> | |
a67edbf4 | 37 | #include <linux/bpf_trace.h> |
7ae92ae5 | 38 | #include <net/busy_poll.h> |
8babd44d | 39 | #include <net/ip6_checksum.h> |
60bbf7ee | 40 | #include <net/page_pool.h> |
e586b3b0 | 41 | #include "en.h" |
12185a9f | 42 | #include "en_tc.h" |
f5f82476 | 43 | #include "eswitch.h" |
1d447a39 | 44 | #include "en_rep.h" |
4301ba7b | 45 | #include "ipoib/ipoib.h" |
899a59d3 | 46 | #include "en_accel/ipsec_rxtx.h" |
7c39afb3 | 47 | #include "lib/clock.h" |
e586b3b0 | 48 | |
7c39afb3 | 49 | static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config) |
ef9814de | 50 | { |
7c39afb3 | 51 | return config->rx_filter == HWTSTAMP_FILTER_ALL; |
ef9814de EBE |
52 | } |
53 | ||
7219ab34 TT |
54 | static inline void mlx5e_read_cqe_slot(struct mlx5e_cq *cq, u32 cqcc, |
55 | void *data) | |
56 | { | |
388ca8be | 57 | u32 ci = cqcc & cq->wq.fbc.sz_m1; |
7219ab34 TT |
58 | |
59 | memcpy(data, mlx5_cqwq_get_wqe(&cq->wq, ci), sizeof(struct mlx5_cqe64)); | |
60 | } | |
61 | ||
62 | static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq, | |
63 | struct mlx5e_cq *cq, u32 cqcc) | |
64 | { | |
65 | mlx5e_read_cqe_slot(cq, cqcc, &cq->title); | |
66 | cq->decmprs_left = be32_to_cpu(cq->title.byte_cnt); | |
67 | cq->decmprs_wqe_counter = be16_to_cpu(cq->title.wqe_counter); | |
68 | rq->stats.cqe_compress_blks++; | |
69 | } | |
70 | ||
71 | static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq *cq, u32 cqcc) | |
72 | { | |
73 | mlx5e_read_cqe_slot(cq, cqcc, cq->mini_arr); | |
74 | cq->mini_arr_idx = 0; | |
75 | } | |
76 | ||
77 | static inline void mlx5e_cqes_update_owner(struct mlx5e_cq *cq, u32 cqcc, int n) | |
78 | { | |
388ca8be YC |
79 | struct mlx5_frag_buf_ctrl *fbc = &cq->wq.fbc; |
80 | u8 op_own = (cqcc >> fbc->log_sz) & 1; | |
81 | u32 wq_sz = 1 << fbc->log_sz; | |
82 | u32 ci = cqcc & fbc->sz_m1; | |
7219ab34 TT |
83 | u32 ci_top = min_t(u32, wq_sz, ci + n); |
84 | ||
85 | for (; ci < ci_top; ci++, n--) { | |
86 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); | |
87 | ||
88 | cqe->op_own = op_own; | |
89 | } | |
90 | ||
91 | if (unlikely(ci == wq_sz)) { | |
92 | op_own = !op_own; | |
93 | for (ci = 0; ci < n; ci++) { | |
94 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, ci); | |
95 | ||
96 | cqe->op_own = op_own; | |
97 | } | |
98 | } | |
99 | } | |
100 | ||
101 | static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq, | |
102 | struct mlx5e_cq *cq, u32 cqcc) | |
103 | { | |
7219ab34 TT |
104 | cq->title.byte_cnt = cq->mini_arr[cq->mini_arr_idx].byte_cnt; |
105 | cq->title.check_sum = cq->mini_arr[cq->mini_arr_idx].checksum; | |
106 | cq->title.op_own &= 0xf0; | |
388ca8be | 107 | cq->title.op_own |= 0x01 & (cqcc >> cq->wq.fbc.log_sz); |
7219ab34 TT |
108 | cq->title.wqe_counter = cpu_to_be16(cq->decmprs_wqe_counter); |
109 | ||
36154be4 TT |
110 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
111 | cq->decmprs_wqe_counter += | |
112 | mpwrq_get_cqe_consumed_strides(&cq->title); | |
113 | else | |
114 | cq->decmprs_wqe_counter = | |
115 | (cq->decmprs_wqe_counter + 1) & rq->wq.sz_m1; | |
7219ab34 TT |
116 | } |
117 | ||
118 | static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq, | |
119 | struct mlx5e_cq *cq, u32 cqcc) | |
120 | { | |
121 | mlx5e_decompress_cqe(rq, cq, cqcc); | |
122 | cq->title.rss_hash_type = 0; | |
123 | cq->title.rss_hash_result = 0; | |
124 | } | |
125 | ||
126 | static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq, | |
127 | struct mlx5e_cq *cq, | |
128 | int update_owner_only, | |
129 | int budget_rem) | |
130 | { | |
131 | u32 cqcc = cq->wq.cc + update_owner_only; | |
132 | u32 cqe_count; | |
133 | u32 i; | |
134 | ||
135 | cqe_count = min_t(u32, cq->decmprs_left, budget_rem); | |
136 | ||
137 | for (i = update_owner_only; i < cqe_count; | |
138 | i++, cq->mini_arr_idx++, cqcc++) { | |
d9d9f156 | 139 | if (cq->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE) |
7219ab34 TT |
140 | mlx5e_read_mini_arr_slot(cq, cqcc); |
141 | ||
142 | mlx5e_decompress_cqe_no_hash(rq, cq, cqcc); | |
143 | rq->handle_rx_cqe(rq, &cq->title); | |
144 | } | |
145 | mlx5e_cqes_update_owner(cq, cq->wq.cc, cqcc - cq->wq.cc); | |
146 | cq->wq.cc = cqcc; | |
147 | cq->decmprs_left -= cqe_count; | |
148 | rq->stats.cqe_compress_pkts += cqe_count; | |
149 | ||
150 | return cqe_count; | |
151 | } | |
152 | ||
153 | static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq, | |
154 | struct mlx5e_cq *cq, | |
155 | int budget_rem) | |
156 | { | |
157 | mlx5e_read_title_slot(rq, cq, cq->wq.cc); | |
158 | mlx5e_read_mini_arr_slot(cq, cq->wq.cc + 1); | |
159 | mlx5e_decompress_cqe(rq, cq, cq->wq.cc); | |
160 | rq->handle_rx_cqe(rq, &cq->title); | |
161 | cq->mini_arr_idx++; | |
162 | ||
163 | return mlx5e_decompress_cqes_cont(rq, cq, 1, budget_rem) - 1; | |
164 | } | |
165 | ||
1bfecfca SM |
166 | #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT) |
167 | ||
accd5883 TT |
168 | static inline bool mlx5e_page_is_reserved(struct page *page) |
169 | { | |
70871f1e | 170 | return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id(); |
accd5883 TT |
171 | } |
172 | ||
1bfecfca SM |
173 | static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq, |
174 | struct mlx5e_dma_info *dma_info) | |
e586b3b0 | 175 | { |
1bfecfca SM |
176 | struct mlx5e_page_cache *cache = &rq->page_cache; |
177 | u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1); | |
e586b3b0 | 178 | |
1bfecfca SM |
179 | if (tail_next == cache->head) { |
180 | rq->stats.cache_full++; | |
181 | return false; | |
182 | } | |
e586b3b0 | 183 | |
70871f1e TT |
184 | if (unlikely(mlx5e_page_is_reserved(dma_info->page))) { |
185 | rq->stats.cache_waive++; | |
e048fc50 | 186 | return false; |
70871f1e | 187 | } |
e048fc50 | 188 | |
1bfecfca SM |
189 | cache->page_cache[cache->tail] = *dma_info; |
190 | cache->tail = tail_next; | |
191 | return true; | |
192 | } | |
e586b3b0 | 193 | |
1bfecfca SM |
194 | static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq, |
195 | struct mlx5e_dma_info *dma_info) | |
196 | { | |
197 | struct mlx5e_page_cache *cache = &rq->page_cache; | |
198 | ||
199 | if (unlikely(cache->head == cache->tail)) { | |
200 | rq->stats.cache_empty++; | |
201 | return false; | |
202 | } | |
203 | ||
204 | if (page_ref_count(cache->page_cache[cache->head].page) != 1) { | |
205 | rq->stats.cache_busy++; | |
206 | return false; | |
207 | } | |
e586b3b0 | 208 | |
1bfecfca SM |
209 | *dma_info = cache->page_cache[cache->head]; |
210 | cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1); | |
211 | rq->stats.cache_reuse++; | |
e586b3b0 | 212 | |
1bfecfca SM |
213 | dma_sync_single_for_device(rq->pdev, dma_info->addr, |
214 | RQ_PAGE_SIZE(rq), | |
215 | DMA_FROM_DEVICE); | |
216 | return true; | |
217 | } | |
218 | ||
219 | static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq *rq, | |
220 | struct mlx5e_dma_info *dma_info) | |
221 | { | |
1bfecfca SM |
222 | if (mlx5e_rx_cache_get(rq, dma_info)) |
223 | return 0; | |
224 | ||
60bbf7ee | 225 | dma_info->page = page_pool_dev_alloc_pages(rq->page_pool); |
2e50b261 | 226 | if (unlikely(!dma_info->page)) |
1bfecfca SM |
227 | return -ENOMEM; |
228 | ||
2e50b261 | 229 | dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0, |
b5503b99 | 230 | RQ_PAGE_SIZE(rq), rq->buff.map_dir); |
1bfecfca | 231 | if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) { |
2e50b261 IK |
232 | put_page(dma_info->page); |
233 | dma_info->page = NULL; | |
1bfecfca SM |
234 | return -ENOMEM; |
235 | } | |
e586b3b0 AV |
236 | |
237 | return 0; | |
1bfecfca SM |
238 | } |
239 | ||
5168d732 JDB |
240 | static void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, |
241 | struct mlx5e_dma_info *dma_info) | |
242 | { | |
243 | dma_unmap_page(rq->pdev, dma_info->addr, RQ_PAGE_SIZE(rq), | |
244 | rq->buff.map_dir); | |
245 | } | |
246 | ||
1bfecfca SM |
247 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
248 | bool recycle) | |
249 | { | |
60bbf7ee JDB |
250 | if (likely(recycle)) { |
251 | if (mlx5e_rx_cache_put(rq, dma_info)) | |
252 | return; | |
253 | ||
254 | mlx5e_page_dma_unmap(rq, dma_info); | |
255 | page_pool_recycle_direct(rq->page_pool, dma_info->page); | |
256 | } else { | |
257 | mlx5e_page_dma_unmap(rq, dma_info); | |
258 | put_page(dma_info->page); | |
259 | } | |
1bfecfca SM |
260 | } |
261 | ||
accd5883 TT |
262 | static inline bool mlx5e_page_reuse(struct mlx5e_rq *rq, |
263 | struct mlx5e_wqe_frag_info *wi) | |
264 | { | |
265 | return rq->wqe.page_reuse && wi->di.page && | |
266 | (wi->offset + rq->wqe.frag_sz <= RQ_PAGE_SIZE(rq)) && | |
267 | !mlx5e_page_is_reserved(wi->di.page); | |
268 | } | |
269 | ||
7cc6d77b | 270 | static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix) |
1bfecfca | 271 | { |
accd5883 | 272 | struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; |
e586b3b0 | 273 | |
accd5883 TT |
274 | /* check if page exists, hence can be reused */ |
275 | if (!wi->di.page) { | |
276 | if (unlikely(mlx5e_page_alloc_mapped(rq, &wi->di))) | |
277 | return -ENOMEM; | |
278 | wi->offset = 0; | |
279 | } | |
e586b3b0 | 280 | |
b45d8b50 | 281 | wqe->data.addr = cpu_to_be64(wi->di.addr + wi->offset + rq->buff.headroom); |
1bfecfca | 282 | return 0; |
e586b3b0 AV |
283 | } |
284 | ||
accd5883 TT |
285 | static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq, |
286 | struct mlx5e_wqe_frag_info *wi) | |
287 | { | |
288 | mlx5e_page_release(rq, &wi->di, true); | |
289 | wi->di.page = NULL; | |
290 | } | |
291 | ||
292 | static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq *rq, | |
293 | struct mlx5e_wqe_frag_info *wi) | |
294 | { | |
295 | if (mlx5e_page_reuse(rq, wi)) { | |
296 | rq->stats.page_reuse++; | |
297 | return; | |
298 | } | |
299 | ||
300 | mlx5e_free_rx_wqe(rq, wi); | |
301 | } | |
302 | ||
6cd392a0 DJ |
303 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix) |
304 | { | |
accd5883 | 305 | struct mlx5e_wqe_frag_info *wi = &rq->wqe.frag_info[ix]; |
6cd392a0 | 306 | |
accd5883 TT |
307 | if (wi->di.page) |
308 | mlx5e_free_rx_wqe(rq, wi); | |
6cd392a0 DJ |
309 | } |
310 | ||
7e426671 TT |
311 | static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq *rq, |
312 | struct sk_buff *skb, | |
9f9e9cd5 TT |
313 | struct mlx5e_dma_info *di, |
314 | u32 frag_offset, u32 len) | |
bc77b240 | 315 | { |
89e89f7a | 316 | unsigned int truesize = ALIGN(len, BIT(rq->mpwqe.log_stride_sz)); |
bc77b240 | 317 | |
d9d9f156 | 318 | dma_sync_single_for_cpu(rq->pdev, |
9f9e9cd5 | 319 | di->addr + frag_offset, |
bc77b240 | 320 | len, DMA_FROM_DEVICE); |
9f9e9cd5 | 321 | page_ref_inc(di->page); |
bc77b240 | 322 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, |
9f9e9cd5 | 323 | di->page, frag_offset, len, truesize); |
bc77b240 TT |
324 | } |
325 | ||
326 | static inline void | |
7e426671 TT |
327 | mlx5e_copy_skb_header_mpwqe(struct device *pdev, |
328 | struct sk_buff *skb, | |
9f9e9cd5 TT |
329 | struct mlx5e_dma_info *dma_info, |
330 | u32 offset, u32 headlen) | |
bc77b240 TT |
331 | { |
332 | u16 headlen_pg = min_t(u32, headlen, PAGE_SIZE - offset); | |
bc77b240 TT |
333 | unsigned int len; |
334 | ||
335 | /* Aligning len to sizeof(long) optimizes memcpy performance */ | |
336 | len = ALIGN(headlen_pg, sizeof(long)); | |
337 | dma_sync_single_for_cpu(pdev, dma_info->addr + offset, len, | |
338 | DMA_FROM_DEVICE); | |
24fd07ab TT |
339 | skb_copy_to_linear_data(skb, page_address(dma_info->page) + offset, len); |
340 | ||
bc77b240 TT |
341 | if (unlikely(offset + headlen > PAGE_SIZE)) { |
342 | dma_info++; | |
343 | headlen_pg = len; | |
344 | len = ALIGN(headlen - headlen_pg, sizeof(long)); | |
345 | dma_sync_single_for_cpu(pdev, dma_info->addr, len, | |
346 | DMA_FROM_DEVICE); | |
347 | skb_copy_to_linear_data_offset(skb, headlen_pg, | |
348 | page_address(dma_info->page), | |
349 | len); | |
350 | } | |
bc77b240 TT |
351 | } |
352 | ||
18187fb2 | 353 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi) |
bc77b240 | 354 | { |
22f45398 TT |
355 | const bool no_xdp_xmit = |
356 | bitmap_empty(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); | |
22f45398 | 357 | struct mlx5e_dma_info *dma_info = wi->umr.dma_info; |
18187fb2 | 358 | int i; |
bc77b240 | 359 | |
9f9e9cd5 | 360 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++) |
22f45398 TT |
361 | if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap)) |
362 | mlx5e_page_release(rq, &dma_info[i], true); | |
18187fb2 | 363 | } |
bc77b240 | 364 | |
18187fb2 TT |
365 | static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq) |
366 | { | |
367 | struct mlx5_wq_ll *wq = &rq->wq; | |
368 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); | |
7e426671 | 369 | |
18187fb2 TT |
370 | rq->mpwqe.umr_in_progress = false; |
371 | ||
372 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
373 | ||
374 | /* ensure wqes are visible to device before updating doorbell record */ | |
375 | dma_wmb(); | |
376 | ||
377 | mlx5_wq_ll_update_db_record(wq); | |
bc77b240 TT |
378 | } |
379 | ||
ab966d7e TT |
380 | static inline u16 mlx5e_icosq_wrap_cnt(struct mlx5e_icosq *sq) |
381 | { | |
382 | return sq->pc >> MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; | |
383 | } | |
384 | ||
18187fb2 | 385 | static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) |
bc77b240 | 386 | { |
21c59685 | 387 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; |
4c2af5cc | 388 | struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0]; |
18187fb2 TT |
389 | struct mlx5e_icosq *sq = &rq->channel->icosq; |
390 | struct mlx5_wq_cyc *wq = &sq->wq; | |
ea3886ca | 391 | struct mlx5e_umr_wqe *umr_wqe; |
b8a98a4c | 392 | u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1); |
7e426671 | 393 | int err; |
18187fb2 | 394 | u16 pi; |
bc77b240 TT |
395 | int i; |
396 | ||
ea3886ca TT |
397 | /* fill sq edge with nops to avoid wqe wrap around */ |
398 | while ((pi = (sq->pc & wq->sz_m1)) > sq->edge) { | |
399 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
400 | mlx5e_post_nop(wq, sq->sqn, &sq->pc); | |
401 | } | |
402 | ||
403 | umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
ab966d7e TT |
404 | if (unlikely(mlx5e_icosq_wrap_cnt(sq) < 2)) |
405 | memcpy(umr_wqe, &rq->mpwqe.umr_wqe, | |
406 | offsetof(struct mlx5e_umr_wqe, inline_mtts)); | |
407 | ||
4c2af5cc | 408 | for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) { |
a5a0c590 | 409 | err = mlx5e_page_alloc_mapped(rq, dma_info); |
7e426671 | 410 | if (unlikely(err)) |
bc77b240 | 411 | goto err_unmap; |
ea3886ca | 412 | umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR); |
bc77b240 TT |
413 | } |
414 | ||
22f45398 | 415 | bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
bc77b240 | 416 | wi->consumed_strides = 0; |
bc77b240 | 417 | |
18187fb2 TT |
418 | rq->mpwqe.umr_in_progress = true; |
419 | ||
ea3886ca | 420 | umr_wqe->ctrl.opmod_idx_opcode = |
18187fb2 TT |
421 | cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) | |
422 | MLX5_OPCODE_UMR); | |
b8a98a4c | 423 | umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset); |
18187fb2 TT |
424 | |
425 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR; | |
ea3886ca TT |
426 | sq->pc += MLX5E_UMR_WQEBBS; |
427 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &umr_wqe->ctrl); | |
18187fb2 | 428 | |
bc77b240 TT |
429 | return 0; |
430 | ||
431 | err_unmap: | |
432 | while (--i >= 0) { | |
4c2af5cc | 433 | dma_info--; |
4415a031 | 434 | mlx5e_page_release(rq, dma_info, true); |
bc77b240 | 435 | } |
18187fb2 | 436 | rq->stats.buff_alloc_err++; |
bc77b240 | 437 | |
7e426671 | 438 | return err; |
bc77b240 TT |
439 | } |
440 | ||
6cd392a0 DJ |
441 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) |
442 | { | |
21c59685 | 443 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; |
6cd392a0 | 444 | |
7e426671 | 445 | mlx5e_free_rx_mpwqe(rq, wi); |
6cd392a0 DJ |
446 | } |
447 | ||
e586b3b0 AV |
448 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq) |
449 | { | |
450 | struct mlx5_wq_ll *wq = &rq->wq; | |
4b7dfc99 | 451 | int err; |
e586b3b0 | 452 | |
0e5c04f6 | 453 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
e586b3b0 AV |
454 | return false; |
455 | ||
4b7dfc99 TT |
456 | if (mlx5_wq_ll_is_full(wq)) |
457 | return false; | |
458 | ||
4b7dfc99 | 459 | do { |
e586b3b0 AV |
460 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(wq, wq->head); |
461 | ||
7cc6d77b | 462 | err = mlx5e_alloc_rx_wqe(rq, wqe, wq->head); |
54984407 | 463 | if (unlikely(err)) { |
7e426671 | 464 | rq->stats.buff_alloc_err++; |
e586b3b0 | 465 | break; |
54984407 | 466 | } |
e586b3b0 AV |
467 | |
468 | mlx5_wq_ll_push(wq, be16_to_cpu(wqe->next.next_wqe_index)); | |
4b7dfc99 | 469 | } while (!mlx5_wq_ll_is_full(wq)); |
e586b3b0 AV |
470 | |
471 | /* ensure wqes are visible to device before updating doorbell record */ | |
472 | dma_wmb(); | |
473 | ||
474 | mlx5_wq_ll_update_db_record(wq); | |
475 | ||
4b7dfc99 | 476 | return !!err; |
e586b3b0 AV |
477 | } |
478 | ||
7cc6d77b TT |
479 | static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq *cq, |
480 | struct mlx5e_icosq *sq, | |
481 | struct mlx5e_rq *rq, | |
3b56f7b2 | 482 | struct mlx5_cqe64 *cqe) |
7cc6d77b TT |
483 | { |
484 | struct mlx5_wq_cyc *wq = &sq->wq; | |
485 | u16 ci = be16_to_cpu(cqe->wqe_counter) & wq->sz_m1; | |
486 | struct mlx5e_sq_wqe_info *icowi = &sq->db.ico_wqe[ci]; | |
487 | ||
488 | mlx5_cqwq_pop(&cq->wq); | |
7cc6d77b TT |
489 | |
490 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_REQ)) { | |
cd4a87df GP |
491 | netdev_WARN_ONCE(cq->channel->netdev, |
492 | "Bad OP in ICOSQ CQE: 0x%x\n", cqe->op_own); | |
7cc6d77b TT |
493 | return; |
494 | } | |
495 | ||
496 | if (likely(icowi->opcode == MLX5_OPCODE_UMR)) { | |
497 | mlx5e_post_rx_mpwqe(rq); | |
498 | return; | |
499 | } | |
500 | ||
501 | if (unlikely(icowi->opcode != MLX5_OPCODE_NOP)) | |
cd4a87df GP |
502 | netdev_WARN_ONCE(cq->channel->netdev, |
503 | "Bad OPCODE in ICOSQ WQE info: 0x%x\n", icowi->opcode); | |
7cc6d77b TT |
504 | } |
505 | ||
506 | static void mlx5e_poll_ico_cq(struct mlx5e_cq *cq, struct mlx5e_rq *rq) | |
507 | { | |
508 | struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq); | |
509 | struct mlx5_cqe64 *cqe; | |
7cc6d77b | 510 | |
0e5c04f6 | 511 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
7cc6d77b TT |
512 | return; |
513 | ||
514 | cqe = mlx5_cqwq_get_cqe(&cq->wq); | |
515 | if (likely(!cqe)) | |
516 | return; | |
517 | ||
7cc6d77b | 518 | /* by design, there's only a single cqe */ |
3b56f7b2 | 519 | mlx5e_poll_ico_single_cqe(cq, sq, rq, cqe); |
7cc6d77b TT |
520 | |
521 | mlx5_cqwq_update_db_record(&cq->wq); | |
7cc6d77b TT |
522 | } |
523 | ||
524 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq) | |
525 | { | |
526 | struct mlx5_wq_ll *wq = &rq->wq; | |
527 | ||
0e5c04f6 | 528 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
7cc6d77b TT |
529 | return false; |
530 | ||
531 | mlx5e_poll_ico_cq(&rq->channel->icosq.cq, rq); | |
532 | ||
533 | if (mlx5_wq_ll_is_full(wq)) | |
534 | return false; | |
535 | ||
536 | if (!rq->mpwqe.umr_in_progress) | |
537 | mlx5e_alloc_rx_mpwqe(rq, wq->head); | |
538 | ||
e4d86a4a | 539 | return false; |
7cc6d77b TT |
540 | } |
541 | ||
8babd44d GP |
542 | static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp) |
543 | { | |
544 | u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe); | |
545 | u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) || | |
546 | (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA); | |
547 | ||
548 | tcp->check = 0; | |
549 | tcp->psh = get_cqe_lro_tcppsh(cqe); | |
550 | ||
551 | if (tcp_ack) { | |
552 | tcp->ack = 1; | |
553 | tcp->ack_seq = cqe->lro_ack_seq_num; | |
554 | tcp->window = cqe->lro_tcp_win; | |
555 | } | |
556 | } | |
557 | ||
461017cb TT |
558 | static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe, |
559 | u32 cqe_bcnt) | |
e586b3b0 | 560 | { |
cd17d230 | 561 | struct ethhdr *eth = (struct ethhdr *)(skb->data); |
e586b3b0 | 562 | struct tcphdr *tcp; |
cd17d230 | 563 | int network_depth = 0; |
8babd44d | 564 | __wsum check; |
cd17d230 GP |
565 | __be16 proto; |
566 | u16 tot_len; | |
604acb19 | 567 | void *ip_p; |
e586b3b0 | 568 | |
cd17d230 | 569 | proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth); |
e586b3b0 | 570 | |
cd17d230 | 571 | tot_len = cqe_bcnt - network_depth; |
604acb19 | 572 | ip_p = skb->data + network_depth; |
cd17d230 GP |
573 | |
574 | if (proto == htons(ETH_P_IP)) { | |
604acb19 | 575 | struct iphdr *ipv4 = ip_p; |
e586b3b0 | 576 | |
604acb19 TT |
577 | tcp = ip_p + sizeof(struct iphdr); |
578 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4; | |
e586b3b0 | 579 | |
e586b3b0 AV |
580 | ipv4->ttl = cqe->lro_min_ttl; |
581 | ipv4->tot_len = cpu_to_be16(tot_len); | |
582 | ipv4->check = 0; | |
583 | ipv4->check = ip_fast_csum((unsigned char *)ipv4, | |
584 | ipv4->ihl); | |
8babd44d GP |
585 | |
586 | mlx5e_lro_update_tcp_hdr(cqe, tcp); | |
587 | check = csum_partial(tcp, tcp->doff * 4, | |
588 | csum_unfold((__force __sum16)cqe->check_sum)); | |
589 | /* Almost done, don't forget the pseudo header */ | |
590 | tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr, | |
591 | tot_len - sizeof(struct iphdr), | |
592 | IPPROTO_TCP, check); | |
e586b3b0 | 593 | } else { |
8babd44d | 594 | u16 payload_len = tot_len - sizeof(struct ipv6hdr); |
604acb19 TT |
595 | struct ipv6hdr *ipv6 = ip_p; |
596 | ||
597 | tcp = ip_p + sizeof(struct ipv6hdr); | |
598 | skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6; | |
599 | ||
e586b3b0 | 600 | ipv6->hop_limit = cqe->lro_min_ttl; |
8babd44d GP |
601 | ipv6->payload_len = cpu_to_be16(payload_len); |
602 | ||
603 | mlx5e_lro_update_tcp_hdr(cqe, tcp); | |
604 | check = csum_partial(tcp, tcp->doff * 4, | |
605 | csum_unfold((__force __sum16)cqe->check_sum)); | |
606 | /* Almost done, don't forget the pseudo header */ | |
607 | tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len, | |
608 | IPPROTO_TCP, check); | |
604acb19 | 609 | } |
e586b3b0 AV |
610 | } |
611 | ||
612 | static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe, | |
613 | struct sk_buff *skb) | |
614 | { | |
615 | u8 cht = cqe->rss_hash_type; | |
616 | int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 : | |
617 | (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 : | |
618 | PKT_HASH_TYPE_NONE; | |
619 | skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht); | |
620 | } | |
621 | ||
f938daee | 622 | static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth) |
bbceefce AS |
623 | { |
624 | __be16 ethertype = ((struct ethhdr *)skb->data)->h_proto; | |
625 | ||
f938daee | 626 | ethertype = __vlan_get_protocol(skb, ethertype, network_depth); |
bbceefce AS |
627 | return (ethertype == htons(ETH_P_IP) || ethertype == htons(ETH_P_IPV6)); |
628 | } | |
629 | ||
630 | static inline void mlx5e_handle_csum(struct net_device *netdev, | |
631 | struct mlx5_cqe64 *cqe, | |
632 | struct mlx5e_rq *rq, | |
5f6d12d1 MF |
633 | struct sk_buff *skb, |
634 | bool lro) | |
bbceefce | 635 | { |
f938daee GP |
636 | int network_depth = 0; |
637 | ||
bbceefce AS |
638 | if (unlikely(!(netdev->features & NETIF_F_RXCSUM))) |
639 | goto csum_none; | |
640 | ||
5f6d12d1 | 641 | if (lro) { |
bbceefce | 642 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
603e1f5b | 643 | rq->stats.csum_unnecessary++; |
1b223dd3 SM |
644 | return; |
645 | } | |
646 | ||
63a612f9 | 647 | if (likely(is_last_ethertype_ip(skb, &network_depth))) { |
bbceefce | 648 | skb->ip_summed = CHECKSUM_COMPLETE; |
ecf842f6 | 649 | skb->csum = csum_unfold((__force __sum16)cqe->check_sum); |
f938daee GP |
650 | if (network_depth > ETH_HLEN) |
651 | /* CQE csum is calculated from the IP header and does | |
652 | * not cover VLAN headers (if present). This will add | |
653 | * the checksum manually. | |
654 | */ | |
655 | skb->csum = csum_partial(skb->data + ETH_HLEN, | |
656 | network_depth - ETH_HLEN, | |
657 | skb->csum); | |
bfe6d8d1 | 658 | rq->stats.csum_complete++; |
1b223dd3 | 659 | return; |
bbceefce AS |
660 | } |
661 | ||
1b223dd3 SM |
662 | if (likely((cqe->hds_ip_ext & CQE_L3_OK) && |
663 | (cqe->hds_ip_ext & CQE_L4_OK))) { | |
664 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
665 | if (cqe_is_tunneled(cqe)) { | |
666 | skb->csum_level = 1; | |
667 | skb->encapsulation = 1; | |
bfe6d8d1 | 668 | rq->stats.csum_unnecessary_inner++; |
603e1f5b | 669 | return; |
1b223dd3 | 670 | } |
603e1f5b | 671 | rq->stats.csum_unnecessary++; |
1b223dd3 SM |
672 | return; |
673 | } | |
bbceefce AS |
674 | csum_none: |
675 | skb->ip_summed = CHECKSUM_NONE; | |
676 | rq->stats.csum_none++; | |
677 | } | |
678 | ||
e586b3b0 | 679 | static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe, |
461017cb | 680 | u32 cqe_bcnt, |
e586b3b0 AV |
681 | struct mlx5e_rq *rq, |
682 | struct sk_buff *skb) | |
683 | { | |
bd206fd5 | 684 | u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24; |
e586b3b0 | 685 | struct net_device *netdev = rq->netdev; |
e586b3b0 | 686 | |
f938daee | 687 | skb->mac_len = ETH_HLEN; |
e586b3b0 | 688 | if (lro_num_seg > 1) { |
461017cb | 689 | mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt); |
d9a40271 | 690 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg); |
8ab7e2ae GP |
691 | /* Subtract one since we already counted this as one |
692 | * "regular" packet in mlx5e_complete_rx_cqe() | |
693 | */ | |
694 | rq->stats.packets += lro_num_seg - 1; | |
e586b3b0 AV |
695 | rq->stats.lro_packets++; |
696 | rq->stats.lro_bytes += cqe_bcnt; | |
697 | } | |
698 | ||
7c39afb3 FD |
699 | if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp))) |
700 | skb_hwtstamps(skb)->hwtstamp = | |
701 | mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); | |
ef9814de | 702 | |
e586b3b0 AV |
703 | skb_record_rx_queue(skb, rq->ix); |
704 | ||
705 | if (likely(netdev->features & NETIF_F_RXHASH)) | |
706 | mlx5e_skb_set_hash(cqe, skb); | |
707 | ||
f24686e8 | 708 | if (cqe_has_vlan(cqe)) { |
e586b3b0 AV |
709 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), |
710 | be16_to_cpu(cqe->vlan_info)); | |
f24686e8 GP |
711 | rq->stats.removed_vlan_packets++; |
712 | } | |
12185a9f AV |
713 | |
714 | skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK; | |
e20a0db3 SM |
715 | |
716 | mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg); | |
717 | skb->protocol = eth_type_trans(skb, netdev); | |
e586b3b0 AV |
718 | } |
719 | ||
461017cb TT |
720 | static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq, |
721 | struct mlx5_cqe64 *cqe, | |
722 | u32 cqe_bcnt, | |
723 | struct sk_buff *skb) | |
724 | { | |
725 | rq->stats.packets++; | |
726 | rq->stats.bytes += cqe_bcnt; | |
727 | mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb); | |
461017cb TT |
728 | } |
729 | ||
31391048 | 730 | static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq *sq) |
35b510e2 SM |
731 | { |
732 | struct mlx5_wq_cyc *wq = &sq->wq; | |
733 | struct mlx5e_tx_wqe *wqe; | |
2239185c | 734 | u16 pi = (sq->pc - 1) & wq->sz_m1; /* last pi */ |
35b510e2 SM |
735 | |
736 | wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
737 | ||
864b2d71 | 738 | mlx5e_notify_hw(wq, sq->pc, sq->uar_map, &wqe->ctrl); |
35b510e2 SM |
739 | } |
740 | ||
a67edbf4 | 741 | static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq *rq, |
b5503b99 | 742 | struct mlx5e_dma_info *di, |
d8bec2b2 | 743 | const struct xdp_buff *xdp) |
b5503b99 | 744 | { |
31391048 | 745 | struct mlx5e_xdpsq *sq = &rq->xdpsq; |
b5503b99 | 746 | struct mlx5_wq_cyc *wq = &sq->wq; |
31391048 | 747 | u16 pi = sq->pc & wq->sz_m1; |
b5503b99 | 748 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
b5503b99 SM |
749 | |
750 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
751 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
752 | struct mlx5_wqe_data_seg *dseg; | |
753 | ||
d8bec2b2 | 754 | ptrdiff_t data_offset = xdp->data - xdp->data_hard_start; |
b70149dd | 755 | dma_addr_t dma_addr = di->addr + data_offset; |
d8bec2b2 MKL |
756 | unsigned int dma_len = xdp->data_end - xdp->data; |
757 | ||
2239185c SM |
758 | prefetchw(wqe); |
759 | ||
472a1e44 | 760 | if (unlikely(dma_len < MLX5E_XDP_MIN_INLINE || rq->hw_mtu < dma_len)) { |
d8bec2b2 | 761 | rq->stats.xdp_drop++; |
a67edbf4 | 762 | return false; |
d8bec2b2 | 763 | } |
b5503b99 | 764 | |
864b2d71 | 765 | if (unlikely(!mlx5e_wqc_has_room_for(wq, sq->cc, sq->pc, 1))) { |
31391048 | 766 | if (sq->db.doorbell) { |
35b510e2 SM |
767 | /* SQ is full, ring doorbell */ |
768 | mlx5e_xmit_xdp_doorbell(sq); | |
31391048 | 769 | sq->db.doorbell = false; |
35b510e2 | 770 | } |
b5503b99 | 771 | rq->stats.xdp_tx_full++; |
a67edbf4 | 772 | return false; |
b5503b99 SM |
773 | } |
774 | ||
2239185c | 775 | dma_sync_single_for_device(sq->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE); |
b5503b99 | 776 | |
2239185c | 777 | cseg->fm_ce_se = 0; |
b5503b99 | 778 | |
b70149dd | 779 | dseg = (struct mlx5_wqe_data_seg *)eseg + 1; |
2239185c | 780 | |
b70149dd SM |
781 | /* copy the inline part if required */ |
782 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
783 | memcpy(eseg->inline_hdr.start, xdp->data, MLX5E_XDP_MIN_INLINE); | |
784 | eseg->inline_hdr.sz = cpu_to_be16(MLX5E_XDP_MIN_INLINE); | |
785 | dma_len -= MLX5E_XDP_MIN_INLINE; | |
786 | dma_addr += MLX5E_XDP_MIN_INLINE; | |
b70149dd SM |
787 | dseg++; |
788 | } | |
b5503b99 SM |
789 | |
790 | /* write the dma part */ | |
791 | dseg->addr = cpu_to_be64(dma_addr); | |
792 | dseg->byte_count = cpu_to_be32(dma_len); | |
b5503b99 SM |
793 | |
794 | cseg->opmod_idx_opcode = cpu_to_be32((sq->pc << 8) | MLX5_OPCODE_SEND); | |
b5503b99 | 795 | |
accd5883 TT |
796 | /* move page to reference to sq responsibility, |
797 | * and mark so it's not put back in page-cache. | |
798 | */ | |
121e8927 | 799 | __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); /* non-atomic */ |
31391048 | 800 | sq->db.di[pi] = *di; |
2239185c | 801 | sq->pc++; |
b5503b99 | 802 | |
31391048 | 803 | sq->db.doorbell = true; |
accd5883 | 804 | |
b5503b99 | 805 | rq->stats.xdp_tx++; |
a67edbf4 | 806 | return true; |
b5503b99 SM |
807 | } |
808 | ||
809 | /* returns true if packet was consumed by xdp */ | |
efb6d7a2 TT |
810 | static inline bool mlx5e_xdp_handle(struct mlx5e_rq *rq, |
811 | struct mlx5e_dma_info *di, | |
812 | void *va, u16 *rx_headroom, u32 *len) | |
86994156 | 813 | { |
5168d732 | 814 | struct bpf_prog *prog = READ_ONCE(rq->xdp_prog); |
86994156 | 815 | struct xdp_buff xdp; |
b5503b99 | 816 | u32 act; |
5168d732 | 817 | int err; |
b5503b99 SM |
818 | |
819 | if (!prog) | |
820 | return false; | |
86994156 | 821 | |
d8bec2b2 | 822 | xdp.data = va + *rx_headroom; |
de8f3a83 | 823 | xdp_set_data_meta_invalid(&xdp); |
d8bec2b2 MKL |
824 | xdp.data_end = xdp.data + *len; |
825 | xdp.data_hard_start = va; | |
0ddf5432 | 826 | xdp.rxq = &rq->xdp_rxq; |
d8bec2b2 | 827 | |
b5503b99 SM |
828 | act = bpf_prog_run_xdp(prog, &xdp); |
829 | switch (act) { | |
830 | case XDP_PASS: | |
d8bec2b2 MKL |
831 | *rx_headroom = xdp.data - xdp.data_hard_start; |
832 | *len = xdp.data_end - xdp.data; | |
b5503b99 SM |
833 | return false; |
834 | case XDP_TX: | |
a67edbf4 DB |
835 | if (unlikely(!mlx5e_xmit_xdp_frame(rq, di, &xdp))) |
836 | trace_xdp_exception(rq->netdev, prog, act); | |
b5503b99 | 837 | return true; |
5168d732 JDB |
838 | case XDP_REDIRECT: |
839 | /* When XDP enabled then page-refcnt==1 here */ | |
840 | err = xdp_do_redirect(rq->netdev, &xdp, prog); | |
841 | if (!err) { | |
842 | __set_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags); | |
843 | rq->xdpsq.db.redirect_flush = true; | |
844 | mlx5e_page_dma_unmap(rq, di); | |
845 | } | |
846 | return true; | |
b5503b99 SM |
847 | default: |
848 | bpf_warn_invalid_xdp_action(act); | |
849 | case XDP_ABORTED: | |
a67edbf4 | 850 | trace_xdp_exception(rq->netdev, prog, act); |
b5503b99 SM |
851 | case XDP_DROP: |
852 | rq->stats.xdp_drop++; | |
b5503b99 SM |
853 | return true; |
854 | } | |
86994156 RS |
855 | } |
856 | ||
619a8f2a TT |
857 | static inline |
858 | struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va, | |
859 | u32 frag_size, u16 headroom, | |
860 | u32 cqe_bcnt) | |
861 | { | |
862 | struct sk_buff *skb = build_skb(va, frag_size); | |
863 | ||
864 | if (unlikely(!skb)) { | |
865 | rq->stats.buff_alloc_err++; | |
866 | return NULL; | |
867 | } | |
868 | ||
869 | skb_reserve(skb, headroom); | |
870 | skb_put(skb, cqe_bcnt); | |
871 | ||
872 | return skb; | |
873 | } | |
874 | ||
8515c581 OG |
875 | static inline |
876 | struct sk_buff *skb_from_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
accd5883 | 877 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt) |
2f48af12 | 878 | { |
accd5883 | 879 | struct mlx5e_dma_info *di = &wi->di; |
b45d8b50 | 880 | u16 rx_headroom = rq->buff.headroom; |
1bfecfca | 881 | struct sk_buff *skb; |
b5503b99 | 882 | void *va, *data; |
366cbf2f | 883 | bool consumed; |
78aedd32 | 884 | u32 frag_size; |
2f48af12 | 885 | |
accd5883 | 886 | va = page_address(di->page) + wi->offset; |
d8bec2b2 | 887 | data = va + rx_headroom; |
accd5883 | 888 | frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt); |
2f48af12 | 889 | |
bd658dda TT |
890 | dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset, |
891 | frag_size, DMA_FROM_DEVICE); | |
03993094 | 892 | prefetchw(va); /* xdp_frame data area */ |
b5503b99 | 893 | prefetch(data); |
accd5883 | 894 | wi->offset += frag_size; |
2f48af12 TT |
895 | |
896 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
897 | rq->stats.wqe_err++; | |
8515c581 | 898 | return NULL; |
2f48af12 TT |
899 | } |
900 | ||
366cbf2f | 901 | rcu_read_lock(); |
d8bec2b2 | 902 | consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt); |
366cbf2f DB |
903 | rcu_read_unlock(); |
904 | if (consumed) | |
8515c581 | 905 | return NULL; /* page/packet was consumed by XDP */ |
86994156 | 906 | |
619a8f2a TT |
907 | skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt); |
908 | if (unlikely(!skb)) | |
8515c581 | 909 | return NULL; |
1bfecfca | 910 | |
accd5883 | 911 | /* queue up for recycling/reuse */ |
1bfecfca | 912 | page_ref_inc(di->page); |
1bfecfca | 913 | |
8515c581 OG |
914 | return skb; |
915 | } | |
916 | ||
917 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
918 | { | |
accd5883 | 919 | struct mlx5e_wqe_frag_info *wi; |
8515c581 OG |
920 | struct mlx5e_rx_wqe *wqe; |
921 | __be16 wqe_counter_be; | |
922 | struct sk_buff *skb; | |
923 | u16 wqe_counter; | |
924 | u32 cqe_bcnt; | |
925 | ||
926 | wqe_counter_be = cqe->wqe_counter; | |
927 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
928 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 929 | wi = &rq->wqe.frag_info[wqe_counter]; |
8515c581 OG |
930 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
931 | ||
accd5883 TT |
932 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
933 | if (!skb) { | |
934 | /* probably for XDP */ | |
121e8927 | 935 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { |
accd5883 | 936 | wi->di.page = NULL; |
accd5883 TT |
937 | /* do not return page to cache, it will be returned on XDP_TX completion */ |
938 | goto wq_ll_pop; | |
939 | } | |
940 | /* probably an XDP_DROP, save the page-reuse checks */ | |
941 | mlx5e_free_rx_wqe(rq, wi); | |
8515c581 | 942 | goto wq_ll_pop; |
accd5883 | 943 | } |
8515c581 | 944 | |
461017cb | 945 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); |
8515c581 | 946 | napi_gro_receive(rq->cq.napi, skb); |
2f48af12 | 947 | |
accd5883 | 948 | mlx5e_free_rx_wqe_reuse(rq, wi); |
2f48af12 TT |
949 | wq_ll_pop: |
950 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
951 | &wqe->next.next_wqe_index); | |
952 | } | |
953 | ||
e80541ec | 954 | #ifdef CONFIG_MLX5_ESWITCH |
f5f82476 OG |
955 | void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
956 | { | |
957 | struct net_device *netdev = rq->netdev; | |
958 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1d447a39 SM |
959 | struct mlx5e_rep_priv *rpriv = priv->ppriv; |
960 | struct mlx5_eswitch_rep *rep = rpriv->rep; | |
accd5883 | 961 | struct mlx5e_wqe_frag_info *wi; |
f5f82476 OG |
962 | struct mlx5e_rx_wqe *wqe; |
963 | struct sk_buff *skb; | |
964 | __be16 wqe_counter_be; | |
965 | u16 wqe_counter; | |
966 | u32 cqe_bcnt; | |
967 | ||
968 | wqe_counter_be = cqe->wqe_counter; | |
969 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
970 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 971 | wi = &rq->wqe.frag_info[wqe_counter]; |
f5f82476 OG |
972 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
973 | ||
accd5883 TT |
974 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
975 | if (!skb) { | |
121e8927 | 976 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) { |
accd5883 | 977 | wi->di.page = NULL; |
accd5883 TT |
978 | /* do not return page to cache, it will be returned on XDP_TX completion */ |
979 | goto wq_ll_pop; | |
980 | } | |
981 | /* probably an XDP_DROP, save the page-reuse checks */ | |
982 | mlx5e_free_rx_wqe(rq, wi); | |
f5f82476 | 983 | goto wq_ll_pop; |
accd5883 | 984 | } |
f5f82476 OG |
985 | |
986 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
987 | ||
988 | if (rep->vlan && skb_vlan_tag_present(skb)) | |
989 | skb_vlan_pop(skb); | |
990 | ||
991 | napi_gro_receive(rq->cq.napi, skb); | |
992 | ||
accd5883 | 993 | mlx5e_free_rx_wqe_reuse(rq, wi); |
f5f82476 OG |
994 | wq_ll_pop: |
995 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
996 | &wqe->next.next_wqe_index); | |
997 | } | |
e80541ec | 998 | #endif |
f5f82476 | 999 | |
619a8f2a TT |
1000 | struct sk_buff * |
1001 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
1002 | u16 cqe_bcnt, u32 head_offset, u32 page_idx) | |
bc77b240 | 1003 | { |
bc77b240 | 1004 | u16 headlen = min_t(u16, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, cqe_bcnt); |
9f9e9cd5 | 1005 | struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; |
bc77b240 | 1006 | u32 frag_offset = head_offset + headlen; |
9f9e9cd5 TT |
1007 | u32 byte_cnt = cqe_bcnt - headlen; |
1008 | struct mlx5e_dma_info *head_di = di; | |
619a8f2a TT |
1009 | struct sk_buff *skb; |
1010 | ||
1011 | skb = napi_alloc_skb(rq->cq.napi, | |
1012 | ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD, sizeof(long))); | |
1013 | if (unlikely(!skb)) { | |
1014 | rq->stats.buff_alloc_err++; | |
1015 | return NULL; | |
1016 | } | |
1017 | ||
1018 | prefetchw(skb->data); | |
bc77b240 | 1019 | |
bc77b240 | 1020 | if (unlikely(frag_offset >= PAGE_SIZE)) { |
9f9e9cd5 | 1021 | di++; |
bc77b240 TT |
1022 | frag_offset -= PAGE_SIZE; |
1023 | } | |
bc77b240 TT |
1024 | |
1025 | while (byte_cnt) { | |
1026 | u32 pg_consumed_bytes = | |
1027 | min_t(u32, PAGE_SIZE - frag_offset, byte_cnt); | |
1028 | ||
9f9e9cd5 | 1029 | mlx5e_add_skb_frag_mpwqe(rq, skb, di, frag_offset, |
7e426671 | 1030 | pg_consumed_bytes); |
bc77b240 TT |
1031 | byte_cnt -= pg_consumed_bytes; |
1032 | frag_offset = 0; | |
9f9e9cd5 | 1033 | di++; |
bc77b240 TT |
1034 | } |
1035 | /* copy header */ | |
9f9e9cd5 | 1036 | mlx5e_copy_skb_header_mpwqe(rq->pdev, skb, head_di, |
7e426671 | 1037 | head_offset, headlen); |
bc77b240 TT |
1038 | /* skb linear part was allocated with headlen and aligned to long */ |
1039 | skb->tail += headlen; | |
1040 | skb->len += headlen; | |
619a8f2a TT |
1041 | |
1042 | return skb; | |
1043 | } | |
1044 | ||
1045 | struct sk_buff * | |
1046 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
1047 | u16 cqe_bcnt, u32 head_offset, u32 page_idx) | |
1048 | { | |
1049 | struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx]; | |
1050 | u16 rx_headroom = rq->buff.headroom; | |
22f45398 | 1051 | u32 cqe_bcnt32 = cqe_bcnt; |
619a8f2a TT |
1052 | struct sk_buff *skb; |
1053 | void *va, *data; | |
1054 | u32 frag_size; | |
22f45398 | 1055 | bool consumed; |
619a8f2a TT |
1056 | |
1057 | va = page_address(di->page) + head_offset; | |
1058 | data = va + rx_headroom; | |
22f45398 | 1059 | frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32); |
619a8f2a TT |
1060 | |
1061 | dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset, | |
1062 | frag_size, DMA_FROM_DEVICE); | |
1063 | prefetch(data); | |
22f45398 TT |
1064 | |
1065 | rcu_read_lock(); | |
1066 | consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32); | |
1067 | rcu_read_unlock(); | |
1068 | if (consumed) { | |
1069 | if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) | |
1070 | __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */ | |
1071 | return NULL; /* page/packet was consumed by XDP */ | |
1072 | } | |
1073 | ||
1074 | skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32); | |
619a8f2a TT |
1075 | if (unlikely(!skb)) |
1076 | return NULL; | |
1077 | ||
1078 | /* queue up for recycling/reuse */ | |
9f9e9cd5 | 1079 | page_ref_inc(di->page); |
619a8f2a TT |
1080 | |
1081 | return skb; | |
bc77b240 TT |
1082 | } |
1083 | ||
461017cb TT |
1084 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) |
1085 | { | |
1086 | u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe); | |
461017cb | 1087 | u16 wqe_id = be16_to_cpu(cqe->wqe_id); |
21c59685 | 1088 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id]; |
619a8f2a TT |
1089 | u16 stride_ix = mpwrq_get_cqe_stride_index(cqe); |
1090 | u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz; | |
1091 | u32 head_offset = wqe_offset & (PAGE_SIZE - 1); | |
1092 | u32 page_idx = wqe_offset >> PAGE_SHIFT; | |
1093 | struct mlx5e_rx_wqe *wqe; | |
461017cb | 1094 | struct sk_buff *skb; |
461017cb | 1095 | u16 cqe_bcnt; |
461017cb TT |
1096 | |
1097 | wi->consumed_strides += cstrides; | |
1098 | ||
1099 | if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) { | |
1100 | rq->stats.wqe_err++; | |
1101 | goto mpwrq_cqe_out; | |
1102 | } | |
1103 | ||
1104 | if (unlikely(mpwrq_is_filler_cqe(cqe))) { | |
1105 | rq->stats.mpwqe_filler++; | |
1106 | goto mpwrq_cqe_out; | |
1107 | } | |
1108 | ||
461017cb | 1109 | cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe); |
461017cb | 1110 | |
619a8f2a TT |
1111 | skb = rq->mpwqe.skb_from_cqe_mpwrq(rq, wi, cqe_bcnt, head_offset, |
1112 | page_idx); | |
22f45398 | 1113 | if (!skb) |
619a8f2a TT |
1114 | goto mpwrq_cqe_out; |
1115 | ||
461017cb | 1116 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); |
8515c581 | 1117 | napi_gro_receive(rq->cq.napi, skb); |
461017cb TT |
1118 | |
1119 | mpwrq_cqe_out: | |
b45d8b50 | 1120 | if (likely(wi->consumed_strides < rq->mpwqe.num_strides)) |
461017cb TT |
1121 | return; |
1122 | ||
619a8f2a | 1123 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_id); |
7e426671 | 1124 | mlx5e_free_rx_mpwqe(rq, wi); |
461017cb TT |
1125 | mlx5_wq_ll_pop(&rq->wq, cqe->wqe_id, &wqe->next.next_wqe_index); |
1126 | } | |
1127 | ||
44fb6fbb | 1128 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget) |
e586b3b0 | 1129 | { |
e3391054 | 1130 | struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq); |
4b7dfc99 TT |
1131 | struct mlx5e_xdpsq *xdpsq; |
1132 | struct mlx5_cqe64 *cqe; | |
7219ab34 | 1133 | int work_done = 0; |
e586b3b0 | 1134 | |
0e5c04f6 | 1135 | if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state))) |
6cd392a0 DJ |
1136 | return 0; |
1137 | ||
7219ab34 TT |
1138 | if (cq->decmprs_left) |
1139 | work_done += mlx5e_decompress_cqes_cont(rq, cq, 0, budget); | |
1140 | ||
4b7dfc99 TT |
1141 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
1142 | if (!cqe) | |
1143 | return 0; | |
e586b3b0 | 1144 | |
4b7dfc99 | 1145 | xdpsq = &rq->xdpsq; |
e586b3b0 | 1146 | |
4b7dfc99 | 1147 | do { |
7219ab34 TT |
1148 | if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) { |
1149 | work_done += | |
1150 | mlx5e_decompress_cqes_start(rq, cq, | |
1151 | budget - work_done); | |
1152 | continue; | |
1153 | } | |
1154 | ||
a1f5a1a8 AS |
1155 | mlx5_cqwq_pop(&cq->wq); |
1156 | ||
2f48af12 | 1157 | rq->handle_rx_cqe(rq, cqe); |
4b7dfc99 | 1158 | } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); |
e586b3b0 | 1159 | |
31391048 | 1160 | if (xdpsq->db.doorbell) { |
31871f87 | 1161 | mlx5e_xmit_xdp_doorbell(xdpsq); |
31391048 | 1162 | xdpsq->db.doorbell = false; |
35b510e2 SM |
1163 | } |
1164 | ||
5168d732 JDB |
1165 | if (xdpsq->db.redirect_flush) { |
1166 | xdp_do_flush_map(); | |
1167 | xdpsq->db.redirect_flush = false; | |
1168 | } | |
1169 | ||
e586b3b0 AV |
1170 | mlx5_cqwq_update_db_record(&cq->wq); |
1171 | ||
1172 | /* ensure cq space is freed before enabling more cqes */ | |
1173 | wmb(); | |
1174 | ||
44fb6fbb | 1175 | return work_done; |
e586b3b0 | 1176 | } |
1c4bf940 SM |
1177 | |
1178 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq) | |
1179 | { | |
31391048 | 1180 | struct mlx5e_xdpsq *sq; |
4b7dfc99 | 1181 | struct mlx5_cqe64 *cqe; |
31871f87 | 1182 | struct mlx5e_rq *rq; |
1c4bf940 SM |
1183 | u16 sqcc; |
1184 | int i; | |
1185 | ||
31391048 | 1186 | sq = container_of(cq, struct mlx5e_xdpsq, cq); |
1c4bf940 | 1187 | |
0e5c04f6 | 1188 | if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state))) |
1c4bf940 SM |
1189 | return false; |
1190 | ||
4b7dfc99 TT |
1191 | cqe = mlx5_cqwq_get_cqe(&cq->wq); |
1192 | if (!cqe) | |
1193 | return false; | |
1194 | ||
31871f87 SM |
1195 | rq = container_of(sq, struct mlx5e_rq, xdpsq); |
1196 | ||
1c4bf940 SM |
1197 | /* sq->cc must be updated only after mlx5_cqwq_update_db_record(), |
1198 | * otherwise a cq overrun may occur | |
1199 | */ | |
1200 | sqcc = sq->cc; | |
1201 | ||
4b7dfc99 TT |
1202 | i = 0; |
1203 | do { | |
1c4bf940 SM |
1204 | u16 wqe_counter; |
1205 | bool last_wqe; | |
1206 | ||
1c4bf940 SM |
1207 | mlx5_cqwq_pop(&cq->wq); |
1208 | ||
1209 | wqe_counter = be16_to_cpu(cqe->wqe_counter); | |
1210 | ||
1211 | do { | |
1c4bf940 SM |
1212 | struct mlx5e_dma_info *di; |
1213 | u16 ci; | |
1214 | ||
1215 | last_wqe = (sqcc == wqe_counter); | |
1216 | ||
1217 | ci = sqcc & sq->wq.sz_m1; | |
31391048 | 1218 | di = &sq->db.di[ci]; |
1c4bf940 | 1219 | |
2239185c | 1220 | sqcc++; |
1c4bf940 | 1221 | /* Recycle RX page */ |
31871f87 | 1222 | mlx5e_page_release(rq, di, true); |
1c4bf940 | 1223 | } while (!last_wqe); |
4b7dfc99 | 1224 | } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq))); |
1c4bf940 SM |
1225 | |
1226 | mlx5_cqwq_update_db_record(&cq->wq); | |
1227 | ||
1228 | /* ensure cq space is freed before enabling more cqes */ | |
1229 | wmb(); | |
1230 | ||
1231 | sq->cc = sqcc; | |
1232 | return (i == MLX5E_TX_CQ_POLL_BUDGET); | |
1233 | } | |
1234 | ||
31391048 | 1235 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq) |
1c4bf940 | 1236 | { |
31871f87 | 1237 | struct mlx5e_rq *rq = container_of(sq, struct mlx5e_rq, xdpsq); |
1c4bf940 SM |
1238 | struct mlx5e_dma_info *di; |
1239 | u16 ci; | |
1240 | ||
1241 | while (sq->cc != sq->pc) { | |
1242 | ci = sq->cc & sq->wq.sz_m1; | |
31391048 | 1243 | di = &sq->db.di[ci]; |
2239185c | 1244 | sq->cc++; |
1c4bf940 | 1245 | |
31871f87 | 1246 | mlx5e_page_release(rq, di, false); |
1c4bf940 SM |
1247 | } |
1248 | } | |
9d6bd752 SM |
1249 | |
1250 | #ifdef CONFIG_MLX5_CORE_IPOIB | |
1251 | ||
1252 | #define MLX5_IB_GRH_DGID_OFFSET 24 | |
9d6bd752 SM |
1253 | #define MLX5_GID_SIZE 16 |
1254 | ||
1255 | static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq, | |
1256 | struct mlx5_cqe64 *cqe, | |
1257 | u32 cqe_bcnt, | |
1258 | struct sk_buff *skb) | |
1259 | { | |
36e564b7 | 1260 | struct hwtstamp_config *tstamp; |
7e7f4780 | 1261 | struct net_device *netdev; |
36e564b7 | 1262 | struct mlx5e_priv *priv; |
b57fe691 | 1263 | char *pseudo_header; |
7e7f4780 | 1264 | u32 qpn; |
9d6bd752 SM |
1265 | u8 *dgid; |
1266 | u8 g; | |
1267 | ||
7e7f4780 AV |
1268 | qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff; |
1269 | netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn); | |
1270 | ||
1271 | /* No mapping present, cannot process SKB. This might happen if a child | |
1272 | * interface is going down while having unprocessed CQEs on parent RQ | |
1273 | */ | |
1274 | if (unlikely(!netdev)) { | |
1275 | /* TODO: add drop counters support */ | |
1276 | skb->dev = NULL; | |
1277 | pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn); | |
1278 | return; | |
1279 | } | |
1280 | ||
36e564b7 FD |
1281 | priv = mlx5i_epriv(netdev); |
1282 | tstamp = &priv->tstamp; | |
1283 | ||
9d6bd752 SM |
1284 | g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3; |
1285 | dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET; | |
1286 | if ((!g) || dgid[0] != 0xff) | |
1287 | skb->pkt_type = PACKET_HOST; | |
1288 | else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0) | |
1289 | skb->pkt_type = PACKET_BROADCAST; | |
1290 | else | |
1291 | skb->pkt_type = PACKET_MULTICAST; | |
1292 | ||
1293 | /* TODO: IB/ipoib: Allow mcast packets from other VFs | |
1294 | * 68996a6e760e5c74654723eeb57bf65628ae87f4 | |
1295 | */ | |
1296 | ||
1297 | skb_pull(skb, MLX5_IB_GRH_BYTES); | |
1298 | ||
1299 | skb->protocol = *((__be16 *)(skb->data)); | |
1300 | ||
1301 | skb->ip_summed = CHECKSUM_COMPLETE; | |
1302 | skb->csum = csum_unfold((__force __sum16)cqe->check_sum); | |
1303 | ||
36e564b7 | 1304 | if (unlikely(mlx5e_rx_hw_stamp(tstamp))) |
7c39afb3 FD |
1305 | skb_hwtstamps(skb)->hwtstamp = |
1306 | mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); | |
3844b07e | 1307 | |
9d6bd752 SM |
1308 | skb_record_rx_queue(skb, rq->ix); |
1309 | ||
1310 | if (likely(netdev->features & NETIF_F_RXHASH)) | |
1311 | mlx5e_skb_set_hash(cqe, skb); | |
1312 | ||
b57fe691 ES |
1313 | /* 20 bytes of ipoib header and 4 for encap existing */ |
1314 | pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN); | |
1315 | memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN); | |
9d6bd752 | 1316 | skb_reset_mac_header(skb); |
b57fe691 | 1317 | skb_pull(skb, MLX5_IPOIB_HARD_LEN); |
9d6bd752 SM |
1318 | |
1319 | skb->dev = netdev; | |
1320 | ||
1321 | rq->stats.csum_complete++; | |
1322 | rq->stats.packets++; | |
1323 | rq->stats.bytes += cqe_bcnt; | |
1324 | } | |
1325 | ||
1326 | void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
1327 | { | |
accd5883 | 1328 | struct mlx5e_wqe_frag_info *wi; |
9d6bd752 SM |
1329 | struct mlx5e_rx_wqe *wqe; |
1330 | __be16 wqe_counter_be; | |
1331 | struct sk_buff *skb; | |
1332 | u16 wqe_counter; | |
1333 | u32 cqe_bcnt; | |
1334 | ||
1335 | wqe_counter_be = cqe->wqe_counter; | |
1336 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
1337 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
accd5883 | 1338 | wi = &rq->wqe.frag_info[wqe_counter]; |
9d6bd752 SM |
1339 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); |
1340 | ||
accd5883 | 1341 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); |
9d6bd752 | 1342 | if (!skb) |
accd5883 | 1343 | goto wq_free_wqe; |
9d6bd752 SM |
1344 | |
1345 | mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
7e7f4780 AV |
1346 | if (unlikely(!skb->dev)) { |
1347 | dev_kfree_skb_any(skb); | |
1348 | goto wq_free_wqe; | |
1349 | } | |
9d6bd752 SM |
1350 | napi_gro_receive(rq->cq.napi, skb); |
1351 | ||
accd5883 TT |
1352 | wq_free_wqe: |
1353 | mlx5e_free_rx_wqe_reuse(rq, wi); | |
9d6bd752 SM |
1354 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, |
1355 | &wqe->next.next_wqe_index); | |
1356 | } | |
1357 | ||
1358 | #endif /* CONFIG_MLX5_CORE_IPOIB */ | |
899a59d3 IT |
1359 | |
1360 | #ifdef CONFIG_MLX5_EN_IPSEC | |
1361 | ||
1362 | void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe) | |
1363 | { | |
1364 | struct mlx5e_wqe_frag_info *wi; | |
1365 | struct mlx5e_rx_wqe *wqe; | |
1366 | __be16 wqe_counter_be; | |
1367 | struct sk_buff *skb; | |
1368 | u16 wqe_counter; | |
1369 | u32 cqe_bcnt; | |
1370 | ||
1371 | wqe_counter_be = cqe->wqe_counter; | |
1372 | wqe_counter = be16_to_cpu(wqe_counter_be); | |
1373 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_counter); | |
1374 | wi = &rq->wqe.frag_info[wqe_counter]; | |
1375 | cqe_bcnt = be32_to_cpu(cqe->byte_cnt); | |
1376 | ||
1377 | skb = skb_from_cqe(rq, cqe, wi, cqe_bcnt); | |
1378 | if (unlikely(!skb)) { | |
1379 | /* a DROP, save the page-reuse checks */ | |
1380 | mlx5e_free_rx_wqe(rq, wi); | |
1381 | goto wq_ll_pop; | |
1382 | } | |
1383 | skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb); | |
1384 | if (unlikely(!skb)) { | |
1385 | mlx5e_free_rx_wqe(rq, wi); | |
1386 | goto wq_ll_pop; | |
1387 | } | |
1388 | ||
1389 | mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb); | |
1390 | napi_gro_receive(rq->cq.napi, skb); | |
1391 | ||
1392 | mlx5e_free_rx_wqe_reuse(rq, wi); | |
1393 | wq_ll_pop: | |
1394 | mlx5_wq_ll_pop(&rq->wq, wqe_counter_be, | |
1395 | &wqe->next.next_wqe_index); | |
1396 | } | |
1397 | ||
1398 | #endif /* CONFIG_MLX5_EN_IPSEC */ |