Commit | Line | Data |
---|---|---|
f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
f62b8bb8 | 37 | #include "en.h" |
e8f887ac | 38 | #include "en_tc.h" |
66e49ded | 39 | #include "eswitch.h" |
b3f63c3d | 40 | #include "vxlan.h" |
f62b8bb8 AV |
41 | |
42 | struct mlx5e_rq_param { | |
43 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; | |
44 | struct mlx5_wq_param wq; | |
45 | }; | |
46 | ||
47 | struct mlx5e_sq_param { | |
48 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
49 | struct mlx5_wq_param wq; | |
58d52291 | 50 | u16 max_inline; |
f62b8bb8 AV |
51 | }; |
52 | ||
53 | struct mlx5e_cq_param { | |
54 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
55 | struct mlx5_wq_param wq; | |
56 | u16 eq_ix; | |
57 | }; | |
58 | ||
59 | struct mlx5e_channel_param { | |
60 | struct mlx5e_rq_param rq; | |
61 | struct mlx5e_sq_param sq; | |
62 | struct mlx5e_cq_param rx_cq; | |
63 | struct mlx5e_cq_param tx_cq; | |
64 | }; | |
65 | ||
66 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
67 | { | |
68 | struct mlx5_core_dev *mdev = priv->mdev; | |
69 | u8 port_state; | |
70 | ||
71 | port_state = mlx5_query_vport_state(mdev, | |
e7546514 | 72 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); |
f62b8bb8 AV |
73 | |
74 | if (port_state == VPORT_STATE_UP) | |
75 | netif_carrier_on(priv->netdev); | |
76 | else | |
77 | netif_carrier_off(priv->netdev); | |
78 | } | |
79 | ||
80 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
81 | { | |
82 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
83 | update_carrier_work); | |
84 | ||
85 | mutex_lock(&priv->state_lock); | |
86 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
87 | mlx5e_update_carrier(priv); | |
88 | mutex_unlock(&priv->state_lock); | |
89 | } | |
90 | ||
efea389d GP |
91 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) |
92 | { | |
93 | struct mlx5_core_dev *mdev = priv->mdev; | |
94 | struct mlx5e_pport_stats *s = &priv->stats.pport; | |
95 | u32 *in; | |
96 | u32 *out; | |
97 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
98 | ||
99 | in = mlx5_vzalloc(sz); | |
100 | out = mlx5_vzalloc(sz); | |
101 | if (!in || !out) | |
102 | goto free_out; | |
103 | ||
104 | MLX5_SET(ppcnt_reg, in, local_port, 1); | |
105 | ||
106 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
107 | mlx5_core_access_reg(mdev, in, sz, out, | |
108 | sz, MLX5_REG_PPCNT, 0, 0); | |
109 | memcpy(s->IEEE_802_3_counters, | |
110 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
111 | sizeof(s->IEEE_802_3_counters)); | |
112 | ||
113 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
114 | mlx5_core_access_reg(mdev, in, sz, out, | |
115 | sz, MLX5_REG_PPCNT, 0, 0); | |
116 | memcpy(s->RFC_2863_counters, | |
117 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
118 | sizeof(s->RFC_2863_counters)); | |
119 | ||
120 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
121 | mlx5_core_access_reg(mdev, in, sz, out, | |
122 | sz, MLX5_REG_PPCNT, 0, 0); | |
123 | memcpy(s->RFC_2819_counters, | |
124 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
125 | sizeof(s->RFC_2819_counters)); | |
126 | ||
127 | free_out: | |
128 | kvfree(in); | |
129 | kvfree(out); | |
130 | } | |
131 | ||
f62b8bb8 AV |
132 | void mlx5e_update_stats(struct mlx5e_priv *priv) |
133 | { | |
134 | struct mlx5_core_dev *mdev = priv->mdev; | |
135 | struct mlx5e_vport_stats *s = &priv->stats.vport; | |
136 | struct mlx5e_rq_stats *rq_stats; | |
137 | struct mlx5e_sq_stats *sq_stats; | |
138 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
139 | u32 *out; | |
140 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
141 | u64 tx_offload_none; | |
142 | int i, j; | |
143 | ||
144 | out = mlx5_vzalloc(outlen); | |
145 | if (!out) | |
146 | return; | |
147 | ||
148 | /* Collect firts the SW counters and then HW for consistency */ | |
faf4478b GP |
149 | s->rx_packets = 0; |
150 | s->rx_bytes = 0; | |
151 | s->tx_packets = 0; | |
152 | s->tx_bytes = 0; | |
f62b8bb8 AV |
153 | s->tso_packets = 0; |
154 | s->tso_bytes = 0; | |
89db09eb MF |
155 | s->tso_inner_packets = 0; |
156 | s->tso_inner_bytes = 0; | |
f62b8bb8 AV |
157 | s->tx_queue_stopped = 0; |
158 | s->tx_queue_wake = 0; | |
159 | s->tx_queue_dropped = 0; | |
89db09eb | 160 | s->tx_csum_inner = 0; |
f62b8bb8 AV |
161 | tx_offload_none = 0; |
162 | s->lro_packets = 0; | |
163 | s->lro_bytes = 0; | |
164 | s->rx_csum_none = 0; | |
bbceefce | 165 | s->rx_csum_sw = 0; |
f62b8bb8 AV |
166 | s->rx_wqe_err = 0; |
167 | for (i = 0; i < priv->params.num_channels; i++) { | |
168 | rq_stats = &priv->channel[i]->rq.stats; | |
169 | ||
faf4478b GP |
170 | s->rx_packets += rq_stats->packets; |
171 | s->rx_bytes += rq_stats->bytes; | |
f62b8bb8 AV |
172 | s->lro_packets += rq_stats->lro_packets; |
173 | s->lro_bytes += rq_stats->lro_bytes; | |
174 | s->rx_csum_none += rq_stats->csum_none; | |
bbceefce | 175 | s->rx_csum_sw += rq_stats->csum_sw; |
f62b8bb8 AV |
176 | s->rx_wqe_err += rq_stats->wqe_err; |
177 | ||
a4418a6c | 178 | for (j = 0; j < priv->params.num_tc; j++) { |
f62b8bb8 AV |
179 | sq_stats = &priv->channel[i]->sq[j].stats; |
180 | ||
faf4478b GP |
181 | s->tx_packets += sq_stats->packets; |
182 | s->tx_bytes += sq_stats->bytes; | |
f62b8bb8 AV |
183 | s->tso_packets += sq_stats->tso_packets; |
184 | s->tso_bytes += sq_stats->tso_bytes; | |
89db09eb MF |
185 | s->tso_inner_packets += sq_stats->tso_inner_packets; |
186 | s->tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f62b8bb8 AV |
187 | s->tx_queue_stopped += sq_stats->stopped; |
188 | s->tx_queue_wake += sq_stats->wake; | |
189 | s->tx_queue_dropped += sq_stats->dropped; | |
89db09eb | 190 | s->tx_csum_inner += sq_stats->csum_offload_inner; |
f62b8bb8 AV |
191 | tx_offload_none += sq_stats->csum_offload_none; |
192 | } | |
193 | } | |
194 | ||
195 | /* HW counters */ | |
196 | memset(in, 0, sizeof(in)); | |
197 | ||
198 | MLX5_SET(query_vport_counter_in, in, opcode, | |
199 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
200 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
201 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
202 | ||
203 | memset(out, 0, outlen); | |
204 | ||
205 | if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen)) | |
206 | goto free_out; | |
207 | ||
208 | #define MLX5_GET_CTR(p, x) \ | |
209 | MLX5_GET64(query_vport_counter_out, p, x) | |
210 | ||
211 | s->rx_error_packets = | |
212 | MLX5_GET_CTR(out, received_errors.packets); | |
213 | s->rx_error_bytes = | |
214 | MLX5_GET_CTR(out, received_errors.octets); | |
215 | s->tx_error_packets = | |
216 | MLX5_GET_CTR(out, transmit_errors.packets); | |
217 | s->tx_error_bytes = | |
218 | MLX5_GET_CTR(out, transmit_errors.octets); | |
219 | ||
220 | s->rx_unicast_packets = | |
221 | MLX5_GET_CTR(out, received_eth_unicast.packets); | |
222 | s->rx_unicast_bytes = | |
223 | MLX5_GET_CTR(out, received_eth_unicast.octets); | |
224 | s->tx_unicast_packets = | |
225 | MLX5_GET_CTR(out, transmitted_eth_unicast.packets); | |
226 | s->tx_unicast_bytes = | |
227 | MLX5_GET_CTR(out, transmitted_eth_unicast.octets); | |
228 | ||
229 | s->rx_multicast_packets = | |
230 | MLX5_GET_CTR(out, received_eth_multicast.packets); | |
231 | s->rx_multicast_bytes = | |
232 | MLX5_GET_CTR(out, received_eth_multicast.octets); | |
233 | s->tx_multicast_packets = | |
234 | MLX5_GET_CTR(out, transmitted_eth_multicast.packets); | |
235 | s->tx_multicast_bytes = | |
236 | MLX5_GET_CTR(out, transmitted_eth_multicast.octets); | |
237 | ||
238 | s->rx_broadcast_packets = | |
239 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
240 | s->rx_broadcast_bytes = | |
241 | MLX5_GET_CTR(out, received_eth_broadcast.octets); | |
242 | s->tx_broadcast_packets = | |
243 | MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); | |
244 | s->tx_broadcast_bytes = | |
245 | MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); | |
246 | ||
f62b8bb8 | 247 | /* Update calculated offload counters */ |
89db09eb | 248 | s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner; |
bbceefce AS |
249 | s->rx_csum_good = s->rx_packets - s->rx_csum_none - |
250 | s->rx_csum_sw; | |
f62b8bb8 | 251 | |
efea389d | 252 | mlx5e_update_pport_counters(priv); |
f62b8bb8 AV |
253 | free_out: |
254 | kvfree(out); | |
255 | } | |
256 | ||
257 | static void mlx5e_update_stats_work(struct work_struct *work) | |
258 | { | |
259 | struct delayed_work *dwork = to_delayed_work(work); | |
260 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
261 | update_stats_work); | |
262 | mutex_lock(&priv->state_lock); | |
263 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
264 | mlx5e_update_stats(priv); | |
7bb29755 MF |
265 | queue_delayed_work(priv->wq, dwork, |
266 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
267 | } |
268 | mutex_unlock(&priv->state_lock); | |
269 | } | |
270 | ||
daa21560 TT |
271 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
272 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 273 | { |
daa21560 TT |
274 | struct mlx5e_priv *priv = vpriv; |
275 | ||
276 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) | |
277 | return; | |
278 | ||
f62b8bb8 AV |
279 | switch (event) { |
280 | case MLX5_DEV_EVENT_PORT_UP: | |
281 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 282 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 AV |
283 | break; |
284 | ||
285 | default: | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
f62b8bb8 AV |
290 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
291 | { | |
292 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); | |
293 | } | |
294 | ||
295 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
296 | { | |
f62b8bb8 | 297 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); |
daa21560 | 298 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
299 | } |
300 | ||
facc9699 SM |
301 | #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
302 | #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
303 | ||
f62b8bb8 AV |
304 | static int mlx5e_create_rq(struct mlx5e_channel *c, |
305 | struct mlx5e_rq_param *param, | |
306 | struct mlx5e_rq *rq) | |
307 | { | |
308 | struct mlx5e_priv *priv = c->priv; | |
309 | struct mlx5_core_dev *mdev = priv->mdev; | |
310 | void *rqc = param->rqc; | |
311 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
312 | int wq_sz; | |
313 | int err; | |
314 | int i; | |
315 | ||
311c7c71 SM |
316 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
317 | ||
f62b8bb8 AV |
318 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, |
319 | &rq->wq_ctrl); | |
320 | if (err) | |
321 | return err; | |
322 | ||
323 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
324 | ||
325 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
326 | rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL, | |
327 | cpu_to_node(c->cpu)); | |
328 | if (!rq->skb) { | |
329 | err = -ENOMEM; | |
330 | goto err_rq_wq_destroy; | |
331 | } | |
332 | ||
333 | rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz : | |
facc9699 | 334 | MLX5E_SW2HW_MTU(priv->netdev->mtu); |
fc11fbf9 | 335 | rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN); |
f62b8bb8 AV |
336 | |
337 | for (i = 0; i < wq_sz; i++) { | |
338 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
fc11fbf9 | 339 | u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; |
f62b8bb8 AV |
340 | |
341 | wqe->data.lkey = c->mkey_be; | |
fc11fbf9 SM |
342 | wqe->data.byte_count = |
343 | cpu_to_be32(byte_count | MLX5_HW_START_PADDING); | |
f62b8bb8 AV |
344 | } |
345 | ||
346 | rq->pdev = c->pdev; | |
347 | rq->netdev = c->netdev; | |
ef9814de | 348 | rq->tstamp = &priv->tstamp; |
f62b8bb8 AV |
349 | rq->channel = c; |
350 | rq->ix = c->ix; | |
50cfa25a | 351 | rq->priv = c->priv; |
f62b8bb8 AV |
352 | |
353 | return 0; | |
354 | ||
355 | err_rq_wq_destroy: | |
356 | mlx5_wq_destroy(&rq->wq_ctrl); | |
357 | ||
358 | return err; | |
359 | } | |
360 | ||
361 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
362 | { | |
363 | kfree(rq->skb); | |
364 | mlx5_wq_destroy(&rq->wq_ctrl); | |
365 | } | |
366 | ||
367 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
368 | { | |
50cfa25a | 369 | struct mlx5e_priv *priv = rq->priv; |
f62b8bb8 AV |
370 | struct mlx5_core_dev *mdev = priv->mdev; |
371 | ||
372 | void *in; | |
373 | void *rqc; | |
374 | void *wq; | |
375 | int inlen; | |
376 | int err; | |
377 | ||
378 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
379 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
380 | in = mlx5_vzalloc(inlen); | |
381 | if (!in) | |
382 | return -ENOMEM; | |
383 | ||
384 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
385 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
386 | ||
387 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
388 | ||
97de9f31 | 389 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 AV |
390 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
391 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
f62b8bb8 | 392 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 393 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
394 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
395 | ||
396 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
397 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
398 | ||
7db22ffb | 399 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
400 | |
401 | kvfree(in); | |
402 | ||
403 | return err; | |
404 | } | |
405 | ||
406 | static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) | |
407 | { | |
408 | struct mlx5e_channel *c = rq->channel; | |
409 | struct mlx5e_priv *priv = c->priv; | |
410 | struct mlx5_core_dev *mdev = priv->mdev; | |
411 | ||
412 | void *in; | |
413 | void *rqc; | |
414 | int inlen; | |
415 | int err; | |
416 | ||
417 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
418 | in = mlx5_vzalloc(inlen); | |
419 | if (!in) | |
420 | return -ENOMEM; | |
421 | ||
422 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
423 | ||
424 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
425 | MLX5_SET(rqc, rqc, state, next_state); | |
426 | ||
7db22ffb | 427 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
428 | |
429 | kvfree(in); | |
430 | ||
431 | return err; | |
432 | } | |
433 | ||
434 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) | |
435 | { | |
50cfa25a | 436 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); |
f62b8bb8 AV |
437 | } |
438 | ||
439 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
440 | { | |
01c196a2 | 441 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 AV |
442 | struct mlx5e_channel *c = rq->channel; |
443 | struct mlx5e_priv *priv = c->priv; | |
444 | struct mlx5_wq_ll *wq = &rq->wq; | |
f62b8bb8 | 445 | |
01c196a2 | 446 | while (time_before(jiffies, exp_time)) { |
f62b8bb8 AV |
447 | if (wq->cur_sz >= priv->params.min_rx_wqes) |
448 | return 0; | |
449 | ||
450 | msleep(20); | |
451 | } | |
452 | ||
453 | return -ETIMEDOUT; | |
454 | } | |
455 | ||
456 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
457 | struct mlx5e_rq_param *param, | |
458 | struct mlx5e_rq *rq) | |
459 | { | |
460 | int err; | |
461 | ||
462 | err = mlx5e_create_rq(c, param, rq); | |
463 | if (err) | |
464 | return err; | |
465 | ||
466 | err = mlx5e_enable_rq(rq, param); | |
467 | if (err) | |
468 | goto err_destroy_rq; | |
469 | ||
470 | err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); | |
471 | if (err) | |
472 | goto err_disable_rq; | |
473 | ||
474 | set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
12be4b21 | 475 | mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */ |
f62b8bb8 AV |
476 | |
477 | return 0; | |
478 | ||
479 | err_disable_rq: | |
480 | mlx5e_disable_rq(rq); | |
481 | err_destroy_rq: | |
482 | mlx5e_destroy_rq(rq); | |
483 | ||
484 | return err; | |
485 | } | |
486 | ||
487 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
488 | { | |
489 | clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
490 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
491 | ||
492 | mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); | |
493 | while (!mlx5_wq_ll_is_empty(&rq->wq)) | |
494 | msleep(20); | |
495 | ||
496 | /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */ | |
497 | napi_synchronize(&rq->channel->napi); | |
498 | ||
499 | mlx5e_disable_rq(rq); | |
500 | mlx5e_destroy_rq(rq); | |
501 | } | |
502 | ||
503 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
504 | { | |
34802a42 | 505 | kfree(sq->wqe_info); |
f62b8bb8 AV |
506 | kfree(sq->dma_fifo); |
507 | kfree(sq->skb); | |
508 | } | |
509 | ||
510 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
511 | { | |
512 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
513 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
514 | ||
515 | sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa); | |
516 | sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL, | |
517 | numa); | |
34802a42 AS |
518 | sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL, |
519 | numa); | |
f62b8bb8 | 520 | |
34802a42 | 521 | if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) { |
f62b8bb8 AV |
522 | mlx5e_free_sq_db(sq); |
523 | return -ENOMEM; | |
524 | } | |
525 | ||
526 | sq->dma_fifo_mask = df_sz - 1; | |
527 | ||
528 | return 0; | |
529 | } | |
530 | ||
531 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
532 | int tc, | |
533 | struct mlx5e_sq_param *param, | |
534 | struct mlx5e_sq *sq) | |
535 | { | |
536 | struct mlx5e_priv *priv = c->priv; | |
537 | struct mlx5_core_dev *mdev = priv->mdev; | |
538 | ||
539 | void *sqc = param->sqc; | |
540 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
03289b88 | 541 | int txq_ix; |
f62b8bb8 AV |
542 | int err; |
543 | ||
0ba42241 | 544 | err = mlx5_alloc_map_uar(mdev, &sq->uar, true); |
f62b8bb8 AV |
545 | if (err) |
546 | return err; | |
547 | ||
311c7c71 SM |
548 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
549 | ||
f62b8bb8 AV |
550 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, |
551 | &sq->wq_ctrl); | |
552 | if (err) | |
553 | goto err_unmap_free_uar; | |
554 | ||
555 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
0ba42241 ML |
556 | if (sq->uar.bf_map) { |
557 | set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state); | |
558 | sq->uar_map = sq->uar.bf_map; | |
559 | } else { | |
560 | sq->uar_map = sq->uar.map; | |
561 | } | |
f62b8bb8 | 562 | sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; |
58d52291 | 563 | sq->max_inline = param->max_inline; |
f62b8bb8 | 564 | |
7ec0bb22 DC |
565 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); |
566 | if (err) | |
f62b8bb8 AV |
567 | goto err_sq_wq_destroy; |
568 | ||
03289b88 SM |
569 | txq_ix = c->ix + tc * priv->params.num_channels; |
570 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
f62b8bb8 | 571 | |
88a85f99 | 572 | sq->pdev = c->pdev; |
ef9814de | 573 | sq->tstamp = &priv->tstamp; |
88a85f99 AS |
574 | sq->mkey_be = c->mkey_be; |
575 | sq->channel = c; | |
576 | sq->tc = tc; | |
577 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; | |
578 | sq->bf_budget = MLX5E_SQ_BF_BUDGET; | |
03289b88 | 579 | priv->txq_to_sq_map[txq_ix] = sq; |
f62b8bb8 AV |
580 | |
581 | return 0; | |
582 | ||
583 | err_sq_wq_destroy: | |
584 | mlx5_wq_destroy(&sq->wq_ctrl); | |
585 | ||
586 | err_unmap_free_uar: | |
587 | mlx5_unmap_free_uar(mdev, &sq->uar); | |
588 | ||
589 | return err; | |
590 | } | |
591 | ||
592 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
593 | { | |
594 | struct mlx5e_channel *c = sq->channel; | |
595 | struct mlx5e_priv *priv = c->priv; | |
596 | ||
597 | mlx5e_free_sq_db(sq); | |
598 | mlx5_wq_destroy(&sq->wq_ctrl); | |
599 | mlx5_unmap_free_uar(priv->mdev, &sq->uar); | |
600 | } | |
601 | ||
602 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
603 | { | |
604 | struct mlx5e_channel *c = sq->channel; | |
605 | struct mlx5e_priv *priv = c->priv; | |
606 | struct mlx5_core_dev *mdev = priv->mdev; | |
607 | ||
608 | void *in; | |
609 | void *sqc; | |
610 | void *wq; | |
611 | int inlen; | |
612 | int err; | |
613 | ||
614 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
615 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
616 | in = mlx5_vzalloc(inlen); | |
617 | if (!in) | |
618 | return -ENOMEM; | |
619 | ||
620 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
621 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
622 | ||
623 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
624 | ||
f62b8bb8 AV |
625 | MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]); |
626 | MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn); | |
627 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); | |
628 | MLX5_SET(sqc, sqc, tis_lst_sz, 1); | |
629 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); | |
630 | ||
631 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
632 | MLX5_SET(wq, wq, uar_page, sq->uar.index); | |
633 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 634 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
635 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); |
636 | ||
637 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
638 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
639 | ||
7db22ffb | 640 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); |
f62b8bb8 AV |
641 | |
642 | kvfree(in); | |
643 | ||
644 | return err; | |
645 | } | |
646 | ||
647 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) | |
648 | { | |
649 | struct mlx5e_channel *c = sq->channel; | |
650 | struct mlx5e_priv *priv = c->priv; | |
651 | struct mlx5_core_dev *mdev = priv->mdev; | |
652 | ||
653 | void *in; | |
654 | void *sqc; | |
655 | int inlen; | |
656 | int err; | |
657 | ||
658 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
659 | in = mlx5_vzalloc(inlen); | |
660 | if (!in) | |
661 | return -ENOMEM; | |
662 | ||
663 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
664 | ||
665 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
666 | MLX5_SET(sqc, sqc, state, next_state); | |
667 | ||
7db22ffb | 668 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); |
f62b8bb8 AV |
669 | |
670 | kvfree(in); | |
671 | ||
672 | return err; | |
673 | } | |
674 | ||
675 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
676 | { | |
677 | struct mlx5e_channel *c = sq->channel; | |
678 | struct mlx5e_priv *priv = c->priv; | |
679 | struct mlx5_core_dev *mdev = priv->mdev; | |
680 | ||
7db22ffb | 681 | mlx5_core_destroy_sq(mdev, sq->sqn); |
f62b8bb8 AV |
682 | } |
683 | ||
684 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
685 | int tc, | |
686 | struct mlx5e_sq_param *param, | |
687 | struct mlx5e_sq *sq) | |
688 | { | |
689 | int err; | |
690 | ||
691 | err = mlx5e_create_sq(c, tc, param, sq); | |
692 | if (err) | |
693 | return err; | |
694 | ||
695 | err = mlx5e_enable_sq(sq, param); | |
696 | if (err) | |
697 | goto err_destroy_sq; | |
698 | ||
699 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); | |
700 | if (err) | |
701 | goto err_disable_sq; | |
702 | ||
703 | set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
704 | netdev_tx_reset_queue(sq->txq); | |
705 | netif_tx_start_queue(sq->txq); | |
706 | ||
707 | return 0; | |
708 | ||
709 | err_disable_sq: | |
710 | mlx5e_disable_sq(sq); | |
711 | err_destroy_sq: | |
712 | mlx5e_destroy_sq(sq); | |
713 | ||
714 | return err; | |
715 | } | |
716 | ||
717 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
718 | { | |
719 | __netif_tx_lock_bh(txq); | |
720 | netif_tx_stop_queue(txq); | |
721 | __netif_tx_unlock_bh(txq); | |
722 | } | |
723 | ||
724 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
725 | { | |
726 | clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
727 | napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */ | |
728 | netif_tx_disable_queue(sq->txq); | |
729 | ||
730 | /* ensure hw is notified of all pending wqes */ | |
731 | if (mlx5e_sq_has_room_for(sq, 1)) | |
12be4b21 | 732 | mlx5e_send_nop(sq, true); |
f62b8bb8 AV |
733 | |
734 | mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); | |
735 | while (sq->cc != sq->pc) /* wait till sq is empty */ | |
736 | msleep(20); | |
737 | ||
738 | /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */ | |
739 | napi_synchronize(&sq->channel->napi); | |
740 | ||
741 | mlx5e_disable_sq(sq); | |
742 | mlx5e_destroy_sq(sq); | |
743 | } | |
744 | ||
745 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
746 | struct mlx5e_cq_param *param, | |
747 | struct mlx5e_cq *cq) | |
748 | { | |
749 | struct mlx5e_priv *priv = c->priv; | |
750 | struct mlx5_core_dev *mdev = priv->mdev; | |
751 | struct mlx5_core_cq *mcq = &cq->mcq; | |
752 | int eqn_not_used; | |
0b6e26ce | 753 | unsigned int irqn; |
f62b8bb8 AV |
754 | int err; |
755 | u32 i; | |
756 | ||
311c7c71 SM |
757 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
758 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
f62b8bb8 AV |
759 | param->eq_ix = c->ix; |
760 | ||
761 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
762 | &cq->wq_ctrl); | |
763 | if (err) | |
764 | return err; | |
765 | ||
766 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
767 | ||
768 | cq->napi = &c->napi; | |
769 | ||
770 | mcq->cqe_sz = 64; | |
771 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
772 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
773 | *mcq->set_ci_db = 0; | |
774 | *mcq->arm_db = 0; | |
775 | mcq->vector = param->eq_ix; | |
776 | mcq->comp = mlx5e_completion_event; | |
777 | mcq->event = mlx5e_cq_error_event; | |
778 | mcq->irqn = irqn; | |
779 | mcq->uar = &priv->cq_uar; | |
780 | ||
781 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
782 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
783 | ||
784 | cqe->op_own = 0xf1; | |
785 | } | |
786 | ||
787 | cq->channel = c; | |
50cfa25a | 788 | cq->priv = priv; |
f62b8bb8 AV |
789 | |
790 | return 0; | |
791 | } | |
792 | ||
793 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
794 | { | |
795 | mlx5_wq_destroy(&cq->wq_ctrl); | |
796 | } | |
797 | ||
798 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
799 | { | |
50cfa25a | 800 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
801 | struct mlx5_core_dev *mdev = priv->mdev; |
802 | struct mlx5_core_cq *mcq = &cq->mcq; | |
803 | ||
804 | void *in; | |
805 | void *cqc; | |
806 | int inlen; | |
0b6e26ce | 807 | unsigned int irqn_not_used; |
f62b8bb8 AV |
808 | int eqn; |
809 | int err; | |
810 | ||
811 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
812 | sizeof(u64) * cq->wq_ctrl.buf.npages; | |
813 | in = mlx5_vzalloc(inlen); | |
814 | if (!in) | |
815 | return -ENOMEM; | |
816 | ||
817 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
818 | ||
819 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
820 | ||
821 | mlx5_fill_page_array(&cq->wq_ctrl.buf, | |
822 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
823 | ||
824 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
825 | ||
826 | MLX5_SET(cqc, cqc, c_eqn, eqn); | |
827 | MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); | |
828 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 829 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
830 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
831 | ||
832 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
833 | ||
834 | kvfree(in); | |
835 | ||
836 | if (err) | |
837 | return err; | |
838 | ||
839 | mlx5e_cq_arm(cq); | |
840 | ||
841 | return 0; | |
842 | } | |
843 | ||
844 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
845 | { | |
50cfa25a | 846 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
847 | struct mlx5_core_dev *mdev = priv->mdev; |
848 | ||
849 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
850 | } | |
851 | ||
852 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
853 | struct mlx5e_cq_param *param, | |
854 | struct mlx5e_cq *cq, | |
855 | u16 moderation_usecs, | |
856 | u16 moderation_frames) | |
857 | { | |
858 | int err; | |
859 | struct mlx5e_priv *priv = c->priv; | |
860 | struct mlx5_core_dev *mdev = priv->mdev; | |
861 | ||
862 | err = mlx5e_create_cq(c, param, cq); | |
863 | if (err) | |
864 | return err; | |
865 | ||
866 | err = mlx5e_enable_cq(cq, param); | |
867 | if (err) | |
868 | goto err_destroy_cq; | |
869 | ||
7524a5d8 GP |
870 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
871 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
872 | moderation_usecs, | |
873 | moderation_frames); | |
f62b8bb8 AV |
874 | return 0; |
875 | ||
876 | err_destroy_cq: | |
877 | mlx5e_destroy_cq(cq); | |
878 | ||
879 | return err; | |
880 | } | |
881 | ||
882 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
883 | { | |
884 | mlx5e_disable_cq(cq); | |
885 | mlx5e_destroy_cq(cq); | |
886 | } | |
887 | ||
888 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
889 | { | |
890 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
891 | } | |
892 | ||
893 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
894 | struct mlx5e_channel_param *cparam) | |
895 | { | |
896 | struct mlx5e_priv *priv = c->priv; | |
897 | int err; | |
898 | int tc; | |
899 | ||
900 | for (tc = 0; tc < c->num_tc; tc++) { | |
901 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
902 | priv->params.tx_cq_moderation_usec, | |
903 | priv->params.tx_cq_moderation_pkts); | |
904 | if (err) | |
905 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
906 | } |
907 | ||
908 | return 0; | |
909 | ||
910 | err_close_tx_cqs: | |
911 | for (tc--; tc >= 0; tc--) | |
912 | mlx5e_close_cq(&c->sq[tc].cq); | |
913 | ||
914 | return err; | |
915 | } | |
916 | ||
917 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
918 | { | |
919 | int tc; | |
920 | ||
921 | for (tc = 0; tc < c->num_tc; tc++) | |
922 | mlx5e_close_cq(&c->sq[tc].cq); | |
923 | } | |
924 | ||
925 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
926 | struct mlx5e_channel_param *cparam) | |
927 | { | |
928 | int err; | |
929 | int tc; | |
930 | ||
931 | for (tc = 0; tc < c->num_tc; tc++) { | |
932 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
933 | if (err) | |
934 | goto err_close_sqs; | |
935 | } | |
936 | ||
937 | return 0; | |
938 | ||
939 | err_close_sqs: | |
940 | for (tc--; tc >= 0; tc--) | |
941 | mlx5e_close_sq(&c->sq[tc]); | |
942 | ||
943 | return err; | |
944 | } | |
945 | ||
946 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
947 | { | |
948 | int tc; | |
949 | ||
950 | for (tc = 0; tc < c->num_tc; tc++) | |
951 | mlx5e_close_sq(&c->sq[tc]); | |
952 | } | |
953 | ||
5283af89 | 954 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) |
03289b88 SM |
955 | { |
956 | int i; | |
957 | ||
958 | for (i = 0; i < MLX5E_MAX_NUM_TC; i++) | |
5283af89 RS |
959 | priv->channeltc_to_txq_map[ix][i] = |
960 | ix + i * priv->params.num_channels; | |
03289b88 SM |
961 | } |
962 | ||
f62b8bb8 AV |
963 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
964 | struct mlx5e_channel_param *cparam, | |
965 | struct mlx5e_channel **cp) | |
966 | { | |
967 | struct net_device *netdev = priv->netdev; | |
968 | int cpu = mlx5e_get_cpu(priv, ix); | |
969 | struct mlx5e_channel *c; | |
970 | int err; | |
971 | ||
972 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
973 | if (!c) | |
974 | return -ENOMEM; | |
975 | ||
976 | c->priv = priv; | |
977 | c->ix = ix; | |
978 | c->cpu = cpu; | |
979 | c->pdev = &priv->mdev->pdev->dev; | |
980 | c->netdev = priv->netdev; | |
a606b0f6 | 981 | c->mkey_be = cpu_to_be32(priv->mkey.key); |
a4418a6c | 982 | c->num_tc = priv->params.num_tc; |
f62b8bb8 | 983 | |
5283af89 | 984 | mlx5e_build_channeltc_to_txq_map(priv, ix); |
03289b88 | 985 | |
f62b8bb8 AV |
986 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
987 | ||
988 | err = mlx5e_open_tx_cqs(c, cparam); | |
989 | if (err) | |
990 | goto err_napi_del; | |
991 | ||
992 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, | |
993 | priv->params.rx_cq_moderation_usec, | |
994 | priv->params.rx_cq_moderation_pkts); | |
995 | if (err) | |
996 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
997 | |
998 | napi_enable(&c->napi); | |
999 | ||
1000 | err = mlx5e_open_sqs(c, cparam); | |
1001 | if (err) | |
1002 | goto err_disable_napi; | |
1003 | ||
1004 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); | |
1005 | if (err) | |
1006 | goto err_close_sqs; | |
1007 | ||
1008 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1009 | *cp = c; | |
1010 | ||
1011 | return 0; | |
1012 | ||
1013 | err_close_sqs: | |
1014 | mlx5e_close_sqs(c); | |
1015 | ||
1016 | err_disable_napi: | |
1017 | napi_disable(&c->napi); | |
1018 | mlx5e_close_cq(&c->rq.cq); | |
1019 | ||
1020 | err_close_tx_cqs: | |
1021 | mlx5e_close_tx_cqs(c); | |
1022 | ||
1023 | err_napi_del: | |
1024 | netif_napi_del(&c->napi); | |
7ae92ae5 | 1025 | napi_hash_del(&c->napi); |
f62b8bb8 AV |
1026 | kfree(c); |
1027 | ||
1028 | return err; | |
1029 | } | |
1030 | ||
1031 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1032 | { | |
1033 | mlx5e_close_rq(&c->rq); | |
1034 | mlx5e_close_sqs(c); | |
1035 | napi_disable(&c->napi); | |
1036 | mlx5e_close_cq(&c->rq.cq); | |
1037 | mlx5e_close_tx_cqs(c); | |
1038 | netif_napi_del(&c->napi); | |
7ae92ae5 ED |
1039 | |
1040 | napi_hash_del(&c->napi); | |
1041 | synchronize_rcu(); | |
1042 | ||
f62b8bb8 AV |
1043 | kfree(c); |
1044 | } | |
1045 | ||
1046 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1047 | struct mlx5e_rq_param *param) | |
1048 | { | |
1049 | void *rqc = param->rqc; | |
1050 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1051 | ||
1052 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1053 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
1054 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1055 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
1056 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1057 | ||
311c7c71 | 1058 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 AV |
1059 | param->wq.linear = 1; |
1060 | } | |
1061 | ||
556dd1b9 TT |
1062 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1063 | { | |
1064 | void *rqc = param->rqc; | |
1065 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1066 | ||
1067 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1068 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1069 | } | |
1070 | ||
f62b8bb8 AV |
1071 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, |
1072 | struct mlx5e_sq_param *param) | |
1073 | { | |
1074 | void *sqc = param->sqc; | |
1075 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1076 | ||
1077 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1078 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1079 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1080 | ||
311c7c71 | 1081 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
58d52291 | 1082 | param->max_inline = priv->params.tx_max_inline; |
f62b8bb8 AV |
1083 | } |
1084 | ||
1085 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1086 | struct mlx5e_cq_param *param) | |
1087 | { | |
1088 | void *cqc = param->cqc; | |
1089 | ||
1090 | MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); | |
1091 | } | |
1092 | ||
1093 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1094 | struct mlx5e_cq_param *param) | |
1095 | { | |
1096 | void *cqc = param->cqc; | |
1097 | ||
1098 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); | |
1099 | ||
1100 | mlx5e_build_common_cq_param(priv, param); | |
1101 | } | |
1102 | ||
1103 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1104 | struct mlx5e_cq_param *param) | |
1105 | { | |
1106 | void *cqc = param->cqc; | |
1107 | ||
1108 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); | |
1109 | ||
1110 | mlx5e_build_common_cq_param(priv, param); | |
1111 | } | |
1112 | ||
1113 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, | |
1114 | struct mlx5e_channel_param *cparam) | |
1115 | { | |
1116 | memset(cparam, 0, sizeof(*cparam)); | |
1117 | ||
1118 | mlx5e_build_rq_param(priv, &cparam->rq); | |
1119 | mlx5e_build_sq_param(priv, &cparam->sq); | |
1120 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); | |
1121 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
1122 | } | |
1123 | ||
1124 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1125 | { | |
1126 | struct mlx5e_channel_param cparam; | |
a4418a6c | 1127 | int nch = priv->params.num_channels; |
03289b88 | 1128 | int err = -ENOMEM; |
f62b8bb8 AV |
1129 | int i; |
1130 | int j; | |
1131 | ||
a4418a6c AS |
1132 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), |
1133 | GFP_KERNEL); | |
03289b88 | 1134 | |
a4418a6c | 1135 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, |
03289b88 SM |
1136 | sizeof(struct mlx5e_sq *), GFP_KERNEL); |
1137 | ||
1138 | if (!priv->channel || !priv->txq_to_sq_map) | |
1139 | goto err_free_txq_to_sq_map; | |
f62b8bb8 AV |
1140 | |
1141 | mlx5e_build_channel_param(priv, &cparam); | |
a4418a6c | 1142 | for (i = 0; i < nch; i++) { |
f62b8bb8 AV |
1143 | err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); |
1144 | if (err) | |
1145 | goto err_close_channels; | |
1146 | } | |
1147 | ||
a4418a6c | 1148 | for (j = 0; j < nch; j++) { |
f62b8bb8 AV |
1149 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); |
1150 | if (err) | |
1151 | goto err_close_channels; | |
1152 | } | |
1153 | ||
1154 | return 0; | |
1155 | ||
1156 | err_close_channels: | |
1157 | for (i--; i >= 0; i--) | |
1158 | mlx5e_close_channel(priv->channel[i]); | |
1159 | ||
03289b88 SM |
1160 | err_free_txq_to_sq_map: |
1161 | kfree(priv->txq_to_sq_map); | |
f62b8bb8 AV |
1162 | kfree(priv->channel); |
1163 | ||
1164 | return err; | |
1165 | } | |
1166 | ||
1167 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1168 | { | |
1169 | int i; | |
1170 | ||
1171 | for (i = 0; i < priv->params.num_channels; i++) | |
1172 | mlx5e_close_channel(priv->channel[i]); | |
1173 | ||
03289b88 | 1174 | kfree(priv->txq_to_sq_map); |
f62b8bb8 AV |
1175 | kfree(priv->channel); |
1176 | } | |
1177 | ||
2be6967c SM |
1178 | static int mlx5e_rx_hash_fn(int hfunc) |
1179 | { | |
1180 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1181 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1182 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1183 | } | |
1184 | ||
1185 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1186 | { | |
1187 | int inv = 0; | |
1188 | int i; | |
1189 | ||
1190 | for (i = 0; i < size; i++) | |
1191 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1192 | ||
1193 | return inv; | |
1194 | } | |
1195 | ||
936896e9 AS |
1196 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) |
1197 | { | |
1198 | int i; | |
1199 | ||
1200 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1201 | int ix = i; | |
1202 | ||
1203 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1204 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1205 | ||
2d75b2bc | 1206 | ix = priv->params.indirection_rqt[ix]; |
936896e9 AS |
1207 | MLX5_SET(rqtc, rqtc, rq_num[i], |
1208 | test_bit(MLX5E_STATE_OPENED, &priv->state) ? | |
1209 | priv->channel[ix]->rq.rqn : | |
1210 | priv->drop_rq.rqn); | |
1211 | } | |
1212 | } | |
1213 | ||
4cbeaff5 AS |
1214 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc, |
1215 | enum mlx5e_rqt_ix rqt_ix) | |
1216 | { | |
4cbeaff5 AS |
1217 | |
1218 | switch (rqt_ix) { | |
1219 | case MLX5E_INDIRECTION_RQT: | |
936896e9 | 1220 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); |
4cbeaff5 AS |
1221 | |
1222 | break; | |
1223 | ||
1224 | default: /* MLX5E_SINGLE_RQ_RQT */ | |
1225 | MLX5_SET(rqtc, rqtc, rq_num[0], | |
5c50368f AS |
1226 | test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1227 | priv->channel[0]->rq.rqn : | |
1228 | priv->drop_rq.rqn); | |
4cbeaff5 AS |
1229 | |
1230 | break; | |
1231 | } | |
1232 | } | |
1233 | ||
40ab6a6e | 1234 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
f62b8bb8 AV |
1235 | { |
1236 | struct mlx5_core_dev *mdev = priv->mdev; | |
1237 | u32 *in; | |
f62b8bb8 AV |
1238 | void *rqtc; |
1239 | int inlen; | |
4cbeaff5 | 1240 | int sz; |
f62b8bb8 | 1241 | int err; |
4cbeaff5 | 1242 | |
936896e9 | 1243 | sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE; |
f62b8bb8 | 1244 | |
f62b8bb8 AV |
1245 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1246 | in = mlx5_vzalloc(inlen); | |
1247 | if (!in) | |
1248 | return -ENOMEM; | |
1249 | ||
1250 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1251 | ||
1252 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1253 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1254 | ||
4cbeaff5 | 1255 | mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix); |
2be6967c | 1256 | |
4cbeaff5 | 1257 | err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]); |
f62b8bb8 AV |
1258 | |
1259 | kvfree(in); | |
1260 | ||
1261 | return err; | |
1262 | } | |
1263 | ||
2d75b2bc | 1264 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
5c50368f AS |
1265 | { |
1266 | struct mlx5_core_dev *mdev = priv->mdev; | |
1267 | u32 *in; | |
1268 | void *rqtc; | |
1269 | int inlen; | |
5c50368f AS |
1270 | int sz; |
1271 | int err; | |
1272 | ||
936896e9 | 1273 | sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE; |
5c50368f AS |
1274 | |
1275 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; | |
1276 | in = mlx5_vzalloc(inlen); | |
1277 | if (!in) | |
1278 | return -ENOMEM; | |
1279 | ||
1280 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
1281 | ||
1282 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1283 | ||
1284 | mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix); | |
1285 | ||
1286 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
1287 | ||
1288 | err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen); | |
1289 | ||
1290 | kvfree(in); | |
1291 | ||
1292 | return err; | |
1293 | } | |
1294 | ||
40ab6a6e | 1295 | static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
f62b8bb8 | 1296 | { |
4cbeaff5 | 1297 | mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]); |
f62b8bb8 AV |
1298 | } |
1299 | ||
40ab6a6e AS |
1300 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) |
1301 | { | |
1302 | mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT); | |
1303 | mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
1304 | } | |
1305 | ||
5c50368f AS |
1306 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) |
1307 | { | |
1308 | if (!priv->params.lro_en) | |
1309 | return; | |
1310 | ||
1311 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
1312 | ||
1313 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
1314 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
1315 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
1316 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
1317 | (priv->params.lro_wqe_sz - | |
1318 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
1319 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, | |
1320 | MLX5_CAP_ETH(priv->mdev, | |
d9a40271 | 1321 | lro_timer_supported_periods[2])); |
5c50368f AS |
1322 | } |
1323 | ||
bdfc028d TT |
1324 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv) |
1325 | { | |
1326 | MLX5_SET(tirc, tirc, rx_hash_fn, | |
1327 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); | |
1328 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
1329 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
1330 | rx_hash_toeplitz_key); | |
1331 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
1332 | rx_hash_toeplitz_key); | |
1333 | ||
1334 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1335 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); | |
1336 | } | |
1337 | } | |
1338 | ||
ab0394fe | 1339 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
1340 | { |
1341 | struct mlx5_core_dev *mdev = priv->mdev; | |
1342 | ||
1343 | void *in; | |
1344 | void *tirc; | |
1345 | int inlen; | |
1346 | int err; | |
ab0394fe | 1347 | int tt; |
5c50368f AS |
1348 | |
1349 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1350 | in = mlx5_vzalloc(inlen); | |
1351 | if (!in) | |
1352 | return -ENOMEM; | |
1353 | ||
1354 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
1355 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
1356 | ||
1357 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
1358 | ||
ab0394fe TT |
1359 | for (tt = 0; tt < MLX5E_NUM_TT; tt++) { |
1360 | err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen); | |
1361 | if (err) | |
1362 | break; | |
1363 | } | |
5c50368f AS |
1364 | |
1365 | kvfree(in); | |
1366 | ||
1367 | return err; | |
1368 | } | |
1369 | ||
66189961 TT |
1370 | static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev, |
1371 | u32 tirn) | |
1372 | { | |
1373 | void *in; | |
1374 | int inlen; | |
1375 | int err; | |
1376 | ||
1377 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1378 | in = mlx5_vzalloc(inlen); | |
1379 | if (!in) | |
1380 | return -ENOMEM; | |
1381 | ||
1382 | MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); | |
1383 | ||
1384 | err = mlx5_core_modify_tir(mdev, tirn, in, inlen); | |
1385 | ||
1386 | kvfree(in); | |
1387 | ||
1388 | return err; | |
1389 | } | |
1390 | ||
1391 | static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv) | |
1392 | { | |
1393 | int err; | |
1394 | int i; | |
1395 | ||
1396 | for (i = 0; i < MLX5E_NUM_TT; i++) { | |
1397 | err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev, | |
1398 | priv->tirn[i]); | |
1399 | if (err) | |
1400 | return err; | |
1401 | } | |
1402 | ||
1403 | return 0; | |
1404 | } | |
1405 | ||
cd255eff | 1406 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) |
40ab6a6e | 1407 | { |
40ab6a6e | 1408 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff | 1409 | u16 hw_mtu = MLX5E_SW2HW_MTU(mtu); |
40ab6a6e AS |
1410 | int err; |
1411 | ||
cd255eff | 1412 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
1413 | if (err) |
1414 | return err; | |
1415 | ||
cd255eff SM |
1416 | /* Update vport context MTU */ |
1417 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
1418 | return 0; | |
1419 | } | |
1420 | ||
1421 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) | |
1422 | { | |
1423 | struct mlx5_core_dev *mdev = priv->mdev; | |
1424 | u16 hw_mtu = 0; | |
1425 | int err; | |
1426 | ||
1427 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); | |
1428 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
1429 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
1430 | ||
1431 | *mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
1432 | } | |
1433 | ||
1434 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) | |
1435 | { | |
1436 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1437 | u16 mtu; | |
1438 | int err; | |
1439 | ||
1440 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
1441 | if (err) | |
1442 | return err; | |
40ab6a6e | 1443 | |
cd255eff SM |
1444 | mlx5e_query_mtu(priv, &mtu); |
1445 | if (mtu != netdev->mtu) | |
1446 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
1447 | __func__, mtu, netdev->mtu); | |
40ab6a6e | 1448 | |
cd255eff | 1449 | netdev->mtu = mtu; |
40ab6a6e AS |
1450 | return 0; |
1451 | } | |
1452 | ||
08fb1dac SM |
1453 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
1454 | { | |
1455 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1456 | int nch = priv->params.num_channels; | |
1457 | int ntc = priv->params.num_tc; | |
1458 | int tc; | |
1459 | ||
1460 | netdev_reset_tc(netdev); | |
1461 | ||
1462 | if (ntc == 1) | |
1463 | return; | |
1464 | ||
1465 | netdev_set_num_tc(netdev, ntc); | |
1466 | ||
1467 | for (tc = 0; tc < ntc; tc++) | |
1468 | netdev_set_tc_queue(netdev, tc, nch, tc * nch); | |
1469 | } | |
1470 | ||
40ab6a6e AS |
1471 | int mlx5e_open_locked(struct net_device *netdev) |
1472 | { | |
1473 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1474 | int num_txqs; | |
1475 | int err; | |
1476 | ||
1477 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
1478 | ||
08fb1dac SM |
1479 | mlx5e_netdev_set_tcs(netdev); |
1480 | ||
40ab6a6e AS |
1481 | num_txqs = priv->params.num_channels * priv->params.num_tc; |
1482 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
1483 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
1484 | ||
1485 | err = mlx5e_set_dev_port_mtu(netdev); | |
1486 | if (err) | |
343b29f3 | 1487 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1488 | |
1489 | err = mlx5e_open_channels(priv); | |
1490 | if (err) { | |
1491 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
1492 | __func__, err); | |
343b29f3 | 1493 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1494 | } |
1495 | ||
66189961 TT |
1496 | err = mlx5e_refresh_tirs_self_loopback_enable(priv); |
1497 | if (err) { | |
1498 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
1499 | __func__, err); | |
1500 | goto err_close_channels; | |
1501 | } | |
1502 | ||
40ab6a6e | 1503 | mlx5e_redirect_rqts(priv); |
ce89ef36 | 1504 | mlx5e_update_carrier(priv); |
ef9814de | 1505 | mlx5e_timestamp_init(priv); |
40ab6a6e | 1506 | |
7bb29755 | 1507 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); |
40ab6a6e | 1508 | |
9b37b07f | 1509 | return 0; |
343b29f3 | 1510 | |
66189961 TT |
1511 | err_close_channels: |
1512 | mlx5e_close_channels(priv); | |
343b29f3 AS |
1513 | err_clear_state_opened_flag: |
1514 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
1515 | return err; | |
40ab6a6e AS |
1516 | } |
1517 | ||
1518 | static int mlx5e_open(struct net_device *netdev) | |
1519 | { | |
1520 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1521 | int err; | |
1522 | ||
1523 | mutex_lock(&priv->state_lock); | |
1524 | err = mlx5e_open_locked(netdev); | |
1525 | mutex_unlock(&priv->state_lock); | |
1526 | ||
1527 | return err; | |
1528 | } | |
1529 | ||
1530 | int mlx5e_close_locked(struct net_device *netdev) | |
1531 | { | |
1532 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1533 | ||
a1985740 AS |
1534 | /* May already be CLOSED in case a previous configuration operation |
1535 | * (e.g RX/TX queue size change) that involves close&open failed. | |
1536 | */ | |
1537 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1538 | return 0; | |
1539 | ||
40ab6a6e AS |
1540 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
1541 | ||
ef9814de | 1542 | mlx5e_timestamp_cleanup(priv); |
40ab6a6e | 1543 | netif_carrier_off(priv->netdev); |
ce89ef36 | 1544 | mlx5e_redirect_rqts(priv); |
40ab6a6e AS |
1545 | mlx5e_close_channels(priv); |
1546 | ||
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | static int mlx5e_close(struct net_device *netdev) | |
1551 | { | |
1552 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1553 | int err; | |
1554 | ||
1555 | mutex_lock(&priv->state_lock); | |
1556 | err = mlx5e_close_locked(netdev); | |
1557 | mutex_unlock(&priv->state_lock); | |
1558 | ||
1559 | return err; | |
1560 | } | |
1561 | ||
1562 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
1563 | struct mlx5e_rq *rq, | |
1564 | struct mlx5e_rq_param *param) | |
1565 | { | |
1566 | struct mlx5_core_dev *mdev = priv->mdev; | |
1567 | void *rqc = param->rqc; | |
1568 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1569 | int err; | |
1570 | ||
1571 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
1572 | ||
1573 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
1574 | &rq->wq_ctrl); | |
1575 | if (err) | |
1576 | return err; | |
1577 | ||
1578 | rq->priv = priv; | |
1579 | ||
1580 | return 0; | |
1581 | } | |
1582 | ||
1583 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
1584 | struct mlx5e_cq *cq, | |
1585 | struct mlx5e_cq_param *param) | |
1586 | { | |
1587 | struct mlx5_core_dev *mdev = priv->mdev; | |
1588 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1589 | int eqn_not_used; | |
0b6e26ce | 1590 | unsigned int irqn; |
40ab6a6e AS |
1591 | int err; |
1592 | ||
1593 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1594 | &cq->wq_ctrl); | |
1595 | if (err) | |
1596 | return err; | |
1597 | ||
1598 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1599 | ||
1600 | mcq->cqe_sz = 64; | |
1601 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1602 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1603 | *mcq->set_ci_db = 0; | |
1604 | *mcq->arm_db = 0; | |
1605 | mcq->vector = param->eq_ix; | |
1606 | mcq->comp = mlx5e_completion_event; | |
1607 | mcq->event = mlx5e_cq_error_event; | |
1608 | mcq->irqn = irqn; | |
1609 | mcq->uar = &priv->cq_uar; | |
1610 | ||
1611 | cq->priv = priv; | |
1612 | ||
1613 | return 0; | |
1614 | } | |
1615 | ||
1616 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
1617 | { | |
1618 | struct mlx5e_cq_param cq_param; | |
1619 | struct mlx5e_rq_param rq_param; | |
1620 | struct mlx5e_rq *rq = &priv->drop_rq; | |
1621 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
1622 | int err; | |
1623 | ||
1624 | memset(&cq_param, 0, sizeof(cq_param)); | |
1625 | memset(&rq_param, 0, sizeof(rq_param)); | |
556dd1b9 | 1626 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e AS |
1627 | |
1628 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
1629 | if (err) | |
1630 | return err; | |
1631 | ||
1632 | err = mlx5e_enable_cq(cq, &cq_param); | |
1633 | if (err) | |
1634 | goto err_destroy_cq; | |
1635 | ||
1636 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
1637 | if (err) | |
1638 | goto err_disable_cq; | |
1639 | ||
1640 | err = mlx5e_enable_rq(rq, &rq_param); | |
1641 | if (err) | |
1642 | goto err_destroy_rq; | |
1643 | ||
1644 | return 0; | |
1645 | ||
1646 | err_destroy_rq: | |
1647 | mlx5e_destroy_rq(&priv->drop_rq); | |
1648 | ||
1649 | err_disable_cq: | |
1650 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1651 | ||
1652 | err_destroy_cq: | |
1653 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1654 | ||
1655 | return err; | |
1656 | } | |
1657 | ||
1658 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
1659 | { | |
1660 | mlx5e_disable_rq(&priv->drop_rq); | |
1661 | mlx5e_destroy_rq(&priv->drop_rq); | |
1662 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1663 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1664 | } | |
1665 | ||
1666 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
1667 | { | |
1668 | struct mlx5_core_dev *mdev = priv->mdev; | |
1669 | u32 in[MLX5_ST_SZ_DW(create_tis_in)]; | |
1670 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
1671 | ||
1672 | memset(in, 0, sizeof(in)); | |
1673 | ||
08fb1dac | 1674 | MLX5_SET(tisc, tisc, prio, tc << 1); |
40ab6a6e AS |
1675 | MLX5_SET(tisc, tisc, transport_domain, priv->tdn); |
1676 | ||
1677 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
1678 | } | |
1679 | ||
1680 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
1681 | { | |
1682 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
1683 | } | |
1684 | ||
1685 | static int mlx5e_create_tises(struct mlx5e_priv *priv) | |
1686 | { | |
1687 | int err; | |
1688 | int tc; | |
1689 | ||
08fb1dac | 1690 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) { |
40ab6a6e AS |
1691 | err = mlx5e_create_tis(priv, tc); |
1692 | if (err) | |
1693 | goto err_close_tises; | |
1694 | } | |
1695 | ||
1696 | return 0; | |
1697 | ||
1698 | err_close_tises: | |
1699 | for (tc--; tc >= 0; tc--) | |
1700 | mlx5e_destroy_tis(priv, tc); | |
1701 | ||
1702 | return err; | |
1703 | } | |
1704 | ||
1705 | static void mlx5e_destroy_tises(struct mlx5e_priv *priv) | |
1706 | { | |
1707 | int tc; | |
1708 | ||
08fb1dac | 1709 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) |
40ab6a6e AS |
1710 | mlx5e_destroy_tis(priv, tc); |
1711 | } | |
1712 | ||
f62b8bb8 AV |
1713 | static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt) |
1714 | { | |
1715 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1716 | ||
3191e05f AS |
1717 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
1718 | ||
5a6f8aef AS |
1719 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1720 | MLX5_HASH_FIELD_SEL_DST_IP) | |
f62b8bb8 | 1721 | |
5a6f8aef AS |
1722 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1723 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1724 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
1725 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
f62b8bb8 | 1726 | |
a741749f AS |
1727 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1728 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1729 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
1730 | ||
5c50368f | 1731 | mlx5e_build_tir_ctx_lro(tirc, priv); |
f62b8bb8 | 1732 | |
4cbeaff5 AS |
1733 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
1734 | ||
f62b8bb8 AV |
1735 | switch (tt) { |
1736 | case MLX5E_TT_ANY: | |
4cbeaff5 AS |
1737 | MLX5_SET(tirc, tirc, indirect_table, |
1738 | priv->rqtn[MLX5E_SINGLE_RQ_RQT]); | |
1739 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
f62b8bb8 AV |
1740 | break; |
1741 | default: | |
f62b8bb8 | 1742 | MLX5_SET(tirc, tirc, indirect_table, |
4cbeaff5 | 1743 | priv->rqtn[MLX5E_INDIRECTION_RQT]); |
bdfc028d | 1744 | mlx5e_build_tir_ctx_hash(tirc, priv); |
f62b8bb8 AV |
1745 | break; |
1746 | } | |
1747 | ||
1748 | switch (tt) { | |
1749 | case MLX5E_TT_IPV4_TCP: | |
1750 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1751 | MLX5_L3_PROT_TYPE_IPV4); | |
1752 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1753 | MLX5_L4_PROT_TYPE_TCP); | |
1754 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1755 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1756 | break; |
1757 | ||
1758 | case MLX5E_TT_IPV6_TCP: | |
1759 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1760 | MLX5_L3_PROT_TYPE_IPV6); | |
1761 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1762 | MLX5_L4_PROT_TYPE_TCP); | |
1763 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1764 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1765 | break; |
1766 | ||
1767 | case MLX5E_TT_IPV4_UDP: | |
1768 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1769 | MLX5_L3_PROT_TYPE_IPV4); | |
1770 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1771 | MLX5_L4_PROT_TYPE_UDP); | |
1772 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1773 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1774 | break; |
1775 | ||
1776 | case MLX5E_TT_IPV6_UDP: | |
1777 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1778 | MLX5_L3_PROT_TYPE_IPV6); | |
1779 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1780 | MLX5_L4_PROT_TYPE_UDP); | |
1781 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1782 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1783 | break; |
1784 | ||
a741749f AS |
1785 | case MLX5E_TT_IPV4_IPSEC_AH: |
1786 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1787 | MLX5_L3_PROT_TYPE_IPV4); | |
1788 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1789 | MLX5_HASH_IP_IPSEC_SPI); | |
1790 | break; | |
1791 | ||
1792 | case MLX5E_TT_IPV6_IPSEC_AH: | |
1793 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1794 | MLX5_L3_PROT_TYPE_IPV6); | |
1795 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1796 | MLX5_HASH_IP_IPSEC_SPI); | |
1797 | break; | |
1798 | ||
1799 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
1800 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1801 | MLX5_L3_PROT_TYPE_IPV4); | |
1802 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1803 | MLX5_HASH_IP_IPSEC_SPI); | |
1804 | break; | |
1805 | ||
1806 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
1807 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1808 | MLX5_L3_PROT_TYPE_IPV6); | |
1809 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1810 | MLX5_HASH_IP_IPSEC_SPI); | |
1811 | break; | |
1812 | ||
f62b8bb8 AV |
1813 | case MLX5E_TT_IPV4: |
1814 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1815 | MLX5_L3_PROT_TYPE_IPV4); | |
1816 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1817 | MLX5_HASH_IP); | |
1818 | break; | |
1819 | ||
1820 | case MLX5E_TT_IPV6: | |
1821 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1822 | MLX5_L3_PROT_TYPE_IPV6); | |
1823 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1824 | MLX5_HASH_IP); | |
1825 | break; | |
1826 | } | |
1827 | } | |
1828 | ||
40ab6a6e | 1829 | static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt) |
f62b8bb8 AV |
1830 | { |
1831 | struct mlx5_core_dev *mdev = priv->mdev; | |
1832 | u32 *in; | |
1833 | void *tirc; | |
1834 | int inlen; | |
1835 | int err; | |
1836 | ||
1837 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1838 | in = mlx5_vzalloc(inlen); | |
1839 | if (!in) | |
1840 | return -ENOMEM; | |
1841 | ||
1842 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
1843 | ||
1844 | mlx5e_build_tir_ctx(priv, tirc, tt); | |
1845 | ||
7db22ffb | 1846 | err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); |
f62b8bb8 AV |
1847 | |
1848 | kvfree(in); | |
1849 | ||
1850 | return err; | |
1851 | } | |
1852 | ||
40ab6a6e | 1853 | static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt) |
f62b8bb8 | 1854 | { |
7db22ffb | 1855 | mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); |
f62b8bb8 AV |
1856 | } |
1857 | ||
40ab6a6e | 1858 | static int mlx5e_create_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
1859 | { |
1860 | int err; | |
1861 | int i; | |
1862 | ||
1863 | for (i = 0; i < MLX5E_NUM_TT; i++) { | |
40ab6a6e | 1864 | err = mlx5e_create_tir(priv, i); |
f62b8bb8 | 1865 | if (err) |
40ab6a6e | 1866 | goto err_destroy_tirs; |
f62b8bb8 AV |
1867 | } |
1868 | ||
1869 | return 0; | |
1870 | ||
40ab6a6e | 1871 | err_destroy_tirs: |
f62b8bb8 | 1872 | for (i--; i >= 0; i--) |
40ab6a6e | 1873 | mlx5e_destroy_tir(priv, i); |
f62b8bb8 AV |
1874 | |
1875 | return err; | |
1876 | } | |
1877 | ||
40ab6a6e | 1878 | static void mlx5e_destroy_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
1879 | { |
1880 | int i; | |
1881 | ||
1882 | for (i = 0; i < MLX5E_NUM_TT; i++) | |
40ab6a6e | 1883 | mlx5e_destroy_tir(priv, i); |
f62b8bb8 AV |
1884 | } |
1885 | ||
08fb1dac SM |
1886 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) |
1887 | { | |
1888 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1889 | bool was_opened; | |
1890 | int err = 0; | |
1891 | ||
1892 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
1893 | return -EINVAL; | |
1894 | ||
1895 | mutex_lock(&priv->state_lock); | |
1896 | ||
1897 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
1898 | if (was_opened) | |
1899 | mlx5e_close_locked(priv->netdev); | |
1900 | ||
1901 | priv->params.num_tc = tc ? tc : 1; | |
1902 | ||
1903 | if (was_opened) | |
1904 | err = mlx5e_open_locked(priv->netdev); | |
1905 | ||
1906 | mutex_unlock(&priv->state_lock); | |
1907 | ||
1908 | return err; | |
1909 | } | |
1910 | ||
1911 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
1912 | __be16 proto, struct tc_to_netdev *tc) | |
1913 | { | |
e8f887ac AV |
1914 | struct mlx5e_priv *priv = netdev_priv(dev); |
1915 | ||
1916 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS)) | |
1917 | goto mqprio; | |
1918 | ||
1919 | switch (tc->type) { | |
e3a2b7ed AV |
1920 | case TC_SETUP_CLSFLOWER: |
1921 | switch (tc->cls_flower->command) { | |
1922 | case TC_CLSFLOWER_REPLACE: | |
1923 | return mlx5e_configure_flower(priv, proto, tc->cls_flower); | |
1924 | case TC_CLSFLOWER_DESTROY: | |
1925 | return mlx5e_delete_flower(priv, tc->cls_flower); | |
1926 | } | |
e8f887ac AV |
1927 | default: |
1928 | return -EOPNOTSUPP; | |
1929 | } | |
1930 | ||
1931 | mqprio: | |
67ba422e | 1932 | if (tc->type != TC_SETUP_MQPRIO) |
08fb1dac SM |
1933 | return -EINVAL; |
1934 | ||
1935 | return mlx5e_setup_tc(dev, tc->tc); | |
1936 | } | |
1937 | ||
f62b8bb8 AV |
1938 | static struct rtnl_link_stats64 * |
1939 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
1940 | { | |
1941 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1942 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; | |
1943 | ||
1944 | stats->rx_packets = vstats->rx_packets; | |
1945 | stats->rx_bytes = vstats->rx_bytes; | |
1946 | stats->tx_packets = vstats->tx_packets; | |
1947 | stats->tx_bytes = vstats->tx_bytes; | |
1948 | stats->multicast = vstats->rx_multicast_packets + | |
1949 | vstats->tx_multicast_packets; | |
1950 | stats->tx_errors = vstats->tx_error_packets; | |
1951 | stats->rx_errors = vstats->rx_error_packets; | |
1952 | stats->tx_dropped = vstats->tx_queue_dropped; | |
1953 | stats->rx_crc_errors = 0; | |
1954 | stats->rx_length_errors = 0; | |
1955 | ||
1956 | return stats; | |
1957 | } | |
1958 | ||
1959 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
1960 | { | |
1961 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1962 | ||
7bb29755 | 1963 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
1964 | } |
1965 | ||
1966 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
1967 | { | |
1968 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1969 | struct sockaddr *saddr = addr; | |
1970 | ||
1971 | if (!is_valid_ether_addr(saddr->sa_data)) | |
1972 | return -EADDRNOTAVAIL; | |
1973 | ||
1974 | netif_addr_lock_bh(netdev); | |
1975 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
1976 | netif_addr_unlock_bh(netdev); | |
1977 | ||
7bb29755 | 1978 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
1979 | |
1980 | return 0; | |
1981 | } | |
1982 | ||
1983 | static int mlx5e_set_features(struct net_device *netdev, | |
1984 | netdev_features_t features) | |
1985 | { | |
1986 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
98e81b0a | 1987 | int err = 0; |
f62b8bb8 | 1988 | netdev_features_t changes = features ^ netdev->features; |
f62b8bb8 AV |
1989 | |
1990 | mutex_lock(&priv->state_lock); | |
f62b8bb8 AV |
1991 | |
1992 | if (changes & NETIF_F_LRO) { | |
98e81b0a AS |
1993 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
1994 | ||
1995 | if (was_opened) | |
1996 | mlx5e_close_locked(priv->netdev); | |
f62b8bb8 | 1997 | |
98e81b0a | 1998 | priv->params.lro_en = !!(features & NETIF_F_LRO); |
ab0394fe TT |
1999 | err = mlx5e_modify_tirs_lro(priv); |
2000 | if (err) | |
2001 | mlx5_core_warn(priv->mdev, "lro modify failed, %d\n", | |
2002 | err); | |
98e81b0a AS |
2003 | |
2004 | if (was_opened) | |
2005 | err = mlx5e_open_locked(priv->netdev); | |
2006 | } | |
f62b8bb8 | 2007 | |
9b37b07f AS |
2008 | mutex_unlock(&priv->state_lock); |
2009 | ||
f62b8bb8 AV |
2010 | if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) { |
2011 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) | |
2012 | mlx5e_enable_vlan_filter(priv); | |
2013 | else | |
2014 | mlx5e_disable_vlan_filter(priv); | |
2015 | } | |
2016 | ||
e8f887ac AV |
2017 | if ((changes & NETIF_F_HW_TC) && !(features & NETIF_F_HW_TC) && |
2018 | mlx5e_tc_num_filters(priv)) { | |
2019 | netdev_err(netdev, | |
2020 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
2021 | return -EINVAL; | |
2022 | } | |
2023 | ||
fe9f4fe5 | 2024 | return err; |
f62b8bb8 AV |
2025 | } |
2026 | ||
d8edd246 SM |
2027 | #define MXL5_HW_MIN_MTU 64 |
2028 | #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN) | |
2029 | ||
f62b8bb8 AV |
2030 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
2031 | { | |
2032 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2033 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 2034 | bool was_opened; |
046339ea | 2035 | u16 max_mtu; |
d8edd246 | 2036 | u16 min_mtu; |
98e81b0a | 2037 | int err = 0; |
f62b8bb8 | 2038 | |
facc9699 | 2039 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
f62b8bb8 | 2040 | |
50a9eea6 | 2041 | max_mtu = MLX5E_HW2SW_MTU(max_mtu); |
d8edd246 | 2042 | min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU); |
50a9eea6 | 2043 | |
d8edd246 | 2044 | if (new_mtu > max_mtu || new_mtu < min_mtu) { |
facc9699 | 2045 | netdev_err(netdev, |
d8edd246 SM |
2046 | "%s: Bad MTU (%d), valid range is: [%d..%d]\n", |
2047 | __func__, new_mtu, min_mtu, max_mtu); | |
f62b8bb8 AV |
2048 | return -EINVAL; |
2049 | } | |
2050 | ||
2051 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
2052 | |
2053 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2054 | if (was_opened) | |
2055 | mlx5e_close_locked(netdev); | |
2056 | ||
f62b8bb8 | 2057 | netdev->mtu = new_mtu; |
98e81b0a AS |
2058 | |
2059 | if (was_opened) | |
2060 | err = mlx5e_open_locked(netdev); | |
2061 | ||
f62b8bb8 AV |
2062 | mutex_unlock(&priv->state_lock); |
2063 | ||
2064 | return err; | |
2065 | } | |
2066 | ||
ef9814de EBE |
2067 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2068 | { | |
2069 | switch (cmd) { | |
2070 | case SIOCSHWTSTAMP: | |
2071 | return mlx5e_hwstamp_set(dev, ifr); | |
2072 | case SIOCGHWTSTAMP: | |
2073 | return mlx5e_hwstamp_get(dev, ifr); | |
2074 | default: | |
2075 | return -EOPNOTSUPP; | |
2076 | } | |
2077 | } | |
2078 | ||
66e49ded SM |
2079 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2080 | { | |
2081 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2082 | struct mlx5_core_dev *mdev = priv->mdev; | |
2083 | ||
2084 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2085 | } | |
2086 | ||
2087 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) | |
2088 | { | |
2089 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2090 | struct mlx5_core_dev *mdev = priv->mdev; | |
2091 | ||
2092 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
2093 | vlan, qos); | |
2094 | } | |
2095 | ||
2096 | static int mlx5_vport_link2ifla(u8 esw_link) | |
2097 | { | |
2098 | switch (esw_link) { | |
2099 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
2100 | return IFLA_VF_LINK_STATE_DISABLE; | |
2101 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
2102 | return IFLA_VF_LINK_STATE_ENABLE; | |
2103 | } | |
2104 | return IFLA_VF_LINK_STATE_AUTO; | |
2105 | } | |
2106 | ||
2107 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
2108 | { | |
2109 | switch (ifla_link) { | |
2110 | case IFLA_VF_LINK_STATE_DISABLE: | |
2111 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
2112 | case IFLA_VF_LINK_STATE_ENABLE: | |
2113 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
2114 | } | |
2115 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
2116 | } | |
2117 | ||
2118 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
2119 | int link_state) | |
2120 | { | |
2121 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2122 | struct mlx5_core_dev *mdev = priv->mdev; | |
2123 | ||
2124 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
2125 | mlx5_ifla_link2vport(link_state)); | |
2126 | } | |
2127 | ||
2128 | static int mlx5e_get_vf_config(struct net_device *dev, | |
2129 | int vf, struct ifla_vf_info *ivi) | |
2130 | { | |
2131 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2132 | struct mlx5_core_dev *mdev = priv->mdev; | |
2133 | int err; | |
2134 | ||
2135 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
2136 | if (err) | |
2137 | return err; | |
2138 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
2139 | return 0; | |
2140 | } | |
2141 | ||
2142 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
2143 | int vf, struct ifla_vf_stats *vf_stats) | |
2144 | { | |
2145 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2146 | struct mlx5_core_dev *mdev = priv->mdev; | |
2147 | ||
2148 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
2149 | vf_stats); | |
2150 | } | |
2151 | ||
b3f63c3d MF |
2152 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
2153 | sa_family_t sa_family, __be16 port) | |
2154 | { | |
2155 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2156 | ||
2157 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2158 | return; | |
2159 | ||
d8cf2dda | 2160 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1); |
b3f63c3d MF |
2161 | } |
2162 | ||
2163 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
2164 | sa_family_t sa_family, __be16 port) | |
2165 | { | |
2166 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2167 | ||
2168 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2169 | return; | |
2170 | ||
d8cf2dda | 2171 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0); |
b3f63c3d MF |
2172 | } |
2173 | ||
2174 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
2175 | struct sk_buff *skb, | |
2176 | netdev_features_t features) | |
2177 | { | |
2178 | struct udphdr *udph; | |
2179 | u16 proto; | |
2180 | u16 port = 0; | |
2181 | ||
2182 | switch (vlan_get_protocol(skb)) { | |
2183 | case htons(ETH_P_IP): | |
2184 | proto = ip_hdr(skb)->protocol; | |
2185 | break; | |
2186 | case htons(ETH_P_IPV6): | |
2187 | proto = ipv6_hdr(skb)->nexthdr; | |
2188 | break; | |
2189 | default: | |
2190 | goto out; | |
2191 | } | |
2192 | ||
2193 | if (proto == IPPROTO_UDP) { | |
2194 | udph = udp_hdr(skb); | |
2195 | port = be16_to_cpu(udph->dest); | |
2196 | } | |
2197 | ||
2198 | /* Verify if UDP port is being offloaded by HW */ | |
2199 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
2200 | return features; | |
2201 | ||
2202 | out: | |
2203 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
2204 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2205 | } | |
2206 | ||
2207 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
2208 | struct net_device *netdev, | |
2209 | netdev_features_t features) | |
2210 | { | |
2211 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2212 | ||
2213 | features = vlan_features_check(skb, features); | |
2214 | features = vxlan_features_check(skb, features); | |
2215 | ||
2216 | /* Validate if the tunneled packet is being offloaded by HW */ | |
2217 | if (skb->encapsulation && | |
2218 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
2219 | return mlx5e_vxlan_features_check(priv, skb, features); | |
2220 | ||
2221 | return features; | |
2222 | } | |
2223 | ||
b0eed40e | 2224 | static const struct net_device_ops mlx5e_netdev_ops_basic = { |
f62b8bb8 AV |
2225 | .ndo_open = mlx5e_open, |
2226 | .ndo_stop = mlx5e_close, | |
2227 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2228 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2229 | .ndo_select_queue = mlx5e_select_queue, | |
f62b8bb8 AV |
2230 | .ndo_get_stats64 = mlx5e_get_stats, |
2231 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2232 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
2233 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
2234 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 2235 | .ndo_set_features = mlx5e_set_features, |
b0eed40e SM |
2236 | .ndo_change_mtu = mlx5e_change_mtu, |
2237 | .ndo_do_ioctl = mlx5e_ioctl, | |
2238 | }; | |
2239 | ||
2240 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
2241 | .ndo_open = mlx5e_open, | |
2242 | .ndo_stop = mlx5e_close, | |
2243 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2244 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2245 | .ndo_select_queue = mlx5e_select_queue, | |
b0eed40e SM |
2246 | .ndo_get_stats64 = mlx5e_get_stats, |
2247 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2248 | .ndo_set_mac_address = mlx5e_set_mac, | |
2249 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
2250 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
2251 | .ndo_set_features = mlx5e_set_features, | |
2252 | .ndo_change_mtu = mlx5e_change_mtu, | |
2253 | .ndo_do_ioctl = mlx5e_ioctl, | |
b3f63c3d MF |
2254 | .ndo_add_vxlan_port = mlx5e_add_vxlan_port, |
2255 | .ndo_del_vxlan_port = mlx5e_del_vxlan_port, | |
2256 | .ndo_features_check = mlx5e_features_check, | |
b0eed40e SM |
2257 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
2258 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
2259 | .ndo_get_vf_config = mlx5e_get_vf_config, | |
2260 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
2261 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
f62b8bb8 AV |
2262 | }; |
2263 | ||
2264 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
2265 | { | |
2266 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
2267 | return -ENOTSUPP; | |
2268 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
2269 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
2270 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
2271 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
2272 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
2273 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
2274 | MLX5_CAP_FLOWTABLE(mdev, | |
2275 | flow_table_properties_nic_receive.max_ft_level) | |
2276 | < 3) { | |
f62b8bb8 AV |
2277 | mlx5_core_warn(mdev, |
2278 | "Not creating net device, some required device capabilities are missing\n"); | |
2279 | return -ENOTSUPP; | |
2280 | } | |
66189961 TT |
2281 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
2282 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 GP |
2283 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
2284 | mlx5_core_warn(mdev, "CQ modiration is not supported\n"); | |
66189961 | 2285 | |
f62b8bb8 AV |
2286 | return 0; |
2287 | } | |
2288 | ||
58d52291 AS |
2289 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
2290 | { | |
2291 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
2292 | ||
2293 | return bf_buf_size - | |
2294 | sizeof(struct mlx5e_tx_wqe) + | |
2295 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
2296 | } | |
2297 | ||
08fb1dac SM |
2298 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2299 | static void mlx5e_ets_init(struct mlx5e_priv *priv) | |
2300 | { | |
2301 | int i; | |
2302 | ||
2303 | priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1; | |
2304 | for (i = 0; i < priv->params.ets.ets_cap; i++) { | |
2305 | priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC; | |
2306 | priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR; | |
2307 | priv->params.ets.prio_tc[i] = i; | |
2308 | } | |
2309 | ||
2310 | /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */ | |
2311 | priv->params.ets.prio_tc[0] = 1; | |
2312 | priv->params.ets.prio_tc[1] = 0; | |
2313 | } | |
2314 | #endif | |
2315 | ||
85082dba TT |
2316 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
2317 | int num_channels) | |
2318 | { | |
2319 | int i; | |
2320 | ||
2321 | for (i = 0; i < len; i++) | |
2322 | indirection_rqt[i] = i % num_channels; | |
2323 | } | |
2324 | ||
f62b8bb8 AV |
2325 | static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, |
2326 | struct net_device *netdev, | |
936896e9 | 2327 | int num_channels) |
f62b8bb8 AV |
2328 | { |
2329 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2330 | ||
2331 | priv->params.log_sq_size = | |
2332 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
2333 | priv->params.log_rq_size = | |
2334 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2335 | priv->params.rx_cq_moderation_usec = | |
2336 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
2337 | priv->params.rx_cq_moderation_pkts = | |
2338 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
2339 | priv->params.tx_cq_moderation_usec = | |
2340 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
2341 | priv->params.tx_cq_moderation_pkts = | |
2342 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
58d52291 | 2343 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); |
f62b8bb8 AV |
2344 | priv->params.min_rx_wqes = |
2345 | MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; | |
f62b8bb8 | 2346 | priv->params.num_tc = 1; |
2be6967c | 2347 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; |
f62b8bb8 | 2348 | |
57afead5 AS |
2349 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, |
2350 | sizeof(priv->params.toeplitz_hash_key)); | |
2351 | ||
85082dba TT |
2352 | mlx5e_build_default_indir_rqt(priv->params.indirection_rqt, |
2353 | MLX5E_INDIR_RQT_SIZE, num_channels); | |
2d75b2bc | 2354 | |
f62b8bb8 AV |
2355 | priv->params.lro_wqe_sz = |
2356 | MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
2357 | ||
2358 | priv->mdev = mdev; | |
2359 | priv->netdev = netdev; | |
936896e9 | 2360 | priv->params.num_channels = num_channels; |
f62b8bb8 | 2361 | |
08fb1dac SM |
2362 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2363 | mlx5e_ets_init(priv); | |
2364 | #endif | |
f62b8bb8 | 2365 | |
f62b8bb8 AV |
2366 | mutex_init(&priv->state_lock); |
2367 | ||
2368 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
2369 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
2370 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); | |
2371 | } | |
2372 | ||
2373 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
2374 | { | |
2375 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2376 | ||
e1d7d349 | 2377 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
2378 | if (is_zero_ether_addr(netdev->dev_addr) && |
2379 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
2380 | eth_hw_addr_random(netdev); | |
2381 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
2382 | } | |
f62b8bb8 AV |
2383 | } |
2384 | ||
2385 | static void mlx5e_build_netdev(struct net_device *netdev) | |
2386 | { | |
2387 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2388 | struct mlx5_core_dev *mdev = priv->mdev; | |
2389 | ||
2390 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
2391 | ||
08fb1dac | 2392 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { |
b0eed40e | 2393 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; |
08fb1dac SM |
2394 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2395 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
2396 | #endif | |
2397 | } else { | |
b0eed40e | 2398 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; |
08fb1dac | 2399 | } |
66e49ded | 2400 | |
f62b8bb8 AV |
2401 | netdev->watchdog_timeo = 15 * HZ; |
2402 | ||
2403 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
2404 | ||
12be4b21 | 2405 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
2406 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
2407 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
2408 | netdev->vlan_features |= NETIF_F_GRO; | |
2409 | netdev->vlan_features |= NETIF_F_TSO; | |
2410 | netdev->vlan_features |= NETIF_F_TSO6; | |
2411 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
2412 | netdev->vlan_features |= NETIF_F_RXHASH; | |
2413 | ||
2414 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
2415 | netdev->vlan_features |= NETIF_F_LRO; | |
2416 | ||
2417 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 2418 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
2419 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
2420 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
2421 | ||
b3f63c3d MF |
2422 | if (mlx5e_vxlan_allowed(mdev)) { |
2423 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL; | |
2424 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; | |
2425 | netdev->hw_enc_features |= NETIF_F_RXCSUM; | |
2426 | netdev->hw_enc_features |= NETIF_F_TSO; | |
2427 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
2428 | netdev->hw_enc_features |= NETIF_F_RXHASH; | |
2429 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; | |
2430 | } | |
2431 | ||
f62b8bb8 AV |
2432 | netdev->features = netdev->hw_features; |
2433 | if (!priv->params.lro_en) | |
2434 | netdev->features &= ~NETIF_F_LRO; | |
2435 | ||
e8f887ac AV |
2436 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
2437 | if (FT_CAP(flow_modify_en) && | |
2438 | FT_CAP(modify_root) && | |
2439 | FT_CAP(identified_miss_table_mode) && | |
2440 | FT_CAP(flow_table_modify)) | |
2441 | priv->netdev->hw_features |= NETIF_F_HW_TC; | |
2442 | ||
f62b8bb8 AV |
2443 | netdev->features |= NETIF_F_HIGHDMA; |
2444 | ||
2445 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
2446 | ||
2447 | mlx5e_set_netdev_dev_addr(netdev); | |
2448 | } | |
2449 | ||
2450 | static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, | |
a606b0f6 | 2451 | struct mlx5_core_mkey *mkey) |
f62b8bb8 AV |
2452 | { |
2453 | struct mlx5_core_dev *mdev = priv->mdev; | |
2454 | struct mlx5_create_mkey_mbox_in *in; | |
2455 | int err; | |
2456 | ||
2457 | in = mlx5_vzalloc(sizeof(*in)); | |
2458 | if (!in) | |
2459 | return -ENOMEM; | |
2460 | ||
2461 | in->seg.flags = MLX5_PERM_LOCAL_WRITE | | |
2462 | MLX5_PERM_LOCAL_READ | | |
2463 | MLX5_ACCESS_MODE_PA; | |
2464 | in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); | |
2465 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
2466 | ||
a606b0f6 | 2467 | err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL, |
f62b8bb8 AV |
2468 | NULL); |
2469 | ||
2470 | kvfree(in); | |
2471 | ||
2472 | return err; | |
2473 | } | |
2474 | ||
2475 | static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) | |
2476 | { | |
2477 | struct net_device *netdev; | |
2478 | struct mlx5e_priv *priv; | |
3435ab59 | 2479 | int nch = mlx5e_get_max_num_channels(mdev); |
f62b8bb8 AV |
2480 | int err; |
2481 | ||
2482 | if (mlx5e_check_required_hca_cap(mdev)) | |
2483 | return NULL; | |
2484 | ||
08fb1dac SM |
2485 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
2486 | nch * MLX5E_MAX_NUM_TC, | |
2487 | nch); | |
f62b8bb8 AV |
2488 | if (!netdev) { |
2489 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
2490 | return NULL; | |
2491 | } | |
2492 | ||
936896e9 | 2493 | mlx5e_build_netdev_priv(mdev, netdev, nch); |
f62b8bb8 AV |
2494 | mlx5e_build_netdev(netdev); |
2495 | ||
2496 | netif_carrier_off(netdev); | |
2497 | ||
2498 | priv = netdev_priv(netdev); | |
2499 | ||
7bb29755 MF |
2500 | priv->wq = create_singlethread_workqueue("mlx5e"); |
2501 | if (!priv->wq) | |
2502 | goto err_free_netdev; | |
2503 | ||
0ba42241 | 2504 | err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false); |
f62b8bb8 | 2505 | if (err) { |
1f2a3003 | 2506 | mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err); |
7bb29755 | 2507 | goto err_destroy_wq; |
f62b8bb8 AV |
2508 | } |
2509 | ||
2510 | err = mlx5_core_alloc_pd(mdev, &priv->pdn); | |
2511 | if (err) { | |
1f2a3003 | 2512 | mlx5_core_err(mdev, "alloc pd failed, %d\n", err); |
f62b8bb8 AV |
2513 | goto err_unmap_free_uar; |
2514 | } | |
2515 | ||
8d7f9ecb | 2516 | err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn); |
3191e05f | 2517 | if (err) { |
1f2a3003 | 2518 | mlx5_core_err(mdev, "alloc td failed, %d\n", err); |
3191e05f AS |
2519 | goto err_dealloc_pd; |
2520 | } | |
2521 | ||
a606b0f6 | 2522 | err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey); |
f62b8bb8 | 2523 | if (err) { |
1f2a3003 | 2524 | mlx5_core_err(mdev, "create mkey failed, %d\n", err); |
3191e05f | 2525 | goto err_dealloc_transport_domain; |
f62b8bb8 AV |
2526 | } |
2527 | ||
40ab6a6e | 2528 | err = mlx5e_create_tises(priv); |
5c50368f | 2529 | if (err) { |
40ab6a6e | 2530 | mlx5_core_warn(mdev, "create tises failed, %d\n", err); |
5c50368f AS |
2531 | goto err_destroy_mkey; |
2532 | } | |
2533 | ||
2534 | err = mlx5e_open_drop_rq(priv); | |
2535 | if (err) { | |
2536 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
40ab6a6e | 2537 | goto err_destroy_tises; |
5c50368f AS |
2538 | } |
2539 | ||
40ab6a6e | 2540 | err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT); |
5c50368f | 2541 | if (err) { |
40ab6a6e | 2542 | mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err); |
5c50368f AS |
2543 | goto err_close_drop_rq; |
2544 | } | |
2545 | ||
40ab6a6e | 2546 | err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT); |
5c50368f | 2547 | if (err) { |
40ab6a6e AS |
2548 | mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err); |
2549 | goto err_destroy_rqt_indir; | |
5c50368f AS |
2550 | } |
2551 | ||
40ab6a6e | 2552 | err = mlx5e_create_tirs(priv); |
5c50368f | 2553 | if (err) { |
40ab6a6e AS |
2554 | mlx5_core_warn(mdev, "create tirs failed, %d\n", err); |
2555 | goto err_destroy_rqt_single; | |
5c50368f AS |
2556 | } |
2557 | ||
40ab6a6e | 2558 | err = mlx5e_create_flow_tables(priv); |
5c50368f | 2559 | if (err) { |
40ab6a6e AS |
2560 | mlx5_core_warn(mdev, "create flow tables failed, %d\n", err); |
2561 | goto err_destroy_tirs; | |
5c50368f AS |
2562 | } |
2563 | ||
2564 | mlx5e_init_eth_addr(priv); | |
2565 | ||
b3f63c3d MF |
2566 | mlx5e_vxlan_init(priv); |
2567 | ||
e8f887ac AV |
2568 | err = mlx5e_tc_init(priv); |
2569 | if (err) | |
2570 | goto err_destroy_flow_tables; | |
2571 | ||
08fb1dac SM |
2572 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2573 | mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets); | |
2574 | #endif | |
2575 | ||
f62b8bb8 AV |
2576 | err = register_netdev(netdev); |
2577 | if (err) { | |
1f2a3003 | 2578 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
e8f887ac | 2579 | goto err_tc_cleanup; |
f62b8bb8 AV |
2580 | } |
2581 | ||
b3f63c3d MF |
2582 | if (mlx5e_vxlan_allowed(mdev)) |
2583 | vxlan_get_rx_port(netdev); | |
2584 | ||
f62b8bb8 | 2585 | mlx5e_enable_async_events(priv); |
7bb29755 | 2586 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2587 | |
2588 | return priv; | |
2589 | ||
e8f887ac AV |
2590 | err_tc_cleanup: |
2591 | mlx5e_tc_cleanup(priv); | |
2592 | ||
40ab6a6e AS |
2593 | err_destroy_flow_tables: |
2594 | mlx5e_destroy_flow_tables(priv); | |
5c50368f | 2595 | |
40ab6a6e AS |
2596 | err_destroy_tirs: |
2597 | mlx5e_destroy_tirs(priv); | |
5c50368f | 2598 | |
40ab6a6e AS |
2599 | err_destroy_rqt_single: |
2600 | mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
5c50368f | 2601 | |
40ab6a6e AS |
2602 | err_destroy_rqt_indir: |
2603 | mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT); | |
5c50368f AS |
2604 | |
2605 | err_close_drop_rq: | |
2606 | mlx5e_close_drop_rq(priv); | |
2607 | ||
40ab6a6e AS |
2608 | err_destroy_tises: |
2609 | mlx5e_destroy_tises(priv); | |
5c50368f | 2610 | |
f62b8bb8 | 2611 | err_destroy_mkey: |
a606b0f6 | 2612 | mlx5_core_destroy_mkey(mdev, &priv->mkey); |
f62b8bb8 | 2613 | |
3191e05f | 2614 | err_dealloc_transport_domain: |
8d7f9ecb | 2615 | mlx5_core_dealloc_transport_domain(mdev, priv->tdn); |
3191e05f | 2616 | |
f62b8bb8 AV |
2617 | err_dealloc_pd: |
2618 | mlx5_core_dealloc_pd(mdev, priv->pdn); | |
2619 | ||
2620 | err_unmap_free_uar: | |
2621 | mlx5_unmap_free_uar(mdev, &priv->cq_uar); | |
2622 | ||
7bb29755 MF |
2623 | err_destroy_wq: |
2624 | destroy_workqueue(priv->wq); | |
2625 | ||
f62b8bb8 AV |
2626 | err_free_netdev: |
2627 | free_netdev(netdev); | |
2628 | ||
2629 | return NULL; | |
2630 | } | |
2631 | ||
2632 | static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv) | |
2633 | { | |
2634 | struct mlx5e_priv *priv = vpriv; | |
2635 | struct net_device *netdev = priv->netdev; | |
2636 | ||
9b37b07f AS |
2637 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
2638 | ||
7bb29755 | 2639 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1cefa326 | 2640 | mlx5e_disable_async_events(priv); |
7bb29755 | 2641 | flush_workqueue(priv->wq); |
5fc7197d MD |
2642 | if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) { |
2643 | netif_device_detach(netdev); | |
2644 | mutex_lock(&priv->state_lock); | |
2645 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2646 | mlx5e_close_locked(netdev); | |
2647 | mutex_unlock(&priv->state_lock); | |
2648 | } else { | |
2649 | unregister_netdev(netdev); | |
2650 | } | |
2651 | ||
e8f887ac | 2652 | mlx5e_tc_cleanup(priv); |
b3f63c3d | 2653 | mlx5e_vxlan_cleanup(priv); |
40ab6a6e AS |
2654 | mlx5e_destroy_flow_tables(priv); |
2655 | mlx5e_destroy_tirs(priv); | |
2656 | mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
2657 | mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT); | |
5c50368f | 2658 | mlx5e_close_drop_rq(priv); |
40ab6a6e | 2659 | mlx5e_destroy_tises(priv); |
a606b0f6 | 2660 | mlx5_core_destroy_mkey(priv->mdev, &priv->mkey); |
8d7f9ecb | 2661 | mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn); |
f62b8bb8 AV |
2662 | mlx5_core_dealloc_pd(priv->mdev, priv->pdn); |
2663 | mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); | |
7bb29755 MF |
2664 | cancel_delayed_work_sync(&priv->update_stats_work); |
2665 | destroy_workqueue(priv->wq); | |
5fc7197d MD |
2666 | |
2667 | if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) | |
2668 | free_netdev(netdev); | |
f62b8bb8 AV |
2669 | } |
2670 | ||
2671 | static void *mlx5e_get_netdev(void *vpriv) | |
2672 | { | |
2673 | struct mlx5e_priv *priv = vpriv; | |
2674 | ||
2675 | return priv->netdev; | |
2676 | } | |
2677 | ||
2678 | static struct mlx5_interface mlx5e_interface = { | |
2679 | .add = mlx5e_create_netdev, | |
2680 | .remove = mlx5e_destroy_netdev, | |
2681 | .event = mlx5e_async_event, | |
2682 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
2683 | .get_dev = mlx5e_get_netdev, | |
2684 | }; | |
2685 | ||
2686 | void mlx5e_init(void) | |
2687 | { | |
2688 | mlx5_register_interface(&mlx5e_interface); | |
2689 | } | |
2690 | ||
2691 | void mlx5e_cleanup(void) | |
2692 | { | |
2693 | mlx5_unregister_interface(&mlx5e_interface); | |
2694 | } |