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net/mlx5: Implement RoCE LAG feature
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
f62b8bb8 37#include "en.h"
e8f887ac 38#include "en_tc.h"
66e49ded 39#include "eswitch.h"
b3f63c3d 40#include "vxlan.h"
f62b8bb8 41
29429f33
DJ		 42enum {
43 MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000,
44 MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20,
45 MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS /
46 MLX5_EN_QP_FLUSH_MSLEEP_QUANT,
47};
48
f62b8bb8 49struct mlx5e_rq_param {
cb3c7fd4
GR		 50 u32 rqc[MLX5_ST_SZ_DW(rqc)];
51 struct mlx5_wq_param wq;
52 bool am_enabled;
f62b8bb8
AV		 53};
54
55struct mlx5e_sq_param {
56 u32 sqc[MLX5_ST_SZ_DW(sqc)];
57 struct mlx5_wq_param wq;
58d52291 58 u16 max_inline;
cff92d7c 59 u8 min_inline_mode;
d3c9bc27 60 bool icosq;
f62b8bb8
AV		 61};
62
63struct mlx5e_cq_param {
64 u32 cqc[MLX5_ST_SZ_DW(cqc)];
65 struct mlx5_wq_param wq;
66 u16 eq_ix;
9908aa29 67 u8 cq_period_mode;
f62b8bb8
AV		 68};
69
70struct mlx5e_channel_param {
71 struct mlx5e_rq_param rq;
72 struct mlx5e_sq_param sq;
d3c9bc27 73 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 74 struct mlx5e_cq_param rx_cq;
75 struct mlx5e_cq_param tx_cq;
d3c9bc27 76 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 77};
78
79static void mlx5e_update_carrier(struct mlx5e_priv *priv)
80{
81 struct mlx5_core_dev *mdev = priv->mdev;
82 u8 port_state;
83
84 port_state = mlx5_query_vport_state(mdev,
e7546514 85 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 86
87424ad5
SD		 87 if (port_state == VPORT_STATE_UP) {
88 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 89 netif_carrier_on(priv->netdev);
87424ad5
SD		 90 } else {
91 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 92 netif_carrier_off(priv->netdev);
87424ad5 93 }
f62b8bb8
AV		 94}
95
96static void mlx5e_update_carrier_work(struct work_struct *work)
97{
98 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
99 update_carrier_work);
100
101 mutex_lock(&priv->state_lock);
102 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
103 mlx5e_update_carrier(priv);
104 mutex_unlock(&priv->state_lock);
105}
106
3947ca18
DJ		 107static void mlx5e_tx_timeout_work(struct work_struct *work)
108{
109 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
110 tx_timeout_work);
111 int err;
112
113 rtnl_lock();
114 mutex_lock(&priv->state_lock);
115 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
116 goto unlock;
117 mlx5e_close_locked(priv->netdev);
118 err = mlx5e_open_locked(priv->netdev);
119 if (err)
120 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
121 err);
122unlock:
123 mutex_unlock(&priv->state_lock);
124 rtnl_unlock();
125}
126
9218b44d 127static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 128{
9218b44d 129 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 130 struct mlx5e_rq_stats *rq_stats;
131 struct mlx5e_sq_stats *sq_stats;
9218b44d 132 u64 tx_offload_none = 0;
f62b8bb8
AV		 133 int i, j;
134
9218b44d 135 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 136 for (i = 0; i < priv->params.num_channels; i++) {
137 rq_stats = &priv->channel[i]->rq.stats;
138
faf4478b
GP		 139 s->rx_packets += rq_stats->packets;
140 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 141 s->rx_lro_packets += rq_stats->lro_packets;
142 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 143 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 144 s->rx_csum_complete += rq_stats->csum_complete;
145 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
f62b8bb8 146 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 147 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
bc77b240 148 s->rx_mpwqe_frag += rq_stats->mpwqe_frag;
54984407 149 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 150 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
151 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
f62b8bb8 152
a4418a6c 153 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 154 sq_stats = &priv->channel[i]->sq[j].stats;
155
faf4478b
GP		 156 s->tx_packets += sq_stats->packets;
157 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 158 s->tx_tso_packets += sq_stats->tso_packets;
159 s->tx_tso_bytes += sq_stats->tso_bytes;
160 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
161 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 162 s->tx_queue_stopped += sq_stats->stopped;
163 s->tx_queue_wake += sq_stats->wake;
164 s->tx_queue_dropped += sq_stats->dropped;
bfe6d8d1
GP		 165 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
166 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 167 }
168 }
169
9218b44d 170 /* Update calculated offload counters */
bfe6d8d1
GP		 171 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
172 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 173
bfe6d8d1 174 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 175 priv->stats.pport.phy_counters,
176 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 177}
178
179static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
180{
181 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
182 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 183 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 184 struct mlx5_core_dev *mdev = priv->mdev;
185
f62b8bb8
AV		 186 MLX5_SET(query_vport_counter_in, in, opcode,
187 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
188 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
189 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
190
191 memset(out, 0, outlen);
9218b44d
GP		 192 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
193}
194
195static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
196{
197 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
198 struct mlx5_core_dev *mdev = priv->mdev;
199 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 200 int prio;
9218b44d
GP		 201 void *out;
202 u32 *in;
203
204 in = mlx5_vzalloc(sz);
205 if (!in)
f62b8bb8
AV		 206 goto free_out;
207
9218b44d 208 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 209
9218b44d
GP		 210 out = pstats->IEEE_802_3_counters;
211 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
212 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 213
9218b44d
GP		 214 out = pstats->RFC_2863_counters;
215 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
216 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
217
218 out = pstats->RFC_2819_counters;
219 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
220 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 221
121fcdc8
GP		 222 out = pstats->phy_counters;
223 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
224 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
225
cf678570
GP		 226 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
227 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
228 out = pstats->per_prio_counters[prio];
229 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
230 mlx5_core_access_reg(mdev, in, sz, out, sz,
231 MLX5_REG_PPCNT, 0, 0);
232 }
233
f62b8bb8 234free_out:
9218b44d
GP		 235 kvfree(in);
236}
237
238static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
239{
240 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
241
242 if (!priv->q_counter)
243 return;
244
245 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
246 &qcnt->rx_out_of_buffer);
247}
248
249void mlx5e_update_stats(struct mlx5e_priv *priv)
250{
9218b44d
GP		 251 mlx5e_update_q_counter(priv);
252 mlx5e_update_vport_counters(priv);
253 mlx5e_update_pport_counters(priv);
121fcdc8 254 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 255}
256
cb67b832 257void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 258{
259 struct delayed_work *dwork = to_delayed_work(work);
260 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
261 update_stats_work);
262 mutex_lock(&priv->state_lock);
263 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 264 priv->profile->update_stats(priv);
7bb29755
MF		 265 queue_delayed_work(priv->wq, dwork,
266 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 267 }
268 mutex_unlock(&priv->state_lock);
269}
270
daa21560
TT		 271static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
272 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 273{
daa21560
TT		 274 struct mlx5e_priv *priv = vpriv;
275
e0f46eb9 276 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 277 return;
278
f62b8bb8
AV		 279 switch (event) {
280 case MLX5_DEV_EVENT_PORT_UP:
281 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 282 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 283 break;
284
285 default:
286 break;
287 }
288}
289
f62b8bb8
AV		 290static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
291{
e0f46eb9 292 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 293}
294
295static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
296{
e0f46eb9 297 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 298 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 299}
300
facc9699
SM		 301#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
302#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
303
f62b8bb8
AV		 304static int mlx5e_create_rq(struct mlx5e_channel *c,
305 struct mlx5e_rq_param *param,
306 struct mlx5e_rq *rq)
307{
308 struct mlx5e_priv *priv = c->priv;
309 struct mlx5_core_dev *mdev = priv->mdev;
310 void *rqc = param->rqc;
311 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 312 u32 byte_count;
f62b8bb8
AV		 313 int wq_sz;
314 int err;
315 int i;
316
311c7c71
SM		 317 param->wq.db_numa_node = cpu_to_node(c->cpu);
318
f62b8bb8
AV		 319 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
320 &rq->wq_ctrl);
321 if (err)
322 return err;
323
324 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
325
326 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 327
461017cb
TT		 328 switch (priv->params.rq_wq_type) {
329 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
330 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
331 GFP_KERNEL, cpu_to_node(c->cpu));
332 if (!rq->wqe_info) {
333 err = -ENOMEM;
334 goto err_rq_wq_destroy;
335 }
336 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
337 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 338 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 339
d9d9f156
TT		 340 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
341 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
342 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
461017cb
TT		 343 byte_count = rq->wqe_sz;
344 break;
345 default: /* MLX5_WQ_TYPE_LINKED_LIST */
346 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
347 cpu_to_node(c->cpu));
348 if (!rq->skb) {
349 err = -ENOMEM;
350 goto err_rq_wq_destroy;
351 }
352 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
353 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 354 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb
TT		 355
356 rq->wqe_sz = (priv->params.lro_en) ?
357 priv->params.lro_wqe_sz :
358 MLX5E_SW2HW_MTU(priv->netdev->mtu);
c5adb96f
TT		 359 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
360 byte_count = rq->wqe_sz;
461017cb
TT		 361 byte_count |= MLX5_HW_START_PADDING;
362 }
f62b8bb8
AV		 363
364 for (i = 0; i < wq_sz; i++) {
365 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
366
461017cb 367 wqe->data.byte_count = cpu_to_be32(byte_count);
f62b8bb8
AV		 368 }
369
cb3c7fd4
GR		 370 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
371 rq->am.mode = priv->params.rx_cq_period_mode;
372
461017cb 373 rq->wq_type = priv->params.rq_wq_type;
f62b8bb8
AV		 374 rq->pdev = c->pdev;
375 rq->netdev = c->netdev;
ef9814de 376 rq->tstamp = &priv->tstamp;
f62b8bb8
AV		 377 rq->channel = c;
378 rq->ix = c->ix;
50cfa25a 379 rq->priv = c->priv;
bc77b240
TT		 380 rq->mkey_be = c->mkey_be;
381 rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
f62b8bb8
AV		 382
383 return 0;
384
385err_rq_wq_destroy:
386 mlx5_wq_destroy(&rq->wq_ctrl);
387
388 return err;
389}
390
391static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
392{
461017cb
TT		 393 switch (rq->wq_type) {
394 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
395 kfree(rq->wqe_info);
396 break;
397 default: /* MLX5_WQ_TYPE_LINKED_LIST */
398 kfree(rq->skb);
399 }
400
f62b8bb8
AV		 401 mlx5_wq_destroy(&rq->wq_ctrl);
402}
403
404static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
405{
50cfa25a 406 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 407 struct mlx5_core_dev *mdev = priv->mdev;
408
409 void *in;
410 void *rqc;
411 void *wq;
412 int inlen;
413 int err;
414
415 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
416 sizeof(u64) * rq->wq_ctrl.buf.npages;
417 in = mlx5_vzalloc(inlen);
418 if (!in)
419 return -ENOMEM;
420
421 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
422 wq = MLX5_ADDR_OF(rqc, rqc, wq);
423
424 memcpy(rqc, param->rqc, sizeof(param->rqc));
425
97de9f31 426 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 427 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
428 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
36350114 429 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 430 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 431 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 432 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
433
434 mlx5_fill_page_array(&rq->wq_ctrl.buf,
435 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
436
7db22ffb 437 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 438
439 kvfree(in);
440
441 return err;
442}
443
36350114
GP		 444static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
445 int next_state)
f62b8bb8
AV		 446{
447 struct mlx5e_channel *c = rq->channel;
448 struct mlx5e_priv *priv = c->priv;
449 struct mlx5_core_dev *mdev = priv->mdev;
450
451 void *in;
452 void *rqc;
453 int inlen;
454 int err;
455
456 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
457 in = mlx5_vzalloc(inlen);
458 if (!in)
459 return -ENOMEM;
460
461 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
462
463 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
464 MLX5_SET(rqc, rqc, state, next_state);
465
7db22ffb 466 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 467
468 kvfree(in);
469
470 return err;
471}
472
36350114
GP		 473static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
474{
475 struct mlx5e_channel *c = rq->channel;
476 struct mlx5e_priv *priv = c->priv;
477 struct mlx5_core_dev *mdev = priv->mdev;
478
479 void *in;
480 void *rqc;
481 int inlen;
482 int err;
483
484 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
485 in = mlx5_vzalloc(inlen);
486 if (!in)
487 return -ENOMEM;
488
489 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
490
491 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 492 MLX5_SET64(modify_rq_in, in, modify_bitmask,
493 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 494 MLX5_SET(rqc, rqc, vsd, vsd);
495 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
496
497 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
498
499 kvfree(in);
500
501 return err;
502}
503
f62b8bb8
AV		 504static void mlx5e_disable_rq(struct mlx5e_rq *rq)
505{
50cfa25a 506 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 507}
508
509static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
510{
01c196a2 511 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 512 struct mlx5e_channel *c = rq->channel;
513 struct mlx5e_priv *priv = c->priv;
514 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 515
01c196a2 516 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 517 if (wq->cur_sz >= priv->params.min_rx_wqes)
518 return 0;
519
520 msleep(20);
521 }
522
523 return -ETIMEDOUT;
524}
525
526static int mlx5e_open_rq(struct mlx5e_channel *c,
527 struct mlx5e_rq_param *param,
528 struct mlx5e_rq *rq)
529{
d3c9bc27
TT		 530 struct mlx5e_sq *sq = &c->icosq;
531 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 532 int err;
533
534 err = mlx5e_create_rq(c, param, rq);
535 if (err)
536 return err;
537
538 err = mlx5e_enable_rq(rq, param);
539 if (err)
540 goto err_destroy_rq;
541
36350114 542 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 543 if (err)
544 goto err_disable_rq;
545
cb3c7fd4
GR		 546 if (param->am_enabled)
547 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
548
f62b8bb8 549 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
d3c9bc27
TT		 550
551 sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP;
552 sq->ico_wqe_info[pi].num_wqebbs = 1;
553 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 554
555 return 0;
556
557err_disable_rq:
558 mlx5e_disable_rq(rq);
559err_destroy_rq:
560 mlx5e_destroy_rq(rq);
561
562 return err;
563}
564
565static void mlx5e_close_rq(struct mlx5e_rq *rq)
566{
6cd392a0
DJ		 567 int tout = 0;
568 int err;
569
f62b8bb8
AV		 570 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
571 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
572
6cd392a0
DJ		 573 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
574 while (!mlx5_wq_ll_is_empty(&rq->wq) && !err &&
575 tout++ < MLX5_EN_QP_FLUSH_MAX_ITER)
576 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
577
578 if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER)
579 set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state);
f62b8bb8
AV		 580
581 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
582 napi_synchronize(&rq->channel->napi);
583
cb3c7fd4
GR		 584 cancel_work_sync(&rq->am.work);
585
f62b8bb8 586 mlx5e_disable_rq(rq);
6cd392a0 587 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 588 mlx5e_destroy_rq(rq);
589}
590
591static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
592{
34802a42 593 kfree(sq->wqe_info);
f62b8bb8
AV		 594 kfree(sq->dma_fifo);
595 kfree(sq->skb);
596}
597
598static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
599{
600 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
601 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
602
603 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
604 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
605 numa);
34802a42
AS		 606 sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
607 numa);
f62b8bb8 608
34802a42 609 if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
f62b8bb8
AV		 610 mlx5e_free_sq_db(sq);
611 return -ENOMEM;
612 }
613
614 sq->dma_fifo_mask = df_sz - 1;
615
616 return 0;
617}
618
619static int mlx5e_create_sq(struct mlx5e_channel *c,
620 int tc,
621 struct mlx5e_sq_param *param,
622 struct mlx5e_sq *sq)
623{
624 struct mlx5e_priv *priv = c->priv;
625 struct mlx5_core_dev *mdev = priv->mdev;
626
627 void *sqc = param->sqc;
628 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
629 int err;
630
fd4782c2 631 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 632 if (err)
633 return err;
634
311c7c71
SM		 635 param->wq.db_numa_node = cpu_to_node(c->cpu);
636
f62b8bb8
AV		 637 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
638 &sq->wq_ctrl);
639 if (err)
640 goto err_unmap_free_uar;
641
642 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 643 if (sq->uar.bf_map) {
644 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
645 sq->uar_map = sq->uar.bf_map;
646 } else {
647 sq->uar_map = sq->uar.map;
648 }
f62b8bb8 649 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 650 sq->max_inline = param->max_inline;
cff92d7c
HHZ		 651 sq->min_inline_mode =
652 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
653 param->min_inline_mode : 0;
f62b8bb8 654
7ec0bb22
DC		 655 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
656 if (err)
f62b8bb8
AV		 657 goto err_sq_wq_destroy;
658
d3c9bc27
TT		 659 if (param->icosq) {
660 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
661
662 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
663 wq_sz,
664 GFP_KERNEL,
665 cpu_to_node(c->cpu));
666 if (!sq->ico_wqe_info) {
667 err = -ENOMEM;
668 goto err_free_sq_db;
669 }
670 } else {
671 int txq_ix;
672
673 txq_ix = c->ix + tc * priv->params.num_channels;
674 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
675 priv->txq_to_sq_map[txq_ix] = sq;
676 }
f62b8bb8 677
88a85f99 678 sq->pdev = c->pdev;
ef9814de 679 sq->tstamp = &priv->tstamp;
88a85f99
AS		 680 sq->mkey_be = c->mkey_be;
681 sq->channel = c;
682 sq->tc = tc;
683 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
684 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 685
686 return 0;
687
d3c9bc27
TT		 688err_free_sq_db:
689 mlx5e_free_sq_db(sq);
690
f62b8bb8
AV		 691err_sq_wq_destroy:
692 mlx5_wq_destroy(&sq->wq_ctrl);
693
694err_unmap_free_uar:
695 mlx5_unmap_free_uar(mdev, &sq->uar);
696
697 return err;
698}
699
700static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
701{
702 struct mlx5e_channel *c = sq->channel;
703 struct mlx5e_priv *priv = c->priv;
704
d3c9bc27 705 kfree(sq->ico_wqe_info);
f62b8bb8
AV		 706 mlx5e_free_sq_db(sq);
707 mlx5_wq_destroy(&sq->wq_ctrl);
708 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
709}
710
711static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
712{
713 struct mlx5e_channel *c = sq->channel;
714 struct mlx5e_priv *priv = c->priv;
715 struct mlx5_core_dev *mdev = priv->mdev;
716
717 void *in;
718 void *sqc;
719 void *wq;
720 int inlen;
721 int err;
722
723 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
724 sizeof(u64) * sq->wq_ctrl.buf.npages;
725 in = mlx5_vzalloc(inlen);
726 if (!in)
727 return -ENOMEM;
728
729 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
730 wq = MLX5_ADDR_OF(sqc, sqc, wq);
731
732 memcpy(sqc, param->sqc, sizeof(param->sqc));
733
d3c9bc27
TT		 734 MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
735 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 736 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 737 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
d3c9bc27 738 MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1);
f62b8bb8
AV		 739 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
740
741 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
742 MLX5_SET(wq, wq, uar_page, sq->uar.index);
743 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 744 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 745 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
746
747 mlx5_fill_page_array(&sq->wq_ctrl.buf,
748 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
749
7db22ffb 750 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 751
752 kvfree(in);
753
754 return err;
755}
756
507f0c81
YP		 757static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
758 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 759{
760 struct mlx5e_channel *c = sq->channel;
761 struct mlx5e_priv *priv = c->priv;
762 struct mlx5_core_dev *mdev = priv->mdev;
763
764 void *in;
765 void *sqc;
766 int inlen;
767 int err;
768
769 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
770 in = mlx5_vzalloc(inlen);
771 if (!in)
772 return -ENOMEM;
773
774 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
775
776 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
777 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 778 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
779 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
780 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
781 }
f62b8bb8 782
7db22ffb 783 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 784
785 kvfree(in);
786
787 return err;
788}
789
790static void mlx5e_disable_sq(struct mlx5e_sq *sq)
791{
792 struct mlx5e_channel *c = sq->channel;
793 struct mlx5e_priv *priv = c->priv;
794 struct mlx5_core_dev *mdev = priv->mdev;
795
7db22ffb 796 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 797 if (sq->rate_limit)
798 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 799}
800
801static int mlx5e_open_sq(struct mlx5e_channel *c,
802 int tc,
803 struct mlx5e_sq_param *param,
804 struct mlx5e_sq *sq)
805{
806 int err;
807
808 err = mlx5e_create_sq(c, tc, param, sq);
809 if (err)
810 return err;
811
812 err = mlx5e_enable_sq(sq, param);
813 if (err)
814 goto err_destroy_sq;
815
507f0c81
YP		 816 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
817 false, 0);
f62b8bb8
AV		 818 if (err)
819 goto err_disable_sq;
820
d3c9bc27
TT		 821 if (sq->txq) {
822 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
823 netdev_tx_reset_queue(sq->txq);
824 netif_tx_start_queue(sq->txq);
825 }
f62b8bb8
AV		 826
827 return 0;
828
829err_disable_sq:
830 mlx5e_disable_sq(sq);
831err_destroy_sq:
832 mlx5e_destroy_sq(sq);
833
834 return err;
835}
836
837static inline void netif_tx_disable_queue(struct netdev_queue *txq)
838{
839 __netif_tx_lock_bh(txq);
840 netif_tx_stop_queue(txq);
841 __netif_tx_unlock_bh(txq);
842}
843
844static void mlx5e_close_sq(struct mlx5e_sq *sq)
845{
29429f33
DJ		 846 int tout = 0;
847 int err;
848
d3c9bc27
TT		 849 if (sq->txq) {
850 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
851 /* prevent netif_tx_wake_queue */
852 napi_synchronize(&sq->channel->napi);
853 netif_tx_disable_queue(sq->txq);
f62b8bb8 854
d3c9bc27
TT		 855 /* ensure hw is notified of all pending wqes */
856 if (mlx5e_sq_has_room_for(sq, 1))
857 mlx5e_send_nop(sq, true);
858
29429f33 859 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
30d0844b 860 MLX5_SQC_STATE_ERR, false, 0);
29429f33
DJ		 861 if (err)
862 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
d3c9bc27 863 }
f62b8bb8 864
29429f33
DJ		 865 /* wait till sq is empty, unless a TX timeout occurred on this SQ */
866 while (sq->cc != sq->pc &&
867 !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) {
868 msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT);
869 if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER)
870 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
871 }
f62b8bb8
AV		 872
873 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
874 napi_synchronize(&sq->channel->napi);
875
29429f33 876 mlx5e_free_tx_descs(sq);
f62b8bb8
AV		 877 mlx5e_disable_sq(sq);
878 mlx5e_destroy_sq(sq);
879}
880
881static int mlx5e_create_cq(struct mlx5e_channel *c,
882 struct mlx5e_cq_param *param,
883 struct mlx5e_cq *cq)
884{
885 struct mlx5e_priv *priv = c->priv;
886 struct mlx5_core_dev *mdev = priv->mdev;
887 struct mlx5_core_cq *mcq = &cq->mcq;
888 int eqn_not_used;
0b6e26ce 889 unsigned int irqn;
f62b8bb8
AV		 890 int err;
891 u32 i;
892
311c7c71
SM		 893 param->wq.buf_numa_node = cpu_to_node(c->cpu);
894 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 895 param->eq_ix = c->ix;
896
897 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
898 &cq->wq_ctrl);
899 if (err)
900 return err;
901
902 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
903
904 cq->napi = &c->napi;
905
906 mcq->cqe_sz = 64;
907 mcq->set_ci_db = cq->wq_ctrl.db.db;
908 mcq->arm_db = cq->wq_ctrl.db.db + 1;
909 *mcq->set_ci_db = 0;
910 *mcq->arm_db = 0;
911 mcq->vector = param->eq_ix;
912 mcq->comp = mlx5e_completion_event;
913 mcq->event = mlx5e_cq_error_event;
914 mcq->irqn = irqn;
b50d292b 915 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 916
917 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
918 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
919
920 cqe->op_own = 0xf1;
921 }
922
923 cq->channel = c;
50cfa25a 924 cq->priv = priv;
f62b8bb8
AV		 925
926 return 0;
927}
928
929static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
930{
931 mlx5_wq_destroy(&cq->wq_ctrl);
932}
933
934static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
935{
50cfa25a 936 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 937 struct mlx5_core_dev *mdev = priv->mdev;
938 struct mlx5_core_cq *mcq = &cq->mcq;
939
940 void *in;
941 void *cqc;
942 int inlen;
0b6e26ce 943 unsigned int irqn_not_used;
f62b8bb8
AV		 944 int eqn;
945 int err;
946
947 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
948 sizeof(u64) * cq->wq_ctrl.buf.npages;
949 in = mlx5_vzalloc(inlen);
950 if (!in)
951 return -ENOMEM;
952
953 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
954
955 memcpy(cqc, param->cqc, sizeof(param->cqc));
956
957 mlx5_fill_page_array(&cq->wq_ctrl.buf,
958 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
959
960 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
961
9908aa29 962 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 963 MLX5_SET(cqc, cqc, c_eqn, eqn);
964 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
965 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 966 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 967 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
968
969 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
970
971 kvfree(in);
972
973 if (err)
974 return err;
975
976 mlx5e_cq_arm(cq);
977
978 return 0;
979}
980
981static void mlx5e_disable_cq(struct mlx5e_cq *cq)
982{
50cfa25a 983 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 984 struct mlx5_core_dev *mdev = priv->mdev;
985
986 mlx5_core_destroy_cq(mdev, &cq->mcq);
987}
988
989static int mlx5e_open_cq(struct mlx5e_channel *c,
990 struct mlx5e_cq_param *param,
991 struct mlx5e_cq *cq,
9908aa29 992 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 993{
994 int err;
995 struct mlx5e_priv *priv = c->priv;
996 struct mlx5_core_dev *mdev = priv->mdev;
997
998 err = mlx5e_create_cq(c, param, cq);
999 if (err)
1000 return err;
1001
1002 err = mlx5e_enable_cq(cq, param);
1003 if (err)
1004 goto err_destroy_cq;
1005
7524a5d8
GP		 1006 if (MLX5_CAP_GEN(mdev, cq_moderation))
1007 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1008 moderation.usec,
1009 moderation.pkts);
f62b8bb8
AV		 1010 return 0;
1011
1012err_destroy_cq:
1013 mlx5e_destroy_cq(cq);
1014
1015 return err;
1016}
1017
1018static void mlx5e_close_cq(struct mlx5e_cq *cq)
1019{
1020 mlx5e_disable_cq(cq);
1021 mlx5e_destroy_cq(cq);
1022}
1023
1024static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1025{
1026 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1027}
1028
1029static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1030 struct mlx5e_channel_param *cparam)
1031{
1032 struct mlx5e_priv *priv = c->priv;
1033 int err;
1034 int tc;
1035
1036 for (tc = 0; tc < c->num_tc; tc++) {
1037 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1038 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1039 if (err)
1040 goto err_close_tx_cqs;
f62b8bb8
AV		 1041 }
1042
1043 return 0;
1044
1045err_close_tx_cqs:
1046 for (tc--; tc >= 0; tc--)
1047 mlx5e_close_cq(&c->sq[tc].cq);
1048
1049 return err;
1050}
1051
1052static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1053{
1054 int tc;
1055
1056 for (tc = 0; tc < c->num_tc; tc++)
1057 mlx5e_close_cq(&c->sq[tc].cq);
1058}
1059
1060static int mlx5e_open_sqs(struct mlx5e_channel *c,
1061 struct mlx5e_channel_param *cparam)
1062{
1063 int err;
1064 int tc;
1065
1066 for (tc = 0; tc < c->num_tc; tc++) {
1067 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1068 if (err)
1069 goto err_close_sqs;
1070 }
1071
1072 return 0;
1073
1074err_close_sqs:
1075 for (tc--; tc >= 0; tc--)
1076 mlx5e_close_sq(&c->sq[tc]);
1077
1078 return err;
1079}
1080
1081static void mlx5e_close_sqs(struct mlx5e_channel *c)
1082{
1083 int tc;
1084
1085 for (tc = 0; tc < c->num_tc; tc++)
1086 mlx5e_close_sq(&c->sq[tc]);
1087}
1088
5283af89 1089static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1090{
1091 int i;
1092
6bfd390b 1093 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1094 priv->channeltc_to_txq_map[ix][i] =
1095 ix + i * priv->params.num_channels;
03289b88
SM		 1096}
1097
507f0c81
YP		 1098static int mlx5e_set_sq_maxrate(struct net_device *dev,
1099 struct mlx5e_sq *sq, u32 rate)
1100{
1101 struct mlx5e_priv *priv = netdev_priv(dev);
1102 struct mlx5_core_dev *mdev = priv->mdev;
1103 u16 rl_index = 0;
1104 int err;
1105
1106 if (rate == sq->rate_limit)
1107 /* nothing to do */
1108 return 0;
1109
1110 if (sq->rate_limit)
1111 /* remove current rl index to free space to next ones */
1112 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1113
1114 sq->rate_limit = 0;
1115
1116 if (rate) {
1117 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1118 if (err) {
1119 netdev_err(dev, "Failed configuring rate %u: %d\n",
1120 rate, err);
1121 return err;
1122 }
1123 }
1124
1125 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1126 MLX5_SQC_STATE_RDY, true, rl_index);
1127 if (err) {
1128 netdev_err(dev, "Failed configuring rate %u: %d\n",
1129 rate, err);
1130 /* remove the rate from the table */
1131 if (rate)
1132 mlx5_rl_remove_rate(mdev, rate);
1133 return err;
1134 }
1135
1136 sq->rate_limit = rate;
1137 return 0;
1138}
1139
1140static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1141{
1142 struct mlx5e_priv *priv = netdev_priv(dev);
1143 struct mlx5_core_dev *mdev = priv->mdev;
1144 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1145 int err = 0;
1146
1147 if (!mlx5_rl_is_supported(mdev)) {
1148 netdev_err(dev, "Rate limiting is not supported on this device\n");
1149 return -EINVAL;
1150 }
1151
1152 /* rate is given in Mb/sec, HW config is in Kb/sec */
1153 rate = rate << 10;
1154
1155 /* Check whether rate in valid range, 0 is always valid */
1156 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1157 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1158 return -ERANGE;
1159 }
1160
1161 mutex_lock(&priv->state_lock);
1162 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1163 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1164 if (!err)
1165 priv->tx_rates[index] = rate;
1166 mutex_unlock(&priv->state_lock);
1167
1168 return err;
1169}
1170
f62b8bb8
AV		 1171static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1172 struct mlx5e_channel_param *cparam,
1173 struct mlx5e_channel **cp)
1174{
9908aa29 1175 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1176 struct net_device *netdev = priv->netdev;
cb3c7fd4 1177 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1178 int cpu = mlx5e_get_cpu(priv, ix);
1179 struct mlx5e_channel *c;
507f0c81 1180 struct mlx5e_sq *sq;
f62b8bb8 1181 int err;
507f0c81 1182 int i;
f62b8bb8
AV		 1183
1184 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1185 if (!c)
1186 return -ENOMEM;
1187
1188 c->priv = priv;
1189 c->ix = ix;
1190 c->cpu = cpu;
1191 c->pdev = &priv->mdev->pdev->dev;
1192 c->netdev = priv->netdev;
b50d292b 1193 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1194 c->num_tc = priv->params.num_tc;
f62b8bb8 1195
cb3c7fd4
GR		 1196 if (priv->params.rx_am_enabled)
1197 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1198 else
1199 rx_cq_profile = priv->params.rx_cq_moderation;
1200
5283af89 1201 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1202
f62b8bb8
AV		 1203 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1204
9908aa29 1205 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1206 if (err)
1207 goto err_napi_del;
1208
d3c9bc27
TT		 1209 err = mlx5e_open_tx_cqs(c, cparam);
1210 if (err)
1211 goto err_close_icosq_cq;
1212
f62b8bb8 1213 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1214 rx_cq_profile);
f62b8bb8
AV		 1215 if (err)
1216 goto err_close_tx_cqs;
f62b8bb8
AV		 1217
1218 napi_enable(&c->napi);
1219
d3c9bc27 1220 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1221 if (err)
1222 goto err_disable_napi;
1223
d3c9bc27
TT		 1224 err = mlx5e_open_sqs(c, cparam);
1225 if (err)
1226 goto err_close_icosq;
1227
507f0c81
YP		 1228 for (i = 0; i < priv->params.num_tc; i++) {
1229 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1230
1231 if (priv->tx_rates[txq_ix]) {
1232 sq = priv->txq_to_sq_map[txq_ix];
1233 mlx5e_set_sq_maxrate(priv->netdev, sq,
1234 priv->tx_rates[txq_ix]);
1235 }
1236 }
1237
f62b8bb8
AV		 1238 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1239 if (err)
1240 goto err_close_sqs;
1241
1242 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1243 *cp = c;
1244
1245 return 0;
1246
1247err_close_sqs:
1248 mlx5e_close_sqs(c);
1249
d3c9bc27
TT		 1250err_close_icosq:
1251 mlx5e_close_sq(&c->icosq);
1252
f62b8bb8
AV		 1253err_disable_napi:
1254 napi_disable(&c->napi);
1255 mlx5e_close_cq(&c->rq.cq);
1256
1257err_close_tx_cqs:
1258 mlx5e_close_tx_cqs(c);
1259
d3c9bc27
TT		 1260err_close_icosq_cq:
1261 mlx5e_close_cq(&c->icosq.cq);
1262
f62b8bb8
AV		 1263err_napi_del:
1264 netif_napi_del(&c->napi);
7ae92ae5 1265 napi_hash_del(&c->napi);
f62b8bb8
AV		 1266 kfree(c);
1267
1268 return err;
1269}
1270
1271static void mlx5e_close_channel(struct mlx5e_channel *c)
1272{
1273 mlx5e_close_rq(&c->rq);
1274 mlx5e_close_sqs(c);
d3c9bc27 1275 mlx5e_close_sq(&c->icosq);
f62b8bb8
AV		 1276 napi_disable(&c->napi);
1277 mlx5e_close_cq(&c->rq.cq);
1278 mlx5e_close_tx_cqs(c);
d3c9bc27 1279 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1280 netif_napi_del(&c->napi);
7ae92ae5
ED		 1281
1282 napi_hash_del(&c->napi);
1283 synchronize_rcu();
1284
f62b8bb8
AV		 1285 kfree(c);
1286}
1287
1288static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1289 struct mlx5e_rq_param *param)
1290{
1291 void *rqc = param->rqc;
1292 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1293
461017cb
TT		 1294 switch (priv->params.rq_wq_type) {
1295 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1296 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1297 priv->params.mpwqe_log_num_strides - 9);
461017cb 1298 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1299 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1300 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1301 break;
1302 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1303 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1304 }
1305
f62b8bb8
AV		 1306 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1307 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1308 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1309 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1310 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1311
311c7c71 1312 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1313 param->wq.linear = 1;
cb3c7fd4
GR		 1314
1315 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1316}
1317
556dd1b9
TT		 1318static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1319{
1320 void *rqc = param->rqc;
1321 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1322
1323 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1324 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1325}
1326
d3c9bc27
TT		 1327static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1328 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1329{
1330 void *sqc = param->sqc;
1331 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1332
f62b8bb8 1333 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1334 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1335
311c7c71 1336 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1337}
1338
1339static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1340 struct mlx5e_sq_param *param)
1341{
1342 void *sqc = param->sqc;
1343 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1344
1345 mlx5e_build_sq_param_common(priv, param);
1346 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1347
58d52291 1348 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1349 param->min_inline_mode = priv->params.tx_min_inline_mode;
f62b8bb8
AV		 1350}
1351
1352static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1353 struct mlx5e_cq_param *param)
1354{
1355 void *cqc = param->cqc;
1356
b50d292b 1357 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1358}
1359
1360static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1361 struct mlx5e_cq_param *param)
1362{
1363 void *cqc = param->cqc;
461017cb 1364 u8 log_cq_size;
f62b8bb8 1365
461017cb
TT		 1366 switch (priv->params.rq_wq_type) {
1367 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1368 log_cq_size = priv->params.log_rq_size +
d9d9f156 1369 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1370 break;
1371 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1372 log_cq_size = priv->params.log_rq_size;
1373 }
1374
1375 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
7219ab34
TT		 1376 if (priv->params.rx_cqe_compress) {
1377 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1378 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1379 }
f62b8bb8
AV		 1380
1381 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1382
1383 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1384}
1385
1386static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1387 struct mlx5e_cq_param *param)
1388{
1389 void *cqc = param->cqc;
1390
d3c9bc27 1391 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1392
1393 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1394
1395 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1396}
1397
d3c9bc27
TT		 1398static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1399 struct mlx5e_cq_param *param,
1400 u8 log_wq_size)
1401{
1402 void *cqc = param->cqc;
1403
1404 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1405
1406 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1407
1408 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1409}
1410
1411static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1412 struct mlx5e_sq_param *param,
1413 u8 log_wq_size)
1414{
1415 void *sqc = param->sqc;
1416 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1417
1418 mlx5e_build_sq_param_common(priv, param);
1419
1420 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1421 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 1422
1423 param->icosq = true;
1424}
1425
6b87663f 1426static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1427{
bc77b240 1428 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1429
f62b8bb8
AV		 1430 mlx5e_build_rq_param(priv, &cparam->rq);
1431 mlx5e_build_sq_param(priv, &cparam->sq);
d3c9bc27 1432 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1433 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1434 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1435 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1436}
1437
1438static int mlx5e_open_channels(struct mlx5e_priv *priv)
1439{
6b87663f 1440 struct mlx5e_channel_param *cparam;
a4418a6c 1441 int nch = priv->params.num_channels;
03289b88 1442 int err = -ENOMEM;
f62b8bb8
AV		 1443 int i;
1444 int j;
1445
a4418a6c
AS		 1446 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1447 GFP_KERNEL);
03289b88 1448
a4418a6c 1449 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1450 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1451
6b87663f
AB		 1452 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1453
1454 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1455 goto err_free_txq_to_sq_map;
f62b8bb8 1456
6b87663f
AB		 1457 mlx5e_build_channel_param(priv, cparam);
1458
a4418a6c 1459 for (i = 0; i < nch; i++) {
6b87663f 1460 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1461 if (err)
1462 goto err_close_channels;
1463 }
1464
a4418a6c 1465 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1466 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1467 if (err)
1468 goto err_close_channels;
1469 }
1470
c3b7c5c9
MHY		 1471 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1472 * polling for inactive tx queues.
1473 */
1474 netif_tx_start_all_queues(priv->netdev);
1475
6b87663f 1476 kfree(cparam);
f62b8bb8
AV		 1477 return 0;
1478
1479err_close_channels:
1480 for (i--; i >= 0; i--)
1481 mlx5e_close_channel(priv->channel[i]);
1482
03289b88
SM		 1483err_free_txq_to_sq_map:
1484 kfree(priv->txq_to_sq_map);
f62b8bb8 1485 kfree(priv->channel);
6b87663f 1486 kfree(cparam);
f62b8bb8
AV		 1487
1488 return err;
1489}
1490
1491static void mlx5e_close_channels(struct mlx5e_priv *priv)
1492{
1493 int i;
1494
c3b7c5c9
MHY		 1495 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1496 * polling for inactive tx queues.
1497 */
1498 netif_tx_stop_all_queues(priv->netdev);
1499 netif_tx_disable(priv->netdev);
1500
f62b8bb8
AV		 1501 for (i = 0; i < priv->params.num_channels; i++)
1502 mlx5e_close_channel(priv->channel[i]);
1503
03289b88 1504 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1505 kfree(priv->channel);
1506}
1507
2be6967c
SM		 1508static int mlx5e_rx_hash_fn(int hfunc)
1509{
1510 return (hfunc == ETH_RSS_HASH_TOP) ?
1511 MLX5_RX_HASH_FN_TOEPLITZ :
1512 MLX5_RX_HASH_FN_INVERTED_XOR8;
1513}
1514
1515static int mlx5e_bits_invert(unsigned long a, int size)
1516{
1517 int inv = 0;
1518 int i;
1519
1520 for (i = 0; i < size; i++)
1521 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1522
1523 return inv;
1524}
1525
936896e9
AS		 1526static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1527{
1528 int i;
1529
1530 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1531 int ix = i;
1da36696 1532 u32 rqn;
936896e9
AS		 1533
1534 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1535 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1536
2d75b2bc 1537 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1538 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1539 priv->channel[ix]->rq.rqn :
1540 priv->drop_rq.rqn;
1541 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1542 }
1543}
1544
1da36696
TT		 1545static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1546 int ix)
4cbeaff5 1547{
1da36696
TT		 1548 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1549 priv->channel[ix]->rq.rqn :
1550 priv->drop_rq.rqn;
4cbeaff5 1551
1da36696 1552 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1553}
1554
398f3351
HHZ		 1555static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1556 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1557{
1558 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1559 void *rqtc;
1560 int inlen;
1561 int err;
1da36696 1562 u32 *in;
f62b8bb8 1563
f62b8bb8
AV		 1564 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1565 in = mlx5_vzalloc(inlen);
1566 if (!in)
1567 return -ENOMEM;
1568
1569 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1570
1571 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1572 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1573
1da36696
TT		 1574 if (sz > 1) /* RSS */
1575 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1576 else
1577 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1578
398f3351
HHZ		 1579 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1580 if (!err)
1581 rqt->enabled = true;
f62b8bb8
AV		 1582
1583 kvfree(in);
1da36696
TT		 1584 return err;
1585}
1586
cb67b832 1587void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1588{
398f3351
HHZ		 1589 rqt->enabled = false;
1590 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1591}
1592
6bfd390b
HHZ		 1593static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1594{
1595 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1596
1597 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1598}
1599
cb67b832 1600int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1601{
398f3351 1602 struct mlx5e_rqt *rqt;
1da36696
TT		 1603 int err;
1604 int ix;
1605
6bfd390b 1606 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1607 rqt = &priv->direct_tir[ix].rqt;
1608 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1609 if (err)
1610 goto err_destroy_rqts;
1611 }
1612
1613 return 0;
1614
1615err_destroy_rqts:
1616 for (ix--; ix >= 0; ix--)
398f3351 1617 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1618
f62b8bb8
AV		 1619 return err;
1620}
1621
1da36696 1622int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1623{
1624 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1625 void *rqtc;
1626 int inlen;
1da36696 1627 u32 *in;
5c50368f
AS		 1628 int err;
1629
5c50368f
AS		 1630 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1631 in = mlx5_vzalloc(inlen);
1632 if (!in)
1633 return -ENOMEM;
1634
1635 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1636
1637 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1638 if (sz > 1) /* RSS */
1639 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1640 else
1641 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1642
1643 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1644
1da36696 1645 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1646
1647 kvfree(in);
1648
1649 return err;
1650}
1651
40ab6a6e
AS		 1652static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1653{
1da36696
TT		 1654 u32 rqtn;
1655 int ix;
1656
398f3351
HHZ		 1657 if (priv->indir_rqt.enabled) {
1658 rqtn = priv->indir_rqt.rqtn;
1659 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1660 }
1661
1da36696 1662 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1663 if (!priv->direct_tir[ix].rqt.enabled)
1664 continue;
1665 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1666 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1667 }
40ab6a6e
AS		 1668}
1669
5c50368f
AS		 1670static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1671{
1672 if (!priv->params.lro_en)
1673 return;
1674
1675#define ROUGH_MAX_L2_L3_HDR_SZ 256
1676
1677 MLX5_SET(tirc, tirc, lro_enable_mask,
1678 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1679 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1680 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1681 (priv->params.lro_wqe_sz -
1682 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1683 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1684 MLX5_CAP_ETH(priv->mdev,
d9a40271 1685 lro_timer_supported_periods[2]));
5c50368f
AS		 1686}
1687
bdfc028d
TT		 1688void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1689{
1690 MLX5_SET(tirc, tirc, rx_hash_fn,
1691 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1692 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1693 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1694 rx_hash_toeplitz_key);
1695 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1696 rx_hash_toeplitz_key);
1697
1698 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1699 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1700 }
1701}
1702
ab0394fe 1703static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 1704{
1705 struct mlx5_core_dev *mdev = priv->mdev;
1706
1707 void *in;
1708 void *tirc;
1709 int inlen;
1710 int err;
ab0394fe 1711 int tt;
1da36696 1712 int ix;
5c50368f
AS		 1713
1714 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1715 in = mlx5_vzalloc(inlen);
1716 if (!in)
1717 return -ENOMEM;
1718
1719 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1720 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1721
1722 mlx5e_build_tir_ctx_lro(tirc, priv);
1723
1da36696 1724 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 1725 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 1726 inlen);
ab0394fe 1727 if (err)
1da36696 1728 goto free_in;
ab0394fe 1729 }
5c50368f 1730
6bfd390b 1731 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 1732 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1733 in, inlen);
1734 if (err)
1735 goto free_in;
1736 }
1737
1738free_in:
5c50368f
AS		 1739 kvfree(in);
1740
1741 return err;
1742}
1743
cd255eff 1744static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 1745{
40ab6a6e 1746 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 1747 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 1748 int err;
1749
cd255eff 1750 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 1751 if (err)
1752 return err;
1753
cd255eff
SM		 1754 /* Update vport context MTU */
1755 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1756 return 0;
1757}
40ab6a6e 1758
cd255eff
SM		 1759static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1760{
1761 struct mlx5_core_dev *mdev = priv->mdev;
1762 u16 hw_mtu = 0;
1763 int err;
40ab6a6e 1764
cd255eff
SM		 1765 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1766 if (err || !hw_mtu) /* fallback to port oper mtu */
1767 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1768
1769 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1770}
1771
1772static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1773{
1774 struct mlx5e_priv *priv = netdev_priv(netdev);
1775 u16 mtu;
1776 int err;
1777
1778 err = mlx5e_set_mtu(priv, netdev->mtu);
1779 if (err)
1780 return err;
40ab6a6e 1781
cd255eff
SM		 1782 mlx5e_query_mtu(priv, &mtu);
1783 if (mtu != netdev->mtu)
1784 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1785 __func__, mtu, netdev->mtu);
40ab6a6e 1786
cd255eff 1787 netdev->mtu = mtu;
40ab6a6e
AS		 1788 return 0;
1789}
1790
08fb1dac
SM		 1791static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1792{
1793 struct mlx5e_priv *priv = netdev_priv(netdev);
1794 int nch = priv->params.num_channels;
1795 int ntc = priv->params.num_tc;
1796 int tc;
1797
1798 netdev_reset_tc(netdev);
1799
1800 if (ntc == 1)
1801 return;
1802
1803 netdev_set_num_tc(netdev, ntc);
1804
7ccdd084
RS		 1805 /* Map netdev TCs to offset 0
1806 * We have our own UP to TXQ mapping for QoS
1807 */
08fb1dac 1808 for (tc = 0; tc < ntc; tc++)
7ccdd084 1809 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 1810}
1811
40ab6a6e
AS		 1812int mlx5e_open_locked(struct net_device *netdev)
1813{
1814 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 1815 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 1816 int num_txqs;
1817 int err;
1818
1819 set_bit(MLX5E_STATE_OPENED, &priv->state);
1820
08fb1dac
SM		 1821 mlx5e_netdev_set_tcs(netdev);
1822
40ab6a6e
AS		 1823 num_txqs = priv->params.num_channels * priv->params.num_tc;
1824 netif_set_real_num_tx_queues(netdev, num_txqs);
1825 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1826
1827 err = mlx5e_set_dev_port_mtu(netdev);
1828 if (err)
343b29f3 1829 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1830
1831 err = mlx5e_open_channels(priv);
1832 if (err) {
1833 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1834 __func__, err);
343b29f3 1835 goto err_clear_state_opened_flag;
40ab6a6e
AS		 1836 }
1837
724b2aa1 1838 err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
66189961
TT		 1839 if (err) {
1840 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1841 __func__, err);
1842 goto err_close_channels;
1843 }
1844
40ab6a6e 1845 mlx5e_redirect_rqts(priv);
ce89ef36 1846 mlx5e_update_carrier(priv);
ef9814de 1847 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 1848#ifdef CONFIG_RFS_ACCEL
1849 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1850#endif
cb67b832
HHZ		 1851 if (priv->profile->update_stats)
1852 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 1853
cb67b832
HHZ		 1854 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1855 err = mlx5e_add_sqs_fwd_rules(priv);
1856 if (err)
1857 goto err_close_channels;
1858 }
9b37b07f 1859 return 0;
343b29f3 1860
66189961
TT		 1861err_close_channels:
1862 mlx5e_close_channels(priv);
343b29f3
AS		 1863err_clear_state_opened_flag:
1864 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1865 return err;
40ab6a6e
AS		 1866}
1867
cb67b832 1868int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 1869{
1870 struct mlx5e_priv *priv = netdev_priv(netdev);
1871 int err;
1872
1873 mutex_lock(&priv->state_lock);
1874 err = mlx5e_open_locked(netdev);
1875 mutex_unlock(&priv->state_lock);
1876
1877 return err;
1878}
1879
1880int mlx5e_close_locked(struct net_device *netdev)
1881{
1882 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 1883 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 1884
a1985740
AS		 1885 /* May already be CLOSED in case a previous configuration operation
1886 * (e.g RX/TX queue size change) that involves close&open failed.
1887 */
1888 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1889 return 0;
1890
40ab6a6e
AS		 1891 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1892
cb67b832
HHZ		 1893 if (MLX5_CAP_GEN(mdev, vport_group_manager))
1894 mlx5e_remove_sqs_fwd_rules(priv);
1895
ef9814de 1896 mlx5e_timestamp_cleanup(priv);
40ab6a6e 1897 netif_carrier_off(priv->netdev);
ce89ef36 1898 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1899 mlx5e_close_channels(priv);
1900
1901 return 0;
1902}
1903
cb67b832 1904int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 1905{
1906 struct mlx5e_priv *priv = netdev_priv(netdev);
1907 int err;
1908
1909 mutex_lock(&priv->state_lock);
1910 err = mlx5e_close_locked(netdev);
1911 mutex_unlock(&priv->state_lock);
1912
1913 return err;
1914}
1915
1916static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1917 struct mlx5e_rq *rq,
1918 struct mlx5e_rq_param *param)
1919{
1920 struct mlx5_core_dev *mdev = priv->mdev;
1921 void *rqc = param->rqc;
1922 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1923 int err;
1924
1925 param->wq.db_numa_node = param->wq.buf_numa_node;
1926
1927 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1928 &rq->wq_ctrl);
1929 if (err)
1930 return err;
1931
1932 rq->priv = priv;
1933
1934 return 0;
1935}
1936
1937static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1938 struct mlx5e_cq *cq,
1939 struct mlx5e_cq_param *param)
1940{
1941 struct mlx5_core_dev *mdev = priv->mdev;
1942 struct mlx5_core_cq *mcq = &cq->mcq;
1943 int eqn_not_used;
0b6e26ce 1944 unsigned int irqn;
40ab6a6e
AS		 1945 int err;
1946
1947 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1948 &cq->wq_ctrl);
1949 if (err)
1950 return err;
1951
1952 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1953
1954 mcq->cqe_sz = 64;
1955 mcq->set_ci_db = cq->wq_ctrl.db.db;
1956 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1957 *mcq->set_ci_db = 0;
1958 *mcq->arm_db = 0;
1959 mcq->vector = param->eq_ix;
1960 mcq->comp = mlx5e_completion_event;
1961 mcq->event = mlx5e_cq_error_event;
1962 mcq->irqn = irqn;
b50d292b 1963 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 1964
1965 cq->priv = priv;
1966
1967 return 0;
1968}
1969
1970static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1971{
1972 struct mlx5e_cq_param cq_param;
1973 struct mlx5e_rq_param rq_param;
1974 struct mlx5e_rq *rq = &priv->drop_rq;
1975 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1976 int err;
1977
1978 memset(&cq_param, 0, sizeof(cq_param));
1979 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 1980 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 1981
1982 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1983 if (err)
1984 return err;
1985
1986 err = mlx5e_enable_cq(cq, &cq_param);
1987 if (err)
1988 goto err_destroy_cq;
1989
1990 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1991 if (err)
1992 goto err_disable_cq;
1993
1994 err = mlx5e_enable_rq(rq, &rq_param);
1995 if (err)
1996 goto err_destroy_rq;
1997
1998 return 0;
1999
2000err_destroy_rq:
2001 mlx5e_destroy_rq(&priv->drop_rq);
2002
2003err_disable_cq:
2004 mlx5e_disable_cq(&priv->drop_rq.cq);
2005
2006err_destroy_cq:
2007 mlx5e_destroy_cq(&priv->drop_rq.cq);
2008
2009 return err;
2010}
2011
2012static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2013{
2014 mlx5e_disable_rq(&priv->drop_rq);
2015 mlx5e_destroy_rq(&priv->drop_rq);
2016 mlx5e_disable_cq(&priv->drop_rq.cq);
2017 mlx5e_destroy_cq(&priv->drop_rq.cq);
2018}
2019
2020static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2021{
2022 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2023 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2024 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2025
08fb1dac 2026 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2027 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
40ab6a6e
AS		 2028 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2029}
2030
2031static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2032{
2033 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2034}
2035
cb67b832 2036int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2037{
2038 int err;
2039 int tc;
2040
6bfd390b 2041 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2042 err = mlx5e_create_tis(priv, tc);
2043 if (err)
2044 goto err_close_tises;
2045 }
2046
2047 return 0;
2048
2049err_close_tises:
2050 for (tc--; tc >= 0; tc--)
2051 mlx5e_destroy_tis(priv, tc);
2052
2053 return err;
2054}
2055
cb67b832 2056void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2057{
2058 int tc;
2059
6bfd390b 2060 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2061 mlx5e_destroy_tis(priv, tc);
2062}
2063
1da36696
TT		 2064static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2065 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2066{
2067 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2068
b50d292b 2069 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2070
5a6f8aef
AS		 2071#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2072 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2073
5a6f8aef
AS		 2074#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2075 MLX5_HASH_FIELD_SEL_DST_IP |\
2076 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2077 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2078
a741749f
AS		 2079#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2080 MLX5_HASH_FIELD_SEL_DST_IP |\
2081 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2082
5c50368f 2083 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2084
4cbeaff5 2085 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2086 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2087 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2088
2089 switch (tt) {
2090 case MLX5E_TT_IPV4_TCP:
2091 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2092 MLX5_L3_PROT_TYPE_IPV4);
2093 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2094 MLX5_L4_PROT_TYPE_TCP);
2095 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2096 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2097 break;
2098
2099 case MLX5E_TT_IPV6_TCP:
2100 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2101 MLX5_L3_PROT_TYPE_IPV6);
2102 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2103 MLX5_L4_PROT_TYPE_TCP);
2104 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2105 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2106 break;
2107
2108 case MLX5E_TT_IPV4_UDP:
2109 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2110 MLX5_L3_PROT_TYPE_IPV4);
2111 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2112 MLX5_L4_PROT_TYPE_UDP);
2113 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2114 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2115 break;
2116
2117 case MLX5E_TT_IPV6_UDP:
2118 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2119 MLX5_L3_PROT_TYPE_IPV6);
2120 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2121 MLX5_L4_PROT_TYPE_UDP);
2122 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2123 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2124 break;
2125
a741749f
AS		 2126 case MLX5E_TT_IPV4_IPSEC_AH:
2127 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2128 MLX5_L3_PROT_TYPE_IPV4);
2129 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2130 MLX5_HASH_IP_IPSEC_SPI);
2131 break;
2132
2133 case MLX5E_TT_IPV6_IPSEC_AH:
2134 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2135 MLX5_L3_PROT_TYPE_IPV6);
2136 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2137 MLX5_HASH_IP_IPSEC_SPI);
2138 break;
2139
2140 case MLX5E_TT_IPV4_IPSEC_ESP:
2141 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2142 MLX5_L3_PROT_TYPE_IPV4);
2143 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2144 MLX5_HASH_IP_IPSEC_SPI);
2145 break;
2146
2147 case MLX5E_TT_IPV6_IPSEC_ESP:
2148 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2149 MLX5_L3_PROT_TYPE_IPV6);
2150 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2151 MLX5_HASH_IP_IPSEC_SPI);
2152 break;
2153
f62b8bb8
AV		 2154 case MLX5E_TT_IPV4:
2155 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2156 MLX5_L3_PROT_TYPE_IPV4);
2157 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2158 MLX5_HASH_IP);
2159 break;
2160
2161 case MLX5E_TT_IPV6:
2162 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2163 MLX5_L3_PROT_TYPE_IPV6);
2164 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2165 MLX5_HASH_IP);
2166 break;
1da36696
TT		 2167 default:
2168 WARN_ONCE(true,
2169 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2170 }
2171}
2172
1da36696
TT		 2173static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2174 u32 rqtn)
f62b8bb8 2175{
b50d292b 2176 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2177
2178 mlx5e_build_tir_ctx_lro(tirc, priv);
2179
2180 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2181 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2182 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2183}
2184
6bfd390b 2185static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2186{
724b2aa1 2187 struct mlx5e_tir *tir;
f62b8bb8
AV		 2188 void *tirc;
2189 int inlen;
2190 int err;
1da36696 2191 u32 *in;
1da36696 2192 int tt;
f62b8bb8
AV		 2193
2194 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2195 in = mlx5_vzalloc(inlen);
2196 if (!in)
2197 return -ENOMEM;
2198
1da36696
TT		 2199 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2200 memset(in, 0, inlen);
724b2aa1 2201 tir = &priv->indir_tir[tt];
1da36696
TT		 2202 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2203 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2204 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2205 if (err)
40ab6a6e 2206 goto err_destroy_tirs;
f62b8bb8
AV		 2207 }
2208
6bfd390b
HHZ		 2209 kvfree(in);
2210
2211 return 0;
2212
2213err_destroy_tirs:
2214 for (tt--; tt >= 0; tt--)
2215 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2216
2217 kvfree(in);
2218
2219 return err;
2220}
2221
cb67b832 2222int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2223{
2224 int nch = priv->profile->max_nch(priv->mdev);
2225 struct mlx5e_tir *tir;
2226 void *tirc;
2227 int inlen;
2228 int err;
2229 u32 *in;
2230 int ix;
2231
2232 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2233 in = mlx5_vzalloc(inlen);
2234 if (!in)
2235 return -ENOMEM;
2236
1da36696
TT		 2237 for (ix = 0; ix < nch; ix++) {
2238 memset(in, 0, inlen);
724b2aa1 2239 tir = &priv->direct_tir[ix];
1da36696
TT		 2240 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2241 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2242 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2243 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2244 if (err)
2245 goto err_destroy_ch_tirs;
2246 }
2247
2248 kvfree(in);
2249
f62b8bb8
AV		 2250 return 0;
2251
1da36696
TT		 2252err_destroy_ch_tirs:
2253 for (ix--; ix >= 0; ix--)
724b2aa1 2254 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2255
1da36696 2256 kvfree(in);
f62b8bb8
AV		 2257
2258 return err;
2259}
2260
6bfd390b 2261static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2262{
2263 int i;
2264
1da36696 2265 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2266 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2267}
2268
cb67b832 2269void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2270{
2271 int nch = priv->profile->max_nch(priv->mdev);
2272 int i;
2273
2274 for (i = 0; i < nch; i++)
2275 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2276}
2277
36350114
GP		 2278int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2279{
2280 int err = 0;
2281 int i;
2282
2283 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2284 return 0;
2285
2286 for (i = 0; i < priv->params.num_channels; i++) {
2287 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2288 if (err)
2289 return err;
2290 }
2291
2292 return 0;
2293}
2294
08fb1dac
SM		 2295static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2296{
2297 struct mlx5e_priv *priv = netdev_priv(netdev);
2298 bool was_opened;
2299 int err = 0;
2300
2301 if (tc && tc != MLX5E_MAX_NUM_TC)
2302 return -EINVAL;
2303
2304 mutex_lock(&priv->state_lock);
2305
2306 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2307 if (was_opened)
2308 mlx5e_close_locked(priv->netdev);
2309
2310 priv->params.num_tc = tc ? tc : 1;
2311
2312 if (was_opened)
2313 err = mlx5e_open_locked(priv->netdev);
2314
2315 mutex_unlock(&priv->state_lock);
2316
2317 return err;
2318}
2319
2320static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2321 __be16 proto, struct tc_to_netdev *tc)
2322{
e8f887ac
AV		 2323 struct mlx5e_priv *priv = netdev_priv(dev);
2324
2325 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2326 goto mqprio;
2327
2328 switch (tc->type) {
e3a2b7ed
AV		 2329 case TC_SETUP_CLSFLOWER:
2330 switch (tc->cls_flower->command) {
2331 case TC_CLSFLOWER_REPLACE:
2332 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2333 case TC_CLSFLOWER_DESTROY:
2334 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2335 case TC_CLSFLOWER_STATS:
2336 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2337 }
e8f887ac
AV		 2338 default:
2339 return -EOPNOTSUPP;
2340 }
2341
2342mqprio:
67ba422e 2343 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2344 return -EINVAL;
2345
2346 return mlx5e_setup_tc(dev, tc->tc);
2347}
2348
cb67b832 2349struct rtnl_link_stats64 *
f62b8bb8
AV		 2350mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2351{
2352 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2353 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2354 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2355 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2356
9218b44d
GP		 2357 stats->rx_packets = sstats->rx_packets;
2358 stats->rx_bytes = sstats->rx_bytes;
2359 stats->tx_packets = sstats->tx_packets;
2360 stats->tx_bytes = sstats->tx_bytes;
269e6b3a
GP		 2361
2362 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
9218b44d 2363 stats->tx_dropped = sstats->tx_queue_dropped;
269e6b3a
GP		 2364
2365 stats->rx_length_errors =
9218b44d
GP		 2366 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2367 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2368 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2369 stats->rx_crc_errors =
9218b44d
GP		 2370 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2371 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2372 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2373 stats->tx_carrier_errors =
9218b44d 2374 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2375 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2376 stats->rx_frame_errors;
2377 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2378
2379 /* vport multicast also counts packets that are dropped due to steering
2380 * or rx out of buffer
2381 */
9218b44d
GP		 2382 stats->multicast =
2383 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2384
2385 return stats;
2386}
2387
2388static void mlx5e_set_rx_mode(struct net_device *dev)
2389{
2390 struct mlx5e_priv *priv = netdev_priv(dev);
2391
7bb29755 2392 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2393}
2394
2395static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2396{
2397 struct mlx5e_priv *priv = netdev_priv(netdev);
2398 struct sockaddr *saddr = addr;
2399
2400 if (!is_valid_ether_addr(saddr->sa_data))
2401 return -EADDRNOTAVAIL;
2402
2403 netif_addr_lock_bh(netdev);
2404 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2405 netif_addr_unlock_bh(netdev);
2406
7bb29755 2407 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2408
2409 return 0;
2410}
2411
0e405443
GP		 2412#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2413 do { \
2414 if (enable) \
2415 netdev->features |= feature; \
2416 else \
2417 netdev->features &= ~feature; \
2418 } while (0)
2419
2420typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2421
2422static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2423{
2424 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2425 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2426 int err;
f62b8bb8
AV		 2427
2428 mutex_lock(&priv->state_lock);
f62b8bb8 2429
0e405443
GP		 2430 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2431 mlx5e_close_locked(priv->netdev);
98e81b0a 2432
0e405443
GP		 2433 priv->params.lro_en = enable;
2434 err = mlx5e_modify_tirs_lro(priv);
2435 if (err) {
2436 netdev_err(netdev, "lro modify failed, %d\n", err);
2437 priv->params.lro_en = !enable;
98e81b0a 2438 }
f62b8bb8 2439
0e405443
GP		 2440 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2441 mlx5e_open_locked(priv->netdev);
2442
9b37b07f
AS		 2443 mutex_unlock(&priv->state_lock);
2444
0e405443
GP		 2445 return err;
2446}
2447
2448static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2449{
2450 struct mlx5e_priv *priv = netdev_priv(netdev);
2451
2452 if (enable)
2453 mlx5e_enable_vlan_filter(priv);
2454 else
2455 mlx5e_disable_vlan_filter(priv);
2456
2457 return 0;
2458}
2459
2460static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2461{
2462 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2463
0e405443 2464 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2465 netdev_err(netdev,
2466 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2467 return -EINVAL;
2468 }
2469
0e405443
GP		 2470 return 0;
2471}
2472
94cb1ebb
EBE		 2473static int set_feature_rx_all(struct net_device *netdev, bool enable)
2474{
2475 struct mlx5e_priv *priv = netdev_priv(netdev);
2476 struct mlx5_core_dev *mdev = priv->mdev;
2477
2478 return mlx5_set_port_fcs(mdev, !enable);
2479}
2480
36350114
GP		 2481static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2482{
2483 struct mlx5e_priv *priv = netdev_priv(netdev);
2484 int err;
2485
2486 mutex_lock(&priv->state_lock);
2487
2488 priv->params.vlan_strip_disable = !enable;
2489 err = mlx5e_modify_rqs_vsd(priv, !enable);
2490 if (err)
2491 priv->params.vlan_strip_disable = enable;
2492
2493 mutex_unlock(&priv->state_lock);
2494
2495 return err;
2496}
2497
45bf454a
MG		 2498#ifdef CONFIG_RFS_ACCEL
2499static int set_feature_arfs(struct net_device *netdev, bool enable)
2500{
2501 struct mlx5e_priv *priv = netdev_priv(netdev);
2502 int err;
2503
2504 if (enable)
2505 err = mlx5e_arfs_enable(priv);
2506 else
2507 err = mlx5e_arfs_disable(priv);
2508
2509 return err;
2510}
2511#endif
2512
0e405443
GP		 2513static int mlx5e_handle_feature(struct net_device *netdev,
2514 netdev_features_t wanted_features,
2515 netdev_features_t feature,
2516 mlx5e_feature_handler feature_handler)
2517{
2518 netdev_features_t changes = wanted_features ^ netdev->features;
2519 bool enable = !!(wanted_features & feature);
2520 int err;
2521
2522 if (!(changes & feature))
2523 return 0;
2524
2525 err = feature_handler(netdev, enable);
2526 if (err) {
2527 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2528 enable ? "Enable" : "Disable", feature, err);
2529 return err;
2530 }
2531
2532 MLX5E_SET_FEATURE(netdev, feature, enable);
2533 return 0;
2534}
2535
2536static int mlx5e_set_features(struct net_device *netdev,
2537 netdev_features_t features)
2538{
2539 int err;
2540
2541 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2542 set_feature_lro);
2543 err |= mlx5e_handle_feature(netdev, features,
2544 NETIF_F_HW_VLAN_CTAG_FILTER,
2545 set_feature_vlan_filter);
2546 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2547 set_feature_tc_num_filters);
94cb1ebb
EBE		 2548 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2549 set_feature_rx_all);
36350114
GP		 2550 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2551 set_feature_rx_vlan);
45bf454a
MG		 2552#ifdef CONFIG_RFS_ACCEL
2553 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2554 set_feature_arfs);
2555#endif
0e405443
GP		 2556
2557 return err ? -EINVAL : 0;
f62b8bb8
AV		 2558}
2559
d8edd246
SM		 2560#define MXL5_HW_MIN_MTU 64
2561#define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2562
f62b8bb8
AV		 2563static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2564{
2565 struct mlx5e_priv *priv = netdev_priv(netdev);
2566 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 2567 bool was_opened;
046339ea 2568 u16 max_mtu;
d8edd246 2569 u16 min_mtu;
98e81b0a 2570 int err = 0;
f62b8bb8 2571
facc9699 2572 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 2573
50a9eea6 2574 max_mtu = MLX5E_HW2SW_MTU(max_mtu);
d8edd246 2575 min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
50a9eea6 2576
d8edd246 2577 if (new_mtu > max_mtu || new_mtu < min_mtu) {
facc9699 2578 netdev_err(netdev,
d8edd246
SM		 2579 "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2580 __func__, new_mtu, min_mtu, max_mtu);
f62b8bb8
AV		 2581 return -EINVAL;
2582 }
2583
2584 mutex_lock(&priv->state_lock);
98e81b0a
AS		 2585
2586 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2587 if (was_opened)
2588 mlx5e_close_locked(netdev);
2589
f62b8bb8 2590 netdev->mtu = new_mtu;
98e81b0a
AS		 2591
2592 if (was_opened)
2593 err = mlx5e_open_locked(netdev);
2594
f62b8bb8
AV		 2595 mutex_unlock(&priv->state_lock);
2596
2597 return err;
2598}
2599
ef9814de
EBE		 2600static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2601{
2602 switch (cmd) {
2603 case SIOCSHWTSTAMP:
2604 return mlx5e_hwstamp_set(dev, ifr);
2605 case SIOCGHWTSTAMP:
2606 return mlx5e_hwstamp_get(dev, ifr);
2607 default:
2608 return -EOPNOTSUPP;
2609 }
2610}
2611
66e49ded
SM		 2612static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2613{
2614 struct mlx5e_priv *priv = netdev_priv(dev);
2615 struct mlx5_core_dev *mdev = priv->mdev;
2616
2617 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2618}
2619
2620static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2621{
2622 struct mlx5e_priv *priv = netdev_priv(dev);
2623 struct mlx5_core_dev *mdev = priv->mdev;
2624
2625 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2626 vlan, qos);
2627}
2628
f942380c
MHY		 2629static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2630{
2631 struct mlx5e_priv *priv = netdev_priv(dev);
2632 struct mlx5_core_dev *mdev = priv->mdev;
2633
2634 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2635}
2636
1edc57e2
MHY		 2637static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2638{
2639 struct mlx5e_priv *priv = netdev_priv(dev);
2640 struct mlx5_core_dev *mdev = priv->mdev;
2641
2642 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2643}
66e49ded
SM		 2644static int mlx5_vport_link2ifla(u8 esw_link)
2645{
2646 switch (esw_link) {
2647 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2648 return IFLA_VF_LINK_STATE_DISABLE;
2649 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2650 return IFLA_VF_LINK_STATE_ENABLE;
2651 }
2652 return IFLA_VF_LINK_STATE_AUTO;
2653}
2654
2655static int mlx5_ifla_link2vport(u8 ifla_link)
2656{
2657 switch (ifla_link) {
2658 case IFLA_VF_LINK_STATE_DISABLE:
2659 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2660 case IFLA_VF_LINK_STATE_ENABLE:
2661 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2662 }
2663 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2664}
2665
2666static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2667 int link_state)
2668{
2669 struct mlx5e_priv *priv = netdev_priv(dev);
2670 struct mlx5_core_dev *mdev = priv->mdev;
2671
2672 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2673 mlx5_ifla_link2vport(link_state));
2674}
2675
2676static int mlx5e_get_vf_config(struct net_device *dev,
2677 int vf, struct ifla_vf_info *ivi)
2678{
2679 struct mlx5e_priv *priv = netdev_priv(dev);
2680 struct mlx5_core_dev *mdev = priv->mdev;
2681 int err;
2682
2683 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2684 if (err)
2685 return err;
2686 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2687 return 0;
2688}
2689
2690static int mlx5e_get_vf_stats(struct net_device *dev,
2691 int vf, struct ifla_vf_stats *vf_stats)
2692{
2693 struct mlx5e_priv *priv = netdev_priv(dev);
2694 struct mlx5_core_dev *mdev = priv->mdev;
2695
2696 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2697 vf_stats);
2698}
2699
b3f63c3d 2700static void mlx5e_add_vxlan_port(struct net_device *netdev,
974c3f30 2701 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2702{
2703 struct mlx5e_priv *priv = netdev_priv(netdev);
2704
974c3f30
AD		 2705 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2706 return;
2707
b3f63c3d
MF		 2708 if (!mlx5e_vxlan_allowed(priv->mdev))
2709 return;
2710
974c3f30 2711 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 2712}
2713
2714static void mlx5e_del_vxlan_port(struct net_device *netdev,
974c3f30 2715 struct udp_tunnel_info *ti)
b3f63c3d
MF		 2716{
2717 struct mlx5e_priv *priv = netdev_priv(netdev);
2718
974c3f30
AD		 2719 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2720 return;
2721
b3f63c3d
MF		 2722 if (!mlx5e_vxlan_allowed(priv->mdev))
2723 return;
2724
974c3f30 2725 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 2726}
2727
2728static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2729 struct sk_buff *skb,
2730 netdev_features_t features)
2731{
2732 struct udphdr *udph;
2733 u16 proto;
2734 u16 port = 0;
2735
2736 switch (vlan_get_protocol(skb)) {
2737 case htons(ETH_P_IP):
2738 proto = ip_hdr(skb)->protocol;
2739 break;
2740 case htons(ETH_P_IPV6):
2741 proto = ipv6_hdr(skb)->nexthdr;
2742 break;
2743 default:
2744 goto out;
2745 }
2746
2747 if (proto == IPPROTO_UDP) {
2748 udph = udp_hdr(skb);
2749 port = be16_to_cpu(udph->dest);
2750 }
2751
2752 /* Verify if UDP port is being offloaded by HW */
2753 if (port && mlx5e_vxlan_lookup_port(priv, port))
2754 return features;
2755
2756out:
2757 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2758 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2759}
2760
2761static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2762 struct net_device *netdev,
2763 netdev_features_t features)
2764{
2765 struct mlx5e_priv *priv = netdev_priv(netdev);
2766
2767 features = vlan_features_check(skb, features);
2768 features = vxlan_features_check(skb, features);
2769
2770 /* Validate if the tunneled packet is being offloaded by HW */
2771 if (skb->encapsulation &&
2772 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2773 return mlx5e_vxlan_features_check(priv, skb, features);
2774
2775 return features;
2776}
2777
3947ca18
DJ		 2778static void mlx5e_tx_timeout(struct net_device *dev)
2779{
2780 struct mlx5e_priv *priv = netdev_priv(dev);
2781 bool sched_work = false;
2782 int i;
2783
2784 netdev_err(dev, "TX timeout detected\n");
2785
2786 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2787 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2788
2c1ccc99 2789 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 2790 continue;
2791 sched_work = true;
2792 set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state);
2793 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2794 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2795 }
2796
2797 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2798 schedule_work(&priv->tx_timeout_work);
2799}
2800
b0eed40e 2801static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 2802 .ndo_open = mlx5e_open,
2803 .ndo_stop = mlx5e_close,
2804 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2805 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2806 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 2807 .ndo_get_stats64 = mlx5e_get_stats,
2808 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2809 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 2810 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2811 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 2812 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 2813 .ndo_change_mtu = mlx5e_change_mtu,
2814 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 2815 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 2816#ifdef CONFIG_RFS_ACCEL
2817 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2818#endif
3947ca18 2819 .ndo_tx_timeout = mlx5e_tx_timeout,
b0eed40e
SM		 2820};
2821
2822static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2823 .ndo_open = mlx5e_open,
2824 .ndo_stop = mlx5e_close,
2825 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 2826 .ndo_setup_tc = mlx5e_ndo_setup_tc,
2827 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 2828 .ndo_get_stats64 = mlx5e_get_stats,
2829 .ndo_set_rx_mode = mlx5e_set_rx_mode,
2830 .ndo_set_mac_address = mlx5e_set_mac,
2831 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
2832 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
2833 .ndo_set_features = mlx5e_set_features,
2834 .ndo_change_mtu = mlx5e_change_mtu,
2835 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 2836 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
2837 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 2838 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 2839 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 2840#ifdef CONFIG_RFS_ACCEL
2841 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
2842#endif
b0eed40e
SM		 2843 .ndo_set_vf_mac = mlx5e_set_vf_mac,
2844 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 2845 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 2846 .ndo_set_vf_trust = mlx5e_set_vf_trust,
b0eed40e
SM		 2847 .ndo_get_vf_config = mlx5e_get_vf_config,
2848 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
2849 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 2850 .ndo_tx_timeout = mlx5e_tx_timeout,
f62b8bb8
AV		 2851};
2852
2853static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2854{
2855 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2856 return -ENOTSUPP;
2857 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2858 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2859 !MLX5_CAP_ETH(mdev, csum_cap) ||
2860 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2861 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 2862 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2863 MLX5_CAP_FLOWTABLE(mdev,
2864 flow_table_properties_nic_receive.max_ft_level)
2865 < 3) {
f62b8bb8
AV		 2866 mlx5_core_warn(mdev,
2867 "Not creating net device, some required device capabilities are missing\n");
2868 return -ENOTSUPP;
2869 }
66189961
TT		 2870 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2871 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 2872 if (!MLX5_CAP_GEN(mdev, cq_moderation))
2873 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 2874
f62b8bb8
AV		 2875 return 0;
2876}
2877
58d52291
AS		 2878u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2879{
2880 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2881
2882 return bf_buf_size -
2883 sizeof(struct mlx5e_tx_wqe) +
2884 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2885}
2886
08fb1dac
SM		 2887#ifdef CONFIG_MLX5_CORE_EN_DCB
2888static void mlx5e_ets_init(struct mlx5e_priv *priv)
2889{
2890 int i;
2891
2892 priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2893 for (i = 0; i < priv->params.ets.ets_cap; i++) {
2894 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2895 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2896 priv->params.ets.prio_tc[i] = i;
2897 }
2898
2899 /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2900 priv->params.ets.prio_tc[0] = 1;
2901 priv->params.ets.prio_tc[1] = 0;
2902}
2903#endif
2904
d8c9660d
TT		 2905void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2906 u32 *indirection_rqt, int len,
85082dba
TT		 2907 int num_channels)
2908{
d8c9660d
TT		 2909 int node = mdev->priv.numa_node;
2910 int node_num_of_cores;
85082dba
TT		 2911 int i;
2912
d8c9660d
TT		 2913 if (node == -1)
2914 node = first_online_node;
2915
2916 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2917
2918 if (node_num_of_cores)
2919 num_channels = min_t(int, num_channels, node_num_of_cores);
2920
85082dba
TT		 2921 for (i = 0; i < len; i++)
2922 indirection_rqt[i] = i % num_channels;
2923}
2924
bc77b240
TT		 2925static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2926{
2927 return MLX5_CAP_GEN(mdev, striding_rq) &&
2928 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2929 MLX5_CAP_ETH(mdev, reg_umr_sq);
2930}
2931
b797a684
SM		 2932static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2933{
2934 enum pcie_link_width width;
2935 enum pci_bus_speed speed;
2936 int err = 0;
2937
2938 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2939 if (err)
2940 return err;
2941
2942 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2943 return -EINVAL;
2944
2945 switch (speed) {
2946 case PCIE_SPEED_2_5GT:
2947 *pci_bw = 2500 * width;
2948 break;
2949 case PCIE_SPEED_5_0GT:
2950 *pci_bw = 5000 * width;
2951 break;
2952 case PCIE_SPEED_8_0GT:
2953 *pci_bw = 8000 * width;
2954 break;
2955 default:
2956 return -EINVAL;
2957 }
2958
2959 return 0;
2960}
2961
2962static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2963{
2964 return (link_speed && pci_bw &&
2965 (pci_bw < 40000) && (pci_bw < link_speed));
2966}
2967
9908aa29
TT		 2968void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2969{
2970 params->rx_cq_period_mode = cq_period_mode;
2971
2972 params->rx_cq_moderation.pkts =
2973 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2974 params->rx_cq_moderation.usec =
2975 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2976
2977 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2978 params->rx_cq_moderation.usec =
2979 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2980}
2981
cff92d7c
HHZ		 2982static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
2983 u8 *min_inline_mode)
2984{
2985 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
2986 case MLX5E_INLINE_MODE_L2:
2987 *min_inline_mode = MLX5_INLINE_MODE_L2;
2988 break;
2989 case MLX5E_INLINE_MODE_VPORT_CONTEXT:
2990 mlx5_query_nic_vport_min_inline(mdev,
2991 min_inline_mode);
2992 break;
2993 case MLX5_INLINE_MODE_NOT_REQUIRED:
2994 *min_inline_mode = MLX5_INLINE_MODE_NONE;
2995 break;
2996 }
2997}
2998
6bfd390b
HHZ		 2999static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3000 struct net_device *netdev,
127ea380
HHZ		 3001 const struct mlx5e_profile *profile,
3002 void *ppriv)
f62b8bb8
AV		 3003{
3004 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3005 u32 link_speed = 0;
3006 u32 pci_bw = 0;
cb3c7fd4
GR		 3007 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3008 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3009 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 3010
3011 priv->params.log_sq_size =
3012 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
bc77b240 3013 priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
461017cb
TT		 3014 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3015 MLX5_WQ_TYPE_LINKED_LIST;
3016
b797a684
SM		 3017 /* set CQE compression */
3018 priv->params.rx_cqe_compress_admin = false;
3019 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3020 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3021 mlx5e_get_max_linkspeed(mdev, &link_speed);
3022 mlx5e_get_pci_bw(mdev, &pci_bw);
3023 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3024 link_speed, pci_bw);
3025 priv->params.rx_cqe_compress_admin =
3026 cqe_compress_heuristic(link_speed, pci_bw);
3027 }
3028
3029 priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3030
461017cb
TT		 3031 switch (priv->params.rq_wq_type) {
3032 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3033 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
d9d9f156
TT		 3034 priv->params.mpwqe_log_stride_sz =
3035 priv->params.rx_cqe_compress ?
3036 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3037 MLX5_MPWRQ_LOG_STRIDE_SIZE;
3038 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3039 priv->params.mpwqe_log_stride_sz;
461017cb
TT		 3040 priv->params.lro_en = true;
3041 break;
3042 default: /* MLX5_WQ_TYPE_LINKED_LIST */
3043 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3044 }
3045
d9d9f156
TT		 3046 mlx5_core_info(mdev,
3047 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3048 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3049 BIT(priv->params.log_rq_size),
3050 BIT(priv->params.mpwqe_log_stride_sz),
3051 priv->params.rx_cqe_compress_admin);
3052
461017cb
TT		 3053 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3054 BIT(priv->params.log_rq_size));
9908aa29 3055
cb3c7fd4
GR		 3056 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3057 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3058
3059 priv->params.tx_cq_moderation.usec =
f62b8bb8 3060 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3061 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3062 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3063 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3064 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3065 priv->params.num_tc = 1;
2be6967c 3066 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3067
57afead5
AS		 3068 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3069 sizeof(priv->params.toeplitz_hash_key));
3070
d8c9660d 3071 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3072 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3073
f62b8bb8
AV		 3074 priv->params.lro_wqe_sz =
3075 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3076
9908aa29
TT		 3077 /* Initialize pflags */
3078 MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3079 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3080
f62b8bb8
AV		 3081 priv->mdev = mdev;
3082 priv->netdev = netdev;
6bfd390b
HHZ		 3083 priv->params.num_channels = profile->max_nch(mdev);
3084 priv->profile = profile;
127ea380 3085 priv->ppriv = ppriv;
f62b8bb8 3086
08fb1dac
SM		 3087#ifdef CONFIG_MLX5_CORE_EN_DCB
3088 mlx5e_ets_init(priv);
3089#endif
f62b8bb8 3090
f62b8bb8
AV		 3091 mutex_init(&priv->state_lock);
3092
3093 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3094 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3095 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3096 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3097}
3098
3099static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3100{
3101 struct mlx5e_priv *priv = netdev_priv(netdev);
3102
e1d7d349 3103 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3104 if (is_zero_ether_addr(netdev->dev_addr) &&
3105 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3106 eth_hw_addr_random(netdev);
3107 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3108 }
f62b8bb8
AV		 3109}
3110
cb67b832
HHZ		 3111static const struct switchdev_ops mlx5e_switchdev_ops = {
3112 .switchdev_port_attr_get = mlx5e_attr_get,
3113};
3114
6bfd390b 3115static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3116{
3117 struct mlx5e_priv *priv = netdev_priv(netdev);
3118 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3119 bool fcs_supported;
3120 bool fcs_enabled;
f62b8bb8
AV		 3121
3122 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3123
08fb1dac 3124 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3125 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac
SM		 3126#ifdef CONFIG_MLX5_CORE_EN_DCB
3127 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3128#endif
3129 } else {
b0eed40e 3130 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3131 }
66e49ded 3132
f62b8bb8
AV		 3133 netdev->watchdog_timeo = 15 * HZ;
3134
3135 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3136
12be4b21 3137 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3138 netdev->vlan_features |= NETIF_F_IP_CSUM;
3139 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3140 netdev->vlan_features |= NETIF_F_GRO;
3141 netdev->vlan_features |= NETIF_F_TSO;
3142 netdev->vlan_features |= NETIF_F_TSO6;
3143 netdev->vlan_features |= NETIF_F_RXCSUM;
3144 netdev->vlan_features |= NETIF_F_RXHASH;
3145
3146 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3147 netdev->vlan_features |= NETIF_F_LRO;
3148
3149 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3150 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3151 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3152 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3153
b3f63c3d 3154 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3155 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3156 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3157 NETIF_F_GSO_PARTIAL;
b3f63c3d 3158 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3159 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3160 netdev->hw_enc_features |= NETIF_F_TSO;
3161 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3162 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3163 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3164 NETIF_F_GSO_PARTIAL;
3165 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3166 }
3167
94cb1ebb
EBE		 3168 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3169
3170 if (fcs_supported)
3171 netdev->hw_features |= NETIF_F_RXALL;
3172
f62b8bb8
AV		 3173 netdev->features = netdev->hw_features;
3174 if (!priv->params.lro_en)
3175 netdev->features &= ~NETIF_F_LRO;
3176
94cb1ebb
EBE		 3177 if (fcs_enabled)
3178 netdev->features &= ~NETIF_F_RXALL;
3179
e8f887ac
AV		 3180#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3181 if (FT_CAP(flow_modify_en) &&
3182 FT_CAP(modify_root) &&
3183 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3184 FT_CAP(flow_table_modify)) {
3185 netdev->hw_features |= NETIF_F_HW_TC;
3186#ifdef CONFIG_RFS_ACCEL
3187 netdev->hw_features |= NETIF_F_NTUPLE;
3188#endif
3189 }
e8f887ac 3190
f62b8bb8
AV		 3191 netdev->features |= NETIF_F_HIGHDMA;
3192
3193 netdev->priv_flags |= IFF_UNICAST_FLT;
3194
3195 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3196
3197#ifdef CONFIG_NET_SWITCHDEV
3198 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3199 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3200#endif
f62b8bb8
AV		 3201}
3202
593cf338
RS		 3203static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3204{
3205 struct mlx5_core_dev *mdev = priv->mdev;
3206 int err;
3207
3208 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3209 if (err) {
3210 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3211 priv->q_counter = 0;
3212 }
3213}
3214
3215static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3216{
3217 if (!priv->q_counter)
3218 return;
3219
3220 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3221}
3222
bc77b240
TT		 3223static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3224{
3225 struct mlx5_core_dev *mdev = priv->mdev;
ec22eb53
SM		 3226 u64 npages = priv->profile->max_nch(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3227 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3228 void *mkc;
3229 u32 *in;
bc77b240
TT		 3230 int err;
3231
3232 in = mlx5_vzalloc(inlen);
3233 if (!in)
3234 return -ENOMEM;
3235
ec22eb53 3236 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3237
ec22eb53
SM		 3238 MLX5_SET(mkc, mkc, free, 1);
3239 MLX5_SET(mkc, mkc, umr_en, 1);
3240 MLX5_SET(mkc, mkc, lw, 1);
3241 MLX5_SET(mkc, mkc, lr, 1);
3242 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3243
ec22eb53
SM		 3244 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3245 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3246 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3247 MLX5_SET(mkc, mkc, translations_octword_size,
3248 mlx5e_get_mtt_octw(npages));
3249 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3250
ec22eb53 3251 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3252
ec22eb53 3253 kvfree(in);
bc77b240
TT		 3254 return err;
3255}
3256
6bfd390b
HHZ		 3257static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3258 struct net_device *netdev,
127ea380
HHZ		 3259 const struct mlx5e_profile *profile,
3260 void *ppriv)
6bfd390b
HHZ		 3261{
3262 struct mlx5e_priv *priv = netdev_priv(netdev);
3263
127ea380 3264 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3265 mlx5e_build_nic_netdev(netdev);
3266 mlx5e_vxlan_init(priv);
3267}
3268
3269static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3270{
127ea380
HHZ		 3271 struct mlx5_core_dev *mdev = priv->mdev;
3272 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3273
6bfd390b 3274 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3275
3276 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3277 mlx5_eswitch_unregister_vport_rep(esw, 0);
6bfd390b
HHZ		 3278}
3279
3280static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3281{
3282 struct mlx5_core_dev *mdev = priv->mdev;
3283 int err;
3284 int i;
3285
3286 err = mlx5e_create_indirect_rqts(priv);
3287 if (err) {
3288 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3289 return err;
3290 }
3291
3292 err = mlx5e_create_direct_rqts(priv);
3293 if (err) {
3294 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3295 goto err_destroy_indirect_rqts;
3296 }
3297
3298 err = mlx5e_create_indirect_tirs(priv);
3299 if (err) {
3300 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3301 goto err_destroy_direct_rqts;
3302 }
3303
3304 err = mlx5e_create_direct_tirs(priv);
3305 if (err) {
3306 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3307 goto err_destroy_indirect_tirs;
3308 }
3309
3310 err = mlx5e_create_flow_steering(priv);
3311 if (err) {
3312 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3313 goto err_destroy_direct_tirs;
3314 }
3315
3316 err = mlx5e_tc_init(priv);
3317 if (err)
3318 goto err_destroy_flow_steering;
3319
3320 return 0;
3321
3322err_destroy_flow_steering:
3323 mlx5e_destroy_flow_steering(priv);
3324err_destroy_direct_tirs:
3325 mlx5e_destroy_direct_tirs(priv);
3326err_destroy_indirect_tirs:
3327 mlx5e_destroy_indirect_tirs(priv);
3328err_destroy_direct_rqts:
3329 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3330 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3331err_destroy_indirect_rqts:
3332 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3333 return err;
3334}
3335
3336static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3337{
3338 int i;
3339
3340 mlx5e_tc_cleanup(priv);
3341 mlx5e_destroy_flow_steering(priv);
3342 mlx5e_destroy_direct_tirs(priv);
3343 mlx5e_destroy_indirect_tirs(priv);
3344 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3345 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3346 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3347}
3348
3349static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3350{
3351 int err;
3352
3353 err = mlx5e_create_tises(priv);
3354 if (err) {
3355 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3356 return err;
3357 }
3358
3359#ifdef CONFIG_MLX5_CORE_EN_DCB
3360 mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3361#endif
3362 return 0;
3363}
3364
3365static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3366{
3367 struct net_device *netdev = priv->netdev;
3368 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3369 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3370 struct mlx5_eswitch_rep rep;
6bfd390b 3371
7907f23a
AH		 3372 mlx5_lag_add(mdev, netdev);
3373
6bfd390b
HHZ		 3374 if (mlx5e_vxlan_allowed(mdev)) {
3375 rtnl_lock();
3376 udp_tunnel_get_rx_info(netdev);
3377 rtnl_unlock();
3378 }
3379
3380 mlx5e_enable_async_events(priv);
3381 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3382
3383 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
cb67b832
HHZ		 3384 rep.load = mlx5e_nic_rep_load;
3385 rep.unload = mlx5e_nic_rep_unload;
127ea380
HHZ		 3386 rep.vport = 0;
3387 rep.priv_data = priv;
3388 mlx5_eswitch_register_vport_rep(esw, &rep);
3389 }
6bfd390b
HHZ		 3390}
3391
3392static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3393{
3394 queue_work(priv->wq, &priv->set_rx_mode_work);
3395 mlx5e_disable_async_events(priv);
7907f23a 3396 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3397}
3398
3399static const struct mlx5e_profile mlx5e_nic_profile = {
3400 .init = mlx5e_nic_init,
3401 .cleanup = mlx5e_nic_cleanup,
3402 .init_rx = mlx5e_init_nic_rx,
3403 .cleanup_rx = mlx5e_cleanup_nic_rx,
3404 .init_tx = mlx5e_init_nic_tx,
3405 .cleanup_tx = mlx5e_cleanup_nic_tx,
3406 .enable = mlx5e_nic_enable,
3407 .disable = mlx5e_nic_disable,
3408 .update_stats = mlx5e_update_stats,
3409 .max_nch = mlx5e_get_max_num_channels,
3410 .max_tc = MLX5E_MAX_NUM_TC,
3411};
3412
cb67b832
HHZ		 3413void *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3414 const struct mlx5e_profile *profile, void *ppriv)
f62b8bb8
AV		 3415{
3416 struct net_device *netdev;
3417 struct mlx5e_priv *priv;
6bfd390b 3418 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3419 int err;
3420
08fb1dac 3421 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3422 nch * profile->max_tc,
08fb1dac 3423 nch);
f62b8bb8
AV		 3424 if (!netdev) {
3425 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3426 return NULL;
3427 }
3428
127ea380 3429 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3430
3431 netif_carrier_off(netdev);
3432
3433 priv = netdev_priv(netdev);
3434
7bb29755
MF		 3435 priv->wq = create_singlethread_workqueue("mlx5e");
3436 if (!priv->wq)
3437 goto err_free_netdev;
3438
bc77b240
TT		 3439 err = mlx5e_create_umr_mkey(priv);
3440 if (err) {
3441 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
b50d292b 3442 goto err_destroy_wq;
bc77b240
TT		 3443 }
3444
6bfd390b
HHZ		 3445 err = profile->init_tx(priv);
3446 if (err)
bc77b240 3447 goto err_destroy_umr_mkey;
5c50368f
AS		 3448
3449 err = mlx5e_open_drop_rq(priv);
3450 if (err) {
3451 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3452 goto err_cleanup_tx;
5c50368f
AS		 3453 }
3454
6bfd390b
HHZ		 3455 err = profile->init_rx(priv);
3456 if (err)
5c50368f 3457 goto err_close_drop_rq;
5c50368f 3458
593cf338
RS		 3459 mlx5e_create_q_counter(priv);
3460
33cfaaa8 3461 mlx5e_init_l2_addr(priv);
5c50368f 3462
f62b8bb8
AV		 3463 err = register_netdev(netdev);
3464 if (err) {
1f2a3003 3465 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
6bfd390b 3466 goto err_dealloc_q_counters;
01a14098 3467 }
b3f63c3d 3468
6bfd390b
HHZ		 3469 if (profile->enable)
3470 profile->enable(priv);
f62b8bb8
AV		 3471
3472 return priv;
3473
593cf338
RS		 3474err_dealloc_q_counters:
3475 mlx5e_destroy_q_counter(priv);
6bfd390b 3476 profile->cleanup_rx(priv);
5c50368f
AS		 3477
3478err_close_drop_rq:
3479 mlx5e_close_drop_rq(priv);
3480
6bfd390b
HHZ		 3481err_cleanup_tx:
3482 profile->cleanup_tx(priv);
5c50368f 3483
bc77b240
TT		 3484err_destroy_umr_mkey:
3485 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3486
7bb29755
MF		 3487err_destroy_wq:
3488 destroy_workqueue(priv->wq);
3489
f62b8bb8
AV		 3490err_free_netdev:
3491 free_netdev(netdev);
3492
3493 return NULL;
3494}
3495
127ea380
HHZ		 3496static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3497{
3498 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3499 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3500 int vport;
3501
3502 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3503 return;
3504
3505 for (vport = 1; vport < total_vfs; vport++) {
3506 struct mlx5_eswitch_rep rep;
3507
cb67b832
HHZ		 3508 rep.load = mlx5e_vport_rep_load;
3509 rep.unload = mlx5e_vport_rep_unload;
127ea380
HHZ		 3510 rep.vport = vport;
3511 mlx5_eswitch_register_vport_rep(esw, &rep);
3512 }
3513}
3514
b50d292b
HHZ		 3515static void *mlx5e_add(struct mlx5_core_dev *mdev)
3516{
127ea380
HHZ		 3517 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3518 void *ppriv = NULL;
b50d292b
HHZ		 3519 void *ret;
3520
3521 if (mlx5e_check_required_hca_cap(mdev))
3522 return NULL;
3523
3524 if (mlx5e_create_mdev_resources(mdev))
3525 return NULL;
3526
127ea380
HHZ		 3527 mlx5e_register_vport_rep(mdev);
3528
3529 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3530 ppriv = &esw->offloads.vport_reps[0];
3531
3532 ret = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
b50d292b
HHZ		 3533 if (!ret) {
3534 mlx5e_destroy_mdev_resources(mdev);
3535 return NULL;
3536 }
3537 return ret;
3538}
3539
cb67b832 3540void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 3541{
6bfd390b 3542 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 3543 struct net_device *netdev = priv->netdev;
3544
9b37b07f 3545 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
6bfd390b
HHZ		 3546 if (profile->disable)
3547 profile->disable(priv);
9b37b07f 3548
7bb29755 3549 flush_workqueue(priv->wq);
5fc7197d
MD		 3550 if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3551 netif_device_detach(netdev);
811afeaa 3552 mlx5e_close(netdev);
5fc7197d
MD		 3553 } else {
3554 unregister_netdev(netdev);
3555 }
3556
593cf338 3557 mlx5e_destroy_q_counter(priv);
6bfd390b 3558 profile->cleanup_rx(priv);
5c50368f 3559 mlx5e_close_drop_rq(priv);
6bfd390b 3560 profile->cleanup_tx(priv);
bc77b240 3561 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
7bb29755
MF		 3562 cancel_delayed_work_sync(&priv->update_stats_work);
3563 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 3564 if (profile->cleanup)
3565 profile->cleanup(priv);
5fc7197d
MD		 3566
3567 if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3568 free_netdev(netdev);
f62b8bb8
AV		 3569}
3570
b50d292b
HHZ		 3571static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3572{
127ea380
HHZ		 3573 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3574 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 3575 struct mlx5e_priv *priv = vpriv;
127ea380 3576 int vport;
b50d292b
HHZ		 3577
3578 mlx5e_destroy_netdev(mdev, priv);
127ea380
HHZ		 3579
3580 for (vport = 1; vport < total_vfs; vport++)
3581 mlx5_eswitch_unregister_vport_rep(esw, vport);
3582
b50d292b
HHZ		 3583 mlx5e_destroy_mdev_resources(mdev);
3584}
3585
f62b8bb8
AV		 3586static void *mlx5e_get_netdev(void *vpriv)
3587{
3588 struct mlx5e_priv *priv = vpriv;
3589
3590 return priv->netdev;
3591}
3592
3593static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 3594 .add = mlx5e_add,
3595 .remove = mlx5e_remove,
f62b8bb8
AV		 3596 .event = mlx5e_async_event,
3597 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3598 .get_dev = mlx5e_get_netdev,
3599};
3600
3601void mlx5e_init(void)
3602{
665bc539 3603 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 3604 mlx5_register_interface(&mlx5e_interface);
3605}
3606
3607void mlx5e_cleanup(void)
3608{
3609 mlx5_unregister_interface(&mlx5e_interface);
3610}
Linux 6.x block layer and io_uring tree(s)