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[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/flow_table.h>
34#include "en.h"
35
36struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
39};
40
41struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
58d52291 44 u16 max_inline;
f62b8bb8
AV		 45};
46
47struct mlx5e_cq_param {
48 u32 cqc[MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
50 u16 eq_ix;
51};
52
53struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
58};
59
60static void mlx5e_update_carrier(struct mlx5e_priv *priv)
61{
62 struct mlx5_core_dev *mdev = priv->mdev;
63 u8 port_state;
64
65 port_state = mlx5_query_vport_state(mdev,
66 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
67
68 if (port_state == VPORT_STATE_UP)
69 netif_carrier_on(priv->netdev);
70 else
71 netif_carrier_off(priv->netdev);
72}
73
74static void mlx5e_update_carrier_work(struct work_struct *work)
75{
76 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
77 update_carrier_work);
78
79 mutex_lock(&priv->state_lock);
80 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
81 mlx5e_update_carrier(priv);
82 mutex_unlock(&priv->state_lock);
83}
84
efea389d
GP		 85static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
86{
87 struct mlx5_core_dev *mdev = priv->mdev;
88 struct mlx5e_pport_stats *s = &priv->stats.pport;
89 u32 *in;
90 u32 *out;
91 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
92
93 in = mlx5_vzalloc(sz);
94 out = mlx5_vzalloc(sz);
95 if (!in || !out)
96 goto free_out;
97
98 MLX5_SET(ppcnt_reg, in, local_port, 1);
99
100 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
101 mlx5_core_access_reg(mdev, in, sz, out,
102 sz, MLX5_REG_PPCNT, 0, 0);
103 memcpy(s->IEEE_802_3_counters,
104 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
105 sizeof(s->IEEE_802_3_counters));
106
107 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
108 mlx5_core_access_reg(mdev, in, sz, out,
109 sz, MLX5_REG_PPCNT, 0, 0);
110 memcpy(s->RFC_2863_counters,
111 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
112 sizeof(s->RFC_2863_counters));
113
114 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
115 mlx5_core_access_reg(mdev, in, sz, out,
116 sz, MLX5_REG_PPCNT, 0, 0);
117 memcpy(s->RFC_2819_counters,
118 MLX5_ADDR_OF(ppcnt_reg, out, counter_set),
119 sizeof(s->RFC_2819_counters));
120
121free_out:
122 kvfree(in);
123 kvfree(out);
124}
125
f62b8bb8
AV		 126void mlx5e_update_stats(struct mlx5e_priv *priv)
127{
128 struct mlx5_core_dev *mdev = priv->mdev;
129 struct mlx5e_vport_stats *s = &priv->stats.vport;
130 struct mlx5e_rq_stats *rq_stats;
131 struct mlx5e_sq_stats *sq_stats;
132 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
133 u32 *out;
134 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
135 u64 tx_offload_none;
136 int i, j;
137
138 out = mlx5_vzalloc(outlen);
139 if (!out)
140 return;
141
142 /* Collect firts the SW counters and then HW for consistency */
143 s->tso_packets = 0;
144 s->tso_bytes = 0;
145 s->tx_queue_stopped = 0;
146 s->tx_queue_wake = 0;
147 s->tx_queue_dropped = 0;
148 tx_offload_none = 0;
149 s->lro_packets = 0;
150 s->lro_bytes = 0;
151 s->rx_csum_none = 0;
152 s->rx_wqe_err = 0;
153 for (i = 0; i < priv->params.num_channels; i++) {
154 rq_stats = &priv->channel[i]->rq.stats;
155
156 s->lro_packets += rq_stats->lro_packets;
157 s->lro_bytes += rq_stats->lro_bytes;
158 s->rx_csum_none += rq_stats->csum_none;
159 s->rx_wqe_err += rq_stats->wqe_err;
160
a4418a6c 161 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 162 sq_stats = &priv->channel[i]->sq[j].stats;
163
164 s->tso_packets += sq_stats->tso_packets;
165 s->tso_bytes += sq_stats->tso_bytes;
166 s->tx_queue_stopped += sq_stats->stopped;
167 s->tx_queue_wake += sq_stats->wake;
168 s->tx_queue_dropped += sq_stats->dropped;
169 tx_offload_none += sq_stats->csum_offload_none;
170 }
171 }
172
173 /* HW counters */
174 memset(in, 0, sizeof(in));
175
176 MLX5_SET(query_vport_counter_in, in, opcode,
177 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
178 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
179 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
180
181 memset(out, 0, outlen);
182
183 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
184 goto free_out;
185
186#define MLX5_GET_CTR(p, x) \
187 MLX5_GET64(query_vport_counter_out, p, x)
188
189 s->rx_error_packets =
190 MLX5_GET_CTR(out, received_errors.packets);
191 s->rx_error_bytes =
192 MLX5_GET_CTR(out, received_errors.octets);
193 s->tx_error_packets =
194 MLX5_GET_CTR(out, transmit_errors.packets);
195 s->tx_error_bytes =
196 MLX5_GET_CTR(out, transmit_errors.octets);
197
198 s->rx_unicast_packets =
199 MLX5_GET_CTR(out, received_eth_unicast.packets);
200 s->rx_unicast_bytes =
201 MLX5_GET_CTR(out, received_eth_unicast.octets);
202 s->tx_unicast_packets =
203 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
204 s->tx_unicast_bytes =
205 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
206
207 s->rx_multicast_packets =
208 MLX5_GET_CTR(out, received_eth_multicast.packets);
209 s->rx_multicast_bytes =
210 MLX5_GET_CTR(out, received_eth_multicast.octets);
211 s->tx_multicast_packets =
212 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
213 s->tx_multicast_bytes =
214 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
215
216 s->rx_broadcast_packets =
217 MLX5_GET_CTR(out, received_eth_broadcast.packets);
218 s->rx_broadcast_bytes =
219 MLX5_GET_CTR(out, received_eth_broadcast.octets);
220 s->tx_broadcast_packets =
221 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
222 s->tx_broadcast_bytes =
223 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
224
225 s->rx_packets =
226 s->rx_unicast_packets +
227 s->rx_multicast_packets +
228 s->rx_broadcast_packets;
229 s->rx_bytes =
230 s->rx_unicast_bytes +
231 s->rx_multicast_bytes +
232 s->rx_broadcast_bytes;
233 s->tx_packets =
234 s->tx_unicast_packets +
235 s->tx_multicast_packets +
236 s->tx_broadcast_packets;
237 s->tx_bytes =
238 s->tx_unicast_bytes +
239 s->tx_multicast_bytes +
240 s->tx_broadcast_bytes;
241
242 /* Update calculated offload counters */
243 s->tx_csum_offload = s->tx_packets - tx_offload_none;
244 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
245
efea389d 246 mlx5e_update_pport_counters(priv);
f62b8bb8
AV		 247free_out:
248 kvfree(out);
249}
250
251static void mlx5e_update_stats_work(struct work_struct *work)
252{
253 struct delayed_work *dwork = to_delayed_work(work);
254 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
255 update_stats_work);
256 mutex_lock(&priv->state_lock);
257 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
258 mlx5e_update_stats(priv);
259 schedule_delayed_work(dwork,
260 msecs_to_jiffies(
261 MLX5E_UPDATE_STATS_INTERVAL));
262 }
263 mutex_unlock(&priv->state_lock);
264}
265
266static void __mlx5e_async_event(struct mlx5e_priv *priv,
267 enum mlx5_dev_event event)
268{
269 switch (event) {
270 case MLX5_DEV_EVENT_PORT_UP:
271 case MLX5_DEV_EVENT_PORT_DOWN:
272 schedule_work(&priv->update_carrier_work);
273 break;
274
275 default:
276 break;
277 }
278}
279
280static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
281 enum mlx5_dev_event event, unsigned long param)
282{
283 struct mlx5e_priv *priv = vpriv;
284
285 spin_lock(&priv->async_events_spinlock);
286 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
287 __mlx5e_async_event(priv, event);
288 spin_unlock(&priv->async_events_spinlock);
289}
290
291static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
292{
293 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
294}
295
296static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
297{
298 spin_lock_irq(&priv->async_events_spinlock);
299 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
300 spin_unlock_irq(&priv->async_events_spinlock);
301}
302
facc9699
SM		 303#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
304#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
305
f62b8bb8
AV		 306static int mlx5e_create_rq(struct mlx5e_channel *c,
307 struct mlx5e_rq_param *param,
308 struct mlx5e_rq *rq)
309{
310 struct mlx5e_priv *priv = c->priv;
311 struct mlx5_core_dev *mdev = priv->mdev;
312 void *rqc = param->rqc;
313 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
314 int wq_sz;
315 int err;
316 int i;
317
311c7c71
SM		 318 param->wq.db_numa_node = cpu_to_node(c->cpu);
319
f62b8bb8
AV		 320 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
321 &rq->wq_ctrl);
322 if (err)
323 return err;
324
325 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
326
327 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
328 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
329 cpu_to_node(c->cpu));
330 if (!rq->skb) {
331 err = -ENOMEM;
332 goto err_rq_wq_destroy;
333 }
334
335 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 336 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 337 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 338
339 for (i = 0; i < wq_sz; i++) {
340 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 341 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 342
343 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 344 wqe->data.byte_count =
345 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 346 }
347
348 rq->pdev = c->pdev;
349 rq->netdev = c->netdev;
350 rq->channel = c;
351 rq->ix = c->ix;
50cfa25a 352 rq->priv = c->priv;
f62b8bb8
AV		 353
354 return 0;
355
356err_rq_wq_destroy:
357 mlx5_wq_destroy(&rq->wq_ctrl);
358
359 return err;
360}
361
362static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
363{
364 kfree(rq->skb);
365 mlx5_wq_destroy(&rq->wq_ctrl);
366}
367
368static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
369{
50cfa25a 370 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 371 struct mlx5_core_dev *mdev = priv->mdev;
372
373 void *in;
374 void *rqc;
375 void *wq;
376 int inlen;
377 int err;
378
379 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
380 sizeof(u64) * rq->wq_ctrl.buf.npages;
381 in = mlx5_vzalloc(inlen);
382 if (!in)
383 return -ENOMEM;
384
385 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
386 wq = MLX5_ADDR_OF(rqc, rqc, wq);
387
388 memcpy(rqc, param->rqc, sizeof(param->rqc));
389
97de9f31 390 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8
AV		 391 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
392 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8 393 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 394 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 395 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
396
397 mlx5_fill_page_array(&rq->wq_ctrl.buf,
398 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
399
7db22ffb 400 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 401
402 kvfree(in);
403
404 return err;
405}
406
407static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
408{
409 struct mlx5e_channel *c = rq->channel;
410 struct mlx5e_priv *priv = c->priv;
411 struct mlx5_core_dev *mdev = priv->mdev;
412
413 void *in;
414 void *rqc;
415 int inlen;
416 int err;
417
418 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
419 in = mlx5_vzalloc(inlen);
420 if (!in)
421 return -ENOMEM;
422
423 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
424
425 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
426 MLX5_SET(rqc, rqc, state, next_state);
427
7db22ffb 428 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 429
430 kvfree(in);
431
432 return err;
433}
434
435static void mlx5e_disable_rq(struct mlx5e_rq *rq)
436{
50cfa25a 437 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 438}
439
440static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
441{
442 struct mlx5e_channel *c = rq->channel;
443 struct mlx5e_priv *priv = c->priv;
444 struct mlx5_wq_ll *wq = &rq->wq;
445 int i;
446
447 for (i = 0; i < 1000; i++) {
448 if (wq->cur_sz >= priv->params.min_rx_wqes)
449 return 0;
450
451 msleep(20);
452 }
453
454 return -ETIMEDOUT;
455}
456
457static int mlx5e_open_rq(struct mlx5e_channel *c,
458 struct mlx5e_rq_param *param,
459 struct mlx5e_rq *rq)
460{
461 int err;
462
463 err = mlx5e_create_rq(c, param, rq);
464 if (err)
465 return err;
466
467 err = mlx5e_enable_rq(rq, param);
468 if (err)
469 goto err_destroy_rq;
470
471 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
472 if (err)
473 goto err_disable_rq;
474
475 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 476 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 477
478 return 0;
479
480err_disable_rq:
481 mlx5e_disable_rq(rq);
482err_destroy_rq:
483 mlx5e_destroy_rq(rq);
484
485 return err;
486}
487
488static void mlx5e_close_rq(struct mlx5e_rq *rq)
489{
490 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
491 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
492
493 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
494 while (!mlx5_wq_ll_is_empty(&rq->wq))
495 msleep(20);
496
497 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
498 napi_synchronize(&rq->channel->napi);
499
500 mlx5e_disable_rq(rq);
501 mlx5e_destroy_rq(rq);
502}
503
504static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
505{
506 kfree(sq->dma_fifo);
507 kfree(sq->skb);
508}
509
510static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
511{
512 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
513 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
514
515 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
516 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
517 numa);
518
519 if (!sq->skb || !sq->dma_fifo) {
520 mlx5e_free_sq_db(sq);
521 return -ENOMEM;
522 }
523
524 sq->dma_fifo_mask = df_sz - 1;
525
526 return 0;
527}
528
529static int mlx5e_create_sq(struct mlx5e_channel *c,
530 int tc,
531 struct mlx5e_sq_param *param,
532 struct mlx5e_sq *sq)
533{
534 struct mlx5e_priv *priv = c->priv;
535 struct mlx5_core_dev *mdev = priv->mdev;
536
537 void *sqc = param->sqc;
538 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 539 int txq_ix;
f62b8bb8
AV		 540 int err;
541
542 err = mlx5_alloc_map_uar(mdev, &sq->uar);
543 if (err)
544 return err;
545
311c7c71
SM		 546 param->wq.db_numa_node = cpu_to_node(c->cpu);
547
f62b8bb8
AV		 548 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
549 &sq->wq_ctrl);
550 if (err)
551 goto err_unmap_free_uar;
552
553 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
554 sq->uar_map = sq->uar.map;
88a85f99 555 sq->uar_bf_map = sq->uar.bf_map;
f62b8bb8 556 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 557 sq->max_inline = param->max_inline;
f62b8bb8 558
7ec0bb22
DC		 559 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
560 if (err)
f62b8bb8
AV		 561 goto err_sq_wq_destroy;
562
03289b88
SM		 563 txq_ix = c->ix + tc * priv->params.num_channels;
564 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8 565
88a85f99
AS		 566 sq->pdev = c->pdev;
567 sq->mkey_be = c->mkey_be;
568 sq->channel = c;
569 sq->tc = tc;
570 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
571 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
03289b88 572 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 573
574 return 0;
575
576err_sq_wq_destroy:
577 mlx5_wq_destroy(&sq->wq_ctrl);
578
579err_unmap_free_uar:
580 mlx5_unmap_free_uar(mdev, &sq->uar);
581
582 return err;
583}
584
585static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
586{
587 struct mlx5e_channel *c = sq->channel;
588 struct mlx5e_priv *priv = c->priv;
589
590 mlx5e_free_sq_db(sq);
591 mlx5_wq_destroy(&sq->wq_ctrl);
592 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
593}
594
595static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
596{
597 struct mlx5e_channel *c = sq->channel;
598 struct mlx5e_priv *priv = c->priv;
599 struct mlx5_core_dev *mdev = priv->mdev;
600
601 void *in;
602 void *sqc;
603 void *wq;
604 int inlen;
605 int err;
606
607 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
608 sizeof(u64) * sq->wq_ctrl.buf.npages;
609 in = mlx5_vzalloc(inlen);
610 if (!in)
611 return -ENOMEM;
612
613 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
614 wq = MLX5_ADDR_OF(sqc, sqc, wq);
615
616 memcpy(sqc, param->sqc, sizeof(param->sqc));
617
f62b8bb8
AV		 618 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
619 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
620 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
621 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
622 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
623
624 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
625 MLX5_SET(wq, wq, uar_page, sq->uar.index);
626 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 627 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 628 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
629
630 mlx5_fill_page_array(&sq->wq_ctrl.buf,
631 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
632
7db22ffb 633 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 634
635 kvfree(in);
636
637 return err;
638}
639
640static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
641{
642 struct mlx5e_channel *c = sq->channel;
643 struct mlx5e_priv *priv = c->priv;
644 struct mlx5_core_dev *mdev = priv->mdev;
645
646 void *in;
647 void *sqc;
648 int inlen;
649 int err;
650
651 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
652 in = mlx5_vzalloc(inlen);
653 if (!in)
654 return -ENOMEM;
655
656 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
657
658 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
659 MLX5_SET(sqc, sqc, state, next_state);
660
7db22ffb 661 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 662
663 kvfree(in);
664
665 return err;
666}
667
668static void mlx5e_disable_sq(struct mlx5e_sq *sq)
669{
670 struct mlx5e_channel *c = sq->channel;
671 struct mlx5e_priv *priv = c->priv;
672 struct mlx5_core_dev *mdev = priv->mdev;
673
7db22ffb 674 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 675}
676
677static int mlx5e_open_sq(struct mlx5e_channel *c,
678 int tc,
679 struct mlx5e_sq_param *param,
680 struct mlx5e_sq *sq)
681{
682 int err;
683
684 err = mlx5e_create_sq(c, tc, param, sq);
685 if (err)
686 return err;
687
688 err = mlx5e_enable_sq(sq, param);
689 if (err)
690 goto err_destroy_sq;
691
692 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
693 if (err)
694 goto err_disable_sq;
695
696 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
697 netdev_tx_reset_queue(sq->txq);
698 netif_tx_start_queue(sq->txq);
699
700 return 0;
701
702err_disable_sq:
703 mlx5e_disable_sq(sq);
704err_destroy_sq:
705 mlx5e_destroy_sq(sq);
706
707 return err;
708}
709
710static inline void netif_tx_disable_queue(struct netdev_queue *txq)
711{
712 __netif_tx_lock_bh(txq);
713 netif_tx_stop_queue(txq);
714 __netif_tx_unlock_bh(txq);
715}
716
717static void mlx5e_close_sq(struct mlx5e_sq *sq)
718{
719 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
720 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
721 netif_tx_disable_queue(sq->txq);
722
723 /* ensure hw is notified of all pending wqes */
724 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 725 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 726
727 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
728 while (sq->cc != sq->pc) /* wait till sq is empty */
729 msleep(20);
730
731 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
732 napi_synchronize(&sq->channel->napi);
733
734 mlx5e_disable_sq(sq);
735 mlx5e_destroy_sq(sq);
736}
737
738static int mlx5e_create_cq(struct mlx5e_channel *c,
739 struct mlx5e_cq_param *param,
740 struct mlx5e_cq *cq)
741{
742 struct mlx5e_priv *priv = c->priv;
743 struct mlx5_core_dev *mdev = priv->mdev;
744 struct mlx5_core_cq *mcq = &cq->mcq;
745 int eqn_not_used;
746 int irqn;
747 int err;
748 u32 i;
749
311c7c71
SM		 750 param->wq.buf_numa_node = cpu_to_node(c->cpu);
751 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 752 param->eq_ix = c->ix;
753
754 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
755 &cq->wq_ctrl);
756 if (err)
757 return err;
758
759 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
760
761 cq->napi = &c->napi;
762
763 mcq->cqe_sz = 64;
764 mcq->set_ci_db = cq->wq_ctrl.db.db;
765 mcq->arm_db = cq->wq_ctrl.db.db + 1;
766 *mcq->set_ci_db = 0;
767 *mcq->arm_db = 0;
768 mcq->vector = param->eq_ix;
769 mcq->comp = mlx5e_completion_event;
770 mcq->event = mlx5e_cq_error_event;
771 mcq->irqn = irqn;
772 mcq->uar = &priv->cq_uar;
773
774 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
775 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
776
777 cqe->op_own = 0xf1;
778 }
779
780 cq->channel = c;
50cfa25a 781 cq->priv = priv;
f62b8bb8
AV		 782
783 return 0;
784}
785
786static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
787{
788 mlx5_wq_destroy(&cq->wq_ctrl);
789}
790
791static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
792{
50cfa25a 793 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 794 struct mlx5_core_dev *mdev = priv->mdev;
795 struct mlx5_core_cq *mcq = &cq->mcq;
796
797 void *in;
798 void *cqc;
799 int inlen;
800 int irqn_not_used;
801 int eqn;
802 int err;
803
804 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
805 sizeof(u64) * cq->wq_ctrl.buf.npages;
806 in = mlx5_vzalloc(inlen);
807 if (!in)
808 return -ENOMEM;
809
810 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
811
812 memcpy(cqc, param->cqc, sizeof(param->cqc));
813
814 mlx5_fill_page_array(&cq->wq_ctrl.buf,
815 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
816
817 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
818
819 MLX5_SET(cqc, cqc, c_eqn, eqn);
820 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
821 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
68cdf5d6 822 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 823 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
824
825 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
826
827 kvfree(in);
828
829 if (err)
830 return err;
831
832 mlx5e_cq_arm(cq);
833
834 return 0;
835}
836
837static void mlx5e_disable_cq(struct mlx5e_cq *cq)
838{
50cfa25a 839 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 840 struct mlx5_core_dev *mdev = priv->mdev;
841
842 mlx5_core_destroy_cq(mdev, &cq->mcq);
843}
844
845static int mlx5e_open_cq(struct mlx5e_channel *c,
846 struct mlx5e_cq_param *param,
847 struct mlx5e_cq *cq,
848 u16 moderation_usecs,
849 u16 moderation_frames)
850{
851 int err;
852 struct mlx5e_priv *priv = c->priv;
853 struct mlx5_core_dev *mdev = priv->mdev;
854
855 err = mlx5e_create_cq(c, param, cq);
856 if (err)
857 return err;
858
859 err = mlx5e_enable_cq(cq, param);
860 if (err)
861 goto err_destroy_cq;
862
863 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
864 moderation_usecs,
865 moderation_frames);
866 if (err)
867 goto err_destroy_cq;
868
869 return 0;
870
871err_destroy_cq:
872 mlx5e_destroy_cq(cq);
873
874 return err;
875}
876
877static void mlx5e_close_cq(struct mlx5e_cq *cq)
878{
879 mlx5e_disable_cq(cq);
880 mlx5e_destroy_cq(cq);
881}
882
883static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
884{
885 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
886}
887
888static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
889 struct mlx5e_channel_param *cparam)
890{
891 struct mlx5e_priv *priv = c->priv;
892 int err;
893 int tc;
894
895 for (tc = 0; tc < c->num_tc; tc++) {
896 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
897 priv->params.tx_cq_moderation_usec,
898 priv->params.tx_cq_moderation_pkts);
899 if (err)
900 goto err_close_tx_cqs;
f62b8bb8
AV		 901 }
902
903 return 0;
904
905err_close_tx_cqs:
906 for (tc--; tc >= 0; tc--)
907 mlx5e_close_cq(&c->sq[tc].cq);
908
909 return err;
910}
911
912static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
913{
914 int tc;
915
916 for (tc = 0; tc < c->num_tc; tc++)
917 mlx5e_close_cq(&c->sq[tc].cq);
918}
919
920static int mlx5e_open_sqs(struct mlx5e_channel *c,
921 struct mlx5e_channel_param *cparam)
922{
923 int err;
924 int tc;
925
926 for (tc = 0; tc < c->num_tc; tc++) {
927 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
928 if (err)
929 goto err_close_sqs;
930 }
931
932 return 0;
933
934err_close_sqs:
935 for (tc--; tc >= 0; tc--)
936 mlx5e_close_sq(&c->sq[tc]);
937
938 return err;
939}
940
941static void mlx5e_close_sqs(struct mlx5e_channel *c)
942{
943 int tc;
944
945 for (tc = 0; tc < c->num_tc; tc++)
946 mlx5e_close_sq(&c->sq[tc]);
947}
948
03289b88
SM		 949static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
950 int num_channels)
951{
952 int i;
953
954 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
955 c->tc_to_txq_map[i] = c->ix + i * num_channels;
956}
957
f62b8bb8
AV		 958static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
959 struct mlx5e_channel_param *cparam,
960 struct mlx5e_channel **cp)
961{
962 struct net_device *netdev = priv->netdev;
963 int cpu = mlx5e_get_cpu(priv, ix);
964 struct mlx5e_channel *c;
965 int err;
966
967 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
968 if (!c)
969 return -ENOMEM;
970
971 c->priv = priv;
972 c->ix = ix;
973 c->cpu = cpu;
974 c->pdev = &priv->mdev->pdev->dev;
975 c->netdev = priv->netdev;
976 c->mkey_be = cpu_to_be32(priv->mr.key);
a4418a6c 977 c->num_tc = priv->params.num_tc;
f62b8bb8 978
03289b88
SM		 979 mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
980
f62b8bb8
AV		 981 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
982
983 err = mlx5e_open_tx_cqs(c, cparam);
984 if (err)
985 goto err_napi_del;
986
987 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
988 priv->params.rx_cq_moderation_usec,
989 priv->params.rx_cq_moderation_pkts);
990 if (err)
991 goto err_close_tx_cqs;
f62b8bb8
AV		 992
993 napi_enable(&c->napi);
994
995 err = mlx5e_open_sqs(c, cparam);
996 if (err)
997 goto err_disable_napi;
998
999 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1000 if (err)
1001 goto err_close_sqs;
1002
1003 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1004 *cp = c;
1005
1006 return 0;
1007
1008err_close_sqs:
1009 mlx5e_close_sqs(c);
1010
1011err_disable_napi:
1012 napi_disable(&c->napi);
1013 mlx5e_close_cq(&c->rq.cq);
1014
1015err_close_tx_cqs:
1016 mlx5e_close_tx_cqs(c);
1017
1018err_napi_del:
1019 netif_napi_del(&c->napi);
1020 kfree(c);
1021
1022 return err;
1023}
1024
1025static void mlx5e_close_channel(struct mlx5e_channel *c)
1026{
1027 mlx5e_close_rq(&c->rq);
1028 mlx5e_close_sqs(c);
1029 napi_disable(&c->napi);
1030 mlx5e_close_cq(&c->rq.cq);
1031 mlx5e_close_tx_cqs(c);
1032 netif_napi_del(&c->napi);
1033 kfree(c);
1034}
1035
1036static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1037 struct mlx5e_rq_param *param)
1038{
1039 void *rqc = param->rqc;
1040 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1041
1042 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1043 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1044 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1045 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1046 MLX5_SET(wq, wq, pd, priv->pdn);
1047
311c7c71 1048 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1049 param->wq.linear = 1;
1050}
1051
1052static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1053 struct mlx5e_sq_param *param)
1054{
1055 void *sqc = param->sqc;
1056 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1057
1058 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1059 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1060 MLX5_SET(wq, wq, pd, priv->pdn);
1061
311c7c71 1062 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
58d52291 1063 param->max_inline = priv->params.tx_max_inline;
f62b8bb8
AV		 1064}
1065
1066static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1067 struct mlx5e_cq_param *param)
1068{
1069 void *cqc = param->cqc;
1070
1071 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1072}
1073
1074static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1075 struct mlx5e_cq_param *param)
1076{
1077 void *cqc = param->cqc;
1078
1079 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1080
1081 mlx5e_build_common_cq_param(priv, param);
1082}
1083
1084static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1085 struct mlx5e_cq_param *param)
1086{
1087 void *cqc = param->cqc;
1088
1089 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1090
1091 mlx5e_build_common_cq_param(priv, param);
1092}
1093
1094static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1095 struct mlx5e_channel_param *cparam)
1096{
1097 memset(cparam, 0, sizeof(*cparam));
1098
1099 mlx5e_build_rq_param(priv, &cparam->rq);
1100 mlx5e_build_sq_param(priv, &cparam->sq);
1101 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1102 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1103}
1104
1105static int mlx5e_open_channels(struct mlx5e_priv *priv)
1106{
1107 struct mlx5e_channel_param cparam;
a4418a6c 1108 int nch = priv->params.num_channels;
03289b88 1109 int err = -ENOMEM;
f62b8bb8
AV		 1110 int i;
1111 int j;
1112
a4418a6c
AS		 1113 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1114 GFP_KERNEL);
03289b88 1115
a4418a6c 1116 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1117 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1118
1119 if (!priv->channel || !priv->txq_to_sq_map)
1120 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1121
1122 mlx5e_build_channel_param(priv, &cparam);
a4418a6c 1123 for (i = 0; i < nch; i++) {
f62b8bb8
AV		 1124 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1125 if (err)
1126 goto err_close_channels;
1127 }
1128
a4418a6c 1129 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1130 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1131 if (err)
1132 goto err_close_channels;
1133 }
1134
1135 return 0;
1136
1137err_close_channels:
1138 for (i--; i >= 0; i--)
1139 mlx5e_close_channel(priv->channel[i]);
1140
03289b88
SM		 1141err_free_txq_to_sq_map:
1142 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1143 kfree(priv->channel);
1144
1145 return err;
1146}
1147
1148static void mlx5e_close_channels(struct mlx5e_priv *priv)
1149{
1150 int i;
1151
1152 for (i = 0; i < priv->params.num_channels; i++)
1153 mlx5e_close_channel(priv->channel[i]);
1154
03289b88 1155 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1156 kfree(priv->channel);
1157}
1158
2be6967c
SM		 1159static int mlx5e_rx_hash_fn(int hfunc)
1160{
1161 return (hfunc == ETH_RSS_HASH_TOP) ?
1162 MLX5_RX_HASH_FN_TOEPLITZ :
1163 MLX5_RX_HASH_FN_INVERTED_XOR8;
1164}
1165
1166static int mlx5e_bits_invert(unsigned long a, int size)
1167{
1168 int inv = 0;
1169 int i;
1170
1171 for (i = 0; i < size; i++)
1172 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1173
1174 return inv;
1175}
1176
4cbeaff5
AS		 1177static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc,
1178 enum mlx5e_rqt_ix rqt_ix)
1179{
1180 int i;
1181 int log_sz;
1182
1183 switch (rqt_ix) {
1184 case MLX5E_INDIRECTION_RQT:
1185 log_sz = priv->params.rx_hash_log_tbl_sz;
1186 for (i = 0; i < (1 << log_sz); i++) {
1187 int ix = i;
1188
1189 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1190 ix = mlx5e_bits_invert(i, log_sz);
1191
1192 ix = ix % priv->params.num_channels;
1193 MLX5_SET(rqtc, rqtc, rq_num[i],
5c50368f
AS		 1194 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1195 priv->channel[ix]->rq.rqn :
1196 priv->drop_rq.rqn);
4cbeaff5
AS		 1197 }
1198
1199 break;
1200
1201 default: /* MLX5E_SINGLE_RQ_RQT */
1202 MLX5_SET(rqtc, rqtc, rq_num[0],
5c50368f
AS		 1203 test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1204 priv->channel[0]->rq.rqn :
1205 priv->drop_rq.rqn);
4cbeaff5
AS		 1206
1207 break;
1208 }
1209}
1210
40ab6a6e 1211static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8
AV		 1212{
1213 struct mlx5_core_dev *mdev = priv->mdev;
1214 u32 *in;
f62b8bb8
AV		 1215 void *rqtc;
1216 int inlen;
4cbeaff5
AS		 1217 int log_sz;
1218 int sz;
f62b8bb8 1219 int err;
4cbeaff5
AS		 1220
1221 log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1222 priv->params.rx_hash_log_tbl_sz;
1223 sz = 1 << log_sz;
f62b8bb8 1224
f62b8bb8
AV		 1225 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1226 in = mlx5_vzalloc(inlen);
1227 if (!in)
1228 return -ENOMEM;
1229
1230 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1231
1232 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1233 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1234
4cbeaff5 1235 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
2be6967c 1236
4cbeaff5 1237 err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1238
1239 kvfree(in);
1240
1241 return err;
1242}
1243
5c50368f
AS		 1244static int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
1245{
1246 struct mlx5_core_dev *mdev = priv->mdev;
1247 u32 *in;
1248 void *rqtc;
1249 int inlen;
1250 int log_sz;
1251 int sz;
1252 int err;
1253
1254 log_sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 0 :
1255 priv->params.rx_hash_log_tbl_sz;
1256 sz = 1 << log_sz;
1257
1258 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1259 in = mlx5_vzalloc(inlen);
1260 if (!in)
1261 return -ENOMEM;
1262
1263 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1264
1265 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1266
1267 mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix);
1268
1269 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1270
1271 err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen);
1272
1273 kvfree(in);
1274
1275 return err;
1276}
1277
40ab6a6e 1278static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix)
f62b8bb8 1279{
4cbeaff5 1280 mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]);
f62b8bb8
AV		 1281}
1282
40ab6a6e
AS		 1283static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1284{
1285 mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT);
1286 mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT);
1287}
1288
5c50368f
AS		 1289static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1290{
1291 if (!priv->params.lro_en)
1292 return;
1293
1294#define ROUGH_MAX_L2_L3_HDR_SZ 256
1295
1296 MLX5_SET(tirc, tirc, lro_enable_mask,
1297 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1298 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1299 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1300 (priv->params.lro_wqe_sz -
1301 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1302 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1303 MLX5_CAP_ETH(priv->mdev,
1304 lro_timer_supported_periods[3]));
1305}
1306
1307static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt)
1308{
1309 struct mlx5_core_dev *mdev = priv->mdev;
1310
1311 void *in;
1312 void *tirc;
1313 int inlen;
1314 int err;
1315
1316 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1317 in = mlx5_vzalloc(inlen);
1318 if (!in)
1319 return -ENOMEM;
1320
1321 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1322 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1323
1324 mlx5e_build_tir_ctx_lro(tirc, priv);
1325
1326 err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen);
1327
1328 kvfree(in);
1329
1330 return err;
1331}
1332
40ab6a6e
AS		 1333static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1334{
1335 struct mlx5e_priv *priv = netdev_priv(netdev);
1336 struct mlx5_core_dev *mdev = priv->mdev;
1337 int hw_mtu;
1338 int err;
1339
1340 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1341 if (err)
1342 return err;
1343
1344 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1345
1346 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1347 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1348 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1349
1350 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1351 return 0;
1352}
1353
1354int mlx5e_open_locked(struct net_device *netdev)
1355{
1356 struct mlx5e_priv *priv = netdev_priv(netdev);
1357 int num_txqs;
1358 int err;
1359
1360 set_bit(MLX5E_STATE_OPENED, &priv->state);
1361
1362 num_txqs = priv->params.num_channels * priv->params.num_tc;
1363 netif_set_real_num_tx_queues(netdev, num_txqs);
1364 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1365
1366 err = mlx5e_set_dev_port_mtu(netdev);
1367 if (err)
1368 return err;
1369
1370 err = mlx5e_open_channels(priv);
1371 if (err) {
1372 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1373 __func__, err);
1374 return err;
1375 }
1376
40ab6a6e
AS		 1377 mlx5e_update_carrier(priv);
1378 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1379
1380 schedule_delayed_work(&priv->update_stats_work, 0);
40ab6a6e 1381
9b37b07f 1382 return 0;
40ab6a6e
AS		 1383}
1384
1385static int mlx5e_open(struct net_device *netdev)
1386{
1387 struct mlx5e_priv *priv = netdev_priv(netdev);
1388 int err;
1389
1390 mutex_lock(&priv->state_lock);
1391 err = mlx5e_open_locked(netdev);
1392 mutex_unlock(&priv->state_lock);
1393
1394 return err;
1395}
1396
1397int mlx5e_close_locked(struct net_device *netdev)
1398{
1399 struct mlx5e_priv *priv = netdev_priv(netdev);
1400
1401 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1402
1403 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 1404 netif_carrier_off(priv->netdev);
1405 mlx5e_close_channels(priv);
1406
1407 return 0;
1408}
1409
1410static int mlx5e_close(struct net_device *netdev)
1411{
1412 struct mlx5e_priv *priv = netdev_priv(netdev);
1413 int err;
1414
1415 mutex_lock(&priv->state_lock);
1416 err = mlx5e_close_locked(netdev);
1417 mutex_unlock(&priv->state_lock);
1418
1419 return err;
1420}
1421
1422static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1423 struct mlx5e_rq *rq,
1424 struct mlx5e_rq_param *param)
1425{
1426 struct mlx5_core_dev *mdev = priv->mdev;
1427 void *rqc = param->rqc;
1428 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1429 int err;
1430
1431 param->wq.db_numa_node = param->wq.buf_numa_node;
1432
1433 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1434 &rq->wq_ctrl);
1435 if (err)
1436 return err;
1437
1438 rq->priv = priv;
1439
1440 return 0;
1441}
1442
1443static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1444 struct mlx5e_cq *cq,
1445 struct mlx5e_cq_param *param)
1446{
1447 struct mlx5_core_dev *mdev = priv->mdev;
1448 struct mlx5_core_cq *mcq = &cq->mcq;
1449 int eqn_not_used;
1450 int irqn;
1451 int err;
1452
1453 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1454 &cq->wq_ctrl);
1455 if (err)
1456 return err;
1457
1458 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1459
1460 mcq->cqe_sz = 64;
1461 mcq->set_ci_db = cq->wq_ctrl.db.db;
1462 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1463 *mcq->set_ci_db = 0;
1464 *mcq->arm_db = 0;
1465 mcq->vector = param->eq_ix;
1466 mcq->comp = mlx5e_completion_event;
1467 mcq->event = mlx5e_cq_error_event;
1468 mcq->irqn = irqn;
1469 mcq->uar = &priv->cq_uar;
1470
1471 cq->priv = priv;
1472
1473 return 0;
1474}
1475
1476static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1477{
1478 struct mlx5e_cq_param cq_param;
1479 struct mlx5e_rq_param rq_param;
1480 struct mlx5e_rq *rq = &priv->drop_rq;
1481 struct mlx5e_cq *cq = &priv->drop_rq.cq;
1482 int err;
1483
1484 memset(&cq_param, 0, sizeof(cq_param));
1485 memset(&rq_param, 0, sizeof(rq_param));
1486 mlx5e_build_rx_cq_param(priv, &cq_param);
1487 mlx5e_build_rq_param(priv, &rq_param);
1488
1489 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1490 if (err)
1491 return err;
1492
1493 err = mlx5e_enable_cq(cq, &cq_param);
1494 if (err)
1495 goto err_destroy_cq;
1496
1497 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1498 if (err)
1499 goto err_disable_cq;
1500
1501 err = mlx5e_enable_rq(rq, &rq_param);
1502 if (err)
1503 goto err_destroy_rq;
1504
1505 return 0;
1506
1507err_destroy_rq:
1508 mlx5e_destroy_rq(&priv->drop_rq);
1509
1510err_disable_cq:
1511 mlx5e_disable_cq(&priv->drop_rq.cq);
1512
1513err_destroy_cq:
1514 mlx5e_destroy_cq(&priv->drop_rq.cq);
1515
1516 return err;
1517}
1518
1519static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1520{
1521 mlx5e_disable_rq(&priv->drop_rq);
1522 mlx5e_destroy_rq(&priv->drop_rq);
1523 mlx5e_disable_cq(&priv->drop_rq.cq);
1524 mlx5e_destroy_cq(&priv->drop_rq.cq);
1525}
1526
1527static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1528{
1529 struct mlx5_core_dev *mdev = priv->mdev;
1530 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1531 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1532
1533 memset(in, 0, sizeof(in));
1534
1535 MLX5_SET(tisc, tisc, prio, tc);
1536 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1537
1538 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1539}
1540
1541static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1542{
1543 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1544}
1545
1546static int mlx5e_create_tises(struct mlx5e_priv *priv)
1547{
1548 int err;
1549 int tc;
1550
1551 for (tc = 0; tc < priv->params.num_tc; tc++) {
1552 err = mlx5e_create_tis(priv, tc);
1553 if (err)
1554 goto err_close_tises;
1555 }
1556
1557 return 0;
1558
1559err_close_tises:
1560 for (tc--; tc >= 0; tc--)
1561 mlx5e_destroy_tis(priv, tc);
1562
1563 return err;
1564}
1565
1566static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1567{
1568 int tc;
1569
1570 for (tc = 0; tc < priv->params.num_tc; tc++)
1571 mlx5e_destroy_tis(priv, tc);
1572}
1573
f62b8bb8
AV		 1574static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1575{
1576 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1577
3191e05f
AS		 1578 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1579
5a6f8aef
AS		 1580#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1581 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 1582
5a6f8aef
AS		 1583#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
1584 MLX5_HASH_FIELD_SEL_DST_IP |\
1585 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1586 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 1587
a741749f
AS		 1588#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1589 MLX5_HASH_FIELD_SEL_DST_IP |\
1590 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1591
5c50368f 1592 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 1593
4cbeaff5
AS		 1594 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1595
f62b8bb8
AV		 1596 switch (tt) {
1597 case MLX5E_TT_ANY:
4cbeaff5
AS		 1598 MLX5_SET(tirc, tirc, indirect_table,
1599 priv->rqtn[MLX5E_SINGLE_RQ_RQT]);
1600 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
f62b8bb8
AV		 1601 break;
1602 default:
f62b8bb8 1603 MLX5_SET(tirc, tirc, indirect_table,
4cbeaff5 1604 priv->rqtn[MLX5E_INDIRECTION_RQT]);
f62b8bb8 1605 MLX5_SET(tirc, tirc, rx_hash_fn,
2be6967c
SM		 1606 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1607 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1608 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1609 rx_hash_toeplitz_key);
1610 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1611 rx_hash_toeplitz_key);
1612
1613 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
57afead5 1614 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2be6967c 1615 }
f62b8bb8
AV		 1616 break;
1617 }
1618
1619 switch (tt) {
1620 case MLX5E_TT_IPV4_TCP:
1621 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1622 MLX5_L3_PROT_TYPE_IPV4);
1623 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1624 MLX5_L4_PROT_TYPE_TCP);
1625 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1626 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1627 break;
1628
1629 case MLX5E_TT_IPV6_TCP:
1630 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1631 MLX5_L3_PROT_TYPE_IPV6);
1632 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1633 MLX5_L4_PROT_TYPE_TCP);
1634 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1635 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1636 break;
1637
1638 case MLX5E_TT_IPV4_UDP:
1639 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1640 MLX5_L3_PROT_TYPE_IPV4);
1641 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1642 MLX5_L4_PROT_TYPE_UDP);
1643 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1644 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1645 break;
1646
1647 case MLX5E_TT_IPV6_UDP:
1648 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1649 MLX5_L3_PROT_TYPE_IPV6);
1650 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1651 MLX5_L4_PROT_TYPE_UDP);
1652 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 1653 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 1654 break;
1655
a741749f
AS		 1656 case MLX5E_TT_IPV4_IPSEC_AH:
1657 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1658 MLX5_L3_PROT_TYPE_IPV4);
1659 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1660 MLX5_HASH_IP_IPSEC_SPI);
1661 break;
1662
1663 case MLX5E_TT_IPV6_IPSEC_AH:
1664 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1665 MLX5_L3_PROT_TYPE_IPV6);
1666 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1667 MLX5_HASH_IP_IPSEC_SPI);
1668 break;
1669
1670 case MLX5E_TT_IPV4_IPSEC_ESP:
1671 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1672 MLX5_L3_PROT_TYPE_IPV4);
1673 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1674 MLX5_HASH_IP_IPSEC_SPI);
1675 break;
1676
1677 case MLX5E_TT_IPV6_IPSEC_ESP:
1678 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1679 MLX5_L3_PROT_TYPE_IPV6);
1680 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1681 MLX5_HASH_IP_IPSEC_SPI);
1682 break;
1683
f62b8bb8
AV		 1684 case MLX5E_TT_IPV4:
1685 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1686 MLX5_L3_PROT_TYPE_IPV4);
1687 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1688 MLX5_HASH_IP);
1689 break;
1690
1691 case MLX5E_TT_IPV6:
1692 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1693 MLX5_L3_PROT_TYPE_IPV6);
1694 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1695 MLX5_HASH_IP);
1696 break;
1697 }
1698}
1699
40ab6a6e 1700static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8
AV		 1701{
1702 struct mlx5_core_dev *mdev = priv->mdev;
1703 u32 *in;
1704 void *tirc;
1705 int inlen;
1706 int err;
1707
1708 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1709 in = mlx5_vzalloc(inlen);
1710 if (!in)
1711 return -ENOMEM;
1712
1713 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1714
1715 mlx5e_build_tir_ctx(priv, tirc, tt);
1716
7db22ffb 1717 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1718
1719 kvfree(in);
1720
1721 return err;
1722}
1723
40ab6a6e 1724static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt)
f62b8bb8 1725{
7db22ffb 1726 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1727}
1728
40ab6a6e 1729static int mlx5e_create_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1730{
1731 int err;
1732 int i;
1733
1734 for (i = 0; i < MLX5E_NUM_TT; i++) {
40ab6a6e 1735 err = mlx5e_create_tir(priv, i);
f62b8bb8 1736 if (err)
40ab6a6e 1737 goto err_destroy_tirs;
f62b8bb8
AV		 1738 }
1739
1740 return 0;
1741
40ab6a6e 1742err_destroy_tirs:
f62b8bb8 1743 for (i--; i >= 0; i--)
40ab6a6e 1744 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1745
1746 return err;
1747}
1748
40ab6a6e 1749static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 1750{
1751 int i;
1752
1753 for (i = 0; i < MLX5E_NUM_TT; i++)
40ab6a6e 1754 mlx5e_destroy_tir(priv, i);
f62b8bb8
AV		 1755}
1756
f62b8bb8
AV		 1757static struct rtnl_link_stats64 *
1758mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1759{
1760 struct mlx5e_priv *priv = netdev_priv(dev);
1761 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1762
1763 stats->rx_packets = vstats->rx_packets;
1764 stats->rx_bytes = vstats->rx_bytes;
1765 stats->tx_packets = vstats->tx_packets;
1766 stats->tx_bytes = vstats->tx_bytes;
1767 stats->multicast = vstats->rx_multicast_packets +
1768 vstats->tx_multicast_packets;
1769 stats->tx_errors = vstats->tx_error_packets;
1770 stats->rx_errors = vstats->rx_error_packets;
1771 stats->tx_dropped = vstats->tx_queue_dropped;
1772 stats->rx_crc_errors = 0;
1773 stats->rx_length_errors = 0;
1774
1775 return stats;
1776}
1777
1778static void mlx5e_set_rx_mode(struct net_device *dev)
1779{
1780 struct mlx5e_priv *priv = netdev_priv(dev);
1781
1782 schedule_work(&priv->set_rx_mode_work);
1783}
1784
1785static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1786{
1787 struct mlx5e_priv *priv = netdev_priv(netdev);
1788 struct sockaddr *saddr = addr;
1789
1790 if (!is_valid_ether_addr(saddr->sa_data))
1791 return -EADDRNOTAVAIL;
1792
1793 netif_addr_lock_bh(netdev);
1794 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1795 netif_addr_unlock_bh(netdev);
1796
1797 schedule_work(&priv->set_rx_mode_work);
1798
1799 return 0;
1800}
1801
1802static int mlx5e_set_features(struct net_device *netdev,
1803 netdev_features_t features)
1804{
1805 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 1806 int err = 0;
f62b8bb8 1807 netdev_features_t changes = features ^ netdev->features;
f62b8bb8
AV		 1808
1809 mutex_lock(&priv->state_lock);
f62b8bb8
AV		 1810
1811 if (changes & NETIF_F_LRO) {
98e81b0a
AS		 1812 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1813
1814 if (was_opened)
1815 mlx5e_close_locked(priv->netdev);
f62b8bb8 1816
98e81b0a 1817 priv->params.lro_en = !!(features & NETIF_F_LRO);
5c50368f
AS		 1818 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP);
1819 mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP);
98e81b0a
AS		 1820
1821 if (was_opened)
1822 err = mlx5e_open_locked(priv->netdev);
1823 }
f62b8bb8 1824
9b37b07f
AS		 1825 mutex_unlock(&priv->state_lock);
1826
f62b8bb8
AV		 1827 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1828 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1829 mlx5e_enable_vlan_filter(priv);
1830 else
1831 mlx5e_disable_vlan_filter(priv);
1832 }
1833
f62b8bb8
AV		 1834 return 0;
1835}
1836
1837static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1838{
1839 struct mlx5e_priv *priv = netdev_priv(netdev);
1840 struct mlx5_core_dev *mdev = priv->mdev;
98e81b0a 1841 bool was_opened;
f62b8bb8 1842 int max_mtu;
98e81b0a 1843 int err = 0;
f62b8bb8 1844
facc9699 1845 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1846
facc9699
SM		 1847 if (new_mtu > max_mtu) {
1848 netdev_err(netdev,
1849 "%s: Bad MTU (%d) > (%d) Max\n",
1850 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1851 return -EINVAL;
1852 }
1853
1854 mutex_lock(&priv->state_lock);
98e81b0a
AS		 1855
1856 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1857 if (was_opened)
1858 mlx5e_close_locked(netdev);
1859
f62b8bb8 1860 netdev->mtu = new_mtu;
98e81b0a
AS		 1861
1862 if (was_opened)
1863 err = mlx5e_open_locked(netdev);
1864
f62b8bb8
AV		 1865 mutex_unlock(&priv->state_lock);
1866
1867 return err;
1868}
1869
1870static struct net_device_ops mlx5e_netdev_ops = {
1871 .ndo_open = mlx5e_open,
1872 .ndo_stop = mlx5e_close,
1873 .ndo_start_xmit = mlx5e_xmit,
1874 .ndo_get_stats64 = mlx5e_get_stats,
1875 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1876 .ndo_set_mac_address = mlx5e_set_mac,
1877 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1878 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1879 .ndo_set_features = mlx5e_set_features,
1880 .ndo_change_mtu = mlx5e_change_mtu,
1881};
1882
1883static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1884{
1885 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1886 return -ENOTSUPP;
1887 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1888 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1889 !MLX5_CAP_ETH(mdev, csum_cap) ||
1890 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1891 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 1892 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1893 MLX5_CAP_FLOWTABLE(mdev,
1894 flow_table_properties_nic_receive.max_ft_level)
1895 < 3) {
f62b8bb8
AV		 1896 mlx5_core_warn(mdev,
1897 "Not creating net device, some required device capabilities are missing\n");
1898 return -ENOTSUPP;
1899 }
1900 return 0;
1901}
1902
58d52291
AS		 1903u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
1904{
1905 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1906
1907 return bf_buf_size -
1908 sizeof(struct mlx5e_tx_wqe) +
1909 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
1910}
1911
f62b8bb8
AV		 1912static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1913 struct net_device *netdev,
1914 int num_comp_vectors)
1915{
1916 struct mlx5e_priv *priv = netdev_priv(netdev);
1917
1918 priv->params.log_sq_size =
1919 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1920 priv->params.log_rq_size =
1921 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1922 priv->params.rx_cq_moderation_usec =
1923 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1924 priv->params.rx_cq_moderation_pkts =
1925 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1926 priv->params.tx_cq_moderation_usec =
1927 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1928 priv->params.tx_cq_moderation_pkts =
1929 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 1930 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
f62b8bb8
AV		 1931 priv->params.min_rx_wqes =
1932 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1933 priv->params.rx_hash_log_tbl_sz =
1934 (order_base_2(num_comp_vectors) >
1935 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1936 order_base_2(num_comp_vectors) :
1937 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1938 priv->params.num_tc = 1;
1939 priv->params.default_vlan_prio = 0;
2be6967c 1940 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 1941
57afead5
AS		 1942 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
1943 sizeof(priv->params.toeplitz_hash_key));
1944
f62b8bb8
AV		 1945 priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1946 priv->params.lro_wqe_sz =
1947 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1948
1949 priv->mdev = mdev;
1950 priv->netdev = netdev;
1951 priv->params.num_channels = num_comp_vectors;
f62b8bb8
AV		 1952 priv->default_vlan_prio = priv->params.default_vlan_prio;
1953
1954 spin_lock_init(&priv->async_events_spinlock);
1955 mutex_init(&priv->state_lock);
1956
1957 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1958 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1959 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1960}
1961
1962static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1963{
1964 struct mlx5e_priv *priv = netdev_priv(netdev);
1965
d18a9470 1966 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
f62b8bb8
AV		 1967}
1968
1969static void mlx5e_build_netdev(struct net_device *netdev)
1970{
1971 struct mlx5e_priv *priv = netdev_priv(netdev);
1972 struct mlx5_core_dev *mdev = priv->mdev;
1973
1974 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1975
a4418a6c 1976 if (priv->params.num_tc > 1)
f62b8bb8 1977 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
f62b8bb8
AV		 1978
1979 netdev->netdev_ops = &mlx5e_netdev_ops;
1980 netdev->watchdog_timeo = 15 * HZ;
1981
1982 netdev->ethtool_ops = &mlx5e_ethtool_ops;
1983
12be4b21 1984 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 1985 netdev->vlan_features |= NETIF_F_IP_CSUM;
1986 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1987 netdev->vlan_features |= NETIF_F_GRO;
1988 netdev->vlan_features |= NETIF_F_TSO;
1989 netdev->vlan_features |= NETIF_F_TSO6;
1990 netdev->vlan_features |= NETIF_F_RXCSUM;
1991 netdev->vlan_features |= NETIF_F_RXHASH;
1992
1993 if (!!MLX5_CAP_ETH(mdev, lro_cap))
1994 netdev->vlan_features |= NETIF_F_LRO;
1995
1996 netdev->hw_features = netdev->vlan_features;
f62b8bb8
AV		 1997 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1998 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1999
2000 netdev->features = netdev->hw_features;
2001 if (!priv->params.lro_en)
2002 netdev->features &= ~NETIF_F_LRO;
2003
2004 netdev->features |= NETIF_F_HIGHDMA;
2005
2006 netdev->priv_flags |= IFF_UNICAST_FLT;
2007
2008 mlx5e_set_netdev_dev_addr(netdev);
2009}
2010
2011static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2012 struct mlx5_core_mr *mr)
2013{
2014 struct mlx5_core_dev *mdev = priv->mdev;
2015 struct mlx5_create_mkey_mbox_in *in;
2016 int err;
2017
2018 in = mlx5_vzalloc(sizeof(*in));
2019 if (!in)
2020 return -ENOMEM;
2021
2022 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2023 MLX5_PERM_LOCAL_READ |
2024 MLX5_ACCESS_MODE_PA;
2025 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2026 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2027
2028 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2029 NULL);
2030
2031 kvfree(in);
2032
2033 return err;
2034}
2035
2036static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2037{
2038 struct net_device *netdev;
2039 struct mlx5e_priv *priv;
2040 int ncv = mdev->priv.eq_table.num_comp_vectors;
2041 int err;
2042
2043 if (mlx5e_check_required_hca_cap(mdev))
2044 return NULL;
2045
03289b88 2046 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
f62b8bb8
AV		 2047 if (!netdev) {
2048 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2049 return NULL;
2050 }
2051
2052 mlx5e_build_netdev_priv(mdev, netdev, ncv);
2053 mlx5e_build_netdev(netdev);
2054
2055 netif_carrier_off(netdev);
2056
2057 priv = netdev_priv(netdev);
2058
2059 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2060 if (err) {
1f2a3003 2061 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
f62b8bb8
AV		 2062 goto err_free_netdev;
2063 }
2064
2065 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2066 if (err) {
1f2a3003 2067 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
f62b8bb8
AV		 2068 goto err_unmap_free_uar;
2069 }
2070
3191e05f
AS		 2071 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2072 if (err) {
1f2a3003 2073 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3191e05f
AS		 2074 goto err_dealloc_pd;
2075 }
2076
f62b8bb8
AV		 2077 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2078 if (err) {
1f2a3003 2079 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3191e05f 2080 goto err_dealloc_transport_domain;
f62b8bb8
AV		 2081 }
2082
40ab6a6e 2083 err = mlx5e_create_tises(priv);
5c50368f 2084 if (err) {
40ab6a6e 2085 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
5c50368f
AS		 2086 goto err_destroy_mkey;
2087 }
2088
2089 err = mlx5e_open_drop_rq(priv);
2090 if (err) {
2091 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
40ab6a6e 2092 goto err_destroy_tises;
5c50368f
AS		 2093 }
2094
40ab6a6e 2095 err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2096 if (err) {
40ab6a6e 2097 mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err);
5c50368f
AS		 2098 goto err_close_drop_rq;
2099 }
2100
40ab6a6e 2101 err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2102 if (err) {
40ab6a6e
AS		 2103 mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err);
2104 goto err_destroy_rqt_indir;
5c50368f
AS		 2105 }
2106
40ab6a6e 2107 err = mlx5e_create_tirs(priv);
5c50368f 2108 if (err) {
40ab6a6e
AS		 2109 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
2110 goto err_destroy_rqt_single;
5c50368f
AS		 2111 }
2112
40ab6a6e 2113 err = mlx5e_create_flow_tables(priv);
5c50368f 2114 if (err) {
40ab6a6e
AS		 2115 mlx5_core_warn(mdev, "create flow tables failed, %d\n", err);
2116 goto err_destroy_tirs;
5c50368f
AS		 2117 }
2118
2119 mlx5e_init_eth_addr(priv);
2120
f62b8bb8
AV		 2121 err = register_netdev(netdev);
2122 if (err) {
1f2a3003 2123 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
40ab6a6e 2124 goto err_destroy_flow_tables;
f62b8bb8
AV		 2125 }
2126
2127 mlx5e_enable_async_events(priv);
9b37b07f 2128 schedule_work(&priv->set_rx_mode_work);
f62b8bb8
AV		 2129
2130 return priv;
2131
40ab6a6e
AS		 2132err_destroy_flow_tables:
2133 mlx5e_destroy_flow_tables(priv);
5c50368f 2134
40ab6a6e
AS		 2135err_destroy_tirs:
2136 mlx5e_destroy_tirs(priv);
5c50368f 2137
40ab6a6e
AS		 2138err_destroy_rqt_single:
2139 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
5c50368f 2140
40ab6a6e
AS		 2141err_destroy_rqt_indir:
2142 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f
AS		 2143
2144err_close_drop_rq:
2145 mlx5e_close_drop_rq(priv);
2146
40ab6a6e
AS		 2147err_destroy_tises:
2148 mlx5e_destroy_tises(priv);
5c50368f 2149
f62b8bb8
AV		 2150err_destroy_mkey:
2151 mlx5_core_destroy_mkey(mdev, &priv->mr);
2152
3191e05f
AS		 2153err_dealloc_transport_domain:
2154 mlx5_dealloc_transport_domain(mdev, priv->tdn);
2155
f62b8bb8
AV		 2156err_dealloc_pd:
2157 mlx5_core_dealloc_pd(mdev, priv->pdn);
2158
2159err_unmap_free_uar:
2160 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
2161
2162err_free_netdev:
2163 free_netdev(netdev);
2164
2165 return NULL;
2166}
2167
2168static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
2169{
2170 struct mlx5e_priv *priv = vpriv;
2171 struct net_device *netdev = priv->netdev;
2172
9b37b07f
AS		 2173 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
2174
2175 schedule_work(&priv->set_rx_mode_work);
1cefa326
AS		 2176 mlx5e_disable_async_events(priv);
2177 flush_scheduled_work();
f62b8bb8 2178 unregister_netdev(netdev);
40ab6a6e
AS		 2179 mlx5e_destroy_flow_tables(priv);
2180 mlx5e_destroy_tirs(priv);
2181 mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT);
2182 mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT);
5c50368f 2183 mlx5e_close_drop_rq(priv);
40ab6a6e 2184 mlx5e_destroy_tises(priv);
f62b8bb8 2185 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3191e05f 2186 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 2187 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
2188 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
f62b8bb8
AV		 2189 free_netdev(netdev);
2190}
2191
2192static void *mlx5e_get_netdev(void *vpriv)
2193{
2194 struct mlx5e_priv *priv = vpriv;
2195
2196 return priv->netdev;
2197}
2198
2199static struct mlx5_interface mlx5e_interface = {
2200 .add = mlx5e_create_netdev,
2201 .remove = mlx5e_destroy_netdev,
2202 .event = mlx5e_async_event,
2203 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
2204 .get_dev = mlx5e_get_netdev,
2205};
2206
2207void mlx5e_init(void)
2208{
2209 mlx5_register_interface(&mlx5e_interface);
2210}
2211
2212void mlx5e_cleanup(void)
2213{
2214 mlx5_unregister_interface(&mlx5e_interface);
2215}
Linux 6.x block layer and io_uring tree(s)