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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
86d722ad | 33 | #include <linux/mlx5/fs.h> |
b3f63c3d | 34 | #include <net/vxlan.h> |
f62b8bb8 | 35 | #include "en.h" |
66e49ded | 36 | #include "eswitch.h" |
b3f63c3d | 37 | #include "vxlan.h" |
f62b8bb8 AV |
38 | |
39 | struct mlx5e_rq_param { | |
40 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; | |
41 | struct mlx5_wq_param wq; | |
42 | }; | |
43 | ||
44 | struct mlx5e_sq_param { | |
45 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
46 | struct mlx5_wq_param wq; | |
58d52291 | 47 | u16 max_inline; |
f62b8bb8 AV |
48 | }; |
49 | ||
50 | struct mlx5e_cq_param { | |
51 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
52 | struct mlx5_wq_param wq; | |
53 | u16 eq_ix; | |
54 | }; | |
55 | ||
56 | struct mlx5e_channel_param { | |
57 | struct mlx5e_rq_param rq; | |
58 | struct mlx5e_sq_param sq; | |
59 | struct mlx5e_cq_param rx_cq; | |
60 | struct mlx5e_cq_param tx_cq; | |
61 | }; | |
62 | ||
63 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
64 | { | |
65 | struct mlx5_core_dev *mdev = priv->mdev; | |
66 | u8 port_state; | |
67 | ||
68 | port_state = mlx5_query_vport_state(mdev, | |
e7546514 | 69 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); |
f62b8bb8 AV |
70 | |
71 | if (port_state == VPORT_STATE_UP) | |
72 | netif_carrier_on(priv->netdev); | |
73 | else | |
74 | netif_carrier_off(priv->netdev); | |
75 | } | |
76 | ||
77 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
78 | { | |
79 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
80 | update_carrier_work); | |
81 | ||
82 | mutex_lock(&priv->state_lock); | |
83 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
84 | mlx5e_update_carrier(priv); | |
85 | mutex_unlock(&priv->state_lock); | |
86 | } | |
87 | ||
efea389d GP |
88 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) |
89 | { | |
90 | struct mlx5_core_dev *mdev = priv->mdev; | |
91 | struct mlx5e_pport_stats *s = &priv->stats.pport; | |
92 | u32 *in; | |
93 | u32 *out; | |
94 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
95 | ||
96 | in = mlx5_vzalloc(sz); | |
97 | out = mlx5_vzalloc(sz); | |
98 | if (!in || !out) | |
99 | goto free_out; | |
100 | ||
101 | MLX5_SET(ppcnt_reg, in, local_port, 1); | |
102 | ||
103 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
104 | mlx5_core_access_reg(mdev, in, sz, out, | |
105 | sz, MLX5_REG_PPCNT, 0, 0); | |
106 | memcpy(s->IEEE_802_3_counters, | |
107 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
108 | sizeof(s->IEEE_802_3_counters)); | |
109 | ||
110 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
111 | mlx5_core_access_reg(mdev, in, sz, out, | |
112 | sz, MLX5_REG_PPCNT, 0, 0); | |
113 | memcpy(s->RFC_2863_counters, | |
114 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
115 | sizeof(s->RFC_2863_counters)); | |
116 | ||
117 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
118 | mlx5_core_access_reg(mdev, in, sz, out, | |
119 | sz, MLX5_REG_PPCNT, 0, 0); | |
120 | memcpy(s->RFC_2819_counters, | |
121 | MLX5_ADDR_OF(ppcnt_reg, out, counter_set), | |
122 | sizeof(s->RFC_2819_counters)); | |
123 | ||
124 | free_out: | |
125 | kvfree(in); | |
126 | kvfree(out); | |
127 | } | |
128 | ||
f62b8bb8 AV |
129 | void mlx5e_update_stats(struct mlx5e_priv *priv) |
130 | { | |
131 | struct mlx5_core_dev *mdev = priv->mdev; | |
132 | struct mlx5e_vport_stats *s = &priv->stats.vport; | |
133 | struct mlx5e_rq_stats *rq_stats; | |
134 | struct mlx5e_sq_stats *sq_stats; | |
135 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
136 | u32 *out; | |
137 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
138 | u64 tx_offload_none; | |
139 | int i, j; | |
140 | ||
141 | out = mlx5_vzalloc(outlen); | |
142 | if (!out) | |
143 | return; | |
144 | ||
145 | /* Collect firts the SW counters and then HW for consistency */ | |
146 | s->tso_packets = 0; | |
147 | s->tso_bytes = 0; | |
89db09eb MF |
148 | s->tso_inner_packets = 0; |
149 | s->tso_inner_bytes = 0; | |
f62b8bb8 AV |
150 | s->tx_queue_stopped = 0; |
151 | s->tx_queue_wake = 0; | |
152 | s->tx_queue_dropped = 0; | |
89db09eb | 153 | s->tx_csum_inner = 0; |
f62b8bb8 AV |
154 | tx_offload_none = 0; |
155 | s->lro_packets = 0; | |
156 | s->lro_bytes = 0; | |
157 | s->rx_csum_none = 0; | |
bbceefce | 158 | s->rx_csum_sw = 0; |
f62b8bb8 AV |
159 | s->rx_wqe_err = 0; |
160 | for (i = 0; i < priv->params.num_channels; i++) { | |
161 | rq_stats = &priv->channel[i]->rq.stats; | |
162 | ||
163 | s->lro_packets += rq_stats->lro_packets; | |
164 | s->lro_bytes += rq_stats->lro_bytes; | |
165 | s->rx_csum_none += rq_stats->csum_none; | |
bbceefce | 166 | s->rx_csum_sw += rq_stats->csum_sw; |
f62b8bb8 AV |
167 | s->rx_wqe_err += rq_stats->wqe_err; |
168 | ||
a4418a6c | 169 | for (j = 0; j < priv->params.num_tc; j++) { |
f62b8bb8 AV |
170 | sq_stats = &priv->channel[i]->sq[j].stats; |
171 | ||
172 | s->tso_packets += sq_stats->tso_packets; | |
173 | s->tso_bytes += sq_stats->tso_bytes; | |
89db09eb MF |
174 | s->tso_inner_packets += sq_stats->tso_inner_packets; |
175 | s->tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f62b8bb8 AV |
176 | s->tx_queue_stopped += sq_stats->stopped; |
177 | s->tx_queue_wake += sq_stats->wake; | |
178 | s->tx_queue_dropped += sq_stats->dropped; | |
89db09eb | 179 | s->tx_csum_inner += sq_stats->csum_offload_inner; |
f62b8bb8 AV |
180 | tx_offload_none += sq_stats->csum_offload_none; |
181 | } | |
182 | } | |
183 | ||
184 | /* HW counters */ | |
185 | memset(in, 0, sizeof(in)); | |
186 | ||
187 | MLX5_SET(query_vport_counter_in, in, opcode, | |
188 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
189 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
190 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
191 | ||
192 | memset(out, 0, outlen); | |
193 | ||
194 | if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen)) | |
195 | goto free_out; | |
196 | ||
197 | #define MLX5_GET_CTR(p, x) \ | |
198 | MLX5_GET64(query_vport_counter_out, p, x) | |
199 | ||
200 | s->rx_error_packets = | |
201 | MLX5_GET_CTR(out, received_errors.packets); | |
202 | s->rx_error_bytes = | |
203 | MLX5_GET_CTR(out, received_errors.octets); | |
204 | s->tx_error_packets = | |
205 | MLX5_GET_CTR(out, transmit_errors.packets); | |
206 | s->tx_error_bytes = | |
207 | MLX5_GET_CTR(out, transmit_errors.octets); | |
208 | ||
209 | s->rx_unicast_packets = | |
210 | MLX5_GET_CTR(out, received_eth_unicast.packets); | |
211 | s->rx_unicast_bytes = | |
212 | MLX5_GET_CTR(out, received_eth_unicast.octets); | |
213 | s->tx_unicast_packets = | |
214 | MLX5_GET_CTR(out, transmitted_eth_unicast.packets); | |
215 | s->tx_unicast_bytes = | |
216 | MLX5_GET_CTR(out, transmitted_eth_unicast.octets); | |
217 | ||
218 | s->rx_multicast_packets = | |
219 | MLX5_GET_CTR(out, received_eth_multicast.packets); | |
220 | s->rx_multicast_bytes = | |
221 | MLX5_GET_CTR(out, received_eth_multicast.octets); | |
222 | s->tx_multicast_packets = | |
223 | MLX5_GET_CTR(out, transmitted_eth_multicast.packets); | |
224 | s->tx_multicast_bytes = | |
225 | MLX5_GET_CTR(out, transmitted_eth_multicast.octets); | |
226 | ||
227 | s->rx_broadcast_packets = | |
228 | MLX5_GET_CTR(out, received_eth_broadcast.packets); | |
229 | s->rx_broadcast_bytes = | |
230 | MLX5_GET_CTR(out, received_eth_broadcast.octets); | |
231 | s->tx_broadcast_packets = | |
232 | MLX5_GET_CTR(out, transmitted_eth_broadcast.packets); | |
233 | s->tx_broadcast_bytes = | |
234 | MLX5_GET_CTR(out, transmitted_eth_broadcast.octets); | |
235 | ||
236 | s->rx_packets = | |
237 | s->rx_unicast_packets + | |
238 | s->rx_multicast_packets + | |
239 | s->rx_broadcast_packets; | |
240 | s->rx_bytes = | |
241 | s->rx_unicast_bytes + | |
242 | s->rx_multicast_bytes + | |
243 | s->rx_broadcast_bytes; | |
244 | s->tx_packets = | |
245 | s->tx_unicast_packets + | |
246 | s->tx_multicast_packets + | |
247 | s->tx_broadcast_packets; | |
248 | s->tx_bytes = | |
249 | s->tx_unicast_bytes + | |
250 | s->tx_multicast_bytes + | |
251 | s->tx_broadcast_bytes; | |
252 | ||
253 | /* Update calculated offload counters */ | |
89db09eb | 254 | s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner; |
bbceefce AS |
255 | s->rx_csum_good = s->rx_packets - s->rx_csum_none - |
256 | s->rx_csum_sw; | |
f62b8bb8 | 257 | |
efea389d | 258 | mlx5e_update_pport_counters(priv); |
f62b8bb8 AV |
259 | free_out: |
260 | kvfree(out); | |
261 | } | |
262 | ||
263 | static void mlx5e_update_stats_work(struct work_struct *work) | |
264 | { | |
265 | struct delayed_work *dwork = to_delayed_work(work); | |
266 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
267 | update_stats_work); | |
268 | mutex_lock(&priv->state_lock); | |
269 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
270 | mlx5e_update_stats(priv); | |
271 | schedule_delayed_work(dwork, | |
272 | msecs_to_jiffies( | |
273 | MLX5E_UPDATE_STATS_INTERVAL)); | |
274 | } | |
275 | mutex_unlock(&priv->state_lock); | |
276 | } | |
277 | ||
daa21560 TT |
278 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
279 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 280 | { |
daa21560 TT |
281 | struct mlx5e_priv *priv = vpriv; |
282 | ||
283 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state)) | |
284 | return; | |
285 | ||
f62b8bb8 AV |
286 | switch (event) { |
287 | case MLX5_DEV_EVENT_PORT_UP: | |
288 | case MLX5_DEV_EVENT_PORT_DOWN: | |
289 | schedule_work(&priv->update_carrier_work); | |
290 | break; | |
291 | ||
292 | default: | |
293 | break; | |
294 | } | |
295 | } | |
296 | ||
f62b8bb8 AV |
297 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
298 | { | |
299 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); | |
300 | } | |
301 | ||
302 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
303 | { | |
f62b8bb8 | 304 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state); |
daa21560 | 305 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
306 | } |
307 | ||
facc9699 SM |
308 | #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
309 | #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
310 | ||
f62b8bb8 AV |
311 | static int mlx5e_create_rq(struct mlx5e_channel *c, |
312 | struct mlx5e_rq_param *param, | |
313 | struct mlx5e_rq *rq) | |
314 | { | |
315 | struct mlx5e_priv *priv = c->priv; | |
316 | struct mlx5_core_dev *mdev = priv->mdev; | |
317 | void *rqc = param->rqc; | |
318 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
319 | int wq_sz; | |
320 | int err; | |
321 | int i; | |
322 | ||
311c7c71 SM |
323 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
324 | ||
f62b8bb8 AV |
325 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, |
326 | &rq->wq_ctrl); | |
327 | if (err) | |
328 | return err; | |
329 | ||
330 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
331 | ||
332 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
333 | rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL, | |
334 | cpu_to_node(c->cpu)); | |
335 | if (!rq->skb) { | |
336 | err = -ENOMEM; | |
337 | goto err_rq_wq_destroy; | |
338 | } | |
339 | ||
340 | rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz : | |
facc9699 | 341 | MLX5E_SW2HW_MTU(priv->netdev->mtu); |
fc11fbf9 | 342 | rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN); |
f62b8bb8 AV |
343 | |
344 | for (i = 0; i < wq_sz; i++) { | |
345 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
fc11fbf9 | 346 | u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN; |
f62b8bb8 AV |
347 | |
348 | wqe->data.lkey = c->mkey_be; | |
fc11fbf9 SM |
349 | wqe->data.byte_count = |
350 | cpu_to_be32(byte_count | MLX5_HW_START_PADDING); | |
f62b8bb8 AV |
351 | } |
352 | ||
353 | rq->pdev = c->pdev; | |
354 | rq->netdev = c->netdev; | |
ef9814de | 355 | rq->tstamp = &priv->tstamp; |
f62b8bb8 AV |
356 | rq->channel = c; |
357 | rq->ix = c->ix; | |
50cfa25a | 358 | rq->priv = c->priv; |
f62b8bb8 AV |
359 | |
360 | return 0; | |
361 | ||
362 | err_rq_wq_destroy: | |
363 | mlx5_wq_destroy(&rq->wq_ctrl); | |
364 | ||
365 | return err; | |
366 | } | |
367 | ||
368 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
369 | { | |
370 | kfree(rq->skb); | |
371 | mlx5_wq_destroy(&rq->wq_ctrl); | |
372 | } | |
373 | ||
374 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
375 | { | |
50cfa25a | 376 | struct mlx5e_priv *priv = rq->priv; |
f62b8bb8 AV |
377 | struct mlx5_core_dev *mdev = priv->mdev; |
378 | ||
379 | void *in; | |
380 | void *rqc; | |
381 | void *wq; | |
382 | int inlen; | |
383 | int err; | |
384 | ||
385 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
386 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
387 | in = mlx5_vzalloc(inlen); | |
388 | if (!in) | |
389 | return -ENOMEM; | |
390 | ||
391 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
392 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
393 | ||
394 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
395 | ||
97de9f31 | 396 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 AV |
397 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
398 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
f62b8bb8 | 399 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 400 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
401 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
402 | ||
403 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
404 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
405 | ||
7db22ffb | 406 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
407 | |
408 | kvfree(in); | |
409 | ||
410 | return err; | |
411 | } | |
412 | ||
413 | static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state) | |
414 | { | |
415 | struct mlx5e_channel *c = rq->channel; | |
416 | struct mlx5e_priv *priv = c->priv; | |
417 | struct mlx5_core_dev *mdev = priv->mdev; | |
418 | ||
419 | void *in; | |
420 | void *rqc; | |
421 | int inlen; | |
422 | int err; | |
423 | ||
424 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
425 | in = mlx5_vzalloc(inlen); | |
426 | if (!in) | |
427 | return -ENOMEM; | |
428 | ||
429 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
430 | ||
431 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
432 | MLX5_SET(rqc, rqc, state, next_state); | |
433 | ||
7db22ffb | 434 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
435 | |
436 | kvfree(in); | |
437 | ||
438 | return err; | |
439 | } | |
440 | ||
441 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) | |
442 | { | |
50cfa25a | 443 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); |
f62b8bb8 AV |
444 | } |
445 | ||
446 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
447 | { | |
01c196a2 | 448 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 AV |
449 | struct mlx5e_channel *c = rq->channel; |
450 | struct mlx5e_priv *priv = c->priv; | |
451 | struct mlx5_wq_ll *wq = &rq->wq; | |
f62b8bb8 | 452 | |
01c196a2 | 453 | while (time_before(jiffies, exp_time)) { |
f62b8bb8 AV |
454 | if (wq->cur_sz >= priv->params.min_rx_wqes) |
455 | return 0; | |
456 | ||
457 | msleep(20); | |
458 | } | |
459 | ||
460 | return -ETIMEDOUT; | |
461 | } | |
462 | ||
463 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
464 | struct mlx5e_rq_param *param, | |
465 | struct mlx5e_rq *rq) | |
466 | { | |
467 | int err; | |
468 | ||
469 | err = mlx5e_create_rq(c, param, rq); | |
470 | if (err) | |
471 | return err; | |
472 | ||
473 | err = mlx5e_enable_rq(rq, param); | |
474 | if (err) | |
475 | goto err_destroy_rq; | |
476 | ||
477 | err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); | |
478 | if (err) | |
479 | goto err_disable_rq; | |
480 | ||
481 | set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
12be4b21 | 482 | mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */ |
f62b8bb8 AV |
483 | |
484 | return 0; | |
485 | ||
486 | err_disable_rq: | |
487 | mlx5e_disable_rq(rq); | |
488 | err_destroy_rq: | |
489 | mlx5e_destroy_rq(rq); | |
490 | ||
491 | return err; | |
492 | } | |
493 | ||
494 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
495 | { | |
496 | clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
497 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
498 | ||
499 | mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); | |
500 | while (!mlx5_wq_ll_is_empty(&rq->wq)) | |
501 | msleep(20); | |
502 | ||
503 | /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */ | |
504 | napi_synchronize(&rq->channel->napi); | |
505 | ||
506 | mlx5e_disable_rq(rq); | |
507 | mlx5e_destroy_rq(rq); | |
508 | } | |
509 | ||
510 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
511 | { | |
34802a42 | 512 | kfree(sq->wqe_info); |
f62b8bb8 AV |
513 | kfree(sq->dma_fifo); |
514 | kfree(sq->skb); | |
515 | } | |
516 | ||
517 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
518 | { | |
519 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
520 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
521 | ||
522 | sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa); | |
523 | sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL, | |
524 | numa); | |
34802a42 AS |
525 | sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL, |
526 | numa); | |
f62b8bb8 | 527 | |
34802a42 | 528 | if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) { |
f62b8bb8 AV |
529 | mlx5e_free_sq_db(sq); |
530 | return -ENOMEM; | |
531 | } | |
532 | ||
533 | sq->dma_fifo_mask = df_sz - 1; | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
539 | int tc, | |
540 | struct mlx5e_sq_param *param, | |
541 | struct mlx5e_sq *sq) | |
542 | { | |
543 | struct mlx5e_priv *priv = c->priv; | |
544 | struct mlx5_core_dev *mdev = priv->mdev; | |
545 | ||
546 | void *sqc = param->sqc; | |
547 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
03289b88 | 548 | int txq_ix; |
f62b8bb8 AV |
549 | int err; |
550 | ||
551 | err = mlx5_alloc_map_uar(mdev, &sq->uar); | |
552 | if (err) | |
553 | return err; | |
554 | ||
311c7c71 SM |
555 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
556 | ||
f62b8bb8 AV |
557 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, |
558 | &sq->wq_ctrl); | |
559 | if (err) | |
560 | goto err_unmap_free_uar; | |
561 | ||
562 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
563 | sq->uar_map = sq->uar.map; | |
88a85f99 | 564 | sq->uar_bf_map = sq->uar.bf_map; |
f62b8bb8 | 565 | sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; |
58d52291 | 566 | sq->max_inline = param->max_inline; |
f62b8bb8 | 567 | |
7ec0bb22 DC |
568 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); |
569 | if (err) | |
f62b8bb8 AV |
570 | goto err_sq_wq_destroy; |
571 | ||
03289b88 SM |
572 | txq_ix = c->ix + tc * priv->params.num_channels; |
573 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
f62b8bb8 | 574 | |
88a85f99 | 575 | sq->pdev = c->pdev; |
ef9814de | 576 | sq->tstamp = &priv->tstamp; |
88a85f99 AS |
577 | sq->mkey_be = c->mkey_be; |
578 | sq->channel = c; | |
579 | sq->tc = tc; | |
580 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; | |
581 | sq->bf_budget = MLX5E_SQ_BF_BUDGET; | |
03289b88 | 582 | priv->txq_to_sq_map[txq_ix] = sq; |
f62b8bb8 AV |
583 | |
584 | return 0; | |
585 | ||
586 | err_sq_wq_destroy: | |
587 | mlx5_wq_destroy(&sq->wq_ctrl); | |
588 | ||
589 | err_unmap_free_uar: | |
590 | mlx5_unmap_free_uar(mdev, &sq->uar); | |
591 | ||
592 | return err; | |
593 | } | |
594 | ||
595 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
596 | { | |
597 | struct mlx5e_channel *c = sq->channel; | |
598 | struct mlx5e_priv *priv = c->priv; | |
599 | ||
600 | mlx5e_free_sq_db(sq); | |
601 | mlx5_wq_destroy(&sq->wq_ctrl); | |
602 | mlx5_unmap_free_uar(priv->mdev, &sq->uar); | |
603 | } | |
604 | ||
605 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
606 | { | |
607 | struct mlx5e_channel *c = sq->channel; | |
608 | struct mlx5e_priv *priv = c->priv; | |
609 | struct mlx5_core_dev *mdev = priv->mdev; | |
610 | ||
611 | void *in; | |
612 | void *sqc; | |
613 | void *wq; | |
614 | int inlen; | |
615 | int err; | |
616 | ||
617 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
618 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
619 | in = mlx5_vzalloc(inlen); | |
620 | if (!in) | |
621 | return -ENOMEM; | |
622 | ||
623 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
624 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
625 | ||
626 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
627 | ||
f62b8bb8 AV |
628 | MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]); |
629 | MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn); | |
630 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); | |
631 | MLX5_SET(sqc, sqc, tis_lst_sz, 1); | |
632 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); | |
633 | ||
634 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
635 | MLX5_SET(wq, wq, uar_page, sq->uar.index); | |
636 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 637 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
638 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); |
639 | ||
640 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
641 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
642 | ||
7db22ffb | 643 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); |
f62b8bb8 AV |
644 | |
645 | kvfree(in); | |
646 | ||
647 | return err; | |
648 | } | |
649 | ||
650 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) | |
651 | { | |
652 | struct mlx5e_channel *c = sq->channel; | |
653 | struct mlx5e_priv *priv = c->priv; | |
654 | struct mlx5_core_dev *mdev = priv->mdev; | |
655 | ||
656 | void *in; | |
657 | void *sqc; | |
658 | int inlen; | |
659 | int err; | |
660 | ||
661 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
662 | in = mlx5_vzalloc(inlen); | |
663 | if (!in) | |
664 | return -ENOMEM; | |
665 | ||
666 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
667 | ||
668 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
669 | MLX5_SET(sqc, sqc, state, next_state); | |
670 | ||
7db22ffb | 671 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); |
f62b8bb8 AV |
672 | |
673 | kvfree(in); | |
674 | ||
675 | return err; | |
676 | } | |
677 | ||
678 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
679 | { | |
680 | struct mlx5e_channel *c = sq->channel; | |
681 | struct mlx5e_priv *priv = c->priv; | |
682 | struct mlx5_core_dev *mdev = priv->mdev; | |
683 | ||
7db22ffb | 684 | mlx5_core_destroy_sq(mdev, sq->sqn); |
f62b8bb8 AV |
685 | } |
686 | ||
687 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
688 | int tc, | |
689 | struct mlx5e_sq_param *param, | |
690 | struct mlx5e_sq *sq) | |
691 | { | |
692 | int err; | |
693 | ||
694 | err = mlx5e_create_sq(c, tc, param, sq); | |
695 | if (err) | |
696 | return err; | |
697 | ||
698 | err = mlx5e_enable_sq(sq, param); | |
699 | if (err) | |
700 | goto err_destroy_sq; | |
701 | ||
702 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); | |
703 | if (err) | |
704 | goto err_disable_sq; | |
705 | ||
706 | set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
707 | netdev_tx_reset_queue(sq->txq); | |
708 | netif_tx_start_queue(sq->txq); | |
709 | ||
710 | return 0; | |
711 | ||
712 | err_disable_sq: | |
713 | mlx5e_disable_sq(sq); | |
714 | err_destroy_sq: | |
715 | mlx5e_destroy_sq(sq); | |
716 | ||
717 | return err; | |
718 | } | |
719 | ||
720 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
721 | { | |
722 | __netif_tx_lock_bh(txq); | |
723 | netif_tx_stop_queue(txq); | |
724 | __netif_tx_unlock_bh(txq); | |
725 | } | |
726 | ||
727 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
728 | { | |
729 | clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
730 | napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */ | |
731 | netif_tx_disable_queue(sq->txq); | |
732 | ||
733 | /* ensure hw is notified of all pending wqes */ | |
734 | if (mlx5e_sq_has_room_for(sq, 1)) | |
12be4b21 | 735 | mlx5e_send_nop(sq, true); |
f62b8bb8 AV |
736 | |
737 | mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR); | |
738 | while (sq->cc != sq->pc) /* wait till sq is empty */ | |
739 | msleep(20); | |
740 | ||
741 | /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */ | |
742 | napi_synchronize(&sq->channel->napi); | |
743 | ||
744 | mlx5e_disable_sq(sq); | |
745 | mlx5e_destroy_sq(sq); | |
746 | } | |
747 | ||
748 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
749 | struct mlx5e_cq_param *param, | |
750 | struct mlx5e_cq *cq) | |
751 | { | |
752 | struct mlx5e_priv *priv = c->priv; | |
753 | struct mlx5_core_dev *mdev = priv->mdev; | |
754 | struct mlx5_core_cq *mcq = &cq->mcq; | |
755 | int eqn_not_used; | |
0b6e26ce | 756 | unsigned int irqn; |
f62b8bb8 AV |
757 | int err; |
758 | u32 i; | |
759 | ||
311c7c71 SM |
760 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
761 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
f62b8bb8 AV |
762 | param->eq_ix = c->ix; |
763 | ||
764 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
765 | &cq->wq_ctrl); | |
766 | if (err) | |
767 | return err; | |
768 | ||
769 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
770 | ||
771 | cq->napi = &c->napi; | |
772 | ||
773 | mcq->cqe_sz = 64; | |
774 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
775 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
776 | *mcq->set_ci_db = 0; | |
777 | *mcq->arm_db = 0; | |
778 | mcq->vector = param->eq_ix; | |
779 | mcq->comp = mlx5e_completion_event; | |
780 | mcq->event = mlx5e_cq_error_event; | |
781 | mcq->irqn = irqn; | |
782 | mcq->uar = &priv->cq_uar; | |
783 | ||
784 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
785 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
786 | ||
787 | cqe->op_own = 0xf1; | |
788 | } | |
789 | ||
790 | cq->channel = c; | |
50cfa25a | 791 | cq->priv = priv; |
f62b8bb8 AV |
792 | |
793 | return 0; | |
794 | } | |
795 | ||
796 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
797 | { | |
798 | mlx5_wq_destroy(&cq->wq_ctrl); | |
799 | } | |
800 | ||
801 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
802 | { | |
50cfa25a | 803 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
804 | struct mlx5_core_dev *mdev = priv->mdev; |
805 | struct mlx5_core_cq *mcq = &cq->mcq; | |
806 | ||
807 | void *in; | |
808 | void *cqc; | |
809 | int inlen; | |
0b6e26ce | 810 | unsigned int irqn_not_used; |
f62b8bb8 AV |
811 | int eqn; |
812 | int err; | |
813 | ||
814 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
815 | sizeof(u64) * cq->wq_ctrl.buf.npages; | |
816 | in = mlx5_vzalloc(inlen); | |
817 | if (!in) | |
818 | return -ENOMEM; | |
819 | ||
820 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
821 | ||
822 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
823 | ||
824 | mlx5_fill_page_array(&cq->wq_ctrl.buf, | |
825 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
826 | ||
827 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
828 | ||
829 | MLX5_SET(cqc, cqc, c_eqn, eqn); | |
830 | MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); | |
831 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 832 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
833 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
834 | ||
835 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
836 | ||
837 | kvfree(in); | |
838 | ||
839 | if (err) | |
840 | return err; | |
841 | ||
842 | mlx5e_cq_arm(cq); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
848 | { | |
50cfa25a | 849 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
850 | struct mlx5_core_dev *mdev = priv->mdev; |
851 | ||
852 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
853 | } | |
854 | ||
855 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
856 | struct mlx5e_cq_param *param, | |
857 | struct mlx5e_cq *cq, | |
858 | u16 moderation_usecs, | |
859 | u16 moderation_frames) | |
860 | { | |
861 | int err; | |
862 | struct mlx5e_priv *priv = c->priv; | |
863 | struct mlx5_core_dev *mdev = priv->mdev; | |
864 | ||
865 | err = mlx5e_create_cq(c, param, cq); | |
866 | if (err) | |
867 | return err; | |
868 | ||
869 | err = mlx5e_enable_cq(cq, param); | |
870 | if (err) | |
871 | goto err_destroy_cq; | |
872 | ||
873 | err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
874 | moderation_usecs, | |
875 | moderation_frames); | |
876 | if (err) | |
877 | goto err_destroy_cq; | |
878 | ||
879 | return 0; | |
880 | ||
881 | err_destroy_cq: | |
882 | mlx5e_destroy_cq(cq); | |
883 | ||
884 | return err; | |
885 | } | |
886 | ||
887 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
888 | { | |
889 | mlx5e_disable_cq(cq); | |
890 | mlx5e_destroy_cq(cq); | |
891 | } | |
892 | ||
893 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
894 | { | |
895 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
896 | } | |
897 | ||
898 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
899 | struct mlx5e_channel_param *cparam) | |
900 | { | |
901 | struct mlx5e_priv *priv = c->priv; | |
902 | int err; | |
903 | int tc; | |
904 | ||
905 | for (tc = 0; tc < c->num_tc; tc++) { | |
906 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
907 | priv->params.tx_cq_moderation_usec, | |
908 | priv->params.tx_cq_moderation_pkts); | |
909 | if (err) | |
910 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
911 | } |
912 | ||
913 | return 0; | |
914 | ||
915 | err_close_tx_cqs: | |
916 | for (tc--; tc >= 0; tc--) | |
917 | mlx5e_close_cq(&c->sq[tc].cq); | |
918 | ||
919 | return err; | |
920 | } | |
921 | ||
922 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
923 | { | |
924 | int tc; | |
925 | ||
926 | for (tc = 0; tc < c->num_tc; tc++) | |
927 | mlx5e_close_cq(&c->sq[tc].cq); | |
928 | } | |
929 | ||
930 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
931 | struct mlx5e_channel_param *cparam) | |
932 | { | |
933 | int err; | |
934 | int tc; | |
935 | ||
936 | for (tc = 0; tc < c->num_tc; tc++) { | |
937 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
938 | if (err) | |
939 | goto err_close_sqs; | |
940 | } | |
941 | ||
942 | return 0; | |
943 | ||
944 | err_close_sqs: | |
945 | for (tc--; tc >= 0; tc--) | |
946 | mlx5e_close_sq(&c->sq[tc]); | |
947 | ||
948 | return err; | |
949 | } | |
950 | ||
951 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
952 | { | |
953 | int tc; | |
954 | ||
955 | for (tc = 0; tc < c->num_tc; tc++) | |
956 | mlx5e_close_sq(&c->sq[tc]); | |
957 | } | |
958 | ||
5283af89 | 959 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) |
03289b88 SM |
960 | { |
961 | int i; | |
962 | ||
963 | for (i = 0; i < MLX5E_MAX_NUM_TC; i++) | |
5283af89 RS |
964 | priv->channeltc_to_txq_map[ix][i] = |
965 | ix + i * priv->params.num_channels; | |
03289b88 SM |
966 | } |
967 | ||
f62b8bb8 AV |
968 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
969 | struct mlx5e_channel_param *cparam, | |
970 | struct mlx5e_channel **cp) | |
971 | { | |
972 | struct net_device *netdev = priv->netdev; | |
973 | int cpu = mlx5e_get_cpu(priv, ix); | |
974 | struct mlx5e_channel *c; | |
975 | int err; | |
976 | ||
977 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
978 | if (!c) | |
979 | return -ENOMEM; | |
980 | ||
981 | c->priv = priv; | |
982 | c->ix = ix; | |
983 | c->cpu = cpu; | |
984 | c->pdev = &priv->mdev->pdev->dev; | |
985 | c->netdev = priv->netdev; | |
986 | c->mkey_be = cpu_to_be32(priv->mr.key); | |
a4418a6c | 987 | c->num_tc = priv->params.num_tc; |
f62b8bb8 | 988 | |
5283af89 | 989 | mlx5e_build_channeltc_to_txq_map(priv, ix); |
03289b88 | 990 | |
f62b8bb8 AV |
991 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
992 | ||
993 | err = mlx5e_open_tx_cqs(c, cparam); | |
994 | if (err) | |
995 | goto err_napi_del; | |
996 | ||
997 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, | |
998 | priv->params.rx_cq_moderation_usec, | |
999 | priv->params.rx_cq_moderation_pkts); | |
1000 | if (err) | |
1001 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1002 | |
1003 | napi_enable(&c->napi); | |
1004 | ||
1005 | err = mlx5e_open_sqs(c, cparam); | |
1006 | if (err) | |
1007 | goto err_disable_napi; | |
1008 | ||
1009 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); | |
1010 | if (err) | |
1011 | goto err_close_sqs; | |
1012 | ||
1013 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1014 | *cp = c; | |
1015 | ||
1016 | return 0; | |
1017 | ||
1018 | err_close_sqs: | |
1019 | mlx5e_close_sqs(c); | |
1020 | ||
1021 | err_disable_napi: | |
1022 | napi_disable(&c->napi); | |
1023 | mlx5e_close_cq(&c->rq.cq); | |
1024 | ||
1025 | err_close_tx_cqs: | |
1026 | mlx5e_close_tx_cqs(c); | |
1027 | ||
1028 | err_napi_del: | |
1029 | netif_napi_del(&c->napi); | |
7ae92ae5 | 1030 | napi_hash_del(&c->napi); |
f62b8bb8 AV |
1031 | kfree(c); |
1032 | ||
1033 | return err; | |
1034 | } | |
1035 | ||
1036 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1037 | { | |
1038 | mlx5e_close_rq(&c->rq); | |
1039 | mlx5e_close_sqs(c); | |
1040 | napi_disable(&c->napi); | |
1041 | mlx5e_close_cq(&c->rq.cq); | |
1042 | mlx5e_close_tx_cqs(c); | |
1043 | netif_napi_del(&c->napi); | |
7ae92ae5 ED |
1044 | |
1045 | napi_hash_del(&c->napi); | |
1046 | synchronize_rcu(); | |
1047 | ||
f62b8bb8 AV |
1048 | kfree(c); |
1049 | } | |
1050 | ||
1051 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1052 | struct mlx5e_rq_param *param) | |
1053 | { | |
1054 | void *rqc = param->rqc; | |
1055 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1056 | ||
1057 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1058 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); | |
1059 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1060 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
1061 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1062 | ||
311c7c71 | 1063 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 AV |
1064 | param->wq.linear = 1; |
1065 | } | |
1066 | ||
556dd1b9 TT |
1067 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1068 | { | |
1069 | void *rqc = param->rqc; | |
1070 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1071 | ||
1072 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1073 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1074 | } | |
1075 | ||
f62b8bb8 AV |
1076 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, |
1077 | struct mlx5e_sq_param *param) | |
1078 | { | |
1079 | void *sqc = param->sqc; | |
1080 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1081 | ||
1082 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1083 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); | |
1084 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1085 | ||
311c7c71 | 1086 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
58d52291 | 1087 | param->max_inline = priv->params.tx_max_inline; |
f62b8bb8 AV |
1088 | } |
1089 | ||
1090 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1091 | struct mlx5e_cq_param *param) | |
1092 | { | |
1093 | void *cqc = param->cqc; | |
1094 | ||
1095 | MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); | |
1096 | } | |
1097 | ||
1098 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1099 | struct mlx5e_cq_param *param) | |
1100 | { | |
1101 | void *cqc = param->cqc; | |
1102 | ||
1103 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size); | |
1104 | ||
1105 | mlx5e_build_common_cq_param(priv, param); | |
1106 | } | |
1107 | ||
1108 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1109 | struct mlx5e_cq_param *param) | |
1110 | { | |
1111 | void *cqc = param->cqc; | |
1112 | ||
1113 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); | |
1114 | ||
1115 | mlx5e_build_common_cq_param(priv, param); | |
1116 | } | |
1117 | ||
1118 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, | |
1119 | struct mlx5e_channel_param *cparam) | |
1120 | { | |
1121 | memset(cparam, 0, sizeof(*cparam)); | |
1122 | ||
1123 | mlx5e_build_rq_param(priv, &cparam->rq); | |
1124 | mlx5e_build_sq_param(priv, &cparam->sq); | |
1125 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); | |
1126 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
1127 | } | |
1128 | ||
1129 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1130 | { | |
1131 | struct mlx5e_channel_param cparam; | |
a4418a6c | 1132 | int nch = priv->params.num_channels; |
03289b88 | 1133 | int err = -ENOMEM; |
f62b8bb8 AV |
1134 | int i; |
1135 | int j; | |
1136 | ||
a4418a6c AS |
1137 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), |
1138 | GFP_KERNEL); | |
03289b88 | 1139 | |
a4418a6c | 1140 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, |
03289b88 SM |
1141 | sizeof(struct mlx5e_sq *), GFP_KERNEL); |
1142 | ||
1143 | if (!priv->channel || !priv->txq_to_sq_map) | |
1144 | goto err_free_txq_to_sq_map; | |
f62b8bb8 AV |
1145 | |
1146 | mlx5e_build_channel_param(priv, &cparam); | |
a4418a6c | 1147 | for (i = 0; i < nch; i++) { |
f62b8bb8 AV |
1148 | err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]); |
1149 | if (err) | |
1150 | goto err_close_channels; | |
1151 | } | |
1152 | ||
a4418a6c | 1153 | for (j = 0; j < nch; j++) { |
f62b8bb8 AV |
1154 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); |
1155 | if (err) | |
1156 | goto err_close_channels; | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | ||
1161 | err_close_channels: | |
1162 | for (i--; i >= 0; i--) | |
1163 | mlx5e_close_channel(priv->channel[i]); | |
1164 | ||
03289b88 SM |
1165 | err_free_txq_to_sq_map: |
1166 | kfree(priv->txq_to_sq_map); | |
f62b8bb8 AV |
1167 | kfree(priv->channel); |
1168 | ||
1169 | return err; | |
1170 | } | |
1171 | ||
1172 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1173 | { | |
1174 | int i; | |
1175 | ||
1176 | for (i = 0; i < priv->params.num_channels; i++) | |
1177 | mlx5e_close_channel(priv->channel[i]); | |
1178 | ||
03289b88 | 1179 | kfree(priv->txq_to_sq_map); |
f62b8bb8 AV |
1180 | kfree(priv->channel); |
1181 | } | |
1182 | ||
2be6967c SM |
1183 | static int mlx5e_rx_hash_fn(int hfunc) |
1184 | { | |
1185 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1186 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1187 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1188 | } | |
1189 | ||
1190 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1191 | { | |
1192 | int inv = 0; | |
1193 | int i; | |
1194 | ||
1195 | for (i = 0; i < size; i++) | |
1196 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1197 | ||
1198 | return inv; | |
1199 | } | |
1200 | ||
936896e9 AS |
1201 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) |
1202 | { | |
1203 | int i; | |
1204 | ||
1205 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1206 | int ix = i; | |
1207 | ||
1208 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1209 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1210 | ||
2d75b2bc | 1211 | ix = priv->params.indirection_rqt[ix]; |
936896e9 AS |
1212 | ix = ix % priv->params.num_channels; |
1213 | MLX5_SET(rqtc, rqtc, rq_num[i], | |
1214 | test_bit(MLX5E_STATE_OPENED, &priv->state) ? | |
1215 | priv->channel[ix]->rq.rqn : | |
1216 | priv->drop_rq.rqn); | |
1217 | } | |
1218 | } | |
1219 | ||
4cbeaff5 AS |
1220 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, void *rqtc, |
1221 | enum mlx5e_rqt_ix rqt_ix) | |
1222 | { | |
4cbeaff5 AS |
1223 | |
1224 | switch (rqt_ix) { | |
1225 | case MLX5E_INDIRECTION_RQT: | |
936896e9 | 1226 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); |
4cbeaff5 AS |
1227 | |
1228 | break; | |
1229 | ||
1230 | default: /* MLX5E_SINGLE_RQ_RQT */ | |
1231 | MLX5_SET(rqtc, rqtc, rq_num[0], | |
5c50368f AS |
1232 | test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1233 | priv->channel[0]->rq.rqn : | |
1234 | priv->drop_rq.rqn); | |
4cbeaff5 AS |
1235 | |
1236 | break; | |
1237 | } | |
1238 | } | |
1239 | ||
40ab6a6e | 1240 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
f62b8bb8 AV |
1241 | { |
1242 | struct mlx5_core_dev *mdev = priv->mdev; | |
1243 | u32 *in; | |
f62b8bb8 AV |
1244 | void *rqtc; |
1245 | int inlen; | |
4cbeaff5 | 1246 | int sz; |
f62b8bb8 | 1247 | int err; |
4cbeaff5 | 1248 | |
936896e9 | 1249 | sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE; |
f62b8bb8 | 1250 | |
f62b8bb8 AV |
1251 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1252 | in = mlx5_vzalloc(inlen); | |
1253 | if (!in) | |
1254 | return -ENOMEM; | |
1255 | ||
1256 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1257 | ||
1258 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1259 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1260 | ||
4cbeaff5 | 1261 | mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix); |
2be6967c | 1262 | |
4cbeaff5 | 1263 | err = mlx5_core_create_rqt(mdev, in, inlen, &priv->rqtn[rqt_ix]); |
f62b8bb8 AV |
1264 | |
1265 | kvfree(in); | |
1266 | ||
1267 | return err; | |
1268 | } | |
1269 | ||
2d75b2bc | 1270 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
5c50368f AS |
1271 | { |
1272 | struct mlx5_core_dev *mdev = priv->mdev; | |
1273 | u32 *in; | |
1274 | void *rqtc; | |
1275 | int inlen; | |
5c50368f AS |
1276 | int sz; |
1277 | int err; | |
1278 | ||
936896e9 | 1279 | sz = (rqt_ix == MLX5E_SINGLE_RQ_RQT) ? 1 : MLX5E_INDIR_RQT_SIZE; |
5c50368f AS |
1280 | |
1281 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; | |
1282 | in = mlx5_vzalloc(inlen); | |
1283 | if (!in) | |
1284 | return -ENOMEM; | |
1285 | ||
1286 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
1287 | ||
1288 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1289 | ||
1290 | mlx5e_fill_rqt_rqns(priv, rqtc, rqt_ix); | |
1291 | ||
1292 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
1293 | ||
1294 | err = mlx5_core_modify_rqt(mdev, priv->rqtn[rqt_ix], in, inlen); | |
1295 | ||
1296 | kvfree(in); | |
1297 | ||
1298 | return err; | |
1299 | } | |
1300 | ||
40ab6a6e | 1301 | static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix) |
f62b8bb8 | 1302 | { |
4cbeaff5 | 1303 | mlx5_core_destroy_rqt(priv->mdev, priv->rqtn[rqt_ix]); |
f62b8bb8 AV |
1304 | } |
1305 | ||
40ab6a6e AS |
1306 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) |
1307 | { | |
1308 | mlx5e_redirect_rqt(priv, MLX5E_INDIRECTION_RQT); | |
1309 | mlx5e_redirect_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
1310 | } | |
1311 | ||
5c50368f AS |
1312 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) |
1313 | { | |
1314 | if (!priv->params.lro_en) | |
1315 | return; | |
1316 | ||
1317 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
1318 | ||
1319 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
1320 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
1321 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
1322 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
1323 | (priv->params.lro_wqe_sz - | |
1324 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
1325 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, | |
1326 | MLX5_CAP_ETH(priv->mdev, | |
d9a40271 | 1327 | lro_timer_supported_periods[2])); |
5c50368f AS |
1328 | } |
1329 | ||
1330 | static int mlx5e_modify_tir_lro(struct mlx5e_priv *priv, int tt) | |
1331 | { | |
1332 | struct mlx5_core_dev *mdev = priv->mdev; | |
1333 | ||
1334 | void *in; | |
1335 | void *tirc; | |
1336 | int inlen; | |
1337 | int err; | |
1338 | ||
1339 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1340 | in = mlx5_vzalloc(inlen); | |
1341 | if (!in) | |
1342 | return -ENOMEM; | |
1343 | ||
1344 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
1345 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
1346 | ||
1347 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
1348 | ||
1349 | err = mlx5_core_modify_tir(mdev, priv->tirn[tt], in, inlen); | |
1350 | ||
1351 | kvfree(in); | |
1352 | ||
1353 | return err; | |
1354 | } | |
1355 | ||
66189961 TT |
1356 | static int mlx5e_refresh_tir_self_loopback_enable(struct mlx5_core_dev *mdev, |
1357 | u32 tirn) | |
1358 | { | |
1359 | void *in; | |
1360 | int inlen; | |
1361 | int err; | |
1362 | ||
1363 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1364 | in = mlx5_vzalloc(inlen); | |
1365 | if (!in) | |
1366 | return -ENOMEM; | |
1367 | ||
1368 | MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); | |
1369 | ||
1370 | err = mlx5_core_modify_tir(mdev, tirn, in, inlen); | |
1371 | ||
1372 | kvfree(in); | |
1373 | ||
1374 | return err; | |
1375 | } | |
1376 | ||
1377 | static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv) | |
1378 | { | |
1379 | int err; | |
1380 | int i; | |
1381 | ||
1382 | for (i = 0; i < MLX5E_NUM_TT; i++) { | |
1383 | err = mlx5e_refresh_tir_self_loopback_enable(priv->mdev, | |
1384 | priv->tirn[i]); | |
1385 | if (err) | |
1386 | return err; | |
1387 | } | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
40ab6a6e AS |
1392 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) |
1393 | { | |
1394 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1395 | struct mlx5_core_dev *mdev = priv->mdev; | |
1396 | int hw_mtu; | |
1397 | int err; | |
1398 | ||
1399 | err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1); | |
1400 | if (err) | |
1401 | return err; | |
1402 | ||
1403 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
1404 | ||
1405 | if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu) | |
1406 | netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n", | |
1407 | __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu); | |
1408 | ||
1409 | netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
1410 | return 0; | |
1411 | } | |
1412 | ||
08fb1dac SM |
1413 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
1414 | { | |
1415 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1416 | int nch = priv->params.num_channels; | |
1417 | int ntc = priv->params.num_tc; | |
1418 | int tc; | |
1419 | ||
1420 | netdev_reset_tc(netdev); | |
1421 | ||
1422 | if (ntc == 1) | |
1423 | return; | |
1424 | ||
1425 | netdev_set_num_tc(netdev, ntc); | |
1426 | ||
1427 | for (tc = 0; tc < ntc; tc++) | |
1428 | netdev_set_tc_queue(netdev, tc, nch, tc * nch); | |
1429 | } | |
1430 | ||
40ab6a6e AS |
1431 | int mlx5e_open_locked(struct net_device *netdev) |
1432 | { | |
1433 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1434 | int num_txqs; | |
1435 | int err; | |
1436 | ||
1437 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
1438 | ||
08fb1dac SM |
1439 | mlx5e_netdev_set_tcs(netdev); |
1440 | ||
40ab6a6e AS |
1441 | num_txqs = priv->params.num_channels * priv->params.num_tc; |
1442 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
1443 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
1444 | ||
1445 | err = mlx5e_set_dev_port_mtu(netdev); | |
1446 | if (err) | |
343b29f3 | 1447 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1448 | |
1449 | err = mlx5e_open_channels(priv); | |
1450 | if (err) { | |
1451 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
1452 | __func__, err); | |
343b29f3 | 1453 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1454 | } |
1455 | ||
66189961 TT |
1456 | err = mlx5e_refresh_tirs_self_loopback_enable(priv); |
1457 | if (err) { | |
1458 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
1459 | __func__, err); | |
1460 | goto err_close_channels; | |
1461 | } | |
1462 | ||
40ab6a6e | 1463 | mlx5e_redirect_rqts(priv); |
ce89ef36 | 1464 | mlx5e_update_carrier(priv); |
ef9814de | 1465 | mlx5e_timestamp_init(priv); |
40ab6a6e AS |
1466 | |
1467 | schedule_delayed_work(&priv->update_stats_work, 0); | |
40ab6a6e | 1468 | |
9b37b07f | 1469 | return 0; |
343b29f3 | 1470 | |
66189961 TT |
1471 | err_close_channels: |
1472 | mlx5e_close_channels(priv); | |
343b29f3 AS |
1473 | err_clear_state_opened_flag: |
1474 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
1475 | return err; | |
40ab6a6e AS |
1476 | } |
1477 | ||
1478 | static int mlx5e_open(struct net_device *netdev) | |
1479 | { | |
1480 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1481 | int err; | |
1482 | ||
1483 | mutex_lock(&priv->state_lock); | |
1484 | err = mlx5e_open_locked(netdev); | |
1485 | mutex_unlock(&priv->state_lock); | |
1486 | ||
1487 | return err; | |
1488 | } | |
1489 | ||
1490 | int mlx5e_close_locked(struct net_device *netdev) | |
1491 | { | |
1492 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1493 | ||
a1985740 AS |
1494 | /* May already be CLOSED in case a previous configuration operation |
1495 | * (e.g RX/TX queue size change) that involves close&open failed. | |
1496 | */ | |
1497 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1498 | return 0; | |
1499 | ||
40ab6a6e AS |
1500 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
1501 | ||
ef9814de | 1502 | mlx5e_timestamp_cleanup(priv); |
40ab6a6e | 1503 | netif_carrier_off(priv->netdev); |
ce89ef36 | 1504 | mlx5e_redirect_rqts(priv); |
40ab6a6e AS |
1505 | mlx5e_close_channels(priv); |
1506 | ||
1507 | return 0; | |
1508 | } | |
1509 | ||
1510 | static int mlx5e_close(struct net_device *netdev) | |
1511 | { | |
1512 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1513 | int err; | |
1514 | ||
1515 | mutex_lock(&priv->state_lock); | |
1516 | err = mlx5e_close_locked(netdev); | |
1517 | mutex_unlock(&priv->state_lock); | |
1518 | ||
1519 | return err; | |
1520 | } | |
1521 | ||
1522 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
1523 | struct mlx5e_rq *rq, | |
1524 | struct mlx5e_rq_param *param) | |
1525 | { | |
1526 | struct mlx5_core_dev *mdev = priv->mdev; | |
1527 | void *rqc = param->rqc; | |
1528 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1529 | int err; | |
1530 | ||
1531 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
1532 | ||
1533 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
1534 | &rq->wq_ctrl); | |
1535 | if (err) | |
1536 | return err; | |
1537 | ||
1538 | rq->priv = priv; | |
1539 | ||
1540 | return 0; | |
1541 | } | |
1542 | ||
1543 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
1544 | struct mlx5e_cq *cq, | |
1545 | struct mlx5e_cq_param *param) | |
1546 | { | |
1547 | struct mlx5_core_dev *mdev = priv->mdev; | |
1548 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1549 | int eqn_not_used; | |
0b6e26ce | 1550 | unsigned int irqn; |
40ab6a6e AS |
1551 | int err; |
1552 | ||
1553 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1554 | &cq->wq_ctrl); | |
1555 | if (err) | |
1556 | return err; | |
1557 | ||
1558 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1559 | ||
1560 | mcq->cqe_sz = 64; | |
1561 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1562 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1563 | *mcq->set_ci_db = 0; | |
1564 | *mcq->arm_db = 0; | |
1565 | mcq->vector = param->eq_ix; | |
1566 | mcq->comp = mlx5e_completion_event; | |
1567 | mcq->event = mlx5e_cq_error_event; | |
1568 | mcq->irqn = irqn; | |
1569 | mcq->uar = &priv->cq_uar; | |
1570 | ||
1571 | cq->priv = priv; | |
1572 | ||
1573 | return 0; | |
1574 | } | |
1575 | ||
1576 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
1577 | { | |
1578 | struct mlx5e_cq_param cq_param; | |
1579 | struct mlx5e_rq_param rq_param; | |
1580 | struct mlx5e_rq *rq = &priv->drop_rq; | |
1581 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
1582 | int err; | |
1583 | ||
1584 | memset(&cq_param, 0, sizeof(cq_param)); | |
1585 | memset(&rq_param, 0, sizeof(rq_param)); | |
556dd1b9 | 1586 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e AS |
1587 | |
1588 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
1589 | if (err) | |
1590 | return err; | |
1591 | ||
1592 | err = mlx5e_enable_cq(cq, &cq_param); | |
1593 | if (err) | |
1594 | goto err_destroy_cq; | |
1595 | ||
1596 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
1597 | if (err) | |
1598 | goto err_disable_cq; | |
1599 | ||
1600 | err = mlx5e_enable_rq(rq, &rq_param); | |
1601 | if (err) | |
1602 | goto err_destroy_rq; | |
1603 | ||
1604 | return 0; | |
1605 | ||
1606 | err_destroy_rq: | |
1607 | mlx5e_destroy_rq(&priv->drop_rq); | |
1608 | ||
1609 | err_disable_cq: | |
1610 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1611 | ||
1612 | err_destroy_cq: | |
1613 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1614 | ||
1615 | return err; | |
1616 | } | |
1617 | ||
1618 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
1619 | { | |
1620 | mlx5e_disable_rq(&priv->drop_rq); | |
1621 | mlx5e_destroy_rq(&priv->drop_rq); | |
1622 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1623 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1624 | } | |
1625 | ||
1626 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
1627 | { | |
1628 | struct mlx5_core_dev *mdev = priv->mdev; | |
1629 | u32 in[MLX5_ST_SZ_DW(create_tis_in)]; | |
1630 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
1631 | ||
1632 | memset(in, 0, sizeof(in)); | |
1633 | ||
08fb1dac | 1634 | MLX5_SET(tisc, tisc, prio, tc << 1); |
40ab6a6e AS |
1635 | MLX5_SET(tisc, tisc, transport_domain, priv->tdn); |
1636 | ||
1637 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
1638 | } | |
1639 | ||
1640 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
1641 | { | |
1642 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
1643 | } | |
1644 | ||
1645 | static int mlx5e_create_tises(struct mlx5e_priv *priv) | |
1646 | { | |
1647 | int err; | |
1648 | int tc; | |
1649 | ||
08fb1dac | 1650 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) { |
40ab6a6e AS |
1651 | err = mlx5e_create_tis(priv, tc); |
1652 | if (err) | |
1653 | goto err_close_tises; | |
1654 | } | |
1655 | ||
1656 | return 0; | |
1657 | ||
1658 | err_close_tises: | |
1659 | for (tc--; tc >= 0; tc--) | |
1660 | mlx5e_destroy_tis(priv, tc); | |
1661 | ||
1662 | return err; | |
1663 | } | |
1664 | ||
1665 | static void mlx5e_destroy_tises(struct mlx5e_priv *priv) | |
1666 | { | |
1667 | int tc; | |
1668 | ||
08fb1dac | 1669 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) |
40ab6a6e AS |
1670 | mlx5e_destroy_tis(priv, tc); |
1671 | } | |
1672 | ||
f62b8bb8 AV |
1673 | static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt) |
1674 | { | |
1675 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1676 | ||
3191e05f AS |
1677 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
1678 | ||
5a6f8aef AS |
1679 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1680 | MLX5_HASH_FIELD_SEL_DST_IP) | |
f62b8bb8 | 1681 | |
5a6f8aef AS |
1682 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1683 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1684 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
1685 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
f62b8bb8 | 1686 | |
a741749f AS |
1687 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1688 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1689 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
1690 | ||
5c50368f | 1691 | mlx5e_build_tir_ctx_lro(tirc, priv); |
f62b8bb8 | 1692 | |
4cbeaff5 AS |
1693 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
1694 | ||
f62b8bb8 AV |
1695 | switch (tt) { |
1696 | case MLX5E_TT_ANY: | |
4cbeaff5 AS |
1697 | MLX5_SET(tirc, tirc, indirect_table, |
1698 | priv->rqtn[MLX5E_SINGLE_RQ_RQT]); | |
1699 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
f62b8bb8 AV |
1700 | break; |
1701 | default: | |
f62b8bb8 | 1702 | MLX5_SET(tirc, tirc, indirect_table, |
4cbeaff5 | 1703 | priv->rqtn[MLX5E_INDIRECTION_RQT]); |
f62b8bb8 | 1704 | MLX5_SET(tirc, tirc, rx_hash_fn, |
2be6967c SM |
1705 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); |
1706 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
1707 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
1708 | rx_hash_toeplitz_key); | |
1709 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
1710 | rx_hash_toeplitz_key); | |
1711 | ||
1712 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
57afead5 | 1713 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); |
2be6967c | 1714 | } |
f62b8bb8 AV |
1715 | break; |
1716 | } | |
1717 | ||
1718 | switch (tt) { | |
1719 | case MLX5E_TT_IPV4_TCP: | |
1720 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1721 | MLX5_L3_PROT_TYPE_IPV4); | |
1722 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1723 | MLX5_L4_PROT_TYPE_TCP); | |
1724 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1725 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1726 | break; |
1727 | ||
1728 | case MLX5E_TT_IPV6_TCP: | |
1729 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1730 | MLX5_L3_PROT_TYPE_IPV6); | |
1731 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1732 | MLX5_L4_PROT_TYPE_TCP); | |
1733 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1734 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1735 | break; |
1736 | ||
1737 | case MLX5E_TT_IPV4_UDP: | |
1738 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1739 | MLX5_L3_PROT_TYPE_IPV4); | |
1740 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1741 | MLX5_L4_PROT_TYPE_UDP); | |
1742 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1743 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1744 | break; |
1745 | ||
1746 | case MLX5E_TT_IPV6_UDP: | |
1747 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1748 | MLX5_L3_PROT_TYPE_IPV6); | |
1749 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1750 | MLX5_L4_PROT_TYPE_UDP); | |
1751 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1752 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1753 | break; |
1754 | ||
a741749f AS |
1755 | case MLX5E_TT_IPV4_IPSEC_AH: |
1756 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1757 | MLX5_L3_PROT_TYPE_IPV4); | |
1758 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1759 | MLX5_HASH_IP_IPSEC_SPI); | |
1760 | break; | |
1761 | ||
1762 | case MLX5E_TT_IPV6_IPSEC_AH: | |
1763 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1764 | MLX5_L3_PROT_TYPE_IPV6); | |
1765 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1766 | MLX5_HASH_IP_IPSEC_SPI); | |
1767 | break; | |
1768 | ||
1769 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
1770 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1771 | MLX5_L3_PROT_TYPE_IPV4); | |
1772 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1773 | MLX5_HASH_IP_IPSEC_SPI); | |
1774 | break; | |
1775 | ||
1776 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
1777 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1778 | MLX5_L3_PROT_TYPE_IPV6); | |
1779 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1780 | MLX5_HASH_IP_IPSEC_SPI); | |
1781 | break; | |
1782 | ||
f62b8bb8 AV |
1783 | case MLX5E_TT_IPV4: |
1784 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1785 | MLX5_L3_PROT_TYPE_IPV4); | |
1786 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1787 | MLX5_HASH_IP); | |
1788 | break; | |
1789 | ||
1790 | case MLX5E_TT_IPV6: | |
1791 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1792 | MLX5_L3_PROT_TYPE_IPV6); | |
1793 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
1794 | MLX5_HASH_IP); | |
1795 | break; | |
1796 | } | |
1797 | } | |
1798 | ||
40ab6a6e | 1799 | static int mlx5e_create_tir(struct mlx5e_priv *priv, int tt) |
f62b8bb8 AV |
1800 | { |
1801 | struct mlx5_core_dev *mdev = priv->mdev; | |
1802 | u32 *in; | |
1803 | void *tirc; | |
1804 | int inlen; | |
1805 | int err; | |
1806 | ||
1807 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1808 | in = mlx5_vzalloc(inlen); | |
1809 | if (!in) | |
1810 | return -ENOMEM; | |
1811 | ||
1812 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
1813 | ||
1814 | mlx5e_build_tir_ctx(priv, tirc, tt); | |
1815 | ||
7db22ffb | 1816 | err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]); |
f62b8bb8 AV |
1817 | |
1818 | kvfree(in); | |
1819 | ||
1820 | return err; | |
1821 | } | |
1822 | ||
40ab6a6e | 1823 | static void mlx5e_destroy_tir(struct mlx5e_priv *priv, int tt) |
f62b8bb8 | 1824 | { |
7db22ffb | 1825 | mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]); |
f62b8bb8 AV |
1826 | } |
1827 | ||
40ab6a6e | 1828 | static int mlx5e_create_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
1829 | { |
1830 | int err; | |
1831 | int i; | |
1832 | ||
1833 | for (i = 0; i < MLX5E_NUM_TT; i++) { | |
40ab6a6e | 1834 | err = mlx5e_create_tir(priv, i); |
f62b8bb8 | 1835 | if (err) |
40ab6a6e | 1836 | goto err_destroy_tirs; |
f62b8bb8 AV |
1837 | } |
1838 | ||
1839 | return 0; | |
1840 | ||
40ab6a6e | 1841 | err_destroy_tirs: |
f62b8bb8 | 1842 | for (i--; i >= 0; i--) |
40ab6a6e | 1843 | mlx5e_destroy_tir(priv, i); |
f62b8bb8 AV |
1844 | |
1845 | return err; | |
1846 | } | |
1847 | ||
40ab6a6e | 1848 | static void mlx5e_destroy_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
1849 | { |
1850 | int i; | |
1851 | ||
1852 | for (i = 0; i < MLX5E_NUM_TT; i++) | |
40ab6a6e | 1853 | mlx5e_destroy_tir(priv, i); |
f62b8bb8 AV |
1854 | } |
1855 | ||
08fb1dac SM |
1856 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) |
1857 | { | |
1858 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1859 | bool was_opened; | |
1860 | int err = 0; | |
1861 | ||
1862 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
1863 | return -EINVAL; | |
1864 | ||
1865 | mutex_lock(&priv->state_lock); | |
1866 | ||
1867 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
1868 | if (was_opened) | |
1869 | mlx5e_close_locked(priv->netdev); | |
1870 | ||
1871 | priv->params.num_tc = tc ? tc : 1; | |
1872 | ||
1873 | if (was_opened) | |
1874 | err = mlx5e_open_locked(priv->netdev); | |
1875 | ||
1876 | mutex_unlock(&priv->state_lock); | |
1877 | ||
1878 | return err; | |
1879 | } | |
1880 | ||
1881 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
1882 | __be16 proto, struct tc_to_netdev *tc) | |
1883 | { | |
1884 | if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO) | |
1885 | return -EINVAL; | |
1886 | ||
1887 | return mlx5e_setup_tc(dev, tc->tc); | |
1888 | } | |
1889 | ||
f62b8bb8 AV |
1890 | static struct rtnl_link_stats64 * |
1891 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
1892 | { | |
1893 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1894 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; | |
1895 | ||
1896 | stats->rx_packets = vstats->rx_packets; | |
1897 | stats->rx_bytes = vstats->rx_bytes; | |
1898 | stats->tx_packets = vstats->tx_packets; | |
1899 | stats->tx_bytes = vstats->tx_bytes; | |
1900 | stats->multicast = vstats->rx_multicast_packets + | |
1901 | vstats->tx_multicast_packets; | |
1902 | stats->tx_errors = vstats->tx_error_packets; | |
1903 | stats->rx_errors = vstats->rx_error_packets; | |
1904 | stats->tx_dropped = vstats->tx_queue_dropped; | |
1905 | stats->rx_crc_errors = 0; | |
1906 | stats->rx_length_errors = 0; | |
1907 | ||
1908 | return stats; | |
1909 | } | |
1910 | ||
1911 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
1912 | { | |
1913 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1914 | ||
1915 | schedule_work(&priv->set_rx_mode_work); | |
1916 | } | |
1917 | ||
1918 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
1919 | { | |
1920 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1921 | struct sockaddr *saddr = addr; | |
1922 | ||
1923 | if (!is_valid_ether_addr(saddr->sa_data)) | |
1924 | return -EADDRNOTAVAIL; | |
1925 | ||
1926 | netif_addr_lock_bh(netdev); | |
1927 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
1928 | netif_addr_unlock_bh(netdev); | |
1929 | ||
1930 | schedule_work(&priv->set_rx_mode_work); | |
1931 | ||
1932 | return 0; | |
1933 | } | |
1934 | ||
1935 | static int mlx5e_set_features(struct net_device *netdev, | |
1936 | netdev_features_t features) | |
1937 | { | |
1938 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
98e81b0a | 1939 | int err = 0; |
f62b8bb8 | 1940 | netdev_features_t changes = features ^ netdev->features; |
f62b8bb8 AV |
1941 | |
1942 | mutex_lock(&priv->state_lock); | |
f62b8bb8 AV |
1943 | |
1944 | if (changes & NETIF_F_LRO) { | |
98e81b0a AS |
1945 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
1946 | ||
1947 | if (was_opened) | |
1948 | mlx5e_close_locked(priv->netdev); | |
f62b8bb8 | 1949 | |
98e81b0a | 1950 | priv->params.lro_en = !!(features & NETIF_F_LRO); |
5c50368f AS |
1951 | mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV4_TCP); |
1952 | mlx5e_modify_tir_lro(priv, MLX5E_TT_IPV6_TCP); | |
98e81b0a AS |
1953 | |
1954 | if (was_opened) | |
1955 | err = mlx5e_open_locked(priv->netdev); | |
1956 | } | |
f62b8bb8 | 1957 | |
9b37b07f AS |
1958 | mutex_unlock(&priv->state_lock); |
1959 | ||
f62b8bb8 AV |
1960 | if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) { |
1961 | if (features & NETIF_F_HW_VLAN_CTAG_FILTER) | |
1962 | mlx5e_enable_vlan_filter(priv); | |
1963 | else | |
1964 | mlx5e_disable_vlan_filter(priv); | |
1965 | } | |
1966 | ||
fe9f4fe5 | 1967 | return err; |
f62b8bb8 AV |
1968 | } |
1969 | ||
1970 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) | |
1971 | { | |
1972 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1973 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 1974 | bool was_opened; |
f62b8bb8 | 1975 | int max_mtu; |
98e81b0a | 1976 | int err = 0; |
f62b8bb8 | 1977 | |
facc9699 | 1978 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
f62b8bb8 | 1979 | |
50a9eea6 DT |
1980 | max_mtu = MLX5E_HW2SW_MTU(max_mtu); |
1981 | ||
facc9699 SM |
1982 | if (new_mtu > max_mtu) { |
1983 | netdev_err(netdev, | |
1984 | "%s: Bad MTU (%d) > (%d) Max\n", | |
1985 | __func__, new_mtu, max_mtu); | |
f62b8bb8 AV |
1986 | return -EINVAL; |
1987 | } | |
1988 | ||
1989 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
1990 | |
1991 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
1992 | if (was_opened) | |
1993 | mlx5e_close_locked(netdev); | |
1994 | ||
f62b8bb8 | 1995 | netdev->mtu = new_mtu; |
98e81b0a AS |
1996 | |
1997 | if (was_opened) | |
1998 | err = mlx5e_open_locked(netdev); | |
1999 | ||
f62b8bb8 AV |
2000 | mutex_unlock(&priv->state_lock); |
2001 | ||
2002 | return err; | |
2003 | } | |
2004 | ||
ef9814de EBE |
2005 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2006 | { | |
2007 | switch (cmd) { | |
2008 | case SIOCSHWTSTAMP: | |
2009 | return mlx5e_hwstamp_set(dev, ifr); | |
2010 | case SIOCGHWTSTAMP: | |
2011 | return mlx5e_hwstamp_get(dev, ifr); | |
2012 | default: | |
2013 | return -EOPNOTSUPP; | |
2014 | } | |
2015 | } | |
2016 | ||
66e49ded SM |
2017 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2018 | { | |
2019 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2020 | struct mlx5_core_dev *mdev = priv->mdev; | |
2021 | ||
2022 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2023 | } | |
2024 | ||
2025 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) | |
2026 | { | |
2027 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2028 | struct mlx5_core_dev *mdev = priv->mdev; | |
2029 | ||
2030 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
2031 | vlan, qos); | |
2032 | } | |
2033 | ||
2034 | static int mlx5_vport_link2ifla(u8 esw_link) | |
2035 | { | |
2036 | switch (esw_link) { | |
2037 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
2038 | return IFLA_VF_LINK_STATE_DISABLE; | |
2039 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
2040 | return IFLA_VF_LINK_STATE_ENABLE; | |
2041 | } | |
2042 | return IFLA_VF_LINK_STATE_AUTO; | |
2043 | } | |
2044 | ||
2045 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
2046 | { | |
2047 | switch (ifla_link) { | |
2048 | case IFLA_VF_LINK_STATE_DISABLE: | |
2049 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
2050 | case IFLA_VF_LINK_STATE_ENABLE: | |
2051 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
2052 | } | |
2053 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
2054 | } | |
2055 | ||
2056 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
2057 | int link_state) | |
2058 | { | |
2059 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2060 | struct mlx5_core_dev *mdev = priv->mdev; | |
2061 | ||
2062 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
2063 | mlx5_ifla_link2vport(link_state)); | |
2064 | } | |
2065 | ||
2066 | static int mlx5e_get_vf_config(struct net_device *dev, | |
2067 | int vf, struct ifla_vf_info *ivi) | |
2068 | { | |
2069 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2070 | struct mlx5_core_dev *mdev = priv->mdev; | |
2071 | int err; | |
2072 | ||
2073 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
2074 | if (err) | |
2075 | return err; | |
2076 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
2077 | return 0; | |
2078 | } | |
2079 | ||
2080 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
2081 | int vf, struct ifla_vf_stats *vf_stats) | |
2082 | { | |
2083 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2084 | struct mlx5_core_dev *mdev = priv->mdev; | |
2085 | ||
2086 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
2087 | vf_stats); | |
2088 | } | |
2089 | ||
b3f63c3d MF |
2090 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
2091 | sa_family_t sa_family, __be16 port) | |
2092 | { | |
2093 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2094 | ||
2095 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2096 | return; | |
2097 | ||
2098 | mlx5e_vxlan_add_port(priv, be16_to_cpu(port)); | |
2099 | } | |
2100 | ||
2101 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
2102 | sa_family_t sa_family, __be16 port) | |
2103 | { | |
2104 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2105 | ||
2106 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2107 | return; | |
2108 | ||
2109 | mlx5e_vxlan_del_port(priv, be16_to_cpu(port)); | |
2110 | } | |
2111 | ||
2112 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
2113 | struct sk_buff *skb, | |
2114 | netdev_features_t features) | |
2115 | { | |
2116 | struct udphdr *udph; | |
2117 | u16 proto; | |
2118 | u16 port = 0; | |
2119 | ||
2120 | switch (vlan_get_protocol(skb)) { | |
2121 | case htons(ETH_P_IP): | |
2122 | proto = ip_hdr(skb)->protocol; | |
2123 | break; | |
2124 | case htons(ETH_P_IPV6): | |
2125 | proto = ipv6_hdr(skb)->nexthdr; | |
2126 | break; | |
2127 | default: | |
2128 | goto out; | |
2129 | } | |
2130 | ||
2131 | if (proto == IPPROTO_UDP) { | |
2132 | udph = udp_hdr(skb); | |
2133 | port = be16_to_cpu(udph->dest); | |
2134 | } | |
2135 | ||
2136 | /* Verify if UDP port is being offloaded by HW */ | |
2137 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
2138 | return features; | |
2139 | ||
2140 | out: | |
2141 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
2142 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2143 | } | |
2144 | ||
2145 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
2146 | struct net_device *netdev, | |
2147 | netdev_features_t features) | |
2148 | { | |
2149 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2150 | ||
2151 | features = vlan_features_check(skb, features); | |
2152 | features = vxlan_features_check(skb, features); | |
2153 | ||
2154 | /* Validate if the tunneled packet is being offloaded by HW */ | |
2155 | if (skb->encapsulation && | |
2156 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
2157 | return mlx5e_vxlan_features_check(priv, skb, features); | |
2158 | ||
2159 | return features; | |
2160 | } | |
2161 | ||
b0eed40e | 2162 | static const struct net_device_ops mlx5e_netdev_ops_basic = { |
f62b8bb8 AV |
2163 | .ndo_open = mlx5e_open, |
2164 | .ndo_stop = mlx5e_close, | |
2165 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2166 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2167 | .ndo_select_queue = mlx5e_select_queue, | |
f62b8bb8 AV |
2168 | .ndo_get_stats64 = mlx5e_get_stats, |
2169 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2170 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
2171 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
2172 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 2173 | .ndo_set_features = mlx5e_set_features, |
b0eed40e SM |
2174 | .ndo_change_mtu = mlx5e_change_mtu, |
2175 | .ndo_do_ioctl = mlx5e_ioctl, | |
2176 | }; | |
2177 | ||
2178 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
2179 | .ndo_open = mlx5e_open, | |
2180 | .ndo_stop = mlx5e_close, | |
2181 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2182 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2183 | .ndo_select_queue = mlx5e_select_queue, | |
b0eed40e SM |
2184 | .ndo_get_stats64 = mlx5e_get_stats, |
2185 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2186 | .ndo_set_mac_address = mlx5e_set_mac, | |
2187 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
2188 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
2189 | .ndo_set_features = mlx5e_set_features, | |
2190 | .ndo_change_mtu = mlx5e_change_mtu, | |
2191 | .ndo_do_ioctl = mlx5e_ioctl, | |
b3f63c3d MF |
2192 | .ndo_add_vxlan_port = mlx5e_add_vxlan_port, |
2193 | .ndo_del_vxlan_port = mlx5e_del_vxlan_port, | |
2194 | .ndo_features_check = mlx5e_features_check, | |
b0eed40e SM |
2195 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
2196 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
2197 | .ndo_get_vf_config = mlx5e_get_vf_config, | |
2198 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
2199 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
f62b8bb8 AV |
2200 | }; |
2201 | ||
2202 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
2203 | { | |
2204 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
2205 | return -ENOTSUPP; | |
2206 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
2207 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
2208 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
2209 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
2210 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
2211 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
2212 | MLX5_CAP_FLOWTABLE(mdev, | |
2213 | flow_table_properties_nic_receive.max_ft_level) | |
2214 | < 3) { | |
f62b8bb8 AV |
2215 | mlx5_core_warn(mdev, |
2216 | "Not creating net device, some required device capabilities are missing\n"); | |
2217 | return -ENOTSUPP; | |
2218 | } | |
66189961 TT |
2219 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
2220 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
2221 | ||
f62b8bb8 AV |
2222 | return 0; |
2223 | } | |
2224 | ||
58d52291 AS |
2225 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
2226 | { | |
2227 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
2228 | ||
2229 | return bf_buf_size - | |
2230 | sizeof(struct mlx5e_tx_wqe) + | |
2231 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
2232 | } | |
2233 | ||
08fb1dac SM |
2234 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2235 | static void mlx5e_ets_init(struct mlx5e_priv *priv) | |
2236 | { | |
2237 | int i; | |
2238 | ||
2239 | priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1; | |
2240 | for (i = 0; i < priv->params.ets.ets_cap; i++) { | |
2241 | priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC; | |
2242 | priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR; | |
2243 | priv->params.ets.prio_tc[i] = i; | |
2244 | } | |
2245 | ||
2246 | /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */ | |
2247 | priv->params.ets.prio_tc[0] = 1; | |
2248 | priv->params.ets.prio_tc[1] = 0; | |
2249 | } | |
2250 | #endif | |
2251 | ||
f62b8bb8 AV |
2252 | static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, |
2253 | struct net_device *netdev, | |
936896e9 | 2254 | int num_channels) |
f62b8bb8 AV |
2255 | { |
2256 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2d75b2bc | 2257 | int i; |
f62b8bb8 AV |
2258 | |
2259 | priv->params.log_sq_size = | |
2260 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
2261 | priv->params.log_rq_size = | |
2262 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2263 | priv->params.rx_cq_moderation_usec = | |
2264 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
2265 | priv->params.rx_cq_moderation_pkts = | |
2266 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
2267 | priv->params.tx_cq_moderation_usec = | |
2268 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
2269 | priv->params.tx_cq_moderation_pkts = | |
2270 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
58d52291 | 2271 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); |
f62b8bb8 AV |
2272 | priv->params.min_rx_wqes = |
2273 | MLX5E_PARAMS_DEFAULT_MIN_RX_WQES; | |
f62b8bb8 | 2274 | priv->params.num_tc = 1; |
2be6967c | 2275 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; |
f62b8bb8 | 2276 | |
57afead5 AS |
2277 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, |
2278 | sizeof(priv->params.toeplitz_hash_key)); | |
2279 | ||
2d75b2bc AS |
2280 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) |
2281 | priv->params.indirection_rqt[i] = i % num_channels; | |
2282 | ||
f62b8bb8 AV |
2283 | priv->params.lro_wqe_sz = |
2284 | MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
2285 | ||
2286 | priv->mdev = mdev; | |
2287 | priv->netdev = netdev; | |
936896e9 | 2288 | priv->params.num_channels = num_channels; |
08fb1dac SM |
2289 | |
2290 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
2291 | mlx5e_ets_init(priv); | |
2292 | #endif | |
f62b8bb8 | 2293 | |
f62b8bb8 AV |
2294 | mutex_init(&priv->state_lock); |
2295 | ||
2296 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
2297 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
2298 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); | |
2299 | } | |
2300 | ||
2301 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
2302 | { | |
2303 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2304 | ||
e1d7d349 | 2305 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
2306 | if (is_zero_ether_addr(netdev->dev_addr) && |
2307 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
2308 | eth_hw_addr_random(netdev); | |
2309 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
2310 | } | |
f62b8bb8 AV |
2311 | } |
2312 | ||
2313 | static void mlx5e_build_netdev(struct net_device *netdev) | |
2314 | { | |
2315 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2316 | struct mlx5_core_dev *mdev = priv->mdev; | |
2317 | ||
2318 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
2319 | ||
08fb1dac | 2320 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { |
b0eed40e | 2321 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; |
08fb1dac SM |
2322 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2323 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
2324 | #endif | |
2325 | } else { | |
b0eed40e | 2326 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; |
08fb1dac | 2327 | } |
66e49ded | 2328 | |
f62b8bb8 AV |
2329 | netdev->watchdog_timeo = 15 * HZ; |
2330 | ||
2331 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
2332 | ||
12be4b21 | 2333 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
2334 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
2335 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
2336 | netdev->vlan_features |= NETIF_F_GRO; | |
2337 | netdev->vlan_features |= NETIF_F_TSO; | |
2338 | netdev->vlan_features |= NETIF_F_TSO6; | |
2339 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
2340 | netdev->vlan_features |= NETIF_F_RXHASH; | |
2341 | ||
2342 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
2343 | netdev->vlan_features |= NETIF_F_LRO; | |
2344 | ||
2345 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 2346 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
2347 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
2348 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
2349 | ||
b3f63c3d MF |
2350 | if (mlx5e_vxlan_allowed(mdev)) { |
2351 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL; | |
2352 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; | |
2353 | netdev->hw_enc_features |= NETIF_F_RXCSUM; | |
2354 | netdev->hw_enc_features |= NETIF_F_TSO; | |
2355 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
2356 | netdev->hw_enc_features |= NETIF_F_RXHASH; | |
2357 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; | |
2358 | } | |
2359 | ||
f62b8bb8 AV |
2360 | netdev->features = netdev->hw_features; |
2361 | if (!priv->params.lro_en) | |
2362 | netdev->features &= ~NETIF_F_LRO; | |
2363 | ||
2364 | netdev->features |= NETIF_F_HIGHDMA; | |
2365 | ||
2366 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
2367 | ||
2368 | mlx5e_set_netdev_dev_addr(netdev); | |
2369 | } | |
2370 | ||
2371 | static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, | |
2372 | struct mlx5_core_mr *mr) | |
2373 | { | |
2374 | struct mlx5_core_dev *mdev = priv->mdev; | |
2375 | struct mlx5_create_mkey_mbox_in *in; | |
2376 | int err; | |
2377 | ||
2378 | in = mlx5_vzalloc(sizeof(*in)); | |
2379 | if (!in) | |
2380 | return -ENOMEM; | |
2381 | ||
2382 | in->seg.flags = MLX5_PERM_LOCAL_WRITE | | |
2383 | MLX5_PERM_LOCAL_READ | | |
2384 | MLX5_ACCESS_MODE_PA; | |
2385 | in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); | |
2386 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
2387 | ||
2388 | err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL, | |
2389 | NULL); | |
2390 | ||
2391 | kvfree(in); | |
2392 | ||
2393 | return err; | |
2394 | } | |
2395 | ||
2396 | static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) | |
2397 | { | |
2398 | struct net_device *netdev; | |
2399 | struct mlx5e_priv *priv; | |
3435ab59 | 2400 | int nch = mlx5e_get_max_num_channels(mdev); |
f62b8bb8 AV |
2401 | int err; |
2402 | ||
2403 | if (mlx5e_check_required_hca_cap(mdev)) | |
2404 | return NULL; | |
2405 | ||
08fb1dac SM |
2406 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
2407 | nch * MLX5E_MAX_NUM_TC, | |
2408 | nch); | |
f62b8bb8 AV |
2409 | if (!netdev) { |
2410 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
2411 | return NULL; | |
2412 | } | |
2413 | ||
936896e9 | 2414 | mlx5e_build_netdev_priv(mdev, netdev, nch); |
f62b8bb8 AV |
2415 | mlx5e_build_netdev(netdev); |
2416 | ||
2417 | netif_carrier_off(netdev); | |
2418 | ||
2419 | priv = netdev_priv(netdev); | |
2420 | ||
2421 | err = mlx5_alloc_map_uar(mdev, &priv->cq_uar); | |
2422 | if (err) { | |
1f2a3003 | 2423 | mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err); |
f62b8bb8 AV |
2424 | goto err_free_netdev; |
2425 | } | |
2426 | ||
2427 | err = mlx5_core_alloc_pd(mdev, &priv->pdn); | |
2428 | if (err) { | |
1f2a3003 | 2429 | mlx5_core_err(mdev, "alloc pd failed, %d\n", err); |
f62b8bb8 AV |
2430 | goto err_unmap_free_uar; |
2431 | } | |
2432 | ||
8d7f9ecb | 2433 | err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn); |
3191e05f | 2434 | if (err) { |
1f2a3003 | 2435 | mlx5_core_err(mdev, "alloc td failed, %d\n", err); |
3191e05f AS |
2436 | goto err_dealloc_pd; |
2437 | } | |
2438 | ||
f62b8bb8 AV |
2439 | err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr); |
2440 | if (err) { | |
1f2a3003 | 2441 | mlx5_core_err(mdev, "create mkey failed, %d\n", err); |
3191e05f | 2442 | goto err_dealloc_transport_domain; |
f62b8bb8 AV |
2443 | } |
2444 | ||
40ab6a6e | 2445 | err = mlx5e_create_tises(priv); |
5c50368f | 2446 | if (err) { |
40ab6a6e | 2447 | mlx5_core_warn(mdev, "create tises failed, %d\n", err); |
5c50368f AS |
2448 | goto err_destroy_mkey; |
2449 | } | |
2450 | ||
2451 | err = mlx5e_open_drop_rq(priv); | |
2452 | if (err) { | |
2453 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
40ab6a6e | 2454 | goto err_destroy_tises; |
5c50368f AS |
2455 | } |
2456 | ||
40ab6a6e | 2457 | err = mlx5e_create_rqt(priv, MLX5E_INDIRECTION_RQT); |
5c50368f | 2458 | if (err) { |
40ab6a6e | 2459 | mlx5_core_warn(mdev, "create rqt(INDIR) failed, %d\n", err); |
5c50368f AS |
2460 | goto err_close_drop_rq; |
2461 | } | |
2462 | ||
40ab6a6e | 2463 | err = mlx5e_create_rqt(priv, MLX5E_SINGLE_RQ_RQT); |
5c50368f | 2464 | if (err) { |
40ab6a6e AS |
2465 | mlx5_core_warn(mdev, "create rqt(SINGLE) failed, %d\n", err); |
2466 | goto err_destroy_rqt_indir; | |
5c50368f AS |
2467 | } |
2468 | ||
40ab6a6e | 2469 | err = mlx5e_create_tirs(priv); |
5c50368f | 2470 | if (err) { |
40ab6a6e AS |
2471 | mlx5_core_warn(mdev, "create tirs failed, %d\n", err); |
2472 | goto err_destroy_rqt_single; | |
5c50368f AS |
2473 | } |
2474 | ||
40ab6a6e | 2475 | err = mlx5e_create_flow_tables(priv); |
5c50368f | 2476 | if (err) { |
40ab6a6e AS |
2477 | mlx5_core_warn(mdev, "create flow tables failed, %d\n", err); |
2478 | goto err_destroy_tirs; | |
5c50368f AS |
2479 | } |
2480 | ||
2481 | mlx5e_init_eth_addr(priv); | |
2482 | ||
b3f63c3d MF |
2483 | mlx5e_vxlan_init(priv); |
2484 | ||
08fb1dac SM |
2485 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2486 | mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets); | |
2487 | #endif | |
2488 | ||
f62b8bb8 AV |
2489 | err = register_netdev(netdev); |
2490 | if (err) { | |
1f2a3003 | 2491 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
40ab6a6e | 2492 | goto err_destroy_flow_tables; |
f62b8bb8 AV |
2493 | } |
2494 | ||
b3f63c3d MF |
2495 | if (mlx5e_vxlan_allowed(mdev)) |
2496 | vxlan_get_rx_port(netdev); | |
2497 | ||
f62b8bb8 | 2498 | mlx5e_enable_async_events(priv); |
9b37b07f | 2499 | schedule_work(&priv->set_rx_mode_work); |
f62b8bb8 AV |
2500 | |
2501 | return priv; | |
2502 | ||
40ab6a6e AS |
2503 | err_destroy_flow_tables: |
2504 | mlx5e_destroy_flow_tables(priv); | |
5c50368f | 2505 | |
40ab6a6e AS |
2506 | err_destroy_tirs: |
2507 | mlx5e_destroy_tirs(priv); | |
5c50368f | 2508 | |
40ab6a6e AS |
2509 | err_destroy_rqt_single: |
2510 | mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
5c50368f | 2511 | |
40ab6a6e AS |
2512 | err_destroy_rqt_indir: |
2513 | mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT); | |
5c50368f AS |
2514 | |
2515 | err_close_drop_rq: | |
2516 | mlx5e_close_drop_rq(priv); | |
2517 | ||
40ab6a6e AS |
2518 | err_destroy_tises: |
2519 | mlx5e_destroy_tises(priv); | |
5c50368f | 2520 | |
f62b8bb8 AV |
2521 | err_destroy_mkey: |
2522 | mlx5_core_destroy_mkey(mdev, &priv->mr); | |
2523 | ||
3191e05f | 2524 | err_dealloc_transport_domain: |
8d7f9ecb | 2525 | mlx5_core_dealloc_transport_domain(mdev, priv->tdn); |
3191e05f | 2526 | |
f62b8bb8 AV |
2527 | err_dealloc_pd: |
2528 | mlx5_core_dealloc_pd(mdev, priv->pdn); | |
2529 | ||
2530 | err_unmap_free_uar: | |
2531 | mlx5_unmap_free_uar(mdev, &priv->cq_uar); | |
2532 | ||
2533 | err_free_netdev: | |
2534 | free_netdev(netdev); | |
2535 | ||
2536 | return NULL; | |
2537 | } | |
2538 | ||
2539 | static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv) | |
2540 | { | |
2541 | struct mlx5e_priv *priv = vpriv; | |
2542 | struct net_device *netdev = priv->netdev; | |
2543 | ||
9b37b07f AS |
2544 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
2545 | ||
2546 | schedule_work(&priv->set_rx_mode_work); | |
1cefa326 AS |
2547 | mlx5e_disable_async_events(priv); |
2548 | flush_scheduled_work(); | |
f62b8bb8 | 2549 | unregister_netdev(netdev); |
b3f63c3d | 2550 | mlx5e_vxlan_cleanup(priv); |
40ab6a6e AS |
2551 | mlx5e_destroy_flow_tables(priv); |
2552 | mlx5e_destroy_tirs(priv); | |
2553 | mlx5e_destroy_rqt(priv, MLX5E_SINGLE_RQ_RQT); | |
2554 | mlx5e_destroy_rqt(priv, MLX5E_INDIRECTION_RQT); | |
5c50368f | 2555 | mlx5e_close_drop_rq(priv); |
40ab6a6e | 2556 | mlx5e_destroy_tises(priv); |
f62b8bb8 | 2557 | mlx5_core_destroy_mkey(priv->mdev, &priv->mr); |
8d7f9ecb | 2558 | mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn); |
f62b8bb8 AV |
2559 | mlx5_core_dealloc_pd(priv->mdev, priv->pdn); |
2560 | mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); | |
f62b8bb8 AV |
2561 | free_netdev(netdev); |
2562 | } | |
2563 | ||
2564 | static void *mlx5e_get_netdev(void *vpriv) | |
2565 | { | |
2566 | struct mlx5e_priv *priv = vpriv; | |
2567 | ||
2568 | return priv->netdev; | |
2569 | } | |
2570 | ||
2571 | static struct mlx5_interface mlx5e_interface = { | |
2572 | .add = mlx5e_create_netdev, | |
2573 | .remove = mlx5e_destroy_netdev, | |
2574 | .event = mlx5e_async_event, | |
2575 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
2576 | .get_dev = mlx5e_get_netdev, | |
2577 | }; | |
2578 | ||
2579 | void mlx5e_init(void) | |
2580 | { | |
2581 | mlx5_register_interface(&mlx5e_interface); | |
2582 | } | |
2583 | ||
2584 | void mlx5e_cleanup(void) | |
2585 | { | |
2586 | mlx5_unregister_interface(&mlx5e_interface); | |
2587 | } |