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net/mlx5e: Allocate DMA coherent memory on reader NUMA node
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <linux/mlx5/flow_table.h>
34#include "en.h"
35
36struct mlx5e_rq_param {
37 u32 rqc[MLX5_ST_SZ_DW(rqc)];
38 struct mlx5_wq_param wq;
39};
40
41struct mlx5e_sq_param {
42 u32 sqc[MLX5_ST_SZ_DW(sqc)];
43 struct mlx5_wq_param wq;
44};
45
46struct mlx5e_cq_param {
47 u32 cqc[MLX5_ST_SZ_DW(cqc)];
48 struct mlx5_wq_param wq;
49 u16 eq_ix;
50};
51
52struct mlx5e_channel_param {
53 struct mlx5e_rq_param rq;
54 struct mlx5e_sq_param sq;
55 struct mlx5e_cq_param rx_cq;
56 struct mlx5e_cq_param tx_cq;
57};
58
59static void mlx5e_update_carrier(struct mlx5e_priv *priv)
60{
61 struct mlx5_core_dev *mdev = priv->mdev;
62 u8 port_state;
63
64 port_state = mlx5_query_vport_state(mdev,
65 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
66
67 if (port_state == VPORT_STATE_UP)
68 netif_carrier_on(priv->netdev);
69 else
70 netif_carrier_off(priv->netdev);
71}
72
73static void mlx5e_update_carrier_work(struct work_struct *work)
74{
75 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
76 update_carrier_work);
77
78 mutex_lock(&priv->state_lock);
79 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
80 mlx5e_update_carrier(priv);
81 mutex_unlock(&priv->state_lock);
82}
83
84void mlx5e_update_stats(struct mlx5e_priv *priv)
85{
86 struct mlx5_core_dev *mdev = priv->mdev;
87 struct mlx5e_vport_stats *s = &priv->stats.vport;
88 struct mlx5e_rq_stats *rq_stats;
89 struct mlx5e_sq_stats *sq_stats;
90 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
91 u32 *out;
92 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
93 u64 tx_offload_none;
94 int i, j;
95
96 out = mlx5_vzalloc(outlen);
97 if (!out)
98 return;
99
100 /* Collect firts the SW counters and then HW for consistency */
101 s->tso_packets = 0;
102 s->tso_bytes = 0;
103 s->tx_queue_stopped = 0;
104 s->tx_queue_wake = 0;
105 s->tx_queue_dropped = 0;
106 tx_offload_none = 0;
107 s->lro_packets = 0;
108 s->lro_bytes = 0;
109 s->rx_csum_none = 0;
110 s->rx_wqe_err = 0;
111 for (i = 0; i < priv->params.num_channels; i++) {
112 rq_stats = &priv->channel[i]->rq.stats;
113
114 s->lro_packets += rq_stats->lro_packets;
115 s->lro_bytes += rq_stats->lro_bytes;
116 s->rx_csum_none += rq_stats->csum_none;
117 s->rx_wqe_err += rq_stats->wqe_err;
118
119 for (j = 0; j < priv->num_tc; j++) {
120 sq_stats = &priv->channel[i]->sq[j].stats;
121
122 s->tso_packets += sq_stats->tso_packets;
123 s->tso_bytes += sq_stats->tso_bytes;
124 s->tx_queue_stopped += sq_stats->stopped;
125 s->tx_queue_wake += sq_stats->wake;
126 s->tx_queue_dropped += sq_stats->dropped;
127 tx_offload_none += sq_stats->csum_offload_none;
128 }
129 }
130
131 /* HW counters */
132 memset(in, 0, sizeof(in));
133
134 MLX5_SET(query_vport_counter_in, in, opcode,
135 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
136 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
137 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
138
139 memset(out, 0, outlen);
140
141 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
142 goto free_out;
143
144#define MLX5_GET_CTR(p, x) \
145 MLX5_GET64(query_vport_counter_out, p, x)
146
147 s->rx_error_packets =
148 MLX5_GET_CTR(out, received_errors.packets);
149 s->rx_error_bytes =
150 MLX5_GET_CTR(out, received_errors.octets);
151 s->tx_error_packets =
152 MLX5_GET_CTR(out, transmit_errors.packets);
153 s->tx_error_bytes =
154 MLX5_GET_CTR(out, transmit_errors.octets);
155
156 s->rx_unicast_packets =
157 MLX5_GET_CTR(out, received_eth_unicast.packets);
158 s->rx_unicast_bytes =
159 MLX5_GET_CTR(out, received_eth_unicast.octets);
160 s->tx_unicast_packets =
161 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
162 s->tx_unicast_bytes =
163 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
164
165 s->rx_multicast_packets =
166 MLX5_GET_CTR(out, received_eth_multicast.packets);
167 s->rx_multicast_bytes =
168 MLX5_GET_CTR(out, received_eth_multicast.octets);
169 s->tx_multicast_packets =
170 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
171 s->tx_multicast_bytes =
172 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
173
174 s->rx_broadcast_packets =
175 MLX5_GET_CTR(out, received_eth_broadcast.packets);
176 s->rx_broadcast_bytes =
177 MLX5_GET_CTR(out, received_eth_broadcast.octets);
178 s->tx_broadcast_packets =
179 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
180 s->tx_broadcast_bytes =
181 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
182
183 s->rx_packets =
184 s->rx_unicast_packets +
185 s->rx_multicast_packets +
186 s->rx_broadcast_packets;
187 s->rx_bytes =
188 s->rx_unicast_bytes +
189 s->rx_multicast_bytes +
190 s->rx_broadcast_bytes;
191 s->tx_packets =
192 s->tx_unicast_packets +
193 s->tx_multicast_packets +
194 s->tx_broadcast_packets;
195 s->tx_bytes =
196 s->tx_unicast_bytes +
197 s->tx_multicast_bytes +
198 s->tx_broadcast_bytes;
199
200 /* Update calculated offload counters */
201 s->tx_csum_offload = s->tx_packets - tx_offload_none;
202 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
203
204free_out:
205 kvfree(out);
206}
207
208static void mlx5e_update_stats_work(struct work_struct *work)
209{
210 struct delayed_work *dwork = to_delayed_work(work);
211 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
212 update_stats_work);
213 mutex_lock(&priv->state_lock);
214 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
215 mlx5e_update_stats(priv);
216 schedule_delayed_work(dwork,
217 msecs_to_jiffies(
218 MLX5E_UPDATE_STATS_INTERVAL));
219 }
220 mutex_unlock(&priv->state_lock);
221}
222
223static void __mlx5e_async_event(struct mlx5e_priv *priv,
224 enum mlx5_dev_event event)
225{
226 switch (event) {
227 case MLX5_DEV_EVENT_PORT_UP:
228 case MLX5_DEV_EVENT_PORT_DOWN:
229 schedule_work(&priv->update_carrier_work);
230 break;
231
232 default:
233 break;
234 }
235}
236
237static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
238 enum mlx5_dev_event event, unsigned long param)
239{
240 struct mlx5e_priv *priv = vpriv;
241
242 spin_lock(&priv->async_events_spinlock);
243 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
244 __mlx5e_async_event(priv, event);
245 spin_unlock(&priv->async_events_spinlock);
246}
247
248static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
249{
250 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
251}
252
253static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
254{
255 spin_lock_irq(&priv->async_events_spinlock);
256 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
257 spin_unlock_irq(&priv->async_events_spinlock);
258}
259
facc9699
SM		 260#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
261#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
262
f62b8bb8
AV		 263static int mlx5e_create_rq(struct mlx5e_channel *c,
264 struct mlx5e_rq_param *param,
265 struct mlx5e_rq *rq)
266{
267 struct mlx5e_priv *priv = c->priv;
268 struct mlx5_core_dev *mdev = priv->mdev;
269 void *rqc = param->rqc;
270 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
271 int wq_sz;
272 int err;
273 int i;
274
311c7c71
SM		 275 param->wq.db_numa_node = cpu_to_node(c->cpu);
276
f62b8bb8
AV		 277 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
278 &rq->wq_ctrl);
279 if (err)
280 return err;
281
282 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
283
284 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
285 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
286 cpu_to_node(c->cpu));
287 if (!rq->skb) {
288 err = -ENOMEM;
289 goto err_rq_wq_destroy;
290 }
291
292 rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
facc9699 293 MLX5E_SW2HW_MTU(priv->netdev->mtu);
fc11fbf9 294 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
f62b8bb8
AV		 295
296 for (i = 0; i < wq_sz; i++) {
297 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
fc11fbf9 298 u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
f62b8bb8
AV		 299
300 wqe->data.lkey = c->mkey_be;
fc11fbf9
SM		 301 wqe->data.byte_count =
302 cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
f62b8bb8
AV		 303 }
304
305 rq->pdev = c->pdev;
306 rq->netdev = c->netdev;
307 rq->channel = c;
308 rq->ix = c->ix;
309
310 return 0;
311
312err_rq_wq_destroy:
313 mlx5_wq_destroy(&rq->wq_ctrl);
314
315 return err;
316}
317
318static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
319{
320 kfree(rq->skb);
321 mlx5_wq_destroy(&rq->wq_ctrl);
322}
323
324static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
325{
326 struct mlx5e_channel *c = rq->channel;
327 struct mlx5e_priv *priv = c->priv;
328 struct mlx5_core_dev *mdev = priv->mdev;
329
330 void *in;
331 void *rqc;
332 void *wq;
333 int inlen;
334 int err;
335
336 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
337 sizeof(u64) * rq->wq_ctrl.buf.npages;
338 in = mlx5_vzalloc(inlen);
339 if (!in)
340 return -ENOMEM;
341
342 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
343 wq = MLX5_ADDR_OF(rqc, rqc, wq);
344
345 memcpy(rqc, param->rqc, sizeof(param->rqc));
346
347 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
348 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
349 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
f62b8bb8
AV		 350 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
351 PAGE_SHIFT);
352 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
353
354 mlx5_fill_page_array(&rq->wq_ctrl.buf,
355 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
356
7db22ffb 357 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 358
359 kvfree(in);
360
361 return err;
362}
363
364static int mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
365{
366 struct mlx5e_channel *c = rq->channel;
367 struct mlx5e_priv *priv = c->priv;
368 struct mlx5_core_dev *mdev = priv->mdev;
369
370 void *in;
371 void *rqc;
372 int inlen;
373 int err;
374
375 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
376 in = mlx5_vzalloc(inlen);
377 if (!in)
378 return -ENOMEM;
379
380 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
381
382 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
383 MLX5_SET(rqc, rqc, state, next_state);
384
7db22ffb 385 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 386
387 kvfree(in);
388
389 return err;
390}
391
392static void mlx5e_disable_rq(struct mlx5e_rq *rq)
393{
394 struct mlx5e_channel *c = rq->channel;
395 struct mlx5e_priv *priv = c->priv;
396 struct mlx5_core_dev *mdev = priv->mdev;
397
7db22ffb 398 mlx5_core_destroy_rq(mdev, rq->rqn);
f62b8bb8
AV		 399}
400
401static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
402{
403 struct mlx5e_channel *c = rq->channel;
404 struct mlx5e_priv *priv = c->priv;
405 struct mlx5_wq_ll *wq = &rq->wq;
406 int i;
407
408 for (i = 0; i < 1000; i++) {
409 if (wq->cur_sz >= priv->params.min_rx_wqes)
410 return 0;
411
412 msleep(20);
413 }
414
415 return -ETIMEDOUT;
416}
417
418static int mlx5e_open_rq(struct mlx5e_channel *c,
419 struct mlx5e_rq_param *param,
420 struct mlx5e_rq *rq)
421{
422 int err;
423
424 err = mlx5e_create_rq(c, param, rq);
425 if (err)
426 return err;
427
428 err = mlx5e_enable_rq(rq, param);
429 if (err)
430 goto err_destroy_rq;
431
432 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
433 if (err)
434 goto err_disable_rq;
435
436 set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
12be4b21 437 mlx5e_send_nop(&c->sq[0], true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 438
439 return 0;
440
441err_disable_rq:
442 mlx5e_disable_rq(rq);
443err_destroy_rq:
444 mlx5e_destroy_rq(rq);
445
446 return err;
447}
448
449static void mlx5e_close_rq(struct mlx5e_rq *rq)
450{
451 clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
452 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
453
454 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
455 while (!mlx5_wq_ll_is_empty(&rq->wq))
456 msleep(20);
457
458 /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
459 napi_synchronize(&rq->channel->napi);
460
461 mlx5e_disable_rq(rq);
462 mlx5e_destroy_rq(rq);
463}
464
465static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
466{
467 kfree(sq->dma_fifo);
468 kfree(sq->skb);
469}
470
471static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
472{
473 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
474 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
475
476 sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
477 sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
478 numa);
479
480 if (!sq->skb || !sq->dma_fifo) {
481 mlx5e_free_sq_db(sq);
482 return -ENOMEM;
483 }
484
485 sq->dma_fifo_mask = df_sz - 1;
486
487 return 0;
488}
489
490static int mlx5e_create_sq(struct mlx5e_channel *c,
491 int tc,
492 struct mlx5e_sq_param *param,
493 struct mlx5e_sq *sq)
494{
495 struct mlx5e_priv *priv = c->priv;
496 struct mlx5_core_dev *mdev = priv->mdev;
497
498 void *sqc = param->sqc;
499 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
03289b88 500 int txq_ix;
f62b8bb8
AV		 501 int err;
502
503 err = mlx5_alloc_map_uar(mdev, &sq->uar);
504 if (err)
505 return err;
506
311c7c71
SM		 507 param->wq.db_numa_node = cpu_to_node(c->cpu);
508
f62b8bb8
AV		 509 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
510 &sq->wq_ctrl);
511 if (err)
512 goto err_unmap_free_uar;
513
514 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
515 sq->uar_map = sq->uar.map;
516 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
517
7ec0bb22
DC		 518 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
519 if (err)
f62b8bb8
AV		 520 goto err_sq_wq_destroy;
521
03289b88
SM		 522 txq_ix = c->ix + tc * priv->params.num_channels;
523 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
f62b8bb8
AV		 524
525 sq->pdev = c->pdev;
526 sq->mkey_be = c->mkey_be;
527 sq->channel = c;
528 sq->tc = tc;
12be4b21 529 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
03289b88 530 priv->txq_to_sq_map[txq_ix] = sq;
f62b8bb8
AV		 531
532 return 0;
533
534err_sq_wq_destroy:
535 mlx5_wq_destroy(&sq->wq_ctrl);
536
537err_unmap_free_uar:
538 mlx5_unmap_free_uar(mdev, &sq->uar);
539
540 return err;
541}
542
543static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
544{
545 struct mlx5e_channel *c = sq->channel;
546 struct mlx5e_priv *priv = c->priv;
547
548 mlx5e_free_sq_db(sq);
549 mlx5_wq_destroy(&sq->wq_ctrl);
550 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
551}
552
553static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
554{
555 struct mlx5e_channel *c = sq->channel;
556 struct mlx5e_priv *priv = c->priv;
557 struct mlx5_core_dev *mdev = priv->mdev;
558
559 void *in;
560 void *sqc;
561 void *wq;
562 int inlen;
563 int err;
564
565 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
566 sizeof(u64) * sq->wq_ctrl.buf.npages;
567 in = mlx5_vzalloc(inlen);
568 if (!in)
569 return -ENOMEM;
570
571 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
572 wq = MLX5_ADDR_OF(sqc, sqc, wq);
573
574 memcpy(sqc, param->sqc, sizeof(param->sqc));
575
576 MLX5_SET(sqc, sqc, user_index, sq->tc);
577 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
578 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
579 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
580 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
581 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
582
583 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
584 MLX5_SET(wq, wq, uar_page, sq->uar.index);
585 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
586 PAGE_SHIFT);
587 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
588
589 mlx5_fill_page_array(&sq->wq_ctrl.buf,
590 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
591
7db22ffb 592 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 593
594 kvfree(in);
595
596 return err;
597}
598
599static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
600{
601 struct mlx5e_channel *c = sq->channel;
602 struct mlx5e_priv *priv = c->priv;
603 struct mlx5_core_dev *mdev = priv->mdev;
604
605 void *in;
606 void *sqc;
607 int inlen;
608 int err;
609
610 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
611 in = mlx5_vzalloc(inlen);
612 if (!in)
613 return -ENOMEM;
614
615 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
616
617 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
618 MLX5_SET(sqc, sqc, state, next_state);
619
7db22ffb 620 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 621
622 kvfree(in);
623
624 return err;
625}
626
627static void mlx5e_disable_sq(struct mlx5e_sq *sq)
628{
629 struct mlx5e_channel *c = sq->channel;
630 struct mlx5e_priv *priv = c->priv;
631 struct mlx5_core_dev *mdev = priv->mdev;
632
7db22ffb 633 mlx5_core_destroy_sq(mdev, sq->sqn);
f62b8bb8
AV		 634}
635
636static int mlx5e_open_sq(struct mlx5e_channel *c,
637 int tc,
638 struct mlx5e_sq_param *param,
639 struct mlx5e_sq *sq)
640{
641 int err;
642
643 err = mlx5e_create_sq(c, tc, param, sq);
644 if (err)
645 return err;
646
647 err = mlx5e_enable_sq(sq, param);
648 if (err)
649 goto err_destroy_sq;
650
651 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
652 if (err)
653 goto err_disable_sq;
654
655 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
656 netdev_tx_reset_queue(sq->txq);
657 netif_tx_start_queue(sq->txq);
658
659 return 0;
660
661err_disable_sq:
662 mlx5e_disable_sq(sq);
663err_destroy_sq:
664 mlx5e_destroy_sq(sq);
665
666 return err;
667}
668
669static inline void netif_tx_disable_queue(struct netdev_queue *txq)
670{
671 __netif_tx_lock_bh(txq);
672 netif_tx_stop_queue(txq);
673 __netif_tx_unlock_bh(txq);
674}
675
676static void mlx5e_close_sq(struct mlx5e_sq *sq)
677{
678 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
679 napi_synchronize(&sq->channel->napi); /* prevent netif_tx_wake_queue */
680 netif_tx_disable_queue(sq->txq);
681
682 /* ensure hw is notified of all pending wqes */
683 if (mlx5e_sq_has_room_for(sq, 1))
12be4b21 684 mlx5e_send_nop(sq, true);
f62b8bb8
AV		 685
686 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
687 while (sq->cc != sq->pc) /* wait till sq is empty */
688 msleep(20);
689
690 /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
691 napi_synchronize(&sq->channel->napi);
692
693 mlx5e_disable_sq(sq);
694 mlx5e_destroy_sq(sq);
695}
696
697static int mlx5e_create_cq(struct mlx5e_channel *c,
698 struct mlx5e_cq_param *param,
699 struct mlx5e_cq *cq)
700{
701 struct mlx5e_priv *priv = c->priv;
702 struct mlx5_core_dev *mdev = priv->mdev;
703 struct mlx5_core_cq *mcq = &cq->mcq;
704 int eqn_not_used;
705 int irqn;
706 int err;
707 u32 i;
708
311c7c71
SM		 709 param->wq.buf_numa_node = cpu_to_node(c->cpu);
710 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 711 param->eq_ix = c->ix;
712
713 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
714 &cq->wq_ctrl);
715 if (err)
716 return err;
717
718 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
719
720 cq->napi = &c->napi;
721
722 mcq->cqe_sz = 64;
723 mcq->set_ci_db = cq->wq_ctrl.db.db;
724 mcq->arm_db = cq->wq_ctrl.db.db + 1;
725 *mcq->set_ci_db = 0;
726 *mcq->arm_db = 0;
727 mcq->vector = param->eq_ix;
728 mcq->comp = mlx5e_completion_event;
729 mcq->event = mlx5e_cq_error_event;
730 mcq->irqn = irqn;
731 mcq->uar = &priv->cq_uar;
732
733 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
734 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
735
736 cqe->op_own = 0xf1;
737 }
738
739 cq->channel = c;
740
741 return 0;
742}
743
744static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
745{
746 mlx5_wq_destroy(&cq->wq_ctrl);
747}
748
749static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
750{
751 struct mlx5e_channel *c = cq->channel;
752 struct mlx5e_priv *priv = c->priv;
753 struct mlx5_core_dev *mdev = priv->mdev;
754 struct mlx5_core_cq *mcq = &cq->mcq;
755
756 void *in;
757 void *cqc;
758 int inlen;
759 int irqn_not_used;
760 int eqn;
761 int err;
762
763 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
764 sizeof(u64) * cq->wq_ctrl.buf.npages;
765 in = mlx5_vzalloc(inlen);
766 if (!in)
767 return -ENOMEM;
768
769 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
770
771 memcpy(cqc, param->cqc, sizeof(param->cqc));
772
773 mlx5_fill_page_array(&cq->wq_ctrl.buf,
774 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
775
776 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
777
778 MLX5_SET(cqc, cqc, c_eqn, eqn);
779 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
780 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
781 PAGE_SHIFT);
782 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
783
784 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
785
786 kvfree(in);
787
788 if (err)
789 return err;
790
791 mlx5e_cq_arm(cq);
792
793 return 0;
794}
795
796static void mlx5e_disable_cq(struct mlx5e_cq *cq)
797{
798 struct mlx5e_channel *c = cq->channel;
799 struct mlx5e_priv *priv = c->priv;
800 struct mlx5_core_dev *mdev = priv->mdev;
801
802 mlx5_core_destroy_cq(mdev, &cq->mcq);
803}
804
805static int mlx5e_open_cq(struct mlx5e_channel *c,
806 struct mlx5e_cq_param *param,
807 struct mlx5e_cq *cq,
808 u16 moderation_usecs,
809 u16 moderation_frames)
810{
811 int err;
812 struct mlx5e_priv *priv = c->priv;
813 struct mlx5_core_dev *mdev = priv->mdev;
814
815 err = mlx5e_create_cq(c, param, cq);
816 if (err)
817 return err;
818
819 err = mlx5e_enable_cq(cq, param);
820 if (err)
821 goto err_destroy_cq;
822
823 err = mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
824 moderation_usecs,
825 moderation_frames);
826 if (err)
827 goto err_destroy_cq;
828
829 return 0;
830
831err_destroy_cq:
832 mlx5e_destroy_cq(cq);
833
834 return err;
835}
836
837static void mlx5e_close_cq(struct mlx5e_cq *cq)
838{
839 mlx5e_disable_cq(cq);
840 mlx5e_destroy_cq(cq);
841}
842
843static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
844{
845 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
846}
847
848static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
849 struct mlx5e_channel_param *cparam)
850{
851 struct mlx5e_priv *priv = c->priv;
852 int err;
853 int tc;
854
855 for (tc = 0; tc < c->num_tc; tc++) {
856 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
857 priv->params.tx_cq_moderation_usec,
858 priv->params.tx_cq_moderation_pkts);
859 if (err)
860 goto err_close_tx_cqs;
f62b8bb8
AV		 861 }
862
863 return 0;
864
865err_close_tx_cqs:
866 for (tc--; tc >= 0; tc--)
867 mlx5e_close_cq(&c->sq[tc].cq);
868
869 return err;
870}
871
872static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
873{
874 int tc;
875
876 for (tc = 0; tc < c->num_tc; tc++)
877 mlx5e_close_cq(&c->sq[tc].cq);
878}
879
880static int mlx5e_open_sqs(struct mlx5e_channel *c,
881 struct mlx5e_channel_param *cparam)
882{
883 int err;
884 int tc;
885
886 for (tc = 0; tc < c->num_tc; tc++) {
887 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
888 if (err)
889 goto err_close_sqs;
890 }
891
892 return 0;
893
894err_close_sqs:
895 for (tc--; tc >= 0; tc--)
896 mlx5e_close_sq(&c->sq[tc]);
897
898 return err;
899}
900
901static void mlx5e_close_sqs(struct mlx5e_channel *c)
902{
903 int tc;
904
905 for (tc = 0; tc < c->num_tc; tc++)
906 mlx5e_close_sq(&c->sq[tc]);
907}
908
03289b88
SM		 909static void mlx5e_build_tc_to_txq_map(struct mlx5e_channel *c,
910 int num_channels)
911{
912 int i;
913
914 for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
915 c->tc_to_txq_map[i] = c->ix + i * num_channels;
916}
917
f62b8bb8
AV		 918static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
919 struct mlx5e_channel_param *cparam,
920 struct mlx5e_channel **cp)
921{
922 struct net_device *netdev = priv->netdev;
923 int cpu = mlx5e_get_cpu(priv, ix);
924 struct mlx5e_channel *c;
925 int err;
926
927 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
928 if (!c)
929 return -ENOMEM;
930
931 c->priv = priv;
932 c->ix = ix;
933 c->cpu = cpu;
934 c->pdev = &priv->mdev->pdev->dev;
935 c->netdev = priv->netdev;
936 c->mkey_be = cpu_to_be32(priv->mr.key);
937 c->num_tc = priv->num_tc;
938
03289b88
SM		 939 mlx5e_build_tc_to_txq_map(c, priv->params.num_channels);
940
f62b8bb8
AV		 941 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
942
943 err = mlx5e_open_tx_cqs(c, cparam);
944 if (err)
945 goto err_napi_del;
946
947 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
948 priv->params.rx_cq_moderation_usec,
949 priv->params.rx_cq_moderation_pkts);
950 if (err)
951 goto err_close_tx_cqs;
f62b8bb8
AV		 952
953 napi_enable(&c->napi);
954
955 err = mlx5e_open_sqs(c, cparam);
956 if (err)
957 goto err_disable_napi;
958
959 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
960 if (err)
961 goto err_close_sqs;
962
963 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
964 *cp = c;
965
966 return 0;
967
968err_close_sqs:
969 mlx5e_close_sqs(c);
970
971err_disable_napi:
972 napi_disable(&c->napi);
973 mlx5e_close_cq(&c->rq.cq);
974
975err_close_tx_cqs:
976 mlx5e_close_tx_cqs(c);
977
978err_napi_del:
979 netif_napi_del(&c->napi);
980 kfree(c);
981
982 return err;
983}
984
985static void mlx5e_close_channel(struct mlx5e_channel *c)
986{
987 mlx5e_close_rq(&c->rq);
988 mlx5e_close_sqs(c);
989 napi_disable(&c->napi);
990 mlx5e_close_cq(&c->rq.cq);
991 mlx5e_close_tx_cqs(c);
992 netif_napi_del(&c->napi);
993 kfree(c);
994}
995
996static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
997 struct mlx5e_rq_param *param)
998{
999 void *rqc = param->rqc;
1000 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1001
1002 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1003 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1004 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1005 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1006 MLX5_SET(wq, wq, pd, priv->pdn);
1007
311c7c71 1008 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1009 param->wq.linear = 1;
1010}
1011
1012static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1013 struct mlx5e_sq_param *param)
1014{
1015 void *sqc = param->sqc;
1016 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1017
1018 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1019 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1020 MLX5_SET(wq, wq, pd, priv->pdn);
1021
311c7c71 1022 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1023}
1024
1025static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1026 struct mlx5e_cq_param *param)
1027{
1028 void *cqc = param->cqc;
1029
1030 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1031}
1032
1033static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1034 struct mlx5e_cq_param *param)
1035{
1036 void *cqc = param->cqc;
1037
1038 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1039
1040 mlx5e_build_common_cq_param(priv, param);
1041}
1042
1043static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1044 struct mlx5e_cq_param *param)
1045{
1046 void *cqc = param->cqc;
1047
1048 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1049
1050 mlx5e_build_common_cq_param(priv, param);
1051}
1052
1053static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
1054 struct mlx5e_channel_param *cparam)
1055{
1056 memset(cparam, 0, sizeof(*cparam));
1057
1058 mlx5e_build_rq_param(priv, &cparam->rq);
1059 mlx5e_build_sq_param(priv, &cparam->sq);
1060 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1061 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1062}
1063
1064static int mlx5e_open_channels(struct mlx5e_priv *priv)
1065{
1066 struct mlx5e_channel_param cparam;
03289b88 1067 int err = -ENOMEM;
f62b8bb8
AV		 1068 int i;
1069 int j;
1070
1071 priv->channel = kcalloc(priv->params.num_channels,
1072 sizeof(struct mlx5e_channel *), GFP_KERNEL);
03289b88
SM		 1073
1074 priv->txq_to_sq_map = kcalloc(priv->params.num_channels * priv->num_tc,
1075 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1076
1077 if (!priv->channel || !priv->txq_to_sq_map)
1078 goto err_free_txq_to_sq_map;
f62b8bb8
AV		 1079
1080 mlx5e_build_channel_param(priv, &cparam);
1081 for (i = 0; i < priv->params.num_channels; i++) {
1082 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1083 if (err)
1084 goto err_close_channels;
1085 }
1086
1087 for (j = 0; j < priv->params.num_channels; j++) {
1088 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1089 if (err)
1090 goto err_close_channels;
1091 }
1092
1093 return 0;
1094
1095err_close_channels:
1096 for (i--; i >= 0; i--)
1097 mlx5e_close_channel(priv->channel[i]);
1098
03289b88
SM		 1099err_free_txq_to_sq_map:
1100 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1101 kfree(priv->channel);
1102
1103 return err;
1104}
1105
1106static void mlx5e_close_channels(struct mlx5e_priv *priv)
1107{
1108 int i;
1109
1110 for (i = 0; i < priv->params.num_channels; i++)
1111 mlx5e_close_channel(priv->channel[i]);
1112
03289b88 1113 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1114 kfree(priv->channel);
1115}
1116
1117static int mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1118{
1119 struct mlx5_core_dev *mdev = priv->mdev;
1120 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1121 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1122
1123 memset(in, 0, sizeof(in));
1124
1125 MLX5_SET(tisc, tisc, prio, tc);
3191e05f 1126 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
f62b8bb8 1127
7db22ffb 1128 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
f62b8bb8
AV		 1129}
1130
1131static void mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1132{
7db22ffb 1133 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
f62b8bb8
AV		 1134}
1135
1136static int mlx5e_open_tises(struct mlx5e_priv *priv)
1137{
1138 int num_tc = priv->num_tc;
1139 int err;
1140 int tc;
1141
1142 for (tc = 0; tc < num_tc; tc++) {
1143 err = mlx5e_open_tis(priv, tc);
1144 if (err)
1145 goto err_close_tises;
1146 }
1147
1148 return 0;
1149
1150err_close_tises:
1151 for (tc--; tc >= 0; tc--)
1152 mlx5e_close_tis(priv, tc);
1153
1154 return err;
1155}
1156
1157static void mlx5e_close_tises(struct mlx5e_priv *priv)
1158{
1159 int num_tc = priv->num_tc;
1160 int tc;
1161
1162 for (tc = 0; tc < num_tc; tc++)
1163 mlx5e_close_tis(priv, tc);
1164}
1165
2be6967c
SM		 1166static int mlx5e_rx_hash_fn(int hfunc)
1167{
1168 return (hfunc == ETH_RSS_HASH_TOP) ?
1169 MLX5_RX_HASH_FN_TOEPLITZ :
1170 MLX5_RX_HASH_FN_INVERTED_XOR8;
1171}
1172
1173static int mlx5e_bits_invert(unsigned long a, int size)
1174{
1175 int inv = 0;
1176 int i;
1177
1178 for (i = 0; i < size; i++)
1179 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1180
1181 return inv;
1182}
1183
f62b8bb8
AV		 1184static int mlx5e_open_rqt(struct mlx5e_priv *priv)
1185{
1186 struct mlx5_core_dev *mdev = priv->mdev;
1187 u32 *in;
1188 u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1189 void *rqtc;
1190 int inlen;
1191 int err;
2be6967c
SM		 1192 int log_tbl_sz = priv->params.rx_hash_log_tbl_sz;
1193 int sz = 1 << log_tbl_sz;
f62b8bb8
AV		 1194 int i;
1195
f62b8bb8
AV		 1196 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1197 in = mlx5_vzalloc(inlen);
1198 if (!in)
1199 return -ENOMEM;
1200
1201 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1202
1203 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1204 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1205
1206 for (i = 0; i < sz; i++) {
2be6967c
SM		 1207 int ix = i;
1208
1209 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1210 ix = mlx5e_bits_invert(i, log_tbl_sz);
f62b8bb8 1211
2be6967c 1212 ix = ix % priv->params.num_channels;
f62b8bb8
AV		 1213 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1214 }
1215
1216 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1217
1218 memset(out, 0, sizeof(out));
1219 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1220 if (!err)
1221 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1222
1223 kvfree(in);
1224
1225 return err;
1226}
1227
1228static void mlx5e_close_rqt(struct mlx5e_priv *priv)
1229{
1230 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1231 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1232
1233 memset(in, 0, sizeof(in));
1234
1235 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1236 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1237
1238 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1239 sizeof(out));
1240}
1241
1242static void mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, int tt)
1243{
1244 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1245
3191e05f
AS		 1246 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1247
f62b8bb8
AV		 1248#define ROUGH_MAX_L2_L3_HDR_SZ 256
1249
1250#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1251 MLX5_HASH_FIELD_SEL_DST_IP)
1252
1253#define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
1254 MLX5_HASH_FIELD_SEL_DST_IP |\
1255 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1256 MLX5_HASH_FIELD_SEL_L4_DPORT)
1257
1258 if (priv->params.lro_en) {
1259 MLX5_SET(tirc, tirc, lro_enable_mask,
1260 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1261 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1262 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1263 (priv->params.lro_wqe_sz -
1264 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1265 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1266 MLX5_CAP_ETH(priv->mdev,
1267 lro_timer_supported_periods[3]));
1268 }
1269
1270 switch (tt) {
1271 case MLX5E_TT_ANY:
1272 MLX5_SET(tirc, tirc, disp_type,
1273 MLX5_TIRC_DISP_TYPE_DIRECT);
1274 MLX5_SET(tirc, tirc, inline_rqn,
1275 priv->channel[0]->rq.rqn);
1276 break;
1277 default:
1278 MLX5_SET(tirc, tirc, disp_type,
1279 MLX5_TIRC_DISP_TYPE_INDIRECT);
1280 MLX5_SET(tirc, tirc, indirect_table,
1281 priv->rqtn);
1282 MLX5_SET(tirc, tirc, rx_hash_fn,
2be6967c
SM		 1283 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1284 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1285 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1286 rx_hash_toeplitz_key);
1287 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1288 rx_hash_toeplitz_key);
1289
1290 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1291 netdev_rss_key_fill(rss_key, len);
1292 }
f62b8bb8
AV		 1293 break;
1294 }
1295
1296 switch (tt) {
1297 case MLX5E_TT_IPV4_TCP:
1298 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1299 MLX5_L3_PROT_TYPE_IPV4);
1300 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1301 MLX5_L4_PROT_TYPE_TCP);
1302 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1303 MLX5_HASH_ALL);
1304 break;
1305
1306 case MLX5E_TT_IPV6_TCP:
1307 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1308 MLX5_L3_PROT_TYPE_IPV6);
1309 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1310 MLX5_L4_PROT_TYPE_TCP);
1311 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1312 MLX5_HASH_ALL);
1313 break;
1314
1315 case MLX5E_TT_IPV4_UDP:
1316 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1317 MLX5_L3_PROT_TYPE_IPV4);
1318 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1319 MLX5_L4_PROT_TYPE_UDP);
1320 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1321 MLX5_HASH_ALL);
1322 break;
1323
1324 case MLX5E_TT_IPV6_UDP:
1325 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1326 MLX5_L3_PROT_TYPE_IPV6);
1327 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1328 MLX5_L4_PROT_TYPE_UDP);
1329 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1330 MLX5_HASH_ALL);
1331 break;
1332
1333 case MLX5E_TT_IPV4:
1334 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1335 MLX5_L3_PROT_TYPE_IPV4);
1336 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1337 MLX5_HASH_IP);
1338 break;
1339
1340 case MLX5E_TT_IPV6:
1341 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1342 MLX5_L3_PROT_TYPE_IPV6);
1343 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1344 MLX5_HASH_IP);
1345 break;
1346 }
1347}
1348
1349static int mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
1350{
1351 struct mlx5_core_dev *mdev = priv->mdev;
1352 u32 *in;
1353 void *tirc;
1354 int inlen;
1355 int err;
1356
1357 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1358 in = mlx5_vzalloc(inlen);
1359 if (!in)
1360 return -ENOMEM;
1361
1362 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1363
1364 mlx5e_build_tir_ctx(priv, tirc, tt);
1365
7db22ffb 1366 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
f62b8bb8
AV		 1367
1368 kvfree(in);
1369
1370 return err;
1371}
1372
1373static void mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
1374{
7db22ffb 1375 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
f62b8bb8
AV		 1376}
1377
1378static int mlx5e_open_tirs(struct mlx5e_priv *priv)
1379{
1380 int err;
1381 int i;
1382
1383 for (i = 0; i < MLX5E_NUM_TT; i++) {
1384 err = mlx5e_open_tir(priv, i);
1385 if (err)
1386 goto err_close_tirs;
1387 }
1388
1389 return 0;
1390
1391err_close_tirs:
1392 for (i--; i >= 0; i--)
1393 mlx5e_close_tir(priv, i);
1394
1395 return err;
1396}
1397
1398static void mlx5e_close_tirs(struct mlx5e_priv *priv)
1399{
1400 int i;
1401
1402 for (i = 0; i < MLX5E_NUM_TT; i++)
1403 mlx5e_close_tir(priv, i);
1404}
1405
facc9699 1406static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
f62b8bb8
AV		 1407{
1408 struct mlx5e_priv *priv = netdev_priv(netdev);
1409 struct mlx5_core_dev *mdev = priv->mdev;
facc9699
SM		 1410 int hw_mtu;
1411 int err;
1412
1413 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(netdev->mtu), 1);
1414 if (err)
1415 return err;
1416
1417 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1418
1419 if (MLX5E_HW2SW_MTU(hw_mtu) != netdev->mtu)
1420 netdev_warn(netdev, "%s: Port MTU %d is different than netdev mtu %d\n",
1421 __func__, MLX5E_HW2SW_MTU(hw_mtu), netdev->mtu);
1422
1423 netdev->mtu = MLX5E_HW2SW_MTU(hw_mtu);
1424 return 0;
1425}
1426
1427int mlx5e_open_locked(struct net_device *netdev)
1428{
1429 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8
AV		 1430 int num_txqs;
1431 int err;
1432
03289b88 1433 num_txqs = priv->params.num_channels * priv->params.num_tc;
f62b8bb8
AV		 1434 netif_set_real_num_tx_queues(netdev, num_txqs);
1435 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1436
facc9699
SM		 1437 err = mlx5e_set_dev_port_mtu(netdev);
1438 if (err)
f62b8bb8 1439 return err;
f62b8bb8
AV		 1440
1441 err = mlx5e_open_tises(priv);
1442 if (err) {
1443 netdev_err(netdev, "%s: mlx5e_open_tises failed, %d\n",
1444 __func__, err);
1445 return err;
1446 }
1447
1448 err = mlx5e_open_channels(priv);
1449 if (err) {
1450 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1451 __func__, err);
1452 goto err_close_tises;
1453 }
1454
1455 err = mlx5e_open_rqt(priv);
1456 if (err) {
1457 netdev_err(netdev, "%s: mlx5e_open_rqt failed, %d\n",
1458 __func__, err);
1459 goto err_close_channels;
1460 }
1461
1462 err = mlx5e_open_tirs(priv);
1463 if (err) {
1464 netdev_err(netdev, "%s: mlx5e_open_tir failed, %d\n",
1465 __func__, err);
1466 goto err_close_rqls;
1467 }
1468
1469 err = mlx5e_open_flow_table(priv);
1470 if (err) {
1471 netdev_err(netdev, "%s: mlx5e_open_flow_table failed, %d\n",
1472 __func__, err);
1473 goto err_close_tirs;
1474 }
1475
1476 err = mlx5e_add_all_vlan_rules(priv);
1477 if (err) {
1478 netdev_err(netdev, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
1479 __func__, err);
1480 goto err_close_flow_table;
1481 }
1482
1483 mlx5e_init_eth_addr(priv);
1484
1485 set_bit(MLX5E_STATE_OPENED, &priv->state);
1486
1487 mlx5e_update_carrier(priv);
1488 mlx5e_set_rx_mode_core(priv);
1489
1490 schedule_delayed_work(&priv->update_stats_work, 0);
1491 return 0;
1492
1493err_close_flow_table:
1494 mlx5e_close_flow_table(priv);
1495
1496err_close_tirs:
1497 mlx5e_close_tirs(priv);
1498
1499err_close_rqls:
1500 mlx5e_close_rqt(priv);
1501
1502err_close_channels:
1503 mlx5e_close_channels(priv);
1504
1505err_close_tises:
1506 mlx5e_close_tises(priv);
1507
1508 return err;
1509}
1510
1511static int mlx5e_open(struct net_device *netdev)
1512{
1513 struct mlx5e_priv *priv = netdev_priv(netdev);
1514 int err;
1515
1516 mutex_lock(&priv->state_lock);
1517 err = mlx5e_open_locked(netdev);
1518 mutex_unlock(&priv->state_lock);
1519
1520 return err;
1521}
1522
1523int mlx5e_close_locked(struct net_device *netdev)
1524{
1525 struct mlx5e_priv *priv = netdev_priv(netdev);
1526
1527 clear_bit(MLX5E_STATE_OPENED, &priv->state);
1528
1529 mlx5e_set_rx_mode_core(priv);
1530 mlx5e_del_all_vlan_rules(priv);
1531 netif_carrier_off(priv->netdev);
1532 mlx5e_close_flow_table(priv);
1533 mlx5e_close_tirs(priv);
1534 mlx5e_close_rqt(priv);
1535 mlx5e_close_channels(priv);
1536 mlx5e_close_tises(priv);
1537
1538 return 0;
1539}
1540
1541static int mlx5e_close(struct net_device *netdev)
1542{
1543 struct mlx5e_priv *priv = netdev_priv(netdev);
1544 int err;
1545
1546 mutex_lock(&priv->state_lock);
1547 err = mlx5e_close_locked(netdev);
1548 mutex_unlock(&priv->state_lock);
1549
1550 return err;
1551}
1552
1553int mlx5e_update_priv_params(struct mlx5e_priv *priv,
1554 struct mlx5e_params *new_params)
1555{
1556 int err = 0;
1557 int was_opened;
1558
1559 WARN_ON(!mutex_is_locked(&priv->state_lock));
1560
1561 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1562 if (was_opened)
1563 mlx5e_close_locked(priv->netdev);
1564
1565 priv->params = *new_params;
1566
1567 if (was_opened)
1568 err = mlx5e_open_locked(priv->netdev);
1569
1570 return err;
1571}
1572
1573static struct rtnl_link_stats64 *
1574mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
1575{
1576 struct mlx5e_priv *priv = netdev_priv(dev);
1577 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
1578
1579 stats->rx_packets = vstats->rx_packets;
1580 stats->rx_bytes = vstats->rx_bytes;
1581 stats->tx_packets = vstats->tx_packets;
1582 stats->tx_bytes = vstats->tx_bytes;
1583 stats->multicast = vstats->rx_multicast_packets +
1584 vstats->tx_multicast_packets;
1585 stats->tx_errors = vstats->tx_error_packets;
1586 stats->rx_errors = vstats->rx_error_packets;
1587 stats->tx_dropped = vstats->tx_queue_dropped;
1588 stats->rx_crc_errors = 0;
1589 stats->rx_length_errors = 0;
1590
1591 return stats;
1592}
1593
1594static void mlx5e_set_rx_mode(struct net_device *dev)
1595{
1596 struct mlx5e_priv *priv = netdev_priv(dev);
1597
1598 schedule_work(&priv->set_rx_mode_work);
1599}
1600
1601static int mlx5e_set_mac(struct net_device *netdev, void *addr)
1602{
1603 struct mlx5e_priv *priv = netdev_priv(netdev);
1604 struct sockaddr *saddr = addr;
1605
1606 if (!is_valid_ether_addr(saddr->sa_data))
1607 return -EADDRNOTAVAIL;
1608
1609 netif_addr_lock_bh(netdev);
1610 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
1611 netif_addr_unlock_bh(netdev);
1612
1613 schedule_work(&priv->set_rx_mode_work);
1614
1615 return 0;
1616}
1617
1618static int mlx5e_set_features(struct net_device *netdev,
1619 netdev_features_t features)
1620{
1621 struct mlx5e_priv *priv = netdev_priv(netdev);
1622 netdev_features_t changes = features ^ netdev->features;
1623 struct mlx5e_params new_params;
1624 bool update_params = false;
1625
1626 mutex_lock(&priv->state_lock);
1627 new_params = priv->params;
1628
1629 if (changes & NETIF_F_LRO) {
1630 new_params.lro_en = !!(features & NETIF_F_LRO);
1631 update_params = true;
1632 }
1633
1634 if (update_params)
1635 mlx5e_update_priv_params(priv, &new_params);
1636
1637 if (changes & NETIF_F_HW_VLAN_CTAG_FILTER) {
1638 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
1639 mlx5e_enable_vlan_filter(priv);
1640 else
1641 mlx5e_disable_vlan_filter(priv);
1642 }
1643
1644 mutex_unlock(&priv->state_lock);
1645
1646 return 0;
1647}
1648
1649static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
1650{
1651 struct mlx5e_priv *priv = netdev_priv(netdev);
1652 struct mlx5_core_dev *mdev = priv->mdev;
1653 int max_mtu;
facc9699 1654 int err;
f62b8bb8 1655
facc9699 1656 mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
f62b8bb8 1657
facc9699
SM		 1658 if (new_mtu > max_mtu) {
1659 netdev_err(netdev,
1660 "%s: Bad MTU (%d) > (%d) Max\n",
1661 __func__, new_mtu, max_mtu);
f62b8bb8
AV		 1662 return -EINVAL;
1663 }
1664
1665 mutex_lock(&priv->state_lock);
1666 netdev->mtu = new_mtu;
1667 err = mlx5e_update_priv_params(priv, &priv->params);
1668 mutex_unlock(&priv->state_lock);
1669
1670 return err;
1671}
1672
1673static struct net_device_ops mlx5e_netdev_ops = {
1674 .ndo_open = mlx5e_open,
1675 .ndo_stop = mlx5e_close,
1676 .ndo_start_xmit = mlx5e_xmit,
1677 .ndo_get_stats64 = mlx5e_get_stats,
1678 .ndo_set_rx_mode = mlx5e_set_rx_mode,
1679 .ndo_set_mac_address = mlx5e_set_mac,
1680 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
1681 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
1682 .ndo_set_features = mlx5e_set_features,
1683 .ndo_change_mtu = mlx5e_change_mtu,
1684};
1685
1686static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
1687{
1688 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
1689 return -ENOTSUPP;
1690 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
1691 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
1692 !MLX5_CAP_ETH(mdev, csum_cap) ||
1693 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
1694 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 1695 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
1696 MLX5_CAP_FLOWTABLE(mdev,
1697 flow_table_properties_nic_receive.max_ft_level)
1698 < 3) {
f62b8bb8
AV		 1699 mlx5_core_warn(mdev,
1700 "Not creating net device, some required device capabilities are missing\n");
1701 return -ENOTSUPP;
1702 }
1703 return 0;
1704}
1705
1706static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
1707 struct net_device *netdev,
1708 int num_comp_vectors)
1709{
1710 struct mlx5e_priv *priv = netdev_priv(netdev);
1711
1712 priv->params.log_sq_size =
1713 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
1714 priv->params.log_rq_size =
1715 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
1716 priv->params.rx_cq_moderation_usec =
1717 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
1718 priv->params.rx_cq_moderation_pkts =
1719 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
1720 priv->params.tx_cq_moderation_usec =
1721 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
1722 priv->params.tx_cq_moderation_pkts =
1723 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
1724 priv->params.min_rx_wqes =
1725 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
1726 priv->params.rx_hash_log_tbl_sz =
1727 (order_base_2(num_comp_vectors) >
1728 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
1729 order_base_2(num_comp_vectors) :
1730 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
1731 priv->params.num_tc = 1;
1732 priv->params.default_vlan_prio = 0;
2be6967c 1733 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8
AV		 1734
1735 priv->params.lro_en = false && !!MLX5_CAP_ETH(priv->mdev, lro_cap);
1736 priv->params.lro_wqe_sz =
1737 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
1738
1739 priv->mdev = mdev;
1740 priv->netdev = netdev;
1741 priv->params.num_channels = num_comp_vectors;
f62b8bb8
AV		 1742 priv->num_tc = priv->params.num_tc;
1743 priv->default_vlan_prio = priv->params.default_vlan_prio;
1744
1745 spin_lock_init(&priv->async_events_spinlock);
1746 mutex_init(&priv->state_lock);
1747
1748 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
1749 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
1750 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
1751}
1752
1753static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
1754{
1755 struct mlx5e_priv *priv = netdev_priv(netdev);
1756
d18a9470 1757 mlx5_query_nic_vport_mac_address(priv->mdev, netdev->dev_addr);
f62b8bb8
AV		 1758}
1759
1760static void mlx5e_build_netdev(struct net_device *netdev)
1761{
1762 struct mlx5e_priv *priv = netdev_priv(netdev);
1763 struct mlx5_core_dev *mdev = priv->mdev;
1764
1765 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
1766
1767 if (priv->num_tc > 1) {
1768 mlx5e_netdev_ops.ndo_select_queue = mlx5e_select_queue;
f62b8bb8
AV		 1769 }
1770
1771 netdev->netdev_ops = &mlx5e_netdev_ops;
1772 netdev->watchdog_timeo = 15 * HZ;
1773
1774 netdev->ethtool_ops = &mlx5e_ethtool_ops;
1775
12be4b21 1776 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 1777 netdev->vlan_features |= NETIF_F_IP_CSUM;
1778 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1779 netdev->vlan_features |= NETIF_F_GRO;
1780 netdev->vlan_features |= NETIF_F_TSO;
1781 netdev->vlan_features |= NETIF_F_TSO6;
1782 netdev->vlan_features |= NETIF_F_RXCSUM;
1783 netdev->vlan_features |= NETIF_F_RXHASH;
1784
1785 if (!!MLX5_CAP_ETH(mdev, lro_cap))
1786 netdev->vlan_features |= NETIF_F_LRO;
1787
1788 netdev->hw_features = netdev->vlan_features;
f62b8bb8
AV		 1789 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1790 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1791
1792 netdev->features = netdev->hw_features;
1793 if (!priv->params.lro_en)
1794 netdev->features &= ~NETIF_F_LRO;
1795
1796 netdev->features |= NETIF_F_HIGHDMA;
1797
1798 netdev->priv_flags |= IFF_UNICAST_FLT;
1799
1800 mlx5e_set_netdev_dev_addr(netdev);
1801}
1802
1803static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
1804 struct mlx5_core_mr *mr)
1805{
1806 struct mlx5_core_dev *mdev = priv->mdev;
1807 struct mlx5_create_mkey_mbox_in *in;
1808 int err;
1809
1810 in = mlx5_vzalloc(sizeof(*in));
1811 if (!in)
1812 return -ENOMEM;
1813
1814 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
1815 MLX5_PERM_LOCAL_READ |
1816 MLX5_ACCESS_MODE_PA;
1817 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
1818 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
1819
1820 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
1821 NULL);
1822
1823 kvfree(in);
1824
1825 return err;
1826}
1827
1828static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
1829{
1830 struct net_device *netdev;
1831 struct mlx5e_priv *priv;
1832 int ncv = mdev->priv.eq_table.num_comp_vectors;
1833 int err;
1834
1835 if (mlx5e_check_required_hca_cap(mdev))
1836 return NULL;
1837
03289b88 1838 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), ncv, ncv);
f62b8bb8
AV		 1839 if (!netdev) {
1840 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
1841 return NULL;
1842 }
1843
1844 mlx5e_build_netdev_priv(mdev, netdev, ncv);
1845 mlx5e_build_netdev(netdev);
1846
1847 netif_carrier_off(netdev);
1848
1849 priv = netdev_priv(netdev);
1850
1851 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
1852 if (err) {
1853 netdev_err(netdev, "%s: mlx5_alloc_map_uar failed, %d\n",
1854 __func__, err);
1855 goto err_free_netdev;
1856 }
1857
1858 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
1859 if (err) {
1860 netdev_err(netdev, "%s: mlx5_core_alloc_pd failed, %d\n",
1861 __func__, err);
1862 goto err_unmap_free_uar;
1863 }
1864
3191e05f
AS		 1865 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
1866 if (err) {
1867 netdev_err(netdev, "%s: mlx5_alloc_transport_domain failed, %d\n",
1868 __func__, err);
1869 goto err_dealloc_pd;
1870 }
1871
f62b8bb8
AV		 1872 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
1873 if (err) {
1874 netdev_err(netdev, "%s: mlx5e_create_mkey failed, %d\n",
1875 __func__, err);
3191e05f 1876 goto err_dealloc_transport_domain;
f62b8bb8
AV		 1877 }
1878
1879 err = register_netdev(netdev);
1880 if (err) {
1881 netdev_err(netdev, "%s: register_netdev failed, %d\n",
1882 __func__, err);
1883 goto err_destroy_mkey;
1884 }
1885
1886 mlx5e_enable_async_events(priv);
1887
1888 return priv;
1889
1890err_destroy_mkey:
1891 mlx5_core_destroy_mkey(mdev, &priv->mr);
1892
3191e05f
AS		 1893err_dealloc_transport_domain:
1894 mlx5_dealloc_transport_domain(mdev, priv->tdn);
1895
f62b8bb8
AV		 1896err_dealloc_pd:
1897 mlx5_core_dealloc_pd(mdev, priv->pdn);
1898
1899err_unmap_free_uar:
1900 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
1901
1902err_free_netdev:
1903 free_netdev(netdev);
1904
1905 return NULL;
1906}
1907
1908static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
1909{
1910 struct mlx5e_priv *priv = vpriv;
1911 struct net_device *netdev = priv->netdev;
1912
1913 unregister_netdev(netdev);
1914 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3191e05f 1915 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
f62b8bb8
AV		 1916 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
1917 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
1918 mlx5e_disable_async_events(priv);
1919 flush_scheduled_work();
1920 free_netdev(netdev);
1921}
1922
1923static void *mlx5e_get_netdev(void *vpriv)
1924{
1925 struct mlx5e_priv *priv = vpriv;
1926
1927 return priv->netdev;
1928}
1929
1930static struct mlx5_interface mlx5e_interface = {
1931 .add = mlx5e_create_netdev,
1932 .remove = mlx5e_destroy_netdev,
1933 .event = mlx5e_async_event,
1934 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
1935 .get_dev = mlx5e_get_netdev,
1936};
1937
1938void mlx5e_init(void)
1939{
1940 mlx5_register_interface(&mlx5e_interface);
1941}
1942
1943void mlx5e_cleanup(void)
1944{
1945 mlx5_unregister_interface(&mlx5e_interface);
1946}
Linux 6.x block layer and io_uring tree(s)