Commit | Line | Data |
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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
86994156 | 37 | #include <linux/bpf.h> |
1d447a39 | 38 | #include "eswitch.h" |
f62b8bb8 | 39 | #include "en.h" |
e8f887ac | 40 | #include "en_tc.h" |
1d447a39 | 41 | #include "en_rep.h" |
547eede0 | 42 | #include "en_accel/ipsec.h" |
899a59d3 IT |
43 | #include "en_accel/ipsec_rxtx.h" |
44 | #include "accel/ipsec.h" | |
b3f63c3d | 45 | #include "vxlan.h" |
f62b8bb8 AV |
46 | |
47 | struct mlx5e_rq_param { | |
cb3c7fd4 GR |
48 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; |
49 | struct mlx5_wq_param wq; | |
f62b8bb8 AV |
50 | }; |
51 | ||
52 | struct mlx5e_sq_param { | |
53 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
54 | struct mlx5_wq_param wq; | |
55 | }; | |
56 | ||
57 | struct mlx5e_cq_param { | |
58 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
59 | struct mlx5_wq_param wq; | |
60 | u16 eq_ix; | |
9908aa29 | 61 | u8 cq_period_mode; |
f62b8bb8 AV |
62 | }; |
63 | ||
64 | struct mlx5e_channel_param { | |
65 | struct mlx5e_rq_param rq; | |
66 | struct mlx5e_sq_param sq; | |
b5503b99 | 67 | struct mlx5e_sq_param xdp_sq; |
d3c9bc27 | 68 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
69 | struct mlx5e_cq_param rx_cq; |
70 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 71 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
72 | }; |
73 | ||
2fc4bfb7 SM |
74 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
75 | { | |
76 | return MLX5_CAP_GEN(mdev, striding_rq) && | |
77 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && | |
78 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
79 | } | |
80 | ||
696a97cf EE |
81 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
82 | struct mlx5e_params *params, u8 rq_type) | |
2fc4bfb7 | 83 | { |
6a9764ef SM |
84 | params->rq_wq_type = rq_type; |
85 | params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
86 | switch (params->rq_wq_type) { | |
2fc4bfb7 | 87 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
6a9764ef | 88 | params->log_rq_size = is_kdump_kernel() ? |
b4e029da KH |
89 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW : |
90 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | |
696a97cf EE |
91 | params->mpwqe_log_stride_sz = MLX5E_MPWQE_STRIDE_SZ(mdev, |
92 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
6a9764ef SM |
93 | params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - |
94 | params->mpwqe_log_stride_sz; | |
2fc4bfb7 SM |
95 | break; |
96 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
6a9764ef | 97 | params->log_rq_size = is_kdump_kernel() ? |
b4e029da KH |
98 | MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE : |
99 | MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
bce2b2bf TT |
100 | params->rq_headroom = params->xdp_prog ? |
101 | XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM; | |
102 | params->rq_headroom += NET_IP_ALIGN; | |
4078e637 TT |
103 | |
104 | /* Extra room needed for build_skb */ | |
bce2b2bf | 105 | params->lro_wqe_sz -= params->rq_headroom + |
4078e637 | 106 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
2fc4bfb7 | 107 | } |
2fc4bfb7 | 108 | |
6a9764ef SM |
109 | mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", |
110 | params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
111 | BIT(params->log_rq_size), | |
112 | BIT(params->mpwqe_log_stride_sz), | |
113 | MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)); | |
2fc4bfb7 SM |
114 | } |
115 | ||
696a97cf EE |
116 | static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, |
117 | struct mlx5e_params *params) | |
2fc4bfb7 | 118 | { |
6a9764ef | 119 | u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) && |
899a59d3 | 120 | !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ? |
2fc4bfb7 SM |
121 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
122 | MLX5_WQ_TYPE_LINKED_LIST; | |
696a97cf | 123 | mlx5e_init_rq_type_params(mdev, params, rq_type); |
2fc4bfb7 SM |
124 | } |
125 | ||
f62b8bb8 AV |
126 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) |
127 | { | |
128 | struct mlx5_core_dev *mdev = priv->mdev; | |
129 | u8 port_state; | |
130 | ||
131 | port_state = mlx5_query_vport_state(mdev, | |
e53eef63 OG |
132 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, |
133 | 0); | |
f62b8bb8 | 134 | |
87424ad5 SD |
135 | if (port_state == VPORT_STATE_UP) { |
136 | netdev_info(priv->netdev, "Link up\n"); | |
f62b8bb8 | 137 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
138 | } else { |
139 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 140 | netif_carrier_off(priv->netdev); |
87424ad5 | 141 | } |
f62b8bb8 AV |
142 | } |
143 | ||
144 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
145 | { | |
146 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
147 | update_carrier_work); | |
148 | ||
149 | mutex_lock(&priv->state_lock); | |
150 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
7ca42c80 ES |
151 | if (priv->profile->update_carrier) |
152 | priv->profile->update_carrier(priv); | |
f62b8bb8 AV |
153 | mutex_unlock(&priv->state_lock); |
154 | } | |
155 | ||
3947ca18 DJ |
156 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
157 | { | |
158 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
159 | tx_timeout_work); | |
160 | int err; | |
161 | ||
162 | rtnl_lock(); | |
163 | mutex_lock(&priv->state_lock); | |
164 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
165 | goto unlock; | |
166 | mlx5e_close_locked(priv->netdev); | |
167 | err = mlx5e_open_locked(priv->netdev); | |
168 | if (err) | |
169 | netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
170 | err); | |
171 | unlock: | |
172 | mutex_unlock(&priv->state_lock); | |
173 | rtnl_unlock(); | |
174 | } | |
175 | ||
9218b44d | 176 | static void mlx5e_update_sw_counters(struct mlx5e_priv *priv) |
f62b8bb8 | 177 | { |
1510d728 | 178 | struct mlx5e_sw_stats temp, *s = &temp; |
f62b8bb8 AV |
179 | struct mlx5e_rq_stats *rq_stats; |
180 | struct mlx5e_sq_stats *sq_stats; | |
f62b8bb8 AV |
181 | int i, j; |
182 | ||
9218b44d | 183 | memset(s, 0, sizeof(*s)); |
ff9c852f SM |
184 | for (i = 0; i < priv->channels.num; i++) { |
185 | struct mlx5e_channel *c = priv->channels.c[i]; | |
186 | ||
187 | rq_stats = &c->rq.stats; | |
f62b8bb8 | 188 | |
faf4478b GP |
189 | s->rx_packets += rq_stats->packets; |
190 | s->rx_bytes += rq_stats->bytes; | |
bfe6d8d1 GP |
191 | s->rx_lro_packets += rq_stats->lro_packets; |
192 | s->rx_lro_bytes += rq_stats->lro_bytes; | |
f24686e8 | 193 | s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets; |
f62b8bb8 | 194 | s->rx_csum_none += rq_stats->csum_none; |
bfe6d8d1 | 195 | s->rx_csum_complete += rq_stats->csum_complete; |
603e1f5b | 196 | s->rx_csum_unnecessary += rq_stats->csum_unnecessary; |
bfe6d8d1 | 197 | s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; |
86994156 | 198 | s->rx_xdp_drop += rq_stats->xdp_drop; |
b5503b99 SM |
199 | s->rx_xdp_tx += rq_stats->xdp_tx; |
200 | s->rx_xdp_tx_full += rq_stats->xdp_tx_full; | |
f62b8bb8 | 201 | s->rx_wqe_err += rq_stats->wqe_err; |
461017cb | 202 | s->rx_mpwqe_filler += rq_stats->mpwqe_filler; |
54984407 | 203 | s->rx_buff_alloc_err += rq_stats->buff_alloc_err; |
7219ab34 TT |
204 | s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; |
205 | s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; | |
accd5883 | 206 | s->rx_page_reuse += rq_stats->page_reuse; |
4415a031 TT |
207 | s->rx_cache_reuse += rq_stats->cache_reuse; |
208 | s->rx_cache_full += rq_stats->cache_full; | |
209 | s->rx_cache_empty += rq_stats->cache_empty; | |
210 | s->rx_cache_busy += rq_stats->cache_busy; | |
70871f1e | 211 | s->rx_cache_waive += rq_stats->cache_waive; |
f62b8bb8 | 212 | |
6a9764ef | 213 | for (j = 0; j < priv->channels.params.num_tc; j++) { |
ff9c852f | 214 | sq_stats = &c->sq[j].stats; |
f62b8bb8 | 215 | |
faf4478b GP |
216 | s->tx_packets += sq_stats->packets; |
217 | s->tx_bytes += sq_stats->bytes; | |
bfe6d8d1 GP |
218 | s->tx_tso_packets += sq_stats->tso_packets; |
219 | s->tx_tso_bytes += sq_stats->tso_bytes; | |
220 | s->tx_tso_inner_packets += sq_stats->tso_inner_packets; | |
221 | s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f24686e8 | 222 | s->tx_added_vlan_packets += sq_stats->added_vlan_packets; |
f62b8bb8 AV |
223 | s->tx_queue_stopped += sq_stats->stopped; |
224 | s->tx_queue_wake += sq_stats->wake; | |
225 | s->tx_queue_dropped += sq_stats->dropped; | |
c8cf78fe | 226 | s->tx_xmit_more += sq_stats->xmit_more; |
bfe6d8d1 | 227 | s->tx_csum_partial_inner += sq_stats->csum_partial_inner; |
603e1f5b GP |
228 | s->tx_csum_none += sq_stats->csum_none; |
229 | s->tx_csum_partial += sq_stats->csum_partial; | |
f62b8bb8 AV |
230 | } |
231 | } | |
232 | ||
bfe6d8d1 | 233 | s->link_down_events_phy = MLX5_GET(ppcnt_reg, |
121fcdc8 GP |
234 | priv->stats.pport.phy_counters, |
235 | counter_set.phys_layer_cntrs.link_down_events); | |
1510d728 | 236 | memcpy(&priv->stats.sw, s, sizeof(*s)); |
9218b44d GP |
237 | } |
238 | ||
239 | static void mlx5e_update_vport_counters(struct mlx5e_priv *priv) | |
240 | { | |
241 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
242 | u32 *out = (u32 *)priv->stats.vport.query_vport_out; | |
c4f287c4 | 243 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0}; |
9218b44d GP |
244 | struct mlx5_core_dev *mdev = priv->mdev; |
245 | ||
f62b8bb8 AV |
246 | MLX5_SET(query_vport_counter_in, in, opcode, |
247 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
248 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
249 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
250 | ||
9218b44d GP |
251 | mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); |
252 | } | |
253 | ||
3834a5e6 | 254 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full) |
9218b44d GP |
255 | { |
256 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
257 | struct mlx5_core_dev *mdev = priv->mdev; | |
0883b4f4 | 258 | u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0}; |
9218b44d | 259 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); |
cf678570 | 260 | int prio; |
9218b44d | 261 | void *out; |
f62b8bb8 | 262 | |
9218b44d | 263 | MLX5_SET(ppcnt_reg, in, local_port, 1); |
f62b8bb8 | 264 | |
9218b44d GP |
265 | out = pstats->IEEE_802_3_counters; |
266 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
267 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
f62b8bb8 | 268 | |
3834a5e6 GP |
269 | if (!full) |
270 | return; | |
271 | ||
9218b44d GP |
272 | out = pstats->RFC_2863_counters; |
273 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
274 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
275 | ||
276 | out = pstats->RFC_2819_counters; | |
277 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
278 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
593cf338 | 279 | |
121fcdc8 GP |
280 | out = pstats->phy_counters; |
281 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); | |
282 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
283 | ||
5db0a4f6 GP |
284 | if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) { |
285 | out = pstats->phy_statistical_counters; | |
286 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP); | |
287 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
288 | } | |
289 | ||
068aef33 GP |
290 | if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) { |
291 | out = pstats->eth_ext_counters; | |
292 | MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP); | |
5db0a4f6 GP |
293 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); |
294 | } | |
295 | ||
cf678570 GP |
296 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); |
297 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { | |
298 | out = pstats->per_prio_counters[prio]; | |
299 | MLX5_SET(ppcnt_reg, in, prio_tc, prio); | |
300 | mlx5_core_access_reg(mdev, in, sz, out, sz, | |
301 | MLX5_REG_PPCNT, 0, 0); | |
302 | } | |
9218b44d GP |
303 | } |
304 | ||
305 | static void mlx5e_update_q_counter(struct mlx5e_priv *priv) | |
306 | { | |
307 | struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; | |
432609a4 GP |
308 | u32 out[MLX5_ST_SZ_DW(query_q_counter_out)]; |
309 | int err; | |
9218b44d GP |
310 | |
311 | if (!priv->q_counter) | |
312 | return; | |
313 | ||
432609a4 GP |
314 | err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out)); |
315 | if (err) | |
316 | return; | |
317 | ||
318 | qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer); | |
9218b44d GP |
319 | } |
320 | ||
0f7f3481 GP |
321 | static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv) |
322 | { | |
323 | struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie; | |
324 | struct mlx5_core_dev *mdev = priv->mdev; | |
0883b4f4 | 325 | u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0}; |
0f7f3481 GP |
326 | int sz = MLX5_ST_SZ_BYTES(mpcnt_reg); |
327 | void *out; | |
0f7f3481 GP |
328 | |
329 | if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group)) | |
330 | return; | |
331 | ||
0f7f3481 GP |
332 | out = pcie_stats->pcie_perf_counters; |
333 | MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP); | |
334 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0); | |
0f7f3481 GP |
335 | } |
336 | ||
3834a5e6 | 337 | void mlx5e_update_stats(struct mlx5e_priv *priv, bool full) |
9218b44d | 338 | { |
164f16f7 | 339 | if (full) { |
3834a5e6 | 340 | mlx5e_update_pcie_counters(priv); |
164f16f7 IT |
341 | mlx5e_ipsec_update_stats(priv); |
342 | } | |
3834a5e6 | 343 | mlx5e_update_pport_counters(priv, full); |
3dd69e3d SM |
344 | mlx5e_update_vport_counters(priv); |
345 | mlx5e_update_q_counter(priv); | |
121fcdc8 | 346 | mlx5e_update_sw_counters(priv); |
f62b8bb8 AV |
347 | } |
348 | ||
3834a5e6 GP |
349 | static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv) |
350 | { | |
351 | mlx5e_update_stats(priv, false); | |
352 | } | |
353 | ||
cb67b832 | 354 | void mlx5e_update_stats_work(struct work_struct *work) |
f62b8bb8 AV |
355 | { |
356 | struct delayed_work *dwork = to_delayed_work(work); | |
357 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
358 | update_stats_work); | |
359 | mutex_lock(&priv->state_lock); | |
360 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
6bfd390b | 361 | priv->profile->update_stats(priv); |
7bb29755 MF |
362 | queue_delayed_work(priv->wq, dwork, |
363 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
364 | } |
365 | mutex_unlock(&priv->state_lock); | |
366 | } | |
367 | ||
daa21560 TT |
368 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
369 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 370 | { |
daa21560 TT |
371 | struct mlx5e_priv *priv = vpriv; |
372 | ||
e0f46eb9 | 373 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
374 | return; |
375 | ||
f62b8bb8 AV |
376 | switch (event) { |
377 | case MLX5_DEV_EVENT_PORT_UP: | |
378 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 379 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 | 380 | break; |
f62b8bb8 AV |
381 | default: |
382 | break; | |
383 | } | |
384 | } | |
385 | ||
f62b8bb8 AV |
386 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
387 | { | |
e0f46eb9 | 388 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
389 | } |
390 | ||
391 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
392 | { | |
e0f46eb9 | 393 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
78249c42 | 394 | synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
395 | } |
396 | ||
7e426671 TT |
397 | static inline int mlx5e_get_wqe_mtt_sz(void) |
398 | { | |
399 | /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes. | |
400 | * To avoid copying garbage after the mtt array, we allocate | |
401 | * a little more. | |
402 | */ | |
403 | return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64), | |
404 | MLX5_UMR_MTT_ALIGNMENT); | |
405 | } | |
406 | ||
31391048 SM |
407 | static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, |
408 | struct mlx5e_icosq *sq, | |
409 | struct mlx5e_umr_wqe *wqe, | |
410 | u16 ix) | |
7e426671 TT |
411 | { |
412 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
413 | struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl; | |
414 | struct mlx5_wqe_data_seg *dseg = &wqe->data; | |
21c59685 | 415 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix]; |
7e426671 TT |
416 | u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS); |
417 | u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix); | |
418 | ||
419 | cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) | | |
420 | ds_cnt); | |
421 | cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
422 | cseg->imm = rq->mkey_be; | |
423 | ||
424 | ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN; | |
31616255 | 425 | ucseg->xlt_octowords = |
7e426671 TT |
426 | cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE)); |
427 | ucseg->bsf_octowords = | |
428 | cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset)); | |
429 | ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE); | |
430 | ||
431 | dseg->lkey = sq->mkey_be; | |
432 | dseg->addr = cpu_to_be64(wi->umr.mtt_addr); | |
433 | } | |
434 | ||
435 | static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq, | |
436 | struct mlx5e_channel *c) | |
437 | { | |
438 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
439 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
440 | int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1; | |
441 | int i; | |
442 | ||
21c59685 | 443 | rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info), |
231243c8 | 444 | GFP_KERNEL, cpu_to_node(c->cpu)); |
21c59685 | 445 | if (!rq->mpwqe.info) |
7e426671 TT |
446 | goto err_out; |
447 | ||
448 | /* We allocate more than mtt_sz as we will align the pointer */ | |
231243c8 SM |
449 | rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL, |
450 | cpu_to_node(c->cpu)); | |
21c59685 | 451 | if (unlikely(!rq->mpwqe.mtt_no_align)) |
7e426671 TT |
452 | goto err_free_wqe_info; |
453 | ||
454 | for (i = 0; i < wq_sz; i++) { | |
21c59685 | 455 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; |
7e426671 | 456 | |
21c59685 | 457 | wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc, |
7e426671 TT |
458 | MLX5_UMR_ALIGN); |
459 | wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz, | |
460 | PCI_DMA_TODEVICE); | |
461 | if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr))) | |
462 | goto err_unmap_mtts; | |
463 | ||
464 | mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i); | |
465 | } | |
466 | ||
467 | return 0; | |
468 | ||
469 | err_unmap_mtts: | |
470 | while (--i >= 0) { | |
21c59685 | 471 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; |
7e426671 TT |
472 | |
473 | dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz, | |
474 | PCI_DMA_TODEVICE); | |
475 | } | |
21c59685 | 476 | kfree(rq->mpwqe.mtt_no_align); |
7e426671 | 477 | err_free_wqe_info: |
21c59685 | 478 | kfree(rq->mpwqe.info); |
7e426671 TT |
479 | |
480 | err_out: | |
481 | return -ENOMEM; | |
482 | } | |
483 | ||
484 | static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq) | |
485 | { | |
486 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
487 | int mtt_sz = mlx5e_get_wqe_mtt_sz(); | |
488 | int i; | |
489 | ||
490 | for (i = 0; i < wq_sz; i++) { | |
21c59685 | 491 | struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i]; |
7e426671 TT |
492 | |
493 | dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz, | |
494 | PCI_DMA_TODEVICE); | |
495 | } | |
21c59685 SM |
496 | kfree(rq->mpwqe.mtt_no_align); |
497 | kfree(rq->mpwqe.info); | |
7e426671 TT |
498 | } |
499 | ||
a43b25da | 500 | static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev, |
ec8b9981 TT |
501 | u64 npages, u8 page_shift, |
502 | struct mlx5_core_mkey *umr_mkey) | |
3608ae77 | 503 | { |
3608ae77 TT |
504 | int inlen = MLX5_ST_SZ_BYTES(create_mkey_in); |
505 | void *mkc; | |
506 | u32 *in; | |
507 | int err; | |
508 | ||
ec8b9981 TT |
509 | if (!MLX5E_VALID_NUM_MTTS(npages)) |
510 | return -EINVAL; | |
511 | ||
1b9a07ee | 512 | in = kvzalloc(inlen, GFP_KERNEL); |
3608ae77 TT |
513 | if (!in) |
514 | return -ENOMEM; | |
515 | ||
516 | mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); | |
517 | ||
3608ae77 TT |
518 | MLX5_SET(mkc, mkc, free, 1); |
519 | MLX5_SET(mkc, mkc, umr_en, 1); | |
520 | MLX5_SET(mkc, mkc, lw, 1); | |
521 | MLX5_SET(mkc, mkc, lr, 1); | |
522 | MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT); | |
523 | ||
524 | MLX5_SET(mkc, mkc, qpn, 0xffffff); | |
525 | MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn); | |
ec8b9981 | 526 | MLX5_SET64(mkc, mkc, len, npages << page_shift); |
3608ae77 TT |
527 | MLX5_SET(mkc, mkc, translations_octword_size, |
528 | MLX5_MTT_OCTW(npages)); | |
ec8b9981 | 529 | MLX5_SET(mkc, mkc, log_page_size, page_shift); |
3608ae77 | 530 | |
ec8b9981 | 531 | err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen); |
3608ae77 TT |
532 | |
533 | kvfree(in); | |
534 | return err; | |
535 | } | |
536 | ||
a43b25da | 537 | static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq) |
ec8b9981 | 538 | { |
6a9764ef | 539 | u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq)); |
ec8b9981 | 540 | |
a43b25da | 541 | return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey); |
ec8b9981 TT |
542 | } |
543 | ||
3b77235b | 544 | static int mlx5e_alloc_rq(struct mlx5e_channel *c, |
6a9764ef SM |
545 | struct mlx5e_params *params, |
546 | struct mlx5e_rq_param *rqp, | |
3b77235b | 547 | struct mlx5e_rq *rq) |
f62b8bb8 | 548 | { |
a43b25da | 549 | struct mlx5_core_dev *mdev = c->mdev; |
6a9764ef | 550 | void *rqc = rqp->rqc; |
f62b8bb8 | 551 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); |
461017cb | 552 | u32 byte_count; |
1bfecfca | 553 | int npages; |
f62b8bb8 AV |
554 | int wq_sz; |
555 | int err; | |
556 | int i; | |
557 | ||
231243c8 | 558 | rqp->wq.db_numa_node = cpu_to_node(c->cpu); |
311c7c71 | 559 | |
6a9764ef | 560 | err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq, |
f62b8bb8 AV |
561 | &rq->wq_ctrl); |
562 | if (err) | |
563 | return err; | |
564 | ||
565 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
566 | ||
567 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
f62b8bb8 | 568 | |
6a9764ef | 569 | rq->wq_type = params->rq_wq_type; |
7e426671 TT |
570 | rq->pdev = c->pdev; |
571 | rq->netdev = c->netdev; | |
a43b25da | 572 | rq->tstamp = c->tstamp; |
7c39afb3 | 573 | rq->clock = &mdev->clock; |
7e426671 TT |
574 | rq->channel = c; |
575 | rq->ix = c->ix; | |
a43b25da | 576 | rq->mdev = mdev; |
97bc402d | 577 | |
6a9764ef | 578 | rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL; |
97bc402d DB |
579 | if (IS_ERR(rq->xdp_prog)) { |
580 | err = PTR_ERR(rq->xdp_prog); | |
581 | rq->xdp_prog = NULL; | |
582 | goto err_rq_wq_destroy; | |
583 | } | |
7e426671 | 584 | |
bce2b2bf | 585 | rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; |
b45d8b50 | 586 | rq->buff.headroom = params->rq_headroom; |
b5503b99 | 587 | |
6a9764ef | 588 | switch (rq->wq_type) { |
461017cb | 589 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
f5f82476 | 590 | |
7cc6d77b | 591 | rq->post_wqes = mlx5e_post_rx_mpwqes; |
6cd392a0 | 592 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; |
461017cb | 593 | |
20fd0c19 | 594 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe; |
899a59d3 IT |
595 | #ifdef CONFIG_MLX5_EN_IPSEC |
596 | if (MLX5_IPSEC_DEV(mdev)) { | |
597 | err = -EINVAL; | |
598 | netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n"); | |
599 | goto err_rq_wq_destroy; | |
600 | } | |
601 | #endif | |
20fd0c19 SM |
602 | if (!rq->handle_rx_cqe) { |
603 | err = -EINVAL; | |
604 | netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err); | |
605 | goto err_rq_wq_destroy; | |
606 | } | |
607 | ||
89e89f7a | 608 | rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz; |
b45d8b50 | 609 | rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides); |
1bfecfca | 610 | |
b681c481 | 611 | byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz; |
ec8b9981 | 612 | |
a43b25da | 613 | err = mlx5e_create_rq_umr_mkey(mdev, rq); |
7e426671 TT |
614 | if (err) |
615 | goto err_rq_wq_destroy; | |
ec8b9981 TT |
616 | rq->mkey_be = cpu_to_be32(rq->umr_mkey.key); |
617 | ||
618 | err = mlx5e_rq_alloc_mpwqe_info(rq, c); | |
619 | if (err) | |
620 | goto err_destroy_umr_mkey; | |
461017cb TT |
621 | break; |
622 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
accd5883 TT |
623 | rq->wqe.frag_info = |
624 | kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info), | |
231243c8 | 625 | GFP_KERNEL, cpu_to_node(c->cpu)); |
accd5883 | 626 | if (!rq->wqe.frag_info) { |
461017cb TT |
627 | err = -ENOMEM; |
628 | goto err_rq_wq_destroy; | |
629 | } | |
7cc6d77b | 630 | rq->post_wqes = mlx5e_post_rx_wqes; |
6cd392a0 | 631 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; |
461017cb | 632 | |
899a59d3 IT |
633 | #ifdef CONFIG_MLX5_EN_IPSEC |
634 | if (c->priv->ipsec) | |
635 | rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe; | |
636 | else | |
637 | #endif | |
638 | rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe; | |
20fd0c19 | 639 | if (!rq->handle_rx_cqe) { |
accd5883 | 640 | kfree(rq->wqe.frag_info); |
20fd0c19 SM |
641 | err = -EINVAL; |
642 | netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err); | |
643 | goto err_rq_wq_destroy; | |
644 | } | |
645 | ||
b681c481 | 646 | byte_count = params->lro_en ? |
6a9764ef | 647 | params->lro_wqe_sz : |
c139dbfd | 648 | MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu); |
899a59d3 IT |
649 | #ifdef CONFIG_MLX5_EN_IPSEC |
650 | if (MLX5_IPSEC_DEV(mdev)) | |
b681c481 | 651 | byte_count += MLX5E_METADATA_ETHER_LEN; |
899a59d3 | 652 | #endif |
accd5883 | 653 | rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en; |
1bfecfca SM |
654 | |
655 | /* calc the required page order */ | |
b45d8b50 | 656 | rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count); |
accd5883 | 657 | npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE); |
1bfecfca SM |
658 | rq->buff.page_order = order_base_2(npages); |
659 | ||
461017cb | 660 | byte_count |= MLX5_HW_START_PADDING; |
7e426671 | 661 | rq->mkey_be = c->mkey_be; |
461017cb | 662 | } |
f62b8bb8 AV |
663 | |
664 | for (i = 0; i < wq_sz; i++) { | |
665 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
666 | ||
4c2af5cc TT |
667 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) { |
668 | u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT; | |
669 | ||
670 | wqe->data.addr = cpu_to_be64(dma_offset); | |
671 | } | |
672 | ||
461017cb | 673 | wqe->data.byte_count = cpu_to_be32(byte_count); |
7e426671 | 674 | wqe->data.lkey = rq->mkey_be; |
f62b8bb8 AV |
675 | } |
676 | ||
cb3c7fd4 | 677 | INIT_WORK(&rq->am.work, mlx5e_rx_am_work); |
0088cbbc | 678 | rq->am.mode = params->rx_cq_moderation.cq_period_mode; |
4415a031 TT |
679 | rq->page_cache.head = 0; |
680 | rq->page_cache.tail = 0; | |
681 | ||
f62b8bb8 AV |
682 | return 0; |
683 | ||
ec8b9981 TT |
684 | err_destroy_umr_mkey: |
685 | mlx5_core_destroy_mkey(mdev, &rq->umr_mkey); | |
686 | ||
f62b8bb8 | 687 | err_rq_wq_destroy: |
97bc402d DB |
688 | if (rq->xdp_prog) |
689 | bpf_prog_put(rq->xdp_prog); | |
f62b8bb8 AV |
690 | mlx5_wq_destroy(&rq->wq_ctrl); |
691 | ||
692 | return err; | |
693 | } | |
694 | ||
3b77235b | 695 | static void mlx5e_free_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 696 | { |
4415a031 TT |
697 | int i; |
698 | ||
86994156 RS |
699 | if (rq->xdp_prog) |
700 | bpf_prog_put(rq->xdp_prog); | |
701 | ||
461017cb TT |
702 | switch (rq->wq_type) { |
703 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
7e426671 | 704 | mlx5e_rq_free_mpwqe_info(rq); |
a43b25da | 705 | mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey); |
461017cb TT |
706 | break; |
707 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
accd5883 | 708 | kfree(rq->wqe.frag_info); |
461017cb TT |
709 | } |
710 | ||
4415a031 TT |
711 | for (i = rq->page_cache.head; i != rq->page_cache.tail; |
712 | i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) { | |
713 | struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i]; | |
714 | ||
715 | mlx5e_page_release(rq, dma_info, false); | |
716 | } | |
f62b8bb8 AV |
717 | mlx5_wq_destroy(&rq->wq_ctrl); |
718 | } | |
719 | ||
6a9764ef SM |
720 | static int mlx5e_create_rq(struct mlx5e_rq *rq, |
721 | struct mlx5e_rq_param *param) | |
f62b8bb8 | 722 | { |
a43b25da | 723 | struct mlx5_core_dev *mdev = rq->mdev; |
f62b8bb8 AV |
724 | |
725 | void *in; | |
726 | void *rqc; | |
727 | void *wq; | |
728 | int inlen; | |
729 | int err; | |
730 | ||
731 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
732 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
1b9a07ee | 733 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
734 | if (!in) |
735 | return -ENOMEM; | |
736 | ||
737 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
738 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
739 | ||
740 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
741 | ||
97de9f31 | 742 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 | 743 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
f62b8bb8 | 744 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 745 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
746 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
747 | ||
748 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
749 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
750 | ||
7db22ffb | 751 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
752 | |
753 | kvfree(in); | |
754 | ||
755 | return err; | |
756 | } | |
757 | ||
36350114 GP |
758 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
759 | int next_state) | |
f62b8bb8 AV |
760 | { |
761 | struct mlx5e_channel *c = rq->channel; | |
a43b25da | 762 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 AV |
763 | |
764 | void *in; | |
765 | void *rqc; | |
766 | int inlen; | |
767 | int err; | |
768 | ||
769 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 770 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
771 | if (!in) |
772 | return -ENOMEM; | |
773 | ||
774 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
775 | ||
776 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
777 | MLX5_SET(rqc, rqc, state, next_state); | |
778 | ||
7db22ffb | 779 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
780 | |
781 | kvfree(in); | |
782 | ||
783 | return err; | |
784 | } | |
785 | ||
102722fc GE |
786 | static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable) |
787 | { | |
788 | struct mlx5e_channel *c = rq->channel; | |
789 | struct mlx5e_priv *priv = c->priv; | |
790 | struct mlx5_core_dev *mdev = priv->mdev; | |
791 | ||
792 | void *in; | |
793 | void *rqc; | |
794 | int inlen; | |
795 | int err; | |
796 | ||
797 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 798 | in = kvzalloc(inlen, GFP_KERNEL); |
102722fc GE |
799 | if (!in) |
800 | return -ENOMEM; | |
801 | ||
802 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
803 | ||
804 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
805 | MLX5_SET64(modify_rq_in, in, modify_bitmask, | |
806 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS); | |
807 | MLX5_SET(rqc, rqc, scatter_fcs, enable); | |
808 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
809 | ||
810 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
811 | ||
812 | kvfree(in); | |
813 | ||
814 | return err; | |
815 | } | |
816 | ||
36350114 GP |
817 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
818 | { | |
819 | struct mlx5e_channel *c = rq->channel; | |
a43b25da | 820 | struct mlx5_core_dev *mdev = c->mdev; |
36350114 GP |
821 | void *in; |
822 | void *rqc; | |
823 | int inlen; | |
824 | int err; | |
825 | ||
826 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
1b9a07ee | 827 | in = kvzalloc(inlen, GFP_KERNEL); |
36350114 GP |
828 | if (!in) |
829 | return -ENOMEM; | |
830 | ||
831 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
832 | ||
833 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
83b502a1 AV |
834 | MLX5_SET64(modify_rq_in, in, modify_bitmask, |
835 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD); | |
36350114 GP |
836 | MLX5_SET(rqc, rqc, vsd, vsd); |
837 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
838 | ||
839 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
840 | ||
841 | kvfree(in); | |
842 | ||
843 | return err; | |
844 | } | |
845 | ||
3b77235b | 846 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) |
f62b8bb8 | 847 | { |
a43b25da | 848 | mlx5_core_destroy_rq(rq->mdev, rq->rqn); |
f62b8bb8 AV |
849 | } |
850 | ||
851 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
852 | { | |
01c196a2 | 853 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 | 854 | struct mlx5e_channel *c = rq->channel; |
a43b25da | 855 | |
f62b8bb8 | 856 | struct mlx5_wq_ll *wq = &rq->wq; |
6a9764ef | 857 | u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq)); |
f62b8bb8 | 858 | |
01c196a2 | 859 | while (time_before(jiffies, exp_time)) { |
6a9764ef | 860 | if (wq->cur_sz >= min_wqes) |
f62b8bb8 AV |
861 | return 0; |
862 | ||
863 | msleep(20); | |
864 | } | |
865 | ||
a43b25da | 866 | netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n", |
6a9764ef | 867 | rq->rqn, wq->cur_sz, min_wqes); |
f62b8bb8 AV |
868 | return -ETIMEDOUT; |
869 | } | |
870 | ||
f2fde18c SM |
871 | static void mlx5e_free_rx_descs(struct mlx5e_rq *rq) |
872 | { | |
873 | struct mlx5_wq_ll *wq = &rq->wq; | |
874 | struct mlx5e_rx_wqe *wqe; | |
875 | __be16 wqe_ix_be; | |
876 | u16 wqe_ix; | |
877 | ||
8484f9ed | 878 | /* UMR WQE (if in progress) is always at wq->head */ |
a071cb9f TT |
879 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ && |
880 | rq->mpwqe.umr_in_progress) | |
21c59685 | 881 | mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]); |
8484f9ed | 882 | |
f2fde18c SM |
883 | while (!mlx5_wq_ll_is_empty(wq)) { |
884 | wqe_ix_be = *wq->tail_next; | |
885 | wqe_ix = be16_to_cpu(wqe_ix_be); | |
886 | wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix); | |
887 | rq->dealloc_wqe(rq, wqe_ix); | |
888 | mlx5_wq_ll_pop(&rq->wq, wqe_ix_be, | |
889 | &wqe->next.next_wqe_index); | |
890 | } | |
accd5883 TT |
891 | |
892 | if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) { | |
893 | /* Clean outstanding pages on handled WQEs that decided to do page-reuse, | |
894 | * but yet to be re-posted. | |
895 | */ | |
896 | int wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
897 | ||
898 | for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++) | |
899 | rq->dealloc_wqe(rq, wqe_ix); | |
900 | } | |
f2fde18c SM |
901 | } |
902 | ||
f62b8bb8 | 903 | static int mlx5e_open_rq(struct mlx5e_channel *c, |
6a9764ef | 904 | struct mlx5e_params *params, |
f62b8bb8 AV |
905 | struct mlx5e_rq_param *param, |
906 | struct mlx5e_rq *rq) | |
907 | { | |
908 | int err; | |
909 | ||
6a9764ef | 910 | err = mlx5e_alloc_rq(c, params, param, rq); |
f62b8bb8 AV |
911 | if (err) |
912 | return err; | |
913 | ||
3b77235b | 914 | err = mlx5e_create_rq(rq, param); |
f62b8bb8 | 915 | if (err) |
3b77235b | 916 | goto err_free_rq; |
f62b8bb8 | 917 | |
36350114 | 918 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 | 919 | if (err) |
3b77235b | 920 | goto err_destroy_rq; |
f62b8bb8 | 921 | |
6a9764ef | 922 | if (params->rx_am_enabled) |
a1eaba4c | 923 | c->rq.state |= BIT(MLX5E_RQ_STATE_AM); |
cb3c7fd4 | 924 | |
f62b8bb8 AV |
925 | return 0; |
926 | ||
f62b8bb8 AV |
927 | err_destroy_rq: |
928 | mlx5e_destroy_rq(rq); | |
3b77235b SM |
929 | err_free_rq: |
930 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
931 | |
932 | return err; | |
933 | } | |
934 | ||
acc6c595 SM |
935 | static void mlx5e_activate_rq(struct mlx5e_rq *rq) |
936 | { | |
937 | struct mlx5e_icosq *sq = &rq->channel->icosq; | |
938 | u16 pi = sq->pc & sq->wq.sz_m1; | |
939 | struct mlx5e_tx_wqe *nopwqe; | |
940 | ||
941 | set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); | |
942 | sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP; | |
acc6c595 SM |
943 | nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); |
944 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl); | |
945 | } | |
946 | ||
947 | static void mlx5e_deactivate_rq(struct mlx5e_rq *rq) | |
f62b8bb8 | 948 | { |
c0f1147d | 949 | clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state); |
f62b8bb8 | 950 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ |
acc6c595 | 951 | } |
cb3c7fd4 | 952 | |
acc6c595 SM |
953 | static void mlx5e_close_rq(struct mlx5e_rq *rq) |
954 | { | |
955 | cancel_work_sync(&rq->am.work); | |
f62b8bb8 | 956 | mlx5e_destroy_rq(rq); |
3b77235b SM |
957 | mlx5e_free_rx_descs(rq); |
958 | mlx5e_free_rq(rq); | |
f62b8bb8 AV |
959 | } |
960 | ||
31391048 | 961 | static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq) |
b5503b99 | 962 | { |
31391048 | 963 | kfree(sq->db.di); |
b5503b99 SM |
964 | } |
965 | ||
31391048 | 966 | static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa) |
b5503b99 SM |
967 | { |
968 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
969 | ||
31391048 | 970 | sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz, |
b5503b99 | 971 | GFP_KERNEL, numa); |
31391048 SM |
972 | if (!sq->db.di) { |
973 | mlx5e_free_xdpsq_db(sq); | |
b5503b99 SM |
974 | return -ENOMEM; |
975 | } | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
31391048 | 980 | static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c, |
6a9764ef | 981 | struct mlx5e_params *params, |
31391048 SM |
982 | struct mlx5e_sq_param *param, |
983 | struct mlx5e_xdpsq *sq) | |
984 | { | |
985 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); | |
a43b25da | 986 | struct mlx5_core_dev *mdev = c->mdev; |
31391048 SM |
987 | int err; |
988 | ||
989 | sq->pdev = c->pdev; | |
990 | sq->mkey_be = c->mkey_be; | |
991 | sq->channel = c; | |
992 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
6a9764ef | 993 | sq->min_inline_mode = params->tx_min_inline_mode; |
31391048 | 994 | |
231243c8 | 995 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 SM |
996 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
997 | if (err) | |
998 | return err; | |
999 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
1000 | ||
231243c8 | 1001 | err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1002 | if (err) |
1003 | goto err_sq_wq_destroy; | |
1004 | ||
1005 | return 0; | |
1006 | ||
1007 | err_sq_wq_destroy: | |
1008 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1009 | ||
1010 | return err; | |
1011 | } | |
1012 | ||
1013 | static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq) | |
1014 | { | |
1015 | mlx5e_free_xdpsq_db(sq); | |
1016 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1017 | } | |
1018 | ||
1019 | static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq) | |
f62b8bb8 | 1020 | { |
f10b7cc7 | 1021 | kfree(sq->db.ico_wqe); |
f62b8bb8 AV |
1022 | } |
1023 | ||
31391048 | 1024 | static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa) |
f10b7cc7 SM |
1025 | { |
1026 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
1027 | ||
1028 | sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz, | |
1029 | GFP_KERNEL, numa); | |
1030 | if (!sq->db.ico_wqe) | |
1031 | return -ENOMEM; | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
31391048 | 1036 | static int mlx5e_alloc_icosq(struct mlx5e_channel *c, |
31391048 SM |
1037 | struct mlx5e_sq_param *param, |
1038 | struct mlx5e_icosq *sq) | |
f10b7cc7 | 1039 | { |
31391048 | 1040 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1041 | struct mlx5_core_dev *mdev = c->mdev; |
31391048 | 1042 | int err; |
f10b7cc7 | 1043 | |
31391048 SM |
1044 | sq->mkey_be = c->mkey_be; |
1045 | sq->channel = c; | |
1046 | sq->uar_map = mdev->mlx5e_res.bfreg.map; | |
f62b8bb8 | 1047 | |
231243c8 | 1048 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 SM |
1049 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
1050 | if (err) | |
1051 | return err; | |
1052 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
f62b8bb8 | 1053 | |
231243c8 | 1054 | err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu)); |
31391048 SM |
1055 | if (err) |
1056 | goto err_sq_wq_destroy; | |
1057 | ||
1058 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS; | |
f62b8bb8 AV |
1059 | |
1060 | return 0; | |
31391048 SM |
1061 | |
1062 | err_sq_wq_destroy: | |
1063 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1064 | ||
1065 | return err; | |
f62b8bb8 AV |
1066 | } |
1067 | ||
31391048 | 1068 | static void mlx5e_free_icosq(struct mlx5e_icosq *sq) |
f10b7cc7 | 1069 | { |
31391048 SM |
1070 | mlx5e_free_icosq_db(sq); |
1071 | mlx5_wq_destroy(&sq->wq_ctrl); | |
f10b7cc7 SM |
1072 | } |
1073 | ||
31391048 | 1074 | static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq) |
f10b7cc7 | 1075 | { |
31391048 SM |
1076 | kfree(sq->db.wqe_info); |
1077 | kfree(sq->db.dma_fifo); | |
f10b7cc7 SM |
1078 | } |
1079 | ||
31391048 | 1080 | static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa) |
b5503b99 | 1081 | { |
31391048 SM |
1082 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); |
1083 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
1084 | ||
31391048 SM |
1085 | sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo), |
1086 | GFP_KERNEL, numa); | |
1087 | sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info), | |
1088 | GFP_KERNEL, numa); | |
77bdf895 | 1089 | if (!sq->db.dma_fifo || !sq->db.wqe_info) { |
31391048 SM |
1090 | mlx5e_free_txqsq_db(sq); |
1091 | return -ENOMEM; | |
b5503b99 | 1092 | } |
31391048 SM |
1093 | |
1094 | sq->dma_fifo_mask = df_sz - 1; | |
1095 | ||
1096 | return 0; | |
b5503b99 SM |
1097 | } |
1098 | ||
31391048 | 1099 | static int mlx5e_alloc_txqsq(struct mlx5e_channel *c, |
acc6c595 | 1100 | int txq_ix, |
6a9764ef | 1101 | struct mlx5e_params *params, |
31391048 SM |
1102 | struct mlx5e_sq_param *param, |
1103 | struct mlx5e_txqsq *sq) | |
f62b8bb8 | 1104 | { |
31391048 | 1105 | void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq); |
a43b25da | 1106 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 AV |
1107 | int err; |
1108 | ||
f10b7cc7 | 1109 | sq->pdev = c->pdev; |
a43b25da | 1110 | sq->tstamp = c->tstamp; |
7c39afb3 | 1111 | sq->clock = &mdev->clock; |
f10b7cc7 SM |
1112 | sq->mkey_be = c->mkey_be; |
1113 | sq->channel = c; | |
acc6c595 | 1114 | sq->txq_ix = txq_ix; |
aff26157 | 1115 | sq->uar_map = mdev->mlx5e_res.bfreg.map; |
6a9764ef SM |
1116 | sq->max_inline = params->tx_max_inline; |
1117 | sq->min_inline_mode = params->tx_min_inline_mode; | |
2ac9cfe7 IT |
1118 | if (MLX5_IPSEC_DEV(c->priv->mdev)) |
1119 | set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state); | |
f10b7cc7 | 1120 | |
231243c8 | 1121 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
31391048 | 1122 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl); |
f62b8bb8 | 1123 | if (err) |
aff26157 | 1124 | return err; |
31391048 | 1125 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; |
f62b8bb8 | 1126 | |
231243c8 | 1127 | err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu)); |
7ec0bb22 | 1128 | if (err) |
f62b8bb8 AV |
1129 | goto err_sq_wq_destroy; |
1130 | ||
31391048 | 1131 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; |
f62b8bb8 AV |
1132 | |
1133 | return 0; | |
1134 | ||
1135 | err_sq_wq_destroy: | |
1136 | mlx5_wq_destroy(&sq->wq_ctrl); | |
1137 | ||
f62b8bb8 AV |
1138 | return err; |
1139 | } | |
1140 | ||
31391048 | 1141 | static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1142 | { |
31391048 | 1143 | mlx5e_free_txqsq_db(sq); |
f62b8bb8 | 1144 | mlx5_wq_destroy(&sq->wq_ctrl); |
f62b8bb8 AV |
1145 | } |
1146 | ||
33ad9711 SM |
1147 | struct mlx5e_create_sq_param { |
1148 | struct mlx5_wq_ctrl *wq_ctrl; | |
1149 | u32 cqn; | |
1150 | u32 tisn; | |
1151 | u8 tis_lst_sz; | |
1152 | u8 min_inline_mode; | |
1153 | }; | |
1154 | ||
a43b25da | 1155 | static int mlx5e_create_sq(struct mlx5_core_dev *mdev, |
33ad9711 SM |
1156 | struct mlx5e_sq_param *param, |
1157 | struct mlx5e_create_sq_param *csp, | |
1158 | u32 *sqn) | |
f62b8bb8 | 1159 | { |
f62b8bb8 AV |
1160 | void *in; |
1161 | void *sqc; | |
1162 | void *wq; | |
1163 | int inlen; | |
1164 | int err; | |
1165 | ||
1166 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
33ad9711 | 1167 | sizeof(u64) * csp->wq_ctrl->buf.npages; |
1b9a07ee | 1168 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1169 | if (!in) |
1170 | return -ENOMEM; | |
1171 | ||
1172 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
1173 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1174 | ||
1175 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
33ad9711 SM |
1176 | MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz); |
1177 | MLX5_SET(sqc, sqc, tis_num_0, csp->tisn); | |
1178 | MLX5_SET(sqc, sqc, cqn, csp->cqn); | |
a6f402e4 SM |
1179 | |
1180 | if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) | |
33ad9711 | 1181 | MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode); |
a6f402e4 | 1182 | |
33ad9711 | 1183 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
f62b8bb8 AV |
1184 | |
1185 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
a43b25da | 1186 | MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index); |
33ad9711 | 1187 | MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift - |
68cdf5d6 | 1188 | MLX5_ADAPTER_PAGE_SHIFT); |
33ad9711 | 1189 | MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma); |
f62b8bb8 | 1190 | |
33ad9711 | 1191 | mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); |
f62b8bb8 | 1192 | |
33ad9711 | 1193 | err = mlx5_core_create_sq(mdev, in, inlen, sqn); |
f62b8bb8 AV |
1194 | |
1195 | kvfree(in); | |
1196 | ||
1197 | return err; | |
1198 | } | |
1199 | ||
33ad9711 SM |
1200 | struct mlx5e_modify_sq_param { |
1201 | int curr_state; | |
1202 | int next_state; | |
1203 | bool rl_update; | |
1204 | int rl_index; | |
1205 | }; | |
1206 | ||
a43b25da | 1207 | static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
33ad9711 | 1208 | struct mlx5e_modify_sq_param *p) |
f62b8bb8 | 1209 | { |
f62b8bb8 AV |
1210 | void *in; |
1211 | void *sqc; | |
1212 | int inlen; | |
1213 | int err; | |
1214 | ||
1215 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
1b9a07ee | 1216 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1217 | if (!in) |
1218 | return -ENOMEM; | |
1219 | ||
1220 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
1221 | ||
33ad9711 SM |
1222 | MLX5_SET(modify_sq_in, in, sq_state, p->curr_state); |
1223 | MLX5_SET(sqc, sqc, state, p->next_state); | |
1224 | if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) { | |
507f0c81 | 1225 | MLX5_SET64(modify_sq_in, in, modify_bitmask, 1); |
33ad9711 | 1226 | MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index); |
507f0c81 | 1227 | } |
f62b8bb8 | 1228 | |
33ad9711 | 1229 | err = mlx5_core_modify_sq(mdev, sqn, in, inlen); |
f62b8bb8 AV |
1230 | |
1231 | kvfree(in); | |
1232 | ||
1233 | return err; | |
1234 | } | |
1235 | ||
a43b25da | 1236 | static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn) |
33ad9711 | 1237 | { |
a43b25da | 1238 | mlx5_core_destroy_sq(mdev, sqn); |
f62b8bb8 AV |
1239 | } |
1240 | ||
a43b25da | 1241 | static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, |
31391048 SM |
1242 | struct mlx5e_sq_param *param, |
1243 | struct mlx5e_create_sq_param *csp, | |
1244 | u32 *sqn) | |
f62b8bb8 | 1245 | { |
33ad9711 | 1246 | struct mlx5e_modify_sq_param msp = {0}; |
31391048 SM |
1247 | int err; |
1248 | ||
a43b25da | 1249 | err = mlx5e_create_sq(mdev, param, csp, sqn); |
31391048 SM |
1250 | if (err) |
1251 | return err; | |
1252 | ||
1253 | msp.curr_state = MLX5_SQC_STATE_RST; | |
1254 | msp.next_state = MLX5_SQC_STATE_RDY; | |
a43b25da | 1255 | err = mlx5e_modify_sq(mdev, *sqn, &msp); |
31391048 | 1256 | if (err) |
a43b25da | 1257 | mlx5e_destroy_sq(mdev, *sqn); |
31391048 SM |
1258 | |
1259 | return err; | |
1260 | } | |
1261 | ||
7f859ecf SM |
1262 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
1263 | struct mlx5e_txqsq *sq, u32 rate); | |
1264 | ||
31391048 | 1265 | static int mlx5e_open_txqsq(struct mlx5e_channel *c, |
a43b25da | 1266 | u32 tisn, |
acc6c595 | 1267 | int txq_ix, |
6a9764ef | 1268 | struct mlx5e_params *params, |
31391048 SM |
1269 | struct mlx5e_sq_param *param, |
1270 | struct mlx5e_txqsq *sq) | |
1271 | { | |
1272 | struct mlx5e_create_sq_param csp = {}; | |
7f859ecf | 1273 | u32 tx_rate; |
f62b8bb8 AV |
1274 | int err; |
1275 | ||
6a9764ef | 1276 | err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq); |
f62b8bb8 AV |
1277 | if (err) |
1278 | return err; | |
1279 | ||
a43b25da | 1280 | csp.tisn = tisn; |
31391048 | 1281 | csp.tis_lst_sz = 1; |
33ad9711 SM |
1282 | csp.cqn = sq->cq.mcq.cqn; |
1283 | csp.wq_ctrl = &sq->wq_ctrl; | |
1284 | csp.min_inline_mode = sq->min_inline_mode; | |
a43b25da | 1285 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
f62b8bb8 | 1286 | if (err) |
31391048 | 1287 | goto err_free_txqsq; |
f62b8bb8 | 1288 | |
a43b25da | 1289 | tx_rate = c->priv->tx_rates[sq->txq_ix]; |
7f859ecf | 1290 | if (tx_rate) |
a43b25da | 1291 | mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate); |
7f859ecf | 1292 | |
f62b8bb8 AV |
1293 | return 0; |
1294 | ||
31391048 | 1295 | err_free_txqsq: |
3b77235b | 1296 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
31391048 | 1297 | mlx5e_free_txqsq(sq); |
f62b8bb8 AV |
1298 | |
1299 | return err; | |
1300 | } | |
1301 | ||
acc6c595 SM |
1302 | static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq) |
1303 | { | |
a43b25da | 1304 | sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix); |
acc6c595 SM |
1305 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
1306 | netdev_tx_reset_queue(sq->txq); | |
1307 | netif_tx_start_queue(sq->txq); | |
1308 | } | |
1309 | ||
f62b8bb8 AV |
1310 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) |
1311 | { | |
1312 | __netif_tx_lock_bh(txq); | |
1313 | netif_tx_stop_queue(txq); | |
1314 | __netif_tx_unlock_bh(txq); | |
1315 | } | |
1316 | ||
acc6c595 | 1317 | static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq) |
f62b8bb8 | 1318 | { |
33ad9711 | 1319 | struct mlx5e_channel *c = sq->channel; |
33ad9711 | 1320 | |
c0f1147d | 1321 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
6e8dd6d6 | 1322 | /* prevent netif_tx_wake_queue */ |
33ad9711 | 1323 | napi_synchronize(&c->napi); |
29429f33 | 1324 | |
31391048 | 1325 | netif_tx_disable_queue(sq->txq); |
f62b8bb8 | 1326 | |
31391048 SM |
1327 | /* last doorbell out, godspeed .. */ |
1328 | if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) { | |
1329 | struct mlx5e_tx_wqe *nop; | |
864b2d71 | 1330 | |
77bdf895 | 1331 | sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL; |
31391048 SM |
1332 | nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc); |
1333 | mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl); | |
29429f33 | 1334 | } |
acc6c595 SM |
1335 | } |
1336 | ||
1337 | static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq) | |
1338 | { | |
1339 | struct mlx5e_channel *c = sq->channel; | |
a43b25da | 1340 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 | 1341 | |
a43b25da | 1342 | mlx5e_destroy_sq(mdev, sq->sqn); |
33ad9711 SM |
1343 | if (sq->rate_limit) |
1344 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
31391048 SM |
1345 | mlx5e_free_txqsq_descs(sq); |
1346 | mlx5e_free_txqsq(sq); | |
1347 | } | |
1348 | ||
1349 | static int mlx5e_open_icosq(struct mlx5e_channel *c, | |
6a9764ef | 1350 | struct mlx5e_params *params, |
31391048 SM |
1351 | struct mlx5e_sq_param *param, |
1352 | struct mlx5e_icosq *sq) | |
1353 | { | |
1354 | struct mlx5e_create_sq_param csp = {}; | |
1355 | int err; | |
1356 | ||
6a9764ef | 1357 | err = mlx5e_alloc_icosq(c, param, sq); |
31391048 SM |
1358 | if (err) |
1359 | return err; | |
1360 | ||
1361 | csp.cqn = sq->cq.mcq.cqn; | |
1362 | csp.wq_ctrl = &sq->wq_ctrl; | |
6a9764ef | 1363 | csp.min_inline_mode = params->tx_min_inline_mode; |
31391048 | 1364 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
a43b25da | 1365 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1366 | if (err) |
1367 | goto err_free_icosq; | |
1368 | ||
1369 | return 0; | |
1370 | ||
1371 | err_free_icosq: | |
1372 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1373 | mlx5e_free_icosq(sq); | |
1374 | ||
1375 | return err; | |
1376 | } | |
1377 | ||
1378 | static void mlx5e_close_icosq(struct mlx5e_icosq *sq) | |
1379 | { | |
1380 | struct mlx5e_channel *c = sq->channel; | |
1381 | ||
1382 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1383 | napi_synchronize(&c->napi); | |
1384 | ||
a43b25da | 1385 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1386 | mlx5e_free_icosq(sq); |
1387 | } | |
1388 | ||
1389 | static int mlx5e_open_xdpsq(struct mlx5e_channel *c, | |
6a9764ef | 1390 | struct mlx5e_params *params, |
31391048 SM |
1391 | struct mlx5e_sq_param *param, |
1392 | struct mlx5e_xdpsq *sq) | |
1393 | { | |
1394 | unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT; | |
1395 | struct mlx5e_create_sq_param csp = {}; | |
31391048 SM |
1396 | unsigned int inline_hdr_sz = 0; |
1397 | int err; | |
1398 | int i; | |
1399 | ||
6a9764ef | 1400 | err = mlx5e_alloc_xdpsq(c, params, param, sq); |
31391048 SM |
1401 | if (err) |
1402 | return err; | |
1403 | ||
1404 | csp.tis_lst_sz = 1; | |
a43b25da | 1405 | csp.tisn = c->priv->tisn[0]; /* tc = 0 */ |
31391048 SM |
1406 | csp.cqn = sq->cq.mcq.cqn; |
1407 | csp.wq_ctrl = &sq->wq_ctrl; | |
1408 | csp.min_inline_mode = sq->min_inline_mode; | |
1409 | set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
a43b25da | 1410 | err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn); |
31391048 SM |
1411 | if (err) |
1412 | goto err_free_xdpsq; | |
1413 | ||
1414 | if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) { | |
1415 | inline_hdr_sz = MLX5E_XDP_MIN_INLINE; | |
1416 | ds_cnt++; | |
1417 | } | |
1418 | ||
1419 | /* Pre initialize fixed WQE fields */ | |
1420 | for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) { | |
1421 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i); | |
1422 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1423 | struct mlx5_wqe_eth_seg *eseg = &wqe->eth; | |
1424 | struct mlx5_wqe_data_seg *dseg; | |
1425 | ||
1426 | cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt); | |
1427 | eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz); | |
1428 | ||
1429 | dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1); | |
1430 | dseg->lkey = sq->mkey_be; | |
1431 | } | |
1432 | ||
1433 | return 0; | |
1434 | ||
1435 | err_free_xdpsq: | |
1436 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1437 | mlx5e_free_xdpsq(sq); | |
1438 | ||
1439 | return err; | |
1440 | } | |
1441 | ||
1442 | static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq) | |
1443 | { | |
1444 | struct mlx5e_channel *c = sq->channel; | |
1445 | ||
1446 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); | |
1447 | napi_synchronize(&c->napi); | |
1448 | ||
a43b25da | 1449 | mlx5e_destroy_sq(c->mdev, sq->sqn); |
31391048 SM |
1450 | mlx5e_free_xdpsq_descs(sq); |
1451 | mlx5e_free_xdpsq(sq); | |
f62b8bb8 AV |
1452 | } |
1453 | ||
95b6c6a5 EBE |
1454 | static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev, |
1455 | struct mlx5e_cq_param *param, | |
1456 | struct mlx5e_cq *cq) | |
f62b8bb8 | 1457 | { |
f62b8bb8 AV |
1458 | struct mlx5_core_cq *mcq = &cq->mcq; |
1459 | int eqn_not_used; | |
0b6e26ce | 1460 | unsigned int irqn; |
f62b8bb8 AV |
1461 | int err; |
1462 | u32 i; | |
1463 | ||
f62b8bb8 AV |
1464 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, |
1465 | &cq->wq_ctrl); | |
1466 | if (err) | |
1467 | return err; | |
1468 | ||
1469 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1470 | ||
f62b8bb8 AV |
1471 | mcq->cqe_sz = 64; |
1472 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1473 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1474 | *mcq->set_ci_db = 0; | |
1475 | *mcq->arm_db = 0; | |
1476 | mcq->vector = param->eq_ix; | |
1477 | mcq->comp = mlx5e_completion_event; | |
1478 | mcq->event = mlx5e_cq_error_event; | |
1479 | mcq->irqn = irqn; | |
f62b8bb8 AV |
1480 | |
1481 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
1482 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
1483 | ||
1484 | cqe->op_own = 0xf1; | |
1485 | } | |
1486 | ||
a43b25da | 1487 | cq->mdev = mdev; |
f62b8bb8 AV |
1488 | |
1489 | return 0; | |
1490 | } | |
1491 | ||
95b6c6a5 EBE |
1492 | static int mlx5e_alloc_cq(struct mlx5e_channel *c, |
1493 | struct mlx5e_cq_param *param, | |
1494 | struct mlx5e_cq *cq) | |
1495 | { | |
1496 | struct mlx5_core_dev *mdev = c->priv->mdev; | |
1497 | int err; | |
1498 | ||
231243c8 SM |
1499 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
1500 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
95b6c6a5 EBE |
1501 | param->eq_ix = c->ix; |
1502 | ||
1503 | err = mlx5e_alloc_cq_common(mdev, param, cq); | |
1504 | ||
1505 | cq->napi = &c->napi; | |
1506 | cq->channel = c; | |
1507 | ||
1508 | return err; | |
1509 | } | |
1510 | ||
3b77235b | 1511 | static void mlx5e_free_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1512 | { |
1c1b5228 | 1513 | mlx5_cqwq_destroy(&cq->wq_ctrl); |
f62b8bb8 AV |
1514 | } |
1515 | ||
3b77235b | 1516 | static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) |
f62b8bb8 | 1517 | { |
a43b25da | 1518 | struct mlx5_core_dev *mdev = cq->mdev; |
f62b8bb8 AV |
1519 | struct mlx5_core_cq *mcq = &cq->mcq; |
1520 | ||
1521 | void *in; | |
1522 | void *cqc; | |
1523 | int inlen; | |
0b6e26ce | 1524 | unsigned int irqn_not_used; |
f62b8bb8 AV |
1525 | int eqn; |
1526 | int err; | |
1527 | ||
1528 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
1c1b5228 | 1529 | sizeof(u64) * cq->wq_ctrl.frag_buf.npages; |
1b9a07ee | 1530 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
1531 | if (!in) |
1532 | return -ENOMEM; | |
1533 | ||
1534 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
1535 | ||
1536 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
1537 | ||
1c1b5228 TT |
1538 | mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf, |
1539 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
f62b8bb8 AV |
1540 | |
1541 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
1542 | ||
9908aa29 | 1543 | MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode); |
f62b8bb8 | 1544 | MLX5_SET(cqc, cqc, c_eqn, eqn); |
30aa60b3 | 1545 | MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index); |
1c1b5228 | 1546 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift - |
68cdf5d6 | 1547 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
1548 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
1549 | ||
1550 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
1551 | ||
1552 | kvfree(in); | |
1553 | ||
1554 | if (err) | |
1555 | return err; | |
1556 | ||
1557 | mlx5e_cq_arm(cq); | |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
3b77235b | 1562 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) |
f62b8bb8 | 1563 | { |
a43b25da | 1564 | mlx5_core_destroy_cq(cq->mdev, &cq->mcq); |
f62b8bb8 AV |
1565 | } |
1566 | ||
1567 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
6a9764ef | 1568 | struct mlx5e_cq_moder moder, |
f62b8bb8 | 1569 | struct mlx5e_cq_param *param, |
6a9764ef | 1570 | struct mlx5e_cq *cq) |
f62b8bb8 | 1571 | { |
a43b25da | 1572 | struct mlx5_core_dev *mdev = c->mdev; |
f62b8bb8 | 1573 | int err; |
f62b8bb8 | 1574 | |
3b77235b | 1575 | err = mlx5e_alloc_cq(c, param, cq); |
f62b8bb8 AV |
1576 | if (err) |
1577 | return err; | |
1578 | ||
3b77235b | 1579 | err = mlx5e_create_cq(cq, param); |
f62b8bb8 | 1580 | if (err) |
3b77235b | 1581 | goto err_free_cq; |
f62b8bb8 | 1582 | |
7524a5d8 | 1583 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
6a9764ef | 1584 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts); |
f62b8bb8 AV |
1585 | return 0; |
1586 | ||
3b77235b SM |
1587 | err_free_cq: |
1588 | mlx5e_free_cq(cq); | |
f62b8bb8 AV |
1589 | |
1590 | return err; | |
1591 | } | |
1592 | ||
1593 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
1594 | { | |
f62b8bb8 | 1595 | mlx5e_destroy_cq(cq); |
3b77235b | 1596 | mlx5e_free_cq(cq); |
f62b8bb8 AV |
1597 | } |
1598 | ||
231243c8 SM |
1599 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) |
1600 | { | |
1601 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1602 | } | |
1603 | ||
f62b8bb8 | 1604 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, |
6a9764ef | 1605 | struct mlx5e_params *params, |
f62b8bb8 AV |
1606 | struct mlx5e_channel_param *cparam) |
1607 | { | |
f62b8bb8 AV |
1608 | int err; |
1609 | int tc; | |
1610 | ||
1611 | for (tc = 0; tc < c->num_tc; tc++) { | |
6a9764ef SM |
1612 | err = mlx5e_open_cq(c, params->tx_cq_moderation, |
1613 | &cparam->tx_cq, &c->sq[tc].cq); | |
f62b8bb8 AV |
1614 | if (err) |
1615 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1616 | } |
1617 | ||
1618 | return 0; | |
1619 | ||
1620 | err_close_tx_cqs: | |
1621 | for (tc--; tc >= 0; tc--) | |
1622 | mlx5e_close_cq(&c->sq[tc].cq); | |
1623 | ||
1624 | return err; | |
1625 | } | |
1626 | ||
1627 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1628 | { | |
1629 | int tc; | |
1630 | ||
1631 | for (tc = 0; tc < c->num_tc; tc++) | |
1632 | mlx5e_close_cq(&c->sq[tc].cq); | |
1633 | } | |
1634 | ||
1635 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
6a9764ef | 1636 | struct mlx5e_params *params, |
f62b8bb8 AV |
1637 | struct mlx5e_channel_param *cparam) |
1638 | { | |
1639 | int err; | |
1640 | int tc; | |
1641 | ||
6a9764ef SM |
1642 | for (tc = 0; tc < params->num_tc; tc++) { |
1643 | int txq_ix = c->ix + tc * params->num_channels; | |
acc6c595 | 1644 | |
a43b25da SM |
1645 | err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix, |
1646 | params, &cparam->sq, &c->sq[tc]); | |
f62b8bb8 AV |
1647 | if (err) |
1648 | goto err_close_sqs; | |
1649 | } | |
1650 | ||
1651 | return 0; | |
1652 | ||
1653 | err_close_sqs: | |
1654 | for (tc--; tc >= 0; tc--) | |
31391048 | 1655 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1656 | |
1657 | return err; | |
1658 | } | |
1659 | ||
1660 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1661 | { | |
1662 | int tc; | |
1663 | ||
1664 | for (tc = 0; tc < c->num_tc; tc++) | |
31391048 | 1665 | mlx5e_close_txqsq(&c->sq[tc]); |
f62b8bb8 AV |
1666 | } |
1667 | ||
507f0c81 | 1668 | static int mlx5e_set_sq_maxrate(struct net_device *dev, |
31391048 | 1669 | struct mlx5e_txqsq *sq, u32 rate) |
507f0c81 YP |
1670 | { |
1671 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1672 | struct mlx5_core_dev *mdev = priv->mdev; | |
33ad9711 | 1673 | struct mlx5e_modify_sq_param msp = {0}; |
507f0c81 YP |
1674 | u16 rl_index = 0; |
1675 | int err; | |
1676 | ||
1677 | if (rate == sq->rate_limit) | |
1678 | /* nothing to do */ | |
1679 | return 0; | |
1680 | ||
1681 | if (sq->rate_limit) | |
1682 | /* remove current rl index to free space to next ones */ | |
1683 | mlx5_rl_remove_rate(mdev, sq->rate_limit); | |
1684 | ||
1685 | sq->rate_limit = 0; | |
1686 | ||
1687 | if (rate) { | |
1688 | err = mlx5_rl_add_rate(mdev, rate, &rl_index); | |
1689 | if (err) { | |
1690 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1691 | rate, err); | |
1692 | return err; | |
1693 | } | |
1694 | } | |
1695 | ||
33ad9711 SM |
1696 | msp.curr_state = MLX5_SQC_STATE_RDY; |
1697 | msp.next_state = MLX5_SQC_STATE_RDY; | |
1698 | msp.rl_index = rl_index; | |
1699 | msp.rl_update = true; | |
a43b25da | 1700 | err = mlx5e_modify_sq(mdev, sq->sqn, &msp); |
507f0c81 YP |
1701 | if (err) { |
1702 | netdev_err(dev, "Failed configuring rate %u: %d\n", | |
1703 | rate, err); | |
1704 | /* remove the rate from the table */ | |
1705 | if (rate) | |
1706 | mlx5_rl_remove_rate(mdev, rate); | |
1707 | return err; | |
1708 | } | |
1709 | ||
1710 | sq->rate_limit = rate; | |
1711 | return 0; | |
1712 | } | |
1713 | ||
1714 | static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate) | |
1715 | { | |
1716 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1717 | struct mlx5_core_dev *mdev = priv->mdev; | |
acc6c595 | 1718 | struct mlx5e_txqsq *sq = priv->txq2sq[index]; |
507f0c81 YP |
1719 | int err = 0; |
1720 | ||
1721 | if (!mlx5_rl_is_supported(mdev)) { | |
1722 | netdev_err(dev, "Rate limiting is not supported on this device\n"); | |
1723 | return -EINVAL; | |
1724 | } | |
1725 | ||
1726 | /* rate is given in Mb/sec, HW config is in Kb/sec */ | |
1727 | rate = rate << 10; | |
1728 | ||
1729 | /* Check whether rate in valid range, 0 is always valid */ | |
1730 | if (rate && !mlx5_rl_is_in_range(mdev, rate)) { | |
1731 | netdev_err(dev, "TX rate %u, is not in range\n", rate); | |
1732 | return -ERANGE; | |
1733 | } | |
1734 | ||
1735 | mutex_lock(&priv->state_lock); | |
1736 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1737 | err = mlx5e_set_sq_maxrate(dev, sq, rate); | |
1738 | if (!err) | |
1739 | priv->tx_rates[index] = rate; | |
1740 | mutex_unlock(&priv->state_lock); | |
1741 | ||
1742 | return err; | |
1743 | } | |
1744 | ||
f62b8bb8 | 1745 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
6a9764ef | 1746 | struct mlx5e_params *params, |
f62b8bb8 AV |
1747 | struct mlx5e_channel_param *cparam, |
1748 | struct mlx5e_channel **cp) | |
1749 | { | |
6a9764ef | 1750 | struct mlx5e_cq_moder icocq_moder = {0, 0}; |
f62b8bb8 | 1751 | struct net_device *netdev = priv->netdev; |
231243c8 | 1752 | int cpu = mlx5e_get_cpu(priv, ix); |
f62b8bb8 | 1753 | struct mlx5e_channel *c; |
a8c2eb15 | 1754 | unsigned int irq; |
f62b8bb8 | 1755 | int err; |
a8c2eb15 | 1756 | int eqn; |
f62b8bb8 | 1757 | |
231243c8 | 1758 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); |
f62b8bb8 AV |
1759 | if (!c) |
1760 | return -ENOMEM; | |
1761 | ||
1762 | c->priv = priv; | |
a43b25da SM |
1763 | c->mdev = priv->mdev; |
1764 | c->tstamp = &priv->tstamp; | |
f62b8bb8 | 1765 | c->ix = ix; |
231243c8 | 1766 | c->cpu = cpu; |
f62b8bb8 AV |
1767 | c->pdev = &priv->mdev->pdev->dev; |
1768 | c->netdev = priv->netdev; | |
b50d292b | 1769 | c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key); |
6a9764ef SM |
1770 | c->num_tc = params->num_tc; |
1771 | c->xdp = !!params->xdp_prog; | |
cb3c7fd4 | 1772 | |
a8c2eb15 TT |
1773 | mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq); |
1774 | c->irq_desc = irq_to_desc(irq); | |
1775 | ||
f62b8bb8 AV |
1776 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1777 | ||
6a9764ef | 1778 | err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq); |
f62b8bb8 AV |
1779 | if (err) |
1780 | goto err_napi_del; | |
1781 | ||
6a9764ef | 1782 | err = mlx5e_open_tx_cqs(c, params, cparam); |
d3c9bc27 TT |
1783 | if (err) |
1784 | goto err_close_icosq_cq; | |
1785 | ||
6a9764ef | 1786 | err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq); |
f62b8bb8 AV |
1787 | if (err) |
1788 | goto err_close_tx_cqs; | |
f62b8bb8 | 1789 | |
d7a0ecab | 1790 | /* XDP SQ CQ params are same as normal TXQ sq CQ params */ |
6a9764ef SM |
1791 | err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation, |
1792 | &cparam->tx_cq, &c->rq.xdpsq.cq) : 0; | |
d7a0ecab SM |
1793 | if (err) |
1794 | goto err_close_rx_cq; | |
1795 | ||
f62b8bb8 AV |
1796 | napi_enable(&c->napi); |
1797 | ||
6a9764ef | 1798 | err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1799 | if (err) |
1800 | goto err_disable_napi; | |
1801 | ||
6a9764ef | 1802 | err = mlx5e_open_sqs(c, params, cparam); |
d3c9bc27 TT |
1803 | if (err) |
1804 | goto err_close_icosq; | |
1805 | ||
6a9764ef | 1806 | err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0; |
d7a0ecab SM |
1807 | if (err) |
1808 | goto err_close_sqs; | |
b5503b99 | 1809 | |
6a9764ef | 1810 | err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq); |
f62b8bb8 | 1811 | if (err) |
b5503b99 | 1812 | goto err_close_xdp_sq; |
f62b8bb8 | 1813 | |
f62b8bb8 AV |
1814 | *cp = c; |
1815 | ||
1816 | return 0; | |
b5503b99 | 1817 | err_close_xdp_sq: |
d7a0ecab | 1818 | if (c->xdp) |
31391048 | 1819 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 AV |
1820 | |
1821 | err_close_sqs: | |
1822 | mlx5e_close_sqs(c); | |
1823 | ||
d3c9bc27 | 1824 | err_close_icosq: |
31391048 | 1825 | mlx5e_close_icosq(&c->icosq); |
d3c9bc27 | 1826 | |
f62b8bb8 AV |
1827 | err_disable_napi: |
1828 | napi_disable(&c->napi); | |
d7a0ecab | 1829 | if (c->xdp) |
31871f87 | 1830 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
d7a0ecab SM |
1831 | |
1832 | err_close_rx_cq: | |
f62b8bb8 AV |
1833 | mlx5e_close_cq(&c->rq.cq); |
1834 | ||
1835 | err_close_tx_cqs: | |
1836 | mlx5e_close_tx_cqs(c); | |
1837 | ||
d3c9bc27 TT |
1838 | err_close_icosq_cq: |
1839 | mlx5e_close_cq(&c->icosq.cq); | |
1840 | ||
f62b8bb8 AV |
1841 | err_napi_del: |
1842 | netif_napi_del(&c->napi); | |
1843 | kfree(c); | |
1844 | ||
1845 | return err; | |
1846 | } | |
1847 | ||
acc6c595 SM |
1848 | static void mlx5e_activate_channel(struct mlx5e_channel *c) |
1849 | { | |
1850 | int tc; | |
1851 | ||
1852 | for (tc = 0; tc < c->num_tc; tc++) | |
1853 | mlx5e_activate_txqsq(&c->sq[tc]); | |
1854 | mlx5e_activate_rq(&c->rq); | |
231243c8 | 1855 | netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix); |
acc6c595 SM |
1856 | } |
1857 | ||
1858 | static void mlx5e_deactivate_channel(struct mlx5e_channel *c) | |
1859 | { | |
1860 | int tc; | |
1861 | ||
1862 | mlx5e_deactivate_rq(&c->rq); | |
1863 | for (tc = 0; tc < c->num_tc; tc++) | |
1864 | mlx5e_deactivate_txqsq(&c->sq[tc]); | |
1865 | } | |
1866 | ||
f62b8bb8 AV |
1867 | static void mlx5e_close_channel(struct mlx5e_channel *c) |
1868 | { | |
1869 | mlx5e_close_rq(&c->rq); | |
b5503b99 | 1870 | if (c->xdp) |
31391048 | 1871 | mlx5e_close_xdpsq(&c->rq.xdpsq); |
f62b8bb8 | 1872 | mlx5e_close_sqs(c); |
31391048 | 1873 | mlx5e_close_icosq(&c->icosq); |
f62b8bb8 | 1874 | napi_disable(&c->napi); |
b5503b99 | 1875 | if (c->xdp) |
31871f87 | 1876 | mlx5e_close_cq(&c->rq.xdpsq.cq); |
f62b8bb8 AV |
1877 | mlx5e_close_cq(&c->rq.cq); |
1878 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1879 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1880 | netif_napi_del(&c->napi); |
7ae92ae5 | 1881 | |
f62b8bb8 AV |
1882 | kfree(c); |
1883 | } | |
1884 | ||
1885 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1886 | struct mlx5e_params *params, |
f62b8bb8 AV |
1887 | struct mlx5e_rq_param *param) |
1888 | { | |
1889 | void *rqc = param->rqc; | |
1890 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1891 | ||
6a9764ef | 1892 | switch (params->rq_wq_type) { |
461017cb | 1893 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
6a9764ef SM |
1894 | MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9); |
1895 | MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6); | |
461017cb TT |
1896 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
1897 | break; | |
1898 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1899 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1900 | } | |
1901 | ||
f62b8bb8 AV |
1902 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1903 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
6a9764ef | 1904 | MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size); |
b50d292b | 1905 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
593cf338 | 1906 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
6a9764ef | 1907 | MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable); |
102722fc | 1908 | MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en); |
f62b8bb8 | 1909 | |
311c7c71 | 1910 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 AV |
1911 | param->wq.linear = 1; |
1912 | } | |
1913 | ||
556dd1b9 TT |
1914 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1915 | { | |
1916 | void *rqc = param->rqc; | |
1917 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1918 | ||
1919 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1920 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1921 | } | |
1922 | ||
d3c9bc27 TT |
1923 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
1924 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
1925 | { |
1926 | void *sqc = param->sqc; | |
1927 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1928 | ||
f62b8bb8 | 1929 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
b50d292b | 1930 | MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn); |
f62b8bb8 | 1931 | |
311c7c71 | 1932 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
1933 | } |
1934 | ||
1935 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1936 | struct mlx5e_params *params, |
d3c9bc27 TT |
1937 | struct mlx5e_sq_param *param) |
1938 | { | |
1939 | void *sqc = param->sqc; | |
1940 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1941 | ||
1942 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 1943 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
2ac9cfe7 | 1944 | MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev)); |
f62b8bb8 AV |
1945 | } |
1946 | ||
1947 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1948 | struct mlx5e_cq_param *param) | |
1949 | { | |
1950 | void *cqc = param->cqc; | |
1951 | ||
30aa60b3 | 1952 | MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index); |
f62b8bb8 AV |
1953 | } |
1954 | ||
1955 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1956 | struct mlx5e_params *params, |
f62b8bb8 AV |
1957 | struct mlx5e_cq_param *param) |
1958 | { | |
1959 | void *cqc = param->cqc; | |
461017cb | 1960 | u8 log_cq_size; |
f62b8bb8 | 1961 | |
6a9764ef | 1962 | switch (params->rq_wq_type) { |
461017cb | 1963 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: |
6a9764ef | 1964 | log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides; |
461017cb TT |
1965 | break; |
1966 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
6a9764ef | 1967 | log_cq_size = params->log_rq_size; |
461017cb TT |
1968 | } |
1969 | ||
1970 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
6a9764ef | 1971 | if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) { |
7219ab34 TT |
1972 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); |
1973 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
1974 | } | |
f62b8bb8 AV |
1975 | |
1976 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 1977 | param->cq_period_mode = params->rx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
1978 | } |
1979 | ||
1980 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
6a9764ef | 1981 | struct mlx5e_params *params, |
f62b8bb8 AV |
1982 | struct mlx5e_cq_param *param) |
1983 | { | |
1984 | void *cqc = param->cqc; | |
1985 | ||
6a9764ef | 1986 | MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size); |
f62b8bb8 AV |
1987 | |
1988 | mlx5e_build_common_cq_param(priv, param); | |
0088cbbc | 1989 | param->cq_period_mode = params->tx_cq_moderation.cq_period_mode; |
f62b8bb8 AV |
1990 | } |
1991 | ||
d3c9bc27 | 1992 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
6a9764ef SM |
1993 | u8 log_wq_size, |
1994 | struct mlx5e_cq_param *param) | |
d3c9bc27 TT |
1995 | { |
1996 | void *cqc = param->cqc; | |
1997 | ||
1998 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
1999 | ||
2000 | mlx5e_build_common_cq_param(priv, param); | |
9908aa29 TT |
2001 | |
2002 | param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
d3c9bc27 TT |
2003 | } |
2004 | ||
2005 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
6a9764ef SM |
2006 | u8 log_wq_size, |
2007 | struct mlx5e_sq_param *param) | |
d3c9bc27 TT |
2008 | { |
2009 | void *sqc = param->sqc; | |
2010 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2011 | ||
2012 | mlx5e_build_sq_param_common(priv, param); | |
2013 | ||
2014 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 2015 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
2016 | } |
2017 | ||
b5503b99 | 2018 | static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv, |
6a9764ef | 2019 | struct mlx5e_params *params, |
b5503b99 SM |
2020 | struct mlx5e_sq_param *param) |
2021 | { | |
2022 | void *sqc = param->sqc; | |
2023 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
2024 | ||
2025 | mlx5e_build_sq_param_common(priv, param); | |
6a9764ef | 2026 | MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size); |
b5503b99 SM |
2027 | } |
2028 | ||
6a9764ef SM |
2029 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, |
2030 | struct mlx5e_params *params, | |
2031 | struct mlx5e_channel_param *cparam) | |
f62b8bb8 | 2032 | { |
bc77b240 | 2033 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 2034 | |
6a9764ef SM |
2035 | mlx5e_build_rq_param(priv, params, &cparam->rq); |
2036 | mlx5e_build_sq_param(priv, params, &cparam->sq); | |
2037 | mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq); | |
2038 | mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq); | |
2039 | mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq); | |
2040 | mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq); | |
2041 | mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq); | |
f62b8bb8 AV |
2042 | } |
2043 | ||
55c2503d SM |
2044 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
2045 | struct mlx5e_channels *chs) | |
f62b8bb8 | 2046 | { |
6b87663f | 2047 | struct mlx5e_channel_param *cparam; |
03289b88 | 2048 | int err = -ENOMEM; |
f62b8bb8 | 2049 | int i; |
f62b8bb8 | 2050 | |
6a9764ef | 2051 | chs->num = chs->params.num_channels; |
03289b88 | 2052 | |
ff9c852f | 2053 | chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL); |
6b87663f | 2054 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
acc6c595 SM |
2055 | if (!chs->c || !cparam) |
2056 | goto err_free; | |
f62b8bb8 | 2057 | |
6a9764ef | 2058 | mlx5e_build_channel_param(priv, &chs->params, cparam); |
ff9c852f | 2059 | for (i = 0; i < chs->num; i++) { |
6a9764ef | 2060 | err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]); |
f62b8bb8 AV |
2061 | if (err) |
2062 | goto err_close_channels; | |
2063 | } | |
2064 | ||
6b87663f | 2065 | kfree(cparam); |
f62b8bb8 AV |
2066 | return 0; |
2067 | ||
2068 | err_close_channels: | |
2069 | for (i--; i >= 0; i--) | |
ff9c852f | 2070 | mlx5e_close_channel(chs->c[i]); |
f62b8bb8 | 2071 | |
acc6c595 | 2072 | err_free: |
ff9c852f | 2073 | kfree(chs->c); |
6b87663f | 2074 | kfree(cparam); |
ff9c852f | 2075 | chs->num = 0; |
f62b8bb8 AV |
2076 | return err; |
2077 | } | |
2078 | ||
acc6c595 | 2079 | static void mlx5e_activate_channels(struct mlx5e_channels *chs) |
f62b8bb8 AV |
2080 | { |
2081 | int i; | |
2082 | ||
acc6c595 SM |
2083 | for (i = 0; i < chs->num; i++) |
2084 | mlx5e_activate_channel(chs->c[i]); | |
2085 | } | |
2086 | ||
2087 | static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs) | |
2088 | { | |
2089 | int err = 0; | |
2090 | int i; | |
2091 | ||
2092 | for (i = 0; i < chs->num; i++) { | |
2093 | err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq); | |
2094 | if (err) | |
2095 | break; | |
2096 | } | |
2097 | ||
2098 | return err; | |
2099 | } | |
2100 | ||
2101 | static void mlx5e_deactivate_channels(struct mlx5e_channels *chs) | |
2102 | { | |
2103 | int i; | |
2104 | ||
2105 | for (i = 0; i < chs->num; i++) | |
2106 | mlx5e_deactivate_channel(chs->c[i]); | |
2107 | } | |
2108 | ||
55c2503d | 2109 | void mlx5e_close_channels(struct mlx5e_channels *chs) |
acc6c595 SM |
2110 | { |
2111 | int i; | |
c3b7c5c9 | 2112 | |
ff9c852f SM |
2113 | for (i = 0; i < chs->num; i++) |
2114 | mlx5e_close_channel(chs->c[i]); | |
f62b8bb8 | 2115 | |
ff9c852f SM |
2116 | kfree(chs->c); |
2117 | chs->num = 0; | |
f62b8bb8 AV |
2118 | } |
2119 | ||
a5f97fee SM |
2120 | static int |
2121 | mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt) | |
f62b8bb8 AV |
2122 | { |
2123 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
2124 | void *rqtc; |
2125 | int inlen; | |
2126 | int err; | |
1da36696 | 2127 | u32 *in; |
a5f97fee | 2128 | int i; |
f62b8bb8 | 2129 | |
f62b8bb8 | 2130 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2131 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2132 | if (!in) |
2133 | return -ENOMEM; | |
2134 | ||
2135 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
2136 | ||
2137 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
2138 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
2139 | ||
a5f97fee SM |
2140 | for (i = 0; i < sz; i++) |
2141 | MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn); | |
2be6967c | 2142 | |
398f3351 HHZ |
2143 | err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn); |
2144 | if (!err) | |
2145 | rqt->enabled = true; | |
f62b8bb8 AV |
2146 | |
2147 | kvfree(in); | |
1da36696 TT |
2148 | return err; |
2149 | } | |
2150 | ||
cb67b832 | 2151 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt) |
1da36696 | 2152 | { |
398f3351 HHZ |
2153 | rqt->enabled = false; |
2154 | mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn); | |
1da36696 TT |
2155 | } |
2156 | ||
8f493ffd | 2157 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv) |
6bfd390b HHZ |
2158 | { |
2159 | struct mlx5e_rqt *rqt = &priv->indir_rqt; | |
8f493ffd | 2160 | int err; |
6bfd390b | 2161 | |
8f493ffd SM |
2162 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt); |
2163 | if (err) | |
2164 | mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err); | |
2165 | return err; | |
6bfd390b HHZ |
2166 | } |
2167 | ||
cb67b832 | 2168 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv) |
1da36696 | 2169 | { |
398f3351 | 2170 | struct mlx5e_rqt *rqt; |
1da36696 TT |
2171 | int err; |
2172 | int ix; | |
2173 | ||
6bfd390b | 2174 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
398f3351 | 2175 | rqt = &priv->direct_tir[ix].rqt; |
a5f97fee | 2176 | err = mlx5e_create_rqt(priv, 1 /*size */, rqt); |
1da36696 TT |
2177 | if (err) |
2178 | goto err_destroy_rqts; | |
2179 | } | |
2180 | ||
2181 | return 0; | |
2182 | ||
2183 | err_destroy_rqts: | |
8f493ffd | 2184 | mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err); |
1da36696 | 2185 | for (ix--; ix >= 0; ix--) |
398f3351 | 2186 | mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt); |
1da36696 | 2187 | |
f62b8bb8 AV |
2188 | return err; |
2189 | } | |
2190 | ||
8f493ffd SM |
2191 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv) |
2192 | { | |
2193 | int i; | |
2194 | ||
2195 | for (i = 0; i < priv->profile->max_nch(priv->mdev); i++) | |
2196 | mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt); | |
2197 | } | |
2198 | ||
a5f97fee SM |
2199 | static int mlx5e_rx_hash_fn(int hfunc) |
2200 | { | |
2201 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
2202 | MLX5_RX_HASH_FN_TOEPLITZ : | |
2203 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
2204 | } | |
2205 | ||
2206 | static int mlx5e_bits_invert(unsigned long a, int size) | |
2207 | { | |
2208 | int inv = 0; | |
2209 | int i; | |
2210 | ||
2211 | for (i = 0; i < size; i++) | |
2212 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
2213 | ||
2214 | return inv; | |
2215 | } | |
2216 | ||
2217 | static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz, | |
2218 | struct mlx5e_redirect_rqt_param rrp, void *rqtc) | |
2219 | { | |
2220 | int i; | |
2221 | ||
2222 | for (i = 0; i < sz; i++) { | |
2223 | u32 rqn; | |
2224 | ||
2225 | if (rrp.is_rss) { | |
2226 | int ix = i; | |
2227 | ||
2228 | if (rrp.rss.hfunc == ETH_RSS_HASH_XOR) | |
2229 | ix = mlx5e_bits_invert(i, ilog2(sz)); | |
2230 | ||
6a9764ef | 2231 | ix = priv->channels.params.indirection_rqt[ix]; |
a5f97fee SM |
2232 | rqn = rrp.rss.channels->c[ix]->rq.rqn; |
2233 | } else { | |
2234 | rqn = rrp.rqn; | |
2235 | } | |
2236 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
2237 | } | |
2238 | } | |
2239 | ||
2240 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
2241 | struct mlx5e_redirect_rqt_param rrp) | |
5c50368f AS |
2242 | { |
2243 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
2244 | void *rqtc; |
2245 | int inlen; | |
1da36696 | 2246 | u32 *in; |
5c50368f AS |
2247 | int err; |
2248 | ||
5c50368f | 2249 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1b9a07ee | 2250 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2251 | if (!in) |
2252 | return -ENOMEM; | |
2253 | ||
2254 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
2255 | ||
2256 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
5c50368f | 2257 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); |
a5f97fee | 2258 | mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc); |
1da36696 | 2259 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
2260 | |
2261 | kvfree(in); | |
5c50368f AS |
2262 | return err; |
2263 | } | |
2264 | ||
a5f97fee SM |
2265 | static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix, |
2266 | struct mlx5e_redirect_rqt_param rrp) | |
2267 | { | |
2268 | if (!rrp.is_rss) | |
2269 | return rrp.rqn; | |
2270 | ||
2271 | if (ix >= rrp.rss.channels->num) | |
2272 | return priv->drop_rq.rqn; | |
2273 | ||
2274 | return rrp.rss.channels->c[ix]->rq.rqn; | |
2275 | } | |
2276 | ||
2277 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv, | |
2278 | struct mlx5e_redirect_rqt_param rrp) | |
40ab6a6e | 2279 | { |
1da36696 TT |
2280 | u32 rqtn; |
2281 | int ix; | |
2282 | ||
398f3351 | 2283 | if (priv->indir_rqt.enabled) { |
a5f97fee | 2284 | /* RSS RQ table */ |
398f3351 | 2285 | rqtn = priv->indir_rqt.rqtn; |
a5f97fee | 2286 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp); |
398f3351 HHZ |
2287 | } |
2288 | ||
a5f97fee SM |
2289 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
2290 | struct mlx5e_redirect_rqt_param direct_rrp = { | |
2291 | .is_rss = false, | |
95632791 AM |
2292 | { |
2293 | .rqn = mlx5e_get_direct_rqn(priv, ix, rrp) | |
2294 | }, | |
a5f97fee SM |
2295 | }; |
2296 | ||
2297 | /* Direct RQ Tables */ | |
398f3351 HHZ |
2298 | if (!priv->direct_tir[ix].rqt.enabled) |
2299 | continue; | |
a5f97fee | 2300 | |
398f3351 | 2301 | rqtn = priv->direct_tir[ix].rqt.rqtn; |
a5f97fee | 2302 | mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp); |
1da36696 | 2303 | } |
40ab6a6e AS |
2304 | } |
2305 | ||
a5f97fee SM |
2306 | static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv, |
2307 | struct mlx5e_channels *chs) | |
2308 | { | |
2309 | struct mlx5e_redirect_rqt_param rrp = { | |
2310 | .is_rss = true, | |
95632791 AM |
2311 | { |
2312 | .rss = { | |
2313 | .channels = chs, | |
2314 | .hfunc = chs->params.rss_hfunc, | |
2315 | } | |
2316 | }, | |
a5f97fee SM |
2317 | }; |
2318 | ||
2319 | mlx5e_redirect_rqts(priv, rrp); | |
2320 | } | |
2321 | ||
2322 | static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv) | |
2323 | { | |
2324 | struct mlx5e_redirect_rqt_param drop_rrp = { | |
2325 | .is_rss = false, | |
95632791 AM |
2326 | { |
2327 | .rqn = priv->drop_rq.rqn, | |
2328 | }, | |
a5f97fee SM |
2329 | }; |
2330 | ||
2331 | mlx5e_redirect_rqts(priv, drop_rrp); | |
2332 | } | |
2333 | ||
6a9764ef | 2334 | static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc) |
5c50368f | 2335 | { |
6a9764ef | 2336 | if (!params->lro_en) |
5c50368f AS |
2337 | return; |
2338 | ||
2339 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
2340 | ||
2341 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
2342 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
2343 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
2344 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
6a9764ef SM |
2345 | (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8); |
2346 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout); | |
5c50368f AS |
2347 | } |
2348 | ||
6a9764ef SM |
2349 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
2350 | enum mlx5e_traffic_types tt, | |
7b3722fa | 2351 | void *tirc, bool inner) |
bdfc028d | 2352 | { |
7b3722fa GP |
2353 | void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) : |
2354 | MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
a100ff3e GP |
2355 | |
2356 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2357 | MLX5_HASH_FIELD_SEL_DST_IP) | |
2358 | ||
2359 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2360 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2361 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
2362 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
2363 | ||
2364 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ | |
2365 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
2366 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
2367 | ||
6a9764ef SM |
2368 | MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc)); |
2369 | if (params->rss_hfunc == ETH_RSS_HASH_TOP) { | |
bdfc028d TT |
2370 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, |
2371 | rx_hash_toeplitz_key); | |
2372 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
2373 | rx_hash_toeplitz_key); | |
2374 | ||
2375 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
6a9764ef | 2376 | memcpy(rss_key, params->toeplitz_hash_key, len); |
bdfc028d | 2377 | } |
a100ff3e GP |
2378 | |
2379 | switch (tt) { | |
2380 | case MLX5E_TT_IPV4_TCP: | |
2381 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2382 | MLX5_L3_PROT_TYPE_IPV4); | |
2383 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2384 | MLX5_L4_PROT_TYPE_TCP); | |
2385 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2386 | MLX5_HASH_IP_L4PORTS); | |
2387 | break; | |
2388 | ||
2389 | case MLX5E_TT_IPV6_TCP: | |
2390 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2391 | MLX5_L3_PROT_TYPE_IPV6); | |
2392 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2393 | MLX5_L4_PROT_TYPE_TCP); | |
2394 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2395 | MLX5_HASH_IP_L4PORTS); | |
2396 | break; | |
2397 | ||
2398 | case MLX5E_TT_IPV4_UDP: | |
2399 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2400 | MLX5_L3_PROT_TYPE_IPV4); | |
2401 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2402 | MLX5_L4_PROT_TYPE_UDP); | |
2403 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2404 | MLX5_HASH_IP_L4PORTS); | |
2405 | break; | |
2406 | ||
2407 | case MLX5E_TT_IPV6_UDP: | |
2408 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2409 | MLX5_L3_PROT_TYPE_IPV6); | |
2410 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2411 | MLX5_L4_PROT_TYPE_UDP); | |
2412 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2413 | MLX5_HASH_IP_L4PORTS); | |
2414 | break; | |
2415 | ||
2416 | case MLX5E_TT_IPV4_IPSEC_AH: | |
2417 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2418 | MLX5_L3_PROT_TYPE_IPV4); | |
2419 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2420 | MLX5_HASH_IP_IPSEC_SPI); | |
2421 | break; | |
2422 | ||
2423 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2424 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2425 | MLX5_L3_PROT_TYPE_IPV6); | |
2426 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2427 | MLX5_HASH_IP_IPSEC_SPI); | |
2428 | break; | |
2429 | ||
2430 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2431 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2432 | MLX5_L3_PROT_TYPE_IPV4); | |
2433 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2434 | MLX5_HASH_IP_IPSEC_SPI); | |
2435 | break; | |
2436 | ||
2437 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2438 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2439 | MLX5_L3_PROT_TYPE_IPV6); | |
2440 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2441 | MLX5_HASH_IP_IPSEC_SPI); | |
2442 | break; | |
2443 | ||
2444 | case MLX5E_TT_IPV4: | |
2445 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2446 | MLX5_L3_PROT_TYPE_IPV4); | |
2447 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2448 | MLX5_HASH_IP); | |
2449 | break; | |
2450 | ||
2451 | case MLX5E_TT_IPV6: | |
2452 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2453 | MLX5_L3_PROT_TYPE_IPV6); | |
2454 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2455 | MLX5_HASH_IP); | |
2456 | break; | |
2457 | default: | |
2458 | WARN_ONCE(true, "%s: bad traffic type!\n", __func__); | |
2459 | } | |
bdfc028d TT |
2460 | } |
2461 | ||
ab0394fe | 2462 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
2463 | { |
2464 | struct mlx5_core_dev *mdev = priv->mdev; | |
2465 | ||
2466 | void *in; | |
2467 | void *tirc; | |
2468 | int inlen; | |
2469 | int err; | |
ab0394fe | 2470 | int tt; |
1da36696 | 2471 | int ix; |
5c50368f AS |
2472 | |
2473 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1b9a07ee | 2474 | in = kvzalloc(inlen, GFP_KERNEL); |
5c50368f AS |
2475 | if (!in) |
2476 | return -ENOMEM; | |
2477 | ||
2478 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
2479 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
2480 | ||
6a9764ef | 2481 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
5c50368f | 2482 | |
1da36696 | 2483 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
724b2aa1 | 2484 | err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, |
1da36696 | 2485 | inlen); |
ab0394fe | 2486 | if (err) |
1da36696 | 2487 | goto free_in; |
ab0394fe | 2488 | } |
5c50368f | 2489 | |
6bfd390b | 2490 | for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) { |
1da36696 TT |
2491 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, |
2492 | in, inlen); | |
2493 | if (err) | |
2494 | goto free_in; | |
2495 | } | |
2496 | ||
2497 | free_in: | |
5c50368f AS |
2498 | kvfree(in); |
2499 | ||
2500 | return err; | |
2501 | } | |
2502 | ||
7b3722fa GP |
2503 | static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv, |
2504 | enum mlx5e_traffic_types tt, | |
2505 | u32 *tirc) | |
2506 | { | |
2507 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); | |
2508 | ||
2509 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); | |
2510 | ||
2511 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2512 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); | |
2513 | MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1); | |
2514 | ||
2515 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true); | |
2516 | } | |
2517 | ||
cd255eff | 2518 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) |
40ab6a6e | 2519 | { |
40ab6a6e | 2520 | struct mlx5_core_dev *mdev = priv->mdev; |
c139dbfd | 2521 | u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu); |
40ab6a6e AS |
2522 | int err; |
2523 | ||
cd255eff | 2524 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
2525 | if (err) |
2526 | return err; | |
2527 | ||
cd255eff SM |
2528 | /* Update vport context MTU */ |
2529 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
2530 | return 0; | |
2531 | } | |
40ab6a6e | 2532 | |
cd255eff SM |
2533 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) |
2534 | { | |
2535 | struct mlx5_core_dev *mdev = priv->mdev; | |
2536 | u16 hw_mtu = 0; | |
2537 | int err; | |
40ab6a6e | 2538 | |
cd255eff SM |
2539 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
2540 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
2541 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
2542 | ||
c139dbfd | 2543 | *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu); |
cd255eff SM |
2544 | } |
2545 | ||
2e20a151 | 2546 | static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) |
cd255eff | 2547 | { |
2e20a151 | 2548 | struct net_device *netdev = priv->netdev; |
cd255eff SM |
2549 | u16 mtu; |
2550 | int err; | |
2551 | ||
2552 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
2553 | if (err) | |
2554 | return err; | |
40ab6a6e | 2555 | |
cd255eff SM |
2556 | mlx5e_query_mtu(priv, &mtu); |
2557 | if (mtu != netdev->mtu) | |
2558 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
2559 | __func__, mtu, netdev->mtu); | |
40ab6a6e | 2560 | |
cd255eff | 2561 | netdev->mtu = mtu; |
40ab6a6e AS |
2562 | return 0; |
2563 | } | |
2564 | ||
08fb1dac SM |
2565 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
2566 | { | |
2567 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6a9764ef SM |
2568 | int nch = priv->channels.params.num_channels; |
2569 | int ntc = priv->channels.params.num_tc; | |
08fb1dac SM |
2570 | int tc; |
2571 | ||
2572 | netdev_reset_tc(netdev); | |
2573 | ||
2574 | if (ntc == 1) | |
2575 | return; | |
2576 | ||
2577 | netdev_set_num_tc(netdev, ntc); | |
2578 | ||
7ccdd084 RS |
2579 | /* Map netdev TCs to offset 0 |
2580 | * We have our own UP to TXQ mapping for QoS | |
2581 | */ | |
08fb1dac | 2582 | for (tc = 0; tc < ntc; tc++) |
7ccdd084 | 2583 | netdev_set_tc_queue(netdev, tc, nch, 0); |
08fb1dac SM |
2584 | } |
2585 | ||
acc6c595 SM |
2586 | static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv) |
2587 | { | |
2588 | struct mlx5e_channel *c; | |
2589 | struct mlx5e_txqsq *sq; | |
2590 | int i, tc; | |
2591 | ||
2592 | for (i = 0; i < priv->channels.num; i++) | |
2593 | for (tc = 0; tc < priv->profile->max_tc; tc++) | |
2594 | priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num; | |
2595 | ||
2596 | for (i = 0; i < priv->channels.num; i++) { | |
2597 | c = priv->channels.c[i]; | |
2598 | for (tc = 0; tc < c->num_tc; tc++) { | |
2599 | sq = &c->sq[tc]; | |
2600 | priv->txq2sq[sq->txq_ix] = sq; | |
2601 | } | |
2602 | } | |
2603 | } | |
2604 | ||
603f4a45 | 2605 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2606 | { |
9008ae07 SM |
2607 | int num_txqs = priv->channels.num * priv->channels.params.num_tc; |
2608 | struct net_device *netdev = priv->netdev; | |
2609 | ||
2610 | mlx5e_netdev_set_tcs(netdev); | |
053ee0a7 TR |
2611 | netif_set_real_num_tx_queues(netdev, num_txqs); |
2612 | netif_set_real_num_rx_queues(netdev, priv->channels.num); | |
9008ae07 | 2613 | |
acc6c595 SM |
2614 | mlx5e_build_channels_tx_maps(priv); |
2615 | mlx5e_activate_channels(&priv->channels); | |
2616 | netif_tx_start_all_queues(priv->netdev); | |
9008ae07 | 2617 | |
a9f7705f | 2618 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2619 | mlx5e_add_sqs_fwd_rules(priv); |
2620 | ||
acc6c595 | 2621 | mlx5e_wait_channels_min_rx_wqes(&priv->channels); |
9008ae07 | 2622 | mlx5e_redirect_rqts_to_channels(priv, &priv->channels); |
acc6c595 SM |
2623 | } |
2624 | ||
603f4a45 | 2625 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv) |
acc6c595 | 2626 | { |
9008ae07 SM |
2627 | mlx5e_redirect_rqts_to_drop(priv); |
2628 | ||
a9f7705f | 2629 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
9008ae07 SM |
2630 | mlx5e_remove_sqs_fwd_rules(priv); |
2631 | ||
acc6c595 SM |
2632 | /* FIXME: This is a W/A only for tx timeout watch dog false alarm when |
2633 | * polling for inactive tx queues. | |
2634 | */ | |
2635 | netif_tx_stop_all_queues(priv->netdev); | |
2636 | netif_tx_disable(priv->netdev); | |
2637 | mlx5e_deactivate_channels(&priv->channels); | |
2638 | } | |
2639 | ||
55c2503d | 2640 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
2641 | struct mlx5e_channels *new_chs, |
2642 | mlx5e_fp_hw_modify hw_modify) | |
55c2503d SM |
2643 | { |
2644 | struct net_device *netdev = priv->netdev; | |
2645 | int new_num_txqs; | |
7ca42c80 | 2646 | int carrier_ok; |
55c2503d SM |
2647 | new_num_txqs = new_chs->num * new_chs->params.num_tc; |
2648 | ||
7ca42c80 | 2649 | carrier_ok = netif_carrier_ok(netdev); |
55c2503d SM |
2650 | netif_carrier_off(netdev); |
2651 | ||
2652 | if (new_num_txqs < netdev->real_num_tx_queues) | |
2653 | netif_set_real_num_tx_queues(netdev, new_num_txqs); | |
2654 | ||
2655 | mlx5e_deactivate_priv_channels(priv); | |
2656 | mlx5e_close_channels(&priv->channels); | |
2657 | ||
2658 | priv->channels = *new_chs; | |
2659 | ||
2e20a151 SM |
2660 | /* New channels are ready to roll, modify HW settings if needed */ |
2661 | if (hw_modify) | |
2662 | hw_modify(priv); | |
2663 | ||
55c2503d SM |
2664 | mlx5e_refresh_tirs(priv, false); |
2665 | mlx5e_activate_priv_channels(priv); | |
2666 | ||
7ca42c80 ES |
2667 | /* return carrier back if needed */ |
2668 | if (carrier_ok) | |
2669 | netif_carrier_on(netdev); | |
55c2503d SM |
2670 | } |
2671 | ||
7c39afb3 FD |
2672 | void mlx5e_timestamp_set(struct mlx5e_priv *priv) |
2673 | { | |
2674 | priv->tstamp.tx_type = HWTSTAMP_TX_OFF; | |
2675 | priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE; | |
2676 | } | |
2677 | ||
40ab6a6e AS |
2678 | int mlx5e_open_locked(struct net_device *netdev) |
2679 | { | |
2680 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
40ab6a6e AS |
2681 | int err; |
2682 | ||
2683 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
2684 | ||
ff9c852f | 2685 | err = mlx5e_open_channels(priv, &priv->channels); |
acc6c595 | 2686 | if (err) |
343b29f3 | 2687 | goto err_clear_state_opened_flag; |
40ab6a6e | 2688 | |
b676f653 | 2689 | mlx5e_refresh_tirs(priv, false); |
acc6c595 | 2690 | mlx5e_activate_priv_channels(priv); |
7ca42c80 ES |
2691 | if (priv->profile->update_carrier) |
2692 | priv->profile->update_carrier(priv); | |
7c39afb3 | 2693 | mlx5e_timestamp_set(priv); |
be4891af | 2694 | |
cb67b832 HHZ |
2695 | if (priv->profile->update_stats) |
2696 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); | |
40ab6a6e | 2697 | |
9b37b07f | 2698 | return 0; |
343b29f3 AS |
2699 | |
2700 | err_clear_state_opened_flag: | |
2701 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
2702 | return err; | |
40ab6a6e AS |
2703 | } |
2704 | ||
cb67b832 | 2705 | int mlx5e_open(struct net_device *netdev) |
40ab6a6e AS |
2706 | { |
2707 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2708 | int err; | |
2709 | ||
2710 | mutex_lock(&priv->state_lock); | |
2711 | err = mlx5e_open_locked(netdev); | |
63bfd399 EBE |
2712 | if (!err) |
2713 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP); | |
40ab6a6e AS |
2714 | mutex_unlock(&priv->state_lock); |
2715 | ||
2716 | return err; | |
2717 | } | |
2718 | ||
2719 | int mlx5e_close_locked(struct net_device *netdev) | |
2720 | { | |
2721 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2722 | ||
a1985740 AS |
2723 | /* May already be CLOSED in case a previous configuration operation |
2724 | * (e.g RX/TX queue size change) that involves close&open failed. | |
2725 | */ | |
2726 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2727 | return 0; | |
2728 | ||
40ab6a6e AS |
2729 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
2730 | ||
40ab6a6e | 2731 | netif_carrier_off(priv->netdev); |
acc6c595 SM |
2732 | mlx5e_deactivate_priv_channels(priv); |
2733 | mlx5e_close_channels(&priv->channels); | |
40ab6a6e AS |
2734 | |
2735 | return 0; | |
2736 | } | |
2737 | ||
cb67b832 | 2738 | int mlx5e_close(struct net_device *netdev) |
40ab6a6e AS |
2739 | { |
2740 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2741 | int err; | |
2742 | ||
26e59d80 MHY |
2743 | if (!netif_device_present(netdev)) |
2744 | return -ENODEV; | |
2745 | ||
40ab6a6e | 2746 | mutex_lock(&priv->state_lock); |
63bfd399 | 2747 | mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN); |
40ab6a6e AS |
2748 | err = mlx5e_close_locked(netdev); |
2749 | mutex_unlock(&priv->state_lock); | |
2750 | ||
2751 | return err; | |
2752 | } | |
2753 | ||
a43b25da | 2754 | static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2755 | struct mlx5e_rq *rq, |
2756 | struct mlx5e_rq_param *param) | |
40ab6a6e | 2757 | { |
40ab6a6e AS |
2758 | void *rqc = param->rqc; |
2759 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
2760 | int err; | |
2761 | ||
2762 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
2763 | ||
2764 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
2765 | &rq->wq_ctrl); | |
2766 | if (err) | |
2767 | return err; | |
2768 | ||
a43b25da | 2769 | rq->mdev = mdev; |
40ab6a6e AS |
2770 | |
2771 | return 0; | |
2772 | } | |
2773 | ||
a43b25da | 2774 | static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev, |
3b77235b SM |
2775 | struct mlx5e_cq *cq, |
2776 | struct mlx5e_cq_param *param) | |
40ab6a6e | 2777 | { |
95b6c6a5 | 2778 | return mlx5e_alloc_cq_common(mdev, param, cq); |
40ab6a6e AS |
2779 | } |
2780 | ||
a43b25da SM |
2781 | static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev, |
2782 | struct mlx5e_rq *drop_rq) | |
40ab6a6e | 2783 | { |
a43b25da SM |
2784 | struct mlx5e_cq_param cq_param = {}; |
2785 | struct mlx5e_rq_param rq_param = {}; | |
2786 | struct mlx5e_cq *cq = &drop_rq->cq; | |
40ab6a6e AS |
2787 | int err; |
2788 | ||
556dd1b9 | 2789 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e | 2790 | |
a43b25da | 2791 | err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param); |
40ab6a6e AS |
2792 | if (err) |
2793 | return err; | |
2794 | ||
3b77235b | 2795 | err = mlx5e_create_cq(cq, &cq_param); |
40ab6a6e | 2796 | if (err) |
3b77235b | 2797 | goto err_free_cq; |
40ab6a6e | 2798 | |
a43b25da | 2799 | err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param); |
40ab6a6e | 2800 | if (err) |
3b77235b | 2801 | goto err_destroy_cq; |
40ab6a6e | 2802 | |
a43b25da | 2803 | err = mlx5e_create_rq(drop_rq, &rq_param); |
40ab6a6e | 2804 | if (err) |
3b77235b | 2805 | goto err_free_rq; |
40ab6a6e AS |
2806 | |
2807 | return 0; | |
2808 | ||
3b77235b | 2809 | err_free_rq: |
a43b25da | 2810 | mlx5e_free_rq(drop_rq); |
40ab6a6e AS |
2811 | |
2812 | err_destroy_cq: | |
a43b25da | 2813 | mlx5e_destroy_cq(cq); |
40ab6a6e | 2814 | |
3b77235b | 2815 | err_free_cq: |
a43b25da | 2816 | mlx5e_free_cq(cq); |
3b77235b | 2817 | |
40ab6a6e AS |
2818 | return err; |
2819 | } | |
2820 | ||
a43b25da | 2821 | static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq) |
40ab6a6e | 2822 | { |
a43b25da SM |
2823 | mlx5e_destroy_rq(drop_rq); |
2824 | mlx5e_free_rq(drop_rq); | |
2825 | mlx5e_destroy_cq(&drop_rq->cq); | |
2826 | mlx5e_free_cq(&drop_rq->cq); | |
40ab6a6e AS |
2827 | } |
2828 | ||
5426a0b2 SM |
2829 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
2830 | u32 underlay_qpn, u32 *tisn) | |
40ab6a6e | 2831 | { |
c4f287c4 | 2832 | u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0}; |
40ab6a6e AS |
2833 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); |
2834 | ||
08fb1dac | 2835 | MLX5_SET(tisc, tisc, prio, tc << 1); |
5426a0b2 | 2836 | MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn); |
b50d292b | 2837 | MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn); |
db60b802 AH |
2838 | |
2839 | if (mlx5_lag_is_lacp_owner(mdev)) | |
2840 | MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1); | |
2841 | ||
5426a0b2 | 2842 | return mlx5_core_create_tis(mdev, in, sizeof(in), tisn); |
40ab6a6e AS |
2843 | } |
2844 | ||
5426a0b2 | 2845 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn) |
40ab6a6e | 2846 | { |
5426a0b2 | 2847 | mlx5_core_destroy_tis(mdev, tisn); |
40ab6a6e AS |
2848 | } |
2849 | ||
cb67b832 | 2850 | int mlx5e_create_tises(struct mlx5e_priv *priv) |
40ab6a6e AS |
2851 | { |
2852 | int err; | |
2853 | int tc; | |
2854 | ||
6bfd390b | 2855 | for (tc = 0; tc < priv->profile->max_tc; tc++) { |
5426a0b2 | 2856 | err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]); |
40ab6a6e AS |
2857 | if (err) |
2858 | goto err_close_tises; | |
2859 | } | |
2860 | ||
2861 | return 0; | |
2862 | ||
2863 | err_close_tises: | |
2864 | for (tc--; tc >= 0; tc--) | |
5426a0b2 | 2865 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2866 | |
2867 | return err; | |
2868 | } | |
2869 | ||
cb67b832 | 2870 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv) |
40ab6a6e AS |
2871 | { |
2872 | int tc; | |
2873 | ||
6bfd390b | 2874 | for (tc = 0; tc < priv->profile->max_tc; tc++) |
5426a0b2 | 2875 | mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]); |
40ab6a6e AS |
2876 | } |
2877 | ||
6a9764ef SM |
2878 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, |
2879 | enum mlx5e_traffic_types tt, | |
2880 | u32 *tirc) | |
f62b8bb8 | 2881 | { |
b50d292b | 2882 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
3191e05f | 2883 | |
6a9764ef | 2884 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
f62b8bb8 | 2885 | |
4cbeaff5 | 2886 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
398f3351 | 2887 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn); |
7b3722fa | 2888 | mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false); |
f62b8bb8 AV |
2889 | } |
2890 | ||
6a9764ef | 2891 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc) |
f62b8bb8 | 2892 | { |
b50d292b | 2893 | MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn); |
1da36696 | 2894 | |
6a9764ef | 2895 | mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc); |
1da36696 TT |
2896 | |
2897 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2898 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2899 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2900 | } | |
2901 | ||
8f493ffd | 2902 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv) |
1da36696 | 2903 | { |
724b2aa1 | 2904 | struct mlx5e_tir *tir; |
f62b8bb8 AV |
2905 | void *tirc; |
2906 | int inlen; | |
7b3722fa | 2907 | int i = 0; |
f62b8bb8 | 2908 | int err; |
1da36696 | 2909 | u32 *in; |
1da36696 | 2910 | int tt; |
f62b8bb8 AV |
2911 | |
2912 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 2913 | in = kvzalloc(inlen, GFP_KERNEL); |
f62b8bb8 AV |
2914 | if (!in) |
2915 | return -ENOMEM; | |
2916 | ||
1da36696 TT |
2917 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
2918 | memset(in, 0, inlen); | |
724b2aa1 | 2919 | tir = &priv->indir_tir[tt]; |
1da36696 | 2920 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 2921 | mlx5e_build_indir_tir_ctx(priv, tt, tirc); |
724b2aa1 | 2922 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
7b3722fa GP |
2923 | if (err) { |
2924 | mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err); | |
2925 | goto err_destroy_inner_tirs; | |
2926 | } | |
f62b8bb8 AV |
2927 | } |
2928 | ||
7b3722fa GP |
2929 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) |
2930 | goto out; | |
2931 | ||
2932 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { | |
2933 | memset(in, 0, inlen); | |
2934 | tir = &priv->inner_indir_tir[i]; | |
2935 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2936 | mlx5e_build_inner_indir_tir_ctx(priv, i, tirc); | |
2937 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); | |
2938 | if (err) { | |
2939 | mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err); | |
2940 | goto err_destroy_inner_tirs; | |
2941 | } | |
2942 | } | |
2943 | ||
2944 | out: | |
6bfd390b HHZ |
2945 | kvfree(in); |
2946 | ||
2947 | return 0; | |
2948 | ||
7b3722fa GP |
2949 | err_destroy_inner_tirs: |
2950 | for (i--; i >= 0; i--) | |
2951 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
2952 | ||
6bfd390b HHZ |
2953 | for (tt--; tt >= 0; tt--) |
2954 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]); | |
2955 | ||
2956 | kvfree(in); | |
2957 | ||
2958 | return err; | |
2959 | } | |
2960 | ||
cb67b832 | 2961 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
2962 | { |
2963 | int nch = priv->profile->max_nch(priv->mdev); | |
2964 | struct mlx5e_tir *tir; | |
2965 | void *tirc; | |
2966 | int inlen; | |
2967 | int err; | |
2968 | u32 *in; | |
2969 | int ix; | |
2970 | ||
2971 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
1b9a07ee | 2972 | in = kvzalloc(inlen, GFP_KERNEL); |
6bfd390b HHZ |
2973 | if (!in) |
2974 | return -ENOMEM; | |
2975 | ||
1da36696 TT |
2976 | for (ix = 0; ix < nch; ix++) { |
2977 | memset(in, 0, inlen); | |
724b2aa1 | 2978 | tir = &priv->direct_tir[ix]; |
1da36696 | 2979 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); |
6a9764ef | 2980 | mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc); |
724b2aa1 | 2981 | err = mlx5e_create_tir(priv->mdev, tir, in, inlen); |
1da36696 TT |
2982 | if (err) |
2983 | goto err_destroy_ch_tirs; | |
2984 | } | |
2985 | ||
2986 | kvfree(in); | |
2987 | ||
f62b8bb8 AV |
2988 | return 0; |
2989 | ||
1da36696 | 2990 | err_destroy_ch_tirs: |
8f493ffd | 2991 | mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err); |
1da36696 | 2992 | for (ix--; ix >= 0; ix--) |
724b2aa1 | 2993 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]); |
1da36696 | 2994 | |
1da36696 | 2995 | kvfree(in); |
f62b8bb8 AV |
2996 | |
2997 | return err; | |
2998 | } | |
2999 | ||
8f493ffd | 3000 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv) |
f62b8bb8 AV |
3001 | { |
3002 | int i; | |
3003 | ||
1da36696 | 3004 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) |
724b2aa1 | 3005 | mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]); |
7b3722fa GP |
3006 | |
3007 | if (!mlx5e_tunnel_inner_ft_supported(priv->mdev)) | |
3008 | return; | |
3009 | ||
3010 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
3011 | mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]); | |
f62b8bb8 AV |
3012 | } |
3013 | ||
cb67b832 | 3014 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv) |
6bfd390b HHZ |
3015 | { |
3016 | int nch = priv->profile->max_nch(priv->mdev); | |
3017 | int i; | |
3018 | ||
3019 | for (i = 0; i < nch; i++) | |
3020 | mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]); | |
3021 | } | |
3022 | ||
102722fc GE |
3023 | static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable) |
3024 | { | |
3025 | int err = 0; | |
3026 | int i; | |
3027 | ||
3028 | for (i = 0; i < chs->num; i++) { | |
3029 | err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable); | |
3030 | if (err) | |
3031 | return err; | |
3032 | } | |
3033 | ||
3034 | return 0; | |
3035 | } | |
3036 | ||
f6d96a20 | 3037 | static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd) |
36350114 GP |
3038 | { |
3039 | int err = 0; | |
3040 | int i; | |
3041 | ||
ff9c852f SM |
3042 | for (i = 0; i < chs->num; i++) { |
3043 | err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd); | |
36350114 GP |
3044 | if (err) |
3045 | return err; | |
3046 | } | |
3047 | ||
3048 | return 0; | |
3049 | } | |
3050 | ||
0cf0f6d3 JP |
3051 | static int mlx5e_setup_tc_mqprio(struct net_device *netdev, |
3052 | struct tc_mqprio_qopt *mqprio) | |
08fb1dac SM |
3053 | { |
3054 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
6f9485af | 3055 | struct mlx5e_channels new_channels = {}; |
0cf0f6d3 | 3056 | u8 tc = mqprio->num_tc; |
08fb1dac SM |
3057 | int err = 0; |
3058 | ||
0cf0f6d3 JP |
3059 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
3060 | ||
08fb1dac SM |
3061 | if (tc && tc != MLX5E_MAX_NUM_TC) |
3062 | return -EINVAL; | |
3063 | ||
3064 | mutex_lock(&priv->state_lock); | |
3065 | ||
6f9485af SM |
3066 | new_channels.params = priv->channels.params; |
3067 | new_channels.params.num_tc = tc ? tc : 1; | |
08fb1dac | 3068 | |
20b6a1c7 | 3069 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) { |
6f9485af SM |
3070 | priv->channels.params = new_channels.params; |
3071 | goto out; | |
3072 | } | |
08fb1dac | 3073 | |
6f9485af SM |
3074 | err = mlx5e_open_channels(priv, &new_channels); |
3075 | if (err) | |
3076 | goto out; | |
08fb1dac | 3077 | |
2e20a151 | 3078 | mlx5e_switch_priv_channels(priv, &new_channels, NULL); |
6f9485af | 3079 | out: |
08fb1dac | 3080 | mutex_unlock(&priv->state_lock); |
08fb1dac SM |
3081 | return err; |
3082 | } | |
3083 | ||
e80541ec | 3084 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba | 3085 | static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv, |
0cf0f6d3 | 3086 | struct tc_cls_flower_offload *cls_flower) |
08fb1dac | 3087 | { |
d6c862ba | 3088 | if (cls_flower->common.chain_index) |
0cf0f6d3 | 3089 | return -EOPNOTSUPP; |
e8f887ac | 3090 | |
0cf0f6d3 JP |
3091 | switch (cls_flower->command) { |
3092 | case TC_CLSFLOWER_REPLACE: | |
5fd9fc4e | 3093 | return mlx5e_configure_flower(priv, cls_flower); |
0cf0f6d3 JP |
3094 | case TC_CLSFLOWER_DESTROY: |
3095 | return mlx5e_delete_flower(priv, cls_flower); | |
3096 | case TC_CLSFLOWER_STATS: | |
3097 | return mlx5e_stats_flower(priv, cls_flower); | |
3098 | default: | |
a5fcf8a6 | 3099 | return -EOPNOTSUPP; |
0cf0f6d3 JP |
3100 | } |
3101 | } | |
d6c862ba JP |
3102 | |
3103 | int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, | |
3104 | void *cb_priv) | |
3105 | { | |
3106 | struct mlx5e_priv *priv = cb_priv; | |
3107 | ||
44ae12a7 JP |
3108 | if (!tc_can_offload(priv->netdev)) |
3109 | return -EOPNOTSUPP; | |
3110 | ||
d6c862ba JP |
3111 | switch (type) { |
3112 | case TC_SETUP_CLSFLOWER: | |
3113 | return mlx5e_setup_tc_cls_flower(priv, type_data); | |
3114 | default: | |
3115 | return -EOPNOTSUPP; | |
3116 | } | |
3117 | } | |
3118 | ||
3119 | static int mlx5e_setup_tc_block(struct net_device *dev, | |
3120 | struct tc_block_offload *f) | |
3121 | { | |
3122 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3123 | ||
3124 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) | |
3125 | return -EOPNOTSUPP; | |
3126 | ||
3127 | switch (f->command) { | |
3128 | case TC_BLOCK_BIND: | |
3129 | return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb, | |
3130 | priv, priv); | |
3131 | case TC_BLOCK_UNBIND: | |
3132 | tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb, | |
3133 | priv); | |
3134 | return 0; | |
3135 | default: | |
3136 | return -EOPNOTSUPP; | |
3137 | } | |
3138 | } | |
e80541ec | 3139 | #endif |
a5fcf8a6 | 3140 | |
717503b9 JP |
3141 | int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type, |
3142 | void *type_data) | |
0cf0f6d3 | 3143 | { |
2572ac53 | 3144 | switch (type) { |
fde6af47 | 3145 | #ifdef CONFIG_MLX5_ESWITCH |
d6c862ba JP |
3146 | case TC_SETUP_BLOCK: |
3147 | return mlx5e_setup_tc_block(dev, type_data); | |
fde6af47 | 3148 | #endif |
575ed7d3 | 3149 | case TC_SETUP_QDISC_MQPRIO: |
de4784ca | 3150 | return mlx5e_setup_tc_mqprio(dev, type_data); |
e8f887ac AV |
3151 | default: |
3152 | return -EOPNOTSUPP; | |
3153 | } | |
08fb1dac SM |
3154 | } |
3155 | ||
bc1f4470 | 3156 | static void |
f62b8bb8 AV |
3157 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) |
3158 | { | |
3159 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 3160 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 3161 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 3162 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 3163 | |
370bad0f OG |
3164 | if (mlx5e_is_uplink_rep(priv)) { |
3165 | stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok); | |
3166 | stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok); | |
3167 | stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok); | |
3168 | stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok); | |
3169 | } else { | |
3170 | stats->rx_packets = sstats->rx_packets; | |
3171 | stats->rx_bytes = sstats->rx_bytes; | |
3172 | stats->tx_packets = sstats->tx_packets; | |
3173 | stats->tx_bytes = sstats->tx_bytes; | |
3174 | stats->tx_dropped = sstats->tx_queue_dropped; | |
3175 | } | |
269e6b3a GP |
3176 | |
3177 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
269e6b3a GP |
3178 | |
3179 | stats->rx_length_errors = | |
9218b44d GP |
3180 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
3181 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
3182 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 3183 | stats->rx_crc_errors = |
9218b44d GP |
3184 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
3185 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
3186 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a GP |
3187 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
3188 | stats->rx_frame_errors; | |
3189 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
3190 | ||
3191 | /* vport multicast also counts packets that are dropped due to steering | |
3192 | * or rx out of buffer | |
3193 | */ | |
9218b44d GP |
3194 | stats->multicast = |
3195 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
3196 | } |
3197 | ||
3198 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
3199 | { | |
3200 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3201 | ||
7bb29755 | 3202 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3203 | } |
3204 | ||
3205 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
3206 | { | |
3207 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3208 | struct sockaddr *saddr = addr; | |
3209 | ||
3210 | if (!is_valid_ether_addr(saddr->sa_data)) | |
3211 | return -EADDRNOTAVAIL; | |
3212 | ||
3213 | netif_addr_lock_bh(netdev); | |
3214 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
3215 | netif_addr_unlock_bh(netdev); | |
3216 | ||
7bb29755 | 3217 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3218 | |
3219 | return 0; | |
3220 | } | |
3221 | ||
0e405443 GP |
3222 | #define MLX5E_SET_FEATURE(netdev, feature, enable) \ |
3223 | do { \ | |
3224 | if (enable) \ | |
3225 | netdev->features |= feature; \ | |
3226 | else \ | |
3227 | netdev->features &= ~feature; \ | |
3228 | } while (0) | |
3229 | ||
3230 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
3231 | ||
3232 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
3233 | { |
3234 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2e20a151 SM |
3235 | struct mlx5e_channels new_channels = {}; |
3236 | int err = 0; | |
3237 | bool reset; | |
f62b8bb8 AV |
3238 | |
3239 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 3240 | |
2e20a151 SM |
3241 | reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST); |
3242 | reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); | |
98e81b0a | 3243 | |
2e20a151 SM |
3244 | new_channels.params = priv->channels.params; |
3245 | new_channels.params.lro_en = enable; | |
3246 | ||
3247 | if (!reset) { | |
3248 | priv->channels.params = new_channels.params; | |
3249 | err = mlx5e_modify_tirs_lro(priv); | |
3250 | goto out; | |
98e81b0a | 3251 | } |
f62b8bb8 | 3252 | |
2e20a151 SM |
3253 | err = mlx5e_open_channels(priv, &new_channels); |
3254 | if (err) | |
3255 | goto out; | |
0e405443 | 3256 | |
2e20a151 SM |
3257 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro); |
3258 | out: | |
9b37b07f | 3259 | mutex_unlock(&priv->state_lock); |
0e405443 GP |
3260 | return err; |
3261 | } | |
3262 | ||
2b52a283 | 3263 | static int set_feature_cvlan_filter(struct net_device *netdev, bool enable) |
0e405443 GP |
3264 | { |
3265 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3266 | ||
3267 | if (enable) | |
2b52a283 | 3268 | mlx5e_enable_cvlan_filter(priv); |
0e405443 | 3269 | else |
2b52a283 | 3270 | mlx5e_disable_cvlan_filter(priv); |
0e405443 GP |
3271 | |
3272 | return 0; | |
3273 | } | |
3274 | ||
3275 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
3276 | { | |
3277 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 3278 | |
0e405443 | 3279 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
3280 | netdev_err(netdev, |
3281 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
3282 | return -EINVAL; | |
3283 | } | |
3284 | ||
0e405443 GP |
3285 | return 0; |
3286 | } | |
3287 | ||
94cb1ebb EBE |
3288 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
3289 | { | |
3290 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3291 | struct mlx5_core_dev *mdev = priv->mdev; | |
3292 | ||
3293 | return mlx5_set_port_fcs(mdev, !enable); | |
3294 | } | |
3295 | ||
102722fc GE |
3296 | static int set_feature_rx_fcs(struct net_device *netdev, bool enable) |
3297 | { | |
3298 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3299 | int err; | |
3300 | ||
3301 | mutex_lock(&priv->state_lock); | |
3302 | ||
3303 | priv->channels.params.scatter_fcs_en = enable; | |
3304 | err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable); | |
3305 | if (err) | |
3306 | priv->channels.params.scatter_fcs_en = !enable; | |
3307 | ||
3308 | mutex_unlock(&priv->state_lock); | |
3309 | ||
3310 | return err; | |
3311 | } | |
3312 | ||
36350114 GP |
3313 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
3314 | { | |
3315 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
ff9c852f | 3316 | int err = 0; |
36350114 GP |
3317 | |
3318 | mutex_lock(&priv->state_lock); | |
3319 | ||
6a9764ef | 3320 | priv->channels.params.vlan_strip_disable = !enable; |
ff9c852f SM |
3321 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
3322 | goto unlock; | |
3323 | ||
3324 | err = mlx5e_modify_channels_vsd(&priv->channels, !enable); | |
36350114 | 3325 | if (err) |
6a9764ef | 3326 | priv->channels.params.vlan_strip_disable = enable; |
36350114 | 3327 | |
ff9c852f | 3328 | unlock: |
36350114 GP |
3329 | mutex_unlock(&priv->state_lock); |
3330 | ||
3331 | return err; | |
3332 | } | |
3333 | ||
45bf454a MG |
3334 | #ifdef CONFIG_RFS_ACCEL |
3335 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
3336 | { | |
3337 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3338 | int err; | |
3339 | ||
3340 | if (enable) | |
3341 | err = mlx5e_arfs_enable(priv); | |
3342 | else | |
3343 | err = mlx5e_arfs_disable(priv); | |
3344 | ||
3345 | return err; | |
3346 | } | |
3347 | #endif | |
3348 | ||
0e405443 GP |
3349 | static int mlx5e_handle_feature(struct net_device *netdev, |
3350 | netdev_features_t wanted_features, | |
3351 | netdev_features_t feature, | |
3352 | mlx5e_feature_handler feature_handler) | |
3353 | { | |
3354 | netdev_features_t changes = wanted_features ^ netdev->features; | |
3355 | bool enable = !!(wanted_features & feature); | |
3356 | int err; | |
3357 | ||
3358 | if (!(changes & feature)) | |
3359 | return 0; | |
3360 | ||
3361 | err = feature_handler(netdev, enable); | |
3362 | if (err) { | |
b20eab15 GP |
3363 | netdev_err(netdev, "%s feature %pNF failed, err %d\n", |
3364 | enable ? "Enable" : "Disable", &feature, err); | |
0e405443 GP |
3365 | return err; |
3366 | } | |
3367 | ||
3368 | MLX5E_SET_FEATURE(netdev, feature, enable); | |
3369 | return 0; | |
3370 | } | |
3371 | ||
3372 | static int mlx5e_set_features(struct net_device *netdev, | |
3373 | netdev_features_t features) | |
3374 | { | |
3375 | int err; | |
3376 | ||
3377 | err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO, | |
3378 | set_feature_lro); | |
3379 | err |= mlx5e_handle_feature(netdev, features, | |
3380 | NETIF_F_HW_VLAN_CTAG_FILTER, | |
2b52a283 | 3381 | set_feature_cvlan_filter); |
0e405443 GP |
3382 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC, |
3383 | set_feature_tc_num_filters); | |
94cb1ebb EBE |
3384 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL, |
3385 | set_feature_rx_all); | |
102722fc GE |
3386 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS, |
3387 | set_feature_rx_fcs); | |
36350114 GP |
3388 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX, |
3389 | set_feature_rx_vlan); | |
45bf454a MG |
3390 | #ifdef CONFIG_RFS_ACCEL |
3391 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE, | |
3392 | set_feature_arfs); | |
3393 | #endif | |
0e405443 GP |
3394 | |
3395 | return err ? -EINVAL : 0; | |
f62b8bb8 AV |
3396 | } |
3397 | ||
7d92d580 GP |
3398 | static netdev_features_t mlx5e_fix_features(struct net_device *netdev, |
3399 | netdev_features_t features) | |
3400 | { | |
3401 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3402 | ||
3403 | mutex_lock(&priv->state_lock); | |
3404 | if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) { | |
3405 | /* HW strips the outer C-tag header, this is a problem | |
3406 | * for S-tag traffic. | |
3407 | */ | |
3408 | features &= ~NETIF_F_HW_VLAN_CTAG_RX; | |
3409 | if (!priv->channels.params.vlan_strip_disable) | |
3410 | netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n"); | |
3411 | } | |
3412 | mutex_unlock(&priv->state_lock); | |
3413 | ||
3414 | return features; | |
3415 | } | |
3416 | ||
f62b8bb8 AV |
3417 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
3418 | { | |
3419 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2e20a151 SM |
3420 | struct mlx5e_channels new_channels = {}; |
3421 | int curr_mtu; | |
98e81b0a | 3422 | int err = 0; |
506753b0 | 3423 | bool reset; |
f62b8bb8 | 3424 | |
f62b8bb8 | 3425 | mutex_lock(&priv->state_lock); |
98e81b0a | 3426 | |
6a9764ef SM |
3427 | reset = !priv->channels.params.lro_en && |
3428 | (priv->channels.params.rq_wq_type != | |
506753b0 TT |
3429 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
3430 | ||
2e20a151 | 3431 | reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state); |
98e81b0a | 3432 | |
2e20a151 | 3433 | curr_mtu = netdev->mtu; |
f62b8bb8 | 3434 | netdev->mtu = new_mtu; |
98e81b0a | 3435 | |
2e20a151 SM |
3436 | if (!reset) { |
3437 | mlx5e_set_dev_port_mtu(priv); | |
3438 | goto out; | |
3439 | } | |
98e81b0a | 3440 | |
2e20a151 SM |
3441 | new_channels.params = priv->channels.params; |
3442 | err = mlx5e_open_channels(priv, &new_channels); | |
3443 | if (err) { | |
3444 | netdev->mtu = curr_mtu; | |
3445 | goto out; | |
3446 | } | |
3447 | ||
3448 | mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu); | |
f62b8bb8 | 3449 | |
2e20a151 SM |
3450 | out: |
3451 | mutex_unlock(&priv->state_lock); | |
f62b8bb8 AV |
3452 | return err; |
3453 | } | |
3454 | ||
7c39afb3 FD |
3455 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr) |
3456 | { | |
3457 | struct hwtstamp_config config; | |
3458 | int err; | |
3459 | ||
3460 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3461 | return -EOPNOTSUPP; | |
3462 | ||
3463 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
3464 | return -EFAULT; | |
3465 | ||
3466 | /* TX HW timestamp */ | |
3467 | switch (config.tx_type) { | |
3468 | case HWTSTAMP_TX_OFF: | |
3469 | case HWTSTAMP_TX_ON: | |
3470 | break; | |
3471 | default: | |
3472 | return -ERANGE; | |
3473 | } | |
3474 | ||
3475 | mutex_lock(&priv->state_lock); | |
3476 | /* RX HW timestamp */ | |
3477 | switch (config.rx_filter) { | |
3478 | case HWTSTAMP_FILTER_NONE: | |
3479 | /* Reset CQE compression to Admin default */ | |
3480 | mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def); | |
3481 | break; | |
3482 | case HWTSTAMP_FILTER_ALL: | |
3483 | case HWTSTAMP_FILTER_SOME: | |
3484 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3485 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
3486 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3487 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3488 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3489 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3490 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3491 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3492 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3493 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3494 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3495 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3496 | case HWTSTAMP_FILTER_NTP_ALL: | |
3497 | /* Disable CQE compression */ | |
3498 | netdev_warn(priv->netdev, "Disabling cqe compression"); | |
3499 | err = mlx5e_modify_rx_cqe_compression_locked(priv, false); | |
3500 | if (err) { | |
3501 | netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err); | |
3502 | mutex_unlock(&priv->state_lock); | |
3503 | return err; | |
3504 | } | |
3505 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
3506 | break; | |
3507 | default: | |
3508 | mutex_unlock(&priv->state_lock); | |
3509 | return -ERANGE; | |
3510 | } | |
3511 | ||
3512 | memcpy(&priv->tstamp, &config, sizeof(config)); | |
3513 | mutex_unlock(&priv->state_lock); | |
3514 | ||
3515 | return copy_to_user(ifr->ifr_data, &config, | |
3516 | sizeof(config)) ? -EFAULT : 0; | |
3517 | } | |
3518 | ||
3519 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr) | |
3520 | { | |
3521 | struct hwtstamp_config *cfg = &priv->tstamp; | |
3522 | ||
3523 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
3524 | return -EOPNOTSUPP; | |
3525 | ||
3526 | return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0; | |
3527 | } | |
3528 | ||
ef9814de EBE |
3529 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3530 | { | |
1170fbd8 FD |
3531 | struct mlx5e_priv *priv = netdev_priv(dev); |
3532 | ||
ef9814de EBE |
3533 | switch (cmd) { |
3534 | case SIOCSHWTSTAMP: | |
1170fbd8 | 3535 | return mlx5e_hwstamp_set(priv, ifr); |
ef9814de | 3536 | case SIOCGHWTSTAMP: |
1170fbd8 | 3537 | return mlx5e_hwstamp_get(priv, ifr); |
ef9814de EBE |
3538 | default: |
3539 | return -EOPNOTSUPP; | |
3540 | } | |
3541 | } | |
3542 | ||
e80541ec | 3543 | #ifdef CONFIG_MLX5_ESWITCH |
66e49ded SM |
3544 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
3545 | { | |
3546 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3547 | struct mlx5_core_dev *mdev = priv->mdev; | |
3548 | ||
3549 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
3550 | } | |
3551 | ||
79aab093 MS |
3552 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos, |
3553 | __be16 vlan_proto) | |
66e49ded SM |
3554 | { |
3555 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3556 | struct mlx5_core_dev *mdev = priv->mdev; | |
3557 | ||
79aab093 MS |
3558 | if (vlan_proto != htons(ETH_P_8021Q)) |
3559 | return -EPROTONOSUPPORT; | |
3560 | ||
66e49ded SM |
3561 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, |
3562 | vlan, qos); | |
3563 | } | |
3564 | ||
f942380c MHY |
3565 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
3566 | { | |
3567 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3568 | struct mlx5_core_dev *mdev = priv->mdev; | |
3569 | ||
3570 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
3571 | } | |
3572 | ||
1edc57e2 MHY |
3573 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
3574 | { | |
3575 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3576 | struct mlx5_core_dev *mdev = priv->mdev; | |
3577 | ||
3578 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
3579 | } | |
bd77bf1c MHY |
3580 | |
3581 | static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, | |
3582 | int max_tx_rate) | |
3583 | { | |
3584 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3585 | struct mlx5_core_dev *mdev = priv->mdev; | |
3586 | ||
bd77bf1c | 3587 | return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1, |
c9497c98 | 3588 | max_tx_rate, min_tx_rate); |
bd77bf1c MHY |
3589 | } |
3590 | ||
66e49ded SM |
3591 | static int mlx5_vport_link2ifla(u8 esw_link) |
3592 | { | |
3593 | switch (esw_link) { | |
3594 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
3595 | return IFLA_VF_LINK_STATE_DISABLE; | |
3596 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
3597 | return IFLA_VF_LINK_STATE_ENABLE; | |
3598 | } | |
3599 | return IFLA_VF_LINK_STATE_AUTO; | |
3600 | } | |
3601 | ||
3602 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
3603 | { | |
3604 | switch (ifla_link) { | |
3605 | case IFLA_VF_LINK_STATE_DISABLE: | |
3606 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
3607 | case IFLA_VF_LINK_STATE_ENABLE: | |
3608 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
3609 | } | |
3610 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
3611 | } | |
3612 | ||
3613 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
3614 | int link_state) | |
3615 | { | |
3616 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3617 | struct mlx5_core_dev *mdev = priv->mdev; | |
3618 | ||
3619 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
3620 | mlx5_ifla_link2vport(link_state)); | |
3621 | } | |
3622 | ||
3623 | static int mlx5e_get_vf_config(struct net_device *dev, | |
3624 | int vf, struct ifla_vf_info *ivi) | |
3625 | { | |
3626 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3627 | struct mlx5_core_dev *mdev = priv->mdev; | |
3628 | int err; | |
3629 | ||
3630 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
3631 | if (err) | |
3632 | return err; | |
3633 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
3634 | return 0; | |
3635 | } | |
3636 | ||
3637 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
3638 | int vf, struct ifla_vf_stats *vf_stats) | |
3639 | { | |
3640 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3641 | struct mlx5_core_dev *mdev = priv->mdev; | |
3642 | ||
3643 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
3644 | vf_stats); | |
3645 | } | |
e80541ec | 3646 | #endif |
66e49ded | 3647 | |
1ad9a00a PB |
3648 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
3649 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3650 | { |
3651 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3652 | ||
974c3f30 AD |
3653 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3654 | return; | |
3655 | ||
b3f63c3d MF |
3656 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3657 | return; | |
3658 | ||
974c3f30 | 3659 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1); |
b3f63c3d MF |
3660 | } |
3661 | ||
1ad9a00a PB |
3662 | static void mlx5e_del_vxlan_port(struct net_device *netdev, |
3663 | struct udp_tunnel_info *ti) | |
b3f63c3d MF |
3664 | { |
3665 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3666 | ||
974c3f30 AD |
3667 | if (ti->type != UDP_TUNNEL_TYPE_VXLAN) |
3668 | return; | |
3669 | ||
b3f63c3d MF |
3670 | if (!mlx5e_vxlan_allowed(priv->mdev)) |
3671 | return; | |
3672 | ||
974c3f30 | 3673 | mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0); |
b3f63c3d MF |
3674 | } |
3675 | ||
27299841 GP |
3676 | static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv, |
3677 | struct sk_buff *skb, | |
3678 | netdev_features_t features) | |
b3f63c3d | 3679 | { |
2989ad1e | 3680 | unsigned int offset = 0; |
b3f63c3d | 3681 | struct udphdr *udph; |
27299841 GP |
3682 | u8 proto; |
3683 | u16 port; | |
b3f63c3d MF |
3684 | |
3685 | switch (vlan_get_protocol(skb)) { | |
3686 | case htons(ETH_P_IP): | |
3687 | proto = ip_hdr(skb)->protocol; | |
3688 | break; | |
3689 | case htons(ETH_P_IPV6): | |
2989ad1e | 3690 | proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL); |
b3f63c3d MF |
3691 | break; |
3692 | default: | |
3693 | goto out; | |
3694 | } | |
3695 | ||
27299841 GP |
3696 | switch (proto) { |
3697 | case IPPROTO_GRE: | |
3698 | return features; | |
3699 | case IPPROTO_UDP: | |
b3f63c3d MF |
3700 | udph = udp_hdr(skb); |
3701 | port = be16_to_cpu(udph->dest); | |
b3f63c3d | 3702 | |
27299841 GP |
3703 | /* Verify if UDP port is being offloaded by HW */ |
3704 | if (mlx5e_vxlan_lookup_port(priv, port)) | |
3705 | return features; | |
3706 | } | |
b3f63c3d MF |
3707 | |
3708 | out: | |
3709 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
3710 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
3711 | } | |
3712 | ||
3713 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
3714 | struct net_device *netdev, | |
3715 | netdev_features_t features) | |
3716 | { | |
3717 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3718 | ||
3719 | features = vlan_features_check(skb, features); | |
3720 | features = vxlan_features_check(skb, features); | |
3721 | ||
2ac9cfe7 IT |
3722 | #ifdef CONFIG_MLX5_EN_IPSEC |
3723 | if (mlx5e_ipsec_feature_check(skb, netdev, features)) | |
3724 | return features; | |
3725 | #endif | |
3726 | ||
b3f63c3d MF |
3727 | /* Validate if the tunneled packet is being offloaded by HW */ |
3728 | if (skb->encapsulation && | |
3729 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
27299841 | 3730 | return mlx5e_tunnel_features_check(priv, skb, features); |
b3f63c3d MF |
3731 | |
3732 | return features; | |
3733 | } | |
3734 | ||
3947ca18 DJ |
3735 | static void mlx5e_tx_timeout(struct net_device *dev) |
3736 | { | |
3737 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3738 | bool sched_work = false; | |
3739 | int i; | |
3740 | ||
3741 | netdev_err(dev, "TX timeout detected\n"); | |
3742 | ||
6a9764ef | 3743 | for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) { |
acc6c595 | 3744 | struct mlx5e_txqsq *sq = priv->txq2sq[i]; |
3947ca18 | 3745 | |
2c1ccc99 | 3746 | if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i))) |
3947ca18 DJ |
3747 | continue; |
3748 | sched_work = true; | |
c0f1147d | 3749 | clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state); |
3947ca18 DJ |
3750 | netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n", |
3751 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc); | |
3752 | } | |
3753 | ||
3754 | if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
3755 | schedule_work(&priv->tx_timeout_work); | |
3756 | } | |
3757 | ||
86994156 RS |
3758 | static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog) |
3759 | { | |
3760 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
3761 | struct bpf_prog *old_prog; | |
3762 | int err = 0; | |
3763 | bool reset, was_opened; | |
3764 | int i; | |
3765 | ||
3766 | mutex_lock(&priv->state_lock); | |
3767 | ||
3768 | if ((netdev->features & NETIF_F_LRO) && prog) { | |
3769 | netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n"); | |
3770 | err = -EINVAL; | |
3771 | goto unlock; | |
3772 | } | |
3773 | ||
547eede0 IT |
3774 | if ((netdev->features & NETIF_F_HW_ESP) && prog) { |
3775 | netdev_warn(netdev, "can't set XDP with IPSec offload\n"); | |
3776 | err = -EINVAL; | |
3777 | goto unlock; | |
3778 | } | |
3779 | ||
86994156 RS |
3780 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
3781 | /* no need for full reset when exchanging programs */ | |
6a9764ef | 3782 | reset = (!priv->channels.params.xdp_prog || !prog); |
86994156 RS |
3783 | |
3784 | if (was_opened && reset) | |
3785 | mlx5e_close_locked(netdev); | |
c54c0629 DB |
3786 | if (was_opened && !reset) { |
3787 | /* num_channels is invariant here, so we can take the | |
3788 | * batched reference right upfront. | |
3789 | */ | |
6a9764ef | 3790 | prog = bpf_prog_add(prog, priv->channels.num); |
c54c0629 DB |
3791 | if (IS_ERR(prog)) { |
3792 | err = PTR_ERR(prog); | |
3793 | goto unlock; | |
3794 | } | |
3795 | } | |
86994156 | 3796 | |
c54c0629 DB |
3797 | /* exchange programs, extra prog reference we got from caller |
3798 | * as long as we don't fail from this point onwards. | |
3799 | */ | |
6a9764ef | 3800 | old_prog = xchg(&priv->channels.params.xdp_prog, prog); |
86994156 RS |
3801 | if (old_prog) |
3802 | bpf_prog_put(old_prog); | |
3803 | ||
3804 | if (reset) /* change RQ type according to priv->xdp_prog */ | |
6a9764ef | 3805 | mlx5e_set_rq_params(priv->mdev, &priv->channels.params); |
86994156 RS |
3806 | |
3807 | if (was_opened && reset) | |
3808 | mlx5e_open_locked(netdev); | |
3809 | ||
3810 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset) | |
3811 | goto unlock; | |
3812 | ||
3813 | /* exchanging programs w/o reset, we update ref counts on behalf | |
3814 | * of the channels RQs here. | |
3815 | */ | |
ff9c852f SM |
3816 | for (i = 0; i < priv->channels.num; i++) { |
3817 | struct mlx5e_channel *c = priv->channels.c[i]; | |
86994156 | 3818 | |
c0f1147d | 3819 | clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 RS |
3820 | napi_synchronize(&c->napi); |
3821 | /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */ | |
3822 | ||
3823 | old_prog = xchg(&c->rq.xdp_prog, prog); | |
3824 | ||
c0f1147d | 3825 | set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state); |
86994156 | 3826 | /* napi_schedule in case we have missed anything */ |
86994156 RS |
3827 | napi_schedule(&c->napi); |
3828 | ||
3829 | if (old_prog) | |
3830 | bpf_prog_put(old_prog); | |
3831 | } | |
3832 | ||
3833 | unlock: | |
3834 | mutex_unlock(&priv->state_lock); | |
3835 | return err; | |
3836 | } | |
3837 | ||
821b2e29 | 3838 | static u32 mlx5e_xdp_query(struct net_device *dev) |
86994156 RS |
3839 | { |
3840 | struct mlx5e_priv *priv = netdev_priv(dev); | |
821b2e29 MKL |
3841 | const struct bpf_prog *xdp_prog; |
3842 | u32 prog_id = 0; | |
86994156 | 3843 | |
821b2e29 MKL |
3844 | mutex_lock(&priv->state_lock); |
3845 | xdp_prog = priv->channels.params.xdp_prog; | |
3846 | if (xdp_prog) | |
3847 | prog_id = xdp_prog->aux->id; | |
3848 | mutex_unlock(&priv->state_lock); | |
3849 | ||
3850 | return prog_id; | |
86994156 RS |
3851 | } |
3852 | ||
f4e63525 | 3853 | static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp) |
86994156 RS |
3854 | { |
3855 | switch (xdp->command) { | |
3856 | case XDP_SETUP_PROG: | |
3857 | return mlx5e_xdp_set(dev, xdp->prog); | |
3858 | case XDP_QUERY_PROG: | |
821b2e29 MKL |
3859 | xdp->prog_id = mlx5e_xdp_query(dev); |
3860 | xdp->prog_attached = !!xdp->prog_id; | |
86994156 RS |
3861 | return 0; |
3862 | default: | |
3863 | return -EINVAL; | |
3864 | } | |
3865 | } | |
3866 | ||
80378384 CO |
3867 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3868 | /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without | |
3869 | * reenabling interrupts. | |
3870 | */ | |
3871 | static void mlx5e_netpoll(struct net_device *dev) | |
3872 | { | |
3873 | struct mlx5e_priv *priv = netdev_priv(dev); | |
ff9c852f SM |
3874 | struct mlx5e_channels *chs = &priv->channels; |
3875 | ||
80378384 CO |
3876 | int i; |
3877 | ||
ff9c852f SM |
3878 | for (i = 0; i < chs->num; i++) |
3879 | napi_schedule(&chs->c[i]->napi); | |
80378384 CO |
3880 | } |
3881 | #endif | |
3882 | ||
e80541ec | 3883 | static const struct net_device_ops mlx5e_netdev_ops = { |
f62b8bb8 AV |
3884 | .ndo_open = mlx5e_open, |
3885 | .ndo_stop = mlx5e_close, | |
3886 | .ndo_start_xmit = mlx5e_xmit, | |
0cf0f6d3 | 3887 | .ndo_setup_tc = mlx5e_setup_tc, |
08fb1dac | 3888 | .ndo_select_queue = mlx5e_select_queue, |
f62b8bb8 AV |
3889 | .ndo_get_stats64 = mlx5e_get_stats, |
3890 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
3891 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
3892 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
3893 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 3894 | .ndo_set_features = mlx5e_set_features, |
7d92d580 | 3895 | .ndo_fix_features = mlx5e_fix_features, |
b0eed40e SM |
3896 | .ndo_change_mtu = mlx5e_change_mtu, |
3897 | .ndo_do_ioctl = mlx5e_ioctl, | |
507f0c81 | 3898 | .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate, |
706b3583 SM |
3899 | .ndo_udp_tunnel_add = mlx5e_add_vxlan_port, |
3900 | .ndo_udp_tunnel_del = mlx5e_del_vxlan_port, | |
3901 | .ndo_features_check = mlx5e_features_check, | |
45bf454a MG |
3902 | #ifdef CONFIG_RFS_ACCEL |
3903 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
3904 | #endif | |
3947ca18 | 3905 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f4e63525 | 3906 | .ndo_bpf = mlx5e_xdp, |
80378384 CO |
3907 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3908 | .ndo_poll_controller = mlx5e_netpoll, | |
3909 | #endif | |
e80541ec | 3910 | #ifdef CONFIG_MLX5_ESWITCH |
706b3583 | 3911 | /* SRIOV E-Switch NDOs */ |
b0eed40e SM |
3912 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
3913 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 3914 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 3915 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
bd77bf1c | 3916 | .ndo_set_vf_rate = mlx5e_set_vf_rate, |
b0eed40e SM |
3917 | .ndo_get_vf_config = mlx5e_get_vf_config, |
3918 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
3919 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
370bad0f OG |
3920 | .ndo_has_offload_stats = mlx5e_has_offload_stats, |
3921 | .ndo_get_offload_stats = mlx5e_get_offload_stats, | |
e80541ec | 3922 | #endif |
f62b8bb8 AV |
3923 | }; |
3924 | ||
3925 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
3926 | { | |
3927 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
9eb78923 | 3928 | return -EOPNOTSUPP; |
f62b8bb8 AV |
3929 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || |
3930 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
3931 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
3932 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
3933 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
3934 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
3935 | MLX5_CAP_FLOWTABLE(mdev, | |
3936 | flow_table_properties_nic_receive.max_ft_level) | |
3937 | < 3) { | |
f62b8bb8 AV |
3938 | mlx5_core_warn(mdev, |
3939 | "Not creating net device, some required device capabilities are missing\n"); | |
9eb78923 | 3940 | return -EOPNOTSUPP; |
f62b8bb8 | 3941 | } |
66189961 TT |
3942 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
3943 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 | 3944 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
3e432ab6 | 3945 | mlx5_core_warn(mdev, "CQ moderation is not supported\n"); |
66189961 | 3946 | |
f62b8bb8 AV |
3947 | return 0; |
3948 | } | |
3949 | ||
58d52291 AS |
3950 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
3951 | { | |
3952 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
3953 | ||
3954 | return bf_buf_size - | |
3955 | sizeof(struct mlx5e_tx_wqe) + | |
3956 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
3957 | } | |
3958 | ||
d4b6c488 | 3959 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba TT |
3960 | int num_channels) |
3961 | { | |
3962 | int i; | |
3963 | ||
3964 | for (i = 0; i < len; i++) | |
3965 | indirection_rqt[i] = i % num_channels; | |
3966 | } | |
3967 | ||
b797a684 SM |
3968 | static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) |
3969 | { | |
3970 | enum pcie_link_width width; | |
3971 | enum pci_bus_speed speed; | |
3972 | int err = 0; | |
3973 | ||
3974 | err = pcie_get_minimum_link(mdev->pdev, &speed, &width); | |
3975 | if (err) | |
3976 | return err; | |
3977 | ||
3978 | if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) | |
3979 | return -EINVAL; | |
3980 | ||
3981 | switch (speed) { | |
3982 | case PCIE_SPEED_2_5GT: | |
3983 | *pci_bw = 2500 * width; | |
3984 | break; | |
3985 | case PCIE_SPEED_5_0GT: | |
3986 | *pci_bw = 5000 * width; | |
3987 | break; | |
3988 | case PCIE_SPEED_8_0GT: | |
3989 | *pci_bw = 8000 * width; | |
3990 | break; | |
3991 | default: | |
3992 | return -EINVAL; | |
3993 | } | |
3994 | ||
3995 | return 0; | |
3996 | } | |
3997 | ||
3998 | static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) | |
3999 | { | |
4000 | return (link_speed && pci_bw && | |
4001 | (pci_bw < 40000) && (pci_bw < link_speed)); | |
4002 | } | |
4003 | ||
0f6e4cf6 EBE |
4004 | static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw) |
4005 | { | |
4006 | return !(link_speed && pci_bw && | |
4007 | (pci_bw <= 16000) && (pci_bw < link_speed)); | |
4008 | } | |
4009 | ||
0088cbbc TG |
4010 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
4011 | { | |
4012 | params->tx_cq_moderation.cq_period_mode = cq_period_mode; | |
4013 | ||
4014 | params->tx_cq_moderation.pkts = | |
4015 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
4016 | params->tx_cq_moderation.usec = | |
4017 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
4018 | ||
4019 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
4020 | params->tx_cq_moderation.usec = | |
4021 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE; | |
4022 | ||
4023 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
4024 | params->tx_cq_moderation.cq_period_mode == | |
4025 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
4026 | } | |
4027 | ||
9908aa29 TT |
4028 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode) |
4029 | { | |
0088cbbc | 4030 | params->rx_cq_moderation.cq_period_mode = cq_period_mode; |
9908aa29 TT |
4031 | |
4032 | params->rx_cq_moderation.pkts = | |
4033 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
4034 | params->rx_cq_moderation.usec = | |
0088cbbc | 4035 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; |
9908aa29 TT |
4036 | |
4037 | if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE) | |
4038 | params->rx_cq_moderation.usec = | |
4039 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE; | |
6a9764ef | 4040 | |
457fcd8a SM |
4041 | if (params->rx_am_enabled) |
4042 | params->rx_cq_moderation = | |
0088cbbc | 4043 | mlx5e_am_get_def_profile(cq_period_mode); |
457fcd8a | 4044 | |
6a9764ef | 4045 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER, |
0088cbbc TG |
4046 | params->rx_cq_moderation.cq_period_mode == |
4047 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE); | |
9908aa29 TT |
4048 | } |
4049 | ||
2b029556 SM |
4050 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout) |
4051 | { | |
4052 | int i; | |
4053 | ||
4054 | /* The supported periods are organized in ascending order */ | |
4055 | for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++) | |
4056 | if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) | |
4057 | break; | |
4058 | ||
4059 | return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); | |
4060 | } | |
4061 | ||
8f493ffd SM |
4062 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
4063 | struct mlx5e_params *params, | |
4064 | u16 max_channels) | |
f62b8bb8 | 4065 | { |
6a9764ef | 4066 | u8 cq_period_mode = 0; |
b797a684 SM |
4067 | u32 link_speed = 0; |
4068 | u32 pci_bw = 0; | |
2fc4bfb7 | 4069 | |
6a9764ef SM |
4070 | params->num_channels = max_channels; |
4071 | params->num_tc = 1; | |
2b029556 | 4072 | |
0f6e4cf6 EBE |
4073 | mlx5e_get_max_linkspeed(mdev, &link_speed); |
4074 | mlx5e_get_pci_bw(mdev, &pci_bw); | |
4075 | mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n", | |
4076 | link_speed, pci_bw); | |
4077 | ||
6a9764ef SM |
4078 | /* SQ */ |
4079 | params->log_sq_size = is_kdump_kernel() ? | |
b4e029da KH |
4080 | MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE : |
4081 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
461017cb | 4082 | |
b797a684 | 4083 | /* set CQE compression */ |
6a9764ef | 4084 | params->rx_cqe_compress_def = false; |
b797a684 | 4085 | if (MLX5_CAP_GEN(mdev, cqe_compression) && |
e53eef63 | 4086 | MLX5_CAP_GEN(mdev, vport_group_manager)) |
6a9764ef | 4087 | params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw); |
0f6e4cf6 | 4088 | |
6a9764ef SM |
4089 | MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def); |
4090 | ||
4091 | /* RQ */ | |
4092 | mlx5e_set_rq_params(mdev, params); | |
b797a684 | 4093 | |
6a9764ef | 4094 | /* HW LRO */ |
c139dbfd | 4095 | |
5426a0b2 | 4096 | /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */ |
6a9764ef | 4097 | if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) |
0f6e4cf6 | 4098 | params->lro_en = hw_lro_heuristic(link_speed, pci_bw); |
6a9764ef | 4099 | params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT); |
b0d4660b | 4100 | |
6a9764ef SM |
4101 | /* CQ moderation params */ |
4102 | cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? | |
4103 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : | |
4104 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
4105 | params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation); | |
4106 | mlx5e_set_rx_cq_mode_params(params, cq_period_mode); | |
0088cbbc | 4107 | mlx5e_set_tx_cq_mode_params(params, cq_period_mode); |
9908aa29 | 4108 | |
6a9764ef SM |
4109 | /* TX inline */ |
4110 | params->tx_max_inline = mlx5e_get_max_inline_cap(mdev); | |
fbcb127e | 4111 | params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev); |
a6f402e4 | 4112 | |
6a9764ef SM |
4113 | /* RSS */ |
4114 | params->rss_hfunc = ETH_RSS_HASH_XOR; | |
4115 | netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key)); | |
d4b6c488 | 4116 | mlx5e_build_default_indir_rqt(params->indirection_rqt, |
6a9764ef SM |
4117 | MLX5E_INDIR_RQT_SIZE, max_channels); |
4118 | } | |
f62b8bb8 | 4119 | |
6a9764ef SM |
4120 | static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev, |
4121 | struct net_device *netdev, | |
4122 | const struct mlx5e_profile *profile, | |
4123 | void *ppriv) | |
4124 | { | |
4125 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
57afead5 | 4126 | |
6a9764ef SM |
4127 | priv->mdev = mdev; |
4128 | priv->netdev = netdev; | |
4129 | priv->profile = profile; | |
4130 | priv->ppriv = ppriv; | |
79c48764 | 4131 | priv->msglevel = MLX5E_MSG_LEVEL; |
c139dbfd | 4132 | priv->hard_mtu = MLX5E_ETH_HARD_MTU; |
2d75b2bc | 4133 | |
6a9764ef | 4134 | mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev)); |
9908aa29 | 4135 | |
f62b8bb8 AV |
4136 | mutex_init(&priv->state_lock); |
4137 | ||
4138 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
4139 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3947ca18 | 4140 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); |
f62b8bb8 AV |
4141 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
4142 | } | |
4143 | ||
4144 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
4145 | { | |
4146 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4147 | ||
e1d7d349 | 4148 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
4149 | if (is_zero_ether_addr(netdev->dev_addr) && |
4150 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
4151 | eth_hw_addr_random(netdev); | |
4152 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
4153 | } | |
f62b8bb8 AV |
4154 | } |
4155 | ||
e80541ec | 4156 | #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH) |
cb67b832 HHZ |
4157 | static const struct switchdev_ops mlx5e_switchdev_ops = { |
4158 | .switchdev_port_attr_get = mlx5e_attr_get, | |
4159 | }; | |
e80541ec | 4160 | #endif |
cb67b832 | 4161 | |
6bfd390b | 4162 | static void mlx5e_build_nic_netdev(struct net_device *netdev) |
f62b8bb8 AV |
4163 | { |
4164 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
4165 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
4166 | bool fcs_supported; |
4167 | bool fcs_enabled; | |
f62b8bb8 AV |
4168 | |
4169 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
4170 | ||
e80541ec SM |
4171 | netdev->netdev_ops = &mlx5e_netdev_ops; |
4172 | ||
08fb1dac | 4173 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
e80541ec SM |
4174 | if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) |
4175 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
08fb1dac | 4176 | #endif |
66e49ded | 4177 | |
f62b8bb8 AV |
4178 | netdev->watchdog_timeo = 15 * HZ; |
4179 | ||
4180 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
4181 | ||
12be4b21 | 4182 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
4183 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
4184 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
4185 | netdev->vlan_features |= NETIF_F_GRO; | |
4186 | netdev->vlan_features |= NETIF_F_TSO; | |
4187 | netdev->vlan_features |= NETIF_F_TSO6; | |
4188 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
4189 | netdev->vlan_features |= NETIF_F_RXHASH; | |
4190 | ||
4191 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
4192 | netdev->vlan_features |= NETIF_F_LRO; | |
4193 | ||
4194 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 4195 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
4196 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
4197 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
4382c7b9 | 4198 | netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX; |
f62b8bb8 | 4199 | |
27299841 GP |
4200 | if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4201 | netdev->hw_features |= NETIF_F_GSO_PARTIAL; | |
b3f63c3d | 4202 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 4203 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
4204 | netdev->hw_enc_features |= NETIF_F_TSO; |
4205 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
27299841 GP |
4206 | netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL; |
4207 | } | |
4208 | ||
4209 | if (mlx5e_vxlan_allowed(mdev)) { | |
4210 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4211 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
4212 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL | | |
4213 | NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b49663c8 | 4214 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; |
b3f63c3d MF |
4215 | } |
4216 | ||
27299841 GP |
4217 | if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) { |
4218 | netdev->hw_features |= NETIF_F_GSO_GRE | | |
4219 | NETIF_F_GSO_GRE_CSUM; | |
4220 | netdev->hw_enc_features |= NETIF_F_GSO_GRE | | |
4221 | NETIF_F_GSO_GRE_CSUM; | |
4222 | netdev->gso_partial_features |= NETIF_F_GSO_GRE | | |
4223 | NETIF_F_GSO_GRE_CSUM; | |
4224 | } | |
4225 | ||
94cb1ebb EBE |
4226 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
4227 | ||
4228 | if (fcs_supported) | |
4229 | netdev->hw_features |= NETIF_F_RXALL; | |
4230 | ||
102722fc GE |
4231 | if (MLX5_CAP_ETH(mdev, scatter_fcs)) |
4232 | netdev->hw_features |= NETIF_F_RXFCS; | |
4233 | ||
f62b8bb8 | 4234 | netdev->features = netdev->hw_features; |
6a9764ef | 4235 | if (!priv->channels.params.lro_en) |
f62b8bb8 AV |
4236 | netdev->features &= ~NETIF_F_LRO; |
4237 | ||
94cb1ebb EBE |
4238 | if (fcs_enabled) |
4239 | netdev->features &= ~NETIF_F_RXALL; | |
4240 | ||
102722fc GE |
4241 | if (!priv->channels.params.scatter_fcs_en) |
4242 | netdev->features &= ~NETIF_F_RXFCS; | |
4243 | ||
e8f887ac AV |
4244 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
4245 | if (FT_CAP(flow_modify_en) && | |
4246 | FT_CAP(modify_root) && | |
4247 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
4248 | FT_CAP(flow_table_modify)) { |
4249 | netdev->hw_features |= NETIF_F_HW_TC; | |
4250 | #ifdef CONFIG_RFS_ACCEL | |
4251 | netdev->hw_features |= NETIF_F_NTUPLE; | |
4252 | #endif | |
4253 | } | |
e8f887ac | 4254 | |
f62b8bb8 | 4255 | netdev->features |= NETIF_F_HIGHDMA; |
7d92d580 | 4256 | netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER; |
f62b8bb8 AV |
4257 | |
4258 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
4259 | ||
4260 | mlx5e_set_netdev_dev_addr(netdev); | |
cb67b832 | 4261 | |
e80541ec | 4262 | #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH) |
a9f7705f | 4263 | if (MLX5_VPORT_MANAGER(mdev)) |
cb67b832 HHZ |
4264 | netdev->switchdev_ops = &mlx5e_switchdev_ops; |
4265 | #endif | |
547eede0 IT |
4266 | |
4267 | mlx5e_ipsec_build_netdev(priv); | |
f62b8bb8 AV |
4268 | } |
4269 | ||
593cf338 RS |
4270 | static void mlx5e_create_q_counter(struct mlx5e_priv *priv) |
4271 | { | |
4272 | struct mlx5_core_dev *mdev = priv->mdev; | |
4273 | int err; | |
4274 | ||
4275 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
4276 | if (err) { | |
4277 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
4278 | priv->q_counter = 0; | |
4279 | } | |
4280 | } | |
4281 | ||
4282 | static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv) | |
4283 | { | |
4284 | if (!priv->q_counter) | |
4285 | return; | |
4286 | ||
4287 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
4288 | } | |
4289 | ||
6bfd390b HHZ |
4290 | static void mlx5e_nic_init(struct mlx5_core_dev *mdev, |
4291 | struct net_device *netdev, | |
127ea380 HHZ |
4292 | const struct mlx5e_profile *profile, |
4293 | void *ppriv) | |
6bfd390b HHZ |
4294 | { |
4295 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
547eede0 | 4296 | int err; |
6bfd390b | 4297 | |
127ea380 | 4298 | mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv); |
547eede0 IT |
4299 | err = mlx5e_ipsec_init(priv); |
4300 | if (err) | |
4301 | mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err); | |
6bfd390b HHZ |
4302 | mlx5e_build_nic_netdev(netdev); |
4303 | mlx5e_vxlan_init(priv); | |
4304 | } | |
4305 | ||
4306 | static void mlx5e_nic_cleanup(struct mlx5e_priv *priv) | |
4307 | { | |
547eede0 | 4308 | mlx5e_ipsec_cleanup(priv); |
6bfd390b | 4309 | mlx5e_vxlan_cleanup(priv); |
127ea380 | 4310 | |
6a9764ef SM |
4311 | if (priv->channels.params.xdp_prog) |
4312 | bpf_prog_put(priv->channels.params.xdp_prog); | |
6bfd390b HHZ |
4313 | } |
4314 | ||
4315 | static int mlx5e_init_nic_rx(struct mlx5e_priv *priv) | |
4316 | { | |
4317 | struct mlx5_core_dev *mdev = priv->mdev; | |
4318 | int err; | |
6bfd390b | 4319 | |
8f493ffd SM |
4320 | err = mlx5e_create_indirect_rqt(priv); |
4321 | if (err) | |
6bfd390b | 4322 | return err; |
6bfd390b HHZ |
4323 | |
4324 | err = mlx5e_create_direct_rqts(priv); | |
8f493ffd | 4325 | if (err) |
6bfd390b | 4326 | goto err_destroy_indirect_rqts; |
6bfd390b HHZ |
4327 | |
4328 | err = mlx5e_create_indirect_tirs(priv); | |
8f493ffd | 4329 | if (err) |
6bfd390b | 4330 | goto err_destroy_direct_rqts; |
6bfd390b HHZ |
4331 | |
4332 | err = mlx5e_create_direct_tirs(priv); | |
8f493ffd | 4333 | if (err) |
6bfd390b | 4334 | goto err_destroy_indirect_tirs; |
6bfd390b HHZ |
4335 | |
4336 | err = mlx5e_create_flow_steering(priv); | |
4337 | if (err) { | |
4338 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); | |
4339 | goto err_destroy_direct_tirs; | |
4340 | } | |
4341 | ||
4342 | err = mlx5e_tc_init(priv); | |
4343 | if (err) | |
4344 | goto err_destroy_flow_steering; | |
4345 | ||
4346 | return 0; | |
4347 | ||
4348 | err_destroy_flow_steering: | |
4349 | mlx5e_destroy_flow_steering(priv); | |
4350 | err_destroy_direct_tirs: | |
4351 | mlx5e_destroy_direct_tirs(priv); | |
4352 | err_destroy_indirect_tirs: | |
4353 | mlx5e_destroy_indirect_tirs(priv); | |
4354 | err_destroy_direct_rqts: | |
8f493ffd | 4355 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4356 | err_destroy_indirect_rqts: |
4357 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); | |
4358 | return err; | |
4359 | } | |
4360 | ||
4361 | static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv) | |
4362 | { | |
6bfd390b HHZ |
4363 | mlx5e_tc_cleanup(priv); |
4364 | mlx5e_destroy_flow_steering(priv); | |
4365 | mlx5e_destroy_direct_tirs(priv); | |
4366 | mlx5e_destroy_indirect_tirs(priv); | |
8f493ffd | 4367 | mlx5e_destroy_direct_rqts(priv); |
6bfd390b HHZ |
4368 | mlx5e_destroy_rqt(priv, &priv->indir_rqt); |
4369 | } | |
4370 | ||
4371 | static int mlx5e_init_nic_tx(struct mlx5e_priv *priv) | |
4372 | { | |
4373 | int err; | |
4374 | ||
4375 | err = mlx5e_create_tises(priv); | |
4376 | if (err) { | |
4377 | mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err); | |
4378 | return err; | |
4379 | } | |
4380 | ||
4381 | #ifdef CONFIG_MLX5_CORE_EN_DCB | |
e207b7e9 | 4382 | mlx5e_dcbnl_initialize(priv); |
6bfd390b HHZ |
4383 | #endif |
4384 | return 0; | |
4385 | } | |
4386 | ||
4387 | static void mlx5e_nic_enable(struct mlx5e_priv *priv) | |
4388 | { | |
4389 | struct net_device *netdev = priv->netdev; | |
4390 | struct mlx5_core_dev *mdev = priv->mdev; | |
2c3b5bee SM |
4391 | u16 max_mtu; |
4392 | ||
4393 | mlx5e_init_l2_addr(priv); | |
4394 | ||
63bfd399 EBE |
4395 | /* Marking the link as currently not needed by the Driver */ |
4396 | if (!netif_running(netdev)) | |
4397 | mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN); | |
4398 | ||
2c3b5bee SM |
4399 | /* MTU range: 68 - hw-specific max */ |
4400 | netdev->min_mtu = ETH_MIN_MTU; | |
4401 | mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1); | |
c139dbfd | 4402 | netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu); |
2c3b5bee | 4403 | mlx5e_set_dev_port_mtu(priv); |
6bfd390b | 4404 | |
7907f23a AH |
4405 | mlx5_lag_add(mdev, netdev); |
4406 | ||
6bfd390b | 4407 | mlx5e_enable_async_events(priv); |
127ea380 | 4408 | |
a9f7705f | 4409 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 | 4410 | mlx5e_register_vport_reps(priv); |
2c3b5bee | 4411 | |
610e89e0 SM |
4412 | if (netdev->reg_state != NETREG_REGISTERED) |
4413 | return; | |
2a5e7a13 HN |
4414 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4415 | mlx5e_dcbnl_init_app(priv); | |
4416 | #endif | |
610e89e0 SM |
4417 | /* Device already registered: sync netdev system state */ |
4418 | if (mlx5e_vxlan_allowed(mdev)) { | |
4419 | rtnl_lock(); | |
4420 | udp_tunnel_get_rx_info(netdev); | |
4421 | rtnl_unlock(); | |
4422 | } | |
4423 | ||
4424 | queue_work(priv->wq, &priv->set_rx_mode_work); | |
2c3b5bee SM |
4425 | |
4426 | rtnl_lock(); | |
4427 | if (netif_running(netdev)) | |
4428 | mlx5e_open(netdev); | |
4429 | netif_device_attach(netdev); | |
4430 | rtnl_unlock(); | |
6bfd390b HHZ |
4431 | } |
4432 | ||
4433 | static void mlx5e_nic_disable(struct mlx5e_priv *priv) | |
4434 | { | |
3deef8ce | 4435 | struct mlx5_core_dev *mdev = priv->mdev; |
3deef8ce | 4436 | |
2a5e7a13 HN |
4437 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4438 | if (priv->netdev->reg_state == NETREG_REGISTERED) | |
4439 | mlx5e_dcbnl_delete_app(priv); | |
4440 | #endif | |
4441 | ||
2c3b5bee SM |
4442 | rtnl_lock(); |
4443 | if (netif_running(priv->netdev)) | |
4444 | mlx5e_close(priv->netdev); | |
4445 | netif_device_detach(priv->netdev); | |
4446 | rtnl_unlock(); | |
4447 | ||
6bfd390b | 4448 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1d447a39 | 4449 | |
a9f7705f | 4450 | if (MLX5_VPORT_MANAGER(priv->mdev)) |
1d447a39 SM |
4451 | mlx5e_unregister_vport_reps(priv); |
4452 | ||
6bfd390b | 4453 | mlx5e_disable_async_events(priv); |
3deef8ce | 4454 | mlx5_lag_remove(mdev); |
6bfd390b HHZ |
4455 | } |
4456 | ||
4457 | static const struct mlx5e_profile mlx5e_nic_profile = { | |
4458 | .init = mlx5e_nic_init, | |
4459 | .cleanup = mlx5e_nic_cleanup, | |
4460 | .init_rx = mlx5e_init_nic_rx, | |
4461 | .cleanup_rx = mlx5e_cleanup_nic_rx, | |
4462 | .init_tx = mlx5e_init_nic_tx, | |
4463 | .cleanup_tx = mlx5e_cleanup_nic_tx, | |
4464 | .enable = mlx5e_nic_enable, | |
4465 | .disable = mlx5e_nic_disable, | |
3834a5e6 | 4466 | .update_stats = mlx5e_update_ndo_stats, |
6bfd390b | 4467 | .max_nch = mlx5e_get_max_num_channels, |
7ca42c80 | 4468 | .update_carrier = mlx5e_update_carrier, |
20fd0c19 SM |
4469 | .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe, |
4470 | .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq, | |
6bfd390b HHZ |
4471 | .max_tc = MLX5E_MAX_NUM_TC, |
4472 | }; | |
4473 | ||
2c3b5bee SM |
4474 | /* mlx5e generic netdev management API (move to en_common.c) */ |
4475 | ||
26e59d80 MHY |
4476 | struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev, |
4477 | const struct mlx5e_profile *profile, | |
4478 | void *ppriv) | |
f62b8bb8 | 4479 | { |
26e59d80 | 4480 | int nch = profile->max_nch(mdev); |
f62b8bb8 AV |
4481 | struct net_device *netdev; |
4482 | struct mlx5e_priv *priv; | |
f62b8bb8 | 4483 | |
08fb1dac | 4484 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
6bfd390b | 4485 | nch * profile->max_tc, |
08fb1dac | 4486 | nch); |
f62b8bb8 AV |
4487 | if (!netdev) { |
4488 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
4489 | return NULL; | |
4490 | } | |
4491 | ||
be4891af SM |
4492 | #ifdef CONFIG_RFS_ACCEL |
4493 | netdev->rx_cpu_rmap = mdev->rmap; | |
4494 | #endif | |
4495 | ||
127ea380 | 4496 | profile->init(mdev, netdev, profile, ppriv); |
f62b8bb8 AV |
4497 | |
4498 | netif_carrier_off(netdev); | |
4499 | ||
4500 | priv = netdev_priv(netdev); | |
4501 | ||
7bb29755 MF |
4502 | priv->wq = create_singlethread_workqueue("mlx5e"); |
4503 | if (!priv->wq) | |
26e59d80 MHY |
4504 | goto err_cleanup_nic; |
4505 | ||
4506 | return netdev; | |
4507 | ||
4508 | err_cleanup_nic: | |
31ac9338 OG |
4509 | if (profile->cleanup) |
4510 | profile->cleanup(priv); | |
26e59d80 MHY |
4511 | free_netdev(netdev); |
4512 | ||
4513 | return NULL; | |
4514 | } | |
4515 | ||
2c3b5bee | 4516 | int mlx5e_attach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4517 | { |
2c3b5bee | 4518 | struct mlx5_core_dev *mdev = priv->mdev; |
26e59d80 | 4519 | const struct mlx5e_profile *profile; |
26e59d80 MHY |
4520 | int err; |
4521 | ||
26e59d80 MHY |
4522 | profile = priv->profile; |
4523 | clear_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
7bb29755 | 4524 | |
6bfd390b HHZ |
4525 | err = profile->init_tx(priv); |
4526 | if (err) | |
ec8b9981 | 4527 | goto out; |
5c50368f | 4528 | |
a43b25da | 4529 | err = mlx5e_open_drop_rq(mdev, &priv->drop_rq); |
5c50368f AS |
4530 | if (err) { |
4531 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
6bfd390b | 4532 | goto err_cleanup_tx; |
5c50368f AS |
4533 | } |
4534 | ||
6bfd390b HHZ |
4535 | err = profile->init_rx(priv); |
4536 | if (err) | |
5c50368f | 4537 | goto err_close_drop_rq; |
5c50368f | 4538 | |
593cf338 RS |
4539 | mlx5e_create_q_counter(priv); |
4540 | ||
6bfd390b HHZ |
4541 | if (profile->enable) |
4542 | profile->enable(priv); | |
f62b8bb8 | 4543 | |
26e59d80 | 4544 | return 0; |
5c50368f AS |
4545 | |
4546 | err_close_drop_rq: | |
a43b25da | 4547 | mlx5e_close_drop_rq(&priv->drop_rq); |
5c50368f | 4548 | |
6bfd390b HHZ |
4549 | err_cleanup_tx: |
4550 | profile->cleanup_tx(priv); | |
5c50368f | 4551 | |
26e59d80 MHY |
4552 | out: |
4553 | return err; | |
f62b8bb8 AV |
4554 | } |
4555 | ||
2c3b5bee | 4556 | void mlx5e_detach_netdev(struct mlx5e_priv *priv) |
26e59d80 | 4557 | { |
26e59d80 MHY |
4558 | const struct mlx5e_profile *profile = priv->profile; |
4559 | ||
4560 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); | |
26e59d80 | 4561 | |
37f304d1 SM |
4562 | if (profile->disable) |
4563 | profile->disable(priv); | |
4564 | flush_workqueue(priv->wq); | |
4565 | ||
26e59d80 MHY |
4566 | mlx5e_destroy_q_counter(priv); |
4567 | profile->cleanup_rx(priv); | |
a43b25da | 4568 | mlx5e_close_drop_rq(&priv->drop_rq); |
26e59d80 | 4569 | profile->cleanup_tx(priv); |
26e59d80 MHY |
4570 | cancel_delayed_work_sync(&priv->update_stats_work); |
4571 | } | |
4572 | ||
2c3b5bee SM |
4573 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv) |
4574 | { | |
4575 | const struct mlx5e_profile *profile = priv->profile; | |
4576 | struct net_device *netdev = priv->netdev; | |
4577 | ||
4578 | destroy_workqueue(priv->wq); | |
4579 | if (profile->cleanup) | |
4580 | profile->cleanup(priv); | |
4581 | free_netdev(netdev); | |
4582 | } | |
4583 | ||
26e59d80 MHY |
4584 | /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying |
4585 | * hardware contexts and to connect it to the current netdev. | |
4586 | */ | |
4587 | static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv) | |
4588 | { | |
4589 | struct mlx5e_priv *priv = vpriv; | |
4590 | struct net_device *netdev = priv->netdev; | |
4591 | int err; | |
4592 | ||
4593 | if (netif_device_present(netdev)) | |
4594 | return 0; | |
4595 | ||
4596 | err = mlx5e_create_mdev_resources(mdev); | |
4597 | if (err) | |
4598 | return err; | |
4599 | ||
2c3b5bee | 4600 | err = mlx5e_attach_netdev(priv); |
26e59d80 MHY |
4601 | if (err) { |
4602 | mlx5e_destroy_mdev_resources(mdev); | |
4603 | return err; | |
4604 | } | |
4605 | ||
4606 | return 0; | |
4607 | } | |
4608 | ||
4609 | static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv) | |
4610 | { | |
4611 | struct mlx5e_priv *priv = vpriv; | |
4612 | struct net_device *netdev = priv->netdev; | |
4613 | ||
4614 | if (!netif_device_present(netdev)) | |
4615 | return; | |
4616 | ||
2c3b5bee | 4617 | mlx5e_detach_netdev(priv); |
26e59d80 MHY |
4618 | mlx5e_destroy_mdev_resources(mdev); |
4619 | } | |
4620 | ||
b50d292b HHZ |
4621 | static void *mlx5e_add(struct mlx5_core_dev *mdev) |
4622 | { | |
07c9f1e5 SM |
4623 | struct net_device *netdev; |
4624 | void *rpriv = NULL; | |
26e59d80 | 4625 | void *priv; |
26e59d80 | 4626 | int err; |
b50d292b | 4627 | |
26e59d80 MHY |
4628 | err = mlx5e_check_required_hca_cap(mdev); |
4629 | if (err) | |
b50d292b HHZ |
4630 | return NULL; |
4631 | ||
e80541ec | 4632 | #ifdef CONFIG_MLX5_ESWITCH |
a9f7705f | 4633 | if (MLX5_VPORT_MANAGER(mdev)) { |
07c9f1e5 | 4634 | rpriv = mlx5e_alloc_nic_rep_priv(mdev); |
1d447a39 | 4635 | if (!rpriv) { |
07c9f1e5 | 4636 | mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n"); |
1d447a39 SM |
4637 | return NULL; |
4638 | } | |
1d447a39 | 4639 | } |
e80541ec | 4640 | #endif |
127ea380 | 4641 | |
1d447a39 | 4642 | netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv); |
26e59d80 MHY |
4643 | if (!netdev) { |
4644 | mlx5_core_err(mdev, "mlx5e_create_netdev failed\n"); | |
07c9f1e5 | 4645 | goto err_free_rpriv; |
26e59d80 MHY |
4646 | } |
4647 | ||
4648 | priv = netdev_priv(netdev); | |
4649 | ||
4650 | err = mlx5e_attach(mdev, priv); | |
4651 | if (err) { | |
4652 | mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err); | |
4653 | goto err_destroy_netdev; | |
4654 | } | |
4655 | ||
4656 | err = register_netdev(netdev); | |
4657 | if (err) { | |
4658 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); | |
4659 | goto err_detach; | |
b50d292b | 4660 | } |
26e59d80 | 4661 | |
2a5e7a13 HN |
4662 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4663 | mlx5e_dcbnl_init_app(priv); | |
4664 | #endif | |
26e59d80 MHY |
4665 | return priv; |
4666 | ||
4667 | err_detach: | |
4668 | mlx5e_detach(mdev, priv); | |
26e59d80 | 4669 | err_destroy_netdev: |
2c3b5bee | 4670 | mlx5e_destroy_netdev(priv); |
07c9f1e5 | 4671 | err_free_rpriv: |
1d447a39 | 4672 | kfree(rpriv); |
26e59d80 | 4673 | return NULL; |
b50d292b HHZ |
4674 | } |
4675 | ||
b50d292b HHZ |
4676 | static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv) |
4677 | { | |
4678 | struct mlx5e_priv *priv = vpriv; | |
1d447a39 | 4679 | void *ppriv = priv->ppriv; |
127ea380 | 4680 | |
2a5e7a13 HN |
4681 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
4682 | mlx5e_dcbnl_delete_app(priv); | |
4683 | #endif | |
5e1e93c7 | 4684 | unregister_netdev(priv->netdev); |
26e59d80 | 4685 | mlx5e_detach(mdev, vpriv); |
2c3b5bee | 4686 | mlx5e_destroy_netdev(priv); |
1d447a39 | 4687 | kfree(ppriv); |
b50d292b HHZ |
4688 | } |
4689 | ||
f62b8bb8 AV |
4690 | static void *mlx5e_get_netdev(void *vpriv) |
4691 | { | |
4692 | struct mlx5e_priv *priv = vpriv; | |
4693 | ||
4694 | return priv->netdev; | |
4695 | } | |
4696 | ||
4697 | static struct mlx5_interface mlx5e_interface = { | |
b50d292b HHZ |
4698 | .add = mlx5e_add, |
4699 | .remove = mlx5e_remove, | |
26e59d80 MHY |
4700 | .attach = mlx5e_attach, |
4701 | .detach = mlx5e_detach, | |
f62b8bb8 AV |
4702 | .event = mlx5e_async_event, |
4703 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
4704 | .get_dev = mlx5e_get_netdev, | |
4705 | }; | |
4706 | ||
4707 | void mlx5e_init(void) | |
4708 | { | |
2ac9cfe7 | 4709 | mlx5e_ipsec_build_inverse_table(); |
665bc539 | 4710 | mlx5e_build_ptys2ethtool_map(); |
f62b8bb8 AV |
4711 | mlx5_register_interface(&mlx5e_interface); |
4712 | } | |
4713 | ||
4714 | void mlx5e_cleanup(void) | |
4715 | { | |
4716 | mlx5_unregister_interface(&mlx5e_interface); | |
4717 | } |