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Revert "mlx5: move affinity hints assignments to generic code"
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
1d447a39 38#include "eswitch.h"
f62b8bb8 39#include "en.h"
e8f887ac 40#include "en_tc.h"
1d447a39 41#include "en_rep.h"
547eede0 42#include "en_accel/ipsec.h"
899a59d3
IT		 43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
b3f63c3d 45#include "vxlan.h"
f62b8bb8
AV		 46
47struct mlx5e_rq_param {
cb3c7fd4
GR		 48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
f62b8bb8
AV		 50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
6a9764ef
SM		 81void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev,
82 struct mlx5e_params *params, u8 rq_type)
2fc4bfb7 83{
6a9764ef
SM		 84 params->rq_wq_type = rq_type;
85 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
86 switch (params->rq_wq_type) {
2fc4bfb7 87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 88 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW :
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
6a9764ef
SM		 91 params->mpwqe_log_stride_sz =
92 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
93 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) :
94 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev);
95 params->mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
96 params->mpwqe_log_stride_sz;
2fc4bfb7
SM		 97 break;
98 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 99 params->log_rq_size = is_kdump_kernel() ?
b4e029da
KH		 100 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
101 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
bce2b2bf
TT		 102 params->rq_headroom = params->xdp_prog ?
103 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
104 params->rq_headroom += NET_IP_ALIGN;
4078e637
TT		 105
106 /* Extra room needed for build_skb */
bce2b2bf 107 params->lro_wqe_sz -= params->rq_headroom +
4078e637 108 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2fc4bfb7 109 }
2fc4bfb7 110
6a9764ef
SM		 111 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
112 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
113 BIT(params->log_rq_size),
114 BIT(params->mpwqe_log_stride_sz),
115 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 116}
117
6a9764ef 118static void mlx5e_set_rq_params(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
2fc4bfb7 119{
6a9764ef 120 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) &&
899a59d3 121 !params->xdp_prog && !MLX5_IPSEC_DEV(mdev) ?
2fc4bfb7
SM		 122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
123 MLX5_WQ_TYPE_LINKED_LIST;
6a9764ef 124 mlx5e_set_rq_type_params(mdev, params, rq_type);
2fc4bfb7
SM		 125}
126
f62b8bb8
AV		 127static void mlx5e_update_carrier(struct mlx5e_priv *priv)
128{
129 struct mlx5_core_dev *mdev = priv->mdev;
130 u8 port_state;
131
132 port_state = mlx5_query_vport_state(mdev,
e53eef63
OG		 133 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
134 0);
f62b8bb8 135
87424ad5
SD		 136 if (port_state == VPORT_STATE_UP) {
137 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 138 netif_carrier_on(priv->netdev);
87424ad5
SD		 139 } else {
140 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 141 netif_carrier_off(priv->netdev);
87424ad5 142 }
f62b8bb8
AV		 143}
144
145static void mlx5e_update_carrier_work(struct work_struct *work)
146{
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 update_carrier_work);
149
150 mutex_lock(&priv->state_lock);
151 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
7ca42c80
ES		 152 if (priv->profile->update_carrier)
153 priv->profile->update_carrier(priv);
f62b8bb8
AV		 154 mutex_unlock(&priv->state_lock);
155}
156
3947ca18
DJ		 157static void mlx5e_tx_timeout_work(struct work_struct *work)
158{
159 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
160 tx_timeout_work);
161 int err;
162
163 rtnl_lock();
164 mutex_lock(&priv->state_lock);
165 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
166 goto unlock;
167 mlx5e_close_locked(priv->netdev);
168 err = mlx5e_open_locked(priv->netdev);
169 if (err)
170 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
171 err);
172unlock:
173 mutex_unlock(&priv->state_lock);
174 rtnl_unlock();
175}
176
9218b44d 177static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 178{
1510d728 179 struct mlx5e_sw_stats temp, *s = &temp;
f62b8bb8
AV		 180 struct mlx5e_rq_stats *rq_stats;
181 struct mlx5e_sq_stats *sq_stats;
f62b8bb8
AV		 182 int i, j;
183
9218b44d 184 memset(s, 0, sizeof(*s));
ff9c852f
SM		 185 for (i = 0; i < priv->channels.num; i++) {
186 struct mlx5e_channel *c = priv->channels.c[i];
187
188 rq_stats = &c->rq.stats;
f62b8bb8 189
faf4478b
GP		 190 s->rx_packets += rq_stats->packets;
191 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 192 s->rx_lro_packets += rq_stats->lro_packets;
193 s->rx_lro_bytes += rq_stats->lro_bytes;
f24686e8 194 s->rx_removed_vlan_packets += rq_stats->removed_vlan_packets;
f62b8bb8 195 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1 196 s->rx_csum_complete += rq_stats->csum_complete;
603e1f5b 197 s->rx_csum_unnecessary += rq_stats->csum_unnecessary;
bfe6d8d1 198 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 199 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 200 s->rx_xdp_tx += rq_stats->xdp_tx;
201 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 202 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 203 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 204 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 205 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
206 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
accd5883 207 s->rx_page_reuse += rq_stats->page_reuse;
4415a031
TT		 208 s->rx_cache_reuse += rq_stats->cache_reuse;
209 s->rx_cache_full += rq_stats->cache_full;
210 s->rx_cache_empty += rq_stats->cache_empty;
211 s->rx_cache_busy += rq_stats->cache_busy;
70871f1e 212 s->rx_cache_waive += rq_stats->cache_waive;
f62b8bb8 213
6a9764ef 214 for (j = 0; j < priv->channels.params.num_tc; j++) {
ff9c852f 215 sq_stats = &c->sq[j].stats;
f62b8bb8 216
faf4478b
GP		 217 s->tx_packets += sq_stats->packets;
218 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 219 s->tx_tso_packets += sq_stats->tso_packets;
220 s->tx_tso_bytes += sq_stats->tso_bytes;
221 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
222 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f24686e8 223 s->tx_added_vlan_packets += sq_stats->added_vlan_packets;
f62b8bb8
AV		 224 s->tx_queue_stopped += sq_stats->stopped;
225 s->tx_queue_wake += sq_stats->wake;
226 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 227 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1 228 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
603e1f5b
GP		 229 s->tx_csum_none += sq_stats->csum_none;
230 s->tx_csum_partial += sq_stats->csum_partial;
f62b8bb8
AV		 231 }
232 }
233
bfe6d8d1 234 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 235 priv->stats.pport.phy_counters,
236 counter_set.phys_layer_cntrs.link_down_events);
1510d728 237 memcpy(&priv->stats.sw, s, sizeof(*s));
9218b44d
GP		 238}
239
240static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
241{
242 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
243 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 244 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 245 struct mlx5_core_dev *mdev = priv->mdev;
246
f62b8bb8
AV		 247 MLX5_SET(query_vport_counter_in, in, opcode,
248 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
249 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
250 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
251
9218b44d
GP		 252 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
253}
254
3834a5e6 255static void mlx5e_update_pport_counters(struct mlx5e_priv *priv, bool full)
9218b44d
GP		 256{
257 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
258 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 259 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
9218b44d 260 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 261 int prio;
9218b44d 262 void *out;
f62b8bb8 263
9218b44d 264 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 265
9218b44d
GP		 266 out = pstats->IEEE_802_3_counters;
267 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
268 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 269
3834a5e6
GP		 270 if (!full)
271 return;
272
9218b44d
GP		 273 out = pstats->RFC_2863_counters;
274 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
275 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
276
277 out = pstats->RFC_2819_counters;
278 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
279 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 280
121fcdc8
GP		 281 out = pstats->phy_counters;
282 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
283 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
284
5db0a4f6
GP		 285 if (MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group)) {
286 out = pstats->phy_statistical_counters;
287 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
288 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
289 }
290
068aef33
GP		 291 if (MLX5_CAP_PCAM_FEATURE(mdev, rx_buffer_fullness_counters)) {
292 out = pstats->eth_ext_counters;
293 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
5db0a4f6
GP		 294 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
295 }
296
cf678570
GP		 297 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
298 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
299 out = pstats->per_prio_counters[prio];
300 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
301 mlx5_core_access_reg(mdev, in, sz, out, sz,
302 MLX5_REG_PPCNT, 0, 0);
303 }
9218b44d
GP		 304}
305
306static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
307{
308 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
432609a4
GP		 309 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)];
310 int err;
9218b44d
GP		 311
312 if (!priv->q_counter)
313 return;
314
432609a4
GP		 315 err = mlx5_core_query_q_counter(priv->mdev, priv->q_counter, 0, out, sizeof(out));
316 if (err)
317 return;
318
319 qcnt->rx_out_of_buffer = MLX5_GET(query_q_counter_out, out, out_of_buffer);
9218b44d
GP		 320}
321
0f7f3481
GP		 322static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
323{
324 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
325 struct mlx5_core_dev *mdev = priv->mdev;
0883b4f4 326 u32 in[MLX5_ST_SZ_DW(mpcnt_reg)] = {0};
0f7f3481
GP		 327 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
328 void *out;
0f7f3481
GP		 329
330 if (!MLX5_CAP_MCAM_FEATURE(mdev, pcie_performance_group))
331 return;
332
0f7f3481
GP		 333 out = pcie_stats->pcie_perf_counters;
334 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
335 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
0f7f3481
GP		 336}
337
3834a5e6 338void mlx5e_update_stats(struct mlx5e_priv *priv, bool full)
9218b44d 339{
164f16f7 340 if (full) {
3834a5e6 341 mlx5e_update_pcie_counters(priv);
164f16f7
IT		 342 mlx5e_ipsec_update_stats(priv);
343 }
3834a5e6 344 mlx5e_update_pport_counters(priv, full);
3dd69e3d
SM		 345 mlx5e_update_vport_counters(priv);
346 mlx5e_update_q_counter(priv);
121fcdc8 347 mlx5e_update_sw_counters(priv);
f62b8bb8
AV		 348}
349
3834a5e6
GP		 350static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
351{
352 mlx5e_update_stats(priv, false);
353}
354
cb67b832 355void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 356{
357 struct delayed_work *dwork = to_delayed_work(work);
358 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
359 update_stats_work);
360 mutex_lock(&priv->state_lock);
361 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 362 priv->profile->update_stats(priv);
7bb29755
MF		 363 queue_delayed_work(priv->wq, dwork,
364 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 365 }
366 mutex_unlock(&priv->state_lock);
367}
368
daa21560
TT		 369static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
370 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 371{
daa21560
TT		 372 struct mlx5e_priv *priv = vpriv;
373
e0f46eb9 374 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 375 return;
376
f62b8bb8
AV		 377 switch (event) {
378 case MLX5_DEV_EVENT_PORT_UP:
379 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 380 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8 381 break;
f62b8bb8
AV		 382 default:
383 break;
384 }
385}
386
f62b8bb8
AV		 387static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
388{
e0f46eb9 389 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 390}
391
392static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
393{
e0f46eb9 394 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
78249c42 395 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 396}
397
7e426671
TT		 398static inline int mlx5e_get_wqe_mtt_sz(void)
399{
400 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
401 * To avoid copying garbage after the mtt array, we allocate
402 * a little more.
403 */
404 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
405 MLX5_UMR_MTT_ALIGNMENT);
406}
407
31391048
SM		 408static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
409 struct mlx5e_icosq *sq,
410 struct mlx5e_umr_wqe *wqe,
411 u16 ix)
7e426671
TT		 412{
413 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
414 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
415 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 416 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 417 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
418 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
419
420 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
421 ds_cnt);
422 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
423 cseg->imm = rq->mkey_be;
424
425 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
31616255 426 ucseg->xlt_octowords =
7e426671
TT		 427 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
428 ucseg->bsf_octowords =
429 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
430 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
431
432 dseg->lkey = sq->mkey_be;
433 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
434}
435
436static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
437 struct mlx5e_channel *c)
438{
439 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
440 int mtt_sz = mlx5e_get_wqe_mtt_sz();
441 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
442 int i;
443
21c59685 444 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
231243c8 445 GFP_KERNEL, cpu_to_node(c->cpu));
21c59685 446 if (!rq->mpwqe.info)
7e426671
TT		 447 goto err_out;
448
449 /* We allocate more than mtt_sz as we will align the pointer */
231243c8
SM		 450 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
451 cpu_to_node(c->cpu));
21c59685 452 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 453 goto err_free_wqe_info;
454
455 for (i = 0; i < wq_sz; i++) {
21c59685 456 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 457
21c59685 458 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 459 MLX5_UMR_ALIGN);
460 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
461 PCI_DMA_TODEVICE);
462 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
463 goto err_unmap_mtts;
464
465 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
466 }
467
468 return 0;
469
470err_unmap_mtts:
471 while (--i >= 0) {
21c59685 472 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 473
474 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
475 PCI_DMA_TODEVICE);
476 }
21c59685 477 kfree(rq->mpwqe.mtt_no_align);
7e426671 478err_free_wqe_info:
21c59685 479 kfree(rq->mpwqe.info);
7e426671
TT		 480
481err_out:
482 return -ENOMEM;
483}
484
485static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
486{
487 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
488 int mtt_sz = mlx5e_get_wqe_mtt_sz();
489 int i;
490
491 for (i = 0; i < wq_sz; i++) {
21c59685 492 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 493
494 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
495 PCI_DMA_TODEVICE);
496 }
21c59685
SM		 497 kfree(rq->mpwqe.mtt_no_align);
498 kfree(rq->mpwqe.info);
7e426671
TT		 499}
500
a43b25da 501static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
ec8b9981
TT		 502 u64 npages, u8 page_shift,
503 struct mlx5_core_mkey *umr_mkey)
3608ae77 504{
3608ae77
TT		 505 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
506 void *mkc;
507 u32 *in;
508 int err;
509
ec8b9981
TT		 510 if (!MLX5E_VALID_NUM_MTTS(npages))
511 return -EINVAL;
512
1b9a07ee 513 in = kvzalloc(inlen, GFP_KERNEL);
3608ae77
TT		 514 if (!in)
515 return -ENOMEM;
516
517 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
518
3608ae77
TT		 519 MLX5_SET(mkc, mkc, free, 1);
520 MLX5_SET(mkc, mkc, umr_en, 1);
521 MLX5_SET(mkc, mkc, lw, 1);
522 MLX5_SET(mkc, mkc, lr, 1);
523 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
524
525 MLX5_SET(mkc, mkc, qpn, 0xffffff);
526 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
ec8b9981 527 MLX5_SET64(mkc, mkc, len, npages << page_shift);
3608ae77
TT		 528 MLX5_SET(mkc, mkc, translations_octword_size,
529 MLX5_MTT_OCTW(npages));
ec8b9981 530 MLX5_SET(mkc, mkc, log_page_size, page_shift);
3608ae77 531
ec8b9981 532 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
3608ae77
TT		 533
534 kvfree(in);
535 return err;
536}
537
a43b25da 538static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
ec8b9981 539{
6a9764ef 540 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
ec8b9981 541
a43b25da 542 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
ec8b9981
TT		 543}
544
3b77235b 545static int mlx5e_alloc_rq(struct mlx5e_channel *c,
6a9764ef
SM		 546 struct mlx5e_params *params,
547 struct mlx5e_rq_param *rqp,
3b77235b 548 struct mlx5e_rq *rq)
f62b8bb8 549{
a43b25da 550 struct mlx5_core_dev *mdev = c->mdev;
6a9764ef 551 void *rqc = rqp->rqc;
f62b8bb8 552 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 553 u32 byte_count;
1bfecfca 554 int npages;
f62b8bb8
AV		 555 int wq_sz;
556 int err;
557 int i;
558
231243c8 559 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
311c7c71 560
6a9764ef 561 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
f62b8bb8
AV		 562 &rq->wq_ctrl);
563 if (err)
564 return err;
565
566 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
567
568 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 569
6a9764ef 570 rq->wq_type = params->rq_wq_type;
7e426671
TT		 571 rq->pdev = c->pdev;
572 rq->netdev = c->netdev;
a43b25da 573 rq->tstamp = c->tstamp;
7c39afb3 574 rq->clock = &mdev->clock;
7e426671
TT		 575 rq->channel = c;
576 rq->ix = c->ix;
a43b25da 577 rq->mdev = mdev;
97bc402d 578
6a9764ef 579 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
97bc402d
DB		 580 if (IS_ERR(rq->xdp_prog)) {
581 err = PTR_ERR(rq->xdp_prog);
582 rq->xdp_prog = NULL;
583 goto err_rq_wq_destroy;
584 }
7e426671 585
bce2b2bf 586 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
b45d8b50 587 rq->buff.headroom = params->rq_headroom;
b5503b99 588
6a9764ef 589 switch (rq->wq_type) {
461017cb 590 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476 591
7cc6d77b 592 rq->post_wqes = mlx5e_post_rx_mpwqes;
6cd392a0 593 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 594
20fd0c19 595 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
899a59d3
IT		 596#ifdef CONFIG_MLX5_EN_IPSEC
597 if (MLX5_IPSEC_DEV(mdev)) {
598 err = -EINVAL;
599 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
600 goto err_rq_wq_destroy;
601 }
602#endif
20fd0c19
SM		 603 if (!rq->handle_rx_cqe) {
604 err = -EINVAL;
605 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
606 goto err_rq_wq_destroy;
607 }
608
89e89f7a 609 rq->mpwqe.log_stride_sz = params->mpwqe_log_stride_sz;
b45d8b50 610 rq->mpwqe.num_strides = BIT(params->mpwqe_log_num_strides);
1bfecfca 611
b681c481 612 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
ec8b9981 613
a43b25da 614 err = mlx5e_create_rq_umr_mkey(mdev, rq);
7e426671
TT		 615 if (err)
616 goto err_rq_wq_destroy;
ec8b9981
TT		 617 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
618
619 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
620 if (err)
621 goto err_destroy_umr_mkey;
461017cb
TT		 622 break;
623 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883
TT		 624 rq->wqe.frag_info =
625 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
231243c8 626 GFP_KERNEL, cpu_to_node(c->cpu));
accd5883 627 if (!rq->wqe.frag_info) {
461017cb
TT		 628 err = -ENOMEM;
629 goto err_rq_wq_destroy;
630 }
7cc6d77b 631 rq->post_wqes = mlx5e_post_rx_wqes;
6cd392a0 632 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 633
899a59d3
IT		 634#ifdef CONFIG_MLX5_EN_IPSEC
635 if (c->priv->ipsec)
636 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
637 else
638#endif
639 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
20fd0c19 640 if (!rq->handle_rx_cqe) {
accd5883 641 kfree(rq->wqe.frag_info);
20fd0c19
SM		 642 err = -EINVAL;
643 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
644 goto err_rq_wq_destroy;
645 }
646
b681c481 647 byte_count = params->lro_en ?
6a9764ef 648 params->lro_wqe_sz :
c139dbfd 649 MLX5E_SW2HW_MTU(c->priv, c->netdev->mtu);
899a59d3
IT		 650#ifdef CONFIG_MLX5_EN_IPSEC
651 if (MLX5_IPSEC_DEV(mdev))
b681c481 652 byte_count += MLX5E_METADATA_ETHER_LEN;
899a59d3 653#endif
accd5883 654 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
1bfecfca
SM		 655
656 /* calc the required page order */
b45d8b50 657 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
accd5883 658 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
1bfecfca
SM		 659 rq->buff.page_order = order_base_2(npages);
660
461017cb 661 byte_count |= MLX5_HW_START_PADDING;
7e426671 662 rq->mkey_be = c->mkey_be;
461017cb 663 }
f62b8bb8
AV		 664
665 for (i = 0; i < wq_sz; i++) {
666 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
667
4c2af5cc
TT		 668 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
669 u64 dma_offset = (u64)mlx5e_get_wqe_mtt_offset(rq, i) << PAGE_SHIFT;
670
671 wqe->data.addr = cpu_to_be64(dma_offset);
672 }
673
461017cb 674 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 675 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 676 }
677
cb3c7fd4 678 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
0088cbbc 679 rq->am.mode = params->rx_cq_moderation.cq_period_mode;
4415a031
TT		 680 rq->page_cache.head = 0;
681 rq->page_cache.tail = 0;
682
f62b8bb8
AV		 683 return 0;
684
ec8b9981
TT		 685err_destroy_umr_mkey:
686 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
687
f62b8bb8 688err_rq_wq_destroy:
97bc402d
DB		 689 if (rq->xdp_prog)
690 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 691 mlx5_wq_destroy(&rq->wq_ctrl);
692
693 return err;
694}
695
3b77235b 696static void mlx5e_free_rq(struct mlx5e_rq *rq)
f62b8bb8 697{
4415a031
TT		 698 int i;
699
86994156
RS		 700 if (rq->xdp_prog)
701 bpf_prog_put(rq->xdp_prog);
702
461017cb
TT		 703 switch (rq->wq_type) {
704 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 705 mlx5e_rq_free_mpwqe_info(rq);
a43b25da 706 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
461017cb
TT		 707 break;
708 default: /* MLX5_WQ_TYPE_LINKED_LIST */
accd5883 709 kfree(rq->wqe.frag_info);
461017cb
TT		 710 }
711
4415a031
TT		 712 for (i = rq->page_cache.head; i != rq->page_cache.tail;
713 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
714 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
715
716 mlx5e_page_release(rq, dma_info, false);
717 }
f62b8bb8
AV		 718 mlx5_wq_destroy(&rq->wq_ctrl);
719}
720
6a9764ef
SM		 721static int mlx5e_create_rq(struct mlx5e_rq *rq,
722 struct mlx5e_rq_param *param)
f62b8bb8 723{
a43b25da 724 struct mlx5_core_dev *mdev = rq->mdev;
f62b8bb8
AV		 725
726 void *in;
727 void *rqc;
728 void *wq;
729 int inlen;
730 int err;
731
732 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
733 sizeof(u64) * rq->wq_ctrl.buf.npages;
1b9a07ee 734 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 735 if (!in)
736 return -ENOMEM;
737
738 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
739 wq = MLX5_ADDR_OF(rqc, rqc, wq);
740
741 memcpy(rqc, param->rqc, sizeof(param->rqc));
742
97de9f31 743 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 744 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
f62b8bb8 745 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 746 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 747 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
748
749 mlx5_fill_page_array(&rq->wq_ctrl.buf,
750 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
751
7db22ffb 752 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 753
754 kvfree(in);
755
756 return err;
757}
758
36350114
GP		 759static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
760 int next_state)
f62b8bb8
AV		 761{
762 struct mlx5e_channel *c = rq->channel;
a43b25da 763 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 764
765 void *in;
766 void *rqc;
767 int inlen;
768 int err;
769
770 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 771 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 772 if (!in)
773 return -ENOMEM;
774
775 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
776
777 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
778 MLX5_SET(rqc, rqc, state, next_state);
779
7db22ffb 780 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 781
782 kvfree(in);
783
784 return err;
785}
786
102722fc
GE		 787static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
788{
789 struct mlx5e_channel *c = rq->channel;
790 struct mlx5e_priv *priv = c->priv;
791 struct mlx5_core_dev *mdev = priv->mdev;
792
793 void *in;
794 void *rqc;
795 int inlen;
796 int err;
797
798 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 799 in = kvzalloc(inlen, GFP_KERNEL);
102722fc
GE		 800 if (!in)
801 return -ENOMEM;
802
803 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
804
805 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
806 MLX5_SET64(modify_rq_in, in, modify_bitmask,
807 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
808 MLX5_SET(rqc, rqc, scatter_fcs, enable);
809 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
810
811 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
812
813 kvfree(in);
814
815 return err;
816}
817
36350114
GP		 818static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
819{
820 struct mlx5e_channel *c = rq->channel;
a43b25da 821 struct mlx5_core_dev *mdev = c->mdev;
36350114
GP		 822 void *in;
823 void *rqc;
824 int inlen;
825 int err;
826
827 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1b9a07ee 828 in = kvzalloc(inlen, GFP_KERNEL);
36350114
GP		 829 if (!in)
830 return -ENOMEM;
831
832 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
833
834 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 835 MLX5_SET64(modify_rq_in, in, modify_bitmask,
836 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 837 MLX5_SET(rqc, rqc, vsd, vsd);
838 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
839
840 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
841
842 kvfree(in);
843
844 return err;
845}
846
3b77235b 847static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
f62b8bb8 848{
a43b25da 849 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
f62b8bb8
AV		 850}
851
852static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
853{
01c196a2 854 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8 855 struct mlx5e_channel *c = rq->channel;
a43b25da 856
f62b8bb8 857 struct mlx5_wq_ll *wq = &rq->wq;
6a9764ef 858 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
f62b8bb8 859
01c196a2 860 while (time_before(jiffies, exp_time)) {
6a9764ef 861 if (wq->cur_sz >= min_wqes)
f62b8bb8
AV		 862 return 0;
863
864 msleep(20);
865 }
866
a43b25da 867 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
6a9764ef 868 rq->rqn, wq->cur_sz, min_wqes);
f62b8bb8
AV		 869 return -ETIMEDOUT;
870}
871
f2fde18c
SM		 872static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
873{
874 struct mlx5_wq_ll *wq = &rq->wq;
875 struct mlx5e_rx_wqe *wqe;
876 __be16 wqe_ix_be;
877 u16 wqe_ix;
878
8484f9ed 879 /* UMR WQE (if in progress) is always at wq->head */
a071cb9f
TT		 880 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
881 rq->mpwqe.umr_in_progress)
21c59685 882 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 883
f2fde18c
SM		 884 while (!mlx5_wq_ll_is_empty(wq)) {
885 wqe_ix_be = *wq->tail_next;
886 wqe_ix = be16_to_cpu(wqe_ix_be);
887 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
888 rq->dealloc_wqe(rq, wqe_ix);
889 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
890 &wqe->next.next_wqe_index);
891 }
accd5883
TT		 892
893 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
894 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
895 * but yet to be re-posted.
896 */
897 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
898
899 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
900 rq->dealloc_wqe(rq, wqe_ix);
901 }
f2fde18c
SM		 902}
903
f62b8bb8 904static int mlx5e_open_rq(struct mlx5e_channel *c,
6a9764ef 905 struct mlx5e_params *params,
f62b8bb8
AV		 906 struct mlx5e_rq_param *param,
907 struct mlx5e_rq *rq)
908{
909 int err;
910
6a9764ef 911 err = mlx5e_alloc_rq(c, params, param, rq);
f62b8bb8
AV		 912 if (err)
913 return err;
914
3b77235b 915 err = mlx5e_create_rq(rq, param);
f62b8bb8 916 if (err)
3b77235b 917 goto err_free_rq;
f62b8bb8 918
36350114 919 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8 920 if (err)
3b77235b 921 goto err_destroy_rq;
f62b8bb8 922
6a9764ef 923 if (params->rx_am_enabled)
a1eaba4c 924 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
cb3c7fd4 925
f62b8bb8
AV		 926 return 0;
927
f62b8bb8
AV		 928err_destroy_rq:
929 mlx5e_destroy_rq(rq);
3b77235b
SM		 930err_free_rq:
931 mlx5e_free_rq(rq);
f62b8bb8
AV		 932
933 return err;
934}
935
acc6c595
SM		 936static void mlx5e_activate_rq(struct mlx5e_rq *rq)
937{
938 struct mlx5e_icosq *sq = &rq->channel->icosq;
939 u16 pi = sq->pc & sq->wq.sz_m1;
940 struct mlx5e_tx_wqe *nopwqe;
941
942 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
943 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
acc6c595
SM		 944 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
945 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
946}
947
948static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
f62b8bb8 949{
c0f1147d 950 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
f62b8bb8 951 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
acc6c595 952}
cb3c7fd4 953
acc6c595
SM		 954static void mlx5e_close_rq(struct mlx5e_rq *rq)
955{
956 cancel_work_sync(&rq->am.work);
f62b8bb8 957 mlx5e_destroy_rq(rq);
3b77235b
SM		 958 mlx5e_free_rx_descs(rq);
959 mlx5e_free_rq(rq);
f62b8bb8
AV		 960}
961
31391048 962static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
b5503b99 963{
31391048 964 kfree(sq->db.di);
b5503b99
SM		 965}
966
31391048 967static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
b5503b99
SM		 968{
969 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
970
31391048 971 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
b5503b99 972 GFP_KERNEL, numa);
31391048
SM		 973 if (!sq->db.di) {
974 mlx5e_free_xdpsq_db(sq);
b5503b99
SM		 975 return -ENOMEM;
976 }
977
978 return 0;
979}
980
31391048 981static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
6a9764ef 982 struct mlx5e_params *params,
31391048
SM		 983 struct mlx5e_sq_param *param,
984 struct mlx5e_xdpsq *sq)
985{
986 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 987 struct mlx5_core_dev *mdev = c->mdev;
31391048
SM		 988 int err;
989
990 sq->pdev = c->pdev;
991 sq->mkey_be = c->mkey_be;
992 sq->channel = c;
993 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef 994 sq->min_inline_mode = params->tx_min_inline_mode;
31391048 995
231243c8 996 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 997 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
998 if (err)
999 return err;
1000 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1001
231243c8 1002 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1003 if (err)
1004 goto err_sq_wq_destroy;
1005
1006 return 0;
1007
1008err_sq_wq_destroy:
1009 mlx5_wq_destroy(&sq->wq_ctrl);
1010
1011 return err;
1012}
1013
1014static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
1015{
1016 mlx5e_free_xdpsq_db(sq);
1017 mlx5_wq_destroy(&sq->wq_ctrl);
1018}
1019
1020static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
f62b8bb8 1021{
f10b7cc7 1022 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 1023}
1024
31391048 1025static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
f10b7cc7
SM		 1026{
1027 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1028
1029 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
1030 GFP_KERNEL, numa);
1031 if (!sq->db.ico_wqe)
1032 return -ENOMEM;
1033
1034 return 0;
1035}
1036
31391048 1037static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
31391048
SM		 1038 struct mlx5e_sq_param *param,
1039 struct mlx5e_icosq *sq)
f10b7cc7 1040{
31391048 1041 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1042 struct mlx5_core_dev *mdev = c->mdev;
31391048 1043 int err;
f10b7cc7 1044
31391048
SM		 1045 sq->mkey_be = c->mkey_be;
1046 sq->channel = c;
1047 sq->uar_map = mdev->mlx5e_res.bfreg.map;
f62b8bb8 1048
231243c8 1049 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048
SM		 1050 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
1051 if (err)
1052 return err;
1053 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1054
231243c8 1055 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
31391048
SM		 1056 if (err)
1057 goto err_sq_wq_destroy;
1058
1059 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
f62b8bb8
AV		 1060
1061 return 0;
31391048
SM		 1062
1063err_sq_wq_destroy:
1064 mlx5_wq_destroy(&sq->wq_ctrl);
1065
1066 return err;
f62b8bb8
AV		 1067}
1068
31391048 1069static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
f10b7cc7 1070{
31391048
SM		 1071 mlx5e_free_icosq_db(sq);
1072 mlx5_wq_destroy(&sq->wq_ctrl);
f10b7cc7
SM		 1073}
1074
31391048 1075static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
f10b7cc7 1076{
31391048
SM		 1077 kfree(sq->db.wqe_info);
1078 kfree(sq->db.dma_fifo);
f10b7cc7
SM		 1079}
1080
31391048 1081static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
b5503b99 1082{
31391048
SM		 1083 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1084 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
1085
31391048
SM		 1086 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
1087 GFP_KERNEL, numa);
1088 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
1089 GFP_KERNEL, numa);
77bdf895 1090 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
31391048
SM		 1091 mlx5e_free_txqsq_db(sq);
1092 return -ENOMEM;
b5503b99 1093 }
31391048
SM		 1094
1095 sq->dma_fifo_mask = df_sz - 1;
1096
1097 return 0;
b5503b99
SM		 1098}
1099
31391048 1100static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
acc6c595 1101 int txq_ix,
6a9764ef 1102 struct mlx5e_params *params,
31391048
SM		 1103 struct mlx5e_sq_param *param,
1104 struct mlx5e_txqsq *sq)
f62b8bb8 1105{
31391048 1106 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
a43b25da 1107 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8
AV		 1108 int err;
1109
f10b7cc7 1110 sq->pdev = c->pdev;
a43b25da 1111 sq->tstamp = c->tstamp;
7c39afb3 1112 sq->clock = &mdev->clock;
f10b7cc7
SM		 1113 sq->mkey_be = c->mkey_be;
1114 sq->channel = c;
acc6c595 1115 sq->txq_ix = txq_ix;
aff26157 1116 sq->uar_map = mdev->mlx5e_res.bfreg.map;
6a9764ef
SM		 1117 sq->max_inline = params->tx_max_inline;
1118 sq->min_inline_mode = params->tx_min_inline_mode;
2ac9cfe7
IT		 1119 if (MLX5_IPSEC_DEV(c->priv->mdev))
1120 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
f10b7cc7 1121
231243c8 1122 param->wq.db_numa_node = cpu_to_node(c->cpu);
31391048 1123 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
f62b8bb8 1124 if (err)
aff26157 1125 return err;
31391048 1126 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
f62b8bb8 1127
231243c8 1128 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
7ec0bb22 1129 if (err)
f62b8bb8
AV		 1130 goto err_sq_wq_destroy;
1131
31391048 1132 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
f62b8bb8
AV		 1133
1134 return 0;
1135
1136err_sq_wq_destroy:
1137 mlx5_wq_destroy(&sq->wq_ctrl);
1138
f62b8bb8
AV		 1139 return err;
1140}
1141
31391048 1142static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1143{
31391048 1144 mlx5e_free_txqsq_db(sq);
f62b8bb8 1145 mlx5_wq_destroy(&sq->wq_ctrl);
f62b8bb8
AV		 1146}
1147
33ad9711
SM		 1148struct mlx5e_create_sq_param {
1149 struct mlx5_wq_ctrl *wq_ctrl;
1150 u32 cqn;
1151 u32 tisn;
1152 u8 tis_lst_sz;
1153 u8 min_inline_mode;
1154};
1155
a43b25da 1156static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
33ad9711
SM		 1157 struct mlx5e_sq_param *param,
1158 struct mlx5e_create_sq_param *csp,
1159 u32 *sqn)
f62b8bb8 1160{
f62b8bb8
AV		 1161 void *in;
1162 void *sqc;
1163 void *wq;
1164 int inlen;
1165 int err;
1166
1167 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
33ad9711 1168 sizeof(u64) * csp->wq_ctrl->buf.npages;
1b9a07ee 1169 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1170 if (!in)
1171 return -ENOMEM;
1172
1173 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1174 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1175
1176 memcpy(sqc, param->sqc, sizeof(param->sqc));
33ad9711
SM		 1177 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1178 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1179 MLX5_SET(sqc, sqc, cqn, csp->cqn);
a6f402e4
SM		 1180
1181 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
33ad9711 1182 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
a6f402e4 1183
33ad9711 1184 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f62b8bb8
AV		 1185
1186 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
a43b25da 1187 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
33ad9711 1188 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
68cdf5d6 1189 MLX5_ADAPTER_PAGE_SHIFT);
33ad9711 1190 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
f62b8bb8 1191
33ad9711 1192 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
f62b8bb8 1193
33ad9711 1194 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
f62b8bb8
AV		 1195
1196 kvfree(in);
1197
1198 return err;
1199}
1200
33ad9711
SM		 1201struct mlx5e_modify_sq_param {
1202 int curr_state;
1203 int next_state;
1204 bool rl_update;
1205 int rl_index;
1206};
1207
a43b25da 1208static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
33ad9711 1209 struct mlx5e_modify_sq_param *p)
f62b8bb8 1210{
f62b8bb8
AV		 1211 void *in;
1212 void *sqc;
1213 int inlen;
1214 int err;
1215
1216 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1b9a07ee 1217 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1218 if (!in)
1219 return -ENOMEM;
1220
1221 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1222
33ad9711
SM		 1223 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1224 MLX5_SET(sqc, sqc, state, p->next_state);
1225 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
507f0c81 1226 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
33ad9711 1227 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
507f0c81 1228 }
f62b8bb8 1229
33ad9711 1230 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
f62b8bb8
AV		 1231
1232 kvfree(in);
1233
1234 return err;
1235}
1236
a43b25da 1237static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
33ad9711 1238{
a43b25da 1239 mlx5_core_destroy_sq(mdev, sqn);
f62b8bb8
AV		 1240}
1241
a43b25da 1242static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
31391048
SM		 1243 struct mlx5e_sq_param *param,
1244 struct mlx5e_create_sq_param *csp,
1245 u32 *sqn)
f62b8bb8 1246{
33ad9711 1247 struct mlx5e_modify_sq_param msp = {0};
31391048
SM		 1248 int err;
1249
a43b25da 1250 err = mlx5e_create_sq(mdev, param, csp, sqn);
31391048
SM		 1251 if (err)
1252 return err;
1253
1254 msp.curr_state = MLX5_SQC_STATE_RST;
1255 msp.next_state = MLX5_SQC_STATE_RDY;
a43b25da 1256 err = mlx5e_modify_sq(mdev, *sqn, &msp);
31391048 1257 if (err)
a43b25da 1258 mlx5e_destroy_sq(mdev, *sqn);
31391048
SM		 1259
1260 return err;
1261}
1262
7f859ecf
SM		 1263static int mlx5e_set_sq_maxrate(struct net_device *dev,
1264 struct mlx5e_txqsq *sq, u32 rate);
1265
31391048 1266static int mlx5e_open_txqsq(struct mlx5e_channel *c,
a43b25da 1267 u32 tisn,
acc6c595 1268 int txq_ix,
6a9764ef 1269 struct mlx5e_params *params,
31391048
SM		 1270 struct mlx5e_sq_param *param,
1271 struct mlx5e_txqsq *sq)
1272{
1273 struct mlx5e_create_sq_param csp = {};
7f859ecf 1274 u32 tx_rate;
f62b8bb8
AV		 1275 int err;
1276
6a9764ef 1277 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
f62b8bb8
AV		 1278 if (err)
1279 return err;
1280
a43b25da 1281 csp.tisn = tisn;
31391048 1282 csp.tis_lst_sz = 1;
33ad9711
SM		 1283 csp.cqn = sq->cq.mcq.cqn;
1284 csp.wq_ctrl = &sq->wq_ctrl;
1285 csp.min_inline_mode = sq->min_inline_mode;
a43b25da 1286 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
f62b8bb8 1287 if (err)
31391048 1288 goto err_free_txqsq;
f62b8bb8 1289
a43b25da 1290 tx_rate = c->priv->tx_rates[sq->txq_ix];
7f859ecf 1291 if (tx_rate)
a43b25da 1292 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
7f859ecf 1293
f62b8bb8
AV		 1294 return 0;
1295
31391048 1296err_free_txqsq:
3b77235b 1297 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
31391048 1298 mlx5e_free_txqsq(sq);
f62b8bb8
AV		 1299
1300 return err;
1301}
1302
acc6c595
SM		 1303static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1304{
a43b25da 1305 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
acc6c595
SM		 1306 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1307 netdev_tx_reset_queue(sq->txq);
1308 netif_tx_start_queue(sq->txq);
1309}
1310
f62b8bb8
AV		 1311static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1312{
1313 __netif_tx_lock_bh(txq);
1314 netif_tx_stop_queue(txq);
1315 __netif_tx_unlock_bh(txq);
1316}
1317
acc6c595 1318static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
f62b8bb8 1319{
33ad9711 1320 struct mlx5e_channel *c = sq->channel;
33ad9711 1321
c0f1147d 1322 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
6e8dd6d6 1323 /* prevent netif_tx_wake_queue */
33ad9711 1324 napi_synchronize(&c->napi);
29429f33 1325
31391048 1326 netif_tx_disable_queue(sq->txq);
f62b8bb8 1327
31391048
SM		 1328 /* last doorbell out, godspeed .. */
1329 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1330 struct mlx5e_tx_wqe *nop;
864b2d71 1331
77bdf895 1332 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
31391048
SM		 1333 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1334 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
29429f33 1335 }
acc6c595
SM		 1336}
1337
1338static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1339{
1340 struct mlx5e_channel *c = sq->channel;
a43b25da 1341 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1342
a43b25da 1343 mlx5e_destroy_sq(mdev, sq->sqn);
33ad9711
SM		 1344 if (sq->rate_limit)
1345 mlx5_rl_remove_rate(mdev, sq->rate_limit);
31391048
SM		 1346 mlx5e_free_txqsq_descs(sq);
1347 mlx5e_free_txqsq(sq);
1348}
1349
1350static int mlx5e_open_icosq(struct mlx5e_channel *c,
6a9764ef 1351 struct mlx5e_params *params,
31391048
SM		 1352 struct mlx5e_sq_param *param,
1353 struct mlx5e_icosq *sq)
1354{
1355 struct mlx5e_create_sq_param csp = {};
1356 int err;
1357
6a9764ef 1358 err = mlx5e_alloc_icosq(c, param, sq);
31391048
SM		 1359 if (err)
1360 return err;
1361
1362 csp.cqn = sq->cq.mcq.cqn;
1363 csp.wq_ctrl = &sq->wq_ctrl;
6a9764ef 1364 csp.min_inline_mode = params->tx_min_inline_mode;
31391048 1365 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1366 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1367 if (err)
1368 goto err_free_icosq;
1369
1370 return 0;
1371
1372err_free_icosq:
1373 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1374 mlx5e_free_icosq(sq);
1375
1376 return err;
1377}
1378
1379static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1380{
1381 struct mlx5e_channel *c = sq->channel;
1382
1383 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1384 napi_synchronize(&c->napi);
1385
a43b25da 1386 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1387 mlx5e_free_icosq(sq);
1388}
1389
1390static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
6a9764ef 1391 struct mlx5e_params *params,
31391048
SM		 1392 struct mlx5e_sq_param *param,
1393 struct mlx5e_xdpsq *sq)
1394{
1395 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1396 struct mlx5e_create_sq_param csp = {};
31391048
SM		 1397 unsigned int inline_hdr_sz = 0;
1398 int err;
1399 int i;
1400
6a9764ef 1401 err = mlx5e_alloc_xdpsq(c, params, param, sq);
31391048
SM		 1402 if (err)
1403 return err;
1404
1405 csp.tis_lst_sz = 1;
a43b25da 1406 csp.tisn = c->priv->tisn[0]; /* tc = 0 */
31391048
SM		 1407 csp.cqn = sq->cq.mcq.cqn;
1408 csp.wq_ctrl = &sq->wq_ctrl;
1409 csp.min_inline_mode = sq->min_inline_mode;
1410 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
a43b25da 1411 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
31391048
SM		 1412 if (err)
1413 goto err_free_xdpsq;
1414
1415 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1416 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1417 ds_cnt++;
1418 }
1419
1420 /* Pre initialize fixed WQE fields */
1421 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1422 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1423 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1424 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1425 struct mlx5_wqe_data_seg *dseg;
1426
1427 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1428 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1429
1430 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1431 dseg->lkey = sq->mkey_be;
1432 }
1433
1434 return 0;
1435
1436err_free_xdpsq:
1437 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1438 mlx5e_free_xdpsq(sq);
1439
1440 return err;
1441}
1442
1443static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1444{
1445 struct mlx5e_channel *c = sq->channel;
1446
1447 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1448 napi_synchronize(&c->napi);
1449
a43b25da 1450 mlx5e_destroy_sq(c->mdev, sq->sqn);
31391048
SM		 1451 mlx5e_free_xdpsq_descs(sq);
1452 mlx5e_free_xdpsq(sq);
f62b8bb8
AV		 1453}
1454
95b6c6a5
EBE		 1455static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1456 struct mlx5e_cq_param *param,
1457 struct mlx5e_cq *cq)
f62b8bb8 1458{
f62b8bb8
AV		 1459 struct mlx5_core_cq *mcq = &cq->mcq;
1460 int eqn_not_used;
0b6e26ce 1461 unsigned int irqn;
f62b8bb8
AV		 1462 int err;
1463 u32 i;
1464
f62b8bb8
AV		 1465 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1466 &cq->wq_ctrl);
1467 if (err)
1468 return err;
1469
1470 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1471
f62b8bb8
AV		 1472 mcq->cqe_sz = 64;
1473 mcq->set_ci_db = cq->wq_ctrl.db.db;
1474 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1475 *mcq->set_ci_db = 0;
1476 *mcq->arm_db = 0;
1477 mcq->vector = param->eq_ix;
1478 mcq->comp = mlx5e_completion_event;
1479 mcq->event = mlx5e_cq_error_event;
1480 mcq->irqn = irqn;
f62b8bb8
AV		 1481
1482 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1483 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1484
1485 cqe->op_own = 0xf1;
1486 }
1487
a43b25da 1488 cq->mdev = mdev;
f62b8bb8
AV		 1489
1490 return 0;
1491}
1492
95b6c6a5
EBE		 1493static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1494 struct mlx5e_cq_param *param,
1495 struct mlx5e_cq *cq)
1496{
1497 struct mlx5_core_dev *mdev = c->priv->mdev;
1498 int err;
1499
231243c8
SM		 1500 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1501 param->wq.db_numa_node = cpu_to_node(c->cpu);
95b6c6a5
EBE		 1502 param->eq_ix = c->ix;
1503
1504 err = mlx5e_alloc_cq_common(mdev, param, cq);
1505
1506 cq->napi = &c->napi;
1507 cq->channel = c;
1508
1509 return err;
1510}
1511
3b77235b 1512static void mlx5e_free_cq(struct mlx5e_cq *cq)
f62b8bb8 1513{
1c1b5228 1514 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1515}
1516
3b77235b 1517static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
f62b8bb8 1518{
a43b25da 1519 struct mlx5_core_dev *mdev = cq->mdev;
f62b8bb8
AV		 1520 struct mlx5_core_cq *mcq = &cq->mcq;
1521
1522 void *in;
1523 void *cqc;
1524 int inlen;
0b6e26ce 1525 unsigned int irqn_not_used;
f62b8bb8
AV		 1526 int eqn;
1527 int err;
1528
1529 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1530 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1b9a07ee 1531 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 1532 if (!in)
1533 return -ENOMEM;
1534
1535 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1536
1537 memcpy(cqc, param->cqc, sizeof(param->cqc));
1538
1c1b5228
TT		 1539 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1540 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1541
1542 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1543
9908aa29 1544 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8 1545 MLX5_SET(cqc, cqc, c_eqn, eqn);
30aa60b3 1546 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1c1b5228 1547 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1548 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1549 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1550
1551 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1552
1553 kvfree(in);
1554
1555 if (err)
1556 return err;
1557
1558 mlx5e_cq_arm(cq);
1559
1560 return 0;
1561}
1562
3b77235b 1563static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
f62b8bb8 1564{
a43b25da 1565 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
f62b8bb8
AV		 1566}
1567
1568static int mlx5e_open_cq(struct mlx5e_channel *c,
6a9764ef 1569 struct mlx5e_cq_moder moder,
f62b8bb8 1570 struct mlx5e_cq_param *param,
6a9764ef 1571 struct mlx5e_cq *cq)
f62b8bb8 1572{
a43b25da 1573 struct mlx5_core_dev *mdev = c->mdev;
f62b8bb8 1574 int err;
f62b8bb8 1575
3b77235b 1576 err = mlx5e_alloc_cq(c, param, cq);
f62b8bb8
AV		 1577 if (err)
1578 return err;
1579
3b77235b 1580 err = mlx5e_create_cq(cq, param);
f62b8bb8 1581 if (err)
3b77235b 1582 goto err_free_cq;
f62b8bb8 1583
7524a5d8 1584 if (MLX5_CAP_GEN(mdev, cq_moderation))
6a9764ef 1585 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
f62b8bb8
AV		 1586 return 0;
1587
3b77235b
SM		 1588err_free_cq:
1589 mlx5e_free_cq(cq);
f62b8bb8
AV		 1590
1591 return err;
1592}
1593
1594static void mlx5e_close_cq(struct mlx5e_cq *cq)
1595{
f62b8bb8 1596 mlx5e_destroy_cq(cq);
3b77235b 1597 mlx5e_free_cq(cq);
f62b8bb8
AV		 1598}
1599
231243c8
SM		 1600static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1601{
1602 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1603}
1604
f62b8bb8 1605static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
6a9764ef 1606 struct mlx5e_params *params,
f62b8bb8
AV		 1607 struct mlx5e_channel_param *cparam)
1608{
f62b8bb8
AV		 1609 int err;
1610 int tc;
1611
1612 for (tc = 0; tc < c->num_tc; tc++) {
6a9764ef
SM		 1613 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1614 &cparam->tx_cq, &c->sq[tc].cq);
f62b8bb8
AV		 1615 if (err)
1616 goto err_close_tx_cqs;
f62b8bb8
AV		 1617 }
1618
1619 return 0;
1620
1621err_close_tx_cqs:
1622 for (tc--; tc >= 0; tc--)
1623 mlx5e_close_cq(&c->sq[tc].cq);
1624
1625 return err;
1626}
1627
1628static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1629{
1630 int tc;
1631
1632 for (tc = 0; tc < c->num_tc; tc++)
1633 mlx5e_close_cq(&c->sq[tc].cq);
1634}
1635
1636static int mlx5e_open_sqs(struct mlx5e_channel *c,
6a9764ef 1637 struct mlx5e_params *params,
f62b8bb8
AV		 1638 struct mlx5e_channel_param *cparam)
1639{
1640 int err;
1641 int tc;
1642
6a9764ef
SM		 1643 for (tc = 0; tc < params->num_tc; tc++) {
1644 int txq_ix = c->ix + tc * params->num_channels;
acc6c595 1645
a43b25da
SM		 1646 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1647 params, &cparam->sq, &c->sq[tc]);
f62b8bb8
AV		 1648 if (err)
1649 goto err_close_sqs;
1650 }
1651
1652 return 0;
1653
1654err_close_sqs:
1655 for (tc--; tc >= 0; tc--)
31391048 1656 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1657
1658 return err;
1659}
1660
1661static void mlx5e_close_sqs(struct mlx5e_channel *c)
1662{
1663 int tc;
1664
1665 for (tc = 0; tc < c->num_tc; tc++)
31391048 1666 mlx5e_close_txqsq(&c->sq[tc]);
f62b8bb8
AV		 1667}
1668
507f0c81 1669static int mlx5e_set_sq_maxrate(struct net_device *dev,
31391048 1670 struct mlx5e_txqsq *sq, u32 rate)
507f0c81
YP		 1671{
1672 struct mlx5e_priv *priv = netdev_priv(dev);
1673 struct mlx5_core_dev *mdev = priv->mdev;
33ad9711 1674 struct mlx5e_modify_sq_param msp = {0};
507f0c81
YP		 1675 u16 rl_index = 0;
1676 int err;
1677
1678 if (rate == sq->rate_limit)
1679 /* nothing to do */
1680 return 0;
1681
1682 if (sq->rate_limit)
1683 /* remove current rl index to free space to next ones */
1684 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1685
1686 sq->rate_limit = 0;
1687
1688 if (rate) {
1689 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1690 if (err) {
1691 netdev_err(dev, "Failed configuring rate %u: %d\n",
1692 rate, err);
1693 return err;
1694 }
1695 }
1696
33ad9711
SM		 1697 msp.curr_state = MLX5_SQC_STATE_RDY;
1698 msp.next_state = MLX5_SQC_STATE_RDY;
1699 msp.rl_index = rl_index;
1700 msp.rl_update = true;
a43b25da 1701 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
507f0c81
YP		 1702 if (err) {
1703 netdev_err(dev, "Failed configuring rate %u: %d\n",
1704 rate, err);
1705 /* remove the rate from the table */
1706 if (rate)
1707 mlx5_rl_remove_rate(mdev, rate);
1708 return err;
1709 }
1710
1711 sq->rate_limit = rate;
1712 return 0;
1713}
1714
1715static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1716{
1717 struct mlx5e_priv *priv = netdev_priv(dev);
1718 struct mlx5_core_dev *mdev = priv->mdev;
acc6c595 1719 struct mlx5e_txqsq *sq = priv->txq2sq[index];
507f0c81
YP		 1720 int err = 0;
1721
1722 if (!mlx5_rl_is_supported(mdev)) {
1723 netdev_err(dev, "Rate limiting is not supported on this device\n");
1724 return -EINVAL;
1725 }
1726
1727 /* rate is given in Mb/sec, HW config is in Kb/sec */
1728 rate = rate << 10;
1729
1730 /* Check whether rate in valid range, 0 is always valid */
1731 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1732 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1733 return -ERANGE;
1734 }
1735
1736 mutex_lock(&priv->state_lock);
1737 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1738 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1739 if (!err)
1740 priv->tx_rates[index] = rate;
1741 mutex_unlock(&priv->state_lock);
1742
1743 return err;
1744}
1745
f62b8bb8 1746static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
6a9764ef 1747 struct mlx5e_params *params,
f62b8bb8
AV		 1748 struct mlx5e_channel_param *cparam,
1749 struct mlx5e_channel **cp)
1750{
6a9764ef 1751 struct mlx5e_cq_moder icocq_moder = {0, 0};
f62b8bb8 1752 struct net_device *netdev = priv->netdev;
231243c8 1753 int cpu = mlx5e_get_cpu(priv, ix);
f62b8bb8 1754 struct mlx5e_channel *c;
a8c2eb15 1755 unsigned int irq;
f62b8bb8 1756 int err;
a8c2eb15 1757 int eqn;
f62b8bb8 1758
231243c8 1759 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
f62b8bb8
AV		 1760 if (!c)
1761 return -ENOMEM;
1762
1763 c->priv = priv;
a43b25da
SM		 1764 c->mdev = priv->mdev;
1765 c->tstamp = &priv->tstamp;
f62b8bb8 1766 c->ix = ix;
231243c8 1767 c->cpu = cpu;
f62b8bb8
AV		 1768 c->pdev = &priv->mdev->pdev->dev;
1769 c->netdev = priv->netdev;
b50d292b 1770 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
6a9764ef
SM		 1771 c->num_tc = params->num_tc;
1772 c->xdp = !!params->xdp_prog;
cb3c7fd4 1773
a8c2eb15
TT		 1774 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1775 c->irq_desc = irq_to_desc(irq);
1776
f62b8bb8
AV		 1777 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1778
6a9764ef 1779 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
f62b8bb8
AV		 1780 if (err)
1781 goto err_napi_del;
1782
6a9764ef 1783 err = mlx5e_open_tx_cqs(c, params, cparam);
d3c9bc27
TT		 1784 if (err)
1785 goto err_close_icosq_cq;
1786
6a9764ef 1787 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
f62b8bb8
AV		 1788 if (err)
1789 goto err_close_tx_cqs;
f62b8bb8 1790
d7a0ecab 1791 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
6a9764ef
SM		 1792 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1793 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
d7a0ecab
SM		 1794 if (err)
1795 goto err_close_rx_cq;
1796
f62b8bb8
AV		 1797 napi_enable(&c->napi);
1798
6a9764ef 1799 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1800 if (err)
1801 goto err_disable_napi;
1802
6a9764ef 1803 err = mlx5e_open_sqs(c, params, cparam);
d3c9bc27
TT		 1804 if (err)
1805 goto err_close_icosq;
1806
6a9764ef 1807 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
d7a0ecab
SM		 1808 if (err)
1809 goto err_close_sqs;
b5503b99 1810
6a9764ef 1811 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
f62b8bb8 1812 if (err)
b5503b99 1813 goto err_close_xdp_sq;
f62b8bb8 1814
f62b8bb8
AV		 1815 *cp = c;
1816
1817 return 0;
b5503b99 1818err_close_xdp_sq:
d7a0ecab 1819 if (c->xdp)
31391048 1820 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8
AV		 1821
1822err_close_sqs:
1823 mlx5e_close_sqs(c);
1824
d3c9bc27 1825err_close_icosq:
31391048 1826 mlx5e_close_icosq(&c->icosq);
d3c9bc27 1827
f62b8bb8
AV		 1828err_disable_napi:
1829 napi_disable(&c->napi);
d7a0ecab 1830 if (c->xdp)
31871f87 1831 mlx5e_close_cq(&c->rq.xdpsq.cq);
d7a0ecab
SM		 1832
1833err_close_rx_cq:
f62b8bb8
AV		 1834 mlx5e_close_cq(&c->rq.cq);
1835
1836err_close_tx_cqs:
1837 mlx5e_close_tx_cqs(c);
1838
d3c9bc27
TT		 1839err_close_icosq_cq:
1840 mlx5e_close_cq(&c->icosq.cq);
1841
f62b8bb8
AV		 1842err_napi_del:
1843 netif_napi_del(&c->napi);
1844 kfree(c);
1845
1846 return err;
1847}
1848
acc6c595
SM		 1849static void mlx5e_activate_channel(struct mlx5e_channel *c)
1850{
1851 int tc;
1852
1853 for (tc = 0; tc < c->num_tc; tc++)
1854 mlx5e_activate_txqsq(&c->sq[tc]);
1855 mlx5e_activate_rq(&c->rq);
231243c8 1856 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
acc6c595
SM		 1857}
1858
1859static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1860{
1861 int tc;
1862
1863 mlx5e_deactivate_rq(&c->rq);
1864 for (tc = 0; tc < c->num_tc; tc++)
1865 mlx5e_deactivate_txqsq(&c->sq[tc]);
1866}
1867
f62b8bb8
AV		 1868static void mlx5e_close_channel(struct mlx5e_channel *c)
1869{
1870 mlx5e_close_rq(&c->rq);
b5503b99 1871 if (c->xdp)
31391048 1872 mlx5e_close_xdpsq(&c->rq.xdpsq);
f62b8bb8 1873 mlx5e_close_sqs(c);
31391048 1874 mlx5e_close_icosq(&c->icosq);
f62b8bb8 1875 napi_disable(&c->napi);
b5503b99 1876 if (c->xdp)
31871f87 1877 mlx5e_close_cq(&c->rq.xdpsq.cq);
f62b8bb8
AV		 1878 mlx5e_close_cq(&c->rq.cq);
1879 mlx5e_close_tx_cqs(c);
d3c9bc27 1880 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1881 netif_napi_del(&c->napi);
7ae92ae5 1882
f62b8bb8
AV		 1883 kfree(c);
1884}
1885
1886static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
6a9764ef 1887 struct mlx5e_params *params,
f62b8bb8
AV		 1888 struct mlx5e_rq_param *param)
1889{
1890 void *rqc = param->rqc;
1891 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1892
6a9764ef 1893 switch (params->rq_wq_type) {
461017cb 1894 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef
SM		 1895 MLX5_SET(wq, wq, log_wqe_num_of_strides, params->mpwqe_log_num_strides - 9);
1896 MLX5_SET(wq, wq, log_wqe_stride_size, params->mpwqe_log_stride_sz - 6);
461017cb
TT		 1897 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1898 break;
1899 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1900 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1901 }
1902
f62b8bb8
AV		 1903 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1904 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
6a9764ef 1905 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_size);
b50d292b 1906 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1907 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
6a9764ef 1908 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
102722fc 1909 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
f62b8bb8 1910
311c7c71 1911 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8
AV		 1912 param->wq.linear = 1;
1913}
1914
556dd1b9
TT		 1915static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1916{
1917 void *rqc = param->rqc;
1918 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1919
1920 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1921 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1922}
1923
d3c9bc27
TT		 1924static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1925 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1926{
1927 void *sqc = param->sqc;
1928 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1929
f62b8bb8 1930 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1931 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1932
311c7c71 1933 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1934}
1935
1936static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
6a9764ef 1937 struct mlx5e_params *params,
d3c9bc27
TT		 1938 struct mlx5e_sq_param *param)
1939{
1940 void *sqc = param->sqc;
1941 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1942
1943 mlx5e_build_sq_param_common(priv, param);
6a9764ef 1944 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2ac9cfe7 1945 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
f62b8bb8
AV		 1946}
1947
1948static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1949 struct mlx5e_cq_param *param)
1950{
1951 void *cqc = param->cqc;
1952
30aa60b3 1953 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
f62b8bb8
AV		 1954}
1955
1956static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1957 struct mlx5e_params *params,
f62b8bb8
AV		 1958 struct mlx5e_cq_param *param)
1959{
1960 void *cqc = param->cqc;
461017cb 1961 u8 log_cq_size;
f62b8bb8 1962
6a9764ef 1963 switch (params->rq_wq_type) {
461017cb 1964 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
6a9764ef 1965 log_cq_size = params->log_rq_size + params->mpwqe_log_num_strides;
461017cb
TT		 1966 break;
1967 default: /* MLX5_WQ_TYPE_LINKED_LIST */
6a9764ef 1968 log_cq_size = params->log_rq_size;
461017cb
TT		 1969 }
1970
1971 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
6a9764ef 1972 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1973 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1974 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1975 }
f62b8bb8
AV		 1976
1977 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1978 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1979}
1980
1981static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
6a9764ef 1982 struct mlx5e_params *params,
f62b8bb8
AV		 1983 struct mlx5e_cq_param *param)
1984{
1985 void *cqc = param->cqc;
1986
6a9764ef 1987 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
f62b8bb8
AV		 1988
1989 mlx5e_build_common_cq_param(priv, param);
0088cbbc 1990 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
f62b8bb8
AV		 1991}
1992
d3c9bc27 1993static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 1994 u8 log_wq_size,
1995 struct mlx5e_cq_param *param)
d3c9bc27
TT		 1996{
1997 void *cqc = param->cqc;
1998
1999 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
2000
2001 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 2002
2003 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 2004}
2005
2006static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
6a9764ef
SM		 2007 u8 log_wq_size,
2008 struct mlx5e_sq_param *param)
d3c9bc27
TT		 2009{
2010 void *sqc = param->sqc;
2011 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2012
2013 mlx5e_build_sq_param_common(priv, param);
2014
2015 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 2016 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27
TT		 2017}
2018
b5503b99 2019static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
6a9764ef 2020 struct mlx5e_params *params,
b5503b99
SM		 2021 struct mlx5e_sq_param *param)
2022{
2023 void *sqc = param->sqc;
2024 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2025
2026 mlx5e_build_sq_param_common(priv, param);
6a9764ef 2027 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
b5503b99
SM		 2028}
2029
6a9764ef
SM		 2030static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2031 struct mlx5e_params *params,
2032 struct mlx5e_channel_param *cparam)
f62b8bb8 2033{
bc77b240 2034 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 2035
6a9764ef
SM		 2036 mlx5e_build_rq_param(priv, params, &cparam->rq);
2037 mlx5e_build_sq_param(priv, params, &cparam->sq);
2038 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2039 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2040 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2041 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2042 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
f62b8bb8
AV		 2043}
2044
55c2503d
SM		 2045int mlx5e_open_channels(struct mlx5e_priv *priv,
2046 struct mlx5e_channels *chs)
f62b8bb8 2047{
6b87663f 2048 struct mlx5e_channel_param *cparam;
03289b88 2049 int err = -ENOMEM;
f62b8bb8 2050 int i;
f62b8bb8 2051
6a9764ef 2052 chs->num = chs->params.num_channels;
03289b88 2053
ff9c852f 2054 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
6b87663f 2055 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
acc6c595
SM		 2056 if (!chs->c || !cparam)
2057 goto err_free;
f62b8bb8 2058
6a9764ef 2059 mlx5e_build_channel_param(priv, &chs->params, cparam);
ff9c852f 2060 for (i = 0; i < chs->num; i++) {
6a9764ef 2061 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
f62b8bb8
AV		 2062 if (err)
2063 goto err_close_channels;
2064 }
2065
6b87663f 2066 kfree(cparam);
f62b8bb8
AV		 2067 return 0;
2068
2069err_close_channels:
2070 for (i--; i >= 0; i--)
ff9c852f 2071 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2072
acc6c595 2073err_free:
ff9c852f 2074 kfree(chs->c);
6b87663f 2075 kfree(cparam);
ff9c852f 2076 chs->num = 0;
f62b8bb8
AV		 2077 return err;
2078}
2079
acc6c595 2080static void mlx5e_activate_channels(struct mlx5e_channels *chs)
f62b8bb8
AV		 2081{
2082 int i;
2083
acc6c595
SM		 2084 for (i = 0; i < chs->num; i++)
2085 mlx5e_activate_channel(chs->c[i]);
2086}
2087
2088static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2089{
2090 int err = 0;
2091 int i;
2092
2093 for (i = 0; i < chs->num; i++) {
2094 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2095 if (err)
2096 break;
2097 }
2098
2099 return err;
2100}
2101
2102static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2103{
2104 int i;
2105
2106 for (i = 0; i < chs->num; i++)
2107 mlx5e_deactivate_channel(chs->c[i]);
2108}
2109
55c2503d 2110void mlx5e_close_channels(struct mlx5e_channels *chs)
acc6c595
SM		 2111{
2112 int i;
c3b7c5c9 2113
ff9c852f
SM		 2114 for (i = 0; i < chs->num; i++)
2115 mlx5e_close_channel(chs->c[i]);
f62b8bb8 2116
ff9c852f
SM		 2117 kfree(chs->c);
2118 chs->num = 0;
f62b8bb8
AV		 2119}
2120
a5f97fee
SM		 2121static int
2122mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 2123{
2124 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 2125 void *rqtc;
2126 int inlen;
2127 int err;
1da36696 2128 u32 *in;
a5f97fee 2129 int i;
f62b8bb8 2130
f62b8bb8 2131 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2132 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2133 if (!in)
2134 return -ENOMEM;
2135
2136 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2137
2138 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2139 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2140
a5f97fee
SM		 2141 for (i = 0; i < sz; i++)
2142 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2be6967c 2143
398f3351
HHZ		 2144 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2145 if (!err)
2146 rqt->enabled = true;
f62b8bb8
AV		 2147
2148 kvfree(in);
1da36696
TT		 2149 return err;
2150}
2151
cb67b832 2152void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 2153{
398f3351
HHZ		 2154 rqt->enabled = false;
2155 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 2156}
2157
8f493ffd 2158int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2159{
2160 struct mlx5e_rqt *rqt = &priv->indir_rqt;
8f493ffd 2161 int err;
6bfd390b 2162
8f493ffd
SM		 2163 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2164 if (err)
2165 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2166 return err;
6bfd390b
HHZ		 2167}
2168
cb67b832 2169int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 2170{
398f3351 2171 struct mlx5e_rqt *rqt;
1da36696
TT		 2172 int err;
2173 int ix;
2174
6bfd390b 2175 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351 2176 rqt = &priv->direct_tir[ix].rqt;
a5f97fee 2177 err = mlx5e_create_rqt(priv, 1 /*size */, rqt);
1da36696
TT		 2178 if (err)
2179 goto err_destroy_rqts;
2180 }
2181
2182 return 0;
2183
2184err_destroy_rqts:
8f493ffd 2185 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
1da36696 2186 for (ix--; ix >= 0; ix--)
398f3351 2187 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 2188
f62b8bb8
AV		 2189 return err;
2190}
2191
8f493ffd
SM		 2192void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2193{
2194 int i;
2195
2196 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2197 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2198}
2199
a5f97fee
SM		 2200static int mlx5e_rx_hash_fn(int hfunc)
2201{
2202 return (hfunc == ETH_RSS_HASH_TOP) ?
2203 MLX5_RX_HASH_FN_TOEPLITZ :
2204 MLX5_RX_HASH_FN_INVERTED_XOR8;
2205}
2206
2207static int mlx5e_bits_invert(unsigned long a, int size)
2208{
2209 int inv = 0;
2210 int i;
2211
2212 for (i = 0; i < size; i++)
2213 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2214
2215 return inv;
2216}
2217
2218static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2219 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2220{
2221 int i;
2222
2223 for (i = 0; i < sz; i++) {
2224 u32 rqn;
2225
2226 if (rrp.is_rss) {
2227 int ix = i;
2228
2229 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2230 ix = mlx5e_bits_invert(i, ilog2(sz));
2231
6a9764ef 2232 ix = priv->channels.params.indirection_rqt[ix];
a5f97fee
SM		 2233 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2234 } else {
2235 rqn = rrp.rqn;
2236 }
2237 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2238 }
2239}
2240
2241int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2242 struct mlx5e_redirect_rqt_param rrp)
5c50368f
AS		 2243{
2244 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 2245 void *rqtc;
2246 int inlen;
1da36696 2247 u32 *in;
5c50368f
AS		 2248 int err;
2249
5c50368f 2250 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1b9a07ee 2251 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2252 if (!in)
2253 return -ENOMEM;
2254
2255 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2256
2257 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5c50368f 2258 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
a5f97fee 2259 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
1da36696 2260 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 2261
2262 kvfree(in);
5c50368f
AS		 2263 return err;
2264}
2265
a5f97fee
SM		 2266static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2267 struct mlx5e_redirect_rqt_param rrp)
2268{
2269 if (!rrp.is_rss)
2270 return rrp.rqn;
2271
2272 if (ix >= rrp.rss.channels->num)
2273 return priv->drop_rq.rqn;
2274
2275 return rrp.rss.channels->c[ix]->rq.rqn;
2276}
2277
2278static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2279 struct mlx5e_redirect_rqt_param rrp)
40ab6a6e 2280{
1da36696
TT		 2281 u32 rqtn;
2282 int ix;
2283
398f3351 2284 if (priv->indir_rqt.enabled) {
a5f97fee 2285 /* RSS RQ table */
398f3351 2286 rqtn = priv->indir_rqt.rqtn;
a5f97fee 2287 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
398f3351
HHZ		 2288 }
2289
a5f97fee
SM		 2290 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2291 struct mlx5e_redirect_rqt_param direct_rrp = {
2292 .is_rss = false,
95632791
AM		 2293 {
2294 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2295 },
a5f97fee
SM		 2296 };
2297
2298 /* Direct RQ Tables */
398f3351
HHZ		 2299 if (!priv->direct_tir[ix].rqt.enabled)
2300 continue;
a5f97fee 2301
398f3351 2302 rqtn = priv->direct_tir[ix].rqt.rqtn;
a5f97fee 2303 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
1da36696 2304 }
40ab6a6e
AS		 2305}
2306
a5f97fee
SM		 2307static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2308 struct mlx5e_channels *chs)
2309{
2310 struct mlx5e_redirect_rqt_param rrp = {
2311 .is_rss = true,
95632791
AM		 2312 {
2313 .rss = {
2314 .channels = chs,
2315 .hfunc = chs->params.rss_hfunc,
2316 }
2317 },
a5f97fee
SM		 2318 };
2319
2320 mlx5e_redirect_rqts(priv, rrp);
2321}
2322
2323static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2324{
2325 struct mlx5e_redirect_rqt_param drop_rrp = {
2326 .is_rss = false,
95632791
AM		 2327 {
2328 .rqn = priv->drop_rq.rqn,
2329 },
a5f97fee
SM		 2330 };
2331
2332 mlx5e_redirect_rqts(priv, drop_rrp);
2333}
2334
6a9764ef 2335static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
5c50368f 2336{
6a9764ef 2337 if (!params->lro_en)
5c50368f
AS		 2338 return;
2339
2340#define ROUGH_MAX_L2_L3_HDR_SZ 256
2341
2342 MLX5_SET(tirc, tirc, lro_enable_mask,
2343 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2344 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2345 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
6a9764ef
SM		 2346 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2347 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
5c50368f
AS		 2348}
2349
6a9764ef
SM		 2350void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2351 enum mlx5e_traffic_types tt,
7b3722fa 2352 void *tirc, bool inner)
bdfc028d 2353{
7b3722fa
GP		 2354 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2355 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
a100ff3e
GP		 2356
2357#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2358 MLX5_HASH_FIELD_SEL_DST_IP)
2359
2360#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2361 MLX5_HASH_FIELD_SEL_DST_IP |\
2362 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2363 MLX5_HASH_FIELD_SEL_L4_DPORT)
2364
2365#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2366 MLX5_HASH_FIELD_SEL_DST_IP |\
2367 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2368
6a9764ef
SM		 2369 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2370 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
bdfc028d
TT		 2371 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2372 rx_hash_toeplitz_key);
2373 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2374 rx_hash_toeplitz_key);
2375
2376 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
6a9764ef 2377 memcpy(rss_key, params->toeplitz_hash_key, len);
bdfc028d 2378 }
a100ff3e
GP		 2379
2380 switch (tt) {
2381 case MLX5E_TT_IPV4_TCP:
2382 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2383 MLX5_L3_PROT_TYPE_IPV4);
2384 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2385 MLX5_L4_PROT_TYPE_TCP);
2386 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2387 MLX5_HASH_IP_L4PORTS);
2388 break;
2389
2390 case MLX5E_TT_IPV6_TCP:
2391 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2392 MLX5_L3_PROT_TYPE_IPV6);
2393 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2394 MLX5_L4_PROT_TYPE_TCP);
2395 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2396 MLX5_HASH_IP_L4PORTS);
2397 break;
2398
2399 case MLX5E_TT_IPV4_UDP:
2400 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2401 MLX5_L3_PROT_TYPE_IPV4);
2402 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2403 MLX5_L4_PROT_TYPE_UDP);
2404 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405 MLX5_HASH_IP_L4PORTS);
2406 break;
2407
2408 case MLX5E_TT_IPV6_UDP:
2409 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2410 MLX5_L3_PROT_TYPE_IPV6);
2411 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2412 MLX5_L4_PROT_TYPE_UDP);
2413 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2414 MLX5_HASH_IP_L4PORTS);
2415 break;
2416
2417 case MLX5E_TT_IPV4_IPSEC_AH:
2418 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2419 MLX5_L3_PROT_TYPE_IPV4);
2420 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2421 MLX5_HASH_IP_IPSEC_SPI);
2422 break;
2423
2424 case MLX5E_TT_IPV6_IPSEC_AH:
2425 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2426 MLX5_L3_PROT_TYPE_IPV6);
2427 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2428 MLX5_HASH_IP_IPSEC_SPI);
2429 break;
2430
2431 case MLX5E_TT_IPV4_IPSEC_ESP:
2432 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2433 MLX5_L3_PROT_TYPE_IPV4);
2434 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435 MLX5_HASH_IP_IPSEC_SPI);
2436 break;
2437
2438 case MLX5E_TT_IPV6_IPSEC_ESP:
2439 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2440 MLX5_L3_PROT_TYPE_IPV6);
2441 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2442 MLX5_HASH_IP_IPSEC_SPI);
2443 break;
2444
2445 case MLX5E_TT_IPV4:
2446 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2447 MLX5_L3_PROT_TYPE_IPV4);
2448 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2449 MLX5_HASH_IP);
2450 break;
2451
2452 case MLX5E_TT_IPV6:
2453 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2454 MLX5_L3_PROT_TYPE_IPV6);
2455 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2456 MLX5_HASH_IP);
2457 break;
2458 default:
2459 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2460 }
bdfc028d
TT		 2461}
2462
ab0394fe 2463static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2464{
2465 struct mlx5_core_dev *mdev = priv->mdev;
2466
2467 void *in;
2468 void *tirc;
2469 int inlen;
2470 int err;
ab0394fe 2471 int tt;
1da36696 2472 int ix;
5c50368f
AS		 2473
2474 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee 2475 in = kvzalloc(inlen, GFP_KERNEL);
5c50368f
AS		 2476 if (!in)
2477 return -ENOMEM;
2478
2479 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2480 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2481
6a9764ef 2482 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
5c50368f 2483
1da36696 2484 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2485 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2486 inlen);
ab0394fe 2487 if (err)
1da36696 2488 goto free_in;
ab0394fe 2489 }
5c50368f 2490
6bfd390b 2491 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2492 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2493 in, inlen);
2494 if (err)
2495 goto free_in;
2496 }
2497
2498free_in:
5c50368f
AS		 2499 kvfree(in);
2500
2501 return err;
2502}
2503
7b3722fa
GP		 2504static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2505 enum mlx5e_traffic_types tt,
2506 u32 *tirc)
2507{
2508 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2509
2510 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2511
2512 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2513 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2514 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2515
2516 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2517}
2518
cd255eff 2519static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2520{
40ab6a6e 2521 struct mlx5_core_dev *mdev = priv->mdev;
c139dbfd 2522 u16 hw_mtu = MLX5E_SW2HW_MTU(priv, mtu);
40ab6a6e
AS		 2523 int err;
2524
cd255eff 2525 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2526 if (err)
2527 return err;
2528
cd255eff
SM		 2529 /* Update vport context MTU */
2530 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2531 return 0;
2532}
40ab6a6e 2533
cd255eff
SM		 2534static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2535{
2536 struct mlx5_core_dev *mdev = priv->mdev;
2537 u16 hw_mtu = 0;
2538 int err;
40ab6a6e 2539
cd255eff
SM		 2540 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2541 if (err || !hw_mtu) /* fallback to port oper mtu */
2542 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2543
c139dbfd 2544 *mtu = MLX5E_HW2SW_MTU(priv, hw_mtu);
cd255eff
SM		 2545}
2546
2e20a151 2547static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
cd255eff 2548{
2e20a151 2549 struct net_device *netdev = priv->netdev;
cd255eff
SM		 2550 u16 mtu;
2551 int err;
2552
2553 err = mlx5e_set_mtu(priv, netdev->mtu);
2554 if (err)
2555 return err;
40ab6a6e 2556
cd255eff
SM		 2557 mlx5e_query_mtu(priv, &mtu);
2558 if (mtu != netdev->mtu)
2559 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2560 __func__, mtu, netdev->mtu);
40ab6a6e 2561
cd255eff 2562 netdev->mtu = mtu;
40ab6a6e
AS		 2563 return 0;
2564}
2565
08fb1dac
SM		 2566static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2567{
2568 struct mlx5e_priv *priv = netdev_priv(netdev);
6a9764ef
SM		 2569 int nch = priv->channels.params.num_channels;
2570 int ntc = priv->channels.params.num_tc;
08fb1dac
SM		 2571 int tc;
2572
2573 netdev_reset_tc(netdev);
2574
2575 if (ntc == 1)
2576 return;
2577
2578 netdev_set_num_tc(netdev, ntc);
2579
7ccdd084
RS		 2580 /* Map netdev TCs to offset 0
2581 * We have our own UP to TXQ mapping for QoS
2582 */
08fb1dac 2583 for (tc = 0; tc < ntc; tc++)
7ccdd084 2584 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2585}
2586
acc6c595
SM		 2587static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2588{
2589 struct mlx5e_channel *c;
2590 struct mlx5e_txqsq *sq;
2591 int i, tc;
2592
2593 for (i = 0; i < priv->channels.num; i++)
2594 for (tc = 0; tc < priv->profile->max_tc; tc++)
2595 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2596
2597 for (i = 0; i < priv->channels.num; i++) {
2598 c = priv->channels.c[i];
2599 for (tc = 0; tc < c->num_tc; tc++) {
2600 sq = &c->sq[tc];
2601 priv->txq2sq[sq->txq_ix] = sq;
2602 }
2603 }
2604}
2605
603f4a45 2606void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2607{
9008ae07
SM		 2608 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2609 struct net_device *netdev = priv->netdev;
2610
2611 mlx5e_netdev_set_tcs(netdev);
053ee0a7
TR		 2612 netif_set_real_num_tx_queues(netdev, num_txqs);
2613 netif_set_real_num_rx_queues(netdev, priv->channels.num);
9008ae07 2614
acc6c595
SM		 2615 mlx5e_build_channels_tx_maps(priv);
2616 mlx5e_activate_channels(&priv->channels);
2617 netif_tx_start_all_queues(priv->netdev);
9008ae07 2618
a9f7705f 2619 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2620 mlx5e_add_sqs_fwd_rules(priv);
2621
acc6c595 2622 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
9008ae07 2623 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
acc6c595
SM		 2624}
2625
603f4a45 2626void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
acc6c595 2627{
9008ae07
SM		 2628 mlx5e_redirect_rqts_to_drop(priv);
2629
a9f7705f 2630 if (MLX5_VPORT_MANAGER(priv->mdev))
9008ae07
SM		 2631 mlx5e_remove_sqs_fwd_rules(priv);
2632
acc6c595
SM		 2633 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2634 * polling for inactive tx queues.
2635 */
2636 netif_tx_stop_all_queues(priv->netdev);
2637 netif_tx_disable(priv->netdev);
2638 mlx5e_deactivate_channels(&priv->channels);
2639}
2640
55c2503d 2641void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2e20a151
SM		 2642 struct mlx5e_channels *new_chs,
2643 mlx5e_fp_hw_modify hw_modify)
55c2503d
SM		 2644{
2645 struct net_device *netdev = priv->netdev;
2646 int new_num_txqs;
7ca42c80 2647 int carrier_ok;
55c2503d
SM		 2648 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2649
7ca42c80 2650 carrier_ok = netif_carrier_ok(netdev);
55c2503d
SM		 2651 netif_carrier_off(netdev);
2652
2653 if (new_num_txqs < netdev->real_num_tx_queues)
2654 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2655
2656 mlx5e_deactivate_priv_channels(priv);
2657 mlx5e_close_channels(&priv->channels);
2658
2659 priv->channels = *new_chs;
2660
2e20a151
SM		 2661 /* New channels are ready to roll, modify HW settings if needed */
2662 if (hw_modify)
2663 hw_modify(priv);
2664
55c2503d
SM		 2665 mlx5e_refresh_tirs(priv, false);
2666 mlx5e_activate_priv_channels(priv);
2667
7ca42c80
ES		 2668 /* return carrier back if needed */
2669 if (carrier_ok)
2670 netif_carrier_on(netdev);
55c2503d
SM		 2671}
2672
7c39afb3
FD		 2673void mlx5e_timestamp_set(struct mlx5e_priv *priv)
2674{
2675 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2676 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2677}
2678
40ab6a6e
AS		 2679int mlx5e_open_locked(struct net_device *netdev)
2680{
2681 struct mlx5e_priv *priv = netdev_priv(netdev);
40ab6a6e
AS		 2682 int err;
2683
2684 set_bit(MLX5E_STATE_OPENED, &priv->state);
2685
ff9c852f 2686 err = mlx5e_open_channels(priv, &priv->channels);
acc6c595 2687 if (err)
343b29f3 2688 goto err_clear_state_opened_flag;
40ab6a6e 2689
b676f653 2690 mlx5e_refresh_tirs(priv, false);
acc6c595 2691 mlx5e_activate_priv_channels(priv);
7ca42c80
ES		 2692 if (priv->profile->update_carrier)
2693 priv->profile->update_carrier(priv);
7c39afb3 2694 mlx5e_timestamp_set(priv);
be4891af 2695
cb67b832
HHZ		 2696 if (priv->profile->update_stats)
2697 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2698
9b37b07f 2699 return 0;
343b29f3
AS		 2700
2701err_clear_state_opened_flag:
2702 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2703 return err;
40ab6a6e
AS		 2704}
2705
cb67b832 2706int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2707{
2708 struct mlx5e_priv *priv = netdev_priv(netdev);
2709 int err;
2710
2711 mutex_lock(&priv->state_lock);
2712 err = mlx5e_open_locked(netdev);
63bfd399
EBE		 2713 if (!err)
2714 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
40ab6a6e
AS		 2715 mutex_unlock(&priv->state_lock);
2716
2717 return err;
2718}
2719
2720int mlx5e_close_locked(struct net_device *netdev)
2721{
2722 struct mlx5e_priv *priv = netdev_priv(netdev);
2723
a1985740
AS		 2724 /* May already be CLOSED in case a previous configuration operation
2725 * (e.g RX/TX queue size change) that involves close&open failed.
2726 */
2727 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2728 return 0;
2729
40ab6a6e
AS		 2730 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2731
40ab6a6e 2732 netif_carrier_off(priv->netdev);
acc6c595
SM		 2733 mlx5e_deactivate_priv_channels(priv);
2734 mlx5e_close_channels(&priv->channels);
40ab6a6e
AS		 2735
2736 return 0;
2737}
2738
cb67b832 2739int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2740{
2741 struct mlx5e_priv *priv = netdev_priv(netdev);
2742 int err;
2743
26e59d80
MHY		 2744 if (!netif_device_present(netdev))
2745 return -ENODEV;
2746
40ab6a6e 2747 mutex_lock(&priv->state_lock);
63bfd399 2748 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
40ab6a6e
AS		 2749 err = mlx5e_close_locked(netdev);
2750 mutex_unlock(&priv->state_lock);
2751
2752 return err;
2753}
2754
a43b25da 2755static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2756 struct mlx5e_rq *rq,
2757 struct mlx5e_rq_param *param)
40ab6a6e 2758{
40ab6a6e
AS		 2759 void *rqc = param->rqc;
2760 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2761 int err;
2762
2763 param->wq.db_numa_node = param->wq.buf_numa_node;
2764
2765 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2766 &rq->wq_ctrl);
2767 if (err)
2768 return err;
2769
a43b25da 2770 rq->mdev = mdev;
40ab6a6e
AS		 2771
2772 return 0;
2773}
2774
a43b25da 2775static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
3b77235b
SM		 2776 struct mlx5e_cq *cq,
2777 struct mlx5e_cq_param *param)
40ab6a6e 2778{
95b6c6a5 2779 return mlx5e_alloc_cq_common(mdev, param, cq);
40ab6a6e
AS		 2780}
2781
a43b25da
SM		 2782static int mlx5e_open_drop_rq(struct mlx5_core_dev *mdev,
2783 struct mlx5e_rq *drop_rq)
40ab6a6e 2784{
a43b25da
SM		 2785 struct mlx5e_cq_param cq_param = {};
2786 struct mlx5e_rq_param rq_param = {};
2787 struct mlx5e_cq *cq = &drop_rq->cq;
40ab6a6e
AS		 2788 int err;
2789
556dd1b9 2790 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e 2791
a43b25da 2792 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
40ab6a6e
AS		 2793 if (err)
2794 return err;
2795
3b77235b 2796 err = mlx5e_create_cq(cq, &cq_param);
40ab6a6e 2797 if (err)
3b77235b 2798 goto err_free_cq;
40ab6a6e 2799
a43b25da 2800 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
40ab6a6e 2801 if (err)
3b77235b 2802 goto err_destroy_cq;
40ab6a6e 2803
a43b25da 2804 err = mlx5e_create_rq(drop_rq, &rq_param);
40ab6a6e 2805 if (err)
3b77235b 2806 goto err_free_rq;
40ab6a6e
AS		 2807
2808 return 0;
2809
3b77235b 2810err_free_rq:
a43b25da 2811 mlx5e_free_rq(drop_rq);
40ab6a6e
AS		 2812
2813err_destroy_cq:
a43b25da 2814 mlx5e_destroy_cq(cq);
40ab6a6e 2815
3b77235b 2816err_free_cq:
a43b25da 2817 mlx5e_free_cq(cq);
3b77235b 2818
40ab6a6e
AS		 2819 return err;
2820}
2821
a43b25da 2822static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
40ab6a6e 2823{
a43b25da
SM		 2824 mlx5e_destroy_rq(drop_rq);
2825 mlx5e_free_rq(drop_rq);
2826 mlx5e_destroy_cq(&drop_rq->cq);
2827 mlx5e_free_cq(&drop_rq->cq);
40ab6a6e
AS		 2828}
2829
5426a0b2
SM		 2830int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2831 u32 underlay_qpn, u32 *tisn)
40ab6a6e 2832{
c4f287c4 2833 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2834 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2835
08fb1dac 2836 MLX5_SET(tisc, tisc, prio, tc << 1);
5426a0b2 2837 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
b50d292b 2838 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2839
2840 if (mlx5_lag_is_lacp_owner(mdev))
2841 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2842
5426a0b2 2843 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
40ab6a6e
AS		 2844}
2845
5426a0b2 2846void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
40ab6a6e 2847{
5426a0b2 2848 mlx5_core_destroy_tis(mdev, tisn);
40ab6a6e
AS		 2849}
2850
cb67b832 2851int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2852{
2853 int err;
2854 int tc;
2855
6bfd390b 2856 for (tc = 0; tc < priv->profile->max_tc; tc++) {
5426a0b2 2857 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
40ab6a6e
AS		 2858 if (err)
2859 goto err_close_tises;
2860 }
2861
2862 return 0;
2863
2864err_close_tises:
2865 for (tc--; tc >= 0; tc--)
5426a0b2 2866 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2867
2868 return err;
2869}
2870
cb67b832 2871void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2872{
2873 int tc;
2874
6bfd390b 2875 for (tc = 0; tc < priv->profile->max_tc; tc++)
5426a0b2 2876 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
40ab6a6e
AS		 2877}
2878
6a9764ef
SM		 2879static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2880 enum mlx5e_traffic_types tt,
2881 u32 *tirc)
f62b8bb8 2882{
b50d292b 2883 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2884
6a9764ef 2885 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
f62b8bb8 2886
4cbeaff5 2887 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2888 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
7b3722fa 2889 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
f62b8bb8
AV		 2890}
2891
6a9764ef 2892static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
f62b8bb8 2893{
b50d292b 2894 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696 2895
6a9764ef 2896 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
1da36696
TT		 2897
2898 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2899 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2900 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2901}
2902
8f493ffd 2903int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2904{
724b2aa1 2905 struct mlx5e_tir *tir;
f62b8bb8
AV		 2906 void *tirc;
2907 int inlen;
7b3722fa 2908 int i = 0;
f62b8bb8 2909 int err;
1da36696 2910 u32 *in;
1da36696 2911 int tt;
f62b8bb8
AV		 2912
2913 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2914 in = kvzalloc(inlen, GFP_KERNEL);
f62b8bb8
AV		 2915 if (!in)
2916 return -ENOMEM;
2917
1da36696
TT		 2918 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2919 memset(in, 0, inlen);
724b2aa1 2920 tir = &priv->indir_tir[tt];
1da36696 2921 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2922 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
724b2aa1 2923 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
7b3722fa
GP		 2924 if (err) {
2925 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2926 goto err_destroy_inner_tirs;
2927 }
f62b8bb8
AV		 2928 }
2929
7b3722fa
GP		 2930 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2931 goto out;
2932
2933 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2934 memset(in, 0, inlen);
2935 tir = &priv->inner_indir_tir[i];
2936 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2937 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2938 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2939 if (err) {
2940 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2941 goto err_destroy_inner_tirs;
2942 }
2943 }
2944
2945out:
6bfd390b
HHZ		 2946 kvfree(in);
2947
2948 return 0;
2949
7b3722fa
GP		 2950err_destroy_inner_tirs:
2951 for (i--; i >= 0; i--)
2952 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2953
6bfd390b
HHZ		 2954 for (tt--; tt >= 0; tt--)
2955 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2956
2957 kvfree(in);
2958
2959 return err;
2960}
2961
cb67b832 2962int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2963{
2964 int nch = priv->profile->max_nch(priv->mdev);
2965 struct mlx5e_tir *tir;
2966 void *tirc;
2967 int inlen;
2968 int err;
2969 u32 *in;
2970 int ix;
2971
2972 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1b9a07ee 2973 in = kvzalloc(inlen, GFP_KERNEL);
6bfd390b
HHZ		 2974 if (!in)
2975 return -ENOMEM;
2976
1da36696
TT		 2977 for (ix = 0; ix < nch; ix++) {
2978 memset(in, 0, inlen);
724b2aa1 2979 tir = &priv->direct_tir[ix];
1da36696 2980 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
6a9764ef 2981 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
724b2aa1 2982 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2983 if (err)
2984 goto err_destroy_ch_tirs;
2985 }
2986
2987 kvfree(in);
2988
f62b8bb8
AV		 2989 return 0;
2990
1da36696 2991err_destroy_ch_tirs:
8f493ffd 2992 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
1da36696 2993 for (ix--; ix >= 0; ix--)
724b2aa1 2994 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2995
1da36696 2996 kvfree(in);
f62b8bb8
AV		 2997
2998 return err;
2999}
3000
8f493ffd 3001void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 3002{
3003 int i;
3004
1da36696 3005 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 3006 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
7b3722fa
GP		 3007
3008 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3009 return;
3010
3011 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3012 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
f62b8bb8
AV		 3013}
3014
cb67b832 3015void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 3016{
3017 int nch = priv->profile->max_nch(priv->mdev);
3018 int i;
3019
3020 for (i = 0; i < nch; i++)
3021 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3022}
3023
102722fc
GE		 3024static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3025{
3026 int err = 0;
3027 int i;
3028
3029 for (i = 0; i < chs->num; i++) {
3030 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3031 if (err)
3032 return err;
3033 }
3034
3035 return 0;
3036}
3037
f6d96a20 3038static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
36350114
GP		 3039{
3040 int err = 0;
3041 int i;
3042
ff9c852f
SM		 3043 for (i = 0; i < chs->num; i++) {
3044 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
36350114
GP		 3045 if (err)
3046 return err;
3047 }
3048
3049 return 0;
3050}
3051
0cf0f6d3
JP		 3052static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3053 struct tc_mqprio_qopt *mqprio)
08fb1dac
SM		 3054{
3055 struct mlx5e_priv *priv = netdev_priv(netdev);
6f9485af 3056 struct mlx5e_channels new_channels = {};
0cf0f6d3 3057 u8 tc = mqprio->num_tc;
08fb1dac
SM		 3058 int err = 0;
3059
0cf0f6d3
JP		 3060 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3061
08fb1dac
SM		 3062 if (tc && tc != MLX5E_MAX_NUM_TC)
3063 return -EINVAL;
3064
3065 mutex_lock(&priv->state_lock);
3066
6f9485af
SM		 3067 new_channels.params = priv->channels.params;
3068 new_channels.params.num_tc = tc ? tc : 1;
08fb1dac 3069
20b6a1c7 3070 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6f9485af
SM		 3071 priv->channels.params = new_channels.params;
3072 goto out;
3073 }
08fb1dac 3074
6f9485af
SM		 3075 err = mlx5e_open_channels(priv, &new_channels);
3076 if (err)
3077 goto out;
08fb1dac 3078
2e20a151 3079 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
6f9485af 3080out:
08fb1dac 3081 mutex_unlock(&priv->state_lock);
08fb1dac
SM		 3082 return err;
3083}
3084
e80541ec 3085#ifdef CONFIG_MLX5_ESWITCH
d6c862ba 3086static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
0cf0f6d3 3087 struct tc_cls_flower_offload *cls_flower)
08fb1dac 3088{
d6c862ba 3089 if (cls_flower->common.chain_index)
0cf0f6d3 3090 return -EOPNOTSUPP;
e8f887ac 3091
0cf0f6d3
JP		 3092 switch (cls_flower->command) {
3093 case TC_CLSFLOWER_REPLACE:
5fd9fc4e 3094 return mlx5e_configure_flower(priv, cls_flower);
0cf0f6d3
JP		 3095 case TC_CLSFLOWER_DESTROY:
3096 return mlx5e_delete_flower(priv, cls_flower);
3097 case TC_CLSFLOWER_STATS:
3098 return mlx5e_stats_flower(priv, cls_flower);
3099 default:
a5fcf8a6 3100 return -EOPNOTSUPP;
0cf0f6d3
JP		 3101 }
3102}
d6c862ba
JP		 3103
3104int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3105 void *cb_priv)
3106{
3107 struct mlx5e_priv *priv = cb_priv;
3108
44ae12a7
JP		 3109 if (!tc_can_offload(priv->netdev))
3110 return -EOPNOTSUPP;
3111
d6c862ba
JP		 3112 switch (type) {
3113 case TC_SETUP_CLSFLOWER:
3114 return mlx5e_setup_tc_cls_flower(priv, type_data);
3115 default:
3116 return -EOPNOTSUPP;
3117 }
3118}
3119
3120static int mlx5e_setup_tc_block(struct net_device *dev,
3121 struct tc_block_offload *f)
3122{
3123 struct mlx5e_priv *priv = netdev_priv(dev);
3124
3125 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3126 return -EOPNOTSUPP;
3127
3128 switch (f->command) {
3129 case TC_BLOCK_BIND:
3130 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3131 priv, priv);
3132 case TC_BLOCK_UNBIND:
3133 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3134 priv);
3135 return 0;
3136 default:
3137 return -EOPNOTSUPP;
3138 }
3139}
e80541ec 3140#endif
a5fcf8a6 3141
717503b9
JP		 3142int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3143 void *type_data)
0cf0f6d3 3144{
2572ac53 3145 switch (type) {
fde6af47 3146#ifdef CONFIG_MLX5_ESWITCH
d6c862ba
JP		 3147 case TC_SETUP_BLOCK:
3148 return mlx5e_setup_tc_block(dev, type_data);
fde6af47 3149#endif
575ed7d3 3150 case TC_SETUP_QDISC_MQPRIO:
de4784ca 3151 return mlx5e_setup_tc_mqprio(dev, type_data);
e8f887ac
AV		 3152 default:
3153 return -EOPNOTSUPP;
3154 }
08fb1dac
SM		 3155}
3156
bc1f4470 3157static void
f62b8bb8
AV		 3158mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3159{
3160 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 3161 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 3162 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 3163 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 3164
370bad0f
OG		 3165 if (mlx5e_is_uplink_rep(priv)) {
3166 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3167 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3168 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3169 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3170 } else {
3171 stats->rx_packets = sstats->rx_packets;
3172 stats->rx_bytes = sstats->rx_bytes;
3173 stats->tx_packets = sstats->tx_packets;
3174 stats->tx_bytes = sstats->tx_bytes;
3175 stats->tx_dropped = sstats->tx_queue_dropped;
3176 }
269e6b3a
GP		 3177
3178 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 3179
3180 stats->rx_length_errors =
9218b44d
GP		 3181 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3182 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3183 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 3184 stats->rx_crc_errors =
9218b44d
GP		 3185 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3186 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3187 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a
GP		 3188 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3189 stats->rx_frame_errors;
3190 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3191
3192 /* vport multicast also counts packets that are dropped due to steering
3193 * or rx out of buffer
3194 */
9218b44d
GP		 3195 stats->multicast =
3196 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 3197}
3198
3199static void mlx5e_set_rx_mode(struct net_device *dev)
3200{
3201 struct mlx5e_priv *priv = netdev_priv(dev);
3202
7bb29755 3203 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3204}
3205
3206static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3207{
3208 struct mlx5e_priv *priv = netdev_priv(netdev);
3209 struct sockaddr *saddr = addr;
3210
3211 if (!is_valid_ether_addr(saddr->sa_data))
3212 return -EADDRNOTAVAIL;
3213
3214 netif_addr_lock_bh(netdev);
3215 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3216 netif_addr_unlock_bh(netdev);
3217
7bb29755 3218 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 3219
3220 return 0;
3221}
3222
0e405443
GP		 3223#define MLX5E_SET_FEATURE(netdev, feature, enable) \
3224 do { \
3225 if (enable) \
3226 netdev->features |= feature; \
3227 else \
3228 netdev->features &= ~feature; \
3229 } while (0)
3230
3231typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3232
3233static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 3234{
3235 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3236 struct mlx5e_channels new_channels = {};
3237 int err = 0;
3238 bool reset;
f62b8bb8
AV		 3239
3240 mutex_lock(&priv->state_lock);
f62b8bb8 3241
2e20a151
SM		 3242 reset = (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST);
3243 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3244
2e20a151
SM		 3245 new_channels.params = priv->channels.params;
3246 new_channels.params.lro_en = enable;
3247
3248 if (!reset) {
3249 priv->channels.params = new_channels.params;
3250 err = mlx5e_modify_tirs_lro(priv);
3251 goto out;
98e81b0a 3252 }
f62b8bb8 3253
2e20a151
SM		 3254 err = mlx5e_open_channels(priv, &new_channels);
3255 if (err)
3256 goto out;
0e405443 3257
2e20a151
SM		 3258 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3259out:
9b37b07f 3260 mutex_unlock(&priv->state_lock);
0e405443
GP		 3261 return err;
3262}
3263
2b52a283 3264static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
0e405443
GP		 3265{
3266 struct mlx5e_priv *priv = netdev_priv(netdev);
3267
3268 if (enable)
2b52a283 3269 mlx5e_enable_cvlan_filter(priv);
0e405443 3270 else
2b52a283 3271 mlx5e_disable_cvlan_filter(priv);
0e405443
GP		 3272
3273 return 0;
3274}
3275
3276static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3277{
3278 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 3279
0e405443 3280 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 3281 netdev_err(netdev,
3282 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3283 return -EINVAL;
3284 }
3285
0e405443
GP		 3286 return 0;
3287}
3288
94cb1ebb
EBE		 3289static int set_feature_rx_all(struct net_device *netdev, bool enable)
3290{
3291 struct mlx5e_priv *priv = netdev_priv(netdev);
3292 struct mlx5_core_dev *mdev = priv->mdev;
3293
3294 return mlx5_set_port_fcs(mdev, !enable);
3295}
3296
102722fc
GE		 3297static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3298{
3299 struct mlx5e_priv *priv = netdev_priv(netdev);
3300 int err;
3301
3302 mutex_lock(&priv->state_lock);
3303
3304 priv->channels.params.scatter_fcs_en = enable;
3305 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3306 if (err)
3307 priv->channels.params.scatter_fcs_en = !enable;
3308
3309 mutex_unlock(&priv->state_lock);
3310
3311 return err;
3312}
3313
36350114
GP		 3314static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3315{
3316 struct mlx5e_priv *priv = netdev_priv(netdev);
ff9c852f 3317 int err = 0;
36350114
GP		 3318
3319 mutex_lock(&priv->state_lock);
3320
6a9764ef 3321 priv->channels.params.vlan_strip_disable = !enable;
ff9c852f
SM		 3322 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3323 goto unlock;
3324
3325 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
36350114 3326 if (err)
6a9764ef 3327 priv->channels.params.vlan_strip_disable = enable;
36350114 3328
ff9c852f 3329unlock:
36350114
GP		 3330 mutex_unlock(&priv->state_lock);
3331
3332 return err;
3333}
3334
45bf454a
MG		 3335#ifdef CONFIG_RFS_ACCEL
3336static int set_feature_arfs(struct net_device *netdev, bool enable)
3337{
3338 struct mlx5e_priv *priv = netdev_priv(netdev);
3339 int err;
3340
3341 if (enable)
3342 err = mlx5e_arfs_enable(priv);
3343 else
3344 err = mlx5e_arfs_disable(priv);
3345
3346 return err;
3347}
3348#endif
3349
0e405443
GP		 3350static int mlx5e_handle_feature(struct net_device *netdev,
3351 netdev_features_t wanted_features,
3352 netdev_features_t feature,
3353 mlx5e_feature_handler feature_handler)
3354{
3355 netdev_features_t changes = wanted_features ^ netdev->features;
3356 bool enable = !!(wanted_features & feature);
3357 int err;
3358
3359 if (!(changes & feature))
3360 return 0;
3361
3362 err = feature_handler(netdev, enable);
3363 if (err) {
b20eab15
GP		 3364 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3365 enable ? "Enable" : "Disable", &feature, err);
0e405443
GP		 3366 return err;
3367 }
3368
3369 MLX5E_SET_FEATURE(netdev, feature, enable);
3370 return 0;
3371}
3372
3373static int mlx5e_set_features(struct net_device *netdev,
3374 netdev_features_t features)
3375{
3376 int err;
3377
3378 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
3379 set_feature_lro);
3380 err |= mlx5e_handle_feature(netdev, features,
3381 NETIF_F_HW_VLAN_CTAG_FILTER,
2b52a283 3382 set_feature_cvlan_filter);
0e405443
GP		 3383 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
3384 set_feature_tc_num_filters);
94cb1ebb
EBE		 3385 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
3386 set_feature_rx_all);
102722fc
GE		 3387 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXFCS,
3388 set_feature_rx_fcs);
36350114
GP		 3389 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
3390 set_feature_rx_vlan);
45bf454a
MG		 3391#ifdef CONFIG_RFS_ACCEL
3392 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
3393 set_feature_arfs);
3394#endif
0e405443
GP		 3395
3396 return err ? -EINVAL : 0;
f62b8bb8
AV		 3397}
3398
7d92d580
GP		 3399static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3400 netdev_features_t features)
3401{
3402 struct mlx5e_priv *priv = netdev_priv(netdev);
3403
3404 mutex_lock(&priv->state_lock);
3405 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3406 /* HW strips the outer C-tag header, this is a problem
3407 * for S-tag traffic.
3408 */
3409 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3410 if (!priv->channels.params.vlan_strip_disable)
3411 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3412 }
3413 mutex_unlock(&priv->state_lock);
3414
3415 return features;
3416}
3417
f62b8bb8
AV		 3418static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3419{
3420 struct mlx5e_priv *priv = netdev_priv(netdev);
2e20a151
SM		 3421 struct mlx5e_channels new_channels = {};
3422 int curr_mtu;
98e81b0a 3423 int err = 0;
506753b0 3424 bool reset;
f62b8bb8 3425
f62b8bb8 3426 mutex_lock(&priv->state_lock);
98e81b0a 3427
6a9764ef
SM		 3428 reset = !priv->channels.params.lro_en &&
3429 (priv->channels.params.rq_wq_type !=
506753b0
TT		 3430 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
3431
2e20a151 3432 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
98e81b0a 3433
2e20a151 3434 curr_mtu = netdev->mtu;
f62b8bb8 3435 netdev->mtu = new_mtu;
98e81b0a 3436
2e20a151
SM		 3437 if (!reset) {
3438 mlx5e_set_dev_port_mtu(priv);
3439 goto out;
3440 }
98e81b0a 3441
2e20a151
SM		 3442 new_channels.params = priv->channels.params;
3443 err = mlx5e_open_channels(priv, &new_channels);
3444 if (err) {
3445 netdev->mtu = curr_mtu;
3446 goto out;
3447 }
3448
3449 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
f62b8bb8 3450
2e20a151
SM		 3451out:
3452 mutex_unlock(&priv->state_lock);
f62b8bb8
AV		 3453 return err;
3454}
3455
7c39afb3
FD		 3456int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3457{
3458 struct hwtstamp_config config;
3459 int err;
3460
3461 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3462 return -EOPNOTSUPP;
3463
3464 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3465 return -EFAULT;
3466
3467 /* TX HW timestamp */
3468 switch (config.tx_type) {
3469 case HWTSTAMP_TX_OFF:
3470 case HWTSTAMP_TX_ON:
3471 break;
3472 default:
3473 return -ERANGE;
3474 }
3475
3476 mutex_lock(&priv->state_lock);
3477 /* RX HW timestamp */
3478 switch (config.rx_filter) {
3479 case HWTSTAMP_FILTER_NONE:
3480 /* Reset CQE compression to Admin default */
3481 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3482 break;
3483 case HWTSTAMP_FILTER_ALL:
3484 case HWTSTAMP_FILTER_SOME:
3485 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3486 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3487 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3488 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3489 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3490 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3491 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3492 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3493 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3494 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3495 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3496 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3497 case HWTSTAMP_FILTER_NTP_ALL:
3498 /* Disable CQE compression */
3499 netdev_warn(priv->netdev, "Disabling cqe compression");
3500 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3501 if (err) {
3502 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3503 mutex_unlock(&priv->state_lock);
3504 return err;
3505 }
3506 config.rx_filter = HWTSTAMP_FILTER_ALL;
3507 break;
3508 default:
3509 mutex_unlock(&priv->state_lock);
3510 return -ERANGE;
3511 }
3512
3513 memcpy(&priv->tstamp, &config, sizeof(config));
3514 mutex_unlock(&priv->state_lock);
3515
3516 return copy_to_user(ifr->ifr_data, &config,
3517 sizeof(config)) ? -EFAULT : 0;
3518}
3519
3520int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3521{
3522 struct hwtstamp_config *cfg = &priv->tstamp;
3523
3524 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3525 return -EOPNOTSUPP;
3526
3527 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3528}
3529
ef9814de
EBE		 3530static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3531{
1170fbd8
FD		 3532 struct mlx5e_priv *priv = netdev_priv(dev);
3533
ef9814de
EBE		 3534 switch (cmd) {
3535 case SIOCSHWTSTAMP:
1170fbd8 3536 return mlx5e_hwstamp_set(priv, ifr);
ef9814de 3537 case SIOCGHWTSTAMP:
1170fbd8 3538 return mlx5e_hwstamp_get(priv, ifr);
ef9814de
EBE		 3539 default:
3540 return -EOPNOTSUPP;
3541 }
3542}
3543
e80541ec 3544#ifdef CONFIG_MLX5_ESWITCH
66e49ded
SM		 3545static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3546{
3547 struct mlx5e_priv *priv = netdev_priv(dev);
3548 struct mlx5_core_dev *mdev = priv->mdev;
3549
3550 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3551}
3552
79aab093
MS		 3553static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3554 __be16 vlan_proto)
66e49ded
SM		 3555{
3556 struct mlx5e_priv *priv = netdev_priv(dev);
3557 struct mlx5_core_dev *mdev = priv->mdev;
3558
79aab093
MS		 3559 if (vlan_proto != htons(ETH_P_8021Q))
3560 return -EPROTONOSUPPORT;
3561
66e49ded
SM		 3562 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3563 vlan, qos);
3564}
3565
f942380c
MHY		 3566static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3567{
3568 struct mlx5e_priv *priv = netdev_priv(dev);
3569 struct mlx5_core_dev *mdev = priv->mdev;
3570
3571 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3572}
3573
1edc57e2
MHY		 3574static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3575{
3576 struct mlx5e_priv *priv = netdev_priv(dev);
3577 struct mlx5_core_dev *mdev = priv->mdev;
3578
3579 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3580}
bd77bf1c
MHY		 3581
3582static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3583 int max_tx_rate)
3584{
3585 struct mlx5e_priv *priv = netdev_priv(dev);
3586 struct mlx5_core_dev *mdev = priv->mdev;
3587
bd77bf1c 3588 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
c9497c98 3589 max_tx_rate, min_tx_rate);
bd77bf1c
MHY		 3590}
3591
66e49ded
SM		 3592static int mlx5_vport_link2ifla(u8 esw_link)
3593{
3594 switch (esw_link) {
3595 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3596 return IFLA_VF_LINK_STATE_DISABLE;
3597 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3598 return IFLA_VF_LINK_STATE_ENABLE;
3599 }
3600 return IFLA_VF_LINK_STATE_AUTO;
3601}
3602
3603static int mlx5_ifla_link2vport(u8 ifla_link)
3604{
3605 switch (ifla_link) {
3606 case IFLA_VF_LINK_STATE_DISABLE:
3607 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3608 case IFLA_VF_LINK_STATE_ENABLE:
3609 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3610 }
3611 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3612}
3613
3614static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3615 int link_state)
3616{
3617 struct mlx5e_priv *priv = netdev_priv(dev);
3618 struct mlx5_core_dev *mdev = priv->mdev;
3619
3620 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3621 mlx5_ifla_link2vport(link_state));
3622}
3623
3624static int mlx5e_get_vf_config(struct net_device *dev,
3625 int vf, struct ifla_vf_info *ivi)
3626{
3627 struct mlx5e_priv *priv = netdev_priv(dev);
3628 struct mlx5_core_dev *mdev = priv->mdev;
3629 int err;
3630
3631 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3632 if (err)
3633 return err;
3634 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3635 return 0;
3636}
3637
3638static int mlx5e_get_vf_stats(struct net_device *dev,
3639 int vf, struct ifla_vf_stats *vf_stats)
3640{
3641 struct mlx5e_priv *priv = netdev_priv(dev);
3642 struct mlx5_core_dev *mdev = priv->mdev;
3643
3644 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3645 vf_stats);
3646}
e80541ec 3647#endif
66e49ded 3648
1ad9a00a
PB		 3649static void mlx5e_add_vxlan_port(struct net_device *netdev,
3650 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3651{
3652 struct mlx5e_priv *priv = netdev_priv(netdev);
3653
974c3f30
AD		 3654 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3655 return;
3656
b3f63c3d
MF		 3657 if (!mlx5e_vxlan_allowed(priv->mdev))
3658 return;
3659
974c3f30 3660 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3661}
3662
1ad9a00a
PB		 3663static void mlx5e_del_vxlan_port(struct net_device *netdev,
3664 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3665{
3666 struct mlx5e_priv *priv = netdev_priv(netdev);
3667
974c3f30
AD		 3668 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3669 return;
3670
b3f63c3d
MF		 3671 if (!mlx5e_vxlan_allowed(priv->mdev))
3672 return;
3673
974c3f30 3674 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3675}
3676
27299841
GP		 3677static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3678 struct sk_buff *skb,
3679 netdev_features_t features)
b3f63c3d
MF		 3680{
3681 struct udphdr *udph;
27299841
GP		 3682 u8 proto;
3683 u16 port;
b3f63c3d
MF		 3684
3685 switch (vlan_get_protocol(skb)) {
3686 case htons(ETH_P_IP):
3687 proto = ip_hdr(skb)->protocol;
3688 break;
3689 case htons(ETH_P_IPV6):
3690 proto = ipv6_hdr(skb)->nexthdr;
3691 break;
3692 default:
3693 goto out;
3694 }
3695
27299841
GP		 3696 switch (proto) {
3697 case IPPROTO_GRE:
3698 return features;
3699 case IPPROTO_UDP:
b3f63c3d
MF		 3700 udph = udp_hdr(skb);
3701 port = be16_to_cpu(udph->dest);
b3f63c3d 3702
27299841
GP		 3703 /* Verify if UDP port is being offloaded by HW */
3704 if (mlx5e_vxlan_lookup_port(priv, port))
3705 return features;
3706 }
b3f63c3d
MF		 3707
3708out:
3709 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3710 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3711}
3712
3713static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3714 struct net_device *netdev,
3715 netdev_features_t features)
3716{
3717 struct mlx5e_priv *priv = netdev_priv(netdev);
3718
3719 features = vlan_features_check(skb, features);
3720 features = vxlan_features_check(skb, features);
3721
2ac9cfe7
IT		 3722#ifdef CONFIG_MLX5_EN_IPSEC
3723 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3724 return features;
3725#endif
3726
b3f63c3d
MF		 3727 /* Validate if the tunneled packet is being offloaded by HW */
3728 if (skb->encapsulation &&
3729 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
27299841 3730 return mlx5e_tunnel_features_check(priv, skb, features);
b3f63c3d
MF		 3731
3732 return features;
3733}
3734
3947ca18
DJ		 3735static void mlx5e_tx_timeout(struct net_device *dev)
3736{
3737 struct mlx5e_priv *priv = netdev_priv(dev);
3738 bool sched_work = false;
3739 int i;
3740
3741 netdev_err(dev, "TX timeout detected\n");
3742
6a9764ef 3743 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
acc6c595 3744 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3947ca18 3745
2c1ccc99 3746 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3747 continue;
3748 sched_work = true;
c0f1147d 3749 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3947ca18
DJ		 3750 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3751 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3752 }
3753
3754 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3755 schedule_work(&priv->tx_timeout_work);
3756}
3757
86994156
RS		 3758static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3759{
3760 struct mlx5e_priv *priv = netdev_priv(netdev);
3761 struct bpf_prog *old_prog;
3762 int err = 0;
3763 bool reset, was_opened;
3764 int i;
3765
3766 mutex_lock(&priv->state_lock);
3767
3768 if ((netdev->features & NETIF_F_LRO) && prog) {
3769 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3770 err = -EINVAL;
3771 goto unlock;
3772 }
3773
547eede0
IT		 3774 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3775 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3776 err = -EINVAL;
3777 goto unlock;
3778 }
3779
86994156
RS		 3780 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3781 /* no need for full reset when exchanging programs */
6a9764ef 3782 reset = (!priv->channels.params.xdp_prog || !prog);
86994156
RS		 3783
3784 if (was_opened && reset)
3785 mlx5e_close_locked(netdev);
c54c0629
DB		 3786 if (was_opened && !reset) {
3787 /* num_channels is invariant here, so we can take the
3788 * batched reference right upfront.
3789 */
6a9764ef 3790 prog = bpf_prog_add(prog, priv->channels.num);
c54c0629
DB		 3791 if (IS_ERR(prog)) {
3792 err = PTR_ERR(prog);
3793 goto unlock;
3794 }
3795 }
86994156 3796
c54c0629
DB		 3797 /* exchange programs, extra prog reference we got from caller
3798 * as long as we don't fail from this point onwards.
3799 */
6a9764ef 3800 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
86994156
RS		 3801 if (old_prog)
3802 bpf_prog_put(old_prog);
3803
3804 if (reset) /* change RQ type according to priv->xdp_prog */
6a9764ef 3805 mlx5e_set_rq_params(priv->mdev, &priv->channels.params);
86994156
RS		 3806
3807 if (was_opened && reset)
3808 mlx5e_open_locked(netdev);
3809
3810 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3811 goto unlock;
3812
3813 /* exchanging programs w/o reset, we update ref counts on behalf
3814 * of the channels RQs here.
3815 */
ff9c852f
SM		 3816 for (i = 0; i < priv->channels.num; i++) {
3817 struct mlx5e_channel *c = priv->channels.c[i];
86994156 3818
c0f1147d 3819 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156
RS		 3820 napi_synchronize(&c->napi);
3821 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3822
3823 old_prog = xchg(&c->rq.xdp_prog, prog);
3824
c0f1147d 3825 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
86994156 3826 /* napi_schedule in case we have missed anything */
86994156
RS		 3827 napi_schedule(&c->napi);
3828
3829 if (old_prog)
3830 bpf_prog_put(old_prog);
3831 }
3832
3833unlock:
3834 mutex_unlock(&priv->state_lock);
3835 return err;
3836}
3837
821b2e29 3838static u32 mlx5e_xdp_query(struct net_device *dev)
86994156
RS		 3839{
3840 struct mlx5e_priv *priv = netdev_priv(dev);
821b2e29
MKL		 3841 const struct bpf_prog *xdp_prog;
3842 u32 prog_id = 0;
86994156 3843
821b2e29
MKL		 3844 mutex_lock(&priv->state_lock);
3845 xdp_prog = priv->channels.params.xdp_prog;
3846 if (xdp_prog)
3847 prog_id = xdp_prog->aux->id;
3848 mutex_unlock(&priv->state_lock);
3849
3850 return prog_id;
86994156
RS		 3851}
3852
f4e63525 3853static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
86994156
RS		 3854{
3855 switch (xdp->command) {
3856 case XDP_SETUP_PROG:
3857 return mlx5e_xdp_set(dev, xdp->prog);
3858 case XDP_QUERY_PROG:
821b2e29
MKL		 3859 xdp->prog_id = mlx5e_xdp_query(dev);
3860 xdp->prog_attached = !!xdp->prog_id;
86994156
RS		 3861 return 0;
3862 default:
3863 return -EINVAL;
3864 }
3865}
3866
80378384
CO		 3867#ifdef CONFIG_NET_POLL_CONTROLLER
3868/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3869 * reenabling interrupts.
3870 */
3871static void mlx5e_netpoll(struct net_device *dev)
3872{
3873 struct mlx5e_priv *priv = netdev_priv(dev);
ff9c852f
SM		 3874 struct mlx5e_channels *chs = &priv->channels;
3875
80378384
CO		 3876 int i;
3877
ff9c852f
SM		 3878 for (i = 0; i < chs->num; i++)
3879 napi_schedule(&chs->c[i]->napi);
80378384
CO		 3880}
3881#endif
3882
e80541ec 3883static const struct net_device_ops mlx5e_netdev_ops = {
f62b8bb8
AV		 3884 .ndo_open = mlx5e_open,
3885 .ndo_stop = mlx5e_close,
3886 .ndo_start_xmit = mlx5e_xmit,
0cf0f6d3 3887 .ndo_setup_tc = mlx5e_setup_tc,
08fb1dac 3888 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3889 .ndo_get_stats64 = mlx5e_get_stats,
3890 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3891 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3892 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3893 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3894 .ndo_set_features = mlx5e_set_features,
7d92d580 3895 .ndo_fix_features = mlx5e_fix_features,
b0eed40e
SM		 3896 .ndo_change_mtu = mlx5e_change_mtu,
3897 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3898 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
706b3583
SM		 3899 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3900 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3901 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3902#ifdef CONFIG_RFS_ACCEL
3903 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3904#endif
3947ca18 3905 .ndo_tx_timeout = mlx5e_tx_timeout,
f4e63525 3906 .ndo_bpf = mlx5e_xdp,
80378384
CO		 3907#ifdef CONFIG_NET_POLL_CONTROLLER
3908 .ndo_poll_controller = mlx5e_netpoll,
3909#endif
e80541ec 3910#ifdef CONFIG_MLX5_ESWITCH
706b3583 3911 /* SRIOV E-Switch NDOs */
b0eed40e
SM		 3912 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3913 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3914 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3915 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3916 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3917 .ndo_get_vf_config = mlx5e_get_vf_config,
3918 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3919 .ndo_get_vf_stats = mlx5e_get_vf_stats,
370bad0f
OG		 3920 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3921 .ndo_get_offload_stats = mlx5e_get_offload_stats,
e80541ec 3922#endif
f62b8bb8
AV		 3923};
3924
3925static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3926{
3927 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
9eb78923 3928 return -EOPNOTSUPP;
f62b8bb8
AV		 3929 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3930 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3931 !MLX5_CAP_ETH(mdev, csum_cap) ||
3932 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3933 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3934 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3935 MLX5_CAP_FLOWTABLE(mdev,
3936 flow_table_properties_nic_receive.max_ft_level)
3937 < 3) {
f62b8bb8
AV		 3938 mlx5_core_warn(mdev,
3939 "Not creating net device, some required device capabilities are missing\n");
9eb78923 3940 return -EOPNOTSUPP;
f62b8bb8 3941 }
66189961
TT		 3942 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3943 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8 3944 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3e432ab6 3945 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
66189961 3946
f62b8bb8
AV		 3947 return 0;
3948}
3949
58d52291
AS		 3950u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3951{
3952 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3953
3954 return bf_buf_size -
3955 sizeof(struct mlx5e_tx_wqe) +
3956 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3957}
3958
d4b6c488 3959void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
85082dba
TT		 3960 int num_channels)
3961{
3962 int i;
3963
3964 for (i = 0; i < len; i++)
3965 indirection_rqt[i] = i % num_channels;
3966}
3967
b797a684
SM		 3968static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3969{
3970 enum pcie_link_width width;
3971 enum pci_bus_speed speed;
3972 int err = 0;
3973
3974 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3975 if (err)
3976 return err;
3977
3978 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3979 return -EINVAL;
3980
3981 switch (speed) {
3982 case PCIE_SPEED_2_5GT:
3983 *pci_bw = 2500 * width;
3984 break;
3985 case PCIE_SPEED_5_0GT:
3986 *pci_bw = 5000 * width;
3987 break;
3988 case PCIE_SPEED_8_0GT:
3989 *pci_bw = 8000 * width;
3990 break;
3991 default:
3992 return -EINVAL;
3993 }
3994
3995 return 0;
3996}
3997
3998static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3999{
4000 return (link_speed && pci_bw &&
4001 (pci_bw < 40000) && (pci_bw < link_speed));
4002}
4003
0f6e4cf6
EBE		 4004static bool hw_lro_heuristic(u32 link_speed, u32 pci_bw)
4005{
4006 return !(link_speed && pci_bw &&
4007 (pci_bw <= 16000) && (pci_bw < link_speed));
4008}
4009
0088cbbc
TG		 4010void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4011{
4012 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4013
4014 params->tx_cq_moderation.pkts =
4015 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4016 params->tx_cq_moderation.usec =
4017 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4018
4019 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4020 params->tx_cq_moderation.usec =
4021 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4022
4023 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4024 params->tx_cq_moderation.cq_period_mode ==
4025 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4026}
4027
9908aa29
TT		 4028void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4029{
0088cbbc 4030 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
9908aa29
TT		 4031
4032 params->rx_cq_moderation.pkts =
4033 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4034 params->rx_cq_moderation.usec =
0088cbbc 4035 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
9908aa29
TT		 4036
4037 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4038 params->rx_cq_moderation.usec =
4039 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
6a9764ef 4040
457fcd8a
SM		 4041 if (params->rx_am_enabled)
4042 params->rx_cq_moderation =
0088cbbc 4043 mlx5e_am_get_def_profile(cq_period_mode);
457fcd8a 4044
6a9764ef 4045 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
0088cbbc
TG		 4046 params->rx_cq_moderation.cq_period_mode ==
4047 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9908aa29
TT		 4048}
4049
2b029556
SM		 4050u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4051{
4052 int i;
4053
4054 /* The supported periods are organized in ascending order */
4055 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4056 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4057 break;
4058
4059 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4060}
4061
8f493ffd
SM		 4062void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4063 struct mlx5e_params *params,
4064 u16 max_channels)
f62b8bb8 4065{
6a9764ef 4066 u8 cq_period_mode = 0;
b797a684
SM		 4067 u32 link_speed = 0;
4068 u32 pci_bw = 0;
2fc4bfb7 4069
6a9764ef
SM		 4070 params->num_channels = max_channels;
4071 params->num_tc = 1;
2b029556 4072
0f6e4cf6
EBE		 4073 mlx5e_get_max_linkspeed(mdev, &link_speed);
4074 mlx5e_get_pci_bw(mdev, &pci_bw);
4075 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
4076 link_speed, pci_bw);
4077
6a9764ef
SM		 4078 /* SQ */
4079 params->log_sq_size = is_kdump_kernel() ?
b4e029da
KH		 4080 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4081 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 4082
b797a684 4083 /* set CQE compression */
6a9764ef 4084 params->rx_cqe_compress_def = false;
b797a684 4085 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
e53eef63 4086 MLX5_CAP_GEN(mdev, vport_group_manager))
6a9764ef 4087 params->rx_cqe_compress_def = cqe_compress_heuristic(link_speed, pci_bw);
0f6e4cf6 4088
6a9764ef
SM		 4089 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4090
4091 /* RQ */
4092 mlx5e_set_rq_params(mdev, params);
b797a684 4093
6a9764ef 4094 /* HW LRO */
c139dbfd 4095
5426a0b2 4096 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
6a9764ef 4097 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
0f6e4cf6 4098 params->lro_en = hw_lro_heuristic(link_speed, pci_bw);
6a9764ef 4099 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
b0d4660b 4100
6a9764ef
SM		 4101 /* CQ moderation params */
4102 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4103 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4104 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4105 params->rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4106 mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
0088cbbc 4107 mlx5e_set_tx_cq_mode_params(params, cq_period_mode);
9908aa29 4108
6a9764ef
SM		 4109 /* TX inline */
4110 params->tx_max_inline = mlx5e_get_max_inline_cap(mdev);
fbcb127e 4111 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
a6f402e4 4112
6a9764ef
SM		 4113 /* RSS */
4114 params->rss_hfunc = ETH_RSS_HASH_XOR;
4115 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
d4b6c488 4116 mlx5e_build_default_indir_rqt(params->indirection_rqt,
6a9764ef
SM		 4117 MLX5E_INDIR_RQT_SIZE, max_channels);
4118}
f62b8bb8 4119
6a9764ef
SM		 4120static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4121 struct net_device *netdev,
4122 const struct mlx5e_profile *profile,
4123 void *ppriv)
4124{
4125 struct mlx5e_priv *priv = netdev_priv(netdev);
57afead5 4126
6a9764ef
SM		 4127 priv->mdev = mdev;
4128 priv->netdev = netdev;
4129 priv->profile = profile;
4130 priv->ppriv = ppriv;
79c48764 4131 priv->msglevel = MLX5E_MSG_LEVEL;
c139dbfd 4132 priv->hard_mtu = MLX5E_ETH_HARD_MTU;
2d75b2bc 4133
6a9764ef 4134 mlx5e_build_nic_params(mdev, &priv->channels.params, profile->max_nch(mdev));
9908aa29 4135
f62b8bb8
AV		 4136 mutex_init(&priv->state_lock);
4137
4138 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4139 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 4140 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 4141 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4142}
4143
4144static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4145{
4146 struct mlx5e_priv *priv = netdev_priv(netdev);
4147
e1d7d349 4148 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 4149 if (is_zero_ether_addr(netdev->dev_addr) &&
4150 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4151 eth_hw_addr_random(netdev);
4152 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4153 }
f62b8bb8
AV		 4154}
4155
e80541ec 4156#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
cb67b832
HHZ		 4157static const struct switchdev_ops mlx5e_switchdev_ops = {
4158 .switchdev_port_attr_get = mlx5e_attr_get,
4159};
e80541ec 4160#endif
cb67b832 4161
6bfd390b 4162static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 4163{
4164 struct mlx5e_priv *priv = netdev_priv(netdev);
4165 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 4166 bool fcs_supported;
4167 bool fcs_enabled;
f62b8bb8
AV		 4168
4169 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4170
e80541ec
SM		 4171 netdev->netdev_ops = &mlx5e_netdev_ops;
4172
08fb1dac 4173#ifdef CONFIG_MLX5_CORE_EN_DCB
e80541ec
SM		 4174 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4175 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac 4176#endif
66e49ded 4177
f62b8bb8
AV		 4178 netdev->watchdog_timeo = 15 * HZ;
4179
4180 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4181
12be4b21 4182 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 4183 netdev->vlan_features |= NETIF_F_IP_CSUM;
4184 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4185 netdev->vlan_features |= NETIF_F_GRO;
4186 netdev->vlan_features |= NETIF_F_TSO;
4187 netdev->vlan_features |= NETIF_F_TSO6;
4188 netdev->vlan_features |= NETIF_F_RXCSUM;
4189 netdev->vlan_features |= NETIF_F_RXHASH;
4190
4191 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4192 netdev->vlan_features |= NETIF_F_LRO;
4193
4194 netdev->hw_features = netdev->vlan_features;
e4cf27bd 4195 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 4196 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4197 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4382c7b9 4198 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
f62b8bb8 4199
27299841
GP		 4200 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4201 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
b3f63c3d 4202 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 4203 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 4204 netdev->hw_enc_features |= NETIF_F_TSO;
4205 netdev->hw_enc_features |= NETIF_F_TSO6;
27299841
GP		 4206 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4207 }
4208
4209 if (mlx5e_vxlan_allowed(mdev)) {
4210 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4211 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4212 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4213 NETIF_F_GSO_UDP_TUNNEL_CSUM;
b49663c8 4214 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 4215 }
4216
27299841
GP		 4217 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4218 netdev->hw_features |= NETIF_F_GSO_GRE |
4219 NETIF_F_GSO_GRE_CSUM;
4220 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4221 NETIF_F_GSO_GRE_CSUM;
4222 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4223 NETIF_F_GSO_GRE_CSUM;
4224 }
4225
94cb1ebb
EBE		 4226 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4227
4228 if (fcs_supported)
4229 netdev->hw_features |= NETIF_F_RXALL;
4230
102722fc
GE		 4231 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4232 netdev->hw_features |= NETIF_F_RXFCS;
4233
f62b8bb8 4234 netdev->features = netdev->hw_features;
6a9764ef 4235 if (!priv->channels.params.lro_en)
f62b8bb8
AV		 4236 netdev->features &= ~NETIF_F_LRO;
4237
94cb1ebb
EBE		 4238 if (fcs_enabled)
4239 netdev->features &= ~NETIF_F_RXALL;
4240
102722fc
GE		 4241 if (!priv->channels.params.scatter_fcs_en)
4242 netdev->features &= ~NETIF_F_RXFCS;
4243
e8f887ac
AV		 4244#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4245 if (FT_CAP(flow_modify_en) &&
4246 FT_CAP(modify_root) &&
4247 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 4248 FT_CAP(flow_table_modify)) {
4249 netdev->hw_features |= NETIF_F_HW_TC;
4250#ifdef CONFIG_RFS_ACCEL
4251 netdev->hw_features |= NETIF_F_NTUPLE;
4252#endif
4253 }
e8f887ac 4254
f62b8bb8 4255 netdev->features |= NETIF_F_HIGHDMA;
7d92d580 4256 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
f62b8bb8
AV		 4257
4258 netdev->priv_flags |= IFF_UNICAST_FLT;
4259
4260 mlx5e_set_netdev_dev_addr(netdev);
cb67b832 4261
e80541ec 4262#if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
a9f7705f 4263 if (MLX5_VPORT_MANAGER(mdev))
cb67b832
HHZ		 4264 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4265#endif
547eede0
IT		 4266
4267 mlx5e_ipsec_build_netdev(priv);
f62b8bb8
AV		 4268}
4269
593cf338
RS		 4270static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
4271{
4272 struct mlx5_core_dev *mdev = priv->mdev;
4273 int err;
4274
4275 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4276 if (err) {
4277 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4278 priv->q_counter = 0;
4279 }
4280}
4281
4282static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
4283{
4284 if (!priv->q_counter)
4285 return;
4286
4287 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4288}
4289
6bfd390b
HHZ		 4290static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4291 struct net_device *netdev,
127ea380
HHZ		 4292 const struct mlx5e_profile *profile,
4293 void *ppriv)
6bfd390b
HHZ		 4294{
4295 struct mlx5e_priv *priv = netdev_priv(netdev);
547eede0 4296 int err;
6bfd390b 4297
127ea380 4298 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
547eede0
IT		 4299 err = mlx5e_ipsec_init(priv);
4300 if (err)
4301 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
6bfd390b
HHZ		 4302 mlx5e_build_nic_netdev(netdev);
4303 mlx5e_vxlan_init(priv);
4304}
4305
4306static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4307{
547eede0 4308 mlx5e_ipsec_cleanup(priv);
6bfd390b 4309 mlx5e_vxlan_cleanup(priv);
127ea380 4310
6a9764ef
SM		 4311 if (priv->channels.params.xdp_prog)
4312 bpf_prog_put(priv->channels.params.xdp_prog);
6bfd390b
HHZ		 4313}
4314
4315static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4316{
4317 struct mlx5_core_dev *mdev = priv->mdev;
4318 int err;
6bfd390b 4319
8f493ffd
SM		 4320 err = mlx5e_create_indirect_rqt(priv);
4321 if (err)
6bfd390b 4322 return err;
6bfd390b
HHZ		 4323
4324 err = mlx5e_create_direct_rqts(priv);
8f493ffd 4325 if (err)
6bfd390b 4326 goto err_destroy_indirect_rqts;
6bfd390b
HHZ		 4327
4328 err = mlx5e_create_indirect_tirs(priv);
8f493ffd 4329 if (err)
6bfd390b 4330 goto err_destroy_direct_rqts;
6bfd390b
HHZ		 4331
4332 err = mlx5e_create_direct_tirs(priv);
8f493ffd 4333 if (err)
6bfd390b 4334 goto err_destroy_indirect_tirs;
6bfd390b
HHZ		 4335
4336 err = mlx5e_create_flow_steering(priv);
4337 if (err) {
4338 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4339 goto err_destroy_direct_tirs;
4340 }
4341
4342 err = mlx5e_tc_init(priv);
4343 if (err)
4344 goto err_destroy_flow_steering;
4345
4346 return 0;
4347
4348err_destroy_flow_steering:
4349 mlx5e_destroy_flow_steering(priv);
4350err_destroy_direct_tirs:
4351 mlx5e_destroy_direct_tirs(priv);
4352err_destroy_indirect_tirs:
4353 mlx5e_destroy_indirect_tirs(priv);
4354err_destroy_direct_rqts:
8f493ffd 4355 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4356err_destroy_indirect_rqts:
4357 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4358 return err;
4359}
4360
4361static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4362{
6bfd390b
HHZ		 4363 mlx5e_tc_cleanup(priv);
4364 mlx5e_destroy_flow_steering(priv);
4365 mlx5e_destroy_direct_tirs(priv);
4366 mlx5e_destroy_indirect_tirs(priv);
8f493ffd 4367 mlx5e_destroy_direct_rqts(priv);
6bfd390b
HHZ		 4368 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4369}
4370
4371static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4372{
4373 int err;
4374
4375 err = mlx5e_create_tises(priv);
4376 if (err) {
4377 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4378 return err;
4379 }
4380
4381#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 4382 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 4383#endif
4384 return 0;
4385}
4386
4387static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4388{
4389 struct net_device *netdev = priv->netdev;
4390 struct mlx5_core_dev *mdev = priv->mdev;
2c3b5bee
SM		 4391 u16 max_mtu;
4392
4393 mlx5e_init_l2_addr(priv);
4394
63bfd399
EBE		 4395 /* Marking the link as currently not needed by the Driver */
4396 if (!netif_running(netdev))
4397 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4398
2c3b5bee
SM		 4399 /* MTU range: 68 - hw-specific max */
4400 netdev->min_mtu = ETH_MIN_MTU;
4401 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
c139dbfd 4402 netdev->max_mtu = MLX5E_HW2SW_MTU(priv, max_mtu);
2c3b5bee 4403 mlx5e_set_dev_port_mtu(priv);
6bfd390b 4404
7907f23a
AH		 4405 mlx5_lag_add(mdev, netdev);
4406
6bfd390b 4407 mlx5e_enable_async_events(priv);
127ea380 4408
a9f7705f 4409 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39 4410 mlx5e_register_vport_reps(priv);
2c3b5bee 4411
610e89e0
SM		 4412 if (netdev->reg_state != NETREG_REGISTERED)
4413 return;
2a5e7a13
HN		 4414#ifdef CONFIG_MLX5_CORE_EN_DCB
4415 mlx5e_dcbnl_init_app(priv);
4416#endif
610e89e0
SM		 4417 /* Device already registered: sync netdev system state */
4418 if (mlx5e_vxlan_allowed(mdev)) {
4419 rtnl_lock();
4420 udp_tunnel_get_rx_info(netdev);
4421 rtnl_unlock();
4422 }
4423
4424 queue_work(priv->wq, &priv->set_rx_mode_work);
2c3b5bee
SM		 4425
4426 rtnl_lock();
4427 if (netif_running(netdev))
4428 mlx5e_open(netdev);
4429 netif_device_attach(netdev);
4430 rtnl_unlock();
6bfd390b
HHZ		 4431}
4432
4433static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4434{
3deef8ce 4435 struct mlx5_core_dev *mdev = priv->mdev;
3deef8ce 4436
2a5e7a13
HN		 4437#ifdef CONFIG_MLX5_CORE_EN_DCB
4438 if (priv->netdev->reg_state == NETREG_REGISTERED)
4439 mlx5e_dcbnl_delete_app(priv);
4440#endif
4441
2c3b5bee
SM		 4442 rtnl_lock();
4443 if (netif_running(priv->netdev))
4444 mlx5e_close(priv->netdev);
4445 netif_device_detach(priv->netdev);
4446 rtnl_unlock();
4447
6bfd390b 4448 queue_work(priv->wq, &priv->set_rx_mode_work);
1d447a39 4449
a9f7705f 4450 if (MLX5_VPORT_MANAGER(priv->mdev))
1d447a39
SM		 4451 mlx5e_unregister_vport_reps(priv);
4452
6bfd390b 4453 mlx5e_disable_async_events(priv);
3deef8ce 4454 mlx5_lag_remove(mdev);
6bfd390b
HHZ		 4455}
4456
4457static const struct mlx5e_profile mlx5e_nic_profile = {
4458 .init = mlx5e_nic_init,
4459 .cleanup = mlx5e_nic_cleanup,
4460 .init_rx = mlx5e_init_nic_rx,
4461 .cleanup_rx = mlx5e_cleanup_nic_rx,
4462 .init_tx = mlx5e_init_nic_tx,
4463 .cleanup_tx = mlx5e_cleanup_nic_tx,
4464 .enable = mlx5e_nic_enable,
4465 .disable = mlx5e_nic_disable,
3834a5e6 4466 .update_stats = mlx5e_update_ndo_stats,
6bfd390b 4467 .max_nch = mlx5e_get_max_num_channels,
7ca42c80 4468 .update_carrier = mlx5e_update_carrier,
20fd0c19
SM		 4469 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4470 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
6bfd390b
HHZ		 4471 .max_tc = MLX5E_MAX_NUM_TC,
4472};
4473
2c3b5bee
SM		 4474/* mlx5e generic netdev management API (move to en_common.c) */
4475
26e59d80
MHY		 4476struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4477 const struct mlx5e_profile *profile,
4478 void *ppriv)
f62b8bb8 4479{
26e59d80 4480 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 4481 struct net_device *netdev;
4482 struct mlx5e_priv *priv;
f62b8bb8 4483
08fb1dac 4484 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 4485 nch * profile->max_tc,
08fb1dac 4486 nch);
f62b8bb8
AV		 4487 if (!netdev) {
4488 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4489 return NULL;
4490 }
4491
be4891af
SM		 4492#ifdef CONFIG_RFS_ACCEL
4493 netdev->rx_cpu_rmap = mdev->rmap;
4494#endif
4495
127ea380 4496 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 4497
4498 netif_carrier_off(netdev);
4499
4500 priv = netdev_priv(netdev);
4501
7bb29755
MF		 4502 priv->wq = create_singlethread_workqueue("mlx5e");
4503 if (!priv->wq)
26e59d80
MHY		 4504 goto err_cleanup_nic;
4505
4506 return netdev;
4507
4508err_cleanup_nic:
31ac9338
OG		 4509 if (profile->cleanup)
4510 profile->cleanup(priv);
26e59d80
MHY		 4511 free_netdev(netdev);
4512
4513 return NULL;
4514}
4515
2c3b5bee 4516int mlx5e_attach_netdev(struct mlx5e_priv *priv)
26e59d80 4517{
2c3b5bee 4518 struct mlx5_core_dev *mdev = priv->mdev;
26e59d80 4519 const struct mlx5e_profile *profile;
26e59d80
MHY		 4520 int err;
4521
26e59d80
MHY		 4522 profile = priv->profile;
4523 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 4524
6bfd390b
HHZ		 4525 err = profile->init_tx(priv);
4526 if (err)
ec8b9981 4527 goto out;
5c50368f 4528
a43b25da 4529 err = mlx5e_open_drop_rq(mdev, &priv->drop_rq);
5c50368f
AS		 4530 if (err) {
4531 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 4532 goto err_cleanup_tx;
5c50368f
AS		 4533 }
4534
6bfd390b
HHZ		 4535 err = profile->init_rx(priv);
4536 if (err)
5c50368f 4537 goto err_close_drop_rq;
5c50368f 4538
593cf338
RS		 4539 mlx5e_create_q_counter(priv);
4540
6bfd390b
HHZ		 4541 if (profile->enable)
4542 profile->enable(priv);
f62b8bb8 4543
26e59d80 4544 return 0;
5c50368f
AS		 4545
4546err_close_drop_rq:
a43b25da 4547 mlx5e_close_drop_rq(&priv->drop_rq);
5c50368f 4548
6bfd390b
HHZ		 4549err_cleanup_tx:
4550 profile->cleanup_tx(priv);
5c50368f 4551
26e59d80
MHY		 4552out:
4553 return err;
f62b8bb8
AV		 4554}
4555
2c3b5bee 4556void mlx5e_detach_netdev(struct mlx5e_priv *priv)
26e59d80 4557{
26e59d80
MHY		 4558 const struct mlx5e_profile *profile = priv->profile;
4559
4560 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
26e59d80 4561
37f304d1
SM		 4562 if (profile->disable)
4563 profile->disable(priv);
4564 flush_workqueue(priv->wq);
4565
26e59d80
MHY		 4566 mlx5e_destroy_q_counter(priv);
4567 profile->cleanup_rx(priv);
a43b25da 4568 mlx5e_close_drop_rq(&priv->drop_rq);
26e59d80 4569 profile->cleanup_tx(priv);
26e59d80
MHY		 4570 cancel_delayed_work_sync(&priv->update_stats_work);
4571}
4572
2c3b5bee
SM		 4573void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4574{
4575 const struct mlx5e_profile *profile = priv->profile;
4576 struct net_device *netdev = priv->netdev;
4577
4578 destroy_workqueue(priv->wq);
4579 if (profile->cleanup)
4580 profile->cleanup(priv);
4581 free_netdev(netdev);
4582}
4583
26e59d80
MHY		 4584/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4585 * hardware contexts and to connect it to the current netdev.
4586 */
4587static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4588{
4589 struct mlx5e_priv *priv = vpriv;
4590 struct net_device *netdev = priv->netdev;
4591 int err;
4592
4593 if (netif_device_present(netdev))
4594 return 0;
4595
4596 err = mlx5e_create_mdev_resources(mdev);
4597 if (err)
4598 return err;
4599
2c3b5bee 4600 err = mlx5e_attach_netdev(priv);
26e59d80
MHY		 4601 if (err) {
4602 mlx5e_destroy_mdev_resources(mdev);
4603 return err;
4604 }
4605
4606 return 0;
4607}
4608
4609static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4610{
4611 struct mlx5e_priv *priv = vpriv;
4612 struct net_device *netdev = priv->netdev;
4613
4614 if (!netif_device_present(netdev))
4615 return;
4616
2c3b5bee 4617 mlx5e_detach_netdev(priv);
26e59d80
MHY		 4618 mlx5e_destroy_mdev_resources(mdev);
4619}
4620
b50d292b
HHZ		 4621static void *mlx5e_add(struct mlx5_core_dev *mdev)
4622{
07c9f1e5
SM		 4623 struct net_device *netdev;
4624 void *rpriv = NULL;
26e59d80 4625 void *priv;
26e59d80 4626 int err;
b50d292b 4627
26e59d80
MHY		 4628 err = mlx5e_check_required_hca_cap(mdev);
4629 if (err)
b50d292b
HHZ		 4630 return NULL;
4631
e80541ec 4632#ifdef CONFIG_MLX5_ESWITCH
a9f7705f 4633 if (MLX5_VPORT_MANAGER(mdev)) {
07c9f1e5 4634 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
1d447a39 4635 if (!rpriv) {
07c9f1e5 4636 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
1d447a39
SM		 4637 return NULL;
4638 }
1d447a39 4639 }
e80541ec 4640#endif
127ea380 4641
1d447a39 4642 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
26e59d80
MHY		 4643 if (!netdev) {
4644 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
07c9f1e5 4645 goto err_free_rpriv;
26e59d80
MHY		 4646 }
4647
4648 priv = netdev_priv(netdev);
4649
4650 err = mlx5e_attach(mdev, priv);
4651 if (err) {
4652 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4653 goto err_destroy_netdev;
4654 }
4655
4656 err = register_netdev(netdev);
4657 if (err) {
4658 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4659 goto err_detach;
b50d292b 4660 }
26e59d80 4661
2a5e7a13
HN		 4662#ifdef CONFIG_MLX5_CORE_EN_DCB
4663 mlx5e_dcbnl_init_app(priv);
4664#endif
26e59d80
MHY		 4665 return priv;
4666
4667err_detach:
4668 mlx5e_detach(mdev, priv);
26e59d80 4669err_destroy_netdev:
2c3b5bee 4670 mlx5e_destroy_netdev(priv);
07c9f1e5 4671err_free_rpriv:
1d447a39 4672 kfree(rpriv);
26e59d80 4673 return NULL;
b50d292b
HHZ		 4674}
4675
b50d292b
HHZ		 4676static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4677{
4678 struct mlx5e_priv *priv = vpriv;
1d447a39 4679 void *ppriv = priv->ppriv;
127ea380 4680
2a5e7a13
HN		 4681#ifdef CONFIG_MLX5_CORE_EN_DCB
4682 mlx5e_dcbnl_delete_app(priv);
4683#endif
5e1e93c7 4684 unregister_netdev(priv->netdev);
26e59d80 4685 mlx5e_detach(mdev, vpriv);
2c3b5bee 4686 mlx5e_destroy_netdev(priv);
1d447a39 4687 kfree(ppriv);
b50d292b
HHZ		 4688}
4689
f62b8bb8
AV		 4690static void *mlx5e_get_netdev(void *vpriv)
4691{
4692 struct mlx5e_priv *priv = vpriv;
4693
4694 return priv->netdev;
4695}
4696
4697static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4698 .add = mlx5e_add,
4699 .remove = mlx5e_remove,
26e59d80
MHY		 4700 .attach = mlx5e_attach,
4701 .detach = mlx5e_detach,
f62b8bb8
AV		 4702 .event = mlx5e_async_event,
4703 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4704 .get_dev = mlx5e_get_netdev,
4705};
4706
4707void mlx5e_init(void)
4708{
2ac9cfe7 4709 mlx5e_ipsec_build_inverse_table();
665bc539 4710 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4711 mlx5_register_interface(&mlx5e_interface);
4712}
4713
4714void mlx5e_cleanup(void)
4715{
4716 mlx5_unregister_interface(&mlx5e_interface);
4717}
Linux 6.x block layer and io_uring tree(s)