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net/mlx5e: Implement Fragmented Work Queue (WQ)
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_main.c
CommitLineData
f62b8bb8 1/*
b3f63c3d 2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8
AV		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e8f887ac
AV		 33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
86d722ad 35#include <linux/mlx5/fs.h>
b3f63c3d 36#include <net/vxlan.h>
86994156 37#include <linux/bpf.h>
f62b8bb8 38#include "en.h"
e8f887ac 39#include "en_tc.h"
66e49ded 40#include "eswitch.h"
b3f63c3d 41#include "vxlan.h"
f62b8bb8
AV		 42
43struct mlx5e_rq_param {
cb3c7fd4
GR		 44 u32 rqc[MLX5_ST_SZ_DW(rqc)];
45 struct mlx5_wq_param wq;
46 bool am_enabled;
f62b8bb8
AV		 47};
48
49struct mlx5e_sq_param {
50 u32 sqc[MLX5_ST_SZ_DW(sqc)];
51 struct mlx5_wq_param wq;
58d52291 52 u16 max_inline;
cff92d7c 53 u8 min_inline_mode;
f10b7cc7 54 enum mlx5e_sq_type type;
f62b8bb8
AV		 55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
9908aa29 61 u8 cq_period_mode;
f62b8bb8
AV		 62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
b5503b99 67 struct mlx5e_sq_param xdp_sq;
d3c9bc27 68 struct mlx5e_sq_param icosq;
f62b8bb8
AV		 69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
d3c9bc27 71 struct mlx5e_cq_param icosq_cq;
f62b8bb8
AV		 72};
73
2fc4bfb7
SM		 74static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 return MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79}
80
81static void mlx5e_set_rq_type_params(struct mlx5e_priv *priv, u8 rq_type)
82{
83 priv->params.rq_wq_type = rq_type;
84 switch (priv->params.rq_wq_type) {
85 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
86 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
9bcc8606
SD		 87 priv->params.mpwqe_log_stride_sz =
88 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS) ?
2fc4bfb7
SM		 89 MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
90 MLX5_MPWRQ_LOG_STRIDE_SIZE;
91 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
92 priv->params.mpwqe_log_stride_sz;
93 break;
94 default: /* MLX5_WQ_TYPE_LINKED_LIST */
95 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
96 }
97 priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
98 BIT(priv->params.log_rq_size));
99
100 mlx5_core_info(priv->mdev,
101 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
102 priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
103 BIT(priv->params.log_rq_size),
104 BIT(priv->params.mpwqe_log_stride_sz),
9bcc8606 105 MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS));
2fc4bfb7
SM		 106}
107
108static void mlx5e_set_rq_priv_params(struct mlx5e_priv *priv)
109{
86994156
RS		 110 u8 rq_type = mlx5e_check_fragmented_striding_rq_cap(priv->mdev) &&
111 !priv->xdp_prog ?
2fc4bfb7
SM		 112 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
113 MLX5_WQ_TYPE_LINKED_LIST;
114 mlx5e_set_rq_type_params(priv, rq_type);
115}
116
f62b8bb8
AV		 117static void mlx5e_update_carrier(struct mlx5e_priv *priv)
118{
119 struct mlx5_core_dev *mdev = priv->mdev;
120 u8 port_state;
121
122 port_state = mlx5_query_vport_state(mdev,
e7546514 123 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
f62b8bb8 124
87424ad5
SD		 125 if (port_state == VPORT_STATE_UP) {
126 netdev_info(priv->netdev, "Link up\n");
f62b8bb8 127 netif_carrier_on(priv->netdev);
87424ad5
SD		 128 } else {
129 netdev_info(priv->netdev, "Link down\n");
f62b8bb8 130 netif_carrier_off(priv->netdev);
87424ad5 131 }
f62b8bb8
AV		 132}
133
134static void mlx5e_update_carrier_work(struct work_struct *work)
135{
136 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
137 update_carrier_work);
138
139 mutex_lock(&priv->state_lock);
140 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
141 mlx5e_update_carrier(priv);
142 mutex_unlock(&priv->state_lock);
143}
144
3947ca18
DJ		 145static void mlx5e_tx_timeout_work(struct work_struct *work)
146{
147 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
148 tx_timeout_work);
149 int err;
150
151 rtnl_lock();
152 mutex_lock(&priv->state_lock);
153 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
154 goto unlock;
155 mlx5e_close_locked(priv->netdev);
156 err = mlx5e_open_locked(priv->netdev);
157 if (err)
158 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
159 err);
160unlock:
161 mutex_unlock(&priv->state_lock);
162 rtnl_unlock();
163}
164
9218b44d 165static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
f62b8bb8 166{
9218b44d 167 struct mlx5e_sw_stats *s = &priv->stats.sw;
f62b8bb8
AV		 168 struct mlx5e_rq_stats *rq_stats;
169 struct mlx5e_sq_stats *sq_stats;
9218b44d 170 u64 tx_offload_none = 0;
f62b8bb8
AV		 171 int i, j;
172
9218b44d 173 memset(s, 0, sizeof(*s));
f62b8bb8
AV		 174 for (i = 0; i < priv->params.num_channels; i++) {
175 rq_stats = &priv->channel[i]->rq.stats;
176
faf4478b
GP		 177 s->rx_packets += rq_stats->packets;
178 s->rx_bytes += rq_stats->bytes;
bfe6d8d1
GP		 179 s->rx_lro_packets += rq_stats->lro_packets;
180 s->rx_lro_bytes += rq_stats->lro_bytes;
f62b8bb8 181 s->rx_csum_none += rq_stats->csum_none;
bfe6d8d1
GP		 182 s->rx_csum_complete += rq_stats->csum_complete;
183 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
86994156 184 s->rx_xdp_drop += rq_stats->xdp_drop;
b5503b99
SM		 185 s->rx_xdp_tx += rq_stats->xdp_tx;
186 s->rx_xdp_tx_full += rq_stats->xdp_tx_full;
f62b8bb8 187 s->rx_wqe_err += rq_stats->wqe_err;
461017cb 188 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
54984407 189 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
7219ab34
TT		 190 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
191 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
4415a031
TT		 192 s->rx_cache_reuse += rq_stats->cache_reuse;
193 s->rx_cache_full += rq_stats->cache_full;
194 s->rx_cache_empty += rq_stats->cache_empty;
195 s->rx_cache_busy += rq_stats->cache_busy;
f62b8bb8 196
a4418a6c 197 for (j = 0; j < priv->params.num_tc; j++) {
f62b8bb8
AV		 198 sq_stats = &priv->channel[i]->sq[j].stats;
199
faf4478b
GP		 200 s->tx_packets += sq_stats->packets;
201 s->tx_bytes += sq_stats->bytes;
bfe6d8d1
GP		 202 s->tx_tso_packets += sq_stats->tso_packets;
203 s->tx_tso_bytes += sq_stats->tso_bytes;
204 s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
205 s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes;
f62b8bb8
AV		 206 s->tx_queue_stopped += sq_stats->stopped;
207 s->tx_queue_wake += sq_stats->wake;
208 s->tx_queue_dropped += sq_stats->dropped;
c8cf78fe 209 s->tx_xmit_more += sq_stats->xmit_more;
bfe6d8d1
GP		 210 s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
211 tx_offload_none += sq_stats->csum_none;
f62b8bb8
AV		 212 }
213 }
214
9218b44d 215 /* Update calculated offload counters */
bfe6d8d1
GP		 216 s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
217 s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
121fcdc8 218
bfe6d8d1 219 s->link_down_events_phy = MLX5_GET(ppcnt_reg,
121fcdc8
GP		 220 priv->stats.pport.phy_counters,
221 counter_set.phys_layer_cntrs.link_down_events);
9218b44d
GP		 222}
223
224static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
225{
226 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
227 u32 *out = (u32 *)priv->stats.vport.query_vport_out;
c4f287c4 228 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
9218b44d
GP		 229 struct mlx5_core_dev *mdev = priv->mdev;
230
f62b8bb8
AV		 231 MLX5_SET(query_vport_counter_in, in, opcode,
232 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
233 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
234 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
235
236 memset(out, 0, outlen);
9218b44d
GP		 237 mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
238}
239
240static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
241{
242 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
243 struct mlx5_core_dev *mdev = priv->mdev;
244 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
cf678570 245 int prio;
9218b44d
GP		 246 void *out;
247 u32 *in;
248
249 in = mlx5_vzalloc(sz);
250 if (!in)
f62b8bb8
AV		 251 goto free_out;
252
9218b44d 253 MLX5_SET(ppcnt_reg, in, local_port, 1);
f62b8bb8 254
9218b44d
GP		 255 out = pstats->IEEE_802_3_counters;
256 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
257 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
f62b8bb8 258
9218b44d
GP		 259 out = pstats->RFC_2863_counters;
260 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
261 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
262
263 out = pstats->RFC_2819_counters;
264 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
265 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
593cf338 266
121fcdc8
GP		 267 out = pstats->phy_counters;
268 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
269 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
270
cf678570
GP		 271 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
272 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
273 out = pstats->per_prio_counters[prio];
274 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
275 mlx5_core_access_reg(mdev, in, sz, out, sz,
276 MLX5_REG_PPCNT, 0, 0);
277 }
278
f62b8bb8 279free_out:
9218b44d
GP		 280 kvfree(in);
281}
282
283static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
284{
285 struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
286
287 if (!priv->q_counter)
288 return;
289
290 mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
291 &qcnt->rx_out_of_buffer);
292}
293
9c726239
GP		 294static void mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
295{
296 struct mlx5e_pcie_stats *pcie_stats = &priv->stats.pcie;
297 struct mlx5_core_dev *mdev = priv->mdev;
298 int sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
299 void *out;
300 u32 *in;
301
302 in = mlx5_vzalloc(sz);
303 if (!in)
304 return;
305
306 out = pcie_stats->pcie_perf_counters;
307 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
308 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
309
310 out = pcie_stats->pcie_tas_counters;
311 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
312 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
313
314 kvfree(in);
315}
316
9218b44d
GP		 317void mlx5e_update_stats(struct mlx5e_priv *priv)
318{
9218b44d
GP		 319 mlx5e_update_q_counter(priv);
320 mlx5e_update_vport_counters(priv);
321 mlx5e_update_pport_counters(priv);
121fcdc8 322 mlx5e_update_sw_counters(priv);
9c726239 323 mlx5e_update_pcie_counters(priv);
f62b8bb8
AV		 324}
325
cb67b832 326void mlx5e_update_stats_work(struct work_struct *work)
f62b8bb8
AV		 327{
328 struct delayed_work *dwork = to_delayed_work(work);
329 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
330 update_stats_work);
331 mutex_lock(&priv->state_lock);
332 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
6bfd390b 333 priv->profile->update_stats(priv);
7bb29755
MF		 334 queue_delayed_work(priv->wq, dwork,
335 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
f62b8bb8
AV		 336 }
337 mutex_unlock(&priv->state_lock);
338}
339
daa21560
TT		 340static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
341 enum mlx5_dev_event event, unsigned long param)
f62b8bb8 342{
daa21560
TT		 343 struct mlx5e_priv *priv = vpriv;
344
e0f46eb9 345 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
daa21560
TT		 346 return;
347
f62b8bb8
AV		 348 switch (event) {
349 case MLX5_DEV_EVENT_PORT_UP:
350 case MLX5_DEV_EVENT_PORT_DOWN:
7bb29755 351 queue_work(priv->wq, &priv->update_carrier_work);
f62b8bb8
AV		 352 break;
353
354 default:
355 break;
356 }
357}
358
f62b8bb8
AV		 359static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
360{
e0f46eb9 361 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
f62b8bb8
AV		 362}
363
364static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
365{
e0f46eb9 366 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
daa21560 367 synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
f62b8bb8
AV		 368}
369
facc9699
SM		 370#define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
371#define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
372
7e426671
TT		 373static inline int mlx5e_get_wqe_mtt_sz(void)
374{
375 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
376 * To avoid copying garbage after the mtt array, we allocate
377 * a little more.
378 */
379 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
380 MLX5_UMR_MTT_ALIGNMENT);
381}
382
383static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
384 struct mlx5e_umr_wqe *wqe, u16 ix)
385{
386 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
387 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
388 struct mlx5_wqe_data_seg *dseg = &wqe->data;
21c59685 389 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
7e426671
TT		 390 u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
391 u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
392
393 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
394 ds_cnt);
395 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
396 cseg->imm = rq->mkey_be;
397
398 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
399 ucseg->klm_octowords =
400 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
401 ucseg->bsf_octowords =
402 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
403 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
404
405 dseg->lkey = sq->mkey_be;
406 dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
407}
408
409static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
410 struct mlx5e_channel *c)
411{
412 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
413 int mtt_sz = mlx5e_get_wqe_mtt_sz();
414 int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
415 int i;
416
21c59685
SM		 417 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
418 GFP_KERNEL, cpu_to_node(c->cpu));
419 if (!rq->mpwqe.info)
7e426671
TT		 420 goto err_out;
421
422 /* We allocate more than mtt_sz as we will align the pointer */
21c59685 423 rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
7e426671 424 cpu_to_node(c->cpu));
21c59685 425 if (unlikely(!rq->mpwqe.mtt_no_align))
7e426671
TT		 426 goto err_free_wqe_info;
427
428 for (i = 0; i < wq_sz; i++) {
21c59685 429 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671 430
21c59685 431 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
7e426671
TT		 432 MLX5_UMR_ALIGN);
433 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
434 PCI_DMA_TODEVICE);
435 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
436 goto err_unmap_mtts;
437
438 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
439 }
440
441 return 0;
442
443err_unmap_mtts:
444 while (--i >= 0) {
21c59685 445 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 446
447 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
448 PCI_DMA_TODEVICE);
449 }
21c59685 450 kfree(rq->mpwqe.mtt_no_align);
7e426671 451err_free_wqe_info:
21c59685 452 kfree(rq->mpwqe.info);
7e426671
TT		 453
454err_out:
455 return -ENOMEM;
456}
457
458static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
459{
460 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
461 int mtt_sz = mlx5e_get_wqe_mtt_sz();
462 int i;
463
464 for (i = 0; i < wq_sz; i++) {
21c59685 465 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
7e426671
TT		 466
467 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
468 PCI_DMA_TODEVICE);
469 }
21c59685
SM		 470 kfree(rq->mpwqe.mtt_no_align);
471 kfree(rq->mpwqe.info);
7e426671
TT		 472}
473
f62b8bb8
AV		 474static int mlx5e_create_rq(struct mlx5e_channel *c,
475 struct mlx5e_rq_param *param,
476 struct mlx5e_rq *rq)
477{
478 struct mlx5e_priv *priv = c->priv;
479 struct mlx5_core_dev *mdev = priv->mdev;
480 void *rqc = param->rqc;
481 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
461017cb 482 u32 byte_count;
1bfecfca
SM		 483 u32 frag_sz;
484 int npages;
f62b8bb8
AV		 485 int wq_sz;
486 int err;
487 int i;
488
311c7c71
SM		 489 param->wq.db_numa_node = cpu_to_node(c->cpu);
490
f62b8bb8
AV		 491 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
492 &rq->wq_ctrl);
493 if (err)
494 return err;
495
496 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
497
498 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
f62b8bb8 499
7e426671
TT		 500 rq->wq_type = priv->params.rq_wq_type;
501 rq->pdev = c->pdev;
502 rq->netdev = c->netdev;
503 rq->tstamp = &priv->tstamp;
504 rq->channel = c;
505 rq->ix = c->ix;
506 rq->priv = c->priv;
97bc402d
DB		 507
508 rq->xdp_prog = priv->xdp_prog ? bpf_prog_inc(priv->xdp_prog) : NULL;
509 if (IS_ERR(rq->xdp_prog)) {
510 err = PTR_ERR(rq->xdp_prog);
511 rq->xdp_prog = NULL;
512 goto err_rq_wq_destroy;
513 }
7e426671 514
b5503b99
SM		 515 rq->buff.map_dir = DMA_FROM_DEVICE;
516 if (rq->xdp_prog)
517 rq->buff.map_dir = DMA_BIDIRECTIONAL;
518
461017cb
TT		 519 switch (priv->params.rq_wq_type) {
520 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
f5f82476
OG		 521 if (mlx5e_is_vf_vport_rep(priv)) {
522 err = -EINVAL;
523 goto err_rq_wq_destroy;
524 }
525
461017cb
TT		 526 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
527 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
6cd392a0 528 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
461017cb 529
21c59685 530 rq->mpwqe.mtt_offset = c->ix *
fe4c988b
SM		 531 MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
532
d9d9f156
TT		 533 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
534 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
1bfecfca
SM		 535
536 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
537 byte_count = rq->buff.wqe_sz;
7e426671
TT		 538 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
539 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
540 if (err)
541 goto err_rq_wq_destroy;
461017cb
TT		 542 break;
543 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca
SM		 544 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
545 GFP_KERNEL, cpu_to_node(c->cpu));
546 if (!rq->dma_info) {
461017cb
TT		 547 err = -ENOMEM;
548 goto err_rq_wq_destroy;
549 }
1bfecfca 550
f5f82476
OG		 551 if (mlx5e_is_vf_vport_rep(priv))
552 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_rep;
553 else
554 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
555
461017cb 556 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
6cd392a0 557 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
461017cb 558
1bfecfca 559 rq->buff.wqe_sz = (priv->params.lro_en) ?
461017cb
TT		 560 priv->params.lro_wqe_sz :
561 MLX5E_SW2HW_MTU(priv->netdev->mtu);
1bfecfca
SM		 562 byte_count = rq->buff.wqe_sz;
563
564 /* calc the required page order */
565 frag_sz = MLX5_RX_HEADROOM +
566 byte_count /* packet data */ +
567 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
568 frag_sz = SKB_DATA_ALIGN(frag_sz);
569
570 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
571 rq->buff.page_order = order_base_2(npages);
572
461017cb 573 byte_count |= MLX5_HW_START_PADDING;
7e426671 574 rq->mkey_be = c->mkey_be;
461017cb 575 }
f62b8bb8
AV		 576
577 for (i = 0; i < wq_sz; i++) {
578 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
579
461017cb 580 wqe->data.byte_count = cpu_to_be32(byte_count);
7e426671 581 wqe->data.lkey = rq->mkey_be;
f62b8bb8
AV		 582 }
583
cb3c7fd4
GR		 584 INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
585 rq->am.mode = priv->params.rx_cq_period_mode;
586
4415a031
TT		 587 rq->page_cache.head = 0;
588 rq->page_cache.tail = 0;
589
f62b8bb8
AV		 590 return 0;
591
592err_rq_wq_destroy:
97bc402d
DB		 593 if (rq->xdp_prog)
594 bpf_prog_put(rq->xdp_prog);
f62b8bb8
AV		 595 mlx5_wq_destroy(&rq->wq_ctrl);
596
597 return err;
598}
599
600static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
601{
4415a031
TT		 602 int i;
603
86994156
RS		 604 if (rq->xdp_prog)
605 bpf_prog_put(rq->xdp_prog);
606
461017cb
TT		 607 switch (rq->wq_type) {
608 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
7e426671 609 mlx5e_rq_free_mpwqe_info(rq);
461017cb
TT		 610 break;
611 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1bfecfca 612 kfree(rq->dma_info);
461017cb
TT		 613 }
614
4415a031
TT		 615 for (i = rq->page_cache.head; i != rq->page_cache.tail;
616 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
617 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
618
619 mlx5e_page_release(rq, dma_info, false);
620 }
f62b8bb8
AV		 621 mlx5_wq_destroy(&rq->wq_ctrl);
622}
623
624static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
625{
50cfa25a 626 struct mlx5e_priv *priv = rq->priv;
f62b8bb8
AV		 627 struct mlx5_core_dev *mdev = priv->mdev;
628
629 void *in;
630 void *rqc;
631 void *wq;
632 int inlen;
633 int err;
634
635 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
636 sizeof(u64) * rq->wq_ctrl.buf.npages;
637 in = mlx5_vzalloc(inlen);
638 if (!in)
639 return -ENOMEM;
640
641 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
642 wq = MLX5_ADDR_OF(rqc, rqc, wq);
643
644 memcpy(rqc, param->rqc, sizeof(param->rqc));
645
97de9f31 646 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
f62b8bb8 647 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
36350114 648 MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable);
f62b8bb8 649 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
68cdf5d6 650 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 651 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
652
653 mlx5_fill_page_array(&rq->wq_ctrl.buf,
654 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
655
7db22ffb 656 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
f62b8bb8
AV		 657
658 kvfree(in);
659
660 return err;
661}
662
36350114
GP		 663static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
664 int next_state)
f62b8bb8
AV		 665{
666 struct mlx5e_channel *c = rq->channel;
667 struct mlx5e_priv *priv = c->priv;
668 struct mlx5_core_dev *mdev = priv->mdev;
669
670 void *in;
671 void *rqc;
672 int inlen;
673 int err;
674
675 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
676 in = mlx5_vzalloc(inlen);
677 if (!in)
678 return -ENOMEM;
679
680 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
681
682 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
683 MLX5_SET(rqc, rqc, state, next_state);
684
7db22ffb 685 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
f62b8bb8
AV		 686
687 kvfree(in);
688
689 return err;
690}
691
36350114
GP		 692static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
693{
694 struct mlx5e_channel *c = rq->channel;
695 struct mlx5e_priv *priv = c->priv;
696 struct mlx5_core_dev *mdev = priv->mdev;
697
698 void *in;
699 void *rqc;
700 int inlen;
701 int err;
702
703 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
704 in = mlx5_vzalloc(inlen);
705 if (!in)
706 return -ENOMEM;
707
708 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
709
710 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
83b502a1
AV		 711 MLX5_SET64(modify_rq_in, in, modify_bitmask,
712 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
36350114
GP		 713 MLX5_SET(rqc, rqc, vsd, vsd);
714 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
715
716 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
717
718 kvfree(in);
719
720 return err;
721}
722
f62b8bb8
AV		 723static void mlx5e_disable_rq(struct mlx5e_rq *rq)
724{
50cfa25a 725 mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
f62b8bb8
AV		 726}
727
728static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
729{
01c196a2 730 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
f62b8bb8
AV		 731 struct mlx5e_channel *c = rq->channel;
732 struct mlx5e_priv *priv = c->priv;
733 struct mlx5_wq_ll *wq = &rq->wq;
f62b8bb8 734
01c196a2 735 while (time_before(jiffies, exp_time)) {
f62b8bb8
AV		 736 if (wq->cur_sz >= priv->params.min_rx_wqes)
737 return 0;
738
739 msleep(20);
740 }
741
742 return -ETIMEDOUT;
743}
744
f2fde18c
SM		 745static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
746{
747 struct mlx5_wq_ll *wq = &rq->wq;
748 struct mlx5e_rx_wqe *wqe;
749 __be16 wqe_ix_be;
750 u16 wqe_ix;
751
8484f9ed
SM		 752 /* UMR WQE (if in progress) is always at wq->head */
753 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
21c59685 754 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
8484f9ed 755
f2fde18c
SM		 756 while (!mlx5_wq_ll_is_empty(wq)) {
757 wqe_ix_be = *wq->tail_next;
758 wqe_ix = be16_to_cpu(wqe_ix_be);
759 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
760 rq->dealloc_wqe(rq, wqe_ix);
761 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
762 &wqe->next.next_wqe_index);
763 }
764}
765
f62b8bb8
AV		 766static int mlx5e_open_rq(struct mlx5e_channel *c,
767 struct mlx5e_rq_param *param,
768 struct mlx5e_rq *rq)
769{
d3c9bc27
TT		 770 struct mlx5e_sq *sq = &c->icosq;
771 u16 pi = sq->pc & sq->wq.sz_m1;
f62b8bb8
AV		 772 int err;
773
774 err = mlx5e_create_rq(c, param, rq);
775 if (err)
776 return err;
777
778 err = mlx5e_enable_rq(rq, param);
779 if (err)
780 goto err_destroy_rq;
781
36350114 782 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
f62b8bb8
AV		 783 if (err)
784 goto err_disable_rq;
785
cb3c7fd4
GR		 786 if (param->am_enabled)
787 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
788
f10b7cc7
SM		 789 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
790 sq->db.ico_wqe[pi].num_wqebbs = 1;
d3c9bc27 791 mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
f62b8bb8
AV		 792
793 return 0;
794
795err_disable_rq:
796 mlx5e_disable_rq(rq);
797err_destroy_rq:
798 mlx5e_destroy_rq(rq);
799
800 return err;
801}
802
803static void mlx5e_close_rq(struct mlx5e_rq *rq)
804{
f2fde18c 805 set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
f62b8bb8 806 napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
cb3c7fd4
GR		 807 cancel_work_sync(&rq->am.work);
808
f62b8bb8 809 mlx5e_disable_rq(rq);
6cd392a0 810 mlx5e_free_rx_descs(rq);
f62b8bb8
AV		 811 mlx5e_destroy_rq(rq);
812}
813
b5503b99
SM		 814static void mlx5e_free_sq_xdp_db(struct mlx5e_sq *sq)
815{
816 kfree(sq->db.xdp.di);
817 kfree(sq->db.xdp.wqe_info);
818}
819
820static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq *sq, int numa)
821{
822 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
823
824 sq->db.xdp.di = kzalloc_node(sizeof(*sq->db.xdp.di) * wq_sz,
825 GFP_KERNEL, numa);
826 sq->db.xdp.wqe_info = kzalloc_node(sizeof(*sq->db.xdp.wqe_info) * wq_sz,
827 GFP_KERNEL, numa);
828 if (!sq->db.xdp.di || !sq->db.xdp.wqe_info) {
829 mlx5e_free_sq_xdp_db(sq);
830 return -ENOMEM;
831 }
832
833 return 0;
834}
835
f10b7cc7 836static void mlx5e_free_sq_ico_db(struct mlx5e_sq *sq)
f62b8bb8 837{
f10b7cc7 838 kfree(sq->db.ico_wqe);
f62b8bb8
AV		 839}
840
f10b7cc7
SM		 841static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq *sq, int numa)
842{
843 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
844
845 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
846 GFP_KERNEL, numa);
847 if (!sq->db.ico_wqe)
848 return -ENOMEM;
849
850 return 0;
851}
852
853static void mlx5e_free_sq_txq_db(struct mlx5e_sq *sq)
854{
855 kfree(sq->db.txq.wqe_info);
856 kfree(sq->db.txq.dma_fifo);
857 kfree(sq->db.txq.skb);
858}
859
860static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq *sq, int numa)
f62b8bb8
AV		 861{
862 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
863 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
864
f10b7cc7
SM		 865 sq->db.txq.skb = kzalloc_node(wq_sz * sizeof(*sq->db.txq.skb),
866 GFP_KERNEL, numa);
867 sq->db.txq.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.txq.dma_fifo),
868 GFP_KERNEL, numa);
869 sq->db.txq.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.txq.wqe_info),
870 GFP_KERNEL, numa);
871 if (!sq->db.txq.skb || !sq->db.txq.dma_fifo || !sq->db.txq.wqe_info) {
872 mlx5e_free_sq_txq_db(sq);
f62b8bb8
AV		 873 return -ENOMEM;
874 }
875
876 sq->dma_fifo_mask = df_sz - 1;
877
878 return 0;
879}
880
f10b7cc7
SM		 881static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
882{
883 switch (sq->type) {
884 case MLX5E_SQ_TXQ:
885 mlx5e_free_sq_txq_db(sq);
886 break;
887 case MLX5E_SQ_ICO:
888 mlx5e_free_sq_ico_db(sq);
889 break;
b5503b99
SM		 890 case MLX5E_SQ_XDP:
891 mlx5e_free_sq_xdp_db(sq);
892 break;
f10b7cc7
SM		 893 }
894}
895
896static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
897{
898 switch (sq->type) {
899 case MLX5E_SQ_TXQ:
900 return mlx5e_alloc_sq_txq_db(sq, numa);
901 case MLX5E_SQ_ICO:
902 return mlx5e_alloc_sq_ico_db(sq, numa);
b5503b99
SM		 903 case MLX5E_SQ_XDP:
904 return mlx5e_alloc_sq_xdp_db(sq, numa);
f10b7cc7
SM		 905 }
906
907 return 0;
908}
909
b5503b99
SM		 910static int mlx5e_sq_get_max_wqebbs(u8 sq_type)
911{
912 switch (sq_type) {
913 case MLX5E_SQ_ICO:
914 return MLX5E_ICOSQ_MAX_WQEBBS;
915 case MLX5E_SQ_XDP:
916 return MLX5E_XDP_TX_WQEBBS;
917 }
918 return MLX5_SEND_WQE_MAX_WQEBBS;
919}
920
f62b8bb8
AV		 921static int mlx5e_create_sq(struct mlx5e_channel *c,
922 int tc,
923 struct mlx5e_sq_param *param,
924 struct mlx5e_sq *sq)
925{
926 struct mlx5e_priv *priv = c->priv;
927 struct mlx5_core_dev *mdev = priv->mdev;
928
929 void *sqc = param->sqc;
930 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
931 int err;
932
f10b7cc7
SM		 933 sq->type = param->type;
934 sq->pdev = c->pdev;
935 sq->tstamp = &priv->tstamp;
936 sq->mkey_be = c->mkey_be;
937 sq->channel = c;
938 sq->tc = tc;
939
fd4782c2 940 err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
f62b8bb8
AV		 941 if (err)
942 return err;
943
311c7c71
SM		 944 param->wq.db_numa_node = cpu_to_node(c->cpu);
945
f62b8bb8
AV		 946 err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
947 &sq->wq_ctrl);
948 if (err)
949 goto err_unmap_free_uar;
950
951 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
0ba42241
ML		 952 if (sq->uar.bf_map) {
953 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
954 sq->uar_map = sq->uar.bf_map;
955 } else {
956 sq->uar_map = sq->uar.map;
957 }
f62b8bb8 958 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
58d52291 959 sq->max_inline = param->max_inline;
cff92d7c 960 sq->min_inline_mode =
34e4e990 961 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT ?
cff92d7c 962 param->min_inline_mode : 0;
f62b8bb8 963
7ec0bb22
DC		 964 err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
965 if (err)
f62b8bb8
AV		 966 goto err_sq_wq_destroy;
967
f10b7cc7 968 if (sq->type == MLX5E_SQ_TXQ) {
d3c9bc27
TT		 969 int txq_ix;
970
971 txq_ix = c->ix + tc * priv->params.num_channels;
972 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
973 priv->txq_to_sq_map[txq_ix] = sq;
974 }
f62b8bb8 975
b5503b99 976 sq->edge = (sq->wq.sz_m1 + 1) - mlx5e_sq_get_max_wqebbs(sq->type);
88a85f99 977 sq->bf_budget = MLX5E_SQ_BF_BUDGET;
f62b8bb8
AV		 978
979 return 0;
980
981err_sq_wq_destroy:
982 mlx5_wq_destroy(&sq->wq_ctrl);
983
984err_unmap_free_uar:
985 mlx5_unmap_free_uar(mdev, &sq->uar);
986
987 return err;
988}
989
990static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
991{
992 struct mlx5e_channel *c = sq->channel;
993 struct mlx5e_priv *priv = c->priv;
994
995 mlx5e_free_sq_db(sq);
996 mlx5_wq_destroy(&sq->wq_ctrl);
997 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
998}
999
1000static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1001{
1002 struct mlx5e_channel *c = sq->channel;
1003 struct mlx5e_priv *priv = c->priv;
1004 struct mlx5_core_dev *mdev = priv->mdev;
1005
1006 void *in;
1007 void *sqc;
1008 void *wq;
1009 int inlen;
1010 int err;
1011
1012 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1013 sizeof(u64) * sq->wq_ctrl.buf.npages;
1014 in = mlx5_vzalloc(inlen);
1015 if (!in)
1016 return -ENOMEM;
1017
1018 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1019 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1020
1021 memcpy(sqc, param->sqc, sizeof(param->sqc));
1022
f10b7cc7
SM		 1023 MLX5_SET(sqc, sqc, tis_num_0, param->type == MLX5E_SQ_ICO ?
1024 0 : priv->tisn[sq->tc]);
d3c9bc27 1025 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
cff92d7c 1026 MLX5_SET(sqc, sqc, min_wqe_inline_mode, sq->min_inline_mode);
f62b8bb8 1027 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
f10b7cc7 1028 MLX5_SET(sqc, sqc, tis_lst_sz, param->type == MLX5E_SQ_ICO ? 0 : 1);
f62b8bb8
AV		 1029 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1030
1031 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1032 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1033 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
68cdf5d6 1034 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1035 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1036
1037 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1038 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1039
7db22ffb 1040 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
f62b8bb8
AV		 1041
1042 kvfree(in);
1043
1044 return err;
1045}
1046
507f0c81
YP		 1047static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
1048 int next_state, bool update_rl, int rl_index)
f62b8bb8
AV		 1049{
1050 struct mlx5e_channel *c = sq->channel;
1051 struct mlx5e_priv *priv = c->priv;
1052 struct mlx5_core_dev *mdev = priv->mdev;
1053
1054 void *in;
1055 void *sqc;
1056 int inlen;
1057 int err;
1058
1059 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1060 in = mlx5_vzalloc(inlen);
1061 if (!in)
1062 return -ENOMEM;
1063
1064 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1065
1066 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1067 MLX5_SET(sqc, sqc, state, next_state);
507f0c81
YP		 1068 if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
1069 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1070 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
1071 }
f62b8bb8 1072
7db22ffb 1073 err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
f62b8bb8
AV		 1074
1075 kvfree(in);
1076
1077 return err;
1078}
1079
1080static void mlx5e_disable_sq(struct mlx5e_sq *sq)
1081{
1082 struct mlx5e_channel *c = sq->channel;
1083 struct mlx5e_priv *priv = c->priv;
1084 struct mlx5_core_dev *mdev = priv->mdev;
1085
7db22ffb 1086 mlx5_core_destroy_sq(mdev, sq->sqn);
507f0c81
YP		 1087 if (sq->rate_limit)
1088 mlx5_rl_remove_rate(mdev, sq->rate_limit);
f62b8bb8
AV		 1089}
1090
1091static int mlx5e_open_sq(struct mlx5e_channel *c,
1092 int tc,
1093 struct mlx5e_sq_param *param,
1094 struct mlx5e_sq *sq)
1095{
1096 int err;
1097
1098 err = mlx5e_create_sq(c, tc, param, sq);
1099 if (err)
1100 return err;
1101
1102 err = mlx5e_enable_sq(sq, param);
1103 if (err)
1104 goto err_destroy_sq;
1105
507f0c81
YP		 1106 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
1107 false, 0);
f62b8bb8
AV		 1108 if (err)
1109 goto err_disable_sq;
1110
d3c9bc27 1111 if (sq->txq) {
d3c9bc27
TT		 1112 netdev_tx_reset_queue(sq->txq);
1113 netif_tx_start_queue(sq->txq);
1114 }
f62b8bb8
AV		 1115
1116 return 0;
1117
1118err_disable_sq:
1119 mlx5e_disable_sq(sq);
1120err_destroy_sq:
1121 mlx5e_destroy_sq(sq);
1122
1123 return err;
1124}
1125
1126static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1127{
1128 __netif_tx_lock_bh(txq);
1129 netif_tx_stop_queue(txq);
1130 __netif_tx_unlock_bh(txq);
1131}
1132
1133static void mlx5e_close_sq(struct mlx5e_sq *sq)
1134{
6e8dd6d6
SM		 1135 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
1136 /* prevent netif_tx_wake_queue */
1137 napi_synchronize(&sq->channel->napi);
29429f33 1138
d3c9bc27 1139 if (sq->txq) {
d3c9bc27 1140 netif_tx_disable_queue(sq->txq);
f62b8bb8 1141
6e8dd6d6 1142 /* last doorbell out, godspeed .. */
f10b7cc7
SM		 1143 if (mlx5e_sq_has_room_for(sq, 1)) {
1144 sq->db.txq.skb[(sq->pc & sq->wq.sz_m1)] = NULL;
d3c9bc27 1145 mlx5e_send_nop(sq, true);
f10b7cc7 1146 }
29429f33 1147 }
f62b8bb8 1148
f62b8bb8 1149 mlx5e_disable_sq(sq);
b5503b99 1150 mlx5e_free_sq_descs(sq);
f62b8bb8
AV		 1151 mlx5e_destroy_sq(sq);
1152}
1153
1154static int mlx5e_create_cq(struct mlx5e_channel *c,
1155 struct mlx5e_cq_param *param,
1156 struct mlx5e_cq *cq)
1157{
1158 struct mlx5e_priv *priv = c->priv;
1159 struct mlx5_core_dev *mdev = priv->mdev;
1160 struct mlx5_core_cq *mcq = &cq->mcq;
1161 int eqn_not_used;
0b6e26ce 1162 unsigned int irqn;
f62b8bb8
AV		 1163 int err;
1164 u32 i;
1165
311c7c71
SM		 1166 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1167 param->wq.db_numa_node = cpu_to_node(c->cpu);
f62b8bb8
AV		 1168 param->eq_ix = c->ix;
1169
1170 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1171 &cq->wq_ctrl);
1172 if (err)
1173 return err;
1174
1175 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1176
1177 cq->napi = &c->napi;
1178
1179 mcq->cqe_sz = 64;
1180 mcq->set_ci_db = cq->wq_ctrl.db.db;
1181 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1182 *mcq->set_ci_db = 0;
1183 *mcq->arm_db = 0;
1184 mcq->vector = param->eq_ix;
1185 mcq->comp = mlx5e_completion_event;
1186 mcq->event = mlx5e_cq_error_event;
1187 mcq->irqn = irqn;
b50d292b 1188 mcq->uar = &mdev->mlx5e_res.cq_uar;
f62b8bb8
AV		 1189
1190 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1191 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1192
1193 cqe->op_own = 0xf1;
1194 }
1195
1196 cq->channel = c;
50cfa25a 1197 cq->priv = priv;
f62b8bb8
AV		 1198
1199 return 0;
1200}
1201
1202static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1203{
1c1b5228 1204 mlx5_cqwq_destroy(&cq->wq_ctrl);
f62b8bb8
AV		 1205}
1206
1207static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1208{
50cfa25a 1209 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1210 struct mlx5_core_dev *mdev = priv->mdev;
1211 struct mlx5_core_cq *mcq = &cq->mcq;
1212
1213 void *in;
1214 void *cqc;
1215 int inlen;
0b6e26ce 1216 unsigned int irqn_not_used;
f62b8bb8
AV		 1217 int eqn;
1218 int err;
1219
1220 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1c1b5228 1221 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
f62b8bb8
AV		 1222 in = mlx5_vzalloc(inlen);
1223 if (!in)
1224 return -ENOMEM;
1225
1226 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1227
1228 memcpy(cqc, param->cqc, sizeof(param->cqc));
1229
1c1b5228
TT		 1230 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1231 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
f62b8bb8
AV		 1232
1233 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1234
9908aa29 1235 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
f62b8bb8
AV		 1236 MLX5_SET(cqc, cqc, c_eqn, eqn);
1237 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1c1b5228 1238 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
68cdf5d6 1239 MLX5_ADAPTER_PAGE_SHIFT);
f62b8bb8
AV		 1240 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1241
1242 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1243
1244 kvfree(in);
1245
1246 if (err)
1247 return err;
1248
1249 mlx5e_cq_arm(cq);
1250
1251 return 0;
1252}
1253
1254static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1255{
50cfa25a 1256 struct mlx5e_priv *priv = cq->priv;
f62b8bb8
AV		 1257 struct mlx5_core_dev *mdev = priv->mdev;
1258
1259 mlx5_core_destroy_cq(mdev, &cq->mcq);
1260}
1261
1262static int mlx5e_open_cq(struct mlx5e_channel *c,
1263 struct mlx5e_cq_param *param,
1264 struct mlx5e_cq *cq,
9908aa29 1265 struct mlx5e_cq_moder moderation)
f62b8bb8
AV		 1266{
1267 int err;
1268 struct mlx5e_priv *priv = c->priv;
1269 struct mlx5_core_dev *mdev = priv->mdev;
1270
1271 err = mlx5e_create_cq(c, param, cq);
1272 if (err)
1273 return err;
1274
1275 err = mlx5e_enable_cq(cq, param);
1276 if (err)
1277 goto err_destroy_cq;
1278
7524a5d8
GP		 1279 if (MLX5_CAP_GEN(mdev, cq_moderation))
1280 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
9908aa29
TT		 1281 moderation.usec,
1282 moderation.pkts);
f62b8bb8
AV		 1283 return 0;
1284
1285err_destroy_cq:
1286 mlx5e_destroy_cq(cq);
1287
1288 return err;
1289}
1290
1291static void mlx5e_close_cq(struct mlx5e_cq *cq)
1292{
1293 mlx5e_disable_cq(cq);
1294 mlx5e_destroy_cq(cq);
1295}
1296
1297static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1298{
1299 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1300}
1301
1302static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1303 struct mlx5e_channel_param *cparam)
1304{
1305 struct mlx5e_priv *priv = c->priv;
1306 int err;
1307 int tc;
1308
1309 for (tc = 0; tc < c->num_tc; tc++) {
1310 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
9908aa29 1311 priv->params.tx_cq_moderation);
f62b8bb8
AV		 1312 if (err)
1313 goto err_close_tx_cqs;
f62b8bb8
AV		 1314 }
1315
1316 return 0;
1317
1318err_close_tx_cqs:
1319 for (tc--; tc >= 0; tc--)
1320 mlx5e_close_cq(&c->sq[tc].cq);
1321
1322 return err;
1323}
1324
1325static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1326{
1327 int tc;
1328
1329 for (tc = 0; tc < c->num_tc; tc++)
1330 mlx5e_close_cq(&c->sq[tc].cq);
1331}
1332
1333static int mlx5e_open_sqs(struct mlx5e_channel *c,
1334 struct mlx5e_channel_param *cparam)
1335{
1336 int err;
1337 int tc;
1338
1339 for (tc = 0; tc < c->num_tc; tc++) {
1340 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1341 if (err)
1342 goto err_close_sqs;
1343 }
1344
1345 return 0;
1346
1347err_close_sqs:
1348 for (tc--; tc >= 0; tc--)
1349 mlx5e_close_sq(&c->sq[tc]);
1350
1351 return err;
1352}
1353
1354static void mlx5e_close_sqs(struct mlx5e_channel *c)
1355{
1356 int tc;
1357
1358 for (tc = 0; tc < c->num_tc; tc++)
1359 mlx5e_close_sq(&c->sq[tc]);
1360}
1361
5283af89 1362static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
03289b88
SM		 1363{
1364 int i;
1365
6bfd390b 1366 for (i = 0; i < priv->profile->max_tc; i++)
5283af89
RS		 1367 priv->channeltc_to_txq_map[ix][i] =
1368 ix + i * priv->params.num_channels;
03289b88
SM		 1369}
1370
507f0c81
YP		 1371static int mlx5e_set_sq_maxrate(struct net_device *dev,
1372 struct mlx5e_sq *sq, u32 rate)
1373{
1374 struct mlx5e_priv *priv = netdev_priv(dev);
1375 struct mlx5_core_dev *mdev = priv->mdev;
1376 u16 rl_index = 0;
1377 int err;
1378
1379 if (rate == sq->rate_limit)
1380 /* nothing to do */
1381 return 0;
1382
1383 if (sq->rate_limit)
1384 /* remove current rl index to free space to next ones */
1385 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1386
1387 sq->rate_limit = 0;
1388
1389 if (rate) {
1390 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1391 if (err) {
1392 netdev_err(dev, "Failed configuring rate %u: %d\n",
1393 rate, err);
1394 return err;
1395 }
1396 }
1397
1398 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1399 MLX5_SQC_STATE_RDY, true, rl_index);
1400 if (err) {
1401 netdev_err(dev, "Failed configuring rate %u: %d\n",
1402 rate, err);
1403 /* remove the rate from the table */
1404 if (rate)
1405 mlx5_rl_remove_rate(mdev, rate);
1406 return err;
1407 }
1408
1409 sq->rate_limit = rate;
1410 return 0;
1411}
1412
1413static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1414{
1415 struct mlx5e_priv *priv = netdev_priv(dev);
1416 struct mlx5_core_dev *mdev = priv->mdev;
1417 struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1418 int err = 0;
1419
1420 if (!mlx5_rl_is_supported(mdev)) {
1421 netdev_err(dev, "Rate limiting is not supported on this device\n");
1422 return -EINVAL;
1423 }
1424
1425 /* rate is given in Mb/sec, HW config is in Kb/sec */
1426 rate = rate << 10;
1427
1428 /* Check whether rate in valid range, 0 is always valid */
1429 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1430 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1431 return -ERANGE;
1432 }
1433
1434 mutex_lock(&priv->state_lock);
1435 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1436 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1437 if (!err)
1438 priv->tx_rates[index] = rate;
1439 mutex_unlock(&priv->state_lock);
1440
1441 return err;
1442}
1443
f62b8bb8
AV		 1444static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1445 struct mlx5e_channel_param *cparam,
1446 struct mlx5e_channel **cp)
1447{
9908aa29 1448 struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
f62b8bb8 1449 struct net_device *netdev = priv->netdev;
cb3c7fd4 1450 struct mlx5e_cq_moder rx_cq_profile;
f62b8bb8
AV		 1451 int cpu = mlx5e_get_cpu(priv, ix);
1452 struct mlx5e_channel *c;
507f0c81 1453 struct mlx5e_sq *sq;
f62b8bb8 1454 int err;
507f0c81 1455 int i;
f62b8bb8
AV		 1456
1457 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1458 if (!c)
1459 return -ENOMEM;
1460
1461 c->priv = priv;
1462 c->ix = ix;
1463 c->cpu = cpu;
1464 c->pdev = &priv->mdev->pdev->dev;
1465 c->netdev = priv->netdev;
b50d292b 1466 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
a4418a6c 1467 c->num_tc = priv->params.num_tc;
d7a0ecab 1468 c->xdp = !!priv->xdp_prog;
f62b8bb8 1469
cb3c7fd4
GR		 1470 if (priv->params.rx_am_enabled)
1471 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1472 else
1473 rx_cq_profile = priv->params.rx_cq_moderation;
1474
5283af89 1475 mlx5e_build_channeltc_to_txq_map(priv, ix);
03289b88 1476
f62b8bb8
AV		 1477 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1478
9908aa29 1479 err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
f62b8bb8
AV		 1480 if (err)
1481 goto err_napi_del;
1482
d3c9bc27
TT		 1483 err = mlx5e_open_tx_cqs(c, cparam);
1484 if (err)
1485 goto err_close_icosq_cq;
1486
f62b8bb8 1487 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
cb3c7fd4 1488 rx_cq_profile);
f62b8bb8
AV		 1489 if (err)
1490 goto err_close_tx_cqs;
f62b8bb8 1491
d7a0ecab
SM		 1492 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1493 err = c->xdp ? mlx5e_open_cq(c, &cparam->tx_cq, &c->xdp_sq.cq,
1494 priv->params.tx_cq_moderation) : 0;
1495 if (err)
1496 goto err_close_rx_cq;
1497
f62b8bb8
AV		 1498 napi_enable(&c->napi);
1499
d3c9bc27 1500 err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
f62b8bb8
AV		 1501 if (err)
1502 goto err_disable_napi;
1503
d3c9bc27
TT		 1504 err = mlx5e_open_sqs(c, cparam);
1505 if (err)
1506 goto err_close_icosq;
1507
507f0c81
YP		 1508 for (i = 0; i < priv->params.num_tc; i++) {
1509 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1510
1511 if (priv->tx_rates[txq_ix]) {
1512 sq = priv->txq_to_sq_map[txq_ix];
1513 mlx5e_set_sq_maxrate(priv->netdev, sq,
1514 priv->tx_rates[txq_ix]);
1515 }
1516 }
1517
d7a0ecab
SM		 1518 err = c->xdp ? mlx5e_open_sq(c, 0, &cparam->xdp_sq, &c->xdp_sq) : 0;
1519 if (err)
1520 goto err_close_sqs;
b5503b99 1521
f62b8bb8
AV		 1522 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1523 if (err)
b5503b99 1524 goto err_close_xdp_sq;
f62b8bb8
AV		 1525
1526 netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1527 *cp = c;
1528
1529 return 0;
b5503b99 1530err_close_xdp_sq:
d7a0ecab 1531 if (c->xdp)
87dc0255 1532 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8
AV		 1533
1534err_close_sqs:
1535 mlx5e_close_sqs(c);
1536
d3c9bc27
TT		 1537err_close_icosq:
1538 mlx5e_close_sq(&c->icosq);
1539
f62b8bb8
AV		 1540err_disable_napi:
1541 napi_disable(&c->napi);
d7a0ecab
SM		 1542 if (c->xdp)
1543 mlx5e_close_cq(&c->xdp_sq.cq);
1544
1545err_close_rx_cq:
f62b8bb8
AV		 1546 mlx5e_close_cq(&c->rq.cq);
1547
1548err_close_tx_cqs:
1549 mlx5e_close_tx_cqs(c);
1550
d3c9bc27
TT		 1551err_close_icosq_cq:
1552 mlx5e_close_cq(&c->icosq.cq);
1553
f62b8bb8
AV		 1554err_napi_del:
1555 netif_napi_del(&c->napi);
1556 kfree(c);
1557
1558 return err;
1559}
1560
1561static void mlx5e_close_channel(struct mlx5e_channel *c)
1562{
1563 mlx5e_close_rq(&c->rq);
b5503b99
SM		 1564 if (c->xdp)
1565 mlx5e_close_sq(&c->xdp_sq);
f62b8bb8 1566 mlx5e_close_sqs(c);
d3c9bc27 1567 mlx5e_close_sq(&c->icosq);
f62b8bb8 1568 napi_disable(&c->napi);
b5503b99
SM		 1569 if (c->xdp)
1570 mlx5e_close_cq(&c->xdp_sq.cq);
f62b8bb8
AV		 1571 mlx5e_close_cq(&c->rq.cq);
1572 mlx5e_close_tx_cqs(c);
d3c9bc27 1573 mlx5e_close_cq(&c->icosq.cq);
f62b8bb8 1574 netif_napi_del(&c->napi);
7ae92ae5 1575
f62b8bb8
AV		 1576 kfree(c);
1577}
1578
1579static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1580 struct mlx5e_rq_param *param)
1581{
1582 void *rqc = param->rqc;
1583 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1584
461017cb
TT		 1585 switch (priv->params.rq_wq_type) {
1586 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1587 MLX5_SET(wq, wq, log_wqe_num_of_strides,
d9d9f156 1588 priv->params.mpwqe_log_num_strides - 9);
461017cb 1589 MLX5_SET(wq, wq, log_wqe_stride_size,
d9d9f156 1590 priv->params.mpwqe_log_stride_sz - 6);
461017cb
TT		 1591 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1592 break;
1593 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1594 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1595 }
1596
f62b8bb8
AV		 1597 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1598 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1599 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
b50d292b 1600 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
593cf338 1601 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
f62b8bb8 1602
311c7c71 1603 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
f62b8bb8 1604 param->wq.linear = 1;
cb3c7fd4
GR		 1605
1606 param->am_enabled = priv->params.rx_am_enabled;
f62b8bb8
AV		 1607}
1608
556dd1b9
TT		 1609static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1610{
1611 void *rqc = param->rqc;
1612 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1613
1614 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1615 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1616}
1617
d3c9bc27
TT		 1618static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1619 struct mlx5e_sq_param *param)
f62b8bb8
AV		 1620{
1621 void *sqc = param->sqc;
1622 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1623
f62b8bb8 1624 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
b50d292b 1625 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
f62b8bb8 1626
311c7c71 1627 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
d3c9bc27
TT		 1628}
1629
1630static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1631 struct mlx5e_sq_param *param)
1632{
1633 void *sqc = param->sqc;
1634 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1635
1636 mlx5e_build_sq_param_common(priv, param);
1637 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1638
58d52291 1639 param->max_inline = priv->params.tx_max_inline;
cff92d7c 1640 param->min_inline_mode = priv->params.tx_min_inline_mode;
f10b7cc7 1641 param->type = MLX5E_SQ_TXQ;
f62b8bb8
AV		 1642}
1643
1644static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1645 struct mlx5e_cq_param *param)
1646{
1647 void *cqc = param->cqc;
1648
b50d292b 1649 MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
f62b8bb8
AV		 1650}
1651
1652static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1653 struct mlx5e_cq_param *param)
1654{
1655 void *cqc = param->cqc;
461017cb 1656 u8 log_cq_size;
f62b8bb8 1657
461017cb
TT		 1658 switch (priv->params.rq_wq_type) {
1659 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1660 log_cq_size = priv->params.log_rq_size +
d9d9f156 1661 priv->params.mpwqe_log_num_strides;
461017cb
TT		 1662 break;
1663 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1664 log_cq_size = priv->params.log_rq_size;
1665 }
1666
1667 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
9bcc8606 1668 if (MLX5E_GET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
7219ab34
TT		 1669 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1670 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1671 }
f62b8bb8
AV		 1672
1673 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1674
1675 param->cq_period_mode = priv->params.rx_cq_period_mode;
f62b8bb8
AV		 1676}
1677
1678static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1679 struct mlx5e_cq_param *param)
1680{
1681 void *cqc = param->cqc;
1682
d3c9bc27 1683 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
f62b8bb8
AV		 1684
1685 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1686
1687 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8
AV		 1688}
1689
d3c9bc27
TT		 1690static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1691 struct mlx5e_cq_param *param,
1692 u8 log_wq_size)
1693{
1694 void *cqc = param->cqc;
1695
1696 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1697
1698 mlx5e_build_common_cq_param(priv, param);
9908aa29
TT		 1699
1700 param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
d3c9bc27
TT		 1701}
1702
1703static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1704 struct mlx5e_sq_param *param,
1705 u8 log_wq_size)
1706{
1707 void *sqc = param->sqc;
1708 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1709
1710 mlx5e_build_sq_param_common(priv, param);
1711
1712 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
bc77b240 1713 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
d3c9bc27 1714
f10b7cc7 1715 param->type = MLX5E_SQ_ICO;
d3c9bc27
TT		 1716}
1717
b5503b99
SM		 1718static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
1719 struct mlx5e_sq_param *param)
1720{
1721 void *sqc = param->sqc;
1722 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1723
1724 mlx5e_build_sq_param_common(priv, param);
1725 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1726
1727 param->max_inline = priv->params.tx_max_inline;
1728 /* FOR XDP SQs will support only L2 inline mode */
1729 param->min_inline_mode = MLX5_INLINE_MODE_NONE;
1730 param->type = MLX5E_SQ_XDP;
1731}
1732
6b87663f 1733static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
f62b8bb8 1734{
bc77b240 1735 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
d3c9bc27 1736
f62b8bb8
AV		 1737 mlx5e_build_rq_param(priv, &cparam->rq);
1738 mlx5e_build_sq_param(priv, &cparam->sq);
b5503b99 1739 mlx5e_build_xdpsq_param(priv, &cparam->xdp_sq);
d3c9bc27 1740 mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
f62b8bb8
AV		 1741 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1742 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
d3c9bc27 1743 mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
f62b8bb8
AV		 1744}
1745
1746static int mlx5e_open_channels(struct mlx5e_priv *priv)
1747{
6b87663f 1748 struct mlx5e_channel_param *cparam;
a4418a6c 1749 int nch = priv->params.num_channels;
03289b88 1750 int err = -ENOMEM;
f62b8bb8
AV		 1751 int i;
1752 int j;
1753
a4418a6c
AS		 1754 priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1755 GFP_KERNEL);
03289b88 1756
a4418a6c 1757 priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
03289b88
SM		 1758 sizeof(struct mlx5e_sq *), GFP_KERNEL);
1759
6b87663f
AB		 1760 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1761
1762 if (!priv->channel || !priv->txq_to_sq_map || !cparam)
03289b88 1763 goto err_free_txq_to_sq_map;
f62b8bb8 1764
6b87663f
AB		 1765 mlx5e_build_channel_param(priv, cparam);
1766
a4418a6c 1767 for (i = 0; i < nch; i++) {
6b87663f 1768 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
f62b8bb8
AV		 1769 if (err)
1770 goto err_close_channels;
1771 }
1772
a4418a6c 1773 for (j = 0; j < nch; j++) {
f62b8bb8
AV		 1774 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1775 if (err)
1776 goto err_close_channels;
1777 }
1778
c3b7c5c9
MHY		 1779 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1780 * polling for inactive tx queues.
1781 */
1782 netif_tx_start_all_queues(priv->netdev);
1783
6b87663f 1784 kfree(cparam);
f62b8bb8
AV		 1785 return 0;
1786
1787err_close_channels:
1788 for (i--; i >= 0; i--)
1789 mlx5e_close_channel(priv->channel[i]);
1790
03289b88
SM		 1791err_free_txq_to_sq_map:
1792 kfree(priv->txq_to_sq_map);
f62b8bb8 1793 kfree(priv->channel);
6b87663f 1794 kfree(cparam);
f62b8bb8
AV		 1795
1796 return err;
1797}
1798
1799static void mlx5e_close_channels(struct mlx5e_priv *priv)
1800{
1801 int i;
1802
c3b7c5c9
MHY		 1803 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1804 * polling for inactive tx queues.
1805 */
1806 netif_tx_stop_all_queues(priv->netdev);
1807 netif_tx_disable(priv->netdev);
1808
f62b8bb8
AV		 1809 for (i = 0; i < priv->params.num_channels; i++)
1810 mlx5e_close_channel(priv->channel[i]);
1811
03289b88 1812 kfree(priv->txq_to_sq_map);
f62b8bb8
AV		 1813 kfree(priv->channel);
1814}
1815
2be6967c
SM		 1816static int mlx5e_rx_hash_fn(int hfunc)
1817{
1818 return (hfunc == ETH_RSS_HASH_TOP) ?
1819 MLX5_RX_HASH_FN_TOEPLITZ :
1820 MLX5_RX_HASH_FN_INVERTED_XOR8;
1821}
1822
1823static int mlx5e_bits_invert(unsigned long a, int size)
1824{
1825 int inv = 0;
1826 int i;
1827
1828 for (i = 0; i < size; i++)
1829 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1830
1831 return inv;
1832}
1833
936896e9
AS		 1834static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1835{
1836 int i;
1837
1838 for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1839 int ix = i;
1da36696 1840 u32 rqn;
936896e9
AS		 1841
1842 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1843 ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1844
2d75b2bc 1845 ix = priv->params.indirection_rqt[ix];
1da36696
TT		 1846 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1847 priv->channel[ix]->rq.rqn :
1848 priv->drop_rq.rqn;
1849 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
936896e9
AS		 1850 }
1851}
1852
1da36696
TT		 1853static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1854 int ix)
4cbeaff5 1855{
1da36696
TT		 1856 u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1857 priv->channel[ix]->rq.rqn :
1858 priv->drop_rq.rqn;
4cbeaff5 1859
1da36696 1860 MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
4cbeaff5
AS		 1861}
1862
398f3351
HHZ		 1863static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1864 int ix, struct mlx5e_rqt *rqt)
f62b8bb8
AV		 1865{
1866 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 1867 void *rqtc;
1868 int inlen;
1869 int err;
1da36696 1870 u32 *in;
f62b8bb8 1871
f62b8bb8
AV		 1872 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1873 in = mlx5_vzalloc(inlen);
1874 if (!in)
1875 return -ENOMEM;
1876
1877 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1878
1879 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1880 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1881
1da36696
TT		 1882 if (sz > 1) /* RSS */
1883 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1884 else
1885 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
2be6967c 1886
398f3351
HHZ		 1887 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1888 if (!err)
1889 rqt->enabled = true;
f62b8bb8
AV		 1890
1891 kvfree(in);
1da36696
TT		 1892 return err;
1893}
1894
cb67b832 1895void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1da36696 1896{
398f3351
HHZ		 1897 rqt->enabled = false;
1898 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1da36696
TT		 1899}
1900
6bfd390b
HHZ		 1901static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1902{
1903 struct mlx5e_rqt *rqt = &priv->indir_rqt;
1904
1905 return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1906}
1907
cb67b832 1908int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1da36696 1909{
398f3351 1910 struct mlx5e_rqt *rqt;
1da36696
TT		 1911 int err;
1912 int ix;
1913
6bfd390b 1914 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
398f3351
HHZ		 1915 rqt = &priv->direct_tir[ix].rqt;
1916 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1da36696
TT		 1917 if (err)
1918 goto err_destroy_rqts;
1919 }
1920
1921 return 0;
1922
1923err_destroy_rqts:
1924 for (ix--; ix >= 0; ix--)
398f3351 1925 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1da36696 1926
f62b8bb8
AV		 1927 return err;
1928}
1929
1da36696 1930int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
5c50368f
AS		 1931{
1932 struct mlx5_core_dev *mdev = priv->mdev;
5c50368f
AS		 1933 void *rqtc;
1934 int inlen;
1da36696 1935 u32 *in;
5c50368f
AS		 1936 int err;
1937
5c50368f
AS		 1938 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1939 in = mlx5_vzalloc(inlen);
1940 if (!in)
1941 return -ENOMEM;
1942
1943 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1944
1945 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1da36696
TT		 1946 if (sz > 1) /* RSS */
1947 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1948 else
1949 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
5c50368f
AS		 1950
1951 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1952
1da36696 1953 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
5c50368f
AS		 1954
1955 kvfree(in);
1956
1957 return err;
1958}
1959
40ab6a6e
AS		 1960static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1961{
1da36696
TT		 1962 u32 rqtn;
1963 int ix;
1964
398f3351
HHZ		 1965 if (priv->indir_rqt.enabled) {
1966 rqtn = priv->indir_rqt.rqtn;
1967 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1968 }
1969
1da36696 1970 for (ix = 0; ix < priv->params.num_channels; ix++) {
398f3351
HHZ		 1971 if (!priv->direct_tir[ix].rqt.enabled)
1972 continue;
1973 rqtn = priv->direct_tir[ix].rqt.rqtn;
1da36696
TT		 1974 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1975 }
40ab6a6e
AS		 1976}
1977
5c50368f
AS		 1978static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1979{
1980 if (!priv->params.lro_en)
1981 return;
1982
1983#define ROUGH_MAX_L2_L3_HDR_SZ 256
1984
1985 MLX5_SET(tirc, tirc, lro_enable_mask,
1986 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1987 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1988 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1989 (priv->params.lro_wqe_sz -
1990 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2b029556 1991 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, priv->params.lro_timeout);
5c50368f
AS		 1992}
1993
bdfc028d
TT		 1994void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1995{
1996 MLX5_SET(tirc, tirc, rx_hash_fn,
1997 mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1998 if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1999 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2000 rx_hash_toeplitz_key);
2001 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2002 rx_hash_toeplitz_key);
2003
2004 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2005 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
2006 }
2007}
2008
ab0394fe 2009static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
5c50368f
AS		 2010{
2011 struct mlx5_core_dev *mdev = priv->mdev;
2012
2013 void *in;
2014 void *tirc;
2015 int inlen;
2016 int err;
ab0394fe 2017 int tt;
1da36696 2018 int ix;
5c50368f
AS		 2019
2020 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2021 in = mlx5_vzalloc(inlen);
2022 if (!in)
2023 return -ENOMEM;
2024
2025 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2026 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2027
2028 mlx5e_build_tir_ctx_lro(tirc, priv);
2029
1da36696 2030 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
724b2aa1 2031 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1da36696 2032 inlen);
ab0394fe 2033 if (err)
1da36696 2034 goto free_in;
ab0394fe 2035 }
5c50368f 2036
6bfd390b 2037 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1da36696
TT		 2038 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2039 in, inlen);
2040 if (err)
2041 goto free_in;
2042 }
2043
2044free_in:
5c50368f
AS		 2045 kvfree(in);
2046
2047 return err;
2048}
2049
cd255eff 2050static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
40ab6a6e 2051{
40ab6a6e 2052 struct mlx5_core_dev *mdev = priv->mdev;
cd255eff 2053 u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
40ab6a6e
AS		 2054 int err;
2055
cd255eff 2056 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
40ab6a6e
AS		 2057 if (err)
2058 return err;
2059
cd255eff
SM		 2060 /* Update vport context MTU */
2061 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2062 return 0;
2063}
40ab6a6e 2064
cd255eff
SM		 2065static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
2066{
2067 struct mlx5_core_dev *mdev = priv->mdev;
2068 u16 hw_mtu = 0;
2069 int err;
40ab6a6e 2070
cd255eff
SM		 2071 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2072 if (err || !hw_mtu) /* fallback to port oper mtu */
2073 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2074
2075 *mtu = MLX5E_HW2SW_MTU(hw_mtu);
2076}
2077
2078static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
2079{
2080 struct mlx5e_priv *priv = netdev_priv(netdev);
2081 u16 mtu;
2082 int err;
2083
2084 err = mlx5e_set_mtu(priv, netdev->mtu);
2085 if (err)
2086 return err;
40ab6a6e 2087
cd255eff
SM		 2088 mlx5e_query_mtu(priv, &mtu);
2089 if (mtu != netdev->mtu)
2090 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2091 __func__, mtu, netdev->mtu);
40ab6a6e 2092
cd255eff 2093 netdev->mtu = mtu;
40ab6a6e
AS		 2094 return 0;
2095}
2096
08fb1dac
SM		 2097static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2098{
2099 struct mlx5e_priv *priv = netdev_priv(netdev);
2100 int nch = priv->params.num_channels;
2101 int ntc = priv->params.num_tc;
2102 int tc;
2103
2104 netdev_reset_tc(netdev);
2105
2106 if (ntc == 1)
2107 return;
2108
2109 netdev_set_num_tc(netdev, ntc);
2110
7ccdd084
RS		 2111 /* Map netdev TCs to offset 0
2112 * We have our own UP to TXQ mapping for QoS
2113 */
08fb1dac 2114 for (tc = 0; tc < ntc; tc++)
7ccdd084 2115 netdev_set_tc_queue(netdev, tc, nch, 0);
08fb1dac
SM		 2116}
2117
40ab6a6e
AS		 2118int mlx5e_open_locked(struct net_device *netdev)
2119{
2120 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2121 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e
AS		 2122 int num_txqs;
2123 int err;
2124
2125 set_bit(MLX5E_STATE_OPENED, &priv->state);
2126
08fb1dac
SM		 2127 mlx5e_netdev_set_tcs(netdev);
2128
40ab6a6e
AS		 2129 num_txqs = priv->params.num_channels * priv->params.num_tc;
2130 netif_set_real_num_tx_queues(netdev, num_txqs);
2131 netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
2132
40ab6a6e
AS		 2133 err = mlx5e_open_channels(priv);
2134 if (err) {
2135 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
2136 __func__, err);
343b29f3 2137 goto err_clear_state_opened_flag;
40ab6a6e
AS		 2138 }
2139
0952da79 2140 err = mlx5e_refresh_tirs_self_loopback(priv->mdev, false);
66189961
TT		 2141 if (err) {
2142 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2143 __func__, err);
2144 goto err_close_channels;
2145 }
2146
40ab6a6e 2147 mlx5e_redirect_rqts(priv);
ce89ef36 2148 mlx5e_update_carrier(priv);
ef9814de 2149 mlx5e_timestamp_init(priv);
5a7b27eb
MG		 2150#ifdef CONFIG_RFS_ACCEL
2151 priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
2152#endif
cb67b832
HHZ		 2153 if (priv->profile->update_stats)
2154 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
40ab6a6e 2155
cb67b832
HHZ		 2156 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2157 err = mlx5e_add_sqs_fwd_rules(priv);
2158 if (err)
2159 goto err_close_channels;
2160 }
9b37b07f 2161 return 0;
343b29f3 2162
66189961
TT		 2163err_close_channels:
2164 mlx5e_close_channels(priv);
343b29f3
AS		 2165err_clear_state_opened_flag:
2166 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2167 return err;
40ab6a6e
AS		 2168}
2169
cb67b832 2170int mlx5e_open(struct net_device *netdev)
40ab6a6e
AS		 2171{
2172 struct mlx5e_priv *priv = netdev_priv(netdev);
2173 int err;
2174
2175 mutex_lock(&priv->state_lock);
2176 err = mlx5e_open_locked(netdev);
2177 mutex_unlock(&priv->state_lock);
2178
2179 return err;
2180}
2181
2182int mlx5e_close_locked(struct net_device *netdev)
2183{
2184 struct mlx5e_priv *priv = netdev_priv(netdev);
cb67b832 2185 struct mlx5_core_dev *mdev = priv->mdev;
40ab6a6e 2186
a1985740
AS		 2187 /* May already be CLOSED in case a previous configuration operation
2188 * (e.g RX/TX queue size change) that involves close&open failed.
2189 */
2190 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2191 return 0;
2192
40ab6a6e
AS		 2193 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2194
cb67b832
HHZ		 2195 if (MLX5_CAP_GEN(mdev, vport_group_manager))
2196 mlx5e_remove_sqs_fwd_rules(priv);
2197
ef9814de 2198 mlx5e_timestamp_cleanup(priv);
40ab6a6e 2199 netif_carrier_off(priv->netdev);
ce89ef36 2200 mlx5e_redirect_rqts(priv);
40ab6a6e
AS		 2201 mlx5e_close_channels(priv);
2202
2203 return 0;
2204}
2205
cb67b832 2206int mlx5e_close(struct net_device *netdev)
40ab6a6e
AS		 2207{
2208 struct mlx5e_priv *priv = netdev_priv(netdev);
2209 int err;
2210
26e59d80
MHY		 2211 if (!netif_device_present(netdev))
2212 return -ENODEV;
2213
40ab6a6e
AS		 2214 mutex_lock(&priv->state_lock);
2215 err = mlx5e_close_locked(netdev);
2216 mutex_unlock(&priv->state_lock);
2217
2218 return err;
2219}
2220
2221static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2222 struct mlx5e_rq *rq,
2223 struct mlx5e_rq_param *param)
2224{
2225 struct mlx5_core_dev *mdev = priv->mdev;
2226 void *rqc = param->rqc;
2227 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2228 int err;
2229
2230 param->wq.db_numa_node = param->wq.buf_numa_node;
2231
2232 err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2233 &rq->wq_ctrl);
2234 if (err)
2235 return err;
2236
2237 rq->priv = priv;
2238
2239 return 0;
2240}
2241
2242static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2243 struct mlx5e_cq *cq,
2244 struct mlx5e_cq_param *param)
2245{
2246 struct mlx5_core_dev *mdev = priv->mdev;
2247 struct mlx5_core_cq *mcq = &cq->mcq;
2248 int eqn_not_used;
0b6e26ce 2249 unsigned int irqn;
40ab6a6e
AS		 2250 int err;
2251
2252 err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2253 &cq->wq_ctrl);
2254 if (err)
2255 return err;
2256
2257 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2258
2259 mcq->cqe_sz = 64;
2260 mcq->set_ci_db = cq->wq_ctrl.db.db;
2261 mcq->arm_db = cq->wq_ctrl.db.db + 1;
2262 *mcq->set_ci_db = 0;
2263 *mcq->arm_db = 0;
2264 mcq->vector = param->eq_ix;
2265 mcq->comp = mlx5e_completion_event;
2266 mcq->event = mlx5e_cq_error_event;
2267 mcq->irqn = irqn;
b50d292b 2268 mcq->uar = &mdev->mlx5e_res.cq_uar;
40ab6a6e
AS		 2269
2270 cq->priv = priv;
2271
2272 return 0;
2273}
2274
2275static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2276{
2277 struct mlx5e_cq_param cq_param;
2278 struct mlx5e_rq_param rq_param;
2279 struct mlx5e_rq *rq = &priv->drop_rq;
2280 struct mlx5e_cq *cq = &priv->drop_rq.cq;
2281 int err;
2282
2283 memset(&cq_param, 0, sizeof(cq_param));
2284 memset(&rq_param, 0, sizeof(rq_param));
556dd1b9 2285 mlx5e_build_drop_rq_param(&rq_param);
40ab6a6e
AS		 2286
2287 err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2288 if (err)
2289 return err;
2290
2291 err = mlx5e_enable_cq(cq, &cq_param);
2292 if (err)
2293 goto err_destroy_cq;
2294
2295 err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2296 if (err)
2297 goto err_disable_cq;
2298
2299 err = mlx5e_enable_rq(rq, &rq_param);
2300 if (err)
2301 goto err_destroy_rq;
2302
2303 return 0;
2304
2305err_destroy_rq:
2306 mlx5e_destroy_rq(&priv->drop_rq);
2307
2308err_disable_cq:
2309 mlx5e_disable_cq(&priv->drop_rq.cq);
2310
2311err_destroy_cq:
2312 mlx5e_destroy_cq(&priv->drop_rq.cq);
2313
2314 return err;
2315}
2316
2317static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2318{
2319 mlx5e_disable_rq(&priv->drop_rq);
2320 mlx5e_destroy_rq(&priv->drop_rq);
2321 mlx5e_disable_cq(&priv->drop_rq.cq);
2322 mlx5e_destroy_cq(&priv->drop_rq.cq);
2323}
2324
2325static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2326{
2327 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 2328 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
40ab6a6e
AS		 2329 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2330
08fb1dac 2331 MLX5_SET(tisc, tisc, prio, tc << 1);
b50d292b 2332 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
db60b802
AH		 2333
2334 if (mlx5_lag_is_lacp_owner(mdev))
2335 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2336
40ab6a6e
AS		 2337 return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2338}
2339
2340static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2341{
2342 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2343}
2344
cb67b832 2345int mlx5e_create_tises(struct mlx5e_priv *priv)
40ab6a6e
AS		 2346{
2347 int err;
2348 int tc;
2349
6bfd390b 2350 for (tc = 0; tc < priv->profile->max_tc; tc++) {
40ab6a6e
AS		 2351 err = mlx5e_create_tis(priv, tc);
2352 if (err)
2353 goto err_close_tises;
2354 }
2355
2356 return 0;
2357
2358err_close_tises:
2359 for (tc--; tc >= 0; tc--)
2360 mlx5e_destroy_tis(priv, tc);
2361
2362 return err;
2363}
2364
cb67b832 2365void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
40ab6a6e
AS		 2366{
2367 int tc;
2368
6bfd390b 2369 for (tc = 0; tc < priv->profile->max_tc; tc++)
40ab6a6e
AS		 2370 mlx5e_destroy_tis(priv, tc);
2371}
2372
1da36696
TT		 2373static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2374 enum mlx5e_traffic_types tt)
f62b8bb8
AV		 2375{
2376 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2377
b50d292b 2378 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
3191e05f 2379
5a6f8aef
AS		 2380#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2381 MLX5_HASH_FIELD_SEL_DST_IP)
f62b8bb8 2382
5a6f8aef
AS		 2383#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2384 MLX5_HASH_FIELD_SEL_DST_IP |\
2385 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2386 MLX5_HASH_FIELD_SEL_L4_DPORT)
f62b8bb8 2387
a741749f
AS		 2388#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2389 MLX5_HASH_FIELD_SEL_DST_IP |\
2390 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2391
5c50368f 2392 mlx5e_build_tir_ctx_lro(tirc, priv);
f62b8bb8 2393
4cbeaff5 2394 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
398f3351 2395 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
1da36696 2396 mlx5e_build_tir_ctx_hash(tirc, priv);
f62b8bb8
AV		 2397
2398 switch (tt) {
2399 case MLX5E_TT_IPV4_TCP:
2400 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2401 MLX5_L3_PROT_TYPE_IPV4);
2402 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2403 MLX5_L4_PROT_TYPE_TCP);
2404 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2405 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2406 break;
2407
2408 case MLX5E_TT_IPV6_TCP:
2409 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2410 MLX5_L3_PROT_TYPE_IPV6);
2411 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2412 MLX5_L4_PROT_TYPE_TCP);
2413 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2414 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2415 break;
2416
2417 case MLX5E_TT_IPV4_UDP:
2418 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2419 MLX5_L3_PROT_TYPE_IPV4);
2420 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2421 MLX5_L4_PROT_TYPE_UDP);
2422 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2423 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2424 break;
2425
2426 case MLX5E_TT_IPV6_UDP:
2427 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2428 MLX5_L3_PROT_TYPE_IPV6);
2429 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2430 MLX5_L4_PROT_TYPE_UDP);
2431 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
5a6f8aef 2432 MLX5_HASH_IP_L4PORTS);
f62b8bb8
AV		 2433 break;
2434
a741749f
AS		 2435 case MLX5E_TT_IPV4_IPSEC_AH:
2436 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2437 MLX5_L3_PROT_TYPE_IPV4);
2438 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2439 MLX5_HASH_IP_IPSEC_SPI);
2440 break;
2441
2442 case MLX5E_TT_IPV6_IPSEC_AH:
2443 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444 MLX5_L3_PROT_TYPE_IPV6);
2445 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2446 MLX5_HASH_IP_IPSEC_SPI);
2447 break;
2448
2449 case MLX5E_TT_IPV4_IPSEC_ESP:
2450 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2451 MLX5_L3_PROT_TYPE_IPV4);
2452 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2453 MLX5_HASH_IP_IPSEC_SPI);
2454 break;
2455
2456 case MLX5E_TT_IPV6_IPSEC_ESP:
2457 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2458 MLX5_L3_PROT_TYPE_IPV6);
2459 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2460 MLX5_HASH_IP_IPSEC_SPI);
2461 break;
2462
f62b8bb8
AV		 2463 case MLX5E_TT_IPV4:
2464 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2465 MLX5_L3_PROT_TYPE_IPV4);
2466 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2467 MLX5_HASH_IP);
2468 break;
2469
2470 case MLX5E_TT_IPV6:
2471 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2472 MLX5_L3_PROT_TYPE_IPV6);
2473 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2474 MLX5_HASH_IP);
2475 break;
1da36696
TT		 2476 default:
2477 WARN_ONCE(true,
2478 "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
f62b8bb8
AV		 2479 }
2480}
2481
1da36696
TT		 2482static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2483 u32 rqtn)
f62b8bb8 2484{
b50d292b 2485 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
1da36696
TT		 2486
2487 mlx5e_build_tir_ctx_lro(tirc, priv);
2488
2489 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2490 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2491 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2492}
2493
6bfd390b 2494static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
1da36696 2495{
724b2aa1 2496 struct mlx5e_tir *tir;
f62b8bb8
AV		 2497 void *tirc;
2498 int inlen;
2499 int err;
1da36696 2500 u32 *in;
1da36696 2501 int tt;
f62b8bb8
AV		 2502
2503 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2504 in = mlx5_vzalloc(inlen);
2505 if (!in)
2506 return -ENOMEM;
2507
1da36696
TT		 2508 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2509 memset(in, 0, inlen);
724b2aa1 2510 tir = &priv->indir_tir[tt];
1da36696
TT		 2511 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2512 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
724b2aa1 2513 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
f62b8bb8 2514 if (err)
40ab6a6e 2515 goto err_destroy_tirs;
f62b8bb8
AV		 2516 }
2517
6bfd390b
HHZ		 2518 kvfree(in);
2519
2520 return 0;
2521
2522err_destroy_tirs:
2523 for (tt--; tt >= 0; tt--)
2524 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2525
2526 kvfree(in);
2527
2528 return err;
2529}
2530
cb67b832 2531int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2532{
2533 int nch = priv->profile->max_nch(priv->mdev);
2534 struct mlx5e_tir *tir;
2535 void *tirc;
2536 int inlen;
2537 int err;
2538 u32 *in;
2539 int ix;
2540
2541 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2542 in = mlx5_vzalloc(inlen);
2543 if (!in)
2544 return -ENOMEM;
2545
1da36696
TT		 2546 for (ix = 0; ix < nch; ix++) {
2547 memset(in, 0, inlen);
724b2aa1 2548 tir = &priv->direct_tir[ix];
1da36696
TT		 2549 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2550 mlx5e_build_direct_tir_ctx(priv, tirc,
398f3351 2551 priv->direct_tir[ix].rqt.rqtn);
724b2aa1 2552 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
1da36696
TT		 2553 if (err)
2554 goto err_destroy_ch_tirs;
2555 }
2556
2557 kvfree(in);
2558
f62b8bb8
AV		 2559 return 0;
2560
1da36696
TT		 2561err_destroy_ch_tirs:
2562 for (ix--; ix >= 0; ix--)
724b2aa1 2563 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
1da36696 2564
1da36696 2565 kvfree(in);
f62b8bb8
AV		 2566
2567 return err;
2568}
2569
6bfd390b 2570static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
f62b8bb8
AV		 2571{
2572 int i;
2573
1da36696 2574 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
724b2aa1 2575 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
f62b8bb8
AV		 2576}
2577
cb67b832 2578void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
6bfd390b
HHZ		 2579{
2580 int nch = priv->profile->max_nch(priv->mdev);
2581 int i;
2582
2583 for (i = 0; i < nch; i++)
2584 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2585}
2586
36350114
GP		 2587int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2588{
2589 int err = 0;
2590 int i;
2591
2592 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2593 return 0;
2594
2595 for (i = 0; i < priv->params.num_channels; i++) {
2596 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2597 if (err)
2598 return err;
2599 }
2600
2601 return 0;
2602}
2603
08fb1dac
SM		 2604static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2605{
2606 struct mlx5e_priv *priv = netdev_priv(netdev);
2607 bool was_opened;
2608 int err = 0;
2609
2610 if (tc && tc != MLX5E_MAX_NUM_TC)
2611 return -EINVAL;
2612
2613 mutex_lock(&priv->state_lock);
2614
2615 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2616 if (was_opened)
2617 mlx5e_close_locked(priv->netdev);
2618
2619 priv->params.num_tc = tc ? tc : 1;
2620
2621 if (was_opened)
2622 err = mlx5e_open_locked(priv->netdev);
2623
2624 mutex_unlock(&priv->state_lock);
2625
2626 return err;
2627}
2628
2629static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2630 __be16 proto, struct tc_to_netdev *tc)
2631{
e8f887ac
AV		 2632 struct mlx5e_priv *priv = netdev_priv(dev);
2633
2634 if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2635 goto mqprio;
2636
2637 switch (tc->type) {
e3a2b7ed
AV		 2638 case TC_SETUP_CLSFLOWER:
2639 switch (tc->cls_flower->command) {
2640 case TC_CLSFLOWER_REPLACE:
2641 return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2642 case TC_CLSFLOWER_DESTROY:
2643 return mlx5e_delete_flower(priv, tc->cls_flower);
aad7e08d
AV		 2644 case TC_CLSFLOWER_STATS:
2645 return mlx5e_stats_flower(priv, tc->cls_flower);
e3a2b7ed 2646 }
e8f887ac
AV		 2647 default:
2648 return -EOPNOTSUPP;
2649 }
2650
2651mqprio:
67ba422e 2652 if (tc->type != TC_SETUP_MQPRIO)
08fb1dac
SM		 2653 return -EINVAL;
2654
2655 return mlx5e_setup_tc(dev, tc->tc);
2656}
2657
370bad0f 2658static struct rtnl_link_stats64 *
f62b8bb8
AV		 2659mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2660{
2661 struct mlx5e_priv *priv = netdev_priv(dev);
9218b44d 2662 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
f62b8bb8 2663 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
269e6b3a 2664 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
f62b8bb8 2665
370bad0f
OG		 2666 if (mlx5e_is_uplink_rep(priv)) {
2667 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
2668 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
2669 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
2670 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
2671 } else {
2672 stats->rx_packets = sstats->rx_packets;
2673 stats->rx_bytes = sstats->rx_bytes;
2674 stats->tx_packets = sstats->tx_packets;
2675 stats->tx_bytes = sstats->tx_bytes;
2676 stats->tx_dropped = sstats->tx_queue_dropped;
2677 }
269e6b3a
GP		 2678
2679 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
269e6b3a
GP		 2680
2681 stats->rx_length_errors =
9218b44d
GP		 2682 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2683 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2684 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
269e6b3a 2685 stats->rx_crc_errors =
9218b44d
GP		 2686 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2687 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2688 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
269e6b3a 2689 stats->tx_carrier_errors =
9218b44d 2690 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
269e6b3a
GP		 2691 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2692 stats->rx_frame_errors;
2693 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2694
2695 /* vport multicast also counts packets that are dropped due to steering
2696 * or rx out of buffer
2697 */
9218b44d
GP		 2698 stats->multicast =
2699 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
f62b8bb8
AV		 2700
2701 return stats;
2702}
2703
2704static void mlx5e_set_rx_mode(struct net_device *dev)
2705{
2706 struct mlx5e_priv *priv = netdev_priv(dev);
2707
7bb29755 2708 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2709}
2710
2711static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2712{
2713 struct mlx5e_priv *priv = netdev_priv(netdev);
2714 struct sockaddr *saddr = addr;
2715
2716 if (!is_valid_ether_addr(saddr->sa_data))
2717 return -EADDRNOTAVAIL;
2718
2719 netif_addr_lock_bh(netdev);
2720 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2721 netif_addr_unlock_bh(netdev);
2722
7bb29755 2723 queue_work(priv->wq, &priv->set_rx_mode_work);
f62b8bb8
AV		 2724
2725 return 0;
2726}
2727
0e405443
GP		 2728#define MLX5E_SET_FEATURE(netdev, feature, enable) \
2729 do { \
2730 if (enable) \
2731 netdev->features |= feature; \
2732 else \
2733 netdev->features &= ~feature; \
2734 } while (0)
2735
2736typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2737
2738static int set_feature_lro(struct net_device *netdev, bool enable)
f62b8bb8
AV		 2739{
2740 struct mlx5e_priv *priv = netdev_priv(netdev);
0e405443
GP		 2741 bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2742 int err;
f62b8bb8
AV		 2743
2744 mutex_lock(&priv->state_lock);
f62b8bb8 2745
0e405443
GP		 2746 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2747 mlx5e_close_locked(priv->netdev);
98e81b0a 2748
0e405443
GP		 2749 priv->params.lro_en = enable;
2750 err = mlx5e_modify_tirs_lro(priv);
2751 if (err) {
2752 netdev_err(netdev, "lro modify failed, %d\n", err);
2753 priv->params.lro_en = !enable;
98e81b0a 2754 }
f62b8bb8 2755
0e405443
GP		 2756 if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2757 mlx5e_open_locked(priv->netdev);
2758
9b37b07f
AS		 2759 mutex_unlock(&priv->state_lock);
2760
0e405443
GP		 2761 return err;
2762}
2763
2764static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2765{
2766 struct mlx5e_priv *priv = netdev_priv(netdev);
2767
2768 if (enable)
2769 mlx5e_enable_vlan_filter(priv);
2770 else
2771 mlx5e_disable_vlan_filter(priv);
2772
2773 return 0;
2774}
2775
2776static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2777{
2778 struct mlx5e_priv *priv = netdev_priv(netdev);
f62b8bb8 2779
0e405443 2780 if (!enable && mlx5e_tc_num_filters(priv)) {
e8f887ac
AV		 2781 netdev_err(netdev,
2782 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2783 return -EINVAL;
2784 }
2785
0e405443
GP		 2786 return 0;
2787}
2788
94cb1ebb
EBE		 2789static int set_feature_rx_all(struct net_device *netdev, bool enable)
2790{
2791 struct mlx5e_priv *priv = netdev_priv(netdev);
2792 struct mlx5_core_dev *mdev = priv->mdev;
2793
2794 return mlx5_set_port_fcs(mdev, !enable);
2795}
2796
36350114
GP		 2797static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2798{
2799 struct mlx5e_priv *priv = netdev_priv(netdev);
2800 int err;
2801
2802 mutex_lock(&priv->state_lock);
2803
2804 priv->params.vlan_strip_disable = !enable;
2805 err = mlx5e_modify_rqs_vsd(priv, !enable);
2806 if (err)
2807 priv->params.vlan_strip_disable = enable;
2808
2809 mutex_unlock(&priv->state_lock);
2810
2811 return err;
2812}
2813
45bf454a
MG		 2814#ifdef CONFIG_RFS_ACCEL
2815static int set_feature_arfs(struct net_device *netdev, bool enable)
2816{
2817 struct mlx5e_priv *priv = netdev_priv(netdev);
2818 int err;
2819
2820 if (enable)
2821 err = mlx5e_arfs_enable(priv);
2822 else
2823 err = mlx5e_arfs_disable(priv);
2824
2825 return err;
2826}
2827#endif
2828
0e405443
GP		 2829static int mlx5e_handle_feature(struct net_device *netdev,
2830 netdev_features_t wanted_features,
2831 netdev_features_t feature,
2832 mlx5e_feature_handler feature_handler)
2833{
2834 netdev_features_t changes = wanted_features ^ netdev->features;
2835 bool enable = !!(wanted_features & feature);
2836 int err;
2837
2838 if (!(changes & feature))
2839 return 0;
2840
2841 err = feature_handler(netdev, enable);
2842 if (err) {
2843 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2844 enable ? "Enable" : "Disable", feature, err);
2845 return err;
2846 }
2847
2848 MLX5E_SET_FEATURE(netdev, feature, enable);
2849 return 0;
2850}
2851
2852static int mlx5e_set_features(struct net_device *netdev,
2853 netdev_features_t features)
2854{
2855 int err;
2856
2857 err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2858 set_feature_lro);
2859 err |= mlx5e_handle_feature(netdev, features,
2860 NETIF_F_HW_VLAN_CTAG_FILTER,
2861 set_feature_vlan_filter);
2862 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2863 set_feature_tc_num_filters);
94cb1ebb
EBE		 2864 err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2865 set_feature_rx_all);
36350114
GP		 2866 err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2867 set_feature_rx_vlan);
45bf454a
MG		 2868#ifdef CONFIG_RFS_ACCEL
2869 err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2870 set_feature_arfs);
2871#endif
0e405443
GP		 2872
2873 return err ? -EINVAL : 0;
f62b8bb8
AV		 2874}
2875
2876static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2877{
2878 struct mlx5e_priv *priv = netdev_priv(netdev);
98e81b0a 2879 bool was_opened;
98e81b0a 2880 int err = 0;
506753b0 2881 bool reset;
f62b8bb8 2882
f62b8bb8 2883 mutex_lock(&priv->state_lock);
98e81b0a 2884
506753b0
TT		 2885 reset = !priv->params.lro_en &&
2886 (priv->params.rq_wq_type !=
2887 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2888
98e81b0a 2889 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
506753b0 2890 if (was_opened && reset)
98e81b0a
AS		 2891 mlx5e_close_locked(netdev);
2892
f62b8bb8 2893 netdev->mtu = new_mtu;
13f9bba7 2894 mlx5e_set_dev_port_mtu(netdev);
98e81b0a 2895
506753b0 2896 if (was_opened && reset)
98e81b0a
AS		 2897 err = mlx5e_open_locked(netdev);
2898
f62b8bb8
AV		 2899 mutex_unlock(&priv->state_lock);
2900
2901 return err;
2902}
2903
ef9814de
EBE		 2904static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2905{
2906 switch (cmd) {
2907 case SIOCSHWTSTAMP:
2908 return mlx5e_hwstamp_set(dev, ifr);
2909 case SIOCGHWTSTAMP:
2910 return mlx5e_hwstamp_get(dev, ifr);
2911 default:
2912 return -EOPNOTSUPP;
2913 }
2914}
2915
66e49ded
SM		 2916static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2917{
2918 struct mlx5e_priv *priv = netdev_priv(dev);
2919 struct mlx5_core_dev *mdev = priv->mdev;
2920
2921 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2922}
2923
79aab093
MS		 2924static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2925 __be16 vlan_proto)
66e49ded
SM		 2926{
2927 struct mlx5e_priv *priv = netdev_priv(dev);
2928 struct mlx5_core_dev *mdev = priv->mdev;
2929
79aab093
MS		 2930 if (vlan_proto != htons(ETH_P_8021Q))
2931 return -EPROTONOSUPPORT;
2932
66e49ded
SM		 2933 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2934 vlan, qos);
2935}
2936
f942380c
MHY		 2937static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2938{
2939 struct mlx5e_priv *priv = netdev_priv(dev);
2940 struct mlx5_core_dev *mdev = priv->mdev;
2941
2942 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2943}
2944
1edc57e2
MHY		 2945static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2946{
2947 struct mlx5e_priv *priv = netdev_priv(dev);
2948 struct mlx5_core_dev *mdev = priv->mdev;
2949
2950 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2951}
bd77bf1c
MHY		 2952
2953static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2954 int max_tx_rate)
2955{
2956 struct mlx5e_priv *priv = netdev_priv(dev);
2957 struct mlx5_core_dev *mdev = priv->mdev;
2958
2959 if (min_tx_rate)
2960 return -EOPNOTSUPP;
2961
2962 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
2963 max_tx_rate);
2964}
2965
66e49ded
SM		 2966static int mlx5_vport_link2ifla(u8 esw_link)
2967{
2968 switch (esw_link) {
2969 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2970 return IFLA_VF_LINK_STATE_DISABLE;
2971 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2972 return IFLA_VF_LINK_STATE_ENABLE;
2973 }
2974 return IFLA_VF_LINK_STATE_AUTO;
2975}
2976
2977static int mlx5_ifla_link2vport(u8 ifla_link)
2978{
2979 switch (ifla_link) {
2980 case IFLA_VF_LINK_STATE_DISABLE:
2981 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2982 case IFLA_VF_LINK_STATE_ENABLE:
2983 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2984 }
2985 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2986}
2987
2988static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2989 int link_state)
2990{
2991 struct mlx5e_priv *priv = netdev_priv(dev);
2992 struct mlx5_core_dev *mdev = priv->mdev;
2993
2994 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2995 mlx5_ifla_link2vport(link_state));
2996}
2997
2998static int mlx5e_get_vf_config(struct net_device *dev,
2999 int vf, struct ifla_vf_info *ivi)
3000{
3001 struct mlx5e_priv *priv = netdev_priv(dev);
3002 struct mlx5_core_dev *mdev = priv->mdev;
3003 int err;
3004
3005 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3006 if (err)
3007 return err;
3008 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3009 return 0;
3010}
3011
3012static int mlx5e_get_vf_stats(struct net_device *dev,
3013 int vf, struct ifla_vf_stats *vf_stats)
3014{
3015 struct mlx5e_priv *priv = netdev_priv(dev);
3016 struct mlx5_core_dev *mdev = priv->mdev;
3017
3018 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3019 vf_stats);
3020}
3021
4a25730e
HHZ		 3022void mlx5e_add_vxlan_port(struct net_device *netdev,
3023 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3024{
3025 struct mlx5e_priv *priv = netdev_priv(netdev);
3026
974c3f30
AD		 3027 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3028 return;
3029
b3f63c3d
MF		 3030 if (!mlx5e_vxlan_allowed(priv->mdev))
3031 return;
3032
974c3f30 3033 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
b3f63c3d
MF		 3034}
3035
4a25730e
HHZ		 3036void mlx5e_del_vxlan_port(struct net_device *netdev,
3037 struct udp_tunnel_info *ti)
b3f63c3d
MF		 3038{
3039 struct mlx5e_priv *priv = netdev_priv(netdev);
3040
974c3f30
AD		 3041 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3042 return;
3043
b3f63c3d
MF		 3044 if (!mlx5e_vxlan_allowed(priv->mdev))
3045 return;
3046
974c3f30 3047 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
b3f63c3d
MF		 3048}
3049
3050static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
3051 struct sk_buff *skb,
3052 netdev_features_t features)
3053{
3054 struct udphdr *udph;
3055 u16 proto;
3056 u16 port = 0;
3057
3058 switch (vlan_get_protocol(skb)) {
3059 case htons(ETH_P_IP):
3060 proto = ip_hdr(skb)->protocol;
3061 break;
3062 case htons(ETH_P_IPV6):
3063 proto = ipv6_hdr(skb)->nexthdr;
3064 break;
3065 default:
3066 goto out;
3067 }
3068
3069 if (proto == IPPROTO_UDP) {
3070 udph = udp_hdr(skb);
3071 port = be16_to_cpu(udph->dest);
3072 }
3073
3074 /* Verify if UDP port is being offloaded by HW */
3075 if (port && mlx5e_vxlan_lookup_port(priv, port))
3076 return features;
3077
3078out:
3079 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3080 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3081}
3082
3083static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3084 struct net_device *netdev,
3085 netdev_features_t features)
3086{
3087 struct mlx5e_priv *priv = netdev_priv(netdev);
3088
3089 features = vlan_features_check(skb, features);
3090 features = vxlan_features_check(skb, features);
3091
3092 /* Validate if the tunneled packet is being offloaded by HW */
3093 if (skb->encapsulation &&
3094 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3095 return mlx5e_vxlan_features_check(priv, skb, features);
3096
3097 return features;
3098}
3099
3947ca18
DJ		 3100static void mlx5e_tx_timeout(struct net_device *dev)
3101{
3102 struct mlx5e_priv *priv = netdev_priv(dev);
3103 bool sched_work = false;
3104 int i;
3105
3106 netdev_err(dev, "TX timeout detected\n");
3107
3108 for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
3109 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
3110
2c1ccc99 3111 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
3947ca18
DJ		 3112 continue;
3113 sched_work = true;
6e8dd6d6 3114 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
3947ca18
DJ		 3115 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3116 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
3117 }
3118
3119 if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
3120 schedule_work(&priv->tx_timeout_work);
3121}
3122
86994156
RS		 3123static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3124{
3125 struct mlx5e_priv *priv = netdev_priv(netdev);
3126 struct bpf_prog *old_prog;
3127 int err = 0;
3128 bool reset, was_opened;
3129 int i;
3130
3131 mutex_lock(&priv->state_lock);
3132
3133 if ((netdev->features & NETIF_F_LRO) && prog) {
3134 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3135 err = -EINVAL;
3136 goto unlock;
3137 }
3138
3139 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3140 /* no need for full reset when exchanging programs */
3141 reset = (!priv->xdp_prog || !prog);
3142
3143 if (was_opened && reset)
3144 mlx5e_close_locked(netdev);
c54c0629
DB		 3145 if (was_opened && !reset) {
3146 /* num_channels is invariant here, so we can take the
3147 * batched reference right upfront.
3148 */
3149 prog = bpf_prog_add(prog, priv->params.num_channels);
3150 if (IS_ERR(prog)) {
3151 err = PTR_ERR(prog);
3152 goto unlock;
3153 }
3154 }
86994156 3155
c54c0629
DB		 3156 /* exchange programs, extra prog reference we got from caller
3157 * as long as we don't fail from this point onwards.
3158 */
86994156 3159 old_prog = xchg(&priv->xdp_prog, prog);
86994156
RS		 3160 if (old_prog)
3161 bpf_prog_put(old_prog);
3162
3163 if (reset) /* change RQ type according to priv->xdp_prog */
3164 mlx5e_set_rq_priv_params(priv);
3165
3166 if (was_opened && reset)
3167 mlx5e_open_locked(netdev);
3168
3169 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3170 goto unlock;
3171
3172 /* exchanging programs w/o reset, we update ref counts on behalf
3173 * of the channels RQs here.
3174 */
86994156
RS		 3175 for (i = 0; i < priv->params.num_channels; i++) {
3176 struct mlx5e_channel *c = priv->channel[i];
3177
3178 set_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3179 napi_synchronize(&c->napi);
3180 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3181
3182 old_prog = xchg(&c->rq.xdp_prog, prog);
3183
3184 clear_bit(MLX5E_RQ_STATE_FLUSH, &c->rq.state);
3185 /* napi_schedule in case we have missed anything */
3186 set_bit(MLX5E_CHANNEL_NAPI_SCHED, &c->flags);
3187 napi_schedule(&c->napi);
3188
3189 if (old_prog)
3190 bpf_prog_put(old_prog);
3191 }
3192
3193unlock:
3194 mutex_unlock(&priv->state_lock);
3195 return err;
3196}
3197
3198static bool mlx5e_xdp_attached(struct net_device *dev)
3199{
3200 struct mlx5e_priv *priv = netdev_priv(dev);
3201
3202 return !!priv->xdp_prog;
3203}
3204
3205static int mlx5e_xdp(struct net_device *dev, struct netdev_xdp *xdp)
3206{
3207 switch (xdp->command) {
3208 case XDP_SETUP_PROG:
3209 return mlx5e_xdp_set(dev, xdp->prog);
3210 case XDP_QUERY_PROG:
3211 xdp->prog_attached = mlx5e_xdp_attached(dev);
3212 return 0;
3213 default:
3214 return -EINVAL;
3215 }
3216}
3217
80378384
CO		 3218#ifdef CONFIG_NET_POLL_CONTROLLER
3219/* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3220 * reenabling interrupts.
3221 */
3222static void mlx5e_netpoll(struct net_device *dev)
3223{
3224 struct mlx5e_priv *priv = netdev_priv(dev);
3225 int i;
3226
3227 for (i = 0; i < priv->params.num_channels; i++)
3228 napi_schedule(&priv->channel[i]->napi);
3229}
3230#endif
3231
b0eed40e 3232static const struct net_device_ops mlx5e_netdev_ops_basic = {
f62b8bb8
AV		 3233 .ndo_open = mlx5e_open,
3234 .ndo_stop = mlx5e_close,
3235 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3236 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3237 .ndo_select_queue = mlx5e_select_queue,
f62b8bb8
AV		 3238 .ndo_get_stats64 = mlx5e_get_stats,
3239 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3240 .ndo_set_mac_address = mlx5e_set_mac,
b0eed40e
SM		 3241 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3242 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
f62b8bb8 3243 .ndo_set_features = mlx5e_set_features,
b0eed40e
SM		 3244 .ndo_change_mtu = mlx5e_change_mtu,
3245 .ndo_do_ioctl = mlx5e_ioctl,
507f0c81 3246 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
45bf454a
MG		 3247#ifdef CONFIG_RFS_ACCEL
3248 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3249#endif
3947ca18 3250 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3251 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3252#ifdef CONFIG_NET_POLL_CONTROLLER
3253 .ndo_poll_controller = mlx5e_netpoll,
3254#endif
b0eed40e
SM		 3255};
3256
3257static const struct net_device_ops mlx5e_netdev_ops_sriov = {
3258 .ndo_open = mlx5e_open,
3259 .ndo_stop = mlx5e_close,
3260 .ndo_start_xmit = mlx5e_xmit,
08fb1dac
SM		 3261 .ndo_setup_tc = mlx5e_ndo_setup_tc,
3262 .ndo_select_queue = mlx5e_select_queue,
b0eed40e
SM		 3263 .ndo_get_stats64 = mlx5e_get_stats,
3264 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3265 .ndo_set_mac_address = mlx5e_set_mac,
3266 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3267 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3268 .ndo_set_features = mlx5e_set_features,
3269 .ndo_change_mtu = mlx5e_change_mtu,
3270 .ndo_do_ioctl = mlx5e_ioctl,
974c3f30
AD		 3271 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3272 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
507f0c81 3273 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
b3f63c3d 3274 .ndo_features_check = mlx5e_features_check,
45bf454a
MG		 3275#ifdef CONFIG_RFS_ACCEL
3276 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3277#endif
b0eed40e
SM		 3278 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3279 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
f942380c 3280 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
1edc57e2 3281 .ndo_set_vf_trust = mlx5e_set_vf_trust,
bd77bf1c 3282 .ndo_set_vf_rate = mlx5e_set_vf_rate,
b0eed40e
SM		 3283 .ndo_get_vf_config = mlx5e_get_vf_config,
3284 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3285 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3947ca18 3286 .ndo_tx_timeout = mlx5e_tx_timeout,
86994156 3287 .ndo_xdp = mlx5e_xdp,
80378384
CO		 3288#ifdef CONFIG_NET_POLL_CONTROLLER
3289 .ndo_poll_controller = mlx5e_netpoll,
3290#endif
370bad0f
OG		 3291 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3292 .ndo_get_offload_stats = mlx5e_get_offload_stats,
f62b8bb8
AV		 3293};
3294
3295static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3296{
3297 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3298 return -ENOTSUPP;
3299 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
3300 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
3301 !MLX5_CAP_ETH(mdev, csum_cap) ||
3302 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
3303 !MLX5_CAP_ETH(mdev, vlan_cap) ||
796a27ec
GP		 3304 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
3305 MLX5_CAP_FLOWTABLE(mdev,
3306 flow_table_properties_nic_receive.max_ft_level)
3307 < 3) {
f62b8bb8
AV		 3308 mlx5_core_warn(mdev,
3309 "Not creating net device, some required device capabilities are missing\n");
3310 return -ENOTSUPP;
3311 }
66189961
TT		 3312 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
3313 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
7524a5d8
GP		 3314 if (!MLX5_CAP_GEN(mdev, cq_moderation))
3315 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
66189961 3316
f62b8bb8
AV		 3317 return 0;
3318}
3319
58d52291
AS		 3320u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3321{
3322 int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
3323
3324 return bf_buf_size -
3325 sizeof(struct mlx5e_tx_wqe) +
3326 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3327}
3328
d8c9660d
TT		 3329void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3330 u32 *indirection_rqt, int len,
85082dba
TT		 3331 int num_channels)
3332{
d8c9660d
TT		 3333 int node = mdev->priv.numa_node;
3334 int node_num_of_cores;
85082dba
TT		 3335 int i;
3336
d8c9660d
TT		 3337 if (node == -1)
3338 node = first_online_node;
3339
3340 node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3341
3342 if (node_num_of_cores)
3343 num_channels = min_t(int, num_channels, node_num_of_cores);
3344
85082dba
TT		 3345 for (i = 0; i < len; i++)
3346 indirection_rqt[i] = i % num_channels;
3347}
3348
b797a684
SM		 3349static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3350{
3351 enum pcie_link_width width;
3352 enum pci_bus_speed speed;
3353 int err = 0;
3354
3355 err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3356 if (err)
3357 return err;
3358
3359 if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3360 return -EINVAL;
3361
3362 switch (speed) {
3363 case PCIE_SPEED_2_5GT:
3364 *pci_bw = 2500 * width;
3365 break;
3366 case PCIE_SPEED_5_0GT:
3367 *pci_bw = 5000 * width;
3368 break;
3369 case PCIE_SPEED_8_0GT:
3370 *pci_bw = 8000 * width;
3371 break;
3372 default:
3373 return -EINVAL;
3374 }
3375
3376 return 0;
3377}
3378
3379static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3380{
3381 return (link_speed && pci_bw &&
3382 (pci_bw < 40000) && (pci_bw < link_speed));
3383}
3384
9908aa29
TT		 3385void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3386{
3387 params->rx_cq_period_mode = cq_period_mode;
3388
3389 params->rx_cq_moderation.pkts =
3390 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3391 params->rx_cq_moderation.usec =
3392 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3393
3394 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3395 params->rx_cq_moderation.usec =
3396 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3397}
3398
cff92d7c
HHZ		 3399static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3400 u8 *min_inline_mode)
3401{
3402 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
34e4e990 3403 case MLX5_CAP_INLINE_MODE_L2:
cff92d7c
HHZ		 3404 *min_inline_mode = MLX5_INLINE_MODE_L2;
3405 break;
34e4e990
RD		 3406 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
3407 mlx5_query_nic_vport_min_inline(mdev, 0, min_inline_mode);
cff92d7c 3408 break;
34e4e990 3409 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
cff92d7c
HHZ		 3410 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3411 break;
3412 }
3413}
3414
2b029556
SM		 3415u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
3416{
3417 int i;
3418
3419 /* The supported periods are organized in ascending order */
3420 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
3421 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
3422 break;
3423
3424 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
3425}
3426
6bfd390b
HHZ		 3427static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3428 struct net_device *netdev,
127ea380
HHZ		 3429 const struct mlx5e_profile *profile,
3430 void *ppriv)
f62b8bb8
AV		 3431{
3432 struct mlx5e_priv *priv = netdev_priv(netdev);
b797a684
SM		 3433 u32 link_speed = 0;
3434 u32 pci_bw = 0;
cb3c7fd4
GR		 3435 u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3436 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3437 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
f62b8bb8 3438
2fc4bfb7
SM		 3439 priv->mdev = mdev;
3440 priv->netdev = netdev;
3441 priv->params.num_channels = profile->max_nch(mdev);
3442 priv->profile = profile;
3443 priv->ppriv = ppriv;
3444
2b029556
SM		 3445 priv->params.lro_timeout =
3446 mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
3447
2fc4bfb7 3448 priv->params.log_sq_size = MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
461017cb 3449
b797a684 3450 /* set CQE compression */
9bcc8606 3451 priv->params.rx_cqe_compress_def = false;
b797a684
SM		 3452 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3453 MLX5_CAP_GEN(mdev, vport_group_manager)) {
3454 mlx5e_get_max_linkspeed(mdev, &link_speed);
3455 mlx5e_get_pci_bw(mdev, &pci_bw);
3456 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3457 link_speed, pci_bw);
9bcc8606 3458 priv->params.rx_cqe_compress_def =
b797a684
SM		 3459 cqe_compress_heuristic(link_speed, pci_bw);
3460 }
b797a684 3461
2fc4bfb7
SM		 3462 mlx5e_set_rq_priv_params(priv);
3463 if (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
461017cb 3464 priv->params.lro_en = true;
9908aa29 3465
cb3c7fd4
GR		 3466 priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3467 mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
9908aa29
TT		 3468
3469 priv->params.tx_cq_moderation.usec =
f62b8bb8 3470 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
9908aa29 3471 priv->params.tx_cq_moderation.pkts =
f62b8bb8 3472 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
58d52291 3473 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
cff92d7c 3474 mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
f62b8bb8 3475 priv->params.num_tc = 1;
2be6967c 3476 priv->params.rss_hfunc = ETH_RSS_HASH_XOR;
f62b8bb8 3477
57afead5
AS		 3478 netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3479 sizeof(priv->params.toeplitz_hash_key));
3480
d8c9660d 3481 mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
6bfd390b 3482 MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
2d75b2bc 3483
e4b85508
SM		 3484 priv->params.lro_wqe_sz =
3485 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ -
3486 /* Extra room needed for build_skb */
3487 MLX5_RX_HEADROOM -
3488 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
f62b8bb8 3489
9908aa29 3490 /* Initialize pflags */
59ece1c9
SD		 3491 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3492 priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
9bcc8606 3493 MLX5E_SET_PFLAG(priv, MLX5E_PFLAG_RX_CQE_COMPRESS, priv->params.rx_cqe_compress_def);
9908aa29 3494
f62b8bb8
AV		 3495 mutex_init(&priv->state_lock);
3496
3497 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3498 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3947ca18 3499 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
f62b8bb8
AV		 3500 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3501}
3502
3503static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3504{
3505 struct mlx5e_priv *priv = netdev_priv(netdev);
3506
e1d7d349 3507 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
108805fc
SM		 3508 if (is_zero_ether_addr(netdev->dev_addr) &&
3509 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3510 eth_hw_addr_random(netdev);
3511 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3512 }
f62b8bb8
AV		 3513}
3514
cb67b832
HHZ		 3515static const struct switchdev_ops mlx5e_switchdev_ops = {
3516 .switchdev_port_attr_get = mlx5e_attr_get,
3517};
3518
6bfd390b 3519static void mlx5e_build_nic_netdev(struct net_device *netdev)
f62b8bb8
AV		 3520{
3521 struct mlx5e_priv *priv = netdev_priv(netdev);
3522 struct mlx5_core_dev *mdev = priv->mdev;
94cb1ebb
EBE		 3523 bool fcs_supported;
3524 bool fcs_enabled;
f62b8bb8
AV		 3525
3526 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3527
08fb1dac 3528 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
b0eed40e 3529 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
08fb1dac 3530#ifdef CONFIG_MLX5_CORE_EN_DCB
80653f73
HN		 3531 if (MLX5_CAP_GEN(mdev, qos))
3532 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
08fb1dac
SM		 3533#endif
3534 } else {
b0eed40e 3535 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
08fb1dac 3536 }
66e49ded 3537
f62b8bb8
AV		 3538 netdev->watchdog_timeo = 15 * HZ;
3539
3540 netdev->ethtool_ops = &mlx5e_ethtool_ops;
3541
12be4b21 3542 netdev->vlan_features |= NETIF_F_SG;
f62b8bb8
AV		 3543 netdev->vlan_features |= NETIF_F_IP_CSUM;
3544 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
3545 netdev->vlan_features |= NETIF_F_GRO;
3546 netdev->vlan_features |= NETIF_F_TSO;
3547 netdev->vlan_features |= NETIF_F_TSO6;
3548 netdev->vlan_features |= NETIF_F_RXCSUM;
3549 netdev->vlan_features |= NETIF_F_RXHASH;
3550
3551 if (!!MLX5_CAP_ETH(mdev, lro_cap))
3552 netdev->vlan_features |= NETIF_F_LRO;
3553
3554 netdev->hw_features = netdev->vlan_features;
e4cf27bd 3555 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
f62b8bb8
AV		 3556 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
3557 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3558
b3f63c3d 3559 if (mlx5e_vxlan_allowed(mdev)) {
b49663c8
AD		 3560 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3561 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3562 NETIF_F_GSO_PARTIAL;
b3f63c3d 3563 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
f3ed653c 3564 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
b3f63c3d
MF		 3565 netdev->hw_enc_features |= NETIF_F_TSO;
3566 netdev->hw_enc_features |= NETIF_F_TSO6;
b3f63c3d 3567 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
b49663c8
AD		 3568 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3569 NETIF_F_GSO_PARTIAL;
3570 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
b3f63c3d
MF		 3571 }
3572
94cb1ebb
EBE		 3573 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3574
3575 if (fcs_supported)
3576 netdev->hw_features |= NETIF_F_RXALL;
3577
f62b8bb8
AV		 3578 netdev->features = netdev->hw_features;
3579 if (!priv->params.lro_en)
3580 netdev->features &= ~NETIF_F_LRO;
3581
94cb1ebb
EBE		 3582 if (fcs_enabled)
3583 netdev->features &= ~NETIF_F_RXALL;
3584
e8f887ac
AV		 3585#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3586 if (FT_CAP(flow_modify_en) &&
3587 FT_CAP(modify_root) &&
3588 FT_CAP(identified_miss_table_mode) &&
1cabe6b0
MG		 3589 FT_CAP(flow_table_modify)) {
3590 netdev->hw_features |= NETIF_F_HW_TC;
3591#ifdef CONFIG_RFS_ACCEL
3592 netdev->hw_features |= NETIF_F_NTUPLE;
3593#endif
3594 }
e8f887ac 3595
f62b8bb8
AV		 3596 netdev->features |= NETIF_F_HIGHDMA;
3597
3598 netdev->priv_flags |= IFF_UNICAST_FLT;
3599
3600 mlx5e_set_netdev_dev_addr(netdev);
cb67b832
HHZ		 3601
3602#ifdef CONFIG_NET_SWITCHDEV
3603 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3604 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3605#endif
f62b8bb8
AV		 3606}
3607
593cf338
RS		 3608static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3609{
3610 struct mlx5_core_dev *mdev = priv->mdev;
3611 int err;
3612
3613 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3614 if (err) {
3615 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3616 priv->q_counter = 0;
3617 }
3618}
3619
3620static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3621{
3622 if (!priv->q_counter)
3623 return;
3624
3625 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3626}
3627
bc77b240
TT		 3628static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3629{
3630 struct mlx5_core_dev *mdev = priv->mdev;
fe4c988b
SM		 3631 u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3632 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
ec22eb53
SM		 3633 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3634 void *mkc;
3635 u32 *in;
bc77b240
TT		 3636 int err;
3637
3638 in = mlx5_vzalloc(inlen);
3639 if (!in)
3640 return -ENOMEM;
3641
ec22eb53 3642 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
bc77b240 3643
fe4c988b
SM		 3644 npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3645
ec22eb53
SM		 3646 MLX5_SET(mkc, mkc, free, 1);
3647 MLX5_SET(mkc, mkc, umr_en, 1);
3648 MLX5_SET(mkc, mkc, lw, 1);
3649 MLX5_SET(mkc, mkc, lr, 1);
3650 MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
bc77b240 3651
ec22eb53
SM		 3652 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3653 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3654 MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3655 MLX5_SET(mkc, mkc, translations_octword_size,
6abdd5f5 3656 MLX5_MTT_OCTW(npages));
ec22eb53 3657 MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
bc77b240 3658
ec22eb53 3659 err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
bc77b240 3660
ec22eb53 3661 kvfree(in);
bc77b240
TT		 3662 return err;
3663}
3664
6bfd390b
HHZ		 3665static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3666 struct net_device *netdev,
127ea380
HHZ		 3667 const struct mlx5e_profile *profile,
3668 void *ppriv)
6bfd390b
HHZ		 3669{
3670 struct mlx5e_priv *priv = netdev_priv(netdev);
3671
127ea380 3672 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
6bfd390b
HHZ		 3673 mlx5e_build_nic_netdev(netdev);
3674 mlx5e_vxlan_init(priv);
3675}
3676
3677static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3678{
127ea380
HHZ		 3679 struct mlx5_core_dev *mdev = priv->mdev;
3680 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3681
6bfd390b 3682 mlx5e_vxlan_cleanup(priv);
127ea380
HHZ		 3683
3684 if (MLX5_CAP_GEN(mdev, vport_group_manager))
3685 mlx5_eswitch_unregister_vport_rep(esw, 0);
a055c19b
DB		 3686
3687 if (priv->xdp_prog)
3688 bpf_prog_put(priv->xdp_prog);
6bfd390b
HHZ		 3689}
3690
3691static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3692{
3693 struct mlx5_core_dev *mdev = priv->mdev;
3694 int err;
3695 int i;
3696
3697 err = mlx5e_create_indirect_rqts(priv);
3698 if (err) {
3699 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3700 return err;
3701 }
3702
3703 err = mlx5e_create_direct_rqts(priv);
3704 if (err) {
3705 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3706 goto err_destroy_indirect_rqts;
3707 }
3708
3709 err = mlx5e_create_indirect_tirs(priv);
3710 if (err) {
3711 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3712 goto err_destroy_direct_rqts;
3713 }
3714
3715 err = mlx5e_create_direct_tirs(priv);
3716 if (err) {
3717 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3718 goto err_destroy_indirect_tirs;
3719 }
3720
3721 err = mlx5e_create_flow_steering(priv);
3722 if (err) {
3723 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3724 goto err_destroy_direct_tirs;
3725 }
3726
3727 err = mlx5e_tc_init(priv);
3728 if (err)
3729 goto err_destroy_flow_steering;
3730
3731 return 0;
3732
3733err_destroy_flow_steering:
3734 mlx5e_destroy_flow_steering(priv);
3735err_destroy_direct_tirs:
3736 mlx5e_destroy_direct_tirs(priv);
3737err_destroy_indirect_tirs:
3738 mlx5e_destroy_indirect_tirs(priv);
3739err_destroy_direct_rqts:
3740 for (i = 0; i < priv->profile->max_nch(mdev); i++)
3741 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3742err_destroy_indirect_rqts:
3743 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3744 return err;
3745}
3746
3747static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3748{
3749 int i;
3750
3751 mlx5e_tc_cleanup(priv);
3752 mlx5e_destroy_flow_steering(priv);
3753 mlx5e_destroy_direct_tirs(priv);
3754 mlx5e_destroy_indirect_tirs(priv);
3755 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3756 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3757 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3758}
3759
3760static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3761{
3762 int err;
3763
3764 err = mlx5e_create_tises(priv);
3765 if (err) {
3766 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3767 return err;
3768 }
3769
3770#ifdef CONFIG_MLX5_CORE_EN_DCB
e207b7e9 3771 mlx5e_dcbnl_initialize(priv);
6bfd390b
HHZ		 3772#endif
3773 return 0;
3774}
3775
3776static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3777{
3778 struct net_device *netdev = priv->netdev;
3779 struct mlx5_core_dev *mdev = priv->mdev;
127ea380
HHZ		 3780 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3781 struct mlx5_eswitch_rep rep;
6bfd390b 3782
7907f23a
AH		 3783 mlx5_lag_add(mdev, netdev);
3784
6bfd390b
HHZ		 3785 if (mlx5e_vxlan_allowed(mdev)) {
3786 rtnl_lock();
3787 udp_tunnel_get_rx_info(netdev);
3788 rtnl_unlock();
3789 }
3790
3791 mlx5e_enable_async_events(priv);
3792 queue_work(priv->wq, &priv->set_rx_mode_work);
127ea380
HHZ		 3793
3794 if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
dbe413e3 3795 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
cb67b832
HHZ		 3796 rep.load = mlx5e_nic_rep_load;
3797 rep.unload = mlx5e_nic_rep_unload;
9deb2241 3798 rep.vport = FDB_UPLINK_VPORT;
127ea380 3799 rep.priv_data = priv;
9deb2241 3800 mlx5_eswitch_register_vport_rep(esw, 0, &rep);
127ea380 3801 }
6bfd390b
HHZ		 3802}
3803
3804static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3805{
3806 queue_work(priv->wq, &priv->set_rx_mode_work);
3807 mlx5e_disable_async_events(priv);
7907f23a 3808 mlx5_lag_remove(priv->mdev);
6bfd390b
HHZ		 3809}
3810
3811static const struct mlx5e_profile mlx5e_nic_profile = {
3812 .init = mlx5e_nic_init,
3813 .cleanup = mlx5e_nic_cleanup,
3814 .init_rx = mlx5e_init_nic_rx,
3815 .cleanup_rx = mlx5e_cleanup_nic_rx,
3816 .init_tx = mlx5e_init_nic_tx,
3817 .cleanup_tx = mlx5e_cleanup_nic_tx,
3818 .enable = mlx5e_nic_enable,
3819 .disable = mlx5e_nic_disable,
3820 .update_stats = mlx5e_update_stats,
3821 .max_nch = mlx5e_get_max_num_channels,
3822 .max_tc = MLX5E_MAX_NUM_TC,
3823};
3824
26e59d80
MHY		 3825struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3826 const struct mlx5e_profile *profile,
3827 void *ppriv)
f62b8bb8 3828{
26e59d80 3829 int nch = profile->max_nch(mdev);
f62b8bb8
AV		 3830 struct net_device *netdev;
3831 struct mlx5e_priv *priv;
f62b8bb8 3832
08fb1dac 3833 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
6bfd390b 3834 nch * profile->max_tc,
08fb1dac 3835 nch);
f62b8bb8
AV		 3836 if (!netdev) {
3837 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3838 return NULL;
3839 }
3840
127ea380 3841 profile->init(mdev, netdev, profile, ppriv);
f62b8bb8
AV		 3842
3843 netif_carrier_off(netdev);
3844
3845 priv = netdev_priv(netdev);
3846
7bb29755
MF		 3847 priv->wq = create_singlethread_workqueue("mlx5e");
3848 if (!priv->wq)
26e59d80
MHY		 3849 goto err_cleanup_nic;
3850
3851 return netdev;
3852
3853err_cleanup_nic:
3854 profile->cleanup(priv);
3855 free_netdev(netdev);
3856
3857 return NULL;
3858}
3859
3860int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3861{
3862 const struct mlx5e_profile *profile;
3863 struct mlx5e_priv *priv;
b80f71f5 3864 u16 max_mtu;
26e59d80
MHY		 3865 int err;
3866
3867 priv = netdev_priv(netdev);
3868 profile = priv->profile;
3869 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
7bb29755 3870
bc77b240
TT		 3871 err = mlx5e_create_umr_mkey(priv);
3872 if (err) {
3873 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
26e59d80 3874 goto out;
bc77b240
TT		 3875 }
3876
6bfd390b
HHZ		 3877 err = profile->init_tx(priv);
3878 if (err)
bc77b240 3879 goto err_destroy_umr_mkey;
5c50368f
AS		 3880
3881 err = mlx5e_open_drop_rq(priv);
3882 if (err) {
3883 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
6bfd390b 3884 goto err_cleanup_tx;
5c50368f
AS		 3885 }
3886
6bfd390b
HHZ		 3887 err = profile->init_rx(priv);
3888 if (err)
5c50368f 3889 goto err_close_drop_rq;
5c50368f 3890
593cf338
RS		 3891 mlx5e_create_q_counter(priv);
3892
33cfaaa8 3893 mlx5e_init_l2_addr(priv);
5c50368f 3894
b80f71f5
JW		 3895 /* MTU range: 68 - hw-specific max */
3896 netdev->min_mtu = ETH_MIN_MTU;
3897 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
3898 netdev->max_mtu = MLX5E_HW2SW_MTU(max_mtu);
3899
13f9bba7
SM		 3900 mlx5e_set_dev_port_mtu(netdev);
3901
6bfd390b
HHZ		 3902 if (profile->enable)
3903 profile->enable(priv);
f62b8bb8 3904
26e59d80
MHY		 3905 rtnl_lock();
3906 if (netif_running(netdev))
3907 mlx5e_open(netdev);
3908 netif_device_attach(netdev);
3909 rtnl_unlock();
f62b8bb8 3910
26e59d80 3911 return 0;
5c50368f
AS		 3912
3913err_close_drop_rq:
3914 mlx5e_close_drop_rq(priv);
3915
6bfd390b
HHZ		 3916err_cleanup_tx:
3917 profile->cleanup_tx(priv);
5c50368f 3918
bc77b240
TT		 3919err_destroy_umr_mkey:
3920 mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3921
26e59d80
MHY		 3922out:
3923 return err;
f62b8bb8
AV		 3924}
3925
127ea380
HHZ		 3926static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3927{
3928 struct mlx5_eswitch *esw = mdev->priv.eswitch;
3929 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3930 int vport;
dbe413e3 3931 u8 mac[ETH_ALEN];
127ea380
HHZ		 3932
3933 if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3934 return;
3935
dbe413e3
HHZ		 3936 mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3937
127ea380
HHZ		 3938 for (vport = 1; vport < total_vfs; vport++) {
3939 struct mlx5_eswitch_rep rep;
3940
cb67b832
HHZ		 3941 rep.load = mlx5e_vport_rep_load;
3942 rep.unload = mlx5e_vport_rep_unload;
127ea380 3943 rep.vport = vport;
dbe413e3 3944 ether_addr_copy(rep.hw_id, mac);
9deb2241 3945 mlx5_eswitch_register_vport_rep(esw, vport, &rep);
127ea380
HHZ		 3946 }
3947}
3948
26e59d80
MHY		 3949void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3950{
3951 struct mlx5e_priv *priv = netdev_priv(netdev);
3952 const struct mlx5e_profile *profile = priv->profile;
3953
3954 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3955 if (profile->disable)
3956 profile->disable(priv);
3957
3958 flush_workqueue(priv->wq);
3959
3960 rtnl_lock();
3961 if (netif_running(netdev))
3962 mlx5e_close(netdev);
3963 netif_device_detach(netdev);
3964 rtnl_unlock();
3965
3966 mlx5e_destroy_q_counter(priv);
3967 profile->cleanup_rx(priv);
3968 mlx5e_close_drop_rq(priv);
3969 profile->cleanup_tx(priv);
3970 mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3971 cancel_delayed_work_sync(&priv->update_stats_work);
3972}
3973
3974/* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3975 * hardware contexts and to connect it to the current netdev.
3976 */
3977static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3978{
3979 struct mlx5e_priv *priv = vpriv;
3980 struct net_device *netdev = priv->netdev;
3981 int err;
3982
3983 if (netif_device_present(netdev))
3984 return 0;
3985
3986 err = mlx5e_create_mdev_resources(mdev);
3987 if (err)
3988 return err;
3989
3990 err = mlx5e_attach_netdev(mdev, netdev);
3991 if (err) {
3992 mlx5e_destroy_mdev_resources(mdev);
3993 return err;
3994 }
3995
3996 return 0;
3997}
3998
3999static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4000{
4001 struct mlx5e_priv *priv = vpriv;
4002 struct net_device *netdev = priv->netdev;
4003
4004 if (!netif_device_present(netdev))
4005 return;
4006
4007 mlx5e_detach_netdev(mdev, netdev);
4008 mlx5e_destroy_mdev_resources(mdev);
4009}
4010
b50d292b
HHZ		 4011static void *mlx5e_add(struct mlx5_core_dev *mdev)
4012{
127ea380 4013 struct mlx5_eswitch *esw = mdev->priv.eswitch;
26e59d80 4014 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
127ea380 4015 void *ppriv = NULL;
26e59d80
MHY		 4016 void *priv;
4017 int vport;
4018 int err;
4019 struct net_device *netdev;
b50d292b 4020
26e59d80
MHY		 4021 err = mlx5e_check_required_hca_cap(mdev);
4022 if (err)
b50d292b
HHZ		 4023 return NULL;
4024
127ea380
HHZ		 4025 mlx5e_register_vport_rep(mdev);
4026
4027 if (MLX5_CAP_GEN(mdev, vport_group_manager))
4028 ppriv = &esw->offloads.vport_reps[0];
4029
26e59d80
MHY		 4030 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
4031 if (!netdev) {
4032 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4033 goto err_unregister_reps;
4034 }
4035
4036 priv = netdev_priv(netdev);
4037
4038 err = mlx5e_attach(mdev, priv);
4039 if (err) {
4040 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4041 goto err_destroy_netdev;
4042 }
4043
4044 err = register_netdev(netdev);
4045 if (err) {
4046 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4047 goto err_detach;
b50d292b 4048 }
26e59d80
MHY		 4049
4050 return priv;
4051
4052err_detach:
4053 mlx5e_detach(mdev, priv);
4054
4055err_destroy_netdev:
4056 mlx5e_destroy_netdev(mdev, priv);
4057
4058err_unregister_reps:
4059 for (vport = 1; vport < total_vfs; vport++)
4060 mlx5_eswitch_unregister_vport_rep(esw, vport);
4061
4062 return NULL;
b50d292b
HHZ		 4063}
4064
cb67b832 4065void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
f62b8bb8 4066{
6bfd390b 4067 const struct mlx5e_profile *profile = priv->profile;
f62b8bb8
AV		 4068 struct net_device *netdev = priv->netdev;
4069
7bb29755 4070 destroy_workqueue(priv->wq);
6bfd390b
HHZ		 4071 if (profile->cleanup)
4072 profile->cleanup(priv);
26e59d80 4073 free_netdev(netdev);
f62b8bb8
AV		 4074}
4075
b50d292b
HHZ		 4076static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4077{
127ea380
HHZ		 4078 struct mlx5_eswitch *esw = mdev->priv.eswitch;
4079 int total_vfs = MLX5_TOTAL_VPORTS(mdev);
b50d292b 4080 struct mlx5e_priv *priv = vpriv;
127ea380 4081 int vport;
b50d292b 4082
127ea380
HHZ		 4083 for (vport = 1; vport < total_vfs; vport++)
4084 mlx5_eswitch_unregister_vport_rep(esw, vport);
4085
5e1e93c7 4086 unregister_netdev(priv->netdev);
26e59d80
MHY		 4087 mlx5e_detach(mdev, vpriv);
4088 mlx5e_destroy_netdev(mdev, priv);
b50d292b
HHZ		 4089}
4090
f62b8bb8
AV		 4091static void *mlx5e_get_netdev(void *vpriv)
4092{
4093 struct mlx5e_priv *priv = vpriv;
4094
4095 return priv->netdev;
4096}
4097
4098static struct mlx5_interface mlx5e_interface = {
b50d292b
HHZ		 4099 .add = mlx5e_add,
4100 .remove = mlx5e_remove,
26e59d80
MHY		 4101 .attach = mlx5e_attach,
4102 .detach = mlx5e_detach,
f62b8bb8
AV		 4103 .event = mlx5e_async_event,
4104 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4105 .get_dev = mlx5e_get_netdev,
4106};
4107
4108void mlx5e_init(void)
4109{
665bc539 4110 mlx5e_build_ptys2ethtool_map();
f62b8bb8
AV		 4111 mlx5_register_interface(&mlx5e_interface);
4112}
4113
4114void mlx5e_cleanup(void)
4115{
4116 mlx5_unregister_interface(&mlx5e_interface);
4117}
Linux 6.x block layer and io_uring tree(s)