Commit | Line | Data |
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f62b8bb8 | 1 | /* |
b3f63c3d | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
e8f887ac AV |
33 | #include <net/tc_act/tc_gact.h> |
34 | #include <net/pkt_cls.h> | |
86d722ad | 35 | #include <linux/mlx5/fs.h> |
b3f63c3d | 36 | #include <net/vxlan.h> |
f62b8bb8 | 37 | #include "en.h" |
e8f887ac | 38 | #include "en_tc.h" |
66e49ded | 39 | #include "eswitch.h" |
b3f63c3d | 40 | #include "vxlan.h" |
f62b8bb8 | 41 | |
29429f33 DJ |
42 | enum { |
43 | MLX5_EN_QP_FLUSH_TIMEOUT_MS = 5000, | |
44 | MLX5_EN_QP_FLUSH_MSLEEP_QUANT = 20, | |
45 | MLX5_EN_QP_FLUSH_MAX_ITER = MLX5_EN_QP_FLUSH_TIMEOUT_MS / | |
46 | MLX5_EN_QP_FLUSH_MSLEEP_QUANT, | |
47 | }; | |
48 | ||
f62b8bb8 AV |
49 | struct mlx5e_rq_param { |
50 | u32 rqc[MLX5_ST_SZ_DW(rqc)]; | |
51 | struct mlx5_wq_param wq; | |
52 | }; | |
53 | ||
54 | struct mlx5e_sq_param { | |
55 | u32 sqc[MLX5_ST_SZ_DW(sqc)]; | |
56 | struct mlx5_wq_param wq; | |
58d52291 | 57 | u16 max_inline; |
d3c9bc27 | 58 | bool icosq; |
f62b8bb8 AV |
59 | }; |
60 | ||
61 | struct mlx5e_cq_param { | |
62 | u32 cqc[MLX5_ST_SZ_DW(cqc)]; | |
63 | struct mlx5_wq_param wq; | |
64 | u16 eq_ix; | |
65 | }; | |
66 | ||
67 | struct mlx5e_channel_param { | |
68 | struct mlx5e_rq_param rq; | |
69 | struct mlx5e_sq_param sq; | |
d3c9bc27 | 70 | struct mlx5e_sq_param icosq; |
f62b8bb8 AV |
71 | struct mlx5e_cq_param rx_cq; |
72 | struct mlx5e_cq_param tx_cq; | |
d3c9bc27 | 73 | struct mlx5e_cq_param icosq_cq; |
f62b8bb8 AV |
74 | }; |
75 | ||
76 | static void mlx5e_update_carrier(struct mlx5e_priv *priv) | |
77 | { | |
78 | struct mlx5_core_dev *mdev = priv->mdev; | |
79 | u8 port_state; | |
80 | ||
81 | port_state = mlx5_query_vport_state(mdev, | |
e7546514 | 82 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0); |
f62b8bb8 | 83 | |
87424ad5 SD |
84 | if (port_state == VPORT_STATE_UP) { |
85 | netdev_info(priv->netdev, "Link up\n"); | |
f62b8bb8 | 86 | netif_carrier_on(priv->netdev); |
87424ad5 SD |
87 | } else { |
88 | netdev_info(priv->netdev, "Link down\n"); | |
f62b8bb8 | 89 | netif_carrier_off(priv->netdev); |
87424ad5 | 90 | } |
f62b8bb8 AV |
91 | } |
92 | ||
93 | static void mlx5e_update_carrier_work(struct work_struct *work) | |
94 | { | |
95 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
96 | update_carrier_work); | |
97 | ||
98 | mutex_lock(&priv->state_lock); | |
99 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
100 | mlx5e_update_carrier(priv); | |
101 | mutex_unlock(&priv->state_lock); | |
102 | } | |
103 | ||
3947ca18 DJ |
104 | static void mlx5e_tx_timeout_work(struct work_struct *work) |
105 | { | |
106 | struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv, | |
107 | tx_timeout_work); | |
108 | int err; | |
109 | ||
110 | rtnl_lock(); | |
111 | mutex_lock(&priv->state_lock); | |
112 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
113 | goto unlock; | |
114 | mlx5e_close_locked(priv->netdev); | |
115 | err = mlx5e_open_locked(priv->netdev); | |
116 | if (err) | |
117 | netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n", | |
118 | err); | |
119 | unlock: | |
120 | mutex_unlock(&priv->state_lock); | |
121 | rtnl_unlock(); | |
122 | } | |
123 | ||
9218b44d | 124 | static void mlx5e_update_sw_counters(struct mlx5e_priv *priv) |
f62b8bb8 | 125 | { |
9218b44d | 126 | struct mlx5e_sw_stats *s = &priv->stats.sw; |
f62b8bb8 AV |
127 | struct mlx5e_rq_stats *rq_stats; |
128 | struct mlx5e_sq_stats *sq_stats; | |
9218b44d | 129 | u64 tx_offload_none = 0; |
f62b8bb8 AV |
130 | int i, j; |
131 | ||
9218b44d | 132 | memset(s, 0, sizeof(*s)); |
f62b8bb8 AV |
133 | for (i = 0; i < priv->params.num_channels; i++) { |
134 | rq_stats = &priv->channel[i]->rq.stats; | |
135 | ||
faf4478b GP |
136 | s->rx_packets += rq_stats->packets; |
137 | s->rx_bytes += rq_stats->bytes; | |
bfe6d8d1 GP |
138 | s->rx_lro_packets += rq_stats->lro_packets; |
139 | s->rx_lro_bytes += rq_stats->lro_bytes; | |
f62b8bb8 | 140 | s->rx_csum_none += rq_stats->csum_none; |
bfe6d8d1 GP |
141 | s->rx_csum_complete += rq_stats->csum_complete; |
142 | s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner; | |
f62b8bb8 | 143 | s->rx_wqe_err += rq_stats->wqe_err; |
461017cb | 144 | s->rx_mpwqe_filler += rq_stats->mpwqe_filler; |
bc77b240 | 145 | s->rx_mpwqe_frag += rq_stats->mpwqe_frag; |
54984407 | 146 | s->rx_buff_alloc_err += rq_stats->buff_alloc_err; |
7219ab34 TT |
147 | s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks; |
148 | s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts; | |
f62b8bb8 | 149 | |
a4418a6c | 150 | for (j = 0; j < priv->params.num_tc; j++) { |
f62b8bb8 AV |
151 | sq_stats = &priv->channel[i]->sq[j].stats; |
152 | ||
faf4478b GP |
153 | s->tx_packets += sq_stats->packets; |
154 | s->tx_bytes += sq_stats->bytes; | |
bfe6d8d1 GP |
155 | s->tx_tso_packets += sq_stats->tso_packets; |
156 | s->tx_tso_bytes += sq_stats->tso_bytes; | |
157 | s->tx_tso_inner_packets += sq_stats->tso_inner_packets; | |
158 | s->tx_tso_inner_bytes += sq_stats->tso_inner_bytes; | |
f62b8bb8 AV |
159 | s->tx_queue_stopped += sq_stats->stopped; |
160 | s->tx_queue_wake += sq_stats->wake; | |
161 | s->tx_queue_dropped += sq_stats->dropped; | |
bfe6d8d1 GP |
162 | s->tx_csum_partial_inner += sq_stats->csum_partial_inner; |
163 | tx_offload_none += sq_stats->csum_none; | |
f62b8bb8 AV |
164 | } |
165 | } | |
166 | ||
9218b44d | 167 | /* Update calculated offload counters */ |
bfe6d8d1 GP |
168 | s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner; |
169 | s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete; | |
121fcdc8 | 170 | |
bfe6d8d1 | 171 | s->link_down_events_phy = MLX5_GET(ppcnt_reg, |
121fcdc8 GP |
172 | priv->stats.pport.phy_counters, |
173 | counter_set.phys_layer_cntrs.link_down_events); | |
9218b44d GP |
174 | } |
175 | ||
176 | static void mlx5e_update_vport_counters(struct mlx5e_priv *priv) | |
177 | { | |
178 | int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out); | |
179 | u32 *out = (u32 *)priv->stats.vport.query_vport_out; | |
180 | u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)]; | |
181 | struct mlx5_core_dev *mdev = priv->mdev; | |
182 | ||
f62b8bb8 AV |
183 | memset(in, 0, sizeof(in)); |
184 | ||
185 | MLX5_SET(query_vport_counter_in, in, opcode, | |
186 | MLX5_CMD_OP_QUERY_VPORT_COUNTER); | |
187 | MLX5_SET(query_vport_counter_in, in, op_mod, 0); | |
188 | MLX5_SET(query_vport_counter_in, in, other_vport, 0); | |
189 | ||
190 | memset(out, 0, outlen); | |
191 | ||
9218b44d GP |
192 | mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen); |
193 | } | |
194 | ||
195 | static void mlx5e_update_pport_counters(struct mlx5e_priv *priv) | |
196 | { | |
197 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; | |
198 | struct mlx5_core_dev *mdev = priv->mdev; | |
199 | int sz = MLX5_ST_SZ_BYTES(ppcnt_reg); | |
cf678570 | 200 | int prio; |
9218b44d GP |
201 | void *out; |
202 | u32 *in; | |
203 | ||
204 | in = mlx5_vzalloc(sz); | |
205 | if (!in) | |
f62b8bb8 AV |
206 | goto free_out; |
207 | ||
9218b44d | 208 | MLX5_SET(ppcnt_reg, in, local_port, 1); |
f62b8bb8 | 209 | |
9218b44d GP |
210 | out = pstats->IEEE_802_3_counters; |
211 | MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP); | |
212 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
f62b8bb8 | 213 | |
9218b44d GP |
214 | out = pstats->RFC_2863_counters; |
215 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP); | |
216 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
217 | ||
218 | out = pstats->RFC_2819_counters; | |
219 | MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP); | |
220 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
593cf338 | 221 | |
121fcdc8 GP |
222 | out = pstats->phy_counters; |
223 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP); | |
224 | mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0); | |
225 | ||
cf678570 GP |
226 | MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP); |
227 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { | |
228 | out = pstats->per_prio_counters[prio]; | |
229 | MLX5_SET(ppcnt_reg, in, prio_tc, prio); | |
230 | mlx5_core_access_reg(mdev, in, sz, out, sz, | |
231 | MLX5_REG_PPCNT, 0, 0); | |
232 | } | |
233 | ||
f62b8bb8 | 234 | free_out: |
9218b44d GP |
235 | kvfree(in); |
236 | } | |
237 | ||
238 | static void mlx5e_update_q_counter(struct mlx5e_priv *priv) | |
239 | { | |
240 | struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt; | |
241 | ||
242 | if (!priv->q_counter) | |
243 | return; | |
244 | ||
245 | mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter, | |
246 | &qcnt->rx_out_of_buffer); | |
247 | } | |
248 | ||
249 | void mlx5e_update_stats(struct mlx5e_priv *priv) | |
250 | { | |
9218b44d GP |
251 | mlx5e_update_q_counter(priv); |
252 | mlx5e_update_vport_counters(priv); | |
253 | mlx5e_update_pport_counters(priv); | |
121fcdc8 | 254 | mlx5e_update_sw_counters(priv); |
f62b8bb8 AV |
255 | } |
256 | ||
257 | static void mlx5e_update_stats_work(struct work_struct *work) | |
258 | { | |
259 | struct delayed_work *dwork = to_delayed_work(work); | |
260 | struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv, | |
261 | update_stats_work); | |
262 | mutex_lock(&priv->state_lock); | |
263 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) { | |
264 | mlx5e_update_stats(priv); | |
7bb29755 MF |
265 | queue_delayed_work(priv->wq, dwork, |
266 | msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL)); | |
f62b8bb8 AV |
267 | } |
268 | mutex_unlock(&priv->state_lock); | |
269 | } | |
270 | ||
daa21560 TT |
271 | static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv, |
272 | enum mlx5_dev_event event, unsigned long param) | |
f62b8bb8 | 273 | { |
daa21560 TT |
274 | struct mlx5e_priv *priv = vpriv; |
275 | ||
e0f46eb9 | 276 | if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state)) |
daa21560 TT |
277 | return; |
278 | ||
f62b8bb8 AV |
279 | switch (event) { |
280 | case MLX5_DEV_EVENT_PORT_UP: | |
281 | case MLX5_DEV_EVENT_PORT_DOWN: | |
7bb29755 | 282 | queue_work(priv->wq, &priv->update_carrier_work); |
f62b8bb8 AV |
283 | break; |
284 | ||
285 | default: | |
286 | break; | |
287 | } | |
288 | } | |
289 | ||
f62b8bb8 AV |
290 | static void mlx5e_enable_async_events(struct mlx5e_priv *priv) |
291 | { | |
e0f46eb9 | 292 | set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
f62b8bb8 AV |
293 | } |
294 | ||
295 | static void mlx5e_disable_async_events(struct mlx5e_priv *priv) | |
296 | { | |
e0f46eb9 | 297 | clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state); |
daa21560 | 298 | synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC)); |
f62b8bb8 AV |
299 | } |
300 | ||
facc9699 SM |
301 | #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) |
302 | #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)) | |
303 | ||
f62b8bb8 AV |
304 | static int mlx5e_create_rq(struct mlx5e_channel *c, |
305 | struct mlx5e_rq_param *param, | |
306 | struct mlx5e_rq *rq) | |
307 | { | |
308 | struct mlx5e_priv *priv = c->priv; | |
309 | struct mlx5_core_dev *mdev = priv->mdev; | |
310 | void *rqc = param->rqc; | |
311 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
461017cb | 312 | u32 byte_count; |
f62b8bb8 AV |
313 | int wq_sz; |
314 | int err; | |
315 | int i; | |
316 | ||
311c7c71 SM |
317 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
318 | ||
f62b8bb8 AV |
319 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, |
320 | &rq->wq_ctrl); | |
321 | if (err) | |
322 | return err; | |
323 | ||
324 | rq->wq.db = &rq->wq.db[MLX5_RCV_DBR]; | |
325 | ||
326 | wq_sz = mlx5_wq_ll_get_size(&rq->wq); | |
f62b8bb8 | 327 | |
461017cb TT |
328 | switch (priv->params.rq_wq_type) { |
329 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
330 | rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info), | |
331 | GFP_KERNEL, cpu_to_node(c->cpu)); | |
332 | if (!rq->wqe_info) { | |
333 | err = -ENOMEM; | |
334 | goto err_rq_wq_destroy; | |
335 | } | |
336 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq; | |
337 | rq->alloc_wqe = mlx5e_alloc_rx_mpwqe; | |
6cd392a0 | 338 | rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe; |
461017cb | 339 | |
d9d9f156 TT |
340 | rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz); |
341 | rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides); | |
342 | rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides; | |
461017cb TT |
343 | byte_count = rq->wqe_sz; |
344 | break; | |
345 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
346 | rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL, | |
347 | cpu_to_node(c->cpu)); | |
348 | if (!rq->skb) { | |
349 | err = -ENOMEM; | |
350 | goto err_rq_wq_destroy; | |
351 | } | |
352 | rq->handle_rx_cqe = mlx5e_handle_rx_cqe; | |
353 | rq->alloc_wqe = mlx5e_alloc_rx_wqe; | |
6cd392a0 | 354 | rq->dealloc_wqe = mlx5e_dealloc_rx_wqe; |
461017cb TT |
355 | |
356 | rq->wqe_sz = (priv->params.lro_en) ? | |
357 | priv->params.lro_wqe_sz : | |
358 | MLX5E_SW2HW_MTU(priv->netdev->mtu); | |
c5adb96f TT |
359 | rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz); |
360 | byte_count = rq->wqe_sz; | |
461017cb TT |
361 | byte_count |= MLX5_HW_START_PADDING; |
362 | } | |
f62b8bb8 AV |
363 | |
364 | for (i = 0; i < wq_sz; i++) { | |
365 | struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i); | |
366 | ||
461017cb | 367 | wqe->data.byte_count = cpu_to_be32(byte_count); |
f62b8bb8 AV |
368 | } |
369 | ||
461017cb | 370 | rq->wq_type = priv->params.rq_wq_type; |
f62b8bb8 AV |
371 | rq->pdev = c->pdev; |
372 | rq->netdev = c->netdev; | |
ef9814de | 373 | rq->tstamp = &priv->tstamp; |
f62b8bb8 AV |
374 | rq->channel = c; |
375 | rq->ix = c->ix; | |
50cfa25a | 376 | rq->priv = c->priv; |
bc77b240 TT |
377 | rq->mkey_be = c->mkey_be; |
378 | rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key); | |
f62b8bb8 AV |
379 | |
380 | return 0; | |
381 | ||
382 | err_rq_wq_destroy: | |
383 | mlx5_wq_destroy(&rq->wq_ctrl); | |
384 | ||
385 | return err; | |
386 | } | |
387 | ||
388 | static void mlx5e_destroy_rq(struct mlx5e_rq *rq) | |
389 | { | |
461017cb TT |
390 | switch (rq->wq_type) { |
391 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
392 | kfree(rq->wqe_info); | |
393 | break; | |
394 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
395 | kfree(rq->skb); | |
396 | } | |
397 | ||
f62b8bb8 AV |
398 | mlx5_wq_destroy(&rq->wq_ctrl); |
399 | } | |
400 | ||
401 | static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param) | |
402 | { | |
50cfa25a | 403 | struct mlx5e_priv *priv = rq->priv; |
f62b8bb8 AV |
404 | struct mlx5_core_dev *mdev = priv->mdev; |
405 | ||
406 | void *in; | |
407 | void *rqc; | |
408 | void *wq; | |
409 | int inlen; | |
410 | int err; | |
411 | ||
412 | inlen = MLX5_ST_SZ_BYTES(create_rq_in) + | |
413 | sizeof(u64) * rq->wq_ctrl.buf.npages; | |
414 | in = mlx5_vzalloc(inlen); | |
415 | if (!in) | |
416 | return -ENOMEM; | |
417 | ||
418 | rqc = MLX5_ADDR_OF(create_rq_in, in, ctx); | |
419 | wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
420 | ||
421 | memcpy(rqc, param->rqc, sizeof(param->rqc)); | |
422 | ||
97de9f31 | 423 | MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn); |
f62b8bb8 AV |
424 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST); |
425 | MLX5_SET(rqc, rqc, flush_in_error_en, 1); | |
36350114 | 426 | MLX5_SET(rqc, rqc, vsd, priv->params.vlan_strip_disable); |
f62b8bb8 | 427 | MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift - |
68cdf5d6 | 428 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
429 | MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma); |
430 | ||
431 | mlx5_fill_page_array(&rq->wq_ctrl.buf, | |
432 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
433 | ||
7db22ffb | 434 | err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn); |
f62b8bb8 AV |
435 | |
436 | kvfree(in); | |
437 | ||
438 | return err; | |
439 | } | |
440 | ||
36350114 GP |
441 | static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, |
442 | int next_state) | |
f62b8bb8 AV |
443 | { |
444 | struct mlx5e_channel *c = rq->channel; | |
445 | struct mlx5e_priv *priv = c->priv; | |
446 | struct mlx5_core_dev *mdev = priv->mdev; | |
447 | ||
448 | void *in; | |
449 | void *rqc; | |
450 | int inlen; | |
451 | int err; | |
452 | ||
453 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
454 | in = mlx5_vzalloc(inlen); | |
455 | if (!in) | |
456 | return -ENOMEM; | |
457 | ||
458 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
459 | ||
460 | MLX5_SET(modify_rq_in, in, rq_state, curr_state); | |
461 | MLX5_SET(rqc, rqc, state, next_state); | |
462 | ||
7db22ffb | 463 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); |
f62b8bb8 AV |
464 | |
465 | kvfree(in); | |
466 | ||
467 | return err; | |
468 | } | |
469 | ||
36350114 GP |
470 | static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd) |
471 | { | |
472 | struct mlx5e_channel *c = rq->channel; | |
473 | struct mlx5e_priv *priv = c->priv; | |
474 | struct mlx5_core_dev *mdev = priv->mdev; | |
475 | ||
476 | void *in; | |
477 | void *rqc; | |
478 | int inlen; | |
479 | int err; | |
480 | ||
481 | inlen = MLX5_ST_SZ_BYTES(modify_rq_in); | |
482 | in = mlx5_vzalloc(inlen); | |
483 | if (!in) | |
484 | return -ENOMEM; | |
485 | ||
486 | rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx); | |
487 | ||
488 | MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY); | |
489 | MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD); | |
490 | MLX5_SET(rqc, rqc, vsd, vsd); | |
491 | MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY); | |
492 | ||
493 | err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen); | |
494 | ||
495 | kvfree(in); | |
496 | ||
497 | return err; | |
498 | } | |
499 | ||
f62b8bb8 AV |
500 | static void mlx5e_disable_rq(struct mlx5e_rq *rq) |
501 | { | |
50cfa25a | 502 | mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn); |
f62b8bb8 AV |
503 | } |
504 | ||
505 | static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq) | |
506 | { | |
01c196a2 | 507 | unsigned long exp_time = jiffies + msecs_to_jiffies(20000); |
f62b8bb8 AV |
508 | struct mlx5e_channel *c = rq->channel; |
509 | struct mlx5e_priv *priv = c->priv; | |
510 | struct mlx5_wq_ll *wq = &rq->wq; | |
f62b8bb8 | 511 | |
01c196a2 | 512 | while (time_before(jiffies, exp_time)) { |
f62b8bb8 AV |
513 | if (wq->cur_sz >= priv->params.min_rx_wqes) |
514 | return 0; | |
515 | ||
516 | msleep(20); | |
517 | } | |
518 | ||
519 | return -ETIMEDOUT; | |
520 | } | |
521 | ||
522 | static int mlx5e_open_rq(struct mlx5e_channel *c, | |
523 | struct mlx5e_rq_param *param, | |
524 | struct mlx5e_rq *rq) | |
525 | { | |
d3c9bc27 TT |
526 | struct mlx5e_sq *sq = &c->icosq; |
527 | u16 pi = sq->pc & sq->wq.sz_m1; | |
f62b8bb8 AV |
528 | int err; |
529 | ||
530 | err = mlx5e_create_rq(c, param, rq); | |
531 | if (err) | |
532 | return err; | |
533 | ||
534 | err = mlx5e_enable_rq(rq, param); | |
535 | if (err) | |
536 | goto err_destroy_rq; | |
537 | ||
36350114 | 538 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY); |
f62b8bb8 AV |
539 | if (err) |
540 | goto err_disable_rq; | |
541 | ||
542 | set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); | |
d3c9bc27 TT |
543 | |
544 | sq->ico_wqe_info[pi].opcode = MLX5_OPCODE_NOP; | |
545 | sq->ico_wqe_info[pi].num_wqebbs = 1; | |
546 | mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */ | |
f62b8bb8 AV |
547 | |
548 | return 0; | |
549 | ||
550 | err_disable_rq: | |
551 | mlx5e_disable_rq(rq); | |
552 | err_destroy_rq: | |
553 | mlx5e_destroy_rq(rq); | |
554 | ||
555 | return err; | |
556 | } | |
557 | ||
558 | static void mlx5e_close_rq(struct mlx5e_rq *rq) | |
559 | { | |
6cd392a0 DJ |
560 | int tout = 0; |
561 | int err; | |
562 | ||
f62b8bb8 AV |
563 | clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state); |
564 | napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */ | |
565 | ||
6cd392a0 DJ |
566 | err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR); |
567 | while (!mlx5_wq_ll_is_empty(&rq->wq) && !err && | |
568 | tout++ < MLX5_EN_QP_FLUSH_MAX_ITER) | |
569 | msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT); | |
570 | ||
571 | if (err || tout == MLX5_EN_QP_FLUSH_MAX_ITER) | |
572 | set_bit(MLX5E_RQ_STATE_FLUSH_TIMEOUT, &rq->state); | |
f62b8bb8 AV |
573 | |
574 | /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */ | |
575 | napi_synchronize(&rq->channel->napi); | |
576 | ||
577 | mlx5e_disable_rq(rq); | |
6cd392a0 | 578 | mlx5e_free_rx_descs(rq); |
f62b8bb8 AV |
579 | mlx5e_destroy_rq(rq); |
580 | } | |
581 | ||
582 | static void mlx5e_free_sq_db(struct mlx5e_sq *sq) | |
583 | { | |
34802a42 | 584 | kfree(sq->wqe_info); |
f62b8bb8 AV |
585 | kfree(sq->dma_fifo); |
586 | kfree(sq->skb); | |
587 | } | |
588 | ||
589 | static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa) | |
590 | { | |
591 | int wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
592 | int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS; | |
593 | ||
594 | sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa); | |
595 | sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL, | |
596 | numa); | |
34802a42 AS |
597 | sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL, |
598 | numa); | |
f62b8bb8 | 599 | |
34802a42 | 600 | if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) { |
f62b8bb8 AV |
601 | mlx5e_free_sq_db(sq); |
602 | return -ENOMEM; | |
603 | } | |
604 | ||
605 | sq->dma_fifo_mask = df_sz - 1; | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
610 | static int mlx5e_create_sq(struct mlx5e_channel *c, | |
611 | int tc, | |
612 | struct mlx5e_sq_param *param, | |
613 | struct mlx5e_sq *sq) | |
614 | { | |
615 | struct mlx5e_priv *priv = c->priv; | |
616 | struct mlx5_core_dev *mdev = priv->mdev; | |
617 | ||
618 | void *sqc = param->sqc; | |
619 | void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
620 | int err; | |
621 | ||
fd4782c2 | 622 | err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf)); |
f62b8bb8 AV |
623 | if (err) |
624 | return err; | |
625 | ||
311c7c71 SM |
626 | param->wq.db_numa_node = cpu_to_node(c->cpu); |
627 | ||
f62b8bb8 AV |
628 | err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, |
629 | &sq->wq_ctrl); | |
630 | if (err) | |
631 | goto err_unmap_free_uar; | |
632 | ||
633 | sq->wq.db = &sq->wq.db[MLX5_SND_DBR]; | |
0ba42241 ML |
634 | if (sq->uar.bf_map) { |
635 | set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state); | |
636 | sq->uar_map = sq->uar.bf_map; | |
637 | } else { | |
638 | sq->uar_map = sq->uar.map; | |
639 | } | |
f62b8bb8 | 640 | sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; |
58d52291 | 641 | sq->max_inline = param->max_inline; |
f62b8bb8 | 642 | |
7ec0bb22 DC |
643 | err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu)); |
644 | if (err) | |
f62b8bb8 AV |
645 | goto err_sq_wq_destroy; |
646 | ||
d3c9bc27 TT |
647 | if (param->icosq) { |
648 | u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq); | |
649 | ||
650 | sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) * | |
651 | wq_sz, | |
652 | GFP_KERNEL, | |
653 | cpu_to_node(c->cpu)); | |
654 | if (!sq->ico_wqe_info) { | |
655 | err = -ENOMEM; | |
656 | goto err_free_sq_db; | |
657 | } | |
658 | } else { | |
659 | int txq_ix; | |
660 | ||
661 | txq_ix = c->ix + tc * priv->params.num_channels; | |
662 | sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix); | |
663 | priv->txq_to_sq_map[txq_ix] = sq; | |
664 | } | |
f62b8bb8 | 665 | |
88a85f99 | 666 | sq->pdev = c->pdev; |
ef9814de | 667 | sq->tstamp = &priv->tstamp; |
88a85f99 AS |
668 | sq->mkey_be = c->mkey_be; |
669 | sq->channel = c; | |
670 | sq->tc = tc; | |
671 | sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS; | |
672 | sq->bf_budget = MLX5E_SQ_BF_BUDGET; | |
f62b8bb8 AV |
673 | |
674 | return 0; | |
675 | ||
d3c9bc27 TT |
676 | err_free_sq_db: |
677 | mlx5e_free_sq_db(sq); | |
678 | ||
f62b8bb8 AV |
679 | err_sq_wq_destroy: |
680 | mlx5_wq_destroy(&sq->wq_ctrl); | |
681 | ||
682 | err_unmap_free_uar: | |
683 | mlx5_unmap_free_uar(mdev, &sq->uar); | |
684 | ||
685 | return err; | |
686 | } | |
687 | ||
688 | static void mlx5e_destroy_sq(struct mlx5e_sq *sq) | |
689 | { | |
690 | struct mlx5e_channel *c = sq->channel; | |
691 | struct mlx5e_priv *priv = c->priv; | |
692 | ||
d3c9bc27 | 693 | kfree(sq->ico_wqe_info); |
f62b8bb8 AV |
694 | mlx5e_free_sq_db(sq); |
695 | mlx5_wq_destroy(&sq->wq_ctrl); | |
696 | mlx5_unmap_free_uar(priv->mdev, &sq->uar); | |
697 | } | |
698 | ||
699 | static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) | |
700 | { | |
701 | struct mlx5e_channel *c = sq->channel; | |
702 | struct mlx5e_priv *priv = c->priv; | |
703 | struct mlx5_core_dev *mdev = priv->mdev; | |
704 | ||
705 | void *in; | |
706 | void *sqc; | |
707 | void *wq; | |
708 | int inlen; | |
709 | int err; | |
710 | ||
711 | inlen = MLX5_ST_SZ_BYTES(create_sq_in) + | |
712 | sizeof(u64) * sq->wq_ctrl.buf.npages; | |
713 | in = mlx5_vzalloc(inlen); | |
714 | if (!in) | |
715 | return -ENOMEM; | |
716 | ||
717 | sqc = MLX5_ADDR_OF(create_sq_in, in, ctx); | |
718 | wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
719 | ||
720 | memcpy(sqc, param->sqc, sizeof(param->sqc)); | |
721 | ||
d3c9bc27 TT |
722 | MLX5_SET(sqc, sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]); |
723 | MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn); | |
f62b8bb8 | 724 | MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST); |
d3c9bc27 | 725 | MLX5_SET(sqc, sqc, tis_lst_sz, param->icosq ? 0 : 1); |
f62b8bb8 AV |
726 | MLX5_SET(sqc, sqc, flush_in_error_en, 1); |
727 | ||
728 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC); | |
729 | MLX5_SET(wq, wq, uar_page, sq->uar.index); | |
730 | MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 731 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
732 | MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma); |
733 | ||
734 | mlx5_fill_page_array(&sq->wq_ctrl.buf, | |
735 | (__be64 *)MLX5_ADDR_OF(wq, wq, pas)); | |
736 | ||
7db22ffb | 737 | err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn); |
f62b8bb8 AV |
738 | |
739 | kvfree(in); | |
740 | ||
741 | return err; | |
742 | } | |
743 | ||
744 | static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) | |
745 | { | |
746 | struct mlx5e_channel *c = sq->channel; | |
747 | struct mlx5e_priv *priv = c->priv; | |
748 | struct mlx5_core_dev *mdev = priv->mdev; | |
749 | ||
750 | void *in; | |
751 | void *sqc; | |
752 | int inlen; | |
753 | int err; | |
754 | ||
755 | inlen = MLX5_ST_SZ_BYTES(modify_sq_in); | |
756 | in = mlx5_vzalloc(inlen); | |
757 | if (!in) | |
758 | return -ENOMEM; | |
759 | ||
760 | sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx); | |
761 | ||
762 | MLX5_SET(modify_sq_in, in, sq_state, curr_state); | |
763 | MLX5_SET(sqc, sqc, state, next_state); | |
764 | ||
7db22ffb | 765 | err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen); |
f62b8bb8 AV |
766 | |
767 | kvfree(in); | |
768 | ||
769 | return err; | |
770 | } | |
771 | ||
772 | static void mlx5e_disable_sq(struct mlx5e_sq *sq) | |
773 | { | |
774 | struct mlx5e_channel *c = sq->channel; | |
775 | struct mlx5e_priv *priv = c->priv; | |
776 | struct mlx5_core_dev *mdev = priv->mdev; | |
777 | ||
7db22ffb | 778 | mlx5_core_destroy_sq(mdev, sq->sqn); |
f62b8bb8 AV |
779 | } |
780 | ||
781 | static int mlx5e_open_sq(struct mlx5e_channel *c, | |
782 | int tc, | |
783 | struct mlx5e_sq_param *param, | |
784 | struct mlx5e_sq *sq) | |
785 | { | |
786 | int err; | |
787 | ||
788 | err = mlx5e_create_sq(c, tc, param, sq); | |
789 | if (err) | |
790 | return err; | |
791 | ||
792 | err = mlx5e_enable_sq(sq, param); | |
793 | if (err) | |
794 | goto err_destroy_sq; | |
795 | ||
796 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY); | |
797 | if (err) | |
798 | goto err_disable_sq; | |
799 | ||
d3c9bc27 TT |
800 | if (sq->txq) { |
801 | set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
802 | netdev_tx_reset_queue(sq->txq); | |
803 | netif_tx_start_queue(sq->txq); | |
804 | } | |
f62b8bb8 AV |
805 | |
806 | return 0; | |
807 | ||
808 | err_disable_sq: | |
809 | mlx5e_disable_sq(sq); | |
810 | err_destroy_sq: | |
811 | mlx5e_destroy_sq(sq); | |
812 | ||
813 | return err; | |
814 | } | |
815 | ||
816 | static inline void netif_tx_disable_queue(struct netdev_queue *txq) | |
817 | { | |
818 | __netif_tx_lock_bh(txq); | |
819 | netif_tx_stop_queue(txq); | |
820 | __netif_tx_unlock_bh(txq); | |
821 | } | |
822 | ||
823 | static void mlx5e_close_sq(struct mlx5e_sq *sq) | |
824 | { | |
29429f33 DJ |
825 | int tout = 0; |
826 | int err; | |
827 | ||
d3c9bc27 TT |
828 | if (sq->txq) { |
829 | clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state); | |
830 | /* prevent netif_tx_wake_queue */ | |
831 | napi_synchronize(&sq->channel->napi); | |
832 | netif_tx_disable_queue(sq->txq); | |
f62b8bb8 | 833 | |
d3c9bc27 TT |
834 | /* ensure hw is notified of all pending wqes */ |
835 | if (mlx5e_sq_has_room_for(sq, 1)) | |
836 | mlx5e_send_nop(sq, true); | |
837 | ||
29429f33 DJ |
838 | err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, |
839 | MLX5_SQC_STATE_ERR); | |
840 | if (err) | |
841 | set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state); | |
d3c9bc27 | 842 | } |
f62b8bb8 | 843 | |
29429f33 DJ |
844 | /* wait till sq is empty, unless a TX timeout occurred on this SQ */ |
845 | while (sq->cc != sq->pc && | |
846 | !test_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state)) { | |
847 | msleep(MLX5_EN_QP_FLUSH_MSLEEP_QUANT); | |
848 | if (tout++ > MLX5_EN_QP_FLUSH_MAX_ITER) | |
849 | set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state); | |
850 | } | |
f62b8bb8 AV |
851 | |
852 | /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */ | |
853 | napi_synchronize(&sq->channel->napi); | |
854 | ||
29429f33 | 855 | mlx5e_free_tx_descs(sq); |
f62b8bb8 AV |
856 | mlx5e_disable_sq(sq); |
857 | mlx5e_destroy_sq(sq); | |
858 | } | |
859 | ||
860 | static int mlx5e_create_cq(struct mlx5e_channel *c, | |
861 | struct mlx5e_cq_param *param, | |
862 | struct mlx5e_cq *cq) | |
863 | { | |
864 | struct mlx5e_priv *priv = c->priv; | |
865 | struct mlx5_core_dev *mdev = priv->mdev; | |
866 | struct mlx5_core_cq *mcq = &cq->mcq; | |
867 | int eqn_not_used; | |
0b6e26ce | 868 | unsigned int irqn; |
f62b8bb8 AV |
869 | int err; |
870 | u32 i; | |
871 | ||
311c7c71 SM |
872 | param->wq.buf_numa_node = cpu_to_node(c->cpu); |
873 | param->wq.db_numa_node = cpu_to_node(c->cpu); | |
f62b8bb8 AV |
874 | param->eq_ix = c->ix; |
875 | ||
876 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
877 | &cq->wq_ctrl); | |
878 | if (err) | |
879 | return err; | |
880 | ||
881 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
882 | ||
883 | cq->napi = &c->napi; | |
884 | ||
885 | mcq->cqe_sz = 64; | |
886 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
887 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
888 | *mcq->set_ci_db = 0; | |
889 | *mcq->arm_db = 0; | |
890 | mcq->vector = param->eq_ix; | |
891 | mcq->comp = mlx5e_completion_event; | |
892 | mcq->event = mlx5e_cq_error_event; | |
893 | mcq->irqn = irqn; | |
894 | mcq->uar = &priv->cq_uar; | |
895 | ||
896 | for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) { | |
897 | struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i); | |
898 | ||
899 | cqe->op_own = 0xf1; | |
900 | } | |
901 | ||
902 | cq->channel = c; | |
50cfa25a | 903 | cq->priv = priv; |
f62b8bb8 AV |
904 | |
905 | return 0; | |
906 | } | |
907 | ||
908 | static void mlx5e_destroy_cq(struct mlx5e_cq *cq) | |
909 | { | |
910 | mlx5_wq_destroy(&cq->wq_ctrl); | |
911 | } | |
912 | ||
913 | static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) | |
914 | { | |
50cfa25a | 915 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
916 | struct mlx5_core_dev *mdev = priv->mdev; |
917 | struct mlx5_core_cq *mcq = &cq->mcq; | |
918 | ||
919 | void *in; | |
920 | void *cqc; | |
921 | int inlen; | |
0b6e26ce | 922 | unsigned int irqn_not_used; |
f62b8bb8 AV |
923 | int eqn; |
924 | int err; | |
925 | ||
926 | inlen = MLX5_ST_SZ_BYTES(create_cq_in) + | |
927 | sizeof(u64) * cq->wq_ctrl.buf.npages; | |
928 | in = mlx5_vzalloc(inlen); | |
929 | if (!in) | |
930 | return -ENOMEM; | |
931 | ||
932 | cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context); | |
933 | ||
934 | memcpy(cqc, param->cqc, sizeof(param->cqc)); | |
935 | ||
936 | mlx5_fill_page_array(&cq->wq_ctrl.buf, | |
937 | (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas)); | |
938 | ||
939 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used); | |
940 | ||
941 | MLX5_SET(cqc, cqc, c_eqn, eqn); | |
942 | MLX5_SET(cqc, cqc, uar_page, mcq->uar->index); | |
943 | MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift - | |
68cdf5d6 | 944 | MLX5_ADAPTER_PAGE_SHIFT); |
f62b8bb8 AV |
945 | MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma); |
946 | ||
947 | err = mlx5_core_create_cq(mdev, mcq, in, inlen); | |
948 | ||
949 | kvfree(in); | |
950 | ||
951 | if (err) | |
952 | return err; | |
953 | ||
954 | mlx5e_cq_arm(cq); | |
955 | ||
956 | return 0; | |
957 | } | |
958 | ||
959 | static void mlx5e_disable_cq(struct mlx5e_cq *cq) | |
960 | { | |
50cfa25a | 961 | struct mlx5e_priv *priv = cq->priv; |
f62b8bb8 AV |
962 | struct mlx5_core_dev *mdev = priv->mdev; |
963 | ||
964 | mlx5_core_destroy_cq(mdev, &cq->mcq); | |
965 | } | |
966 | ||
967 | static int mlx5e_open_cq(struct mlx5e_channel *c, | |
968 | struct mlx5e_cq_param *param, | |
969 | struct mlx5e_cq *cq, | |
970 | u16 moderation_usecs, | |
971 | u16 moderation_frames) | |
972 | { | |
973 | int err; | |
974 | struct mlx5e_priv *priv = c->priv; | |
975 | struct mlx5_core_dev *mdev = priv->mdev; | |
976 | ||
977 | err = mlx5e_create_cq(c, param, cq); | |
978 | if (err) | |
979 | return err; | |
980 | ||
981 | err = mlx5e_enable_cq(cq, param); | |
982 | if (err) | |
983 | goto err_destroy_cq; | |
984 | ||
7524a5d8 GP |
985 | if (MLX5_CAP_GEN(mdev, cq_moderation)) |
986 | mlx5_core_modify_cq_moderation(mdev, &cq->mcq, | |
987 | moderation_usecs, | |
988 | moderation_frames); | |
f62b8bb8 AV |
989 | return 0; |
990 | ||
991 | err_destroy_cq: | |
992 | mlx5e_destroy_cq(cq); | |
993 | ||
994 | return err; | |
995 | } | |
996 | ||
997 | static void mlx5e_close_cq(struct mlx5e_cq *cq) | |
998 | { | |
999 | mlx5e_disable_cq(cq); | |
1000 | mlx5e_destroy_cq(cq); | |
1001 | } | |
1002 | ||
1003 | static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix) | |
1004 | { | |
1005 | return cpumask_first(priv->mdev->priv.irq_info[ix].mask); | |
1006 | } | |
1007 | ||
1008 | static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, | |
1009 | struct mlx5e_channel_param *cparam) | |
1010 | { | |
1011 | struct mlx5e_priv *priv = c->priv; | |
1012 | int err; | |
1013 | int tc; | |
1014 | ||
1015 | for (tc = 0; tc < c->num_tc; tc++) { | |
1016 | err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq, | |
1017 | priv->params.tx_cq_moderation_usec, | |
1018 | priv->params.tx_cq_moderation_pkts); | |
1019 | if (err) | |
1020 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1021 | } |
1022 | ||
1023 | return 0; | |
1024 | ||
1025 | err_close_tx_cqs: | |
1026 | for (tc--; tc >= 0; tc--) | |
1027 | mlx5e_close_cq(&c->sq[tc].cq); | |
1028 | ||
1029 | return err; | |
1030 | } | |
1031 | ||
1032 | static void mlx5e_close_tx_cqs(struct mlx5e_channel *c) | |
1033 | { | |
1034 | int tc; | |
1035 | ||
1036 | for (tc = 0; tc < c->num_tc; tc++) | |
1037 | mlx5e_close_cq(&c->sq[tc].cq); | |
1038 | } | |
1039 | ||
1040 | static int mlx5e_open_sqs(struct mlx5e_channel *c, | |
1041 | struct mlx5e_channel_param *cparam) | |
1042 | { | |
1043 | int err; | |
1044 | int tc; | |
1045 | ||
1046 | for (tc = 0; tc < c->num_tc; tc++) { | |
1047 | err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]); | |
1048 | if (err) | |
1049 | goto err_close_sqs; | |
1050 | } | |
1051 | ||
1052 | return 0; | |
1053 | ||
1054 | err_close_sqs: | |
1055 | for (tc--; tc >= 0; tc--) | |
1056 | mlx5e_close_sq(&c->sq[tc]); | |
1057 | ||
1058 | return err; | |
1059 | } | |
1060 | ||
1061 | static void mlx5e_close_sqs(struct mlx5e_channel *c) | |
1062 | { | |
1063 | int tc; | |
1064 | ||
1065 | for (tc = 0; tc < c->num_tc; tc++) | |
1066 | mlx5e_close_sq(&c->sq[tc]); | |
1067 | } | |
1068 | ||
5283af89 | 1069 | static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) |
03289b88 SM |
1070 | { |
1071 | int i; | |
1072 | ||
1073 | for (i = 0; i < MLX5E_MAX_NUM_TC; i++) | |
5283af89 RS |
1074 | priv->channeltc_to_txq_map[ix][i] = |
1075 | ix + i * priv->params.num_channels; | |
03289b88 SM |
1076 | } |
1077 | ||
f62b8bb8 AV |
1078 | static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, |
1079 | struct mlx5e_channel_param *cparam, | |
1080 | struct mlx5e_channel **cp) | |
1081 | { | |
1082 | struct net_device *netdev = priv->netdev; | |
1083 | int cpu = mlx5e_get_cpu(priv, ix); | |
1084 | struct mlx5e_channel *c; | |
1085 | int err; | |
1086 | ||
1087 | c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu)); | |
1088 | if (!c) | |
1089 | return -ENOMEM; | |
1090 | ||
1091 | c->priv = priv; | |
1092 | c->ix = ix; | |
1093 | c->cpu = cpu; | |
1094 | c->pdev = &priv->mdev->pdev->dev; | |
1095 | c->netdev = priv->netdev; | |
a606b0f6 | 1096 | c->mkey_be = cpu_to_be32(priv->mkey.key); |
a4418a6c | 1097 | c->num_tc = priv->params.num_tc; |
f62b8bb8 | 1098 | |
5283af89 | 1099 | mlx5e_build_channeltc_to_txq_map(priv, ix); |
03289b88 | 1100 | |
f62b8bb8 AV |
1101 | netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64); |
1102 | ||
d3c9bc27 | 1103 | err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0); |
f62b8bb8 AV |
1104 | if (err) |
1105 | goto err_napi_del; | |
1106 | ||
d3c9bc27 TT |
1107 | err = mlx5e_open_tx_cqs(c, cparam); |
1108 | if (err) | |
1109 | goto err_close_icosq_cq; | |
1110 | ||
f62b8bb8 AV |
1111 | err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq, |
1112 | priv->params.rx_cq_moderation_usec, | |
1113 | priv->params.rx_cq_moderation_pkts); | |
1114 | if (err) | |
1115 | goto err_close_tx_cqs; | |
f62b8bb8 AV |
1116 | |
1117 | napi_enable(&c->napi); | |
1118 | ||
d3c9bc27 | 1119 | err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq); |
f62b8bb8 AV |
1120 | if (err) |
1121 | goto err_disable_napi; | |
1122 | ||
d3c9bc27 TT |
1123 | err = mlx5e_open_sqs(c, cparam); |
1124 | if (err) | |
1125 | goto err_close_icosq; | |
1126 | ||
f62b8bb8 AV |
1127 | err = mlx5e_open_rq(c, &cparam->rq, &c->rq); |
1128 | if (err) | |
1129 | goto err_close_sqs; | |
1130 | ||
1131 | netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix); | |
1132 | *cp = c; | |
1133 | ||
1134 | return 0; | |
1135 | ||
1136 | err_close_sqs: | |
1137 | mlx5e_close_sqs(c); | |
1138 | ||
d3c9bc27 TT |
1139 | err_close_icosq: |
1140 | mlx5e_close_sq(&c->icosq); | |
1141 | ||
f62b8bb8 AV |
1142 | err_disable_napi: |
1143 | napi_disable(&c->napi); | |
1144 | mlx5e_close_cq(&c->rq.cq); | |
1145 | ||
1146 | err_close_tx_cqs: | |
1147 | mlx5e_close_tx_cqs(c); | |
1148 | ||
d3c9bc27 TT |
1149 | err_close_icosq_cq: |
1150 | mlx5e_close_cq(&c->icosq.cq); | |
1151 | ||
f62b8bb8 AV |
1152 | err_napi_del: |
1153 | netif_napi_del(&c->napi); | |
7ae92ae5 | 1154 | napi_hash_del(&c->napi); |
f62b8bb8 AV |
1155 | kfree(c); |
1156 | ||
1157 | return err; | |
1158 | } | |
1159 | ||
1160 | static void mlx5e_close_channel(struct mlx5e_channel *c) | |
1161 | { | |
1162 | mlx5e_close_rq(&c->rq); | |
1163 | mlx5e_close_sqs(c); | |
d3c9bc27 | 1164 | mlx5e_close_sq(&c->icosq); |
f62b8bb8 AV |
1165 | napi_disable(&c->napi); |
1166 | mlx5e_close_cq(&c->rq.cq); | |
1167 | mlx5e_close_tx_cqs(c); | |
d3c9bc27 | 1168 | mlx5e_close_cq(&c->icosq.cq); |
f62b8bb8 | 1169 | netif_napi_del(&c->napi); |
7ae92ae5 ED |
1170 | |
1171 | napi_hash_del(&c->napi); | |
1172 | synchronize_rcu(); | |
1173 | ||
f62b8bb8 AV |
1174 | kfree(c); |
1175 | } | |
1176 | ||
1177 | static void mlx5e_build_rq_param(struct mlx5e_priv *priv, | |
1178 | struct mlx5e_rq_param *param) | |
1179 | { | |
1180 | void *rqc = param->rqc; | |
1181 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1182 | ||
461017cb TT |
1183 | switch (priv->params.rq_wq_type) { |
1184 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1185 | MLX5_SET(wq, wq, log_wqe_num_of_strides, | |
d9d9f156 | 1186 | priv->params.mpwqe_log_num_strides - 9); |
461017cb | 1187 | MLX5_SET(wq, wq, log_wqe_stride_size, |
d9d9f156 | 1188 | priv->params.mpwqe_log_stride_sz - 6); |
461017cb TT |
1189 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ); |
1190 | break; | |
1191 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1192 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1193 | } | |
1194 | ||
f62b8bb8 AV |
1195 | MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN); |
1196 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1197 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size); | |
1198 | MLX5_SET(wq, wq, pd, priv->pdn); | |
593cf338 | 1199 | MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter); |
f62b8bb8 | 1200 | |
311c7c71 | 1201 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
f62b8bb8 AV |
1202 | param->wq.linear = 1; |
1203 | } | |
1204 | ||
556dd1b9 TT |
1205 | static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param) |
1206 | { | |
1207 | void *rqc = param->rqc; | |
1208 | void *wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1209 | ||
1210 | MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST); | |
1211 | MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe))); | |
1212 | } | |
1213 | ||
d3c9bc27 TT |
1214 | static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv, |
1215 | struct mlx5e_sq_param *param) | |
f62b8bb8 AV |
1216 | { |
1217 | void *sqc = param->sqc; | |
1218 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1219 | ||
f62b8bb8 AV |
1220 | MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB)); |
1221 | MLX5_SET(wq, wq, pd, priv->pdn); | |
1222 | ||
311c7c71 | 1223 | param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev); |
d3c9bc27 TT |
1224 | } |
1225 | ||
1226 | static void mlx5e_build_sq_param(struct mlx5e_priv *priv, | |
1227 | struct mlx5e_sq_param *param) | |
1228 | { | |
1229 | void *sqc = param->sqc; | |
1230 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1231 | ||
1232 | mlx5e_build_sq_param_common(priv, param); | |
1233 | MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size); | |
1234 | ||
58d52291 | 1235 | param->max_inline = priv->params.tx_max_inline; |
f62b8bb8 AV |
1236 | } |
1237 | ||
1238 | static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv, | |
1239 | struct mlx5e_cq_param *param) | |
1240 | { | |
1241 | void *cqc = param->cqc; | |
1242 | ||
1243 | MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index); | |
1244 | } | |
1245 | ||
1246 | static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, | |
1247 | struct mlx5e_cq_param *param) | |
1248 | { | |
1249 | void *cqc = param->cqc; | |
461017cb | 1250 | u8 log_cq_size; |
f62b8bb8 | 1251 | |
461017cb TT |
1252 | switch (priv->params.rq_wq_type) { |
1253 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
1254 | log_cq_size = priv->params.log_rq_size + | |
d9d9f156 | 1255 | priv->params.mpwqe_log_num_strides; |
461017cb TT |
1256 | break; |
1257 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
1258 | log_cq_size = priv->params.log_rq_size; | |
1259 | } | |
1260 | ||
1261 | MLX5_SET(cqc, cqc, log_cq_size, log_cq_size); | |
7219ab34 TT |
1262 | if (priv->params.rx_cqe_compress) { |
1263 | MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM); | |
1264 | MLX5_SET(cqc, cqc, cqe_comp_en, 1); | |
1265 | } | |
f62b8bb8 AV |
1266 | |
1267 | mlx5e_build_common_cq_param(priv, param); | |
1268 | } | |
1269 | ||
1270 | static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, | |
1271 | struct mlx5e_cq_param *param) | |
1272 | { | |
1273 | void *cqc = param->cqc; | |
1274 | ||
d3c9bc27 | 1275 | MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size); |
f62b8bb8 AV |
1276 | |
1277 | mlx5e_build_common_cq_param(priv, param); | |
1278 | } | |
1279 | ||
d3c9bc27 TT |
1280 | static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, |
1281 | struct mlx5e_cq_param *param, | |
1282 | u8 log_wq_size) | |
1283 | { | |
1284 | void *cqc = param->cqc; | |
1285 | ||
1286 | MLX5_SET(cqc, cqc, log_cq_size, log_wq_size); | |
1287 | ||
1288 | mlx5e_build_common_cq_param(priv, param); | |
1289 | } | |
1290 | ||
1291 | static void mlx5e_build_icosq_param(struct mlx5e_priv *priv, | |
1292 | struct mlx5e_sq_param *param, | |
1293 | u8 log_wq_size) | |
1294 | { | |
1295 | void *sqc = param->sqc; | |
1296 | void *wq = MLX5_ADDR_OF(sqc, sqc, wq); | |
1297 | ||
1298 | mlx5e_build_sq_param_common(priv, param); | |
1299 | ||
1300 | MLX5_SET(wq, wq, log_wq_sz, log_wq_size); | |
bc77b240 | 1301 | MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq)); |
d3c9bc27 TT |
1302 | |
1303 | param->icosq = true; | |
1304 | } | |
1305 | ||
6b87663f | 1306 | static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam) |
f62b8bb8 | 1307 | { |
bc77b240 | 1308 | u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE; |
d3c9bc27 | 1309 | |
f62b8bb8 AV |
1310 | mlx5e_build_rq_param(priv, &cparam->rq); |
1311 | mlx5e_build_sq_param(priv, &cparam->sq); | |
d3c9bc27 | 1312 | mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz); |
f62b8bb8 AV |
1313 | mlx5e_build_rx_cq_param(priv, &cparam->rx_cq); |
1314 | mlx5e_build_tx_cq_param(priv, &cparam->tx_cq); | |
d3c9bc27 | 1315 | mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz); |
f62b8bb8 AV |
1316 | } |
1317 | ||
1318 | static int mlx5e_open_channels(struct mlx5e_priv *priv) | |
1319 | { | |
6b87663f | 1320 | struct mlx5e_channel_param *cparam; |
a4418a6c | 1321 | int nch = priv->params.num_channels; |
03289b88 | 1322 | int err = -ENOMEM; |
f62b8bb8 AV |
1323 | int i; |
1324 | int j; | |
1325 | ||
a4418a6c AS |
1326 | priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *), |
1327 | GFP_KERNEL); | |
03289b88 | 1328 | |
a4418a6c | 1329 | priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc, |
03289b88 SM |
1330 | sizeof(struct mlx5e_sq *), GFP_KERNEL); |
1331 | ||
6b87663f AB |
1332 | cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL); |
1333 | ||
1334 | if (!priv->channel || !priv->txq_to_sq_map || !cparam) | |
03289b88 | 1335 | goto err_free_txq_to_sq_map; |
f62b8bb8 | 1336 | |
6b87663f AB |
1337 | mlx5e_build_channel_param(priv, cparam); |
1338 | ||
a4418a6c | 1339 | for (i = 0; i < nch; i++) { |
6b87663f | 1340 | err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]); |
f62b8bb8 AV |
1341 | if (err) |
1342 | goto err_close_channels; | |
1343 | } | |
1344 | ||
a4418a6c | 1345 | for (j = 0; j < nch; j++) { |
f62b8bb8 AV |
1346 | err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq); |
1347 | if (err) | |
1348 | goto err_close_channels; | |
1349 | } | |
1350 | ||
6b87663f | 1351 | kfree(cparam); |
f62b8bb8 AV |
1352 | return 0; |
1353 | ||
1354 | err_close_channels: | |
1355 | for (i--; i >= 0; i--) | |
1356 | mlx5e_close_channel(priv->channel[i]); | |
1357 | ||
03289b88 SM |
1358 | err_free_txq_to_sq_map: |
1359 | kfree(priv->txq_to_sq_map); | |
f62b8bb8 | 1360 | kfree(priv->channel); |
6b87663f | 1361 | kfree(cparam); |
f62b8bb8 AV |
1362 | |
1363 | return err; | |
1364 | } | |
1365 | ||
1366 | static void mlx5e_close_channels(struct mlx5e_priv *priv) | |
1367 | { | |
1368 | int i; | |
1369 | ||
1370 | for (i = 0; i < priv->params.num_channels; i++) | |
1371 | mlx5e_close_channel(priv->channel[i]); | |
1372 | ||
03289b88 | 1373 | kfree(priv->txq_to_sq_map); |
f62b8bb8 AV |
1374 | kfree(priv->channel); |
1375 | } | |
1376 | ||
2be6967c SM |
1377 | static int mlx5e_rx_hash_fn(int hfunc) |
1378 | { | |
1379 | return (hfunc == ETH_RSS_HASH_TOP) ? | |
1380 | MLX5_RX_HASH_FN_TOEPLITZ : | |
1381 | MLX5_RX_HASH_FN_INVERTED_XOR8; | |
1382 | } | |
1383 | ||
1384 | static int mlx5e_bits_invert(unsigned long a, int size) | |
1385 | { | |
1386 | int inv = 0; | |
1387 | int i; | |
1388 | ||
1389 | for (i = 0; i < size; i++) | |
1390 | inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i; | |
1391 | ||
1392 | return inv; | |
1393 | } | |
1394 | ||
936896e9 AS |
1395 | static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc) |
1396 | { | |
1397 | int i; | |
1398 | ||
1399 | for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) { | |
1400 | int ix = i; | |
1da36696 | 1401 | u32 rqn; |
936896e9 AS |
1402 | |
1403 | if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR) | |
1404 | ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE); | |
1405 | ||
2d75b2bc | 1406 | ix = priv->params.indirection_rqt[ix]; |
1da36696 TT |
1407 | rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1408 | priv->channel[ix]->rq.rqn : | |
1409 | priv->drop_rq.rqn; | |
1410 | MLX5_SET(rqtc, rqtc, rq_num[i], rqn); | |
936896e9 AS |
1411 | } |
1412 | } | |
1413 | ||
1da36696 TT |
1414 | static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc, |
1415 | int ix) | |
4cbeaff5 | 1416 | { |
1da36696 TT |
1417 | u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ? |
1418 | priv->channel[ix]->rq.rqn : | |
1419 | priv->drop_rq.rqn; | |
4cbeaff5 | 1420 | |
1da36696 | 1421 | MLX5_SET(rqtc, rqtc, rq_num[0], rqn); |
4cbeaff5 AS |
1422 | } |
1423 | ||
1da36696 | 1424 | static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn) |
f62b8bb8 AV |
1425 | { |
1426 | struct mlx5_core_dev *mdev = priv->mdev; | |
f62b8bb8 AV |
1427 | void *rqtc; |
1428 | int inlen; | |
1429 | int err; | |
1da36696 | 1430 | u32 *in; |
f62b8bb8 | 1431 | |
f62b8bb8 AV |
1432 | inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz; |
1433 | in = mlx5_vzalloc(inlen); | |
1434 | if (!in) | |
1435 | return -ENOMEM; | |
1436 | ||
1437 | rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context); | |
1438 | ||
1439 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1440 | MLX5_SET(rqtc, rqtc, rqt_max_size, sz); | |
1441 | ||
1da36696 TT |
1442 | if (sz > 1) /* RSS */ |
1443 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1444 | else | |
1445 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
2be6967c | 1446 | |
1da36696 | 1447 | err = mlx5_core_create_rqt(mdev, in, inlen, rqtn); |
f62b8bb8 AV |
1448 | |
1449 | kvfree(in); | |
1da36696 TT |
1450 | return err; |
1451 | } | |
1452 | ||
1453 | static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn) | |
1454 | { | |
1455 | mlx5_core_destroy_rqt(priv->mdev, rqtn); | |
1456 | } | |
1457 | ||
1458 | static int mlx5e_create_rqts(struct mlx5e_priv *priv) | |
1459 | { | |
1460 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1461 | u32 *rqtn; | |
1462 | int err; | |
1463 | int ix; | |
1464 | ||
1465 | /* Indirect RQT */ | |
1466 | rqtn = &priv->indir_rqtn; | |
1467 | err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn); | |
1468 | if (err) | |
1469 | return err; | |
1470 | ||
1471 | /* Direct RQTs */ | |
1472 | for (ix = 0; ix < nch; ix++) { | |
1473 | rqtn = &priv->direct_tir[ix].rqtn; | |
1474 | err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn); | |
1475 | if (err) | |
1476 | goto err_destroy_rqts; | |
1477 | } | |
1478 | ||
1479 | return 0; | |
1480 | ||
1481 | err_destroy_rqts: | |
1482 | for (ix--; ix >= 0; ix--) | |
1483 | mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn); | |
1484 | ||
1485 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
f62b8bb8 AV |
1486 | |
1487 | return err; | |
1488 | } | |
1489 | ||
1da36696 TT |
1490 | static void mlx5e_destroy_rqts(struct mlx5e_priv *priv) |
1491 | { | |
1492 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
1493 | int i; | |
1494 | ||
1495 | for (i = 0; i < nch; i++) | |
1496 | mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn); | |
1497 | ||
1498 | mlx5e_destroy_rqt(priv, priv->indir_rqtn); | |
1499 | } | |
1500 | ||
1501 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix) | |
5c50368f AS |
1502 | { |
1503 | struct mlx5_core_dev *mdev = priv->mdev; | |
5c50368f AS |
1504 | void *rqtc; |
1505 | int inlen; | |
1da36696 | 1506 | u32 *in; |
5c50368f AS |
1507 | int err; |
1508 | ||
5c50368f AS |
1509 | inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz; |
1510 | in = mlx5_vzalloc(inlen); | |
1511 | if (!in) | |
1512 | return -ENOMEM; | |
1513 | ||
1514 | rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx); | |
1515 | ||
1516 | MLX5_SET(rqtc, rqtc, rqt_actual_size, sz); | |
1da36696 TT |
1517 | if (sz > 1) /* RSS */ |
1518 | mlx5e_fill_indir_rqt_rqns(priv, rqtc); | |
1519 | else | |
1520 | mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix); | |
5c50368f AS |
1521 | |
1522 | MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1); | |
1523 | ||
1da36696 | 1524 | err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen); |
5c50368f AS |
1525 | |
1526 | kvfree(in); | |
1527 | ||
1528 | return err; | |
1529 | } | |
1530 | ||
40ab6a6e AS |
1531 | static void mlx5e_redirect_rqts(struct mlx5e_priv *priv) |
1532 | { | |
1da36696 TT |
1533 | u32 rqtn; |
1534 | int ix; | |
1535 | ||
1536 | rqtn = priv->indir_rqtn; | |
1537 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0); | |
1538 | for (ix = 0; ix < priv->params.num_channels; ix++) { | |
1539 | rqtn = priv->direct_tir[ix].rqtn; | |
1540 | mlx5e_redirect_rqt(priv, rqtn, 1, ix); | |
1541 | } | |
40ab6a6e AS |
1542 | } |
1543 | ||
5c50368f AS |
1544 | static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv) |
1545 | { | |
1546 | if (!priv->params.lro_en) | |
1547 | return; | |
1548 | ||
1549 | #define ROUGH_MAX_L2_L3_HDR_SZ 256 | |
1550 | ||
1551 | MLX5_SET(tirc, tirc, lro_enable_mask, | |
1552 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO | | |
1553 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO); | |
1554 | MLX5_SET(tirc, tirc, lro_max_ip_payload_size, | |
1555 | (priv->params.lro_wqe_sz - | |
1556 | ROUGH_MAX_L2_L3_HDR_SZ) >> 8); | |
1557 | MLX5_SET(tirc, tirc, lro_timeout_period_usecs, | |
1558 | MLX5_CAP_ETH(priv->mdev, | |
d9a40271 | 1559 | lro_timer_supported_periods[2])); |
5c50368f AS |
1560 | } |
1561 | ||
bdfc028d TT |
1562 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv) |
1563 | { | |
1564 | MLX5_SET(tirc, tirc, rx_hash_fn, | |
1565 | mlx5e_rx_hash_fn(priv->params.rss_hfunc)); | |
1566 | if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) { | |
1567 | void *rss_key = MLX5_ADDR_OF(tirc, tirc, | |
1568 | rx_hash_toeplitz_key); | |
1569 | size_t len = MLX5_FLD_SZ_BYTES(tirc, | |
1570 | rx_hash_toeplitz_key); | |
1571 | ||
1572 | MLX5_SET(tirc, tirc, rx_hash_symmetric, 1); | |
1573 | memcpy(rss_key, priv->params.toeplitz_hash_key, len); | |
1574 | } | |
1575 | } | |
1576 | ||
ab0394fe | 1577 | static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv) |
5c50368f AS |
1578 | { |
1579 | struct mlx5_core_dev *mdev = priv->mdev; | |
1580 | ||
1581 | void *in; | |
1582 | void *tirc; | |
1583 | int inlen; | |
1584 | int err; | |
ab0394fe | 1585 | int tt; |
1da36696 | 1586 | int ix; |
5c50368f AS |
1587 | |
1588 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1589 | in = mlx5_vzalloc(inlen); | |
1590 | if (!in) | |
1591 | return -ENOMEM; | |
1592 | ||
1593 | MLX5_SET(modify_tir_in, in, bitmask.lro, 1); | |
1594 | tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
1595 | ||
1596 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
1597 | ||
1da36696 TT |
1598 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { |
1599 | err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in, | |
1600 | inlen); | |
ab0394fe | 1601 | if (err) |
1da36696 | 1602 | goto free_in; |
ab0394fe | 1603 | } |
5c50368f | 1604 | |
1da36696 TT |
1605 | for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) { |
1606 | err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn, | |
1607 | in, inlen); | |
1608 | if (err) | |
1609 | goto free_in; | |
1610 | } | |
1611 | ||
1612 | free_in: | |
5c50368f AS |
1613 | kvfree(in); |
1614 | ||
1615 | return err; | |
1616 | } | |
1617 | ||
1da36696 | 1618 | static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv) |
66189961 TT |
1619 | { |
1620 | void *in; | |
1621 | int inlen; | |
1622 | int err; | |
1da36696 | 1623 | int i; |
66189961 TT |
1624 | |
1625 | inlen = MLX5_ST_SZ_BYTES(modify_tir_in); | |
1626 | in = mlx5_vzalloc(inlen); | |
1627 | if (!in) | |
1628 | return -ENOMEM; | |
1629 | ||
1630 | MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); | |
1631 | ||
1da36696 TT |
1632 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { |
1633 | err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in, | |
1634 | inlen); | |
1635 | if (err) | |
1636 | return err; | |
1637 | } | |
66189961 | 1638 | |
1da36696 TT |
1639 | for (i = 0; i < priv->params.num_channels; i++) { |
1640 | err = mlx5_core_modify_tir(priv->mdev, | |
1641 | priv->direct_tir[i].tirn, in, | |
1642 | inlen); | |
66189961 TT |
1643 | if (err) |
1644 | return err; | |
1645 | } | |
1646 | ||
1da36696 TT |
1647 | kvfree(in); |
1648 | ||
66189961 TT |
1649 | return 0; |
1650 | } | |
1651 | ||
cd255eff | 1652 | static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu) |
40ab6a6e | 1653 | { |
40ab6a6e | 1654 | struct mlx5_core_dev *mdev = priv->mdev; |
cd255eff | 1655 | u16 hw_mtu = MLX5E_SW2HW_MTU(mtu); |
40ab6a6e AS |
1656 | int err; |
1657 | ||
cd255eff | 1658 | err = mlx5_set_port_mtu(mdev, hw_mtu, 1); |
40ab6a6e AS |
1659 | if (err) |
1660 | return err; | |
1661 | ||
cd255eff SM |
1662 | /* Update vport context MTU */ |
1663 | mlx5_modify_nic_vport_mtu(mdev, hw_mtu); | |
1664 | return 0; | |
1665 | } | |
40ab6a6e | 1666 | |
cd255eff SM |
1667 | static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu) |
1668 | { | |
1669 | struct mlx5_core_dev *mdev = priv->mdev; | |
1670 | u16 hw_mtu = 0; | |
1671 | int err; | |
40ab6a6e | 1672 | |
cd255eff SM |
1673 | err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu); |
1674 | if (err || !hw_mtu) /* fallback to port oper mtu */ | |
1675 | mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1); | |
1676 | ||
1677 | *mtu = MLX5E_HW2SW_MTU(hw_mtu); | |
1678 | } | |
1679 | ||
1680 | static int mlx5e_set_dev_port_mtu(struct net_device *netdev) | |
1681 | { | |
1682 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1683 | u16 mtu; | |
1684 | int err; | |
1685 | ||
1686 | err = mlx5e_set_mtu(priv, netdev->mtu); | |
1687 | if (err) | |
1688 | return err; | |
40ab6a6e | 1689 | |
cd255eff SM |
1690 | mlx5e_query_mtu(priv, &mtu); |
1691 | if (mtu != netdev->mtu) | |
1692 | netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", | |
1693 | __func__, mtu, netdev->mtu); | |
40ab6a6e | 1694 | |
cd255eff | 1695 | netdev->mtu = mtu; |
40ab6a6e AS |
1696 | return 0; |
1697 | } | |
1698 | ||
08fb1dac SM |
1699 | static void mlx5e_netdev_set_tcs(struct net_device *netdev) |
1700 | { | |
1701 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1702 | int nch = priv->params.num_channels; | |
1703 | int ntc = priv->params.num_tc; | |
1704 | int tc; | |
1705 | ||
1706 | netdev_reset_tc(netdev); | |
1707 | ||
1708 | if (ntc == 1) | |
1709 | return; | |
1710 | ||
1711 | netdev_set_num_tc(netdev, ntc); | |
1712 | ||
7ccdd084 RS |
1713 | /* Map netdev TCs to offset 0 |
1714 | * We have our own UP to TXQ mapping for QoS | |
1715 | */ | |
08fb1dac | 1716 | for (tc = 0; tc < ntc; tc++) |
7ccdd084 | 1717 | netdev_set_tc_queue(netdev, tc, nch, 0); |
08fb1dac SM |
1718 | } |
1719 | ||
40ab6a6e AS |
1720 | int mlx5e_open_locked(struct net_device *netdev) |
1721 | { | |
1722 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1723 | int num_txqs; | |
1724 | int err; | |
1725 | ||
1726 | set_bit(MLX5E_STATE_OPENED, &priv->state); | |
1727 | ||
08fb1dac SM |
1728 | mlx5e_netdev_set_tcs(netdev); |
1729 | ||
40ab6a6e AS |
1730 | num_txqs = priv->params.num_channels * priv->params.num_tc; |
1731 | netif_set_real_num_tx_queues(netdev, num_txqs); | |
1732 | netif_set_real_num_rx_queues(netdev, priv->params.num_channels); | |
1733 | ||
1734 | err = mlx5e_set_dev_port_mtu(netdev); | |
1735 | if (err) | |
343b29f3 | 1736 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1737 | |
1738 | err = mlx5e_open_channels(priv); | |
1739 | if (err) { | |
1740 | netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n", | |
1741 | __func__, err); | |
343b29f3 | 1742 | goto err_clear_state_opened_flag; |
40ab6a6e AS |
1743 | } |
1744 | ||
66189961 TT |
1745 | err = mlx5e_refresh_tirs_self_loopback_enable(priv); |
1746 | if (err) { | |
1747 | netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n", | |
1748 | __func__, err); | |
1749 | goto err_close_channels; | |
1750 | } | |
1751 | ||
40ab6a6e | 1752 | mlx5e_redirect_rqts(priv); |
ce89ef36 | 1753 | mlx5e_update_carrier(priv); |
ef9814de | 1754 | mlx5e_timestamp_init(priv); |
5a7b27eb MG |
1755 | #ifdef CONFIG_RFS_ACCEL |
1756 | priv->netdev->rx_cpu_rmap = priv->mdev->rmap; | |
1757 | #endif | |
40ab6a6e | 1758 | |
7bb29755 | 1759 | queue_delayed_work(priv->wq, &priv->update_stats_work, 0); |
40ab6a6e | 1760 | |
9b37b07f | 1761 | return 0; |
343b29f3 | 1762 | |
66189961 TT |
1763 | err_close_channels: |
1764 | mlx5e_close_channels(priv); | |
343b29f3 AS |
1765 | err_clear_state_opened_flag: |
1766 | clear_bit(MLX5E_STATE_OPENED, &priv->state); | |
1767 | return err; | |
40ab6a6e AS |
1768 | } |
1769 | ||
1770 | static int mlx5e_open(struct net_device *netdev) | |
1771 | { | |
1772 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1773 | int err; | |
1774 | ||
1775 | mutex_lock(&priv->state_lock); | |
1776 | err = mlx5e_open_locked(netdev); | |
1777 | mutex_unlock(&priv->state_lock); | |
1778 | ||
1779 | return err; | |
1780 | } | |
1781 | ||
1782 | int mlx5e_close_locked(struct net_device *netdev) | |
1783 | { | |
1784 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1785 | ||
a1985740 AS |
1786 | /* May already be CLOSED in case a previous configuration operation |
1787 | * (e.g RX/TX queue size change) that involves close&open failed. | |
1788 | */ | |
1789 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
1790 | return 0; | |
1791 | ||
40ab6a6e AS |
1792 | clear_bit(MLX5E_STATE_OPENED, &priv->state); |
1793 | ||
ef9814de | 1794 | mlx5e_timestamp_cleanup(priv); |
40ab6a6e | 1795 | netif_carrier_off(priv->netdev); |
ce89ef36 | 1796 | mlx5e_redirect_rqts(priv); |
40ab6a6e AS |
1797 | mlx5e_close_channels(priv); |
1798 | ||
1799 | return 0; | |
1800 | } | |
1801 | ||
1802 | static int mlx5e_close(struct net_device *netdev) | |
1803 | { | |
1804 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1805 | int err; | |
1806 | ||
1807 | mutex_lock(&priv->state_lock); | |
1808 | err = mlx5e_close_locked(netdev); | |
1809 | mutex_unlock(&priv->state_lock); | |
1810 | ||
1811 | return err; | |
1812 | } | |
1813 | ||
1814 | static int mlx5e_create_drop_rq(struct mlx5e_priv *priv, | |
1815 | struct mlx5e_rq *rq, | |
1816 | struct mlx5e_rq_param *param) | |
1817 | { | |
1818 | struct mlx5_core_dev *mdev = priv->mdev; | |
1819 | void *rqc = param->rqc; | |
1820 | void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq); | |
1821 | int err; | |
1822 | ||
1823 | param->wq.db_numa_node = param->wq.buf_numa_node; | |
1824 | ||
1825 | err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq, | |
1826 | &rq->wq_ctrl); | |
1827 | if (err) | |
1828 | return err; | |
1829 | ||
1830 | rq->priv = priv; | |
1831 | ||
1832 | return 0; | |
1833 | } | |
1834 | ||
1835 | static int mlx5e_create_drop_cq(struct mlx5e_priv *priv, | |
1836 | struct mlx5e_cq *cq, | |
1837 | struct mlx5e_cq_param *param) | |
1838 | { | |
1839 | struct mlx5_core_dev *mdev = priv->mdev; | |
1840 | struct mlx5_core_cq *mcq = &cq->mcq; | |
1841 | int eqn_not_used; | |
0b6e26ce | 1842 | unsigned int irqn; |
40ab6a6e AS |
1843 | int err; |
1844 | ||
1845 | err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq, | |
1846 | &cq->wq_ctrl); | |
1847 | if (err) | |
1848 | return err; | |
1849 | ||
1850 | mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn); | |
1851 | ||
1852 | mcq->cqe_sz = 64; | |
1853 | mcq->set_ci_db = cq->wq_ctrl.db.db; | |
1854 | mcq->arm_db = cq->wq_ctrl.db.db + 1; | |
1855 | *mcq->set_ci_db = 0; | |
1856 | *mcq->arm_db = 0; | |
1857 | mcq->vector = param->eq_ix; | |
1858 | mcq->comp = mlx5e_completion_event; | |
1859 | mcq->event = mlx5e_cq_error_event; | |
1860 | mcq->irqn = irqn; | |
1861 | mcq->uar = &priv->cq_uar; | |
1862 | ||
1863 | cq->priv = priv; | |
1864 | ||
1865 | return 0; | |
1866 | } | |
1867 | ||
1868 | static int mlx5e_open_drop_rq(struct mlx5e_priv *priv) | |
1869 | { | |
1870 | struct mlx5e_cq_param cq_param; | |
1871 | struct mlx5e_rq_param rq_param; | |
1872 | struct mlx5e_rq *rq = &priv->drop_rq; | |
1873 | struct mlx5e_cq *cq = &priv->drop_rq.cq; | |
1874 | int err; | |
1875 | ||
1876 | memset(&cq_param, 0, sizeof(cq_param)); | |
1877 | memset(&rq_param, 0, sizeof(rq_param)); | |
556dd1b9 | 1878 | mlx5e_build_drop_rq_param(&rq_param); |
40ab6a6e AS |
1879 | |
1880 | err = mlx5e_create_drop_cq(priv, cq, &cq_param); | |
1881 | if (err) | |
1882 | return err; | |
1883 | ||
1884 | err = mlx5e_enable_cq(cq, &cq_param); | |
1885 | if (err) | |
1886 | goto err_destroy_cq; | |
1887 | ||
1888 | err = mlx5e_create_drop_rq(priv, rq, &rq_param); | |
1889 | if (err) | |
1890 | goto err_disable_cq; | |
1891 | ||
1892 | err = mlx5e_enable_rq(rq, &rq_param); | |
1893 | if (err) | |
1894 | goto err_destroy_rq; | |
1895 | ||
1896 | return 0; | |
1897 | ||
1898 | err_destroy_rq: | |
1899 | mlx5e_destroy_rq(&priv->drop_rq); | |
1900 | ||
1901 | err_disable_cq: | |
1902 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1903 | ||
1904 | err_destroy_cq: | |
1905 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1906 | ||
1907 | return err; | |
1908 | } | |
1909 | ||
1910 | static void mlx5e_close_drop_rq(struct mlx5e_priv *priv) | |
1911 | { | |
1912 | mlx5e_disable_rq(&priv->drop_rq); | |
1913 | mlx5e_destroy_rq(&priv->drop_rq); | |
1914 | mlx5e_disable_cq(&priv->drop_rq.cq); | |
1915 | mlx5e_destroy_cq(&priv->drop_rq.cq); | |
1916 | } | |
1917 | ||
1918 | static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc) | |
1919 | { | |
1920 | struct mlx5_core_dev *mdev = priv->mdev; | |
1921 | u32 in[MLX5_ST_SZ_DW(create_tis_in)]; | |
1922 | void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx); | |
1923 | ||
1924 | memset(in, 0, sizeof(in)); | |
1925 | ||
08fb1dac | 1926 | MLX5_SET(tisc, tisc, prio, tc << 1); |
40ab6a6e AS |
1927 | MLX5_SET(tisc, tisc, transport_domain, priv->tdn); |
1928 | ||
1929 | return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]); | |
1930 | } | |
1931 | ||
1932 | static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc) | |
1933 | { | |
1934 | mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]); | |
1935 | } | |
1936 | ||
1937 | static int mlx5e_create_tises(struct mlx5e_priv *priv) | |
1938 | { | |
1939 | int err; | |
1940 | int tc; | |
1941 | ||
08fb1dac | 1942 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) { |
40ab6a6e AS |
1943 | err = mlx5e_create_tis(priv, tc); |
1944 | if (err) | |
1945 | goto err_close_tises; | |
1946 | } | |
1947 | ||
1948 | return 0; | |
1949 | ||
1950 | err_close_tises: | |
1951 | for (tc--; tc >= 0; tc--) | |
1952 | mlx5e_destroy_tis(priv, tc); | |
1953 | ||
1954 | return err; | |
1955 | } | |
1956 | ||
1957 | static void mlx5e_destroy_tises(struct mlx5e_priv *priv) | |
1958 | { | |
1959 | int tc; | |
1960 | ||
08fb1dac | 1961 | for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) |
40ab6a6e AS |
1962 | mlx5e_destroy_tis(priv, tc); |
1963 | } | |
1964 | ||
1da36696 TT |
1965 | static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
1966 | enum mlx5e_traffic_types tt) | |
f62b8bb8 AV |
1967 | { |
1968 | void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer); | |
1969 | ||
3191e05f AS |
1970 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
1971 | ||
5a6f8aef AS |
1972 | #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1973 | MLX5_HASH_FIELD_SEL_DST_IP) | |
f62b8bb8 | 1974 | |
5a6f8aef AS |
1975 | #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1976 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1977 | MLX5_HASH_FIELD_SEL_L4_SPORT |\ | |
1978 | MLX5_HASH_FIELD_SEL_L4_DPORT) | |
f62b8bb8 | 1979 | |
a741749f AS |
1980 | #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\ |
1981 | MLX5_HASH_FIELD_SEL_DST_IP |\ | |
1982 | MLX5_HASH_FIELD_SEL_IPSEC_SPI) | |
1983 | ||
5c50368f | 1984 | mlx5e_build_tir_ctx_lro(tirc, priv); |
f62b8bb8 | 1985 | |
4cbeaff5 | 1986 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); |
1da36696 TT |
1987 | MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn); |
1988 | mlx5e_build_tir_ctx_hash(tirc, priv); | |
f62b8bb8 AV |
1989 | |
1990 | switch (tt) { | |
1991 | case MLX5E_TT_IPV4_TCP: | |
1992 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
1993 | MLX5_L3_PROT_TYPE_IPV4); | |
1994 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
1995 | MLX5_L4_PROT_TYPE_TCP); | |
1996 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 1997 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
1998 | break; |
1999 | ||
2000 | case MLX5E_TT_IPV6_TCP: | |
2001 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2002 | MLX5_L3_PROT_TYPE_IPV6); | |
2003 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2004 | MLX5_L4_PROT_TYPE_TCP); | |
2005 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2006 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2007 | break; |
2008 | ||
2009 | case MLX5E_TT_IPV4_UDP: | |
2010 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2011 | MLX5_L3_PROT_TYPE_IPV4); | |
2012 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2013 | MLX5_L4_PROT_TYPE_UDP); | |
2014 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2015 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2016 | break; |
2017 | ||
2018 | case MLX5E_TT_IPV6_UDP: | |
2019 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2020 | MLX5_L3_PROT_TYPE_IPV6); | |
2021 | MLX5_SET(rx_hash_field_select, hfso, l4_prot_type, | |
2022 | MLX5_L4_PROT_TYPE_UDP); | |
2023 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
5a6f8aef | 2024 | MLX5_HASH_IP_L4PORTS); |
f62b8bb8 AV |
2025 | break; |
2026 | ||
a741749f AS |
2027 | case MLX5E_TT_IPV4_IPSEC_AH: |
2028 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2029 | MLX5_L3_PROT_TYPE_IPV4); | |
2030 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2031 | MLX5_HASH_IP_IPSEC_SPI); | |
2032 | break; | |
2033 | ||
2034 | case MLX5E_TT_IPV6_IPSEC_AH: | |
2035 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2036 | MLX5_L3_PROT_TYPE_IPV6); | |
2037 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2038 | MLX5_HASH_IP_IPSEC_SPI); | |
2039 | break; | |
2040 | ||
2041 | case MLX5E_TT_IPV4_IPSEC_ESP: | |
2042 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2043 | MLX5_L3_PROT_TYPE_IPV4); | |
2044 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2045 | MLX5_HASH_IP_IPSEC_SPI); | |
2046 | break; | |
2047 | ||
2048 | case MLX5E_TT_IPV6_IPSEC_ESP: | |
2049 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2050 | MLX5_L3_PROT_TYPE_IPV6); | |
2051 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2052 | MLX5_HASH_IP_IPSEC_SPI); | |
2053 | break; | |
2054 | ||
f62b8bb8 AV |
2055 | case MLX5E_TT_IPV4: |
2056 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2057 | MLX5_L3_PROT_TYPE_IPV4); | |
2058 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2059 | MLX5_HASH_IP); | |
2060 | break; | |
2061 | ||
2062 | case MLX5E_TT_IPV6: | |
2063 | MLX5_SET(rx_hash_field_select, hfso, l3_prot_type, | |
2064 | MLX5_L3_PROT_TYPE_IPV6); | |
2065 | MLX5_SET(rx_hash_field_select, hfso, selected_fields, | |
2066 | MLX5_HASH_IP); | |
2067 | break; | |
1da36696 TT |
2068 | default: |
2069 | WARN_ONCE(true, | |
2070 | "mlx5e_build_indir_tir_ctx: bad traffic type!\n"); | |
f62b8bb8 AV |
2071 | } |
2072 | } | |
2073 | ||
1da36696 TT |
2074 | static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc, |
2075 | u32 rqtn) | |
f62b8bb8 | 2076 | { |
1da36696 TT |
2077 | MLX5_SET(tirc, tirc, transport_domain, priv->tdn); |
2078 | ||
2079 | mlx5e_build_tir_ctx_lro(tirc, priv); | |
2080 | ||
2081 | MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT); | |
2082 | MLX5_SET(tirc, tirc, indirect_table, rqtn); | |
2083 | MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); | |
2084 | } | |
2085 | ||
2086 | static int mlx5e_create_tirs(struct mlx5e_priv *priv) | |
2087 | { | |
2088 | int nch = mlx5e_get_max_num_channels(priv->mdev); | |
f62b8bb8 AV |
2089 | void *tirc; |
2090 | int inlen; | |
1da36696 | 2091 | u32 *tirn; |
f62b8bb8 | 2092 | int err; |
1da36696 TT |
2093 | u32 *in; |
2094 | int ix; | |
2095 | int tt; | |
f62b8bb8 AV |
2096 | |
2097 | inlen = MLX5_ST_SZ_BYTES(create_tir_in); | |
2098 | in = mlx5_vzalloc(inlen); | |
2099 | if (!in) | |
2100 | return -ENOMEM; | |
2101 | ||
1da36696 TT |
2102 | /* indirect tirs */ |
2103 | for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { | |
2104 | memset(in, 0, inlen); | |
2105 | tirn = &priv->indir_tirn[tt]; | |
2106 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2107 | mlx5e_build_indir_tir_ctx(priv, tirc, tt); | |
2108 | err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn); | |
f62b8bb8 | 2109 | if (err) |
40ab6a6e | 2110 | goto err_destroy_tirs; |
f62b8bb8 AV |
2111 | } |
2112 | ||
1da36696 TT |
2113 | /* direct tirs */ |
2114 | for (ix = 0; ix < nch; ix++) { | |
2115 | memset(in, 0, inlen); | |
2116 | tirn = &priv->direct_tir[ix].tirn; | |
2117 | tirc = MLX5_ADDR_OF(create_tir_in, in, ctx); | |
2118 | mlx5e_build_direct_tir_ctx(priv, tirc, | |
2119 | priv->direct_tir[ix].rqtn); | |
2120 | err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn); | |
2121 | if (err) | |
2122 | goto err_destroy_ch_tirs; | |
2123 | } | |
2124 | ||
2125 | kvfree(in); | |
2126 | ||
f62b8bb8 AV |
2127 | return 0; |
2128 | ||
1da36696 TT |
2129 | err_destroy_ch_tirs: |
2130 | for (ix--; ix >= 0; ix--) | |
2131 | mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn); | |
2132 | ||
40ab6a6e | 2133 | err_destroy_tirs: |
1da36696 TT |
2134 | for (tt--; tt >= 0; tt--) |
2135 | mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]); | |
2136 | ||
2137 | kvfree(in); | |
f62b8bb8 AV |
2138 | |
2139 | return err; | |
2140 | } | |
2141 | ||
40ab6a6e | 2142 | static void mlx5e_destroy_tirs(struct mlx5e_priv *priv) |
f62b8bb8 | 2143 | { |
1da36696 | 2144 | int nch = mlx5e_get_max_num_channels(priv->mdev); |
f62b8bb8 AV |
2145 | int i; |
2146 | ||
1da36696 TT |
2147 | for (i = 0; i < nch; i++) |
2148 | mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn); | |
2149 | ||
2150 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) | |
2151 | mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]); | |
f62b8bb8 AV |
2152 | } |
2153 | ||
36350114 GP |
2154 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd) |
2155 | { | |
2156 | int err = 0; | |
2157 | int i; | |
2158 | ||
2159 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2160 | return 0; | |
2161 | ||
2162 | for (i = 0; i < priv->params.num_channels; i++) { | |
2163 | err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd); | |
2164 | if (err) | |
2165 | return err; | |
2166 | } | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
08fb1dac SM |
2171 | static int mlx5e_setup_tc(struct net_device *netdev, u8 tc) |
2172 | { | |
2173 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2174 | bool was_opened; | |
2175 | int err = 0; | |
2176 | ||
2177 | if (tc && tc != MLX5E_MAX_NUM_TC) | |
2178 | return -EINVAL; | |
2179 | ||
2180 | mutex_lock(&priv->state_lock); | |
2181 | ||
2182 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2183 | if (was_opened) | |
2184 | mlx5e_close_locked(priv->netdev); | |
2185 | ||
2186 | priv->params.num_tc = tc ? tc : 1; | |
2187 | ||
2188 | if (was_opened) | |
2189 | err = mlx5e_open_locked(priv->netdev); | |
2190 | ||
2191 | mutex_unlock(&priv->state_lock); | |
2192 | ||
2193 | return err; | |
2194 | } | |
2195 | ||
2196 | static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle, | |
2197 | __be16 proto, struct tc_to_netdev *tc) | |
2198 | { | |
e8f887ac AV |
2199 | struct mlx5e_priv *priv = netdev_priv(dev); |
2200 | ||
2201 | if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS)) | |
2202 | goto mqprio; | |
2203 | ||
2204 | switch (tc->type) { | |
e3a2b7ed AV |
2205 | case TC_SETUP_CLSFLOWER: |
2206 | switch (tc->cls_flower->command) { | |
2207 | case TC_CLSFLOWER_REPLACE: | |
2208 | return mlx5e_configure_flower(priv, proto, tc->cls_flower); | |
2209 | case TC_CLSFLOWER_DESTROY: | |
2210 | return mlx5e_delete_flower(priv, tc->cls_flower); | |
aad7e08d AV |
2211 | case TC_CLSFLOWER_STATS: |
2212 | return mlx5e_stats_flower(priv, tc->cls_flower); | |
e3a2b7ed | 2213 | } |
e8f887ac AV |
2214 | default: |
2215 | return -EOPNOTSUPP; | |
2216 | } | |
2217 | ||
2218 | mqprio: | |
67ba422e | 2219 | if (tc->type != TC_SETUP_MQPRIO) |
08fb1dac SM |
2220 | return -EINVAL; |
2221 | ||
2222 | return mlx5e_setup_tc(dev, tc->tc); | |
2223 | } | |
2224 | ||
f62b8bb8 AV |
2225 | static struct rtnl_link_stats64 * |
2226 | mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats) | |
2227 | { | |
2228 | struct mlx5e_priv *priv = netdev_priv(dev); | |
9218b44d | 2229 | struct mlx5e_sw_stats *sstats = &priv->stats.sw; |
f62b8bb8 | 2230 | struct mlx5e_vport_stats *vstats = &priv->stats.vport; |
269e6b3a | 2231 | struct mlx5e_pport_stats *pstats = &priv->stats.pport; |
f62b8bb8 | 2232 | |
9218b44d GP |
2233 | stats->rx_packets = sstats->rx_packets; |
2234 | stats->rx_bytes = sstats->rx_bytes; | |
2235 | stats->tx_packets = sstats->tx_packets; | |
2236 | stats->tx_bytes = sstats->tx_bytes; | |
269e6b3a GP |
2237 | |
2238 | stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer; | |
9218b44d | 2239 | stats->tx_dropped = sstats->tx_queue_dropped; |
269e6b3a GP |
2240 | |
2241 | stats->rx_length_errors = | |
9218b44d GP |
2242 | PPORT_802_3_GET(pstats, a_in_range_length_errors) + |
2243 | PPORT_802_3_GET(pstats, a_out_of_range_length_field) + | |
2244 | PPORT_802_3_GET(pstats, a_frame_too_long_errors); | |
269e6b3a | 2245 | stats->rx_crc_errors = |
9218b44d GP |
2246 | PPORT_802_3_GET(pstats, a_frame_check_sequence_errors); |
2247 | stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors); | |
2248 | stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards); | |
269e6b3a | 2249 | stats->tx_carrier_errors = |
9218b44d | 2250 | PPORT_802_3_GET(pstats, a_symbol_error_during_carrier); |
269e6b3a GP |
2251 | stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors + |
2252 | stats->rx_frame_errors; | |
2253 | stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors; | |
2254 | ||
2255 | /* vport multicast also counts packets that are dropped due to steering | |
2256 | * or rx out of buffer | |
2257 | */ | |
9218b44d GP |
2258 | stats->multicast = |
2259 | VPORT_COUNTER_GET(vstats, received_eth_multicast.packets); | |
f62b8bb8 AV |
2260 | |
2261 | return stats; | |
2262 | } | |
2263 | ||
2264 | static void mlx5e_set_rx_mode(struct net_device *dev) | |
2265 | { | |
2266 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2267 | ||
7bb29755 | 2268 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2269 | } |
2270 | ||
2271 | static int mlx5e_set_mac(struct net_device *netdev, void *addr) | |
2272 | { | |
2273 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2274 | struct sockaddr *saddr = addr; | |
2275 | ||
2276 | if (!is_valid_ether_addr(saddr->sa_data)) | |
2277 | return -EADDRNOTAVAIL; | |
2278 | ||
2279 | netif_addr_lock_bh(netdev); | |
2280 | ether_addr_copy(netdev->dev_addr, saddr->sa_data); | |
2281 | netif_addr_unlock_bh(netdev); | |
2282 | ||
7bb29755 | 2283 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
2284 | |
2285 | return 0; | |
2286 | } | |
2287 | ||
0e405443 GP |
2288 | #define MLX5E_SET_FEATURE(netdev, feature, enable) \ |
2289 | do { \ | |
2290 | if (enable) \ | |
2291 | netdev->features |= feature; \ | |
2292 | else \ | |
2293 | netdev->features &= ~feature; \ | |
2294 | } while (0) | |
2295 | ||
2296 | typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable); | |
2297 | ||
2298 | static int set_feature_lro(struct net_device *netdev, bool enable) | |
f62b8bb8 AV |
2299 | { |
2300 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
0e405443 GP |
2301 | bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
2302 | int err; | |
f62b8bb8 AV |
2303 | |
2304 | mutex_lock(&priv->state_lock); | |
f62b8bb8 | 2305 | |
0e405443 GP |
2306 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2307 | mlx5e_close_locked(priv->netdev); | |
98e81b0a | 2308 | |
0e405443 GP |
2309 | priv->params.lro_en = enable; |
2310 | err = mlx5e_modify_tirs_lro(priv); | |
2311 | if (err) { | |
2312 | netdev_err(netdev, "lro modify failed, %d\n", err); | |
2313 | priv->params.lro_en = !enable; | |
98e81b0a | 2314 | } |
f62b8bb8 | 2315 | |
0e405443 GP |
2316 | if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)) |
2317 | mlx5e_open_locked(priv->netdev); | |
2318 | ||
9b37b07f AS |
2319 | mutex_unlock(&priv->state_lock); |
2320 | ||
0e405443 GP |
2321 | return err; |
2322 | } | |
2323 | ||
2324 | static int set_feature_vlan_filter(struct net_device *netdev, bool enable) | |
2325 | { | |
2326 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2327 | ||
2328 | if (enable) | |
2329 | mlx5e_enable_vlan_filter(priv); | |
2330 | else | |
2331 | mlx5e_disable_vlan_filter(priv); | |
2332 | ||
2333 | return 0; | |
2334 | } | |
2335 | ||
2336 | static int set_feature_tc_num_filters(struct net_device *netdev, bool enable) | |
2337 | { | |
2338 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
f62b8bb8 | 2339 | |
0e405443 | 2340 | if (!enable && mlx5e_tc_num_filters(priv)) { |
e8f887ac AV |
2341 | netdev_err(netdev, |
2342 | "Active offloaded tc filters, can't turn hw_tc_offload off\n"); | |
2343 | return -EINVAL; | |
2344 | } | |
2345 | ||
0e405443 GP |
2346 | return 0; |
2347 | } | |
2348 | ||
94cb1ebb EBE |
2349 | static int set_feature_rx_all(struct net_device *netdev, bool enable) |
2350 | { | |
2351 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2352 | struct mlx5_core_dev *mdev = priv->mdev; | |
2353 | ||
2354 | return mlx5_set_port_fcs(mdev, !enable); | |
2355 | } | |
2356 | ||
36350114 GP |
2357 | static int set_feature_rx_vlan(struct net_device *netdev, bool enable) |
2358 | { | |
2359 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2360 | int err; | |
2361 | ||
2362 | mutex_lock(&priv->state_lock); | |
2363 | ||
2364 | priv->params.vlan_strip_disable = !enable; | |
2365 | err = mlx5e_modify_rqs_vsd(priv, !enable); | |
2366 | if (err) | |
2367 | priv->params.vlan_strip_disable = enable; | |
2368 | ||
2369 | mutex_unlock(&priv->state_lock); | |
2370 | ||
2371 | return err; | |
2372 | } | |
2373 | ||
45bf454a MG |
2374 | #ifdef CONFIG_RFS_ACCEL |
2375 | static int set_feature_arfs(struct net_device *netdev, bool enable) | |
2376 | { | |
2377 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2378 | int err; | |
2379 | ||
2380 | if (enable) | |
2381 | err = mlx5e_arfs_enable(priv); | |
2382 | else | |
2383 | err = mlx5e_arfs_disable(priv); | |
2384 | ||
2385 | return err; | |
2386 | } | |
2387 | #endif | |
2388 | ||
0e405443 GP |
2389 | static int mlx5e_handle_feature(struct net_device *netdev, |
2390 | netdev_features_t wanted_features, | |
2391 | netdev_features_t feature, | |
2392 | mlx5e_feature_handler feature_handler) | |
2393 | { | |
2394 | netdev_features_t changes = wanted_features ^ netdev->features; | |
2395 | bool enable = !!(wanted_features & feature); | |
2396 | int err; | |
2397 | ||
2398 | if (!(changes & feature)) | |
2399 | return 0; | |
2400 | ||
2401 | err = feature_handler(netdev, enable); | |
2402 | if (err) { | |
2403 | netdev_err(netdev, "%s feature 0x%llx failed err %d\n", | |
2404 | enable ? "Enable" : "Disable", feature, err); | |
2405 | return err; | |
2406 | } | |
2407 | ||
2408 | MLX5E_SET_FEATURE(netdev, feature, enable); | |
2409 | return 0; | |
2410 | } | |
2411 | ||
2412 | static int mlx5e_set_features(struct net_device *netdev, | |
2413 | netdev_features_t features) | |
2414 | { | |
2415 | int err; | |
2416 | ||
2417 | err = mlx5e_handle_feature(netdev, features, NETIF_F_LRO, | |
2418 | set_feature_lro); | |
2419 | err |= mlx5e_handle_feature(netdev, features, | |
2420 | NETIF_F_HW_VLAN_CTAG_FILTER, | |
2421 | set_feature_vlan_filter); | |
2422 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC, | |
2423 | set_feature_tc_num_filters); | |
94cb1ebb EBE |
2424 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL, |
2425 | set_feature_rx_all); | |
36350114 GP |
2426 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX, |
2427 | set_feature_rx_vlan); | |
45bf454a MG |
2428 | #ifdef CONFIG_RFS_ACCEL |
2429 | err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE, | |
2430 | set_feature_arfs); | |
2431 | #endif | |
0e405443 GP |
2432 | |
2433 | return err ? -EINVAL : 0; | |
f62b8bb8 AV |
2434 | } |
2435 | ||
d8edd246 SM |
2436 | #define MXL5_HW_MIN_MTU 64 |
2437 | #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN) | |
2438 | ||
f62b8bb8 AV |
2439 | static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu) |
2440 | { | |
2441 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2442 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 2443 | bool was_opened; |
046339ea | 2444 | u16 max_mtu; |
d8edd246 | 2445 | u16 min_mtu; |
98e81b0a | 2446 | int err = 0; |
f62b8bb8 | 2447 | |
facc9699 | 2448 | mlx5_query_port_max_mtu(mdev, &max_mtu, 1); |
f62b8bb8 | 2449 | |
50a9eea6 | 2450 | max_mtu = MLX5E_HW2SW_MTU(max_mtu); |
d8edd246 | 2451 | min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU); |
50a9eea6 | 2452 | |
d8edd246 | 2453 | if (new_mtu > max_mtu || new_mtu < min_mtu) { |
facc9699 | 2454 | netdev_err(netdev, |
d8edd246 SM |
2455 | "%s: Bad MTU (%d), valid range is: [%d..%d]\n", |
2456 | __func__, new_mtu, min_mtu, max_mtu); | |
f62b8bb8 AV |
2457 | return -EINVAL; |
2458 | } | |
2459 | ||
2460 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
2461 | |
2462 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
2463 | if (was_opened) | |
2464 | mlx5e_close_locked(netdev); | |
2465 | ||
f62b8bb8 | 2466 | netdev->mtu = new_mtu; |
98e81b0a AS |
2467 | |
2468 | if (was_opened) | |
2469 | err = mlx5e_open_locked(netdev); | |
2470 | ||
f62b8bb8 AV |
2471 | mutex_unlock(&priv->state_lock); |
2472 | ||
2473 | return err; | |
2474 | } | |
2475 | ||
ef9814de EBE |
2476 | static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2477 | { | |
2478 | switch (cmd) { | |
2479 | case SIOCSHWTSTAMP: | |
2480 | return mlx5e_hwstamp_set(dev, ifr); | |
2481 | case SIOCGHWTSTAMP: | |
2482 | return mlx5e_hwstamp_get(dev, ifr); | |
2483 | default: | |
2484 | return -EOPNOTSUPP; | |
2485 | } | |
2486 | } | |
2487 | ||
66e49ded SM |
2488 | static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac) |
2489 | { | |
2490 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2491 | struct mlx5_core_dev *mdev = priv->mdev; | |
2492 | ||
2493 | return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac); | |
2494 | } | |
2495 | ||
2496 | static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos) | |
2497 | { | |
2498 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2499 | struct mlx5_core_dev *mdev = priv->mdev; | |
2500 | ||
2501 | return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1, | |
2502 | vlan, qos); | |
2503 | } | |
2504 | ||
f942380c MHY |
2505 | static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting) |
2506 | { | |
2507 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2508 | struct mlx5_core_dev *mdev = priv->mdev; | |
2509 | ||
2510 | return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting); | |
2511 | } | |
2512 | ||
1edc57e2 MHY |
2513 | static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting) |
2514 | { | |
2515 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2516 | struct mlx5_core_dev *mdev = priv->mdev; | |
2517 | ||
2518 | return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting); | |
2519 | } | |
66e49ded SM |
2520 | static int mlx5_vport_link2ifla(u8 esw_link) |
2521 | { | |
2522 | switch (esw_link) { | |
2523 | case MLX5_ESW_VPORT_ADMIN_STATE_DOWN: | |
2524 | return IFLA_VF_LINK_STATE_DISABLE; | |
2525 | case MLX5_ESW_VPORT_ADMIN_STATE_UP: | |
2526 | return IFLA_VF_LINK_STATE_ENABLE; | |
2527 | } | |
2528 | return IFLA_VF_LINK_STATE_AUTO; | |
2529 | } | |
2530 | ||
2531 | static int mlx5_ifla_link2vport(u8 ifla_link) | |
2532 | { | |
2533 | switch (ifla_link) { | |
2534 | case IFLA_VF_LINK_STATE_DISABLE: | |
2535 | return MLX5_ESW_VPORT_ADMIN_STATE_DOWN; | |
2536 | case IFLA_VF_LINK_STATE_ENABLE: | |
2537 | return MLX5_ESW_VPORT_ADMIN_STATE_UP; | |
2538 | } | |
2539 | return MLX5_ESW_VPORT_ADMIN_STATE_AUTO; | |
2540 | } | |
2541 | ||
2542 | static int mlx5e_set_vf_link_state(struct net_device *dev, int vf, | |
2543 | int link_state) | |
2544 | { | |
2545 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2546 | struct mlx5_core_dev *mdev = priv->mdev; | |
2547 | ||
2548 | return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1, | |
2549 | mlx5_ifla_link2vport(link_state)); | |
2550 | } | |
2551 | ||
2552 | static int mlx5e_get_vf_config(struct net_device *dev, | |
2553 | int vf, struct ifla_vf_info *ivi) | |
2554 | { | |
2555 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2556 | struct mlx5_core_dev *mdev = priv->mdev; | |
2557 | int err; | |
2558 | ||
2559 | err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi); | |
2560 | if (err) | |
2561 | return err; | |
2562 | ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate); | |
2563 | return 0; | |
2564 | } | |
2565 | ||
2566 | static int mlx5e_get_vf_stats(struct net_device *dev, | |
2567 | int vf, struct ifla_vf_stats *vf_stats) | |
2568 | { | |
2569 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2570 | struct mlx5_core_dev *mdev = priv->mdev; | |
2571 | ||
2572 | return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1, | |
2573 | vf_stats); | |
2574 | } | |
2575 | ||
b3f63c3d MF |
2576 | static void mlx5e_add_vxlan_port(struct net_device *netdev, |
2577 | sa_family_t sa_family, __be16 port) | |
2578 | { | |
2579 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2580 | ||
2581 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2582 | return; | |
2583 | ||
d8cf2dda | 2584 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1); |
b3f63c3d MF |
2585 | } |
2586 | ||
2587 | static void mlx5e_del_vxlan_port(struct net_device *netdev, | |
2588 | sa_family_t sa_family, __be16 port) | |
2589 | { | |
2590 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2591 | ||
2592 | if (!mlx5e_vxlan_allowed(priv->mdev)) | |
2593 | return; | |
2594 | ||
d8cf2dda | 2595 | mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0); |
b3f63c3d MF |
2596 | } |
2597 | ||
2598 | static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv, | |
2599 | struct sk_buff *skb, | |
2600 | netdev_features_t features) | |
2601 | { | |
2602 | struct udphdr *udph; | |
2603 | u16 proto; | |
2604 | u16 port = 0; | |
2605 | ||
2606 | switch (vlan_get_protocol(skb)) { | |
2607 | case htons(ETH_P_IP): | |
2608 | proto = ip_hdr(skb)->protocol; | |
2609 | break; | |
2610 | case htons(ETH_P_IPV6): | |
2611 | proto = ipv6_hdr(skb)->nexthdr; | |
2612 | break; | |
2613 | default: | |
2614 | goto out; | |
2615 | } | |
2616 | ||
2617 | if (proto == IPPROTO_UDP) { | |
2618 | udph = udp_hdr(skb); | |
2619 | port = be16_to_cpu(udph->dest); | |
2620 | } | |
2621 | ||
2622 | /* Verify if UDP port is being offloaded by HW */ | |
2623 | if (port && mlx5e_vxlan_lookup_port(priv, port)) | |
2624 | return features; | |
2625 | ||
2626 | out: | |
2627 | /* Disable CSUM and GSO if the udp dport is not offloaded by HW */ | |
2628 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
2629 | } | |
2630 | ||
2631 | static netdev_features_t mlx5e_features_check(struct sk_buff *skb, | |
2632 | struct net_device *netdev, | |
2633 | netdev_features_t features) | |
2634 | { | |
2635 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2636 | ||
2637 | features = vlan_features_check(skb, features); | |
2638 | features = vxlan_features_check(skb, features); | |
2639 | ||
2640 | /* Validate if the tunneled packet is being offloaded by HW */ | |
2641 | if (skb->encapsulation && | |
2642 | (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK)) | |
2643 | return mlx5e_vxlan_features_check(priv, skb, features); | |
2644 | ||
2645 | return features; | |
2646 | } | |
2647 | ||
3947ca18 DJ |
2648 | static void mlx5e_tx_timeout(struct net_device *dev) |
2649 | { | |
2650 | struct mlx5e_priv *priv = netdev_priv(dev); | |
2651 | bool sched_work = false; | |
2652 | int i; | |
2653 | ||
2654 | netdev_err(dev, "TX timeout detected\n"); | |
2655 | ||
2656 | for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) { | |
2657 | struct mlx5e_sq *sq = priv->txq_to_sq_map[i]; | |
2658 | ||
2659 | if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i))) | |
2660 | continue; | |
2661 | sched_work = true; | |
2662 | set_bit(MLX5E_SQ_STATE_TX_TIMEOUT, &sq->state); | |
2663 | netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n", | |
2664 | i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc); | |
2665 | } | |
2666 | ||
2667 | if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
2668 | schedule_work(&priv->tx_timeout_work); | |
2669 | } | |
2670 | ||
b0eed40e | 2671 | static const struct net_device_ops mlx5e_netdev_ops_basic = { |
f62b8bb8 AV |
2672 | .ndo_open = mlx5e_open, |
2673 | .ndo_stop = mlx5e_close, | |
2674 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2675 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2676 | .ndo_select_queue = mlx5e_select_queue, | |
f62b8bb8 AV |
2677 | .ndo_get_stats64 = mlx5e_get_stats, |
2678 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2679 | .ndo_set_mac_address = mlx5e_set_mac, | |
b0eed40e SM |
2680 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, |
2681 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
f62b8bb8 | 2682 | .ndo_set_features = mlx5e_set_features, |
b0eed40e SM |
2683 | .ndo_change_mtu = mlx5e_change_mtu, |
2684 | .ndo_do_ioctl = mlx5e_ioctl, | |
45bf454a MG |
2685 | #ifdef CONFIG_RFS_ACCEL |
2686 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2687 | #endif | |
3947ca18 | 2688 | .ndo_tx_timeout = mlx5e_tx_timeout, |
b0eed40e SM |
2689 | }; |
2690 | ||
2691 | static const struct net_device_ops mlx5e_netdev_ops_sriov = { | |
2692 | .ndo_open = mlx5e_open, | |
2693 | .ndo_stop = mlx5e_close, | |
2694 | .ndo_start_xmit = mlx5e_xmit, | |
08fb1dac SM |
2695 | .ndo_setup_tc = mlx5e_ndo_setup_tc, |
2696 | .ndo_select_queue = mlx5e_select_queue, | |
b0eed40e SM |
2697 | .ndo_get_stats64 = mlx5e_get_stats, |
2698 | .ndo_set_rx_mode = mlx5e_set_rx_mode, | |
2699 | .ndo_set_mac_address = mlx5e_set_mac, | |
2700 | .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid, | |
2701 | .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid, | |
2702 | .ndo_set_features = mlx5e_set_features, | |
2703 | .ndo_change_mtu = mlx5e_change_mtu, | |
2704 | .ndo_do_ioctl = mlx5e_ioctl, | |
b3f63c3d MF |
2705 | .ndo_add_vxlan_port = mlx5e_add_vxlan_port, |
2706 | .ndo_del_vxlan_port = mlx5e_del_vxlan_port, | |
2707 | .ndo_features_check = mlx5e_features_check, | |
45bf454a MG |
2708 | #ifdef CONFIG_RFS_ACCEL |
2709 | .ndo_rx_flow_steer = mlx5e_rx_flow_steer, | |
2710 | #endif | |
b0eed40e SM |
2711 | .ndo_set_vf_mac = mlx5e_set_vf_mac, |
2712 | .ndo_set_vf_vlan = mlx5e_set_vf_vlan, | |
f942380c | 2713 | .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk, |
1edc57e2 | 2714 | .ndo_set_vf_trust = mlx5e_set_vf_trust, |
b0eed40e SM |
2715 | .ndo_get_vf_config = mlx5e_get_vf_config, |
2716 | .ndo_set_vf_link_state = mlx5e_set_vf_link_state, | |
2717 | .ndo_get_vf_stats = mlx5e_get_vf_stats, | |
3947ca18 | 2718 | .ndo_tx_timeout = mlx5e_tx_timeout, |
f62b8bb8 AV |
2719 | }; |
2720 | ||
2721 | static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev) | |
2722 | { | |
2723 | if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) | |
2724 | return -ENOTSUPP; | |
2725 | if (!MLX5_CAP_GEN(mdev, eth_net_offloads) || | |
2726 | !MLX5_CAP_GEN(mdev, nic_flow_table) || | |
2727 | !MLX5_CAP_ETH(mdev, csum_cap) || | |
2728 | !MLX5_CAP_ETH(mdev, max_lso_cap) || | |
2729 | !MLX5_CAP_ETH(mdev, vlan_cap) || | |
796a27ec GP |
2730 | !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) || |
2731 | MLX5_CAP_FLOWTABLE(mdev, | |
2732 | flow_table_properties_nic_receive.max_ft_level) | |
2733 | < 3) { | |
f62b8bb8 AV |
2734 | mlx5_core_warn(mdev, |
2735 | "Not creating net device, some required device capabilities are missing\n"); | |
2736 | return -ENOTSUPP; | |
2737 | } | |
66189961 TT |
2738 | if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable)) |
2739 | mlx5_core_warn(mdev, "Self loop back prevention is not supported\n"); | |
7524a5d8 GP |
2740 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
2741 | mlx5_core_warn(mdev, "CQ modiration is not supported\n"); | |
66189961 | 2742 | |
f62b8bb8 AV |
2743 | return 0; |
2744 | } | |
2745 | ||
58d52291 AS |
2746 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev) |
2747 | { | |
2748 | int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2; | |
2749 | ||
2750 | return bf_buf_size - | |
2751 | sizeof(struct mlx5e_tx_wqe) + | |
2752 | 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/; | |
2753 | } | |
2754 | ||
08fb1dac SM |
2755 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2756 | static void mlx5e_ets_init(struct mlx5e_priv *priv) | |
2757 | { | |
2758 | int i; | |
2759 | ||
2760 | priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1; | |
2761 | for (i = 0; i < priv->params.ets.ets_cap; i++) { | |
2762 | priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC; | |
2763 | priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR; | |
2764 | priv->params.ets.prio_tc[i] = i; | |
2765 | } | |
2766 | ||
2767 | /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */ | |
2768 | priv->params.ets.prio_tc[0] = 1; | |
2769 | priv->params.ets.prio_tc[1] = 0; | |
2770 | } | |
2771 | #endif | |
2772 | ||
d8c9660d TT |
2773 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
2774 | u32 *indirection_rqt, int len, | |
85082dba TT |
2775 | int num_channels) |
2776 | { | |
d8c9660d TT |
2777 | int node = mdev->priv.numa_node; |
2778 | int node_num_of_cores; | |
85082dba TT |
2779 | int i; |
2780 | ||
d8c9660d TT |
2781 | if (node == -1) |
2782 | node = first_online_node; | |
2783 | ||
2784 | node_num_of_cores = cpumask_weight(cpumask_of_node(node)); | |
2785 | ||
2786 | if (node_num_of_cores) | |
2787 | num_channels = min_t(int, num_channels, node_num_of_cores); | |
2788 | ||
85082dba TT |
2789 | for (i = 0; i < len; i++) |
2790 | indirection_rqt[i] = i % num_channels; | |
2791 | } | |
2792 | ||
bc77b240 TT |
2793 | static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev) |
2794 | { | |
2795 | return MLX5_CAP_GEN(mdev, striding_rq) && | |
2796 | MLX5_CAP_GEN(mdev, umr_ptr_rlky) && | |
2797 | MLX5_CAP_ETH(mdev, reg_umr_sq); | |
2798 | } | |
2799 | ||
b797a684 SM |
2800 | static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw) |
2801 | { | |
2802 | enum pcie_link_width width; | |
2803 | enum pci_bus_speed speed; | |
2804 | int err = 0; | |
2805 | ||
2806 | err = pcie_get_minimum_link(mdev->pdev, &speed, &width); | |
2807 | if (err) | |
2808 | return err; | |
2809 | ||
2810 | if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) | |
2811 | return -EINVAL; | |
2812 | ||
2813 | switch (speed) { | |
2814 | case PCIE_SPEED_2_5GT: | |
2815 | *pci_bw = 2500 * width; | |
2816 | break; | |
2817 | case PCIE_SPEED_5_0GT: | |
2818 | *pci_bw = 5000 * width; | |
2819 | break; | |
2820 | case PCIE_SPEED_8_0GT: | |
2821 | *pci_bw = 8000 * width; | |
2822 | break; | |
2823 | default: | |
2824 | return -EINVAL; | |
2825 | } | |
2826 | ||
2827 | return 0; | |
2828 | } | |
2829 | ||
2830 | static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) | |
2831 | { | |
2832 | return (link_speed && pci_bw && | |
2833 | (pci_bw < 40000) && (pci_bw < link_speed)); | |
2834 | } | |
2835 | ||
f62b8bb8 AV |
2836 | static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, |
2837 | struct net_device *netdev, | |
936896e9 | 2838 | int num_channels) |
f62b8bb8 AV |
2839 | { |
2840 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
b797a684 SM |
2841 | u32 link_speed = 0; |
2842 | u32 pci_bw = 0; | |
f62b8bb8 AV |
2843 | |
2844 | priv->params.log_sq_size = | |
2845 | MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE; | |
bc77b240 | 2846 | priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ? |
461017cb TT |
2847 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ : |
2848 | MLX5_WQ_TYPE_LINKED_LIST; | |
2849 | ||
b797a684 SM |
2850 | /* set CQE compression */ |
2851 | priv->params.rx_cqe_compress_admin = false; | |
2852 | if (MLX5_CAP_GEN(mdev, cqe_compression) && | |
2853 | MLX5_CAP_GEN(mdev, vport_group_manager)) { | |
2854 | mlx5e_get_max_linkspeed(mdev, &link_speed); | |
2855 | mlx5e_get_pci_bw(mdev, &pci_bw); | |
2856 | mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n", | |
2857 | link_speed, pci_bw); | |
2858 | priv->params.rx_cqe_compress_admin = | |
2859 | cqe_compress_heuristic(link_speed, pci_bw); | |
2860 | } | |
2861 | ||
2862 | priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin; | |
2863 | ||
461017cb TT |
2864 | switch (priv->params.rq_wq_type) { |
2865 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
2866 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW; | |
d9d9f156 TT |
2867 | priv->params.mpwqe_log_stride_sz = |
2868 | priv->params.rx_cqe_compress ? | |
2869 | MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS : | |
2870 | MLX5_MPWRQ_LOG_STRIDE_SIZE; | |
2871 | priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - | |
2872 | priv->params.mpwqe_log_stride_sz; | |
461017cb TT |
2873 | priv->params.lro_en = true; |
2874 | break; | |
2875 | default: /* MLX5_WQ_TYPE_LINKED_LIST */ | |
2876 | priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE; | |
2877 | } | |
2878 | ||
d9d9f156 TT |
2879 | mlx5_core_info(mdev, |
2880 | "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n", | |
2881 | priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ, | |
2882 | BIT(priv->params.log_rq_size), | |
2883 | BIT(priv->params.mpwqe_log_stride_sz), | |
2884 | priv->params.rx_cqe_compress_admin); | |
2885 | ||
461017cb TT |
2886 | priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type, |
2887 | BIT(priv->params.log_rq_size)); | |
f62b8bb8 AV |
2888 | priv->params.rx_cq_moderation_usec = |
2889 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC; | |
2890 | priv->params.rx_cq_moderation_pkts = | |
2891 | MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS; | |
2892 | priv->params.tx_cq_moderation_usec = | |
2893 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC; | |
2894 | priv->params.tx_cq_moderation_pkts = | |
2895 | MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS; | |
58d52291 | 2896 | priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev); |
f62b8bb8 | 2897 | priv->params.num_tc = 1; |
2be6967c | 2898 | priv->params.rss_hfunc = ETH_RSS_HASH_XOR; |
f62b8bb8 | 2899 | |
57afead5 AS |
2900 | netdev_rss_key_fill(priv->params.toeplitz_hash_key, |
2901 | sizeof(priv->params.toeplitz_hash_key)); | |
2902 | ||
d8c9660d | 2903 | mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt, |
85082dba | 2904 | MLX5E_INDIR_RQT_SIZE, num_channels); |
2d75b2bc | 2905 | |
f62b8bb8 AV |
2906 | priv->params.lro_wqe_sz = |
2907 | MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ; | |
2908 | ||
2909 | priv->mdev = mdev; | |
2910 | priv->netdev = netdev; | |
936896e9 | 2911 | priv->params.num_channels = num_channels; |
f62b8bb8 | 2912 | |
08fb1dac SM |
2913 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2914 | mlx5e_ets_init(priv); | |
2915 | #endif | |
f62b8bb8 | 2916 | |
f62b8bb8 AV |
2917 | mutex_init(&priv->state_lock); |
2918 | ||
2919 | INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work); | |
2920 | INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work); | |
3947ca18 | 2921 | INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work); |
f62b8bb8 AV |
2922 | INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work); |
2923 | } | |
2924 | ||
2925 | static void mlx5e_set_netdev_dev_addr(struct net_device *netdev) | |
2926 | { | |
2927 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2928 | ||
e1d7d349 | 2929 | mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr); |
108805fc SM |
2930 | if (is_zero_ether_addr(netdev->dev_addr) && |
2931 | !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) { | |
2932 | eth_hw_addr_random(netdev); | |
2933 | mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr); | |
2934 | } | |
f62b8bb8 AV |
2935 | } |
2936 | ||
2937 | static void mlx5e_build_netdev(struct net_device *netdev) | |
2938 | { | |
2939 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
2940 | struct mlx5_core_dev *mdev = priv->mdev; | |
94cb1ebb EBE |
2941 | bool fcs_supported; |
2942 | bool fcs_enabled; | |
f62b8bb8 AV |
2943 | |
2944 | SET_NETDEV_DEV(netdev, &mdev->pdev->dev); | |
2945 | ||
08fb1dac | 2946 | if (MLX5_CAP_GEN(mdev, vport_group_manager)) { |
b0eed40e | 2947 | netdev->netdev_ops = &mlx5e_netdev_ops_sriov; |
08fb1dac SM |
2948 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
2949 | netdev->dcbnl_ops = &mlx5e_dcbnl_ops; | |
2950 | #endif | |
2951 | } else { | |
b0eed40e | 2952 | netdev->netdev_ops = &mlx5e_netdev_ops_basic; |
08fb1dac | 2953 | } |
66e49ded | 2954 | |
f62b8bb8 AV |
2955 | netdev->watchdog_timeo = 15 * HZ; |
2956 | ||
2957 | netdev->ethtool_ops = &mlx5e_ethtool_ops; | |
2958 | ||
12be4b21 | 2959 | netdev->vlan_features |= NETIF_F_SG; |
f62b8bb8 AV |
2960 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
2961 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; | |
2962 | netdev->vlan_features |= NETIF_F_GRO; | |
2963 | netdev->vlan_features |= NETIF_F_TSO; | |
2964 | netdev->vlan_features |= NETIF_F_TSO6; | |
2965 | netdev->vlan_features |= NETIF_F_RXCSUM; | |
2966 | netdev->vlan_features |= NETIF_F_RXHASH; | |
2967 | ||
2968 | if (!!MLX5_CAP_ETH(mdev, lro_cap)) | |
2969 | netdev->vlan_features |= NETIF_F_LRO; | |
2970 | ||
2971 | netdev->hw_features = netdev->vlan_features; | |
e4cf27bd | 2972 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; |
f62b8bb8 AV |
2973 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; |
2974 | netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; | |
2975 | ||
b3f63c3d | 2976 | if (mlx5e_vxlan_allowed(mdev)) { |
b49663c8 AD |
2977 | netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | |
2978 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
2979 | NETIF_F_GSO_PARTIAL; | |
b3f63c3d | 2980 | netdev->hw_enc_features |= NETIF_F_IP_CSUM; |
f3ed653c | 2981 | netdev->hw_enc_features |= NETIF_F_IPV6_CSUM; |
b3f63c3d MF |
2982 | netdev->hw_enc_features |= NETIF_F_TSO; |
2983 | netdev->hw_enc_features |= NETIF_F_TSO6; | |
b3f63c3d | 2984 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; |
b49663c8 AD |
2985 | netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM | |
2986 | NETIF_F_GSO_PARTIAL; | |
2987 | netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM; | |
b3f63c3d MF |
2988 | } |
2989 | ||
94cb1ebb EBE |
2990 | mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled); |
2991 | ||
2992 | if (fcs_supported) | |
2993 | netdev->hw_features |= NETIF_F_RXALL; | |
2994 | ||
f62b8bb8 AV |
2995 | netdev->features = netdev->hw_features; |
2996 | if (!priv->params.lro_en) | |
2997 | netdev->features &= ~NETIF_F_LRO; | |
2998 | ||
94cb1ebb EBE |
2999 | if (fcs_enabled) |
3000 | netdev->features &= ~NETIF_F_RXALL; | |
3001 | ||
e8f887ac AV |
3002 | #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f) |
3003 | if (FT_CAP(flow_modify_en) && | |
3004 | FT_CAP(modify_root) && | |
3005 | FT_CAP(identified_miss_table_mode) && | |
1cabe6b0 MG |
3006 | FT_CAP(flow_table_modify)) { |
3007 | netdev->hw_features |= NETIF_F_HW_TC; | |
3008 | #ifdef CONFIG_RFS_ACCEL | |
3009 | netdev->hw_features |= NETIF_F_NTUPLE; | |
3010 | #endif | |
3011 | } | |
e8f887ac | 3012 | |
f62b8bb8 AV |
3013 | netdev->features |= NETIF_F_HIGHDMA; |
3014 | ||
3015 | netdev->priv_flags |= IFF_UNICAST_FLT; | |
3016 | ||
3017 | mlx5e_set_netdev_dev_addr(netdev); | |
3018 | } | |
3019 | ||
3020 | static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn, | |
a606b0f6 | 3021 | struct mlx5_core_mkey *mkey) |
f62b8bb8 AV |
3022 | { |
3023 | struct mlx5_core_dev *mdev = priv->mdev; | |
3024 | struct mlx5_create_mkey_mbox_in *in; | |
3025 | int err; | |
3026 | ||
3027 | in = mlx5_vzalloc(sizeof(*in)); | |
3028 | if (!in) | |
3029 | return -ENOMEM; | |
3030 | ||
3031 | in->seg.flags = MLX5_PERM_LOCAL_WRITE | | |
3032 | MLX5_PERM_LOCAL_READ | | |
3033 | MLX5_ACCESS_MODE_PA; | |
3034 | in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64); | |
3035 | in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
3036 | ||
a606b0f6 | 3037 | err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL, |
f62b8bb8 AV |
3038 | NULL); |
3039 | ||
3040 | kvfree(in); | |
3041 | ||
3042 | return err; | |
3043 | } | |
3044 | ||
593cf338 RS |
3045 | static void mlx5e_create_q_counter(struct mlx5e_priv *priv) |
3046 | { | |
3047 | struct mlx5_core_dev *mdev = priv->mdev; | |
3048 | int err; | |
3049 | ||
3050 | err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter); | |
3051 | if (err) { | |
3052 | mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err); | |
3053 | priv->q_counter = 0; | |
3054 | } | |
3055 | } | |
3056 | ||
3057 | static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv) | |
3058 | { | |
3059 | if (!priv->q_counter) | |
3060 | return; | |
3061 | ||
3062 | mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter); | |
3063 | } | |
3064 | ||
bc77b240 TT |
3065 | static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv) |
3066 | { | |
3067 | struct mlx5_core_dev *mdev = priv->mdev; | |
3068 | struct mlx5_create_mkey_mbox_in *in; | |
3069 | struct mlx5_mkey_seg *mkc; | |
3070 | int inlen = sizeof(*in); | |
3071 | u64 npages = | |
3072 | mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS; | |
3073 | int err; | |
3074 | ||
3075 | in = mlx5_vzalloc(inlen); | |
3076 | if (!in) | |
3077 | return -ENOMEM; | |
3078 | ||
3079 | mkc = &in->seg; | |
3080 | mkc->status = MLX5_MKEY_STATUS_FREE; | |
3081 | mkc->flags = MLX5_PERM_UMR_EN | | |
3082 | MLX5_PERM_LOCAL_READ | | |
3083 | MLX5_PERM_LOCAL_WRITE | | |
3084 | MLX5_ACCESS_MODE_MTT; | |
3085 | ||
3086 | mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8); | |
3087 | mkc->flags_pd = cpu_to_be32(priv->pdn); | |
3088 | mkc->len = cpu_to_be64(npages << PAGE_SHIFT); | |
3089 | mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages)); | |
3090 | mkc->log2_page_size = PAGE_SHIFT; | |
3091 | ||
3092 | err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL, | |
3093 | NULL, NULL); | |
3094 | ||
3095 | kvfree(in); | |
3096 | ||
3097 | return err; | |
3098 | } | |
3099 | ||
f62b8bb8 AV |
3100 | static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev) |
3101 | { | |
3102 | struct net_device *netdev; | |
3103 | struct mlx5e_priv *priv; | |
3435ab59 | 3104 | int nch = mlx5e_get_max_num_channels(mdev); |
f62b8bb8 AV |
3105 | int err; |
3106 | ||
3107 | if (mlx5e_check_required_hca_cap(mdev)) | |
3108 | return NULL; | |
3109 | ||
08fb1dac SM |
3110 | netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv), |
3111 | nch * MLX5E_MAX_NUM_TC, | |
3112 | nch); | |
f62b8bb8 AV |
3113 | if (!netdev) { |
3114 | mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n"); | |
3115 | return NULL; | |
3116 | } | |
3117 | ||
936896e9 | 3118 | mlx5e_build_netdev_priv(mdev, netdev, nch); |
f62b8bb8 AV |
3119 | mlx5e_build_netdev(netdev); |
3120 | ||
3121 | netif_carrier_off(netdev); | |
3122 | ||
3123 | priv = netdev_priv(netdev); | |
3124 | ||
7bb29755 MF |
3125 | priv->wq = create_singlethread_workqueue("mlx5e"); |
3126 | if (!priv->wq) | |
3127 | goto err_free_netdev; | |
3128 | ||
0ba42241 | 3129 | err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false); |
f62b8bb8 | 3130 | if (err) { |
1f2a3003 | 3131 | mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err); |
7bb29755 | 3132 | goto err_destroy_wq; |
f62b8bb8 AV |
3133 | } |
3134 | ||
3135 | err = mlx5_core_alloc_pd(mdev, &priv->pdn); | |
3136 | if (err) { | |
1f2a3003 | 3137 | mlx5_core_err(mdev, "alloc pd failed, %d\n", err); |
f62b8bb8 AV |
3138 | goto err_unmap_free_uar; |
3139 | } | |
3140 | ||
8d7f9ecb | 3141 | err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn); |
3191e05f | 3142 | if (err) { |
1f2a3003 | 3143 | mlx5_core_err(mdev, "alloc td failed, %d\n", err); |
3191e05f AS |
3144 | goto err_dealloc_pd; |
3145 | } | |
3146 | ||
a606b0f6 | 3147 | err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey); |
f62b8bb8 | 3148 | if (err) { |
1f2a3003 | 3149 | mlx5_core_err(mdev, "create mkey failed, %d\n", err); |
3191e05f | 3150 | goto err_dealloc_transport_domain; |
f62b8bb8 AV |
3151 | } |
3152 | ||
bc77b240 TT |
3153 | err = mlx5e_create_umr_mkey(priv); |
3154 | if (err) { | |
3155 | mlx5_core_err(mdev, "create umr mkey failed, %d\n", err); | |
3156 | goto err_destroy_mkey; | |
3157 | } | |
3158 | ||
40ab6a6e | 3159 | err = mlx5e_create_tises(priv); |
5c50368f | 3160 | if (err) { |
40ab6a6e | 3161 | mlx5_core_warn(mdev, "create tises failed, %d\n", err); |
bc77b240 | 3162 | goto err_destroy_umr_mkey; |
5c50368f AS |
3163 | } |
3164 | ||
3165 | err = mlx5e_open_drop_rq(priv); | |
3166 | if (err) { | |
3167 | mlx5_core_err(mdev, "open drop rq failed, %d\n", err); | |
40ab6a6e | 3168 | goto err_destroy_tises; |
5c50368f AS |
3169 | } |
3170 | ||
1da36696 | 3171 | err = mlx5e_create_rqts(priv); |
5c50368f | 3172 | if (err) { |
1da36696 | 3173 | mlx5_core_warn(mdev, "create rqts failed, %d\n", err); |
5c50368f AS |
3174 | goto err_close_drop_rq; |
3175 | } | |
3176 | ||
40ab6a6e | 3177 | err = mlx5e_create_tirs(priv); |
5c50368f | 3178 | if (err) { |
40ab6a6e | 3179 | mlx5_core_warn(mdev, "create tirs failed, %d\n", err); |
1da36696 | 3180 | goto err_destroy_rqts; |
5c50368f AS |
3181 | } |
3182 | ||
acff797c | 3183 | err = mlx5e_create_flow_steering(priv); |
5c50368f | 3184 | if (err) { |
acff797c | 3185 | mlx5_core_warn(mdev, "create flow steering failed, %d\n", err); |
40ab6a6e | 3186 | goto err_destroy_tirs; |
5c50368f AS |
3187 | } |
3188 | ||
593cf338 RS |
3189 | mlx5e_create_q_counter(priv); |
3190 | ||
33cfaaa8 | 3191 | mlx5e_init_l2_addr(priv); |
5c50368f | 3192 | |
b3f63c3d MF |
3193 | mlx5e_vxlan_init(priv); |
3194 | ||
e8f887ac AV |
3195 | err = mlx5e_tc_init(priv); |
3196 | if (err) | |
593cf338 | 3197 | goto err_dealloc_q_counters; |
e8f887ac | 3198 | |
08fb1dac SM |
3199 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
3200 | mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets); | |
3201 | #endif | |
3202 | ||
f62b8bb8 AV |
3203 | err = register_netdev(netdev); |
3204 | if (err) { | |
1f2a3003 | 3205 | mlx5_core_err(mdev, "register_netdev failed, %d\n", err); |
e8f887ac | 3206 | goto err_tc_cleanup; |
f62b8bb8 AV |
3207 | } |
3208 | ||
01a14098 MF |
3209 | if (mlx5e_vxlan_allowed(mdev)) { |
3210 | rtnl_lock(); | |
b3f63c3d | 3211 | vxlan_get_rx_port(netdev); |
01a14098 MF |
3212 | rtnl_unlock(); |
3213 | } | |
b3f63c3d | 3214 | |
f62b8bb8 | 3215 | mlx5e_enable_async_events(priv); |
7bb29755 | 3216 | queue_work(priv->wq, &priv->set_rx_mode_work); |
f62b8bb8 AV |
3217 | |
3218 | return priv; | |
3219 | ||
e8f887ac AV |
3220 | err_tc_cleanup: |
3221 | mlx5e_tc_cleanup(priv); | |
3222 | ||
593cf338 RS |
3223 | err_dealloc_q_counters: |
3224 | mlx5e_destroy_q_counter(priv); | |
acff797c | 3225 | mlx5e_destroy_flow_steering(priv); |
5c50368f | 3226 | |
40ab6a6e AS |
3227 | err_destroy_tirs: |
3228 | mlx5e_destroy_tirs(priv); | |
5c50368f | 3229 | |
1da36696 TT |
3230 | err_destroy_rqts: |
3231 | mlx5e_destroy_rqts(priv); | |
5c50368f AS |
3232 | |
3233 | err_close_drop_rq: | |
3234 | mlx5e_close_drop_rq(priv); | |
3235 | ||
40ab6a6e AS |
3236 | err_destroy_tises: |
3237 | mlx5e_destroy_tises(priv); | |
5c50368f | 3238 | |
bc77b240 TT |
3239 | err_destroy_umr_mkey: |
3240 | mlx5_core_destroy_mkey(mdev, &priv->umr_mkey); | |
3241 | ||
f62b8bb8 | 3242 | err_destroy_mkey: |
a606b0f6 | 3243 | mlx5_core_destroy_mkey(mdev, &priv->mkey); |
f62b8bb8 | 3244 | |
3191e05f | 3245 | err_dealloc_transport_domain: |
8d7f9ecb | 3246 | mlx5_core_dealloc_transport_domain(mdev, priv->tdn); |
3191e05f | 3247 | |
f62b8bb8 AV |
3248 | err_dealloc_pd: |
3249 | mlx5_core_dealloc_pd(mdev, priv->pdn); | |
3250 | ||
3251 | err_unmap_free_uar: | |
3252 | mlx5_unmap_free_uar(mdev, &priv->cq_uar); | |
3253 | ||
7bb29755 MF |
3254 | err_destroy_wq: |
3255 | destroy_workqueue(priv->wq); | |
3256 | ||
f62b8bb8 AV |
3257 | err_free_netdev: |
3258 | free_netdev(netdev); | |
3259 | ||
3260 | return NULL; | |
3261 | } | |
3262 | ||
3263 | static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv) | |
3264 | { | |
3265 | struct mlx5e_priv *priv = vpriv; | |
3266 | struct net_device *netdev = priv->netdev; | |
3267 | ||
9b37b07f AS |
3268 | set_bit(MLX5E_STATE_DESTROYING, &priv->state); |
3269 | ||
7bb29755 | 3270 | queue_work(priv->wq, &priv->set_rx_mode_work); |
1cefa326 | 3271 | mlx5e_disable_async_events(priv); |
7bb29755 | 3272 | flush_workqueue(priv->wq); |
5fc7197d MD |
3273 | if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) { |
3274 | netif_device_detach(netdev); | |
811afeaa | 3275 | mlx5e_close(netdev); |
5fc7197d MD |
3276 | } else { |
3277 | unregister_netdev(netdev); | |
3278 | } | |
3279 | ||
e8f887ac | 3280 | mlx5e_tc_cleanup(priv); |
b3f63c3d | 3281 | mlx5e_vxlan_cleanup(priv); |
593cf338 | 3282 | mlx5e_destroy_q_counter(priv); |
acff797c | 3283 | mlx5e_destroy_flow_steering(priv); |
40ab6a6e | 3284 | mlx5e_destroy_tirs(priv); |
1da36696 | 3285 | mlx5e_destroy_rqts(priv); |
5c50368f | 3286 | mlx5e_close_drop_rq(priv); |
40ab6a6e | 3287 | mlx5e_destroy_tises(priv); |
bc77b240 | 3288 | mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey); |
a606b0f6 | 3289 | mlx5_core_destroy_mkey(priv->mdev, &priv->mkey); |
8d7f9ecb | 3290 | mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn); |
f62b8bb8 AV |
3291 | mlx5_core_dealloc_pd(priv->mdev, priv->pdn); |
3292 | mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar); | |
7bb29755 MF |
3293 | cancel_delayed_work_sync(&priv->update_stats_work); |
3294 | destroy_workqueue(priv->wq); | |
5fc7197d MD |
3295 | |
3296 | if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) | |
3297 | free_netdev(netdev); | |
f62b8bb8 AV |
3298 | } |
3299 | ||
3300 | static void *mlx5e_get_netdev(void *vpriv) | |
3301 | { | |
3302 | struct mlx5e_priv *priv = vpriv; | |
3303 | ||
3304 | return priv->netdev; | |
3305 | } | |
3306 | ||
3307 | static struct mlx5_interface mlx5e_interface = { | |
3308 | .add = mlx5e_create_netdev, | |
3309 | .remove = mlx5e_destroy_netdev, | |
3310 | .event = mlx5e_async_event, | |
3311 | .protocol = MLX5_INTERFACE_PROTOCOL_ETH, | |
3312 | .get_dev = mlx5e_get_netdev, | |
3313 | }; | |
3314 | ||
3315 | void mlx5e_init(void) | |
3316 | { | |
3317 | mlx5_register_interface(&mlx5e_interface); | |
3318 | } | |
3319 | ||
3320 | void mlx5e_cleanup(void) | |
3321 | { | |
3322 | mlx5_unregister_interface(&mlx5e_interface); | |
3323 | } |