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net/mlx5: PTP code migration to driver core section
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_ethtool.c
CommitLineData
f62b8bb8
AV		 1/*
2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include "en.h"
164f16f7 34#include "en_accel/ipsec.h"
f62b8bb8 35
076b0936
ES		 36void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv,
37 struct ethtool_drvinfo *drvinfo)
f62b8bb8 38{
f62b8bb8
AV		 39 struct mlx5_core_dev *mdev = priv->mdev;
40
41 strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver));
7913d205 42 strlcpy(drvinfo->version, DRIVER_VERSION,
f62b8bb8
AV		 43 sizeof(drvinfo->version));
44 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
84e11edb
IK		 45 "%d.%d.%04d (%.16s)",
46 fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev),
47 mdev->board_id);
f62b8bb8
AV		 48 strlcpy(drvinfo->bus_info, pci_name(mdev->pdev),
49 sizeof(drvinfo->bus_info));
50}
51
076b0936
ES		 52static void mlx5e_get_drvinfo(struct net_device *dev,
53 struct ethtool_drvinfo *drvinfo)
54{
55 struct mlx5e_priv *priv = netdev_priv(dev);
56
57 mlx5e_ethtool_get_drvinfo(priv, drvinfo);
58}
59
665bc539
GP		 60struct ptys2ethtool_config {
61 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
62 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised);
f62b8bb8 63 u32 speed;
f62b8bb8
AV		 64};
65
665bc539
GP		 66static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER];
67
68#define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \
69 ({ \
70 struct ptys2ethtool_config *cfg; \
71 const unsigned int modes[] = { __VA_ARGS__ }; \
72 unsigned int i; \
73 cfg = &ptys2ethtool_table[reg_]; \
74 cfg->speed = speed_; \
75 bitmap_zero(cfg->supported, \
76 __ETHTOOL_LINK_MODE_MASK_NBITS); \
77 bitmap_zero(cfg->advertised, \
78 __ETHTOOL_LINK_MODE_MASK_NBITS); \
79 for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \
80 __set_bit(modes[i], cfg->supported); \
81 __set_bit(modes[i], cfg->advertised); \
82 } \
83 })
84
85void mlx5e_build_ptys2ethtool_map(void)
86{
87 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000,
88 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
89 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000,
90 ETHTOOL_LINK_MODE_1000baseKX_Full_BIT);
91 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000,
92 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
93 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000,
94 ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT);
95 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000,
96 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
97 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000,
98 ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT);
99 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000,
100 ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT);
101 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000,
102 ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT);
103 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000,
104 ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT);
105 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000,
106 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
107 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000,
108 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
109 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000,
110 ETHTOOL_LINK_MODE_10000baseKR_Full_BIT);
111 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000,
112 ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT);
113 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000,
114 ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT);
115 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000,
116 ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT);
117 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000,
118 ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT);
119 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000,
120 ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT);
121 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000,
122 ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT);
123 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000,
124 ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT);
125 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000,
126 ETHTOOL_LINK_MODE_10000baseT_Full_BIT);
127 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000,
128 ETHTOOL_LINK_MODE_25000baseCR_Full_BIT);
129 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000,
130 ETHTOOL_LINK_MODE_25000baseKR_Full_BIT);
131 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000,
132 ETHTOOL_LINK_MODE_25000baseSR_Full_BIT);
133 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000,
134 ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT);
135 MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000,
136 ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT);
137}
138
cf678570
GP		 139static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv)
140{
141 struct mlx5_core_dev *mdev = priv->mdev;
142 u8 pfc_en_tx;
143 u8 pfc_en_rx;
144 int err;
145
c66f2091
FD		 146 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
147 return 0;
148
cf678570
GP		 149 err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx);
150
151 return err ? 0 : pfc_en_tx | pfc_en_rx;
152}
153
e989d5a5
GP		 154static bool mlx5e_query_global_pause_combined(struct mlx5e_priv *priv)
155{
156 struct mlx5_core_dev *mdev = priv->mdev;
157 u32 rx_pause;
158 u32 tx_pause;
159 int err;
160
c66f2091
FD		 161 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
162 return false;
163
e989d5a5
GP		 164 err = mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
165
166 return err ? false : rx_pause | tx_pause;
167}
168
593cf338 169#define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter))
ff9c852f 170#define MLX5E_NUM_RQ_STATS(priv) (NUM_RQ_STATS * (priv)->channels.num)
9218b44d 171#define MLX5E_NUM_SQ_STATS(priv) \
6a9764ef 172 (NUM_SQ_STATS * (priv)->channels.num * (priv)->channels.params.num_tc)
ed80ec4c 173#define MLX5E_NUM_PFC_COUNTERS(priv) \
e989d5a5
GP		 174 ((mlx5e_query_global_pause_combined(priv) + hweight8(mlx5e_query_pfc_combined(priv))) * \
175 NUM_PPORT_PER_PRIO_PFC_COUNTERS)
593cf338 176
076b0936 177int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset)
f62b8bb8 178{
f62b8bb8
AV		 179 switch (sset) {
180 case ETH_SS_STATS:
9218b44d 181 return NUM_SW_COUNTERS +
593cf338 182 MLX5E_NUM_Q_CNTRS(priv) +
5db0a4f6 183 NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS(priv) +
0f7f3481 184 NUM_PCIE_COUNTERS(priv) +
9218b44d 185 MLX5E_NUM_RQ_STATS(priv) +
cf678570 186 MLX5E_NUM_SQ_STATS(priv) +
bedb7c90
HN		 187 MLX5E_NUM_PFC_COUNTERS(priv) +
188 ARRAY_SIZE(mlx5e_pme_status_desc) +
164f16f7
IT		 189 ARRAY_SIZE(mlx5e_pme_error_desc) +
190 mlx5e_ipsec_get_count(priv);
bedb7c90 191
4e59e288
GP		 192 case ETH_SS_PRIV_FLAGS:
193 return ARRAY_SIZE(mlx5e_priv_flags);
d605d668
KH		 194 case ETH_SS_TEST:
195 return mlx5e_self_test_num(priv);
f62b8bb8
AV		 196 /* fallthrough */
197 default:
198 return -EOPNOTSUPP;
199 }
200}
201
076b0936
ES		 202static int mlx5e_get_sset_count(struct net_device *dev, int sset)
203{
204 struct mlx5e_priv *priv = netdev_priv(dev);
205
206 return mlx5e_ethtool_get_sset_count(priv, sset);
207}
208
c045deef 209static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, u8 *data)
9218b44d 210{
cf678570
GP		 211 int i, j, tc, prio, idx = 0;
212 unsigned long pfc_combined;
9218b44d
GP		 213
214 /* SW counters */
215 for (i = 0; i < NUM_SW_COUNTERS; i++)
bfe6d8d1 216 strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format);
9218b44d
GP		 217
218 /* Q counters */
219 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
bfe6d8d1 220 strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format);
9218b44d
GP		 221
222 /* VPORT counters */
223 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
224 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 225 vport_stats_desc[i].format);
9218b44d
GP		 226
227 /* PPORT counters */
228 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
229 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 230 pport_802_3_stats_desc[i].format);
9218b44d
GP		 231
232 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
233 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 234 pport_2863_stats_desc[i].format);
9218b44d
GP		 235
236 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
237 strcpy(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 238 pport_2819_stats_desc[i].format);
9218b44d 239
5db0a4f6
GP		 240 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
241 strcpy(data + (idx++) * ETH_GSTRING_LEN,
242 pport_phy_statistical_stats_desc[i].format);
243
068aef33
GP		 244 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
245 strcpy(data + (idx++) * ETH_GSTRING_LEN,
246 pport_eth_ext_stats_desc[i].format);
247
0f7f3481
GP		 248 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
249 strcpy(data + (idx++) * ETH_GSTRING_LEN,
250 pcie_perf_stats_desc[i].format);
251
efae7f78 252 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
73e90646 253 strcpy(data + (idx++) * ETH_GSTRING_LEN,
efae7f78
EBE		 254 pcie_perf_stats_desc64[i].format);
255
256 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
09800305
GP		 257 strcpy(data + (idx++) * ETH_GSTRING_LEN,
258 pcie_perf_stall_stats_desc[i].format);
73e90646 259
cf678570
GP		 260 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
261 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
bfe6d8d1
GP		 262 sprintf(data + (idx++) * ETH_GSTRING_LEN,
263 pport_per_prio_traffic_stats_desc[i].format, prio);
cf678570
GP		 264 }
265
266 pfc_combined = mlx5e_query_pfc_combined(priv);
267 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
268 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
e989d5a5
GP		 269 char pfc_string[ETH_GSTRING_LEN];
270
271 snprintf(pfc_string, sizeof(pfc_string), "prio%d", prio);
bfe6d8d1 272 sprintf(data + (idx++) * ETH_GSTRING_LEN,
e989d5a5
GP		 273 pport_per_prio_pfc_stats_desc[i].format, pfc_string);
274 }
275 }
276
277 if (mlx5e_query_global_pause_combined(priv)) {
278 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
279 sprintf(data + (idx++) * ETH_GSTRING_LEN,
280 pport_per_prio_pfc_stats_desc[i].format, "global");
cf678570
GP		 281 }
282 }
283
bedb7c90
HN		 284 /* port module event counters */
285 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
286 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_status_desc[i].format);
287
288 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
289 strcpy(data + (idx++) * ETH_GSTRING_LEN, mlx5e_pme_error_desc[i].format);
290
164f16f7
IT		 291 /* IPSec counters */
292 idx += mlx5e_ipsec_get_strings(priv, data + idx * ETH_GSTRING_LEN);
293
9218b44d
GP		 294 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
295 return;
296
297 /* per channel counters */
ff9c852f 298 for (i = 0; i < priv->channels.num; i++)
9218b44d 299 for (j = 0; j < NUM_RQ_STATS; j++)
bfe6d8d1
GP		 300 sprintf(data + (idx++) * ETH_GSTRING_LEN,
301 rq_stats_desc[j].format, i);
9218b44d 302
6a9764ef 303 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 304 for (i = 0; i < priv->channels.num; i++)
9218b44d
GP		 305 for (j = 0; j < NUM_SQ_STATS; j++)
306 sprintf(data + (idx++) * ETH_GSTRING_LEN,
bfe6d8d1 307 sq_stats_desc[j].format,
acc6c595 308 priv->channel_tc2txq[i][tc]);
9218b44d
GP		 309}
310
c045deef 311void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, u32 stringset, u8 *data)
f62b8bb8 312{
4e59e288 313 int i;
f62b8bb8
AV		 314
315 switch (stringset) {
316 case ETH_SS_PRIV_FLAGS:
4e59e288
GP		 317 for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++)
318 strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]);
f62b8bb8
AV		 319 break;
320
321 case ETH_SS_TEST:
d605d668
KH		 322 for (i = 0; i < mlx5e_self_test_num(priv); i++)
323 strcpy(data + i * ETH_GSTRING_LEN,
324 mlx5e_self_tests[i]);
f62b8bb8
AV		 325 break;
326
327 case ETH_SS_STATS:
9218b44d 328 mlx5e_fill_stats_strings(priv, data);
f62b8bb8
AV		 329 break;
330 }
331}
332
c045deef 333static void mlx5e_get_strings(struct net_device *dev, u32 stringset, u8 *data)
f62b8bb8
AV		 334{
335 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 336
337 mlx5e_ethtool_get_strings(priv, stringset, data);
338}
339
340void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv,
341 struct ethtool_stats *stats, u64 *data)
342{
ff9c852f 343 struct mlx5e_channels *channels;
bedb7c90 344 struct mlx5_priv *mlx5_priv;
cf678570
GP		 345 int i, j, tc, prio, idx = 0;
346 unsigned long pfc_combined;
f62b8bb8
AV		 347
348 if (!data)
349 return;
350
351 mutex_lock(&priv->state_lock);
352 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3834a5e6 353 mlx5e_update_stats(priv, true);
ff9c852f 354 channels = &priv->channels;
f62b8bb8
AV		 355 mutex_unlock(&priv->state_lock);
356
9218b44d
GP		 357 for (i = 0; i < NUM_SW_COUNTERS; i++)
358 data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw,
359 sw_stats_desc, i);
f62b8bb8 360
593cf338 361 for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++)
9218b44d
GP		 362 data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt,
363 q_stats_desc, i);
364
365 for (i = 0; i < NUM_VPORT_COUNTERS; i++)
366 data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out,
367 vport_stats_desc, i);
593cf338 368
9218b44d
GP		 369 for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++)
370 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters,
371 pport_802_3_stats_desc, i);
372
373 for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++)
374 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters,
375 pport_2863_stats_desc, i);
376
377 for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++)
378 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters,
379 pport_2819_stats_desc, i);
380
5db0a4f6
GP		 381 for (i = 0; i < NUM_PPORT_PHY_STATISTICAL_COUNTERS(priv); i++)
382 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.phy_statistical_counters,
383 pport_phy_statistical_stats_desc, i);
068aef33
GP		 384
385 for (i = 0; i < NUM_PPORT_ETH_EXT_COUNTERS(priv); i++)
386 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.eth_ext_counters,
387 pport_eth_ext_stats_desc, i);
5db0a4f6 388
0f7f3481
GP		 389 for (i = 0; i < NUM_PCIE_PERF_COUNTERS(priv); i++)
390 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
391 pcie_perf_stats_desc, i);
392
efae7f78
EBE		 393 for (i = 0; i < NUM_PCIE_PERF_COUNTERS64(priv); i++)
394 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pcie.pcie_perf_counters,
395 pcie_perf_stats_desc64, i);
396
73e90646
GP		 397 for (i = 0; i < NUM_PCIE_PERF_STALL_COUNTERS(priv); i++)
398 data[idx++] = MLX5E_READ_CTR32_BE(&priv->stats.pcie.pcie_perf_counters,
399 pcie_perf_stall_stats_desc, i);
400
cf678570
GP		 401 for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
402 for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++)
403 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
404 pport_per_prio_traffic_stats_desc, i);
405 }
406
407 pfc_combined = mlx5e_query_pfc_combined(priv);
408 for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) {
409 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
410 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio],
411 pport_per_prio_pfc_stats_desc, i);
412 }
413 }
414
e989d5a5
GP		 415 if (mlx5e_query_global_pause_combined(priv)) {
416 for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) {
417 data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[0],
4e39883d 418 pport_per_prio_pfc_stats_desc, i);
e989d5a5
GP		 419 }
420 }
421
bedb7c90
HN		 422 /* port module event counters */
423 mlx5_priv = &priv->mdev->priv;
424 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_status_desc); i++)
425 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.status_counters,
426 mlx5e_pme_status_desc, i);
427
428 for (i = 0; i < ARRAY_SIZE(mlx5e_pme_error_desc); i++)
429 data[idx++] = MLX5E_READ_CTR64_CPU(mlx5_priv->pme_stats.error_counters,
430 mlx5e_pme_error_desc, i);
431
164f16f7
IT		 432 /* IPSec counters */
433 idx += mlx5e_ipsec_get_stats(priv, data + idx);
434
9218b44d
GP		 435 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
436 return;
efea389d 437
f62b8bb8 438 /* per channel counters */
ff9c852f 439 for (i = 0; i < channels->num; i++)
f62b8bb8 440 for (j = 0; j < NUM_RQ_STATS; j++)
9218b44d 441 data[idx++] =
ff9c852f 442 MLX5E_READ_CTR64_CPU(&channels->c[i]->rq.stats,
9218b44d 443 rq_stats_desc, j);
f62b8bb8 444
6a9764ef 445 for (tc = 0; tc < priv->channels.params.num_tc; tc++)
ff9c852f 446 for (i = 0; i < channels->num; i++)
f62b8bb8 447 for (j = 0; j < NUM_SQ_STATS; j++)
ff9c852f 448 data[idx++] = MLX5E_READ_CTR64_CPU(&channels->c[i]->sq[tc].stats,
9218b44d 449 sq_stats_desc, j);
f62b8bb8
AV		 450}
451
076b0936
ES		 452static void mlx5e_get_ethtool_stats(struct net_device *dev,
453 struct ethtool_stats *stats,
454 u64 *data)
455{
456 struct mlx5e_priv *priv = netdev_priv(dev);
457
458 mlx5e_ethtool_get_ethtool_stats(priv, stats, data);
459}
460
cc8e9ebf
EBE		 461static u32 mlx5e_rx_wqes_to_packets(struct mlx5e_priv *priv, int rq_wq_type,
462 int num_wqe)
463{
464 int packets_per_wqe;
465 int stride_size;
466 int num_strides;
467 int wqe_size;
468
469 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
470 return num_wqe;
471
6a9764ef
SM		 472 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
473 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 474 wqe_size = stride_size * num_strides;
475
476 packets_per_wqe = wqe_size /
477 ALIGN(ETH_DATA_LEN, stride_size);
478 return (1 << (order_base_2(num_wqe * packets_per_wqe) - 1));
479}
480
481static u32 mlx5e_packets_to_rx_wqes(struct mlx5e_priv *priv, int rq_wq_type,
482 int num_packets)
483{
484 int packets_per_wqe;
485 int stride_size;
486 int num_strides;
487 int wqe_size;
488 int num_wqes;
489
490 if (rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
491 return num_packets;
492
6a9764ef
SM		 493 stride_size = 1 << priv->channels.params.mpwqe_log_stride_sz;
494 num_strides = 1 << priv->channels.params.mpwqe_log_num_strides;
cc8e9ebf
EBE		 495 wqe_size = stride_size * num_strides;
496
497 num_packets = (1 << order_base_2(num_packets));
498
499 packets_per_wqe = wqe_size /
500 ALIGN(ETH_DATA_LEN, stride_size);
501 num_wqes = DIV_ROUND_UP(num_packets, packets_per_wqe);
502 return 1 << (order_base_2(num_wqes));
503}
504
076b0936
ES		 505void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv,
506 struct ethtool_ringparam *param)
f62b8bb8 507{
6a9764ef 508 int rq_wq_type = priv->channels.params.rq_wq_type;
f62b8bb8 509
cc8e9ebf
EBE		 510 param->rx_max_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
511 1 << mlx5_max_log_rq_size(rq_wq_type));
f62b8bb8 512 param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
cc8e9ebf 513 param->rx_pending = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
6a9764ef
SM		 514 1 << priv->channels.params.log_rq_size);
515 param->tx_pending = 1 << priv->channels.params.log_sq_size;
f62b8bb8
AV		 516}
517
076b0936
ES		 518static void mlx5e_get_ringparam(struct net_device *dev,
519 struct ethtool_ringparam *param)
f62b8bb8
AV		 520{
521 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 522
523 mlx5e_ethtool_get_ringparam(priv, param);
524}
525
526int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv,
527 struct ethtool_ringparam *param)
528{
6a9764ef 529 int rq_wq_type = priv->channels.params.rq_wq_type;
546f18ed 530 struct mlx5e_channels new_channels = {};
cc8e9ebf
EBE		 531 u32 rx_pending_wqes;
532 u32 min_rq_size;
533 u32 max_rq_size;
f62b8bb8
AV		 534 u8 log_rq_size;
535 u8 log_sq_size;
fe4c988b 536 u32 num_mtts;
f62b8bb8
AV		 537 int err = 0;
538
539 if (param->rx_jumbo_pending) {
076b0936 540 netdev_info(priv->netdev, "%s: rx_jumbo_pending not supported\n",
f62b8bb8
AV		 541 __func__);
542 return -EINVAL;
543 }
544 if (param->rx_mini_pending) {
076b0936 545 netdev_info(priv->netdev, "%s: rx_mini_pending not supported\n",
f62b8bb8
AV		 546 __func__);
547 return -EINVAL;
548 }
cc8e9ebf
EBE		 549
550 min_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
551 1 << mlx5_min_log_rq_size(rq_wq_type));
552 max_rq_size = mlx5e_rx_wqes_to_packets(priv, rq_wq_type,
553 1 << mlx5_max_log_rq_size(rq_wq_type));
554 rx_pending_wqes = mlx5e_packets_to_rx_wqes(priv, rq_wq_type,
555 param->rx_pending);
556
557 if (param->rx_pending < min_rq_size) {
076b0936 558 netdev_info(priv->netdev, "%s: rx_pending (%d) < min (%d)\n",
f62b8bb8 559 __func__, param->rx_pending,
cc8e9ebf 560 min_rq_size);
f62b8bb8
AV		 561 return -EINVAL;
562 }
cc8e9ebf 563 if (param->rx_pending > max_rq_size) {
076b0936 564 netdev_info(priv->netdev, "%s: rx_pending (%d) > max (%d)\n",
f62b8bb8 565 __func__, param->rx_pending,
cc8e9ebf 566 max_rq_size);
f62b8bb8
AV		 567 return -EINVAL;
568 }
fe4c988b 569
ec8b9981 570 num_mtts = MLX5E_REQUIRED_MTTS(rx_pending_wqes);
6a9764ef 571 if (priv->channels.params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
fe4c988b 572 !MLX5E_VALID_NUM_MTTS(num_mtts)) {
076b0936 573 netdev_info(priv->netdev, "%s: rx_pending (%d) request can't be satisfied, try to reduce.\n",
fe4c988b
SM		 574 __func__, param->rx_pending);
575 return -EINVAL;
576 }
577
f62b8bb8 578 if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
076b0936 579 netdev_info(priv->netdev, "%s: tx_pending (%d) < min (%d)\n",
f62b8bb8
AV		 580 __func__, param->tx_pending,
581 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
582 return -EINVAL;
583 }
584 if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) {
076b0936 585 netdev_info(priv->netdev, "%s: tx_pending (%d) > max (%d)\n",
f62b8bb8
AV		 586 __func__, param->tx_pending,
587 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE);
588 return -EINVAL;
589 }
590
cc8e9ebf 591 log_rq_size = order_base_2(rx_pending_wqes);
f62b8bb8 592 log_sq_size = order_base_2(param->tx_pending);
f62b8bb8 593
6a9764ef
SM		 594 if (log_rq_size == priv->channels.params.log_rq_size &&
595 log_sq_size == priv->channels.params.log_sq_size)
f62b8bb8
AV		 596 return 0;
597
598 mutex_lock(&priv->state_lock);
98e81b0a 599
546f18ed
SM		 600 new_channels.params = priv->channels.params;
601 new_channels.params.log_rq_size = log_rq_size;
602 new_channels.params.log_sq_size = log_sq_size;
98e81b0a 603
546f18ed
SM		 604 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
605 priv->channels.params = new_channels.params;
606 goto unlock;
607 }
98e81b0a 608
546f18ed
SM		 609 err = mlx5e_open_channels(priv, &new_channels);
610 if (err)
611 goto unlock;
612
2e20a151 613 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 614
546f18ed 615unlock:
f62b8bb8
AV		 616 mutex_unlock(&priv->state_lock);
617
618 return err;
619}
620
076b0936
ES		 621static int mlx5e_set_ringparam(struct net_device *dev,
622 struct ethtool_ringparam *param)
f62b8bb8
AV		 623{
624 struct mlx5e_priv *priv = netdev_priv(dev);
f62b8bb8 625
076b0936
ES		 626 return mlx5e_ethtool_set_ringparam(priv, param);
627}
628
629void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv,
630 struct ethtool_channels *ch)
631{
b4e029da 632 ch->max_combined = priv->profile->max_nch(priv->mdev);
6a9764ef 633 ch->combined_count = priv->channels.params.num_channels;
f62b8bb8
AV		 634}
635
076b0936
ES		 636static void mlx5e_get_channels(struct net_device *dev,
637 struct ethtool_channels *ch)
f62b8bb8
AV		 638{
639 struct mlx5e_priv *priv = netdev_priv(dev);
076b0936
ES		 640
641 mlx5e_ethtool_get_channels(priv, ch);
642}
643
644int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv,
645 struct ethtool_channels *ch)
646{
f62b8bb8 647 unsigned int count = ch->combined_count;
55c2503d 648 struct mlx5e_channels new_channels = {};
45bf454a 649 bool arfs_enabled;
f62b8bb8
AV		 650 int err = 0;
651
652 if (!count) {
076b0936 653 netdev_info(priv->netdev, "%s: combined_count=0 not supported\n",
f62b8bb8
AV		 654 __func__);
655 return -EINVAL;
656 }
f62b8bb8 657
6a9764ef 658 if (priv->channels.params.num_channels == count)
f62b8bb8
AV		 659 return 0;
660
661 mutex_lock(&priv->state_lock);
98e81b0a 662
55c2503d
SM		 663 new_channels.params = priv->channels.params;
664 new_channels.params.num_channels = count;
5a8e1267 665 if (!netif_is_rxfh_configured(priv->netdev))
d4b6c488 666 mlx5e_build_default_indir_rqt(new_channels.params.indirection_rqt,
5a8e1267 667 MLX5E_INDIR_RQT_SIZE, count);
55c2503d
SM		 668
669 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
670 priv->channels.params = new_channels.params;
671 goto out;
672 }
673
674 /* Create fresh channels with new parameters */
675 err = mlx5e_open_channels(priv, &new_channels);
676 if (err)
677 goto out;
98e81b0a 678
076b0936 679 arfs_enabled = priv->netdev->features & NETIF_F_NTUPLE;
45bf454a
MG		 680 if (arfs_enabled)
681 mlx5e_arfs_disable(priv);
682
55c2503d 683 /* Switch to new channels, set new parameters and close old ones */
2e20a151 684 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
45bf454a
MG		 685
686 if (arfs_enabled) {
687 err = mlx5e_arfs_enable(priv);
688 if (err)
076b0936 689 netdev_err(priv->netdev, "%s: mlx5e_arfs_enable failed: %d\n",
45bf454a
MG		 690 __func__, err);
691 }
98e81b0a 692
45bf454a 693out:
f62b8bb8
AV		 694 mutex_unlock(&priv->state_lock);
695
696 return err;
697}
698
076b0936
ES		 699static int mlx5e_set_channels(struct net_device *dev,
700 struct ethtool_channels *ch)
f62b8bb8 701{
076b0936
ES		 702 struct mlx5e_priv *priv = netdev_priv(dev);
703
704 return mlx5e_ethtool_set_channels(priv, ch);
705}
f62b8bb8 706
076b0936
ES		 707int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv,
708 struct ethtool_coalesce *coal)
709{
7524a5d8 710 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation))
9eb78923 711 return -EOPNOTSUPP;
7524a5d8 712
6a9764ef
SM		 713 coal->rx_coalesce_usecs = priv->channels.params.rx_cq_moderation.usec;
714 coal->rx_max_coalesced_frames = priv->channels.params.rx_cq_moderation.pkts;
715 coal->tx_coalesce_usecs = priv->channels.params.tx_cq_moderation.usec;
716 coal->tx_max_coalesced_frames = priv->channels.params.tx_cq_moderation.pkts;
717 coal->use_adaptive_rx_coalesce = priv->channels.params.rx_am_enabled;
f62b8bb8
AV		 718
719 return 0;
720}
721
076b0936
ES		 722static int mlx5e_get_coalesce(struct net_device *netdev,
723 struct ethtool_coalesce *coal)
724{
725 struct mlx5e_priv *priv = netdev_priv(netdev);
726
727 return mlx5e_ethtool_get_coalesce(priv, coal);
728}
729
546f18ed
SM		 730static void
731mlx5e_set_priv_channels_coalesce(struct mlx5e_priv *priv, struct ethtool_coalesce *coal)
f62b8bb8 732{
f62b8bb8 733 struct mlx5_core_dev *mdev = priv->mdev;
f62b8bb8
AV		 734 int tc;
735 int i;
736
ff9c852f
SM		 737 for (i = 0; i < priv->channels.num; ++i) {
738 struct mlx5e_channel *c = priv->channels.c[i];
f62b8bb8
AV		 739
740 for (tc = 0; tc < c->num_tc; tc++) {
741 mlx5_core_modify_cq_moderation(mdev,
742 &c->sq[tc].cq.mcq,
743 coal->tx_coalesce_usecs,
744 coal->tx_max_coalesced_frames);
745 }
746
747 mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq,
748 coal->rx_coalesce_usecs,
749 coal->rx_max_coalesced_frames);
750 }
546f18ed 751}
f62b8bb8 752
076b0936
ES		 753int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv,
754 struct ethtool_coalesce *coal)
546f18ed 755{
546f18ed
SM		 756 struct mlx5_core_dev *mdev = priv->mdev;
757 struct mlx5e_channels new_channels = {};
758 int err = 0;
759 bool reset;
cb3c7fd4 760
546f18ed
SM		 761 if (!MLX5_CAP_GEN(mdev, cq_moderation))
762 return -EOPNOTSUPP;
763
764 mutex_lock(&priv->state_lock);
765 new_channels.params = priv->channels.params;
766
767 new_channels.params.tx_cq_moderation.usec = coal->tx_coalesce_usecs;
768 new_channels.params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames;
769 new_channels.params.rx_cq_moderation.usec = coal->rx_coalesce_usecs;
770 new_channels.params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames;
771 new_channels.params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce;
772
773 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
774 priv->channels.params = new_channels.params;
775 goto out;
776 }
777 /* we are opened */
778
779 reset = !!coal->use_adaptive_rx_coalesce != priv->channels.params.rx_am_enabled;
780 if (!reset) {
781 mlx5e_set_priv_channels_coalesce(priv, coal);
782 priv->channels.params = new_channels.params;
783 goto out;
784 }
785
786 /* open fresh channels with new coal parameters */
787 err = mlx5e_open_channels(priv, &new_channels);
788 if (err)
789 goto out;
790
2e20a151 791 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
546f18ed
SM		 792
793out:
2fcb92fb 794 mutex_unlock(&priv->state_lock);
cb3c7fd4 795 return err;
f62b8bb8
AV		 796}
797
076b0936
ES		 798static int mlx5e_set_coalesce(struct net_device *netdev,
799 struct ethtool_coalesce *coal)
800{
801 struct mlx5e_priv *priv = netdev_priv(netdev);
802
803 return mlx5e_ethtool_set_coalesce(priv, coal);
804}
805
665bc539
GP		 806static void ptys2ethtool_supported_link(unsigned long *supported_modes,
807 u32 eth_proto_cap)
f62b8bb8 808{
7abc2110 809 unsigned long proto_cap = eth_proto_cap;
665bc539 810 int proto;
f62b8bb8 811
7abc2110 812 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 813 bitmap_or(supported_modes, supported_modes,
814 ptys2ethtool_table[proto].supported,
815 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 816}
817
665bc539
GP		 818static void ptys2ethtool_adver_link(unsigned long *advertising_modes,
819 u32 eth_proto_cap)
f62b8bb8 820{
7abc2110 821 unsigned long proto_cap = eth_proto_cap;
665bc539 822 int proto;
f62b8bb8 823
7abc2110 824 for_each_set_bit(proto, &proto_cap, MLX5E_LINK_MODES_NUMBER)
665bc539
GP		 825 bitmap_or(advertising_modes, advertising_modes,
826 ptys2ethtool_table[proto].advertised,
827 __ETHTOOL_LINK_MODE_MASK_NBITS);
f62b8bb8
AV		 828}
829
46e9d0b6
EBE		 830static void ptys2ethtool_supported_advertised_port(struct ethtool_link_ksettings *link_ksettings,
831 u32 eth_proto_cap,
832 u8 connector_type)
f62b8bb8 833{
46e9d0b6
EBE		 834 if (!connector_type || connector_type >= MLX5E_CONNECTOR_TYPE_NUMBER) {
835 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR)
836 | MLX5E_PROT_MASK(MLX5E_10GBASE_SR)
837 | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4)
838 | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4)
839 | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4)
840 | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
841 ethtool_link_ksettings_add_link_mode(link_ksettings,
842 supported,
843 FIBRE);
844 ethtool_link_ksettings_add_link_mode(link_ksettings,
845 advertising,
846 FIBRE);
847 }
848
849 if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4)
850 | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4)
851 | MLX5E_PROT_MASK(MLX5E_10GBASE_KR)
852 | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4)
853 | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) {
854 ethtool_link_ksettings_add_link_mode(link_ksettings,
855 supported,
856 Backplane);
857 ethtool_link_ksettings_add_link_mode(link_ksettings,
858 advertising,
859 Backplane);
860 }
861 return;
f62b8bb8
AV		 862 }
863
46e9d0b6
EBE		 864 switch (connector_type) {
865 case MLX5E_PORT_TP:
866 ethtool_link_ksettings_add_link_mode(link_ksettings,
867 supported, TP);
868 ethtool_link_ksettings_add_link_mode(link_ksettings,
869 advertising, TP);
870 break;
871 case MLX5E_PORT_AUI:
872 ethtool_link_ksettings_add_link_mode(link_ksettings,
873 supported, AUI);
874 ethtool_link_ksettings_add_link_mode(link_ksettings,
875 advertising, AUI);
876 break;
877 case MLX5E_PORT_BNC:
878 ethtool_link_ksettings_add_link_mode(link_ksettings,
879 supported, BNC);
880 ethtool_link_ksettings_add_link_mode(link_ksettings,
881 advertising, BNC);
882 break;
883 case MLX5E_PORT_MII:
884 ethtool_link_ksettings_add_link_mode(link_ksettings,
885 supported, MII);
886 ethtool_link_ksettings_add_link_mode(link_ksettings,
887 advertising, MII);
888 break;
889 case MLX5E_PORT_FIBRE:
890 ethtool_link_ksettings_add_link_mode(link_ksettings,
891 supported, FIBRE);
892 ethtool_link_ksettings_add_link_mode(link_ksettings,
893 advertising, FIBRE);
894 break;
895 case MLX5E_PORT_DA:
896 ethtool_link_ksettings_add_link_mode(link_ksettings,
897 supported, Backplane);
898 ethtool_link_ksettings_add_link_mode(link_ksettings,
899 advertising, Backplane);
900 break;
901 case MLX5E_PORT_NONE:
902 case MLX5E_PORT_OTHER:
903 default:
904 break;
f62b8bb8 905 }
f62b8bb8
AV		 906}
907
b797a684
SM		 908int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed)
909{
910 u32 max_speed = 0;
911 u32 proto_cap;
912 int err;
913 int i;
914
915 err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN);
916 if (err)
917 return err;
918
919 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i)
920 if (proto_cap & MLX5E_PROT_MASK(i))
921 max_speed = max(max_speed, ptys2ethtool_table[i].speed);
922
923 *speed = max_speed;
924 return 0;
925}
926
f62b8bb8
AV		 927static void get_speed_duplex(struct net_device *netdev,
928 u32 eth_proto_oper,
665bc539 929 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 930{
931 int i;
932 u32 speed = SPEED_UNKNOWN;
933 u8 duplex = DUPLEX_UNKNOWN;
934
935 if (!netif_carrier_ok(netdev))
936 goto out;
937
938 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
939 if (eth_proto_oper & MLX5E_PROT_MASK(i)) {
940 speed = ptys2ethtool_table[i].speed;
941 duplex = DUPLEX_FULL;
942 break;
943 }
944 }
945out:
665bc539
GP		 946 link_ksettings->base.speed = speed;
947 link_ksettings->base.duplex = duplex;
f62b8bb8
AV		 948}
949
665bc539
GP		 950static void get_supported(u32 eth_proto_cap,
951 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 952{
665bc539
GP		 953 unsigned long *supported = link_ksettings->link_modes.supported;
954
665bc539
GP		 955 ptys2ethtool_supported_link(supported, eth_proto_cap);
956 ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause);
f62b8bb8
AV		 957}
958
959static void get_advertising(u32 eth_proto_cap, u8 tx_pause,
665bc539
GP		 960 u8 rx_pause,
961 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 962{
665bc539
GP		 963 unsigned long *advertising = link_ksettings->link_modes.advertising;
964
965 ptys2ethtool_adver_link(advertising, eth_proto_cap);
e3c19503 966 if (rx_pause)
665bc539
GP		 967 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause);
968 if (tx_pause ^ rx_pause)
969 ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause);
f62b8bb8
AV		 970}
971
5b4793f8
EBE		 972static int ptys2connector_type[MLX5E_CONNECTOR_TYPE_NUMBER] = {
973 [MLX5E_PORT_UNKNOWN] = PORT_OTHER,
974 [MLX5E_PORT_NONE] = PORT_NONE,
975 [MLX5E_PORT_TP] = PORT_TP,
976 [MLX5E_PORT_AUI] = PORT_AUI,
977 [MLX5E_PORT_BNC] = PORT_BNC,
978 [MLX5E_PORT_MII] = PORT_MII,
979 [MLX5E_PORT_FIBRE] = PORT_FIBRE,
980 [MLX5E_PORT_DA] = PORT_DA,
981 [MLX5E_PORT_OTHER] = PORT_OTHER,
982 };
983
984static u8 get_connector_port(u32 eth_proto, u8 connector_type)
f62b8bb8 985{
5b4793f8
EBE		 986 if (connector_type && connector_type < MLX5E_CONNECTOR_TYPE_NUMBER)
987 return ptys2connector_type[connector_type];
988
61bf2125
OG		 989 if (eth_proto &
990 (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) |
991 MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) |
992 MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) |
993 MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) {
994 return PORT_FIBRE;
f62b8bb8
AV		 995 }
996
61bf2125
OG		 997 if (eth_proto &
998 (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) |
999 MLX5E_PROT_MASK(MLX5E_10GBASE_CR) |
1000 MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) {
1001 return PORT_DA;
f62b8bb8
AV		 1002 }
1003
61bf2125
OG		 1004 if (eth_proto &
1005 (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) |
1006 MLX5E_PROT_MASK(MLX5E_10GBASE_KR) |
1007 MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) |
1008 MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) {
1009 return PORT_NONE;
f62b8bb8
AV		 1010 }
1011
1012 return PORT_OTHER;
1013}
1014
665bc539
GP		 1015static void get_lp_advertising(u32 eth_proto_lp,
1016 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8 1017{
665bc539
GP		 1018 unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising;
1019
1020 ptys2ethtool_adver_link(lp_advertising, eth_proto_lp);
f62b8bb8
AV		 1021}
1022
665bc539
GP		 1023static int mlx5e_get_link_ksettings(struct net_device *netdev,
1024 struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 1025{
1026 struct mlx5e_priv *priv = netdev_priv(netdev);
1027 struct mlx5_core_dev *mdev = priv->mdev;
c4f287c4 1028 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
b383b544
GP		 1029 u32 rx_pause = 0;
1030 u32 tx_pause = 0;
f62b8bb8
AV		 1031 u32 eth_proto_cap;
1032 u32 eth_proto_admin;
1033 u32 eth_proto_lp;
1034 u32 eth_proto_oper;
52244d96
GP		 1035 u8 an_disable_admin;
1036 u8 an_status;
5b4793f8 1037 u8 connector_type;
f62b8bb8
AV		 1038 int err;
1039
a05bdefa 1040 err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
f62b8bb8
AV		 1041 if (err) {
1042 netdev_err(netdev, "%s: query port ptys failed: %d\n",
1043 __func__, err);
1044 goto err_query_ptys;
1045 }
1046
52244d96
GP		 1047 eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
1048 eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
1049 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
1050 eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise);
1051 an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin);
1052 an_status = MLX5_GET(ptys_reg, out, an_status);
5b4793f8 1053 connector_type = MLX5_GET(ptys_reg, out, connector_type);
f62b8bb8 1054
b383b544
GP		 1055 mlx5_query_port_pause(mdev, &rx_pause, &tx_pause);
1056
665bc539
GP		 1057 ethtool_link_ksettings_zero_link_mode(link_ksettings, supported);
1058 ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising);
f62b8bb8 1059
665bc539 1060 get_supported(eth_proto_cap, link_ksettings);
b383b544 1061 get_advertising(eth_proto_admin, tx_pause, rx_pause, link_ksettings);
665bc539 1062 get_speed_duplex(netdev, eth_proto_oper, link_ksettings);
f62b8bb8
AV		 1063
1064 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1065
5b4793f8
EBE		 1066 link_ksettings->base.port = get_connector_port(eth_proto_oper,
1067 connector_type);
46e9d0b6
EBE		 1068 ptys2ethtool_supported_advertised_port(link_ksettings, eth_proto_admin,
1069 connector_type);
665bc539 1070 get_lp_advertising(eth_proto_lp, link_ksettings);
f62b8bb8 1071
52244d96
GP		 1072 if (an_status == MLX5_AN_COMPLETE)
1073 ethtool_link_ksettings_add_link_mode(link_ksettings,
1074 lp_advertising, Autoneg);
1075
1076 link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE :
1077 AUTONEG_ENABLE;
1078 ethtool_link_ksettings_add_link_mode(link_ksettings, supported,
1079 Autoneg);
1080 if (!an_disable_admin)
1081 ethtool_link_ksettings_add_link_mode(link_ksettings,
1082 advertising, Autoneg);
1083
f62b8bb8
AV		 1084err_query_ptys:
1085 return err;
1086}
1087
665bc539 1088static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes)
f62b8bb8
AV		 1089{
1090 u32 i, ptys_modes = 0;
1091
1092 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
665bc539
GP		 1093 if (bitmap_intersects(ptys2ethtool_table[i].advertised,
1094 link_modes,
1095 __ETHTOOL_LINK_MODE_MASK_NBITS))
f62b8bb8
AV		 1096 ptys_modes |= MLX5E_PROT_MASK(i);
1097 }
1098
1099 return ptys_modes;
1100}
1101
1102static u32 mlx5e_ethtool2ptys_speed_link(u32 speed)
1103{
1104 u32 i, speed_links = 0;
1105
1106 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
1107 if (ptys2ethtool_table[i].speed == speed)
1108 speed_links |= MLX5E_PROT_MASK(i);
1109 }
1110
1111 return speed_links;
1112}
1113
665bc539
GP		 1114static int mlx5e_set_link_ksettings(struct net_device *netdev,
1115 const struct ethtool_link_ksettings *link_ksettings)
f62b8bb8
AV		 1116{
1117 struct mlx5e_priv *priv = netdev_priv(netdev);
1118 struct mlx5_core_dev *mdev = priv->mdev;
52244d96
GP		 1119 u32 eth_proto_cap, eth_proto_admin;
1120 bool an_changes = false;
1121 u8 an_disable_admin;
1122 u8 an_disable_cap;
1123 bool an_disable;
f62b8bb8 1124 u32 link_modes;
52244d96 1125 u8 an_status;
f62b8bb8 1126 u32 speed;
f62b8bb8
AV		 1127 int err;
1128
665bc539 1129 speed = link_ksettings->base.speed;
f62b8bb8 1130
665bc539
GP		 1131 link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ?
1132 mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) :
f62b8bb8
AV		 1133 mlx5e_ethtool2ptys_speed_link(speed);
1134
1135 err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
1136 if (err) {
1137 netdev_err(netdev, "%s: query port eth proto cap failed: %d\n",
1138 __func__, err);
1139 goto out;
1140 }
1141
1142 link_modes = link_modes & eth_proto_cap;
1143 if (!link_modes) {
1144 netdev_err(netdev, "%s: Not supported link mode(s) requested",
1145 __func__);
1146 err = -EINVAL;
1147 goto out;
1148 }
1149
1150 err = mlx5_query_port_proto_admin(mdev, &eth_proto_admin, MLX5_PTYS_EN);
1151 if (err) {
1152 netdev_err(netdev, "%s: query port eth proto admin failed: %d\n",
1153 __func__, err);
1154 goto out;
1155 }
1156
52244d96
GP		 1157 mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status,
1158 &an_disable_cap, &an_disable_admin);
1159
1160 an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE;
1161 an_changes = ((!an_disable && an_disable_admin) ||
1162 (an_disable && !an_disable_admin));
1163
1164 if (!an_changes && link_modes == eth_proto_admin)
f62b8bb8
AV		 1165 goto out;
1166
52244d96 1167 mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN);
667daeda 1168 mlx5_toggle_port_link(mdev);
f62b8bb8 1169
f62b8bb8
AV		 1170out:
1171 return err;
1172}
1173
2d75b2bc
AS		 1174static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev)
1175{
1176 struct mlx5e_priv *priv = netdev_priv(netdev);
1177
6a9764ef 1178 return sizeof(priv->channels.params.toeplitz_hash_key);
2d75b2bc
AS		 1179}
1180
1181static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev)
1182{
1183 return MLX5E_INDIR_RQT_SIZE;
1184}
1185
2be6967c
SM		 1186static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
1187 u8 *hfunc)
1188{
1189 struct mlx5e_priv *priv = netdev_priv(netdev);
1190
2d75b2bc 1191 if (indir)
6a9764ef
SM		 1192 memcpy(indir, priv->channels.params.indirection_rqt,
1193 sizeof(priv->channels.params.indirection_rqt));
2d75b2bc
AS		 1194
1195 if (key)
6a9764ef
SM		 1196 memcpy(key, priv->channels.params.toeplitz_hash_key,
1197 sizeof(priv->channels.params.toeplitz_hash_key));
2d75b2bc 1198
2be6967c 1199 if (hfunc)
6a9764ef 1200 *hfunc = priv->channels.params.rss_hfunc;
2be6967c
SM		 1201
1202 return 0;
1203}
1204
bdfc028d
TT		 1205static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen)
1206{
bdfc028d 1207 void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
a100ff3e
GP		 1208 struct mlx5_core_dev *mdev = priv->mdev;
1209 int ctxlen = MLX5_ST_SZ_BYTES(tirc);
1210 int tt;
bdfc028d
TT		 1211
1212 MLX5_SET(modify_tir_in, in, bitmask.hash, 1);
bdfc028d 1213
a100ff3e
GP		 1214 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1215 memset(tirc, 0, ctxlen);
7b3722fa 1216 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
a100ff3e
GP		 1217 mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in, inlen);
1218 }
7b3722fa
GP		 1219
1220 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
1221 return;
1222
1223 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1224 memset(tirc, 0, ctxlen);
1225 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
1226 mlx5_core_modify_tir(mdev, priv->inner_indir_tir[tt].tirn, in, inlen);
1227 }
bdfc028d
TT		 1228}
1229
98e81b0a 1230static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir,
2be6967c
SM		 1231 const u8 *key, const u8 hfunc)
1232{
98e81b0a 1233 struct mlx5e_priv *priv = netdev_priv(dev);
bdfc028d 1234 int inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1d3398fa 1235 bool hash_changed = false;
bdfc028d 1236 void *in;
2be6967c 1237
2d75b2bc
AS		 1238 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) &&
1239 (hfunc != ETH_RSS_HASH_XOR) &&
2be6967c
SM		 1240 (hfunc != ETH_RSS_HASH_TOP))
1241 return -EINVAL;
1242
1b9a07ee 1243 in = kvzalloc(inlen, GFP_KERNEL);
bdfc028d
TT		 1244 if (!in)
1245 return -ENOMEM;
1246
2be6967c
SM		 1247 mutex_lock(&priv->state_lock);
1248
1d3398fa 1249 if (hfunc != ETH_RSS_HASH_NO_CHANGE &&
6a9764ef
SM		 1250 hfunc != priv->channels.params.rss_hfunc) {
1251 priv->channels.params.rss_hfunc = hfunc;
1d3398fa
GP		 1252 hash_changed = true;
1253 }
1254
a5f97fee 1255 if (indir) {
6a9764ef
SM		 1256 memcpy(priv->channels.params.indirection_rqt, indir,
1257 sizeof(priv->channels.params.indirection_rqt));
a5f97fee
SM		 1258
1259 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1260 u32 rqtn = priv->indir_rqt.rqtn;
1261 struct mlx5e_redirect_rqt_param rrp = {
1262 .is_rss = true,
e270e966
AM		 1263 {
1264 .rss = {
1265 .hfunc = priv->channels.params.rss_hfunc,
1266 .channels = &priv->channels,
1267 },
1268 },
a5f97fee
SM		 1269 };
1270
1271 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
1272 }
1273 }
1274
1d3398fa 1275 if (key) {
6a9764ef
SM		 1276 memcpy(priv->channels.params.toeplitz_hash_key, key,
1277 sizeof(priv->channels.params.toeplitz_hash_key));
1d3398fa 1278 hash_changed = hash_changed ||
6a9764ef 1279 priv->channels.params.rss_hfunc == ETH_RSS_HASH_TOP;
1d3398fa 1280 }
2d75b2bc 1281
1d3398fa
GP		 1282 if (hash_changed)
1283 mlx5e_modify_tirs_hash(priv, in, inlen);
2d75b2bc 1284
2be6967c
SM		 1285 mutex_unlock(&priv->state_lock);
1286
bdfc028d
TT		 1287 kvfree(in);
1288
1289 return 0;
2be6967c
SM		 1290}
1291
2d75b2bc
AS		 1292static int mlx5e_get_rxnfc(struct net_device *netdev,
1293 struct ethtool_rxnfc *info, u32 *rule_locs)
1294{
1295 struct mlx5e_priv *priv = netdev_priv(netdev);
1296 int err = 0;
1297
1298 switch (info->cmd) {
1299 case ETHTOOL_GRXRINGS:
6a9764ef 1300 info->data = priv->channels.params.num_channels;
2d75b2bc 1301 break;
f913a72a
MG		 1302 case ETHTOOL_GRXCLSRLCNT:
1303 info->rule_cnt = priv->fs.ethtool.tot_num_rules;
1304 break;
1305 case ETHTOOL_GRXCLSRULE:
1306 err = mlx5e_ethtool_get_flow(priv, info, info->fs.location);
1307 break;
1308 case ETHTOOL_GRXCLSRLALL:
1309 err = mlx5e_ethtool_get_all_flows(priv, info, rule_locs);
1310 break;
2d75b2bc
AS		 1311 default:
1312 err = -EOPNOTSUPP;
1313 break;
1314 }
1315
1316 return err;
1317}
1318
58d52291
AS		 1319static int mlx5e_get_tunable(struct net_device *dev,
1320 const struct ethtool_tunable *tuna,
1321 void *data)
1322{
1323 const struct mlx5e_priv *priv = netdev_priv(dev);
1324 int err = 0;
1325
1326 switch (tuna->id) {
1327 case ETHTOOL_TX_COPYBREAK:
6a9764ef 1328 *(u32 *)data = priv->channels.params.tx_max_inline;
58d52291
AS		 1329 break;
1330 default:
1331 err = -EINVAL;
1332 break;
1333 }
1334
1335 return err;
1336}
1337
1338static int mlx5e_set_tunable(struct net_device *dev,
1339 const struct ethtool_tunable *tuna,
1340 const void *data)
1341{
1342 struct mlx5e_priv *priv = netdev_priv(dev);
1343 struct mlx5_core_dev *mdev = priv->mdev;
546f18ed 1344 struct mlx5e_channels new_channels = {};
58d52291 1345 int err = 0;
546f18ed
SM		 1346 u32 val;
1347
1348 mutex_lock(&priv->state_lock);
58d52291
AS		 1349
1350 switch (tuna->id) {
1351 case ETHTOOL_TX_COPYBREAK:
1352 val = *(u32 *)data;
1353 if (val > mlx5e_get_max_inline_cap(mdev)) {
1354 err = -EINVAL;
1355 break;
1356 }
1357
546f18ed
SM		 1358 new_channels.params = priv->channels.params;
1359 new_channels.params.tx_max_inline = val;
98e81b0a 1360
546f18ed
SM		 1361 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1362 priv->channels.params = new_channels.params;
1363 break;
1364 }
98e81b0a 1365
546f18ed
SM		 1366 err = mlx5e_open_channels(priv, &new_channels);
1367 if (err)
1368 break;
2e20a151 1369 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
98e81b0a 1370
58d52291
AS		 1371 break;
1372 default:
1373 err = -EINVAL;
1374 break;
1375 }
1376
546f18ed 1377 mutex_unlock(&priv->state_lock);
58d52291
AS		 1378 return err;
1379}
1380
3c2d18ef
AS		 1381static void mlx5e_get_pauseparam(struct net_device *netdev,
1382 struct ethtool_pauseparam *pauseparam)
1383{
1384 struct mlx5e_priv *priv = netdev_priv(netdev);
1385 struct mlx5_core_dev *mdev = priv->mdev;
1386 int err;
1387
1388 err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause,
1389 &pauseparam->tx_pause);
1390 if (err) {
1391 netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n",
1392 __func__, err);
1393 }
1394}
1395
1396static int mlx5e_set_pauseparam(struct net_device *netdev,
1397 struct ethtool_pauseparam *pauseparam)
1398{
1399 struct mlx5e_priv *priv = netdev_priv(netdev);
1400 struct mlx5_core_dev *mdev = priv->mdev;
1401 int err;
1402
1403 if (pauseparam->autoneg)
1404 return -EINVAL;
1405
1406 err = mlx5_set_port_pause(mdev,
1407 pauseparam->rx_pause ? 1 : 0,
1408 pauseparam->tx_pause ? 1 : 0);
1409 if (err) {
1410 netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n",
1411 __func__, err);
1412 }
1413
1414 return err;
1415}
1416
3844b07e
FD		 1417int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv,
1418 struct ethtool_ts_info *info)
ef9814de 1419{
7c39afb3 1420 struct mlx5_core_dev *mdev = priv->mdev;
ef9814de
EBE		 1421 int ret;
1422
3844b07e 1423 ret = ethtool_op_get_ts_info(priv->netdev, info);
ef9814de
EBE		 1424 if (ret)
1425 return ret;
1426
7c39afb3
FD		 1427 info->phc_index = mdev->clock.ptp ?
1428 ptp_clock_index(mdev->clock.ptp) : -1;
ef9814de
EBE		 1429
1430 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
1431 return 0;
1432
1433 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
1434 SOF_TIMESTAMPING_RX_HARDWARE |
1435 SOF_TIMESTAMPING_RAW_HARDWARE;
1436
f0b38117
MD		 1437 info->tx_types = BIT(HWTSTAMP_TX_OFF) |
1438 BIT(HWTSTAMP_TX_ON);
ef9814de 1439
f0b38117
MD		 1440 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
1441 BIT(HWTSTAMP_FILTER_ALL);
ef9814de
EBE		 1442
1443 return 0;
1444}
1445
3844b07e
FD		 1446static int mlx5e_get_ts_info(struct net_device *dev,
1447 struct ethtool_ts_info *info)
1448{
1449 struct mlx5e_priv *priv = netdev_priv(dev);
1450
1451 return mlx5e_ethtool_get_ts_info(priv, info);
1452}
1453
928cfe87
TT		 1454static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev)
1455{
1456 __u32 ret = 0;
1457
1458 if (MLX5_CAP_GEN(mdev, wol_g))
1459 ret |= WAKE_MAGIC;
1460
1461 if (MLX5_CAP_GEN(mdev, wol_s))
1462 ret |= WAKE_MAGICSECURE;
1463
1464 if (MLX5_CAP_GEN(mdev, wol_a))
1465 ret |= WAKE_ARP;
1466
1467 if (MLX5_CAP_GEN(mdev, wol_b))
1468 ret |= WAKE_BCAST;
1469
1470 if (MLX5_CAP_GEN(mdev, wol_m))
1471 ret |= WAKE_MCAST;
1472
1473 if (MLX5_CAP_GEN(mdev, wol_u))
1474 ret |= WAKE_UCAST;
1475
1476 if (MLX5_CAP_GEN(mdev, wol_p))
1477 ret |= WAKE_PHY;
1478
1479 return ret;
1480}
1481
1482static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode)
1483{
1484 __u32 ret = 0;
1485
1486 if (mode & MLX5_WOL_MAGIC)
1487 ret |= WAKE_MAGIC;
1488
1489 if (mode & MLX5_WOL_SECURED_MAGIC)
1490 ret |= WAKE_MAGICSECURE;
1491
1492 if (mode & MLX5_WOL_ARP)
1493 ret |= WAKE_ARP;
1494
1495 if (mode & MLX5_WOL_BROADCAST)
1496 ret |= WAKE_BCAST;
1497
1498 if (mode & MLX5_WOL_MULTICAST)
1499 ret |= WAKE_MCAST;
1500
1501 if (mode & MLX5_WOL_UNICAST)
1502 ret |= WAKE_UCAST;
1503
1504 if (mode & MLX5_WOL_PHY_ACTIVITY)
1505 ret |= WAKE_PHY;
1506
1507 return ret;
1508}
1509
1510static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode)
1511{
1512 u8 ret = 0;
1513
1514 if (mode & WAKE_MAGIC)
1515 ret |= MLX5_WOL_MAGIC;
1516
1517 if (mode & WAKE_MAGICSECURE)
1518 ret |= MLX5_WOL_SECURED_MAGIC;
1519
1520 if (mode & WAKE_ARP)
1521 ret |= MLX5_WOL_ARP;
1522
1523 if (mode & WAKE_BCAST)
1524 ret |= MLX5_WOL_BROADCAST;
1525
1526 if (mode & WAKE_MCAST)
1527 ret |= MLX5_WOL_MULTICAST;
1528
1529 if (mode & WAKE_UCAST)
1530 ret |= MLX5_WOL_UNICAST;
1531
1532 if (mode & WAKE_PHY)
1533 ret |= MLX5_WOL_PHY_ACTIVITY;
1534
1535 return ret;
1536}
1537
1538static void mlx5e_get_wol(struct net_device *netdev,
1539 struct ethtool_wolinfo *wol)
1540{
1541 struct mlx5e_priv *priv = netdev_priv(netdev);
1542 struct mlx5_core_dev *mdev = priv->mdev;
1543 u8 mlx5_wol_mode;
1544 int err;
1545
1546 memset(wol, 0, sizeof(*wol));
1547
1548 wol->supported = mlx5e_get_wol_supported(mdev);
1549 if (!wol->supported)
1550 return;
1551
1552 err = mlx5_query_port_wol(mdev, &mlx5_wol_mode);
1553 if (err)
1554 return;
1555
1556 wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode);
1557}
1558
1559static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1560{
1561 struct mlx5e_priv *priv = netdev_priv(netdev);
1562 struct mlx5_core_dev *mdev = priv->mdev;
1563 __u32 wol_supported = mlx5e_get_wol_supported(mdev);
1564 u32 mlx5_wol_mode;
1565
1566 if (!wol_supported)
9eb78923 1567 return -EOPNOTSUPP;
928cfe87
TT		 1568
1569 if (wol->wolopts & ~wol_supported)
1570 return -EINVAL;
1571
1572 mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts);
1573
1574 return mlx5_set_port_wol(mdev, mlx5_wol_mode);
1575}
1576
da54d24e
GP		 1577static int mlx5e_set_phys_id(struct net_device *dev,
1578 enum ethtool_phys_id_state state)
1579{
1580 struct mlx5e_priv *priv = netdev_priv(dev);
1581 struct mlx5_core_dev *mdev = priv->mdev;
1582 u16 beacon_duration;
1583
1584 if (!MLX5_CAP_GEN(mdev, beacon_led))
1585 return -EOPNOTSUPP;
1586
1587 switch (state) {
1588 case ETHTOOL_ID_ACTIVE:
1589 beacon_duration = MLX5_BEACON_DURATION_INF;
1590 break;
1591 case ETHTOOL_ID_INACTIVE:
1592 beacon_duration = MLX5_BEACON_DURATION_OFF;
1593 break;
1594 default:
1595 return -EOPNOTSUPP;
1596 }
1597
1598 return mlx5_set_port_beacon(mdev, beacon_duration);
1599}
1600
bb64143e
GP		 1601static int mlx5e_get_module_info(struct net_device *netdev,
1602 struct ethtool_modinfo *modinfo)
1603{
1604 struct mlx5e_priv *priv = netdev_priv(netdev);
1605 struct mlx5_core_dev *dev = priv->mdev;
1606 int size_read = 0;
1607 u8 data[4];
1608
1609 size_read = mlx5_query_module_eeprom(dev, 0, 2, data);
1610 if (size_read < 2)
1611 return -EIO;
1612
1613 /* data[0] = identifier byte */
1614 switch (data[0]) {
1615 case MLX5_MODULE_ID_QSFP:
1616 modinfo->type = ETH_MODULE_SFF_8436;
1617 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1618 break;
1619 case MLX5_MODULE_ID_QSFP_PLUS:
1620 case MLX5_MODULE_ID_QSFP28:
1621 /* data[1] = revision id */
1622 if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) {
1623 modinfo->type = ETH_MODULE_SFF_8636;
1624 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1625 } else {
1626 modinfo->type = ETH_MODULE_SFF_8436;
1627 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1628 }
1629 break;
1630 case MLX5_MODULE_ID_SFP:
1631 modinfo->type = ETH_MODULE_SFF_8472;
1632 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1633 break;
1634 default:
1635 netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n",
1636 __func__, data[0]);
1637 return -EINVAL;
1638 }
1639
1640 return 0;
1641}
1642
1643static int mlx5e_get_module_eeprom(struct net_device *netdev,
1644 struct ethtool_eeprom *ee,
1645 u8 *data)
1646{
1647 struct mlx5e_priv *priv = netdev_priv(netdev);
1648 struct mlx5_core_dev *mdev = priv->mdev;
1649 int offset = ee->offset;
1650 int size_read;
1651 int i = 0;
1652
1653 if (!ee->len)
1654 return -EINVAL;
1655
1656 memset(data, 0, ee->len);
1657
1658 while (i < ee->len) {
1659 size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i,
1660 data + i);
1661
1662 if (!size_read)
1663 /* Done reading */
1664 return 0;
1665
1666 if (size_read < 0) {
1667 netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n",
1668 __func__, size_read);
1669 return 0;
1670 }
1671
1672 i += size_read;
1673 offset += size_read;
1674 }
1675
1676 return 0;
1677}
1678
4e59e288
GP		 1679typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable);
1680
9908aa29 1681static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable)
4e59e288 1682{
9908aa29
TT		 1683 struct mlx5e_priv *priv = netdev_priv(netdev);
1684 struct mlx5_core_dev *mdev = priv->mdev;
be7e87f9 1685 struct mlx5e_channels new_channels = {};
9908aa29
TT		 1686 bool rx_mode_changed;
1687 u8 rx_cq_period_mode;
1688 int err = 0;
9908aa29
TT		 1689
1690 rx_cq_period_mode = enable ?
1691 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
1692 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
6a9764ef 1693 rx_mode_changed = rx_cq_period_mode != priv->channels.params.rx_cq_period_mode;
9908aa29
TT		 1694
1695 if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE &&
1696 !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe))
9eb78923 1697 return -EOPNOTSUPP;
9908aa29
TT		 1698
1699 if (!rx_mode_changed)
1700 return 0;
1701
be7e87f9
SM		 1702 new_channels.params = priv->channels.params;
1703 mlx5e_set_rx_cq_mode_params(&new_channels.params, rx_cq_period_mode);
9908aa29 1704
be7e87f9
SM		 1705 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1706 priv->channels.params = new_channels.params;
1707 return 0;
1708 }
1709
1710 err = mlx5e_open_channels(priv, &new_channels);
1711 if (err)
1712 return err;
9908aa29 1713
2e20a151 1714 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9
SM		 1715 return 0;
1716}
9908aa29 1717
be7e87f9
SM		 1718int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool new_val)
1719{
1720 bool curr_val = MLX5E_GET_PFLAG(&priv->channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS);
1721 struct mlx5e_channels new_channels = {};
1722 int err = 0;
1723
1724 if (!MLX5_CAP_GEN(priv->mdev, cqe_compression))
1725 return new_val ? -EOPNOTSUPP : 0;
1726
1727 if (curr_val == new_val)
1728 return 0;
1729
1730 new_channels.params = priv->channels.params;
1731 MLX5E_SET_PFLAG(&new_channels.params, MLX5E_PFLAG_RX_CQE_COMPRESS, new_val);
1732
1733 mlx5e_set_rq_type_params(priv->mdev, &new_channels.params,
1734 new_channels.params.rq_wq_type);
1735
1736 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
1737 priv->channels.params = new_channels.params;
1738 return 0;
1739 }
1740
1741 err = mlx5e_open_channels(priv, &new_channels);
1742 if (err)
1743 return err;
1744
2e20a151 1745 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
be7e87f9 1746 return 0;
4e59e288
GP		 1747}
1748
9bcc8606
SD		 1749static int set_pflag_rx_cqe_compress(struct net_device *netdev,
1750 bool enable)
1751{
1752 struct mlx5e_priv *priv = netdev_priv(netdev);
1753 struct mlx5_core_dev *mdev = priv->mdev;
9bcc8606
SD		 1754
1755 if (!MLX5_CAP_GEN(mdev, cqe_compression))
9eb78923 1756 return -EOPNOTSUPP;
9bcc8606 1757
7c39afb3 1758 if (enable && priv->tstamp.rx_filter != HWTSTAMP_FILTER_NONE) {
9bcc8606
SD		 1759 netdev_err(netdev, "Can't enable cqe compression while timestamping is enabled.\n");
1760 return -EINVAL;
1761 }
1762
5eb0249b 1763 mlx5e_modify_rx_cqe_compression_locked(priv, enable);
6a9764ef 1764 priv->channels.params.rx_cqe_compress_def = enable;
9bcc8606 1765
5eb0249b 1766 return 0;
9bcc8606
SD		 1767}
1768
4e59e288
GP		 1769static int mlx5e_handle_pflag(struct net_device *netdev,
1770 u32 wanted_flags,
1771 enum mlx5e_priv_flag flag,
1772 mlx5e_pflag_handler pflag_handler)
1773{
1774 struct mlx5e_priv *priv = netdev_priv(netdev);
1775 bool enable = !!(wanted_flags & flag);
6a9764ef 1776 u32 changes = wanted_flags ^ priv->channels.params.pflags;
4e59e288
GP		 1777 int err;
1778
1779 if (!(changes & flag))
1780 return 0;
1781
1782 err = pflag_handler(netdev, enable);
1783 if (err) {
1784 netdev_err(netdev, "%s private flag 0x%x failed err %d\n",
1785 enable ? "Enable" : "Disable", flag, err);
1786 return err;
1787 }
1788
6a9764ef 1789 MLX5E_SET_PFLAG(&priv->channels.params, flag, enable);
4e59e288
GP		 1790 return 0;
1791}
1792
1793static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags)
1794{
1795 struct mlx5e_priv *priv = netdev_priv(netdev);
1796 int err;
1797
1798 mutex_lock(&priv->state_lock);
9908aa29
TT		 1799 err = mlx5e_handle_pflag(netdev, pflags,
1800 MLX5E_PFLAG_RX_CQE_BASED_MODER,
1801 set_pflag_rx_cqe_based_moder);
9bcc8606
SD		 1802 if (err)
1803 goto out;
4e59e288 1804
9bcc8606
SD		 1805 err = mlx5e_handle_pflag(netdev, pflags,
1806 MLX5E_PFLAG_RX_CQE_COMPRESS,
1807 set_pflag_rx_cqe_compress);
1808
1809out:
4e59e288 1810 mutex_unlock(&priv->state_lock);
9bcc8606 1811 return err;
4e59e288
GP		 1812}
1813
1814static u32 mlx5e_get_priv_flags(struct net_device *netdev)
1815{
1816 struct mlx5e_priv *priv = netdev_priv(netdev);
1817
6a9764ef 1818 return priv->channels.params.pflags;
4e59e288
GP		 1819}
1820
6dc6071c
MG		 1821static int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1822{
1823 int err = 0;
1824 struct mlx5e_priv *priv = netdev_priv(dev);
1825
1826 switch (cmd->cmd) {
1827 case ETHTOOL_SRXCLSRLINS:
1828 err = mlx5e_ethtool_flow_replace(priv, &cmd->fs);
1829 break;
1830 case ETHTOOL_SRXCLSRLDEL:
1831 err = mlx5e_ethtool_flow_remove(priv, cmd->fs.location);
1832 break;
1833 default:
1834 err = -EOPNOTSUPP;
1835 break;
1836 }
1837
1838 return err;
1839}
1840
3ffaabec
OG		 1841int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv,
1842 struct ethtool_flash *flash)
1843{
1844 struct mlx5_core_dev *mdev = priv->mdev;
1845 struct net_device *dev = priv->netdev;
1846 const struct firmware *fw;
1847 int err;
1848
1849 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
1850 return -EOPNOTSUPP;
1851
1852 err = request_firmware_direct(&fw, flash->data, &dev->dev);
1853 if (err)
1854 return err;
1855
1856 dev_hold(dev);
1857 rtnl_unlock();
1858
1859 err = mlx5_firmware_flash(mdev, fw);
1860 release_firmware(fw);
1861
1862 rtnl_lock();
1863 dev_put(dev);
1864 return err;
1865}
1866
1867static int mlx5e_flash_device(struct net_device *dev,
1868 struct ethtool_flash *flash)
1869{
1870 struct mlx5e_priv *priv = netdev_priv(dev);
1871
1872 return mlx5e_ethtool_flash_device(priv, flash);
1873}
1874
f62b8bb8
AV		 1875const struct ethtool_ops mlx5e_ethtool_ops = {
1876 .get_drvinfo = mlx5e_get_drvinfo,
1877 .get_link = ethtool_op_get_link,
1878 .get_strings = mlx5e_get_strings,
1879 .get_sset_count = mlx5e_get_sset_count,
1880 .get_ethtool_stats = mlx5e_get_ethtool_stats,
1881 .get_ringparam = mlx5e_get_ringparam,
1882 .set_ringparam = mlx5e_set_ringparam,
1883 .get_channels = mlx5e_get_channels,
1884 .set_channels = mlx5e_set_channels,
1885 .get_coalesce = mlx5e_get_coalesce,
1886 .set_coalesce = mlx5e_set_coalesce,
665bc539
GP		 1887 .get_link_ksettings = mlx5e_get_link_ksettings,
1888 .set_link_ksettings = mlx5e_set_link_ksettings,
2d75b2bc
AS		 1889 .get_rxfh_key_size = mlx5e_get_rxfh_key_size,
1890 .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size,
2be6967c
SM		 1891 .get_rxfh = mlx5e_get_rxfh,
1892 .set_rxfh = mlx5e_set_rxfh,
2d75b2bc 1893 .get_rxnfc = mlx5e_get_rxnfc,
6dc6071c 1894 .set_rxnfc = mlx5e_set_rxnfc,
3ffaabec 1895 .flash_device = mlx5e_flash_device,
58d52291
AS		 1896 .get_tunable = mlx5e_get_tunable,
1897 .set_tunable = mlx5e_set_tunable,
3c2d18ef
AS		 1898 .get_pauseparam = mlx5e_get_pauseparam,
1899 .set_pauseparam = mlx5e_set_pauseparam,
ef9814de 1900 .get_ts_info = mlx5e_get_ts_info,
da54d24e 1901 .set_phys_id = mlx5e_set_phys_id,
928cfe87
TT		 1902 .get_wol = mlx5e_get_wol,
1903 .set_wol = mlx5e_set_wol,
bb64143e
GP		 1904 .get_module_info = mlx5e_get_module_info,
1905 .get_module_eeprom = mlx5e_get_module_eeprom,
4e59e288 1906 .get_priv_flags = mlx5e_get_priv_flags,
d605d668
KH		 1907 .set_priv_flags = mlx5e_set_priv_flags,
1908 .self_test = mlx5e_self_test,
f62b8bb8 1909};
Linux 6.x block layer and io_uring tree(s)