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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include "en.h" | |
34 | ||
35 | static void mlx5e_get_drvinfo(struct net_device *dev, | |
36 | struct ethtool_drvinfo *drvinfo) | |
37 | { | |
38 | struct mlx5e_priv *priv = netdev_priv(dev); | |
39 | struct mlx5_core_dev *mdev = priv->mdev; | |
40 | ||
41 | strlcpy(drvinfo->driver, DRIVER_NAME, sizeof(drvinfo->driver)); | |
42 | strlcpy(drvinfo->version, DRIVER_VERSION " (" DRIVER_RELDATE ")", | |
43 | sizeof(drvinfo->version)); | |
44 | snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), | |
45 | "%d.%d.%d", | |
46 | fw_rev_maj(mdev), fw_rev_min(mdev), fw_rev_sub(mdev)); | |
47 | strlcpy(drvinfo->bus_info, pci_name(mdev->pdev), | |
48 | sizeof(drvinfo->bus_info)); | |
49 | } | |
50 | ||
665bc539 GP |
51 | struct ptys2ethtool_config { |
52 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); | |
53 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised); | |
f62b8bb8 | 54 | u32 speed; |
f62b8bb8 AV |
55 | }; |
56 | ||
665bc539 GP |
57 | static struct ptys2ethtool_config ptys2ethtool_table[MLX5E_LINK_MODES_NUMBER]; |
58 | ||
59 | #define MLX5_BUILD_PTYS2ETHTOOL_CONFIG(reg_, speed_, ...) \ | |
60 | ({ \ | |
61 | struct ptys2ethtool_config *cfg; \ | |
62 | const unsigned int modes[] = { __VA_ARGS__ }; \ | |
63 | unsigned int i; \ | |
64 | cfg = &ptys2ethtool_table[reg_]; \ | |
65 | cfg->speed = speed_; \ | |
66 | bitmap_zero(cfg->supported, \ | |
67 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
68 | bitmap_zero(cfg->advertised, \ | |
69 | __ETHTOOL_LINK_MODE_MASK_NBITS); \ | |
70 | for (i = 0 ; i < ARRAY_SIZE(modes) ; ++i) { \ | |
71 | __set_bit(modes[i], cfg->supported); \ | |
72 | __set_bit(modes[i], cfg->advertised); \ | |
73 | } \ | |
74 | }) | |
75 | ||
76 | void mlx5e_build_ptys2ethtool_map(void) | |
77 | { | |
78 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_CX_SGMII, SPEED_1000, | |
79 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
80 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_1000BASE_KX, SPEED_1000, | |
81 | ETHTOOL_LINK_MODE_1000baseKX_Full_BIT); | |
82 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CX4, SPEED_10000, | |
83 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
84 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KX4, SPEED_10000, | |
85 | ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT); | |
86 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_KR, SPEED_10000, | |
87 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
88 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_20GBASE_KR2, SPEED_20000, | |
89 | ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT); | |
90 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_CR4, SPEED_40000, | |
91 | ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT); | |
92 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_KR4, SPEED_40000, | |
93 | ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT); | |
94 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_56GBASE_R4, SPEED_56000, | |
95 | ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT); | |
96 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_CR, SPEED_10000, | |
97 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
98 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_SR, SPEED_10000, | |
99 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
100 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_ER, SPEED_10000, | |
101 | ETHTOOL_LINK_MODE_10000baseKR_Full_BIT); | |
102 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_SR4, SPEED_40000, | |
103 | ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT); | |
104 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_40GBASE_LR4, SPEED_40000, | |
105 | ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT); | |
106 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_SR2, SPEED_50000, | |
107 | ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT); | |
108 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_CR4, SPEED_100000, | |
109 | ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT); | |
110 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_SR4, SPEED_100000, | |
111 | ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT); | |
112 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_KR4, SPEED_100000, | |
113 | ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT); | |
114 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_100GBASE_LR4, SPEED_100000, | |
115 | ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT); | |
116 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_10GBASE_T, SPEED_10000, | |
117 | ETHTOOL_LINK_MODE_10000baseT_Full_BIT); | |
118 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_CR, SPEED_25000, | |
119 | ETHTOOL_LINK_MODE_25000baseCR_Full_BIT); | |
120 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_KR, SPEED_25000, | |
121 | ETHTOOL_LINK_MODE_25000baseKR_Full_BIT); | |
122 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_25GBASE_SR, SPEED_25000, | |
123 | ETHTOOL_LINK_MODE_25000baseSR_Full_BIT); | |
124 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_CR2, SPEED_50000, | |
125 | ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT); | |
126 | MLX5_BUILD_PTYS2ETHTOOL_CONFIG(MLX5E_50GBASE_KR2, SPEED_50000, | |
127 | ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT); | |
128 | } | |
129 | ||
cf678570 GP |
130 | static unsigned long mlx5e_query_pfc_combined(struct mlx5e_priv *priv) |
131 | { | |
132 | struct mlx5_core_dev *mdev = priv->mdev; | |
133 | u8 pfc_en_tx; | |
134 | u8 pfc_en_rx; | |
135 | int err; | |
136 | ||
137 | err = mlx5_query_port_pfc(mdev, &pfc_en_tx, &pfc_en_rx); | |
138 | ||
139 | return err ? 0 : pfc_en_tx | pfc_en_rx; | |
140 | } | |
141 | ||
593cf338 | 142 | #define MLX5E_NUM_Q_CNTRS(priv) (NUM_Q_COUNTERS * (!!priv->q_counter)) |
9218b44d GP |
143 | #define MLX5E_NUM_RQ_STATS(priv) \ |
144 | (NUM_RQ_STATS * priv->params.num_channels * \ | |
145 | test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
146 | #define MLX5E_NUM_SQ_STATS(priv) \ | |
147 | (NUM_SQ_STATS * priv->params.num_channels * priv->params.num_tc * \ | |
148 | test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
ed80ec4c GP |
149 | #define MLX5E_NUM_PFC_COUNTERS(priv) \ |
150 | (hweight8(mlx5e_query_pfc_combined(priv)) * \ | |
151 | NUM_PPORT_PER_PRIO_PFC_COUNTERS) | |
593cf338 | 152 | |
f62b8bb8 AV |
153 | static int mlx5e_get_sset_count(struct net_device *dev, int sset) |
154 | { | |
155 | struct mlx5e_priv *priv = netdev_priv(dev); | |
156 | ||
157 | switch (sset) { | |
158 | case ETH_SS_STATS: | |
9218b44d | 159 | return NUM_SW_COUNTERS + |
593cf338 | 160 | MLX5E_NUM_Q_CNTRS(priv) + |
9218b44d GP |
161 | NUM_VPORT_COUNTERS + NUM_PPORT_COUNTERS + |
162 | MLX5E_NUM_RQ_STATS(priv) + | |
cf678570 GP |
163 | MLX5E_NUM_SQ_STATS(priv) + |
164 | MLX5E_NUM_PFC_COUNTERS(priv); | |
4e59e288 GP |
165 | case ETH_SS_PRIV_FLAGS: |
166 | return ARRAY_SIZE(mlx5e_priv_flags); | |
f62b8bb8 AV |
167 | /* fallthrough */ |
168 | default: | |
169 | return -EOPNOTSUPP; | |
170 | } | |
171 | } | |
172 | ||
9218b44d GP |
173 | static void mlx5e_fill_stats_strings(struct mlx5e_priv *priv, uint8_t *data) |
174 | { | |
cf678570 GP |
175 | int i, j, tc, prio, idx = 0; |
176 | unsigned long pfc_combined; | |
9218b44d GP |
177 | |
178 | /* SW counters */ | |
179 | for (i = 0; i < NUM_SW_COUNTERS; i++) | |
bfe6d8d1 | 180 | strcpy(data + (idx++) * ETH_GSTRING_LEN, sw_stats_desc[i].format); |
9218b44d GP |
181 | |
182 | /* Q counters */ | |
183 | for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++) | |
bfe6d8d1 | 184 | strcpy(data + (idx++) * ETH_GSTRING_LEN, q_stats_desc[i].format); |
9218b44d GP |
185 | |
186 | /* VPORT counters */ | |
187 | for (i = 0; i < NUM_VPORT_COUNTERS; i++) | |
188 | strcpy(data + (idx++) * ETH_GSTRING_LEN, | |
bfe6d8d1 | 189 | vport_stats_desc[i].format); |
9218b44d GP |
190 | |
191 | /* PPORT counters */ | |
192 | for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) | |
193 | strcpy(data + (idx++) * ETH_GSTRING_LEN, | |
bfe6d8d1 | 194 | pport_802_3_stats_desc[i].format); |
9218b44d GP |
195 | |
196 | for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) | |
197 | strcpy(data + (idx++) * ETH_GSTRING_LEN, | |
bfe6d8d1 | 198 | pport_2863_stats_desc[i].format); |
9218b44d GP |
199 | |
200 | for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) | |
201 | strcpy(data + (idx++) * ETH_GSTRING_LEN, | |
bfe6d8d1 | 202 | pport_2819_stats_desc[i].format); |
9218b44d | 203 | |
cf678570 GP |
204 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { |
205 | for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) | |
bfe6d8d1 GP |
206 | sprintf(data + (idx++) * ETH_GSTRING_LEN, |
207 | pport_per_prio_traffic_stats_desc[i].format, prio); | |
cf678570 GP |
208 | } |
209 | ||
210 | pfc_combined = mlx5e_query_pfc_combined(priv); | |
211 | for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { | |
212 | for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { | |
bfe6d8d1 GP |
213 | sprintf(data + (idx++) * ETH_GSTRING_LEN, |
214 | pport_per_prio_pfc_stats_desc[i].format, prio); | |
cf678570 GP |
215 | } |
216 | } | |
217 | ||
9218b44d GP |
218 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
219 | return; | |
220 | ||
221 | /* per channel counters */ | |
222 | for (i = 0; i < priv->params.num_channels; i++) | |
223 | for (j = 0; j < NUM_RQ_STATS; j++) | |
bfe6d8d1 GP |
224 | sprintf(data + (idx++) * ETH_GSTRING_LEN, |
225 | rq_stats_desc[j].format, i); | |
9218b44d GP |
226 | |
227 | for (tc = 0; tc < priv->params.num_tc; tc++) | |
228 | for (i = 0; i < priv->params.num_channels; i++) | |
229 | for (j = 0; j < NUM_SQ_STATS; j++) | |
230 | sprintf(data + (idx++) * ETH_GSTRING_LEN, | |
bfe6d8d1 GP |
231 | sq_stats_desc[j].format, |
232 | priv->channeltc_to_txq_map[i][tc]); | |
9218b44d GP |
233 | } |
234 | ||
f62b8bb8 AV |
235 | static void mlx5e_get_strings(struct net_device *dev, |
236 | uint32_t stringset, uint8_t *data) | |
237 | { | |
f62b8bb8 | 238 | struct mlx5e_priv *priv = netdev_priv(dev); |
4e59e288 | 239 | int i; |
f62b8bb8 AV |
240 | |
241 | switch (stringset) { | |
242 | case ETH_SS_PRIV_FLAGS: | |
4e59e288 GP |
243 | for (i = 0; i < ARRAY_SIZE(mlx5e_priv_flags); i++) |
244 | strcpy(data + i * ETH_GSTRING_LEN, mlx5e_priv_flags[i]); | |
f62b8bb8 AV |
245 | break; |
246 | ||
247 | case ETH_SS_TEST: | |
248 | break; | |
249 | ||
250 | case ETH_SS_STATS: | |
9218b44d | 251 | mlx5e_fill_stats_strings(priv, data); |
f62b8bb8 AV |
252 | break; |
253 | } | |
254 | } | |
255 | ||
256 | static void mlx5e_get_ethtool_stats(struct net_device *dev, | |
257 | struct ethtool_stats *stats, u64 *data) | |
258 | { | |
259 | struct mlx5e_priv *priv = netdev_priv(dev); | |
cf678570 GP |
260 | int i, j, tc, prio, idx = 0; |
261 | unsigned long pfc_combined; | |
f62b8bb8 AV |
262 | |
263 | if (!data) | |
264 | return; | |
265 | ||
266 | mutex_lock(&priv->state_lock); | |
267 | if (test_bit(MLX5E_STATE_OPENED, &priv->state)) | |
268 | mlx5e_update_stats(priv); | |
269 | mutex_unlock(&priv->state_lock); | |
270 | ||
9218b44d GP |
271 | for (i = 0; i < NUM_SW_COUNTERS; i++) |
272 | data[idx++] = MLX5E_READ_CTR64_CPU(&priv->stats.sw, | |
273 | sw_stats_desc, i); | |
f62b8bb8 | 274 | |
593cf338 | 275 | for (i = 0; i < MLX5E_NUM_Q_CNTRS(priv); i++) |
9218b44d GP |
276 | data[idx++] = MLX5E_READ_CTR32_CPU(&priv->stats.qcnt, |
277 | q_stats_desc, i); | |
278 | ||
279 | for (i = 0; i < NUM_VPORT_COUNTERS; i++) | |
280 | data[idx++] = MLX5E_READ_CTR64_BE(priv->stats.vport.query_vport_out, | |
281 | vport_stats_desc, i); | |
593cf338 | 282 | |
9218b44d GP |
283 | for (i = 0; i < NUM_PPORT_802_3_COUNTERS; i++) |
284 | data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.IEEE_802_3_counters, | |
285 | pport_802_3_stats_desc, i); | |
286 | ||
287 | for (i = 0; i < NUM_PPORT_2863_COUNTERS; i++) | |
288 | data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2863_counters, | |
289 | pport_2863_stats_desc, i); | |
290 | ||
291 | for (i = 0; i < NUM_PPORT_2819_COUNTERS; i++) | |
292 | data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.RFC_2819_counters, | |
293 | pport_2819_stats_desc, i); | |
294 | ||
cf678570 GP |
295 | for (prio = 0; prio < NUM_PPORT_PRIO; prio++) { |
296 | for (i = 0; i < NUM_PPORT_PER_PRIO_TRAFFIC_COUNTERS; i++) | |
297 | data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], | |
298 | pport_per_prio_traffic_stats_desc, i); | |
299 | } | |
300 | ||
301 | pfc_combined = mlx5e_query_pfc_combined(priv); | |
302 | for_each_set_bit(prio, &pfc_combined, NUM_PPORT_PRIO) { | |
303 | for (i = 0; i < NUM_PPORT_PER_PRIO_PFC_COUNTERS; i++) { | |
304 | data[idx++] = MLX5E_READ_CTR64_BE(&priv->stats.pport.per_prio_counters[prio], | |
305 | pport_per_prio_pfc_stats_desc, i); | |
306 | } | |
307 | } | |
308 | ||
9218b44d GP |
309 | if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) |
310 | return; | |
efea389d | 311 | |
f62b8bb8 AV |
312 | /* per channel counters */ |
313 | for (i = 0; i < priv->params.num_channels; i++) | |
314 | for (j = 0; j < NUM_RQ_STATS; j++) | |
9218b44d GP |
315 | data[idx++] = |
316 | MLX5E_READ_CTR64_CPU(&priv->channel[i]->rq.stats, | |
317 | rq_stats_desc, j); | |
f62b8bb8 | 318 | |
3b619524 TT |
319 | for (tc = 0; tc < priv->params.num_tc; tc++) |
320 | for (i = 0; i < priv->params.num_channels; i++) | |
f62b8bb8 | 321 | for (j = 0; j < NUM_SQ_STATS; j++) |
9218b44d GP |
322 | data[idx++] = MLX5E_READ_CTR64_CPU(&priv->channel[i]->sq[tc].stats, |
323 | sq_stats_desc, j); | |
f62b8bb8 AV |
324 | } |
325 | ||
326 | static void mlx5e_get_ringparam(struct net_device *dev, | |
327 | struct ethtool_ringparam *param) | |
328 | { | |
329 | struct mlx5e_priv *priv = netdev_priv(dev); | |
461017cb | 330 | int rq_wq_type = priv->params.rq_wq_type; |
f62b8bb8 | 331 | |
461017cb | 332 | param->rx_max_pending = 1 << mlx5_max_log_rq_size(rq_wq_type); |
f62b8bb8 AV |
333 | param->tx_max_pending = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE; |
334 | param->rx_pending = 1 << priv->params.log_rq_size; | |
335 | param->tx_pending = 1 << priv->params.log_sq_size; | |
336 | } | |
337 | ||
338 | static int mlx5e_set_ringparam(struct net_device *dev, | |
339 | struct ethtool_ringparam *param) | |
340 | { | |
341 | struct mlx5e_priv *priv = netdev_priv(dev); | |
98e81b0a | 342 | bool was_opened; |
461017cb | 343 | int rq_wq_type = priv->params.rq_wq_type; |
f62b8bb8 AV |
344 | u16 min_rx_wqes; |
345 | u8 log_rq_size; | |
346 | u8 log_sq_size; | |
347 | int err = 0; | |
348 | ||
349 | if (param->rx_jumbo_pending) { | |
350 | netdev_info(dev, "%s: rx_jumbo_pending not supported\n", | |
351 | __func__); | |
352 | return -EINVAL; | |
353 | } | |
354 | if (param->rx_mini_pending) { | |
355 | netdev_info(dev, "%s: rx_mini_pending not supported\n", | |
356 | __func__); | |
357 | return -EINVAL; | |
358 | } | |
461017cb | 359 | if (param->rx_pending < (1 << mlx5_min_log_rq_size(rq_wq_type))) { |
f62b8bb8 AV |
360 | netdev_info(dev, "%s: rx_pending (%d) < min (%d)\n", |
361 | __func__, param->rx_pending, | |
461017cb | 362 | 1 << mlx5_min_log_rq_size(rq_wq_type)); |
f62b8bb8 AV |
363 | return -EINVAL; |
364 | } | |
461017cb | 365 | if (param->rx_pending > (1 << mlx5_max_log_rq_size(rq_wq_type))) { |
f62b8bb8 AV |
366 | netdev_info(dev, "%s: rx_pending (%d) > max (%d)\n", |
367 | __func__, param->rx_pending, | |
461017cb | 368 | 1 << mlx5_max_log_rq_size(rq_wq_type)); |
f62b8bb8 AV |
369 | return -EINVAL; |
370 | } | |
371 | if (param->tx_pending < (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) { | |
372 | netdev_info(dev, "%s: tx_pending (%d) < min (%d)\n", | |
373 | __func__, param->tx_pending, | |
374 | 1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE); | |
375 | return -EINVAL; | |
376 | } | |
377 | if (param->tx_pending > (1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE)) { | |
378 | netdev_info(dev, "%s: tx_pending (%d) > max (%d)\n", | |
379 | __func__, param->tx_pending, | |
380 | 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE); | |
381 | return -EINVAL; | |
382 | } | |
383 | ||
384 | log_rq_size = order_base_2(param->rx_pending); | |
385 | log_sq_size = order_base_2(param->tx_pending); | |
461017cb | 386 | min_rx_wqes = mlx5_min_rx_wqes(rq_wq_type, param->rx_pending); |
f62b8bb8 AV |
387 | |
388 | if (log_rq_size == priv->params.log_rq_size && | |
389 | log_sq_size == priv->params.log_sq_size && | |
390 | min_rx_wqes == priv->params.min_rx_wqes) | |
391 | return 0; | |
392 | ||
393 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
394 | |
395 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
396 | if (was_opened) | |
397 | mlx5e_close_locked(dev); | |
398 | ||
399 | priv->params.log_rq_size = log_rq_size; | |
400 | priv->params.log_sq_size = log_sq_size; | |
401 | priv->params.min_rx_wqes = min_rx_wqes; | |
402 | ||
403 | if (was_opened) | |
404 | err = mlx5e_open_locked(dev); | |
405 | ||
f62b8bb8 AV |
406 | mutex_unlock(&priv->state_lock); |
407 | ||
408 | return err; | |
409 | } | |
410 | ||
411 | static void mlx5e_get_channels(struct net_device *dev, | |
412 | struct ethtool_channels *ch) | |
413 | { | |
414 | struct mlx5e_priv *priv = netdev_priv(dev); | |
f62b8bb8 | 415 | |
3435ab59 | 416 | ch->max_combined = mlx5e_get_max_num_channels(priv->mdev); |
f62b8bb8 AV |
417 | ch->combined_count = priv->params.num_channels; |
418 | } | |
419 | ||
420 | static int mlx5e_set_channels(struct net_device *dev, | |
421 | struct ethtool_channels *ch) | |
422 | { | |
423 | struct mlx5e_priv *priv = netdev_priv(dev); | |
3435ab59 | 424 | int ncv = mlx5e_get_max_num_channels(priv->mdev); |
f62b8bb8 | 425 | unsigned int count = ch->combined_count; |
45bf454a | 426 | bool arfs_enabled; |
98e81b0a | 427 | bool was_opened; |
f62b8bb8 AV |
428 | int err = 0; |
429 | ||
430 | if (!count) { | |
431 | netdev_info(dev, "%s: combined_count=0 not supported\n", | |
432 | __func__); | |
433 | return -EINVAL; | |
434 | } | |
435 | if (ch->rx_count || ch->tx_count) { | |
436 | netdev_info(dev, "%s: separate rx/tx count not supported\n", | |
437 | __func__); | |
438 | return -EINVAL; | |
439 | } | |
440 | if (count > ncv) { | |
441 | netdev_info(dev, "%s: count (%d) > max (%d)\n", | |
442 | __func__, count, ncv); | |
443 | return -EINVAL; | |
444 | } | |
445 | ||
446 | if (priv->params.num_channels == count) | |
447 | return 0; | |
448 | ||
449 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
450 | |
451 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
452 | if (was_opened) | |
453 | mlx5e_close_locked(dev); | |
454 | ||
45bf454a MG |
455 | arfs_enabled = dev->features & NETIF_F_NTUPLE; |
456 | if (arfs_enabled) | |
457 | mlx5e_arfs_disable(priv); | |
458 | ||
98e81b0a | 459 | priv->params.num_channels = count; |
d8c9660d | 460 | mlx5e_build_default_indir_rqt(priv->mdev, priv->params.indirection_rqt, |
85082dba | 461 | MLX5E_INDIR_RQT_SIZE, count); |
98e81b0a AS |
462 | |
463 | if (was_opened) | |
464 | err = mlx5e_open_locked(dev); | |
45bf454a MG |
465 | if (err) |
466 | goto out; | |
467 | ||
468 | if (arfs_enabled) { | |
469 | err = mlx5e_arfs_enable(priv); | |
470 | if (err) | |
471 | netdev_err(dev, "%s: mlx5e_arfs_enable failed: %d\n", | |
472 | __func__, err); | |
473 | } | |
98e81b0a | 474 | |
45bf454a | 475 | out: |
f62b8bb8 AV |
476 | mutex_unlock(&priv->state_lock); |
477 | ||
478 | return err; | |
479 | } | |
480 | ||
481 | static int mlx5e_get_coalesce(struct net_device *netdev, | |
482 | struct ethtool_coalesce *coal) | |
483 | { | |
484 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
485 | ||
7524a5d8 GP |
486 | if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) |
487 | return -ENOTSUPP; | |
488 | ||
9908aa29 TT |
489 | coal->rx_coalesce_usecs = priv->params.rx_cq_moderation.usec; |
490 | coal->rx_max_coalesced_frames = priv->params.rx_cq_moderation.pkts; | |
491 | coal->tx_coalesce_usecs = priv->params.tx_cq_moderation.usec; | |
492 | coal->tx_max_coalesced_frames = priv->params.tx_cq_moderation.pkts; | |
cb3c7fd4 | 493 | coal->use_adaptive_rx_coalesce = priv->params.rx_am_enabled; |
f62b8bb8 AV |
494 | |
495 | return 0; | |
496 | } | |
497 | ||
498 | static int mlx5e_set_coalesce(struct net_device *netdev, | |
499 | struct ethtool_coalesce *coal) | |
500 | { | |
501 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
502 | struct mlx5_core_dev *mdev = priv->mdev; | |
503 | struct mlx5e_channel *c; | |
cb3c7fd4 GR |
504 | bool restart = |
505 | !!coal->use_adaptive_rx_coalesce != priv->params.rx_am_enabled; | |
506 | bool was_opened; | |
507 | int err = 0; | |
f62b8bb8 AV |
508 | int tc; |
509 | int i; | |
510 | ||
7524a5d8 GP |
511 | if (!MLX5_CAP_GEN(mdev, cq_moderation)) |
512 | return -ENOTSUPP; | |
513 | ||
2fcb92fb | 514 | mutex_lock(&priv->state_lock); |
9908aa29 | 515 | |
cb3c7fd4 GR |
516 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); |
517 | if (was_opened && restart) { | |
518 | mlx5e_close_locked(netdev); | |
519 | priv->params.rx_am_enabled = !!coal->use_adaptive_rx_coalesce; | |
520 | } | |
521 | ||
9908aa29 TT |
522 | priv->params.tx_cq_moderation.usec = coal->tx_coalesce_usecs; |
523 | priv->params.tx_cq_moderation.pkts = coal->tx_max_coalesced_frames; | |
524 | priv->params.rx_cq_moderation.usec = coal->rx_coalesce_usecs; | |
525 | priv->params.rx_cq_moderation.pkts = coal->rx_max_coalesced_frames; | |
f62b8bb8 | 526 | |
cb3c7fd4 | 527 | if (!was_opened || restart) |
2fcb92fb GP |
528 | goto out; |
529 | ||
f62b8bb8 AV |
530 | for (i = 0; i < priv->params.num_channels; ++i) { |
531 | c = priv->channel[i]; | |
532 | ||
533 | for (tc = 0; tc < c->num_tc; tc++) { | |
534 | mlx5_core_modify_cq_moderation(mdev, | |
535 | &c->sq[tc].cq.mcq, | |
536 | coal->tx_coalesce_usecs, | |
537 | coal->tx_max_coalesced_frames); | |
538 | } | |
539 | ||
540 | mlx5_core_modify_cq_moderation(mdev, &c->rq.cq.mcq, | |
541 | coal->rx_coalesce_usecs, | |
542 | coal->rx_max_coalesced_frames); | |
543 | } | |
544 | ||
2fcb92fb | 545 | out: |
cb3c7fd4 GR |
546 | if (was_opened && restart) |
547 | err = mlx5e_open_locked(netdev); | |
548 | ||
2fcb92fb | 549 | mutex_unlock(&priv->state_lock); |
cb3c7fd4 | 550 | return err; |
f62b8bb8 AV |
551 | } |
552 | ||
665bc539 GP |
553 | static void ptys2ethtool_supported_link(unsigned long *supported_modes, |
554 | u32 eth_proto_cap) | |
f62b8bb8 | 555 | { |
665bc539 | 556 | int proto; |
f62b8bb8 | 557 | |
665bc539 GP |
558 | for_each_set_bit(proto, (unsigned long *)ð_proto_cap, MLX5E_LINK_MODES_NUMBER) |
559 | bitmap_or(supported_modes, supported_modes, | |
560 | ptys2ethtool_table[proto].supported, | |
561 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
f62b8bb8 AV |
562 | } |
563 | ||
665bc539 GP |
564 | static void ptys2ethtool_adver_link(unsigned long *advertising_modes, |
565 | u32 eth_proto_cap) | |
f62b8bb8 | 566 | { |
665bc539 | 567 | int proto; |
f62b8bb8 | 568 | |
665bc539 GP |
569 | for_each_set_bit(proto, (unsigned long *)ð_proto_cap, MLX5E_LINK_MODES_NUMBER) |
570 | bitmap_or(advertising_modes, advertising_modes, | |
571 | ptys2ethtool_table[proto].advertised, | |
572 | __ETHTOOL_LINK_MODE_MASK_NBITS); | |
f62b8bb8 AV |
573 | } |
574 | ||
665bc539 GP |
575 | static void ptys2ethtool_supported_port(struct ethtool_link_ksettings *link_ksettings, |
576 | u32 eth_proto_cap) | |
f62b8bb8 AV |
577 | { |
578 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | |
579 | | MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | |
580 | | MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | |
581 | | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | |
582 | | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | |
583 | | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
665bc539 | 584 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, FIBRE); |
f62b8bb8 AV |
585 | } |
586 | ||
587 | if (eth_proto_cap & (MLX5E_PROT_MASK(MLX5E_100GBASE_KR4) | |
588 | | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | |
589 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | |
590 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | |
591 | | MLX5E_PROT_MASK(MLX5E_1000BASE_KX))) { | |
665bc539 | 592 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Backplane); |
f62b8bb8 | 593 | } |
f62b8bb8 AV |
594 | } |
595 | ||
b797a684 SM |
596 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed) |
597 | { | |
598 | u32 max_speed = 0; | |
599 | u32 proto_cap; | |
600 | int err; | |
601 | int i; | |
602 | ||
603 | err = mlx5_query_port_proto_cap(mdev, &proto_cap, MLX5_PTYS_EN); | |
604 | if (err) | |
605 | return err; | |
606 | ||
607 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) | |
608 | if (proto_cap & MLX5E_PROT_MASK(i)) | |
609 | max_speed = max(max_speed, ptys2ethtool_table[i].speed); | |
610 | ||
611 | *speed = max_speed; | |
612 | return 0; | |
613 | } | |
614 | ||
f62b8bb8 AV |
615 | static void get_speed_duplex(struct net_device *netdev, |
616 | u32 eth_proto_oper, | |
665bc539 | 617 | struct ethtool_link_ksettings *link_ksettings) |
f62b8bb8 AV |
618 | { |
619 | int i; | |
620 | u32 speed = SPEED_UNKNOWN; | |
621 | u8 duplex = DUPLEX_UNKNOWN; | |
622 | ||
623 | if (!netif_carrier_ok(netdev)) | |
624 | goto out; | |
625 | ||
626 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { | |
627 | if (eth_proto_oper & MLX5E_PROT_MASK(i)) { | |
628 | speed = ptys2ethtool_table[i].speed; | |
629 | duplex = DUPLEX_FULL; | |
630 | break; | |
631 | } | |
632 | } | |
633 | out: | |
665bc539 GP |
634 | link_ksettings->base.speed = speed; |
635 | link_ksettings->base.duplex = duplex; | |
f62b8bb8 AV |
636 | } |
637 | ||
665bc539 GP |
638 | static void get_supported(u32 eth_proto_cap, |
639 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 640 | { |
665bc539 GP |
641 | unsigned long *supported = link_ksettings->link_modes.supported; |
642 | ||
643 | ptys2ethtool_supported_port(link_ksettings, eth_proto_cap); | |
644 | ptys2ethtool_supported_link(supported, eth_proto_cap); | |
645 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Pause); | |
646 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, Asym_Pause); | |
f62b8bb8 AV |
647 | } |
648 | ||
649 | static void get_advertising(u32 eth_proto_cap, u8 tx_pause, | |
665bc539 GP |
650 | u8 rx_pause, |
651 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 652 | { |
665bc539 GP |
653 | unsigned long *advertising = link_ksettings->link_modes.advertising; |
654 | ||
655 | ptys2ethtool_adver_link(advertising, eth_proto_cap); | |
656 | if (tx_pause) | |
657 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Pause); | |
658 | if (tx_pause ^ rx_pause) | |
659 | ethtool_link_ksettings_add_link_mode(link_ksettings, advertising, Asym_Pause); | |
f62b8bb8 AV |
660 | } |
661 | ||
662 | static u8 get_connector_port(u32 eth_proto) | |
663 | { | |
664 | if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_SR) | |
665 | | MLX5E_PROT_MASK(MLX5E_40GBASE_SR4) | |
666 | | MLX5E_PROT_MASK(MLX5E_100GBASE_SR4) | |
667 | | MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII))) { | |
668 | return PORT_FIBRE; | |
669 | } | |
670 | ||
671 | if (eth_proto & (MLX5E_PROT_MASK(MLX5E_40GBASE_CR4) | |
672 | | MLX5E_PROT_MASK(MLX5E_10GBASE_CR) | |
673 | | MLX5E_PROT_MASK(MLX5E_100GBASE_CR4))) { | |
674 | return PORT_DA; | |
675 | } | |
676 | ||
677 | if (eth_proto & (MLX5E_PROT_MASK(MLX5E_10GBASE_KX4) | |
678 | | MLX5E_PROT_MASK(MLX5E_10GBASE_KR) | |
679 | | MLX5E_PROT_MASK(MLX5E_40GBASE_KR4) | |
680 | | MLX5E_PROT_MASK(MLX5E_100GBASE_KR4))) { | |
681 | return PORT_NONE; | |
682 | } | |
683 | ||
684 | return PORT_OTHER; | |
685 | } | |
686 | ||
665bc539 GP |
687 | static void get_lp_advertising(u32 eth_proto_lp, |
688 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 | 689 | { |
665bc539 GP |
690 | unsigned long *lp_advertising = link_ksettings->link_modes.lp_advertising; |
691 | ||
692 | ptys2ethtool_adver_link(lp_advertising, eth_proto_lp); | |
f62b8bb8 AV |
693 | } |
694 | ||
665bc539 GP |
695 | static int mlx5e_get_link_ksettings(struct net_device *netdev, |
696 | struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 AV |
697 | { |
698 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
699 | struct mlx5_core_dev *mdev = priv->mdev; | |
700 | u32 out[MLX5_ST_SZ_DW(ptys_reg)]; | |
701 | u32 eth_proto_cap; | |
702 | u32 eth_proto_admin; | |
703 | u32 eth_proto_lp; | |
704 | u32 eth_proto_oper; | |
52244d96 GP |
705 | u8 an_disable_admin; |
706 | u8 an_status; | |
f62b8bb8 AV |
707 | int err; |
708 | ||
a05bdefa | 709 | err = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1); |
f62b8bb8 AV |
710 | |
711 | if (err) { | |
712 | netdev_err(netdev, "%s: query port ptys failed: %d\n", | |
713 | __func__, err); | |
714 | goto err_query_ptys; | |
715 | } | |
716 | ||
52244d96 GP |
717 | eth_proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability); |
718 | eth_proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin); | |
719 | eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper); | |
720 | eth_proto_lp = MLX5_GET(ptys_reg, out, eth_proto_lp_advertise); | |
721 | an_disable_admin = MLX5_GET(ptys_reg, out, an_disable_admin); | |
722 | an_status = MLX5_GET(ptys_reg, out, an_status); | |
f62b8bb8 | 723 | |
665bc539 GP |
724 | ethtool_link_ksettings_zero_link_mode(link_ksettings, supported); |
725 | ethtool_link_ksettings_zero_link_mode(link_ksettings, advertising); | |
f62b8bb8 | 726 | |
665bc539 GP |
727 | get_supported(eth_proto_cap, link_ksettings); |
728 | get_advertising(eth_proto_admin, 0, 0, link_ksettings); | |
729 | get_speed_duplex(netdev, eth_proto_oper, link_ksettings); | |
f62b8bb8 AV |
730 | |
731 | eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap; | |
732 | ||
665bc539 GP |
733 | link_ksettings->base.port = get_connector_port(eth_proto_oper); |
734 | get_lp_advertising(eth_proto_lp, link_ksettings); | |
f62b8bb8 | 735 | |
52244d96 GP |
736 | if (an_status == MLX5_AN_COMPLETE) |
737 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
738 | lp_advertising, Autoneg); | |
739 | ||
740 | link_ksettings->base.autoneg = an_disable_admin ? AUTONEG_DISABLE : | |
741 | AUTONEG_ENABLE; | |
742 | ethtool_link_ksettings_add_link_mode(link_ksettings, supported, | |
743 | Autoneg); | |
744 | if (!an_disable_admin) | |
745 | ethtool_link_ksettings_add_link_mode(link_ksettings, | |
746 | advertising, Autoneg); | |
747 | ||
f62b8bb8 AV |
748 | err_query_ptys: |
749 | return err; | |
750 | } | |
751 | ||
665bc539 | 752 | static u32 mlx5e_ethtool2ptys_adver_link(const unsigned long *link_modes) |
f62b8bb8 AV |
753 | { |
754 | u32 i, ptys_modes = 0; | |
755 | ||
756 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { | |
665bc539 GP |
757 | if (bitmap_intersects(ptys2ethtool_table[i].advertised, |
758 | link_modes, | |
759 | __ETHTOOL_LINK_MODE_MASK_NBITS)) | |
f62b8bb8 AV |
760 | ptys_modes |= MLX5E_PROT_MASK(i); |
761 | } | |
762 | ||
763 | return ptys_modes; | |
764 | } | |
765 | ||
766 | static u32 mlx5e_ethtool2ptys_speed_link(u32 speed) | |
767 | { | |
768 | u32 i, speed_links = 0; | |
769 | ||
770 | for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) { | |
771 | if (ptys2ethtool_table[i].speed == speed) | |
772 | speed_links |= MLX5E_PROT_MASK(i); | |
773 | } | |
774 | ||
775 | return speed_links; | |
776 | } | |
777 | ||
665bc539 GP |
778 | static int mlx5e_set_link_ksettings(struct net_device *netdev, |
779 | const struct ethtool_link_ksettings *link_ksettings) | |
f62b8bb8 AV |
780 | { |
781 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
782 | struct mlx5_core_dev *mdev = priv->mdev; | |
52244d96 GP |
783 | u32 eth_proto_cap, eth_proto_admin; |
784 | bool an_changes = false; | |
785 | u8 an_disable_admin; | |
786 | u8 an_disable_cap; | |
787 | bool an_disable; | |
f62b8bb8 | 788 | u32 link_modes; |
52244d96 | 789 | u8 an_status; |
f62b8bb8 | 790 | u32 speed; |
f62b8bb8 AV |
791 | int err; |
792 | ||
665bc539 | 793 | speed = link_ksettings->base.speed; |
f62b8bb8 | 794 | |
665bc539 GP |
795 | link_modes = link_ksettings->base.autoneg == AUTONEG_ENABLE ? |
796 | mlx5e_ethtool2ptys_adver_link(link_ksettings->link_modes.advertising) : | |
f62b8bb8 AV |
797 | mlx5e_ethtool2ptys_speed_link(speed); |
798 | ||
799 | err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN); | |
800 | if (err) { | |
801 | netdev_err(netdev, "%s: query port eth proto cap failed: %d\n", | |
802 | __func__, err); | |
803 | goto out; | |
804 | } | |
805 | ||
806 | link_modes = link_modes & eth_proto_cap; | |
807 | if (!link_modes) { | |
808 | netdev_err(netdev, "%s: Not supported link mode(s) requested", | |
809 | __func__); | |
810 | err = -EINVAL; | |
811 | goto out; | |
812 | } | |
813 | ||
814 | err = mlx5_query_port_proto_admin(mdev, ð_proto_admin, MLX5_PTYS_EN); | |
815 | if (err) { | |
816 | netdev_err(netdev, "%s: query port eth proto admin failed: %d\n", | |
817 | __func__, err); | |
818 | goto out; | |
819 | } | |
820 | ||
52244d96 GP |
821 | mlx5_query_port_autoneg(mdev, MLX5_PTYS_EN, &an_status, |
822 | &an_disable_cap, &an_disable_admin); | |
823 | ||
824 | an_disable = link_ksettings->base.autoneg == AUTONEG_DISABLE; | |
825 | an_changes = ((!an_disable && an_disable_admin) || | |
826 | (an_disable && !an_disable_admin)); | |
827 | ||
828 | if (!an_changes && link_modes == eth_proto_admin) | |
f62b8bb8 AV |
829 | goto out; |
830 | ||
52244d96 | 831 | mlx5_set_port_ptys(mdev, an_disable, link_modes, MLX5_PTYS_EN); |
667daeda | 832 | mlx5_toggle_port_link(mdev); |
f62b8bb8 | 833 | |
f62b8bb8 AV |
834 | out: |
835 | return err; | |
836 | } | |
837 | ||
2d75b2bc AS |
838 | static u32 mlx5e_get_rxfh_key_size(struct net_device *netdev) |
839 | { | |
840 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
841 | ||
842 | return sizeof(priv->params.toeplitz_hash_key); | |
843 | } | |
844 | ||
845 | static u32 mlx5e_get_rxfh_indir_size(struct net_device *netdev) | |
846 | { | |
847 | return MLX5E_INDIR_RQT_SIZE; | |
848 | } | |
849 | ||
2be6967c SM |
850 | static int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, |
851 | u8 *hfunc) | |
852 | { | |
853 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
854 | ||
2d75b2bc AS |
855 | if (indir) |
856 | memcpy(indir, priv->params.indirection_rqt, | |
857 | sizeof(priv->params.indirection_rqt)); | |
858 | ||
859 | if (key) | |
860 | memcpy(key, priv->params.toeplitz_hash_key, | |
861 | sizeof(priv->params.toeplitz_hash_key)); | |
862 | ||
2be6967c SM |
863 | if (hfunc) |
864 | *hfunc = priv->params.rss_hfunc; | |
865 | ||
866 | return 0; | |
867 | } | |
868 | ||
bdfc028d TT |
869 | static void mlx5e_modify_tirs_hash(struct mlx5e_priv *priv, void *in, int inlen) |
870 | { | |
871 | struct mlx5_core_dev *mdev = priv->mdev; | |
872 | void *tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx); | |
873 | int i; | |
874 | ||
875 | MLX5_SET(modify_tir_in, in, bitmask.hash, 1); | |
876 | mlx5e_build_tir_ctx_hash(tirc, priv); | |
877 | ||
1da36696 | 878 | for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) |
724b2aa1 | 879 | mlx5_core_modify_tir(mdev, priv->indir_tir[i].tirn, in, inlen); |
bdfc028d TT |
880 | } |
881 | ||
98e81b0a | 882 | static int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, |
2be6967c SM |
883 | const u8 *key, const u8 hfunc) |
884 | { | |
98e81b0a | 885 | struct mlx5e_priv *priv = netdev_priv(dev); |
bdfc028d TT |
886 | int inlen = MLX5_ST_SZ_BYTES(modify_tir_in); |
887 | void *in; | |
2be6967c | 888 | |
2d75b2bc AS |
889 | if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && |
890 | (hfunc != ETH_RSS_HASH_XOR) && | |
2be6967c SM |
891 | (hfunc != ETH_RSS_HASH_TOP)) |
892 | return -EINVAL; | |
893 | ||
bdfc028d TT |
894 | in = mlx5_vzalloc(inlen); |
895 | if (!in) | |
896 | return -ENOMEM; | |
897 | ||
2be6967c SM |
898 | mutex_lock(&priv->state_lock); |
899 | ||
2d75b2bc | 900 | if (indir) { |
398f3351 | 901 | u32 rqtn = priv->indir_rqt.rqtn; |
1da36696 | 902 | |
2d75b2bc AS |
903 | memcpy(priv->params.indirection_rqt, indir, |
904 | sizeof(priv->params.indirection_rqt)); | |
1da36696 | 905 | mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0); |
2be6967c SM |
906 | } |
907 | ||
2d75b2bc AS |
908 | if (key) |
909 | memcpy(priv->params.toeplitz_hash_key, key, | |
910 | sizeof(priv->params.toeplitz_hash_key)); | |
911 | ||
912 | if (hfunc != ETH_RSS_HASH_NO_CHANGE) | |
913 | priv->params.rss_hfunc = hfunc; | |
914 | ||
bdfc028d | 915 | mlx5e_modify_tirs_hash(priv, in, inlen); |
2d75b2bc | 916 | |
2be6967c SM |
917 | mutex_unlock(&priv->state_lock); |
918 | ||
bdfc028d TT |
919 | kvfree(in); |
920 | ||
921 | return 0; | |
2be6967c SM |
922 | } |
923 | ||
2d75b2bc AS |
924 | static int mlx5e_get_rxnfc(struct net_device *netdev, |
925 | struct ethtool_rxnfc *info, u32 *rule_locs) | |
926 | { | |
927 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
928 | int err = 0; | |
929 | ||
930 | switch (info->cmd) { | |
931 | case ETHTOOL_GRXRINGS: | |
932 | info->data = priv->params.num_channels; | |
933 | break; | |
934 | default: | |
935 | err = -EOPNOTSUPP; | |
936 | break; | |
937 | } | |
938 | ||
939 | return err; | |
940 | } | |
941 | ||
58d52291 AS |
942 | static int mlx5e_get_tunable(struct net_device *dev, |
943 | const struct ethtool_tunable *tuna, | |
944 | void *data) | |
945 | { | |
946 | const struct mlx5e_priv *priv = netdev_priv(dev); | |
947 | int err = 0; | |
948 | ||
949 | switch (tuna->id) { | |
950 | case ETHTOOL_TX_COPYBREAK: | |
951 | *(u32 *)data = priv->params.tx_max_inline; | |
952 | break; | |
953 | default: | |
954 | err = -EINVAL; | |
955 | break; | |
956 | } | |
957 | ||
958 | return err; | |
959 | } | |
960 | ||
961 | static int mlx5e_set_tunable(struct net_device *dev, | |
962 | const struct ethtool_tunable *tuna, | |
963 | const void *data) | |
964 | { | |
965 | struct mlx5e_priv *priv = netdev_priv(dev); | |
966 | struct mlx5_core_dev *mdev = priv->mdev; | |
98e81b0a | 967 | bool was_opened; |
58d52291 AS |
968 | u32 val; |
969 | int err = 0; | |
970 | ||
971 | switch (tuna->id) { | |
972 | case ETHTOOL_TX_COPYBREAK: | |
973 | val = *(u32 *)data; | |
974 | if (val > mlx5e_get_max_inline_cap(mdev)) { | |
975 | err = -EINVAL; | |
976 | break; | |
977 | } | |
978 | ||
979 | mutex_lock(&priv->state_lock); | |
98e81b0a AS |
980 | |
981 | was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
982 | if (was_opened) | |
983 | mlx5e_close_locked(dev); | |
984 | ||
985 | priv->params.tx_max_inline = val; | |
986 | ||
987 | if (was_opened) | |
988 | err = mlx5e_open_locked(dev); | |
989 | ||
58d52291 AS |
990 | mutex_unlock(&priv->state_lock); |
991 | break; | |
992 | default: | |
993 | err = -EINVAL; | |
994 | break; | |
995 | } | |
996 | ||
997 | return err; | |
998 | } | |
999 | ||
3c2d18ef AS |
1000 | static void mlx5e_get_pauseparam(struct net_device *netdev, |
1001 | struct ethtool_pauseparam *pauseparam) | |
1002 | { | |
1003 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1004 | struct mlx5_core_dev *mdev = priv->mdev; | |
1005 | int err; | |
1006 | ||
1007 | err = mlx5_query_port_pause(mdev, &pauseparam->rx_pause, | |
1008 | &pauseparam->tx_pause); | |
1009 | if (err) { | |
1010 | netdev_err(netdev, "%s: mlx5_query_port_pause failed:0x%x\n", | |
1011 | __func__, err); | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | static int mlx5e_set_pauseparam(struct net_device *netdev, | |
1016 | struct ethtool_pauseparam *pauseparam) | |
1017 | { | |
1018 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1019 | struct mlx5_core_dev *mdev = priv->mdev; | |
1020 | int err; | |
1021 | ||
1022 | if (pauseparam->autoneg) | |
1023 | return -EINVAL; | |
1024 | ||
1025 | err = mlx5_set_port_pause(mdev, | |
1026 | pauseparam->rx_pause ? 1 : 0, | |
1027 | pauseparam->tx_pause ? 1 : 0); | |
1028 | if (err) { | |
1029 | netdev_err(netdev, "%s: mlx5_set_port_pause failed:0x%x\n", | |
1030 | __func__, err); | |
1031 | } | |
1032 | ||
1033 | return err; | |
1034 | } | |
1035 | ||
ef9814de EBE |
1036 | static int mlx5e_get_ts_info(struct net_device *dev, |
1037 | struct ethtool_ts_info *info) | |
1038 | { | |
1039 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1040 | int ret; | |
1041 | ||
1042 | ret = ethtool_op_get_ts_info(dev, info); | |
1043 | if (ret) | |
1044 | return ret; | |
1045 | ||
3d8c38af EBE |
1046 | info->phc_index = priv->tstamp.ptp ? |
1047 | ptp_clock_index(priv->tstamp.ptp) : -1; | |
ef9814de EBE |
1048 | |
1049 | if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz)) | |
1050 | return 0; | |
1051 | ||
1052 | info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | | |
1053 | SOF_TIMESTAMPING_RX_HARDWARE | | |
1054 | SOF_TIMESTAMPING_RAW_HARDWARE; | |
1055 | ||
1056 | info->tx_types = (BIT(1) << HWTSTAMP_TX_OFF) | | |
1057 | (BIT(1) << HWTSTAMP_TX_ON); | |
1058 | ||
1059 | info->rx_filters = (BIT(1) << HWTSTAMP_FILTER_NONE) | | |
1060 | (BIT(1) << HWTSTAMP_FILTER_ALL); | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
928cfe87 TT |
1065 | static __u32 mlx5e_get_wol_supported(struct mlx5_core_dev *mdev) |
1066 | { | |
1067 | __u32 ret = 0; | |
1068 | ||
1069 | if (MLX5_CAP_GEN(mdev, wol_g)) | |
1070 | ret |= WAKE_MAGIC; | |
1071 | ||
1072 | if (MLX5_CAP_GEN(mdev, wol_s)) | |
1073 | ret |= WAKE_MAGICSECURE; | |
1074 | ||
1075 | if (MLX5_CAP_GEN(mdev, wol_a)) | |
1076 | ret |= WAKE_ARP; | |
1077 | ||
1078 | if (MLX5_CAP_GEN(mdev, wol_b)) | |
1079 | ret |= WAKE_BCAST; | |
1080 | ||
1081 | if (MLX5_CAP_GEN(mdev, wol_m)) | |
1082 | ret |= WAKE_MCAST; | |
1083 | ||
1084 | if (MLX5_CAP_GEN(mdev, wol_u)) | |
1085 | ret |= WAKE_UCAST; | |
1086 | ||
1087 | if (MLX5_CAP_GEN(mdev, wol_p)) | |
1088 | ret |= WAKE_PHY; | |
1089 | ||
1090 | return ret; | |
1091 | } | |
1092 | ||
1093 | static __u32 mlx5e_refomrat_wol_mode_mlx5_to_linux(u8 mode) | |
1094 | { | |
1095 | __u32 ret = 0; | |
1096 | ||
1097 | if (mode & MLX5_WOL_MAGIC) | |
1098 | ret |= WAKE_MAGIC; | |
1099 | ||
1100 | if (mode & MLX5_WOL_SECURED_MAGIC) | |
1101 | ret |= WAKE_MAGICSECURE; | |
1102 | ||
1103 | if (mode & MLX5_WOL_ARP) | |
1104 | ret |= WAKE_ARP; | |
1105 | ||
1106 | if (mode & MLX5_WOL_BROADCAST) | |
1107 | ret |= WAKE_BCAST; | |
1108 | ||
1109 | if (mode & MLX5_WOL_MULTICAST) | |
1110 | ret |= WAKE_MCAST; | |
1111 | ||
1112 | if (mode & MLX5_WOL_UNICAST) | |
1113 | ret |= WAKE_UCAST; | |
1114 | ||
1115 | if (mode & MLX5_WOL_PHY_ACTIVITY) | |
1116 | ret |= WAKE_PHY; | |
1117 | ||
1118 | return ret; | |
1119 | } | |
1120 | ||
1121 | static u8 mlx5e_refomrat_wol_mode_linux_to_mlx5(__u32 mode) | |
1122 | { | |
1123 | u8 ret = 0; | |
1124 | ||
1125 | if (mode & WAKE_MAGIC) | |
1126 | ret |= MLX5_WOL_MAGIC; | |
1127 | ||
1128 | if (mode & WAKE_MAGICSECURE) | |
1129 | ret |= MLX5_WOL_SECURED_MAGIC; | |
1130 | ||
1131 | if (mode & WAKE_ARP) | |
1132 | ret |= MLX5_WOL_ARP; | |
1133 | ||
1134 | if (mode & WAKE_BCAST) | |
1135 | ret |= MLX5_WOL_BROADCAST; | |
1136 | ||
1137 | if (mode & WAKE_MCAST) | |
1138 | ret |= MLX5_WOL_MULTICAST; | |
1139 | ||
1140 | if (mode & WAKE_UCAST) | |
1141 | ret |= MLX5_WOL_UNICAST; | |
1142 | ||
1143 | if (mode & WAKE_PHY) | |
1144 | ret |= MLX5_WOL_PHY_ACTIVITY; | |
1145 | ||
1146 | return ret; | |
1147 | } | |
1148 | ||
1149 | static void mlx5e_get_wol(struct net_device *netdev, | |
1150 | struct ethtool_wolinfo *wol) | |
1151 | { | |
1152 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1153 | struct mlx5_core_dev *mdev = priv->mdev; | |
1154 | u8 mlx5_wol_mode; | |
1155 | int err; | |
1156 | ||
1157 | memset(wol, 0, sizeof(*wol)); | |
1158 | ||
1159 | wol->supported = mlx5e_get_wol_supported(mdev); | |
1160 | if (!wol->supported) | |
1161 | return; | |
1162 | ||
1163 | err = mlx5_query_port_wol(mdev, &mlx5_wol_mode); | |
1164 | if (err) | |
1165 | return; | |
1166 | ||
1167 | wol->wolopts = mlx5e_refomrat_wol_mode_mlx5_to_linux(mlx5_wol_mode); | |
1168 | } | |
1169 | ||
1170 | static int mlx5e_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) | |
1171 | { | |
1172 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1173 | struct mlx5_core_dev *mdev = priv->mdev; | |
1174 | __u32 wol_supported = mlx5e_get_wol_supported(mdev); | |
1175 | u32 mlx5_wol_mode; | |
1176 | ||
1177 | if (!wol_supported) | |
1178 | return -ENOTSUPP; | |
1179 | ||
1180 | if (wol->wolopts & ~wol_supported) | |
1181 | return -EINVAL; | |
1182 | ||
1183 | mlx5_wol_mode = mlx5e_refomrat_wol_mode_linux_to_mlx5(wol->wolopts); | |
1184 | ||
1185 | return mlx5_set_port_wol(mdev, mlx5_wol_mode); | |
1186 | } | |
1187 | ||
da54d24e GP |
1188 | static int mlx5e_set_phys_id(struct net_device *dev, |
1189 | enum ethtool_phys_id_state state) | |
1190 | { | |
1191 | struct mlx5e_priv *priv = netdev_priv(dev); | |
1192 | struct mlx5_core_dev *mdev = priv->mdev; | |
1193 | u16 beacon_duration; | |
1194 | ||
1195 | if (!MLX5_CAP_GEN(mdev, beacon_led)) | |
1196 | return -EOPNOTSUPP; | |
1197 | ||
1198 | switch (state) { | |
1199 | case ETHTOOL_ID_ACTIVE: | |
1200 | beacon_duration = MLX5_BEACON_DURATION_INF; | |
1201 | break; | |
1202 | case ETHTOOL_ID_INACTIVE: | |
1203 | beacon_duration = MLX5_BEACON_DURATION_OFF; | |
1204 | break; | |
1205 | default: | |
1206 | return -EOPNOTSUPP; | |
1207 | } | |
1208 | ||
1209 | return mlx5_set_port_beacon(mdev, beacon_duration); | |
1210 | } | |
1211 | ||
bb64143e GP |
1212 | static int mlx5e_get_module_info(struct net_device *netdev, |
1213 | struct ethtool_modinfo *modinfo) | |
1214 | { | |
1215 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1216 | struct mlx5_core_dev *dev = priv->mdev; | |
1217 | int size_read = 0; | |
1218 | u8 data[4]; | |
1219 | ||
1220 | size_read = mlx5_query_module_eeprom(dev, 0, 2, data); | |
1221 | if (size_read < 2) | |
1222 | return -EIO; | |
1223 | ||
1224 | /* data[0] = identifier byte */ | |
1225 | switch (data[0]) { | |
1226 | case MLX5_MODULE_ID_QSFP: | |
1227 | modinfo->type = ETH_MODULE_SFF_8436; | |
1228 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1229 | break; | |
1230 | case MLX5_MODULE_ID_QSFP_PLUS: | |
1231 | case MLX5_MODULE_ID_QSFP28: | |
1232 | /* data[1] = revision id */ | |
1233 | if (data[0] == MLX5_MODULE_ID_QSFP28 || data[1] >= 0x3) { | |
1234 | modinfo->type = ETH_MODULE_SFF_8636; | |
1235 | modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN; | |
1236 | } else { | |
1237 | modinfo->type = ETH_MODULE_SFF_8436; | |
1238 | modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN; | |
1239 | } | |
1240 | break; | |
1241 | case MLX5_MODULE_ID_SFP: | |
1242 | modinfo->type = ETH_MODULE_SFF_8472; | |
1243 | modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN; | |
1244 | break; | |
1245 | default: | |
1246 | netdev_err(priv->netdev, "%s: cable type not recognized:0x%x\n", | |
1247 | __func__, data[0]); | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | ||
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | static int mlx5e_get_module_eeprom(struct net_device *netdev, | |
1255 | struct ethtool_eeprom *ee, | |
1256 | u8 *data) | |
1257 | { | |
1258 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1259 | struct mlx5_core_dev *mdev = priv->mdev; | |
1260 | int offset = ee->offset; | |
1261 | int size_read; | |
1262 | int i = 0; | |
1263 | ||
1264 | if (!ee->len) | |
1265 | return -EINVAL; | |
1266 | ||
1267 | memset(data, 0, ee->len); | |
1268 | ||
1269 | while (i < ee->len) { | |
1270 | size_read = mlx5_query_module_eeprom(mdev, offset, ee->len - i, | |
1271 | data + i); | |
1272 | ||
1273 | if (!size_read) | |
1274 | /* Done reading */ | |
1275 | return 0; | |
1276 | ||
1277 | if (size_read < 0) { | |
1278 | netdev_err(priv->netdev, "%s: mlx5_query_eeprom failed:0x%x\n", | |
1279 | __func__, size_read); | |
1280 | return 0; | |
1281 | } | |
1282 | ||
1283 | i += size_read; | |
1284 | offset += size_read; | |
1285 | } | |
1286 | ||
1287 | return 0; | |
1288 | } | |
1289 | ||
4e59e288 GP |
1290 | typedef int (*mlx5e_pflag_handler)(struct net_device *netdev, bool enable); |
1291 | ||
9908aa29 | 1292 | static int set_pflag_rx_cqe_based_moder(struct net_device *netdev, bool enable) |
4e59e288 | 1293 | { |
9908aa29 TT |
1294 | struct mlx5e_priv *priv = netdev_priv(netdev); |
1295 | struct mlx5_core_dev *mdev = priv->mdev; | |
1296 | bool rx_mode_changed; | |
1297 | u8 rx_cq_period_mode; | |
1298 | int err = 0; | |
1299 | bool reset; | |
1300 | ||
1301 | rx_cq_period_mode = enable ? | |
1302 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE : | |
1303 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE; | |
1304 | rx_mode_changed = rx_cq_period_mode != priv->params.rx_cq_period_mode; | |
1305 | ||
1306 | if (rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE && | |
1307 | !MLX5_CAP_GEN(mdev, cq_period_start_from_cqe)) | |
1308 | return -ENOTSUPP; | |
1309 | ||
1310 | if (!rx_mode_changed) | |
1311 | return 0; | |
1312 | ||
1313 | reset = test_bit(MLX5E_STATE_OPENED, &priv->state); | |
1314 | if (reset) | |
1315 | mlx5e_close_locked(netdev); | |
1316 | ||
1317 | mlx5e_set_rx_cq_mode_params(&priv->params, rx_cq_period_mode); | |
1318 | ||
1319 | if (reset) | |
1320 | err = mlx5e_open_locked(netdev); | |
1321 | ||
1322 | return err; | |
4e59e288 GP |
1323 | } |
1324 | ||
1325 | static int mlx5e_handle_pflag(struct net_device *netdev, | |
1326 | u32 wanted_flags, | |
1327 | enum mlx5e_priv_flag flag, | |
1328 | mlx5e_pflag_handler pflag_handler) | |
1329 | { | |
1330 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1331 | bool enable = !!(wanted_flags & flag); | |
1332 | u32 changes = wanted_flags ^ priv->pflags; | |
1333 | int err; | |
1334 | ||
1335 | if (!(changes & flag)) | |
1336 | return 0; | |
1337 | ||
1338 | err = pflag_handler(netdev, enable); | |
1339 | if (err) { | |
1340 | netdev_err(netdev, "%s private flag 0x%x failed err %d\n", | |
1341 | enable ? "Enable" : "Disable", flag, err); | |
1342 | return err; | |
1343 | } | |
1344 | ||
1345 | MLX5E_SET_PRIV_FLAG(priv, flag, enable); | |
1346 | return 0; | |
1347 | } | |
1348 | ||
1349 | static int mlx5e_set_priv_flags(struct net_device *netdev, u32 pflags) | |
1350 | { | |
1351 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1352 | int err; | |
1353 | ||
1354 | mutex_lock(&priv->state_lock); | |
1355 | ||
9908aa29 TT |
1356 | err = mlx5e_handle_pflag(netdev, pflags, |
1357 | MLX5E_PFLAG_RX_CQE_BASED_MODER, | |
1358 | set_pflag_rx_cqe_based_moder); | |
4e59e288 GP |
1359 | |
1360 | mutex_unlock(&priv->state_lock); | |
1361 | return err ? -EINVAL : 0; | |
1362 | } | |
1363 | ||
1364 | static u32 mlx5e_get_priv_flags(struct net_device *netdev) | |
1365 | { | |
1366 | struct mlx5e_priv *priv = netdev_priv(netdev); | |
1367 | ||
1368 | return priv->pflags; | |
1369 | } | |
1370 | ||
f62b8bb8 AV |
1371 | const struct ethtool_ops mlx5e_ethtool_ops = { |
1372 | .get_drvinfo = mlx5e_get_drvinfo, | |
1373 | .get_link = ethtool_op_get_link, | |
1374 | .get_strings = mlx5e_get_strings, | |
1375 | .get_sset_count = mlx5e_get_sset_count, | |
1376 | .get_ethtool_stats = mlx5e_get_ethtool_stats, | |
1377 | .get_ringparam = mlx5e_get_ringparam, | |
1378 | .set_ringparam = mlx5e_set_ringparam, | |
1379 | .get_channels = mlx5e_get_channels, | |
1380 | .set_channels = mlx5e_set_channels, | |
1381 | .get_coalesce = mlx5e_get_coalesce, | |
1382 | .set_coalesce = mlx5e_set_coalesce, | |
665bc539 GP |
1383 | .get_link_ksettings = mlx5e_get_link_ksettings, |
1384 | .set_link_ksettings = mlx5e_set_link_ksettings, | |
2d75b2bc AS |
1385 | .get_rxfh_key_size = mlx5e_get_rxfh_key_size, |
1386 | .get_rxfh_indir_size = mlx5e_get_rxfh_indir_size, | |
2be6967c SM |
1387 | .get_rxfh = mlx5e_get_rxfh, |
1388 | .set_rxfh = mlx5e_set_rxfh, | |
2d75b2bc | 1389 | .get_rxnfc = mlx5e_get_rxnfc, |
58d52291 AS |
1390 | .get_tunable = mlx5e_get_tunable, |
1391 | .set_tunable = mlx5e_set_tunable, | |
3c2d18ef AS |
1392 | .get_pauseparam = mlx5e_get_pauseparam, |
1393 | .set_pauseparam = mlx5e_set_pauseparam, | |
ef9814de | 1394 | .get_ts_info = mlx5e_get_ts_info, |
da54d24e | 1395 | .set_phys_id = mlx5e_set_phys_id, |
928cfe87 TT |
1396 | .get_wol = mlx5e_get_wol, |
1397 | .set_wol = mlx5e_set_wol, | |
bb64143e GP |
1398 | .get_module_info = mlx5e_get_module_info, |
1399 | .get_module_eeprom = mlx5e_get_module_eeprom, | |
4e59e288 GP |
1400 | .get_priv_flags = mlx5e_get_priv_flags, |
1401 | .set_priv_flags = mlx5e_set_priv_flags | |
f62b8bb8 | 1402 | }; |