[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_common.c

/*
 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#include "en.h"
#include "lib/crypto.h"

/* mlx5e global resources should be placed in this file.
 * Global resources are common to all the netdevices created on the same nic.
 */

void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
{
	bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
	bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) ||
		       (pcie_relaxed_ordering_enabled(mdev->pdev) &&
			MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));

	MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_read);
	MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write);
}

int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey)
{
	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
	void *mkc;
	u32 *in;
	int err;

	in = kvzalloc(inlen, GFP_KERNEL);
	if (!in)
		return -ENOMEM;

	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
	MLX5_SET(mkc, mkc, lw, 1);
	MLX5_SET(mkc, mkc, lr, 1);
	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
	MLX5_SET(mkc, mkc, pd, pdn);
	MLX5_SET(mkc, mkc, length64, 1);
	MLX5_SET(mkc, mkc, qpn, 0xffffff);

	err = mlx5_core_create_mkey(mdev, mkey, in, inlen);

	kvfree(in);
	return err;
}

int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn)
{
	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);

	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);

	if (mlx5_lag_is_lacp_owner(mdev))
		MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);

	return mlx5_core_create_tis(mdev, in, tisn);
}

void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
{
	mlx5_core_destroy_tis(mdev, tisn);
}

static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
{
	int tc, i;

	for (i = 0; i < mlx5e_get_num_lag_ports(mdev); i++)
		for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++)
			mlx5e_destroy_tis(mdev, tisn[i][tc]);
}

static bool mlx5_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
{
	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
}

static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
{
	int tc, i;
	int err;

	for (i = 0; i < mlx5e_get_num_lag_ports(mdev); i++) {
		for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++) {
			u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
			void *tisc;

			tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);

			MLX5_SET(tisc, tisc, prio, tc << 1);

			if (mlx5_lag_should_assign_affinity(mdev))
				MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);

			err = mlx5e_create_tis(mdev, in, &tisn[i][tc]);
			if (err)
				goto err_close_tises;
		}
	}

	return 0;

err_close_tises:
	for (; i >= 0; i--) {
		for (tc--; tc >= 0; tc--)
			mlx5e_destroy_tis(mdev, tisn[i][tc]);
		tc = MLX5_MAX_NUM_TC;
	}

	return err;
}

int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises)
{
	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
	int err;

	err = mlx5_core_alloc_pd(mdev, &res->pdn);
	if (err) {
		mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
		return err;
	}

	err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
	if (err) {
		mlx5_core_err(mdev, "alloc td failed, %d\n", err);
		goto err_dealloc_pd;
	}

	err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
	if (err) {
		mlx5_core_err(mdev, "create mkey failed, %d\n", err);
		goto err_dealloc_transport_domain;
	}

	err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
	if (err) {
		mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
		goto err_destroy_mkey;
	}

	if (create_tises) {
		err = mlx5e_create_tises(mdev, res->tisn);
		if (err) {
			mlx5_core_err(mdev, "alloc tises failed, %d\n", err);
			goto err_destroy_bfreg;
		}
		res->tisn_valid = true;
	}

	INIT_LIST_HEAD(&res->td.tirs_list);
	mutex_init(&res->td.list_lock);

	mdev->mlx5e_res.dek_priv = mlx5_crypto_dek_init(mdev);
	if (IS_ERR(mdev->mlx5e_res.dek_priv)) {
		mlx5_core_err(mdev, "crypto dek init failed, %ld\n",
			      PTR_ERR(mdev->mlx5e_res.dek_priv));
		mdev->mlx5e_res.dek_priv = NULL;
	}

	return 0;

err_destroy_bfreg:
	mlx5_free_bfreg(mdev, &res->bfreg);
err_destroy_mkey:
	mlx5_core_destroy_mkey(mdev, res->mkey);
err_dealloc_transport_domain:
	mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
err_dealloc_pd:
	mlx5_core_dealloc_pd(mdev, res->pdn);
	return err;
}

void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
{
	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;

	mlx5_crypto_dek_cleanup(mdev->mlx5e_res.dek_priv);
	mdev->mlx5e_res.dek_priv = NULL;
	if (res->tisn_valid)
		mlx5e_destroy_tises(mdev, res->tisn);
	mlx5_free_bfreg(mdev, &res->bfreg);
	mlx5_core_destroy_mkey(mdev, res->mkey);
	mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
	mlx5_core_dealloc_pd(mdev, res->pdn);
	memset(res, 0, sizeof(*res));
}

int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
		       bool enable_mc_lb)
{
	struct mlx5_core_dev *mdev = priv->mdev;
	struct mlx5e_tir *tir;
	u8 lb_flags = 0;
	int err  = 0;
	u32 tirn = 0;
	int inlen;
	void *in;

	inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
	in = kvzalloc(inlen, GFP_KERNEL);
	if (!in)
		return -ENOMEM;

	if (enable_uc_lb)
		lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;

	if (enable_mc_lb)
		lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;

	if (lb_flags)
		MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);

	MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);

	mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
	list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
		tirn = tir->tirn;
		err = mlx5_core_modify_tir(mdev, tirn, in);
		if (err)
			break;
	}
	mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);

	kvfree(in);
	if (err)
		netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);

	return err;
}
Commit	Line	Data
b50d292b HHZ	1	/*
	2	* Copyright (c) 2016, Mellanox Technologies. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#include "en.h"
fe298bdf	34	#include "lib/crypto.h"
b50d292b HHZ	35
b50d292b HHZ	36	/* mlx5e global resources should be placed in this file.
39c538d6	37	* Global resources are common to all the netdevices created on the same nic.
b50d292b HHZ	38	*/
b50d292b HHZ	39
17347d54 AL	40	void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev mdev, void mkc)
17347d54 AL	41	{
17347d54	42	bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
bd4ba605 AH	43	bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) \|\|
	44	(pcie_relaxed_ordering_enabled(mdev->pdev) &&
	45	MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled));
17347d54	46
bd4ba605	47	MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_read);
ed4b0661	48	MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write);
17347d54 AL	49	}
17347d54 AL	50
0e1e03c0	51	int mlx5e_create_mkey(struct mlx5_core_dev mdev, u32 pdn, u32 mkey)
b50d292b	52	{
ec22eb53 SM	53	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
	54	void *mkc;
	55	u32 *in;
b50d292b HHZ	56	int err;
b50d292b HHZ	57
1b9a07ee	58	in = kvzalloc(inlen, GFP_KERNEL);
b50d292b HHZ	59	if (!in)
	60	return -ENOMEM;
	61
ec22eb53	62	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
cdbd0d2b	63	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
ec22eb53 SM	64	MLX5_SET(mkc, mkc, lw, 1);
ec22eb53 SM	65	MLX5_SET(mkc, mkc, lr, 1);
17347d54	66	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
ec22eb53 SM	67	MLX5_SET(mkc, mkc, pd, pdn);
	68	MLX5_SET(mkc, mkc, length64, 1);
	69	MLX5_SET(mkc, mkc, qpn, 0xffffff);
b50d292b	70
ec22eb53	71	err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
b50d292b	72
ec22eb53	73	kvfree(in);
b50d292b HHZ	74	return err;
	75	}
	76
b25bd37c TT	77	int mlx5e_create_tis(struct mlx5_core_dev mdev, void in, u32 *tisn)
	78	{
	79	void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
	80
	81	MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.hw_objs.td.tdn);
	82
	83	if (mlx5_lag_is_lacp_owner(mdev))
	84	MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
	85
	86	return mlx5_core_create_tis(mdev, in, tisn);
	87	}
	88
	89	void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
	90	{
	91	mlx5_core_destroy_tis(mdev, tisn);
	92	}
	93
	94	static void mlx5e_destroy_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
	95	{
	96	int tc, i;
	97
25461ce8	98	for (i = 0; i < mlx5e_get_num_lag_ports(mdev); i++)
b25bd37c TT	99	for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++)
	100	mlx5e_destroy_tis(mdev, tisn[i][tc]);
	101	}
	102
	103	static bool mlx5_lag_should_assign_affinity(struct mlx5_core_dev *mdev)
	104	{
	105	return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1;
	106	}
	107
	108	static int mlx5e_create_tises(struct mlx5_core_dev *mdev, u32 tisn[MLX5_MAX_PORTS][MLX5_MAX_NUM_TC])
	109	{
	110	int tc, i;
	111	int err;
	112
25461ce8	113	for (i = 0; i < mlx5e_get_num_lag_ports(mdev); i++) {
b25bd37c TT	114	for (tc = 0; tc < MLX5_MAX_NUM_TC; tc++) {
	115	u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {};
	116	void *tisc;
	117
	118	tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
	119
	120	MLX5_SET(tisc, tisc, prio, tc << 1);
	121
	122	if (mlx5_lag_should_assign_affinity(mdev))
	123	MLX5_SET(tisc, tisc, lag_tx_port_affinity, i + 1);
	124
	125	err = mlx5e_create_tis(mdev, in, &tisn[i][tc]);
	126	if (err)
	127	goto err_close_tises;
	128	}
	129	}
	130
	131	return 0;
	132
	133	err_close_tises:
	134	for (; i >= 0; i--) {
	135	for (tc--; tc >= 0; tc--)
	136	mlx5e_destroy_tis(mdev, tisn[i][tc]);
	137	tc = MLX5_MAX_NUM_TC;
	138	}
	139
	140	return err;
	141	}
	142
25461ce8	143	int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises)
b50d292b	144	{
c276aae8	145	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
b50d292b HHZ	146	int err;
b50d292b HHZ	147
b50d292b HHZ	148	err = mlx5_core_alloc_pd(mdev, &res->pdn);
	149	if (err) {
	150	mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
30aa60b3	151	return err;
b50d292b HHZ	152	}
	153
	154	err = mlx5_core_alloc_transport_domain(mdev, &res->td.tdn);
	155	if (err) {
	156	mlx5_core_err(mdev, "alloc td failed, %d\n", err);
	157	goto err_dealloc_pd;
	158	}
	159
	160	err = mlx5e_create_mkey(mdev, res->pdn, &res->mkey);
	161	if (err) {
	162	mlx5_core_err(mdev, "create mkey failed, %d\n", err);
	163	goto err_dealloc_transport_domain;
	164	}
	165
aff26157 SM	166	err = mlx5_alloc_bfreg(mdev, &res->bfreg, false, false);
	167	if (err) {
	168	mlx5_core_err(mdev, "alloc bfreg failed, %d\n", err);
	169	goto err_destroy_mkey;
	170	}
	171
25461ce8 SM	172	if (create_tises) {
	173	err = mlx5e_create_tises(mdev, res->tisn);
	174	if (err) {
	175	mlx5_core_err(mdev, "alloc tises failed, %d\n", err);
	176	goto err_destroy_bfreg;
	177	}
	178	res->tisn_valid = true;
b25bd37c	179	}
25461ce8	180
c276aae8 RD	181	INIT_LIST_HEAD(&res->td.tirs_list);
c276aae8 RD	182	mutex_init(&res->td.list_lock);
724b2aa1	183
fe298bdf JL	184	mdev->mlx5e_res.dek_priv = mlx5_crypto_dek_init(mdev);
	185	if (IS_ERR(mdev->mlx5e_res.dek_priv)) {
	186	mlx5_core_err(mdev, "crypto dek init failed, %ld\n",
	187	PTR_ERR(mdev->mlx5e_res.dek_priv));
	188	mdev->mlx5e_res.dek_priv = NULL;
	189	}
	190
b50d292b HHZ	191	return 0;
b50d292b HHZ	192
b25bd37c TT	193	err_destroy_bfreg:
b25bd37c TT	194	mlx5_free_bfreg(mdev, &res->bfreg);
aff26157	195	err_destroy_mkey:
83fec3f1	196	mlx5_core_destroy_mkey(mdev, res->mkey);
b50d292b HHZ	197	err_dealloc_transport_domain:
	198	mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
	199	err_dealloc_pd:
	200	mlx5_core_dealloc_pd(mdev, res->pdn);
b50d292b HHZ	201	return err;
	202	}
	203
	204	void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev)
	205	{
c276aae8	206	struct mlx5e_hw_objs *res = &mdev->mlx5e_res.hw_objs;
b50d292b	207
fe298bdf JL	208	mlx5_crypto_dek_cleanup(mdev->mlx5e_res.dek_priv);
fe298bdf JL	209	mdev->mlx5e_res.dek_priv = NULL;
25461ce8 SM	210	if (res->tisn_valid)
25461ce8 SM	211	mlx5e_destroy_tises(mdev, res->tisn);
aff26157	212	mlx5_free_bfreg(mdev, &res->bfreg);
83fec3f1	213	mlx5_core_destroy_mkey(mdev, res->mkey);
b50d292b HHZ	214	mlx5_core_dealloc_transport_domain(mdev, res->td.tdn);
b50d292b HHZ	215	mlx5_core_dealloc_pd(mdev, res->pdn);
b5ae5777	216	memset(res, 0, sizeof(*res));
b50d292b	217	}
724b2aa1	218
80639b19 ES	219	int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
80639b19 ES	220	bool enable_mc_lb)
724b2aa1	221	{
b676f653	222	struct mlx5_core_dev *mdev = priv->mdev;
724b2aa1	223	struct mlx5e_tir *tir;
80639b19	224	u8 lb_flags = 0;
bc87a003	225	int err = 0;
b676f653	226	u32 tirn = 0;
724b2aa1	227	int inlen;
b676f653 SM	228	void *in;
b676f653 SM	229
724b2aa1	230	inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1b9a07ee	231	in = kvzalloc(inlen, GFP_KERNEL);
b6193d70 SM	232	if (!in)
b6193d70 SM	233	return -ENOMEM;
724b2aa1	234
0952da79	235	if (enable_uc_lb)
80639b19 ES	236	lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
	237
	238	if (enable_mc_lb)
	239	lb_flags \|= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
	240
	241	if (lb_flags)
	242	MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
0952da79	243
724b2aa1 HHZ	244	MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
724b2aa1 HHZ	245
c276aae8 RD	246	mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock);
c276aae8 RD	247	list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) {
b676f653	248	tirn = tir->tirn;
e0b4b472	249	err = mlx5_core_modify_tir(mdev, tirn, in);
724b2aa1	250	if (err)
b6193d70	251	break;
724b2aa1	252	}
b6193d70	253	mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock);
724b2aa1 HHZ	254
724b2aa1 HHZ	255	kvfree(in);
b676f653 SM	256	if (err)
b676f653 SM	257	netdev_err(priv->netdev, "refresh tir(0x%x) failed, %d\n", tirn, err);
724b2aa1	258
bf50082c	259	return err;
724b2aa1	260	}