Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
48935bbb | 39 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 46 | #include <linux/mlx5/fs.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
18a2b7f9 | 48 | #include <net/udp_tunnel.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4f75da36 | 51 | #include <linux/dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
3f3ab178 | 56 | #include "en/dcbnl.h" |
fe6d86b3 | 57 | #include "en/fs.h" |
214baf22 | 58 | #include "en/qos.h" |
cef35af3 | 59 | #include "lib/hv_vhca.h" |
432119de | 60 | #include "lib/clock.h" |
3f22d6c7 | 61 | #include "en/rx_res.h" |
8bf30be7 | 62 | #include "en/selq.h" |
846122b1 | 63 | #include "lib/sd.h" |
f62b8bb8 | 64 | |
4d8fcf21 | 65 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
66 | struct page_pool; |
67 | ||
bb909416 IL |
68 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
69 | #define MLX5E_METADATA_ETHER_LEN 8 | |
70 | ||
c139dbfd ES |
71 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
72 | ||
472a1e44 TT |
73 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
74 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 75 | |
ec60c458 | 76 | #define MLX5E_MAX_NUM_MQPRIO_CH_TC TC_QOPT_MAX_QUEUE |
f62b8bb8 | 77 | |
1bfecfca | 78 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
79 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
80 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 81 | |
94816278 | 82 | #define MLX5E_RX_MAX_HEAD (256) |
758191c9 | 83 | #define MLX5E_SHAMPO_LOG_HEADER_ENTRY_SIZE (8) |
e5ca8fb0 BBI |
84 | #define MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE (9) |
85 | #define MLX5E_SHAMPO_WQ_HEADER_PER_PAGE (PAGE_SIZE >> MLX5E_SHAMPO_LOG_MAX_HEADER_ENTRY_SIZE) | |
86 | #define MLX5E_SHAMPO_WQ_BASE_HEAD_ENTRY_SIZE (64) | |
87 | #define MLX5E_SHAMPO_WQ_RESRV_SIZE (64 * 1024) | |
88 | #define MLX5E_SHAMPO_WQ_BASE_RESRV_SIZE (4096) | |
94816278 | 89 | |
f32f5bd2 DJ |
90 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
91 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
92 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
93 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
94 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
95 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 96 | |
e5a3cc83 MM |
97 | #define MLX5_MPWRQ_MAX_LOG_WQE_SZ 18 |
98 | ||
99 | /* Keep in sync with mlx5e_mpwrq_log_wqe_sz. | |
100 | * These are theoretical maximums, which can be further restricted by | |
101 | * capabilities. These values are used for static resource allocations and | |
102 | * sanity checks. | |
103 | * MLX5_SEND_WQE_MAX_SIZE is a bit bigger than the maximum cacheline-aligned WQE | |
104 | * size actually used at runtime, but it's not a problem when calculating static | |
105 | * array sizes. | |
106 | */ | |
02648b4b | 107 | #define MLX5_UMR_MAX_FLEX_SPACE \ |
e5a3cc83 | 108 | (ALIGN_DOWN(MLX5_SEND_WQE_MAX_SIZE - sizeof(struct mlx5e_umr_wqe), \ |
02648b4b | 109 | MLX5_UMR_FLEX_ALIGNMENT)) |
e5a3cc83 | 110 | #define MLX5_MPWRQ_MAX_PAGES_PER_WQE \ |
02648b4b | 111 | rounddown_pow_of_two(MLX5_UMR_MAX_FLEX_SPACE / sizeof(struct mlx5_mtt)) |
fe4c988b | 112 | |
73281b78 | 113 | #define MLX5E_MAX_RQ_NUM_MTTS \ |
9f123f74 | 114 | (ALIGN_DOWN(U16_MAX, 4) * 2) /* Fits into u16 and aligned by WQEBB. */ |
6470d2e7 | 115 | #define MLX5E_MAX_RQ_NUM_KSMS (U16_MAX - 1) /* So that num_ksms fits into u16. */ |
73281b78 | 116 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) |
73281b78 | 117 | |
069d1146 TT |
118 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
119 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
120 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
121 | ||
73281b78 TT |
122 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
123 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
124 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
125 | ||
069d1146 | 126 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 | 127 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
e5a3cc83 | 128 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd |
73281b78 TT |
129 | |
130 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 131 | |
2b029556 | 132 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
ab6013a5 | 133 | #define MLX5E_DEFAULT_SHAMPO_TIMEOUT 1024 |
2b029556 | 134 | |
f62b8bb8 | 135 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 136 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
137 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
138 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 139 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
140 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
141 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 142 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 143 | |
b4e029da | 144 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
6dd6eaf4 | 145 | #define MLX5E_MAX_NUM_CHANNELS 256 |
f62b8bb8 | 146 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db05815b | 147 | #define MLX5E_TX_XSK_POLL_BUDGET 64 |
db75373c | 148 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 149 | |
214baf22 MM |
150 | #define mlx5e_state_dereference(priv, p) \ |
151 | rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) | |
152 | ||
82f9378c PH |
153 | enum mlx5e_devcom_events { |
154 | MPV_DEVCOM_MASTER_UP, | |
155 | MPV_DEVCOM_MASTER_DOWN, | |
156 | MPV_DEVCOM_IPSEC_MASTER_UP, | |
157 | MPV_DEVCOM_IPSEC_MASTER_DOWN, | |
158 | }; | |
159 | ||
45f171b1 MM |
160 | static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) |
161 | { | |
162 | if (mlx5_lag_is_lacp_owner(mdev)) | |
163 | return 1; | |
164 | ||
165 | return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); | |
166 | } | |
167 | ||
461017cb TT |
168 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
169 | { | |
170 | switch (wq_type) { | |
171 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
172 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
173 | wq_size / 2); | |
174 | default: | |
175 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
176 | wq_size / 2); | |
177 | } | |
178 | } | |
179 | ||
779d986d | 180 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
181 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
182 | { | |
183 | return is_kdump_kernel() ? | |
184 | MLX5E_MIN_NUM_CHANNELS : | |
74a8dada AF |
185 | min3(mlx5_comp_vectors_max(mdev), (u32)MLX5E_MAX_NUM_CHANNELS, |
186 | (u32)(1 << MLX5_CAP_GEN(mdev, log_max_rqt_size))); | |
48935bbb SM |
187 | } |
188 | ||
c27bd171 AL |
189 | /* The maximum WQE size can be retrieved by max_wqe_sz_sq in |
190 | * bytes units. Driver hardens the limitation to 1KB (16 | |
191 | * WQEBBs), unless firmware capability is stricter. | |
192 | */ | |
f060ccc2 | 193 | static inline u8 mlx5e_get_max_sq_wqebbs(struct mlx5_core_dev *mdev) |
c27bd171 | 194 | { |
f060ccc2 MM |
195 | BUILD_BUG_ON(MLX5_SEND_WQE_MAX_WQEBBS > U8_MAX); |
196 | ||
197 | return (u8)min_t(u16, MLX5_SEND_WQE_MAX_WQEBBS, | |
198 | MLX5_CAP_GEN(mdev, max_wqe_sz_sq) / MLX5_SEND_WQE_BB); | |
c27bd171 AL |
199 | } |
200 | ||
ed5c92ff | 201 | static inline u8 mlx5e_get_max_sq_aligned_wqebbs(struct mlx5_core_dev *mdev) |
76c31e5f AL |
202 | { |
203 | /* The return value will be multiplied by MLX5_SEND_WQEBB_NUM_DS. | |
204 | * Since max_sq_wqebbs may be up to MLX5_SEND_WQE_MAX_WQEBBS == 16, | |
205 | * see mlx5e_get_max_sq_wqebbs(), the multiplication (16 * 4 == 64) | |
206 | * overflows the 6-bit DS field of Ctrl Segment. Use a bound lower | |
207 | * than MLX5_SEND_WQE_MAX_WQEBBS to let a full-session WQE be | |
208 | * cache-aligned. | |
209 | */ | |
ed5c92ff | 210 | u8 wqebbs = mlx5e_get_max_sq_wqebbs(mdev); |
677e78c8 | 211 | |
ed5c92ff | 212 | wqebbs = min_t(u8, wqebbs, MLX5_SEND_WQE_MAX_WQEBBS - 1); |
677e78c8 MM |
213 | #if L1_CACHE_BYTES >= 128 |
214 | wqebbs = ALIGN_DOWN(wqebbs, 2); | |
76c31e5f | 215 | #endif |
677e78c8 | 216 | return wqebbs; |
76c31e5f AL |
217 | } |
218 | ||
2f48af12 TT |
219 | struct mlx5e_tx_wqe { |
220 | struct mlx5_wqe_ctrl_seg ctrl; | |
7d0d0d86 | 221 | struct mlx5_wqe_eth_seg eth; |
ad518573 | 222 | struct mlx5_wqe_data_seg data[]; |
2f48af12 TT |
223 | }; |
224 | ||
99cbfa93 | 225 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 226 | struct mlx5_wqe_srq_next_seg next; |
339ffae5 | 227 | struct mlx5_wqe_data_seg data[]; |
99cbfa93 TT |
228 | }; |
229 | ||
230 | struct mlx5e_rx_wqe_cyc { | |
7bd1099c | 231 | DECLARE_FLEX_ARRAY(struct mlx5_wqe_data_seg, data); |
2f48af12 | 232 | }; |
86d722ad | 233 | |
bc77b240 TT |
234 | struct mlx5e_umr_wqe { |
235 | struct mlx5_wqe_ctrl_seg ctrl; | |
236 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
237 | struct mlx5_mkey_seg mkc; | |
d7b896ac | 238 | union { |
ad518573 KC |
239 | DECLARE_FLEX_ARRAY(struct mlx5_mtt, inline_mtts); |
240 | DECLARE_FLEX_ARRAY(struct mlx5_klm, inline_klms); | |
6470d2e7 | 241 | DECLARE_FLEX_ARRAY(struct mlx5_ksm, inline_ksms); |
d7b896ac | 242 | }; |
bc77b240 TT |
243 | }; |
244 | ||
4e59e288 | 245 | enum mlx5e_priv_flag { |
8ff57c18 TT |
246 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
247 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
248 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
249 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
250 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 251 | MLX5E_PFLAG_XDP_TX_MPWQE, |
5af75c74 | 252 | MLX5E_PFLAG_SKB_TX_MPWQE, |
145e5637 | 253 | MLX5E_PFLAG_TX_PORT_TS, |
8ff57c18 | 254 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
255 | }; |
256 | ||
6a9764ef | 257 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
258 | do { \ |
259 | if (enable) \ | |
8ff57c18 | 260 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 261 | else \ |
8ff57c18 | 262 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
263 | } while (0) |
264 | ||
8ff57c18 | 265 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 266 | |
eaee12f0 KM |
267 | enum packet_merge { |
268 | MLX5E_PACKET_MERGE_NONE, | |
269 | MLX5E_PACKET_MERGE_LRO, | |
270 | MLX5E_PACKET_MERGE_SHAMPO, | |
271 | }; | |
272 | ||
273 | struct mlx5e_packet_merge_param { | |
274 | enum packet_merge type; | |
275 | u32 timeout; | |
e5ca8fb0 BBI |
276 | struct { |
277 | u8 match_criteria_type; | |
278 | u8 alignment_granularity; | |
279 | } shampo; | |
eaee12f0 KM |
280 | }; |
281 | ||
f62b8bb8 AV |
282 | struct mlx5e_params { |
283 | u8 log_sq_size; | |
461017cb | 284 | u8 rq_wq_type; |
73281b78 | 285 | u8 log_rq_mtu_frames; |
f62b8bb8 | 286 | u16 num_channels; |
86d747a3 | 287 | struct { |
e2aeac44 | 288 | u16 mode; |
86d747a3 | 289 | u8 num_tc; |
7dbc849b | 290 | struct netdev_tc_txq tc_to_txq[TC_MAX_QUEUE]; |
80743c4f | 291 | struct { |
0bb7228f MT |
292 | u64 max_rate[TC_MAX_QUEUE]; |
293 | u32 hw_id[TC_MAX_QUEUE]; | |
80743c4f | 294 | } channel; |
86d747a3 | 295 | } mqprio; |
9bcc8606 | 296 | bool rx_cqe_compress_def; |
8960b389 TG |
297 | struct dim_cq_moder rx_cq_moderation; |
298 | struct dim_cq_moder tx_cq_moderation; | |
eaee12f0 | 299 | struct mlx5e_packet_merge_param packet_merge; |
cff92d7c | 300 | u8 tx_min_inline_mode; |
36350114 | 301 | bool vlan_strip_disable; |
102722fc | 302 | bool scatter_fcs_en; |
9a317425 | 303 | bool rx_dim_enabled; |
cbce4f44 | 304 | bool tx_dim_enabled; |
445a25f6 RR |
305 | bool rx_moder_use_cqe_mode; |
306 | bool tx_moder_use_cqe_mode; | |
59ece1c9 | 307 | u32 pflags; |
6a9764ef | 308 | struct bpf_prog *xdp_prog; |
db05815b | 309 | struct mlx5e_xsk *xsk; |
472a1e44 TT |
310 | unsigned int sw_mtu; |
311 | int hard_mtu; | |
960fbfe2 | 312 | bool ptp_rx; |
1db1f21c | 313 | __be32 terminate_lkey_be; |
f62b8bb8 AV |
314 | }; |
315 | ||
86d747a3 TT |
316 | static inline u8 mlx5e_get_dcb_num_tc(struct mlx5e_params *params) |
317 | { | |
e2aeac44 TT |
318 | return params->mqprio.mode == TC_MQPRIO_MODE_DCB ? |
319 | params->mqprio.num_tc : 1; | |
86d747a3 TT |
320 | } |
321 | ||
1fe7bc10 AF |
322 | /* Keep this enum consistent with the corresponding strings array |
323 | * declared in en/reporter_rx.c | |
324 | */ | |
f62b8bb8 | 325 | enum { |
1fe7bc10 | 326 | MLX5E_RQ_STATE_ENABLED = 0, |
8276ea13 | 327 | MLX5E_RQ_STATE_RECOVERING, |
2b5bd5b1 | 328 | MLX5E_RQ_STATE_DIM, |
b856df28 | 329 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
db849faa | 330 | MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ |
e5ca8fb0 BBI |
331 | MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX, /* set when mini_cqe_resp_stride_index cap is used */ |
332 | MLX5E_RQ_STATE_SHAMPO, /* set when SHAMPO cap is used */ | |
2c925db0 | 333 | MLX5E_RQ_STATE_MINI_CQE_ENHANCED, /* set when enhanced mini_cqe_cap is used */ |
bb76d250 | 334 | MLX5E_RQ_STATE_XSK, /* set to indicate an xsk rq */ |
1fe7bc10 | 335 | MLX5E_NUM_RQ_STATES, /* Must be kept last */ |
f62b8bb8 AV |
336 | }; |
337 | ||
f62b8bb8 AV |
338 | struct mlx5e_cq { |
339 | /* data path - accessed per cqe */ | |
340 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
341 | |
342 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 343 | u16 event_ctr; |
f62b8bb8 AV |
344 | struct napi_struct *napi; |
345 | struct mlx5_core_cq mcq; | |
4d0b7ef9 | 346 | struct mlx5e_ch_stats *ch_stats; |
f62b8bb8 | 347 | |
79d356ef | 348 | /* control */ |
4d0b7ef9 | 349 | struct net_device *netdev; |
79d356ef | 350 | struct mlx5_core_dev *mdev; |
db52aa6d | 351 | struct workqueue_struct *workqueue; |
79d356ef TT |
352 | struct mlx5_wq_ctrl wq_ctrl; |
353 | } ____cacheline_aligned_in_smp; | |
354 | ||
355 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
356 | /* cqe decompression */ |
357 | struct mlx5_cqe64 title; | |
358 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
359 | u8 mini_arr_idx; | |
79d356ef TT |
360 | u16 left; |
361 | u16 wqe_counter; | |
2c925db0 | 362 | bool last_cqe_title; |
f62b8bb8 AV |
363 | } ____cacheline_aligned_in_smp; |
364 | ||
eba2db2b SM |
365 | enum mlx5e_dma_map_type { |
366 | MLX5E_DMA_MAP_SINGLE, | |
367 | MLX5E_DMA_MAP_PAGE | |
368 | }; | |
369 | ||
370 | struct mlx5e_sq_dma { | |
371 | dma_addr_t addr; | |
372 | u32 size; | |
373 | enum mlx5e_dma_map_type type; | |
374 | }; | |
375 | ||
fc9d982a AF |
376 | /* Keep this enum consistent with with the corresponding strings array |
377 | * declared in en/reporter_tx.c | |
378 | */ | |
eba2db2b | 379 | enum { |
fc9d982a | 380 | MLX5E_SQ_STATE_ENABLED = 0, |
5af75c74 | 381 | MLX5E_SQ_STATE_MPWQE, |
db75373c | 382 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 383 | MLX5E_SQ_STATE_IPSEC, |
2b5bd5b1 | 384 | MLX5E_SQ_STATE_DIM, |
b431302e | 385 | MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, |
e7e0004a | 386 | MLX5E_SQ_STATE_PENDING_XSK_TX, |
e9ce991b | 387 | MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, |
9ded70fa | 388 | MLX5E_SQ_STATE_XDP_MULTIBUF, |
fc9d982a | 389 | MLX5E_NUM_SQ_STATES, /* Must be kept last */ |
eba2db2b SM |
390 | }; |
391 | ||
b39fe61e MM |
392 | struct mlx5e_tx_mpwqe { |
393 | /* Current MPWQE session */ | |
394 | struct mlx5e_tx_wqe *wqe; | |
5af75c74 | 395 | u32 bytes_count; |
b39fe61e MM |
396 | u8 ds_count; |
397 | u8 pkt_count; | |
398 | u8 inline_on; | |
399 | }; | |
400 | ||
0b676aae EBE |
401 | struct mlx5e_skb_fifo { |
402 | struct sk_buff **fifo; | |
403 | u16 *pc; | |
404 | u16 *cc; | |
405 | u16 mask; | |
406 | }; | |
407 | ||
145e5637 EBE |
408 | struct mlx5e_ptpsq; |
409 | ||
31391048 | 410 | struct mlx5e_txqsq { |
eba2db2b SM |
411 | /* data path */ |
412 | ||
413 | /* dirtied @completion */ | |
414 | u16 cc; | |
338c46c6 | 415 | u16 skb_fifo_cc; |
eba2db2b | 416 | u32 dma_fifo_cc; |
a5e89a3f | 417 | struct dim *dim; /* Adaptive Moderation */ |
eba2db2b SM |
418 | |
419 | /* dirtied @xmit */ | |
420 | u16 pc ____cacheline_aligned_in_smp; | |
338c46c6 | 421 | u16 skb_fifo_pc; |
eba2db2b | 422 | u32 dma_fifo_pc; |
5af75c74 | 423 | struct mlx5e_tx_mpwqe mpwqe; |
eba2db2b SM |
424 | |
425 | struct mlx5e_cq cq; | |
426 | ||
eba2db2b SM |
427 | /* read only */ |
428 | struct mlx5_wq_cyc wq; | |
429 | u32 dma_fifo_mask; | |
05909bab | 430 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
431 | struct { |
432 | struct mlx5e_sq_dma *dma_fifo; | |
0b676aae | 433 | struct mlx5e_skb_fifo skb_fifo; |
9a3956da TT |
434 | struct mlx5e_tx_wqe_info *wqe_info; |
435 | } db; | |
eba2db2b SM |
436 | void __iomem *uar_map; |
437 | struct netdev_queue *txq; | |
438 | u32 sqn; | |
01614d4f | 439 | u16 stop_room; |
677e78c8 | 440 | u8 max_sq_mpw_wqebbs; |
eba2db2b | 441 | u8 min_inline_mode; |
eba2db2b | 442 | struct device *pdev; |
eba2db2b SM |
443 | __be32 mkey_be; |
444 | unsigned long state; | |
84d1bb2b | 445 | unsigned int hw_mtu; |
7c39afb3 | 446 | struct mlx5_clock *clock; |
4ad40d8e EBE |
447 | struct net_device *netdev; |
448 | struct mlx5_core_dev *mdev; | |
79efecb4 | 449 | struct mlx5e_channel *channel; |
4ad40d8e | 450 | struct mlx5e_priv *priv; |
eba2db2b SM |
451 | |
452 | /* control path */ | |
453 | struct mlx5_wq_ctrl wq_ctrl; | |
57c70d87 | 454 | int ch_ix; |
acc6c595 | 455 | int txq_ix; |
eba2db2b | 456 | u32 rate_limit; |
de8650a8 | 457 | struct work_struct recover_work; |
145e5637 | 458 | struct mlx5e_ptpsq *ptpsq; |
432119de | 459 | cqe_ts_to_ns ptp_cyc2time; |
31391048 SM |
460 | } ____cacheline_aligned_in_smp; |
461 | ||
fea28dd6 | 462 | struct mlx5e_xdp_info_fifo { |
3f734b8c | 463 | union mlx5e_xdp_info *xi; |
fea28dd6 TT |
464 | u32 *cc; |
465 | u32 *pc; | |
466 | u32 mask; | |
467 | }; | |
468 | ||
5e0d2eef | 469 | struct mlx5e_xdpsq; |
e32654f1 | 470 | struct mlx5e_xmit_data; |
ec706a86 | 471 | struct xsk_tx_metadata; |
db05815b | 472 | typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); |
d963fa15 | 473 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, |
b39fe61e | 474 | struct mlx5e_xmit_data *, |
ec706a86 SF |
475 | int, |
476 | struct xsk_tx_metadata *); | |
d963fa15 | 477 | |
31391048 SM |
478 | struct mlx5e_xdpsq { |
479 | /* data path */ | |
480 | ||
dac0d15f | 481 | /* dirtied @completion */ |
fea28dd6 | 482 | u32 xdpi_fifo_cc; |
31391048 | 483 | u16 cc; |
31391048 | 484 | |
dac0d15f | 485 | /* dirtied @xmit */ |
fea28dd6 TT |
486 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
487 | u16 pc; | |
b8180392 | 488 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
b39fe61e | 489 | struct mlx5e_tx_mpwqe mpwqe; |
31391048 | 490 | |
dac0d15f | 491 | struct mlx5e_cq cq; |
31391048 SM |
492 | |
493 | /* read only */ | |
1742b3d5 | 494 | struct xsk_buff_pool *xsk_pool; |
31391048 | 495 | struct mlx5_wq_cyc wq; |
890388ad | 496 | struct mlx5e_xdpsq_stats *stats; |
db05815b | 497 | mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; |
5e0d2eef | 498 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 499 | struct { |
1feeab80 | 500 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 501 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 502 | } db; |
31391048 SM |
503 | void __iomem *uar_map; |
504 | u32 sqn; | |
505 | struct device *pdev; | |
506 | __be32 mkey_be; | |
c27bd171 | 507 | u16 stop_room; |
677e78c8 | 508 | u8 max_sq_mpw_wqebbs; |
31391048 SM |
509 | u8 min_inline_mode; |
510 | unsigned long state; | |
c94e4f11 | 511 | unsigned int hw_mtu; |
31391048 SM |
512 | |
513 | /* control path */ | |
514 | struct mlx5_wq_ctrl wq_ctrl; | |
515 | struct mlx5e_channel *channel; | |
516 | } ____cacheline_aligned_in_smp; | |
517 | ||
e9ce991b TT |
518 | struct mlx5e_ktls_resync_resp; |
519 | ||
31391048 SM |
520 | struct mlx5e_icosq { |
521 | /* data path */ | |
fd9b4be8 TT |
522 | u16 cc; |
523 | u16 pc; | |
31391048 | 524 | |
fd9b4be8 | 525 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
526 | struct mlx5e_cq cq; |
527 | ||
528 | /* write@xmit, read@completion */ | |
529 | struct { | |
7d42c8e9 | 530 | struct mlx5e_icosq_wqe_info *wqe_info; |
31391048 SM |
531 | } db; |
532 | ||
533 | /* read only */ | |
534 | struct mlx5_wq_cyc wq; | |
535 | void __iomem *uar_map; | |
536 | u32 sqn; | |
3ff3874f | 537 | u16 reserved_room; |
31391048 | 538 | unsigned long state; |
e9ce991b | 539 | struct mlx5e_ktls_resync_resp *ktls_resync; |
31391048 SM |
540 | |
541 | /* control path */ | |
542 | struct mlx5_wq_ctrl wq_ctrl; | |
543 | struct mlx5e_channel *channel; | |
be5323c8 AL |
544 | |
545 | struct work_struct recover_work; | |
eba2db2b SM |
546 | } ____cacheline_aligned_in_smp; |
547 | ||
6f574284 DT |
548 | struct mlx5e_frag_page { |
549 | struct page *page; | |
550 | u16 frags; | |
551 | }; | |
552 | ||
625dff29 DT |
553 | enum mlx5e_wqe_frag_flag { |
554 | MLX5E_WQE_FRAG_LAST_IN_PAGE, | |
3f93f829 | 555 | MLX5E_WQE_FRAG_SKIP_RELEASE, |
625dff29 DT |
556 | }; |
557 | ||
accd5883 | 558 | struct mlx5e_wqe_frag_info { |
8fb1814f | 559 | union { |
6f574284 | 560 | struct mlx5e_frag_page *frag_page; |
8fb1814f DT |
561 | struct xdp_buff **xskp; |
562 | }; | |
accd5883 | 563 | u32 offset; |
625dff29 | 564 | u8 flags; |
accd5883 TT |
565 | }; |
566 | ||
8fb1814f | 567 | union mlx5e_alloc_units { |
6f574284 | 568 | DECLARE_FLEX_ARRAY(struct mlx5e_frag_page, frag_pages); |
8fb1814f DT |
569 | DECLARE_FLEX_ARRAY(struct page *, pages); |
570 | DECLARE_FLEX_ARRAY(struct xdp_buff *, xsk_buffs); | |
571 | }; | |
572 | ||
eba2db2b | 573 | struct mlx5e_mpw_info { |
eba2db2b | 574 | u16 consumed_strides; |
38a36efc | 575 | DECLARE_BITMAP(skip_release_bitmap, MLX5_MPWRQ_MAX_PAGES_PER_WQE); |
f52ac702 | 576 | struct mlx5e_frag_page linear_page; |
d39092ca | 577 | union mlx5e_alloc_units alloc_units; |
eba2db2b SM |
578 | }; |
579 | ||
069d1146 TT |
580 | #define MLX5E_MAX_RX_FRAGS 4 |
581 | ||
eba2db2b SM |
582 | struct mlx5e_rq; |
583 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
584 | typedef struct sk_buff * |
585 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
bc8d405b THJ |
586 | struct mlx5_cqe64 *cqe, u16 cqe_bcnt, |
587 | u32 head_offset, u32 page_idx); | |
069d1146 | 588 | typedef struct sk_buff * |
84a137f0 | 589 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5e_wqe_frag_info *wi, |
bc8d405b | 590 | struct mlx5_cqe64 *cqe, u32 cqe_bcnt); |
7cc6d77b | 591 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b | 592 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
e5ca8fb0 | 593 | typedef void (*mlx5e_fp_shampo_dealloc_hd)(struct mlx5e_rq*, u16, u16, bool); |
eba2db2b | 594 | |
5adf4c47 | 595 | int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); |
5543e989 | 596 | void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); |
5adf4c47 | 597 | |
121e8927 | 598 | enum mlx5e_rq_flag { |
f03590f7 | 599 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 600 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
601 | }; |
602 | ||
069d1146 TT |
603 | struct mlx5e_rq_frag_info { |
604 | int frag_size; | |
605 | int frag_stride; | |
606 | }; | |
607 | ||
608 | struct mlx5e_rq_frags_info { | |
609 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
610 | u8 num_frags; | |
611 | u8 log_num_frags; | |
4ba2b498 | 612 | u16 wqe_bulk; |
cd640b05 | 613 | u16 refill_unit; |
a064c609 | 614 | u8 wqe_index_mask; |
069d1146 TT |
615 | }; |
616 | ||
79008676 MM |
617 | struct mlx5e_dma_info { |
618 | dma_addr_t addr; | |
ca6ef9f0 | 619 | union { |
6f574284 | 620 | struct mlx5e_frag_page *frag_page; |
ca6ef9f0 DT |
621 | struct page *page; |
622 | }; | |
79008676 MM |
623 | }; |
624 | ||
e5ca8fb0 | 625 | struct mlx5e_shampo_hd { |
573bce9e | 626 | u32 mkey; |
e5ca8fb0 | 627 | struct mlx5e_dma_info *info; |
6f574284 | 628 | struct mlx5e_frag_page *pages; |
ca6ef9f0 | 629 | u16 curr_page_index; |
e5ca8fb0 BBI |
630 | u16 hd_per_wq; |
631 | u16 hd_per_wqe; | |
632 | unsigned long *bitmap; | |
633 | u16 pi; | |
634 | u16 ci; | |
635 | __be32 key; | |
636 | u64 last_addr; | |
637 | }; | |
638 | ||
92552d3a KM |
639 | struct mlx5e_hw_gro_data { |
640 | struct sk_buff *skb; | |
641 | struct flow_keys fk; | |
642 | int second_ip_id; | |
643 | }; | |
644 | ||
168723c1 MM |
645 | enum mlx5e_mpwrq_umr_mode { |
646 | MLX5E_MPWRQ_UMR_MODE_ALIGNED, | |
647 | MLX5E_MPWRQ_UMR_MODE_UNALIGNED, | |
13921345 | 648 | MLX5E_MPWRQ_UMR_MODE_OVERSIZED, |
c2c9e31d | 649 | MLX5E_MPWRQ_UMR_MODE_TRIPLE, |
168723c1 MM |
650 | }; |
651 | ||
f62b8bb8 AV |
652 | struct mlx5e_rq { |
653 | /* data path */ | |
21c59685 | 654 | union { |
accd5883 | 655 | struct { |
069d1146 TT |
656 | struct mlx5_wq_cyc wq; |
657 | struct mlx5e_wqe_frag_info *frags; | |
8fb1814f | 658 | union mlx5e_alloc_units *alloc_units; |
069d1146 TT |
659 | struct mlx5e_rq_frags_info info; |
660 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 661 | } wqe; |
21c59685 | 662 | struct { |
422d4c40 | 663 | struct mlx5_wq_ll wq; |
b8a98a4c | 664 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 665 | struct mlx5e_mpw_info *info; |
619a8f2a | 666 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
ecc7ad2e | 667 | __be32 umr_mkey_be; |
b45d8b50 | 668 | u16 num_strides; |
fd9b4be8 | 669 | u16 actual_wq_head; |
89e89f7a | 670 | u8 log_stride_sz; |
fd9b4be8 TT |
671 | u8 umr_in_progress; |
672 | u8 umr_last_bulk; | |
ed084fb6 | 673 | u8 umr_completed; |
4b5fba4a | 674 | u8 min_wqe_bulk; |
997ce6af MM |
675 | u8 page_shift; |
676 | u8 pages_per_wqe; | |
677 | u8 umr_wqebbs; | |
678 | u8 mtts_per_wqe; | |
168723c1 | 679 | u8 umr_mode; |
e5ca8fb0 | 680 | struct mlx5e_shampo_hd *shampo; |
21c59685 SM |
681 | } mpwqe; |
682 | }; | |
1bfecfca | 683 | struct { |
b45d8b50 | 684 | u16 headroom; |
d628ee4f | 685 | u32 frame0_sz; |
b5503b99 | 686 | u8 map_dir; /* dma map direction */ |
1bfecfca | 687 | } buff; |
f62b8bb8 AV |
688 | |
689 | struct device *pdev; | |
690 | struct net_device *netdev; | |
05909bab | 691 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 692 | struct mlx5e_cq cq; |
79d356ef | 693 | struct mlx5e_cq_decomp cqd; |
7c39afb3 FD |
694 | struct hwtstamp_config *tstamp; |
695 | struct mlx5_clock *clock; | |
521f31af AL |
696 | struct mlx5e_icosq *icosq; |
697 | struct mlx5e_priv *priv; | |
4415a031 | 698 | |
92552d3a KM |
699 | struct mlx5e_hw_gro_data *hw_gro_data; |
700 | ||
2f48af12 | 701 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 702 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 703 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
704 | |
705 | unsigned long state; | |
706 | int ix; | |
0073c8f7 | 707 | unsigned int hw_mtu; |
f62b8bb8 | 708 | |
a5e89a3f | 709 | struct dim *dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
710 | |
711 | /* XDP */ | |
fe45386a | 712 | struct bpf_prog __rcu *xdp_prog; |
b9673cf5 | 713 | struct mlx5e_xdpsq *xdpsq; |
121e8927 | 714 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 715 | struct page_pool *page_pool; |
cb3c7fd4 | 716 | |
db05815b | 717 | /* AF_XDP zero-copy */ |
1742b3d5 | 718 | struct xsk_buff_pool *xsk_pool; |
db05815b | 719 | |
8276ea13 AL |
720 | struct work_struct recover_work; |
721 | ||
f62b8bb8 AV |
722 | /* control */ |
723 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 724 | __be32 mkey_be; |
461017cb | 725 | u8 wq_type; |
f62b8bb8 | 726 | u32 rqn; |
a43b25da | 727 | struct mlx5_core_dev *mdev; |
2e642afb | 728 | struct mlx5e_channel *channel; |
c3c94023 | 729 | struct mlx5e_dma_info wqe_overflow; |
0ddf5432 JDB |
730 | |
731 | /* XDP read-mostly */ | |
732 | struct xdp_rxq_info xdp_rxq; | |
432119de | 733 | cqe_ts_to_ns ptp_cyc2time; |
f62b8bb8 AV |
734 | } ____cacheline_aligned_in_smp; |
735 | ||
db05815b MM |
736 | enum mlx5e_channel_state { |
737 | MLX5E_CHANNEL_STATE_XSK, | |
738 | MLX5E_CHANNEL_NUM_STATES | |
739 | }; | |
740 | ||
f62b8bb8 AV |
741 | struct mlx5e_channel { |
742 | /* data path */ | |
743 | struct mlx5e_rq rq; | |
b9673cf5 | 744 | struct mlx5e_xdpsq rq_xdpsq; |
b25bd37c | 745 | struct mlx5e_txqsq sq[MLX5_MAX_NUM_TC]; |
31391048 | 746 | struct mlx5e_icosq icosq; /* internal control operations */ |
214baf22 | 747 | struct mlx5e_txqsq __rcu * __rcu *qos_sqs; |
b5503b99 | 748 | bool xdp; |
f62b8bb8 AV |
749 | struct napi_struct napi; |
750 | struct device *pdev; | |
751 | struct net_device *netdev; | |
752 | __be32 mkey_be; | |
214baf22 | 753 | u16 qos_sqs_size; |
f62b8bb8 | 754 | u8 num_tc; |
45f171b1 | 755 | u8 lag_port; |
f62b8bb8 | 756 | |
58b99ee3 TT |
757 | /* XDP_REDIRECT */ |
758 | struct mlx5e_xdpsq xdpsq; | |
759 | ||
db05815b MM |
760 | /* AF_XDP zero-copy */ |
761 | struct mlx5e_rq xskrq; | |
762 | struct mlx5e_xdpsq xsksq; | |
8d94b590 TT |
763 | |
764 | /* Async ICOSQ */ | |
765 | struct mlx5e_icosq async_icosq; | |
766 | /* async_icosq can be accessed from any CPU - the spinlock protects it. */ | |
767 | spinlock_t async_icosq_lock; | |
db05815b | 768 | |
a8c2eb15 | 769 | /* data path - accessed per napi poll */ |
6e745db4 | 770 | const struct cpumask *aff_mask; |
05909bab | 771 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
772 | |
773 | /* control */ | |
774 | struct mlx5e_priv *priv; | |
a43b25da | 775 | struct mlx5_core_dev *mdev; |
7c39afb3 | 776 | struct hwtstamp_config *tstamp; |
db05815b | 777 | DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); |
f62b8bb8 | 778 | int ix; |
67936e13 | 779 | int vec_ix; |
7f525acb | 780 | int sd_ix; |
231243c8 | 781 | int cpu; |
17958d7c MM |
782 | /* Sync between icosq recovery and XSK enable/disable. */ |
783 | struct mutex icosq_recovery_lock; | |
445a25f6 RR |
784 | |
785 | /* coalescing configuration */ | |
786 | struct dim_cq_moder rx_cq_moder; | |
787 | struct dim_cq_moder tx_cq_moder; | |
f62b8bb8 AV |
788 | }; |
789 | ||
b0d35de4 | 790 | struct mlx5e_ptp; |
145e5637 | 791 | |
ff9c852f SM |
792 | struct mlx5e_channels { |
793 | struct mlx5e_channel **c; | |
b0d35de4 | 794 | struct mlx5e_ptp *ptp; |
ff9c852f | 795 | unsigned int num; |
6a9764ef | 796 | struct mlx5e_params params; |
ff9c852f SM |
797 | }; |
798 | ||
05909bab EBE |
799 | struct mlx5e_channel_stats { |
800 | struct mlx5e_ch_stats ch; | |
b25bd37c | 801 | struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; |
05909bab | 802 | struct mlx5e_rq_stats rq; |
db05815b | 803 | struct mlx5e_rq_stats xskrq; |
890388ad | 804 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 805 | struct mlx5e_xdpsq_stats xdpsq; |
db05815b | 806 | struct mlx5e_xdpsq_stats xsksq; |
05909bab EBE |
807 | } ____cacheline_aligned_in_smp; |
808 | ||
b0d35de4 | 809 | struct mlx5e_ptp_stats { |
145e5637 | 810 | struct mlx5e_ch_stats ch; |
b25bd37c TT |
811 | struct mlx5e_sq_stats sq[MLX5_MAX_NUM_TC]; |
812 | struct mlx5e_ptp_cq_stats cq[MLX5_MAX_NUM_TC]; | |
a099da8f | 813 | struct mlx5e_rq_stats rq; |
145e5637 EBE |
814 | } ____cacheline_aligned_in_smp; |
815 | ||
acff797c | 816 | enum { |
acff797c MG |
817 | MLX5E_STATE_OPENED, |
818 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 819 | MLX5E_STATE_XDP_TX_ENABLED, |
9cf88808 | 820 | MLX5E_STATE_XDP_ACTIVE, |
eab0da38 | 821 | MLX5E_STATE_CHANNELS_ACTIVE, |
acff797c MG |
822 | }; |
823 | ||
de8650a8 EBE |
824 | struct mlx5e_modify_sq_param { |
825 | int curr_state; | |
826 | int next_state; | |
827 | int rl_update; | |
828 | int rl_index; | |
214baf22 MM |
829 | bool qos_update; |
830 | u16 qos_queue_group_id; | |
de8650a8 EBE |
831 | }; |
832 | ||
cef35af3 EBE |
833 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
834 | struct mlx5e_hv_vhca_stats_agent { | |
835 | struct mlx5_hv_vhca_agent *agent; | |
836 | struct delayed_work work; | |
837 | u16 delay; | |
838 | void *buf; | |
839 | }; | |
840 | #endif | |
841 | ||
db05815b | 842 | struct mlx5e_xsk { |
1742b3d5 MK |
843 | /* XSK buffer pools are stored separately from channels, |
844 | * because we don't want to lose them when channels are | |
845 | * recreated. The kernel also stores buffer pool, but it doesn't | |
846 | * distinguish between zero-copy and non-zero-copy UMEMs, so | |
847 | * rely on our mechanism. | |
db05815b | 848 | */ |
1742b3d5 | 849 | struct xsk_buff_pool **pools; |
db05815b MM |
850 | u16 refcnt; |
851 | bool ever_used; | |
852 | }; | |
853 | ||
3909a12e MM |
854 | /* Temporary storage for variables that are allocated when struct mlx5e_priv is |
855 | * initialized, and used where we can't allocate them because that functions | |
856 | * must not fail. Use with care and make sure the same variable is not used | |
857 | * simultaneously by multiple users. | |
858 | */ | |
859 | struct mlx5e_scratchpad { | |
860 | cpumask_var_t cpumask; | |
861 | }; | |
862 | ||
5543e989 | 863 | struct mlx5e_trap; |
aaffda6b | 864 | struct mlx5e_htb; |
5543e989 | 865 | |
f62b8bb8 AV |
866 | struct mlx5e_priv { |
867 | /* priv data path fields - start */ | |
8bf30be7 | 868 | struct mlx5e_selq selq; |
0246a57a | 869 | struct mlx5e_txqsq **txq2sq; |
0a3e5c1b JD |
870 | struct mlx5e_sq_stats **txq2sq_stats; |
871 | ||
2a5e7a13 HN |
872 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
873 | struct mlx5e_dcbx_dp dcbx_dp; | |
874 | #endif | |
f62b8bb8 AV |
875 | /* priv data path fields - end */ |
876 | ||
877 | unsigned long state; | |
878 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 879 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 880 | |
ff9c852f | 881 | struct mlx5e_channels channels; |
3f22d6c7 | 882 | struct mlx5e_rx_res *rx_res; |
0246a57a | 883 | u32 *tx_rates; |
f62b8bb8 | 884 | |
af8bbf73 | 885 | struct mlx5e_flow_steering *fs; |
f62b8bb8 | 886 | |
7bb29755 | 887 | struct workqueue_struct *wq; |
f62b8bb8 AV |
888 | struct work_struct update_carrier_work; |
889 | struct work_struct set_rx_mode_work; | |
3947ca18 | 890 | struct work_struct tx_timeout_work; |
cdeef2b1 | 891 | struct work_struct update_stats_work; |
5c7e8bbb ED |
892 | struct work_struct monitor_counters_work; |
893 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
894 | |
895 | struct mlx5_core_dev *mdev; | |
896 | struct net_device *netdev; | |
5543e989 | 897 | struct mlx5e_trap *en_trap; |
f62b8bb8 | 898 | struct mlx5e_stats stats; |
be98737a | 899 | struct mlx5e_channel_stats **channel_stats; |
5543e989 | 900 | struct mlx5e_channel_stats trap_stats; |
b0d35de4 | 901 | struct mlx5e_ptp_stats ptp_stats; |
db83f24d MT |
902 | struct mlx5e_sq_stats **htb_qos_sq_stats; |
903 | u16 htb_max_qos_sqs; | |
9d758d4a | 904 | u16 stats_nch; |
694826e3 | 905 | u16 max_nch; |
05909bab | 906 | u8 max_opened_tc; |
b0d35de4 | 907 | bool tx_ptp_opened; |
a28359e9 | 908 | bool rx_ptp_opened; |
7c39afb3 | 909 | struct hwtstamp_config tstamp; |
7f525acb | 910 | u16 q_counter[MLX5_SD_MAX_GROUP_SZ]; |
7cbaf9a3 | 911 | u16 drop_rq_q_counter; |
7cffaddd | 912 | struct notifier_block events_nb; |
70038b73 | 913 | struct notifier_block blocking_events_nb; |
7cffaddd | 914 | |
18a2b7f9 | 915 | struct udp_tunnel_nic_info nic_info; |
3a6a931d HN |
916 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
917 | struct mlx5e_dcbx dcbx; | |
918 | #endif | |
919 | ||
6bfd390b | 920 | const struct mlx5e_profile *profile; |
127ea380 | 921 | void *ppriv; |
7390762a | 922 | #ifdef CONFIG_MLX5_MACSEC |
8ff0ac5b LN |
923 | struct mlx5e_macsec *macsec; |
924 | #endif | |
547eede0 IT |
925 | #ifdef CONFIG_MLX5_EN_IPSEC |
926 | struct mlx5e_ipsec *ipsec; | |
927 | #endif | |
43585a41 IL |
928 | #ifdef CONFIG_MLX5_EN_TLS |
929 | struct mlx5e_tls *tls; | |
930 | #endif | |
de8650a8 | 931 | struct devlink_health_reporter *tx_reporter; |
9032e719 | 932 | struct devlink_health_reporter *rx_reporter; |
db05815b | 933 | struct mlx5e_xsk xsk; |
cef35af3 EBE |
934 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
935 | struct mlx5e_hv_vhca_stats_agent stats_agent; | |
936 | #endif | |
3909a12e | 937 | struct mlx5e_scratchpad scratchpad; |
aaffda6b | 938 | struct mlx5e_htb *htb; |
80743c4f | 939 | struct mlx5e_mqprio_rl *mqprio_rl; |
288eca60 | 940 | struct dentry *dfs_root; |
bf11485f | 941 | struct mlx5_devcom_comp_dev *devcom; |
f62b8bb8 AV |
942 | }; |
943 | ||
ee75f1fc JP |
944 | struct mlx5e_dev { |
945 | struct mlx5e_priv *priv; | |
c30f3faa | 946 | struct devlink_port dl_port; |
ee75f1fc JP |
947 | }; |
948 | ||
5adf4c47 TT |
949 | struct mlx5e_rx_handlers { |
950 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
951 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
f97d5c2a | 952 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe_shampo; |
5adf4c47 TT |
953 | }; |
954 | ||
955 | extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; | |
956 | ||
6c72cb05 TT |
957 | enum mlx5e_profile_feature { |
958 | MLX5E_PROFILE_FEATURE_PTP_RX, | |
1958c2bd TT |
959 | MLX5E_PROFILE_FEATURE_PTP_TX, |
960 | MLX5E_PROFILE_FEATURE_QOS_HTB, | |
454533aa LK |
961 | MLX5E_PROFILE_FEATURE_FS_VLAN, |
962 | MLX5E_PROFILE_FEATURE_FS_TC, | |
6c72cb05 TT |
963 | }; |
964 | ||
a43b25da | 965 | struct mlx5e_profile { |
182570b2 | 966 | int (*init)(struct mlx5_core_dev *mdev, |
3ef14e46 | 967 | struct net_device *netdev); |
a43b25da SM |
968 | void (*cleanup)(struct mlx5e_priv *priv); |
969 | int (*init_rx)(struct mlx5e_priv *priv); | |
970 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
971 | int (*init_tx)(struct mlx5e_priv *priv); | |
972 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
973 | void (*enable)(struct mlx5e_priv *priv); | |
974 | void (*disable)(struct mlx5e_priv *priv); | |
a90f88fe | 975 | int (*update_rx)(struct mlx5e_priv *priv); |
a43b25da | 976 | void (*update_stats)(struct mlx5e_priv *priv); |
7ca42c80 | 977 | void (*update_carrier)(struct mlx5e_priv *priv); |
473baf2e | 978 | int (*max_nch_limit)(struct mlx5_core_dev *mdev); |
b25bd37c TT |
979 | u32 (*get_tisn)(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv, |
980 | u8 lag_port, u8 tc); | |
3460c184 | 981 | unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); |
f0ff8e8c | 982 | mlx5e_stats_grp_t *stats_grps; |
5adf4c47 | 983 | const struct mlx5e_rx_handlers *rx_handlers; |
a43b25da | 984 | int max_tc; |
6c72cb05 | 985 | u32 features; |
a43b25da SM |
986 | }; |
987 | ||
b25bd37c TT |
988 | u32 mlx5e_profile_get_tisn(struct mlx5_core_dev *mdev, |
989 | struct mlx5e_priv *priv, | |
990 | const struct mlx5e_profile *profile, | |
991 | u8 lag_port, u8 tc); | |
992 | ||
6c72cb05 | 993 | #define mlx5e_profile_feature_cap(profile, feature) \ |
bc2a7b5c | 994 | ((profile)->features & BIT(MLX5E_PROFILE_FEATURE_##feature)) |
6c72cb05 | 995 | |
665bc539 GP |
996 | void mlx5e_build_ptys2ethtool_map(void); |
997 | ||
6470d2e7 | 998 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev, u8 page_shift, |
168723c1 | 999 | enum mlx5e_mpwrq_umr_mode umr_mode); |
2ccb0a79 | 1000 | |
94e52193 | 1001 | void mlx5e_shampo_fill_umr(struct mlx5e_rq *rq, int len); |
e839ac9a | 1002 | void mlx5e_shampo_dealloc_hd(struct mlx5e_rq *rq); |
d9ee0491 | 1003 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 1004 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 1005 | |
d605d668 | 1006 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
7990b1b5 | 1007 | int mlx5e_self_test_fill_strings(struct mlx5e_priv *priv, u8 *data); |
d605d668 KH |
1008 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, |
1009 | u64 *buf); | |
f62b8bb8 AV |
1010 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
1011 | ||
1170fbd8 FD |
1012 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
1013 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
c91c1da7 | 1014 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val, bool rx_filter); |
ef9814de | 1015 | |
f62b8bb8 AV |
1016 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
1017 | u16 vid); | |
1018 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
1019 | u16 vid); | |
237f258c | 1020 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 1021 | |
db05815b MM |
1022 | struct mlx5e_xsk_param; |
1023 | ||
1024 | struct mlx5e_rq_param; | |
869c5f92 | 1025 | int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, |
7f525acb | 1026 | struct mlx5e_xsk_param *xsk, int node, u16 q_counter, |
869c5f92 | 1027 | struct mlx5e_rq *rq); |
082a9edf | 1028 | #define MLX5E_RQ_WQES_TIMEOUT 20000 /* msecs */ |
db05815b | 1029 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); |
db05815b | 1030 | void mlx5e_close_rq(struct mlx5e_rq *rq); |
7f525acb | 1031 | int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param, u16 q_counter); |
5543e989 | 1032 | void mlx5e_destroy_rq(struct mlx5e_rq *rq); |
db05815b | 1033 | |
445a25f6 RR |
1034 | bool mlx5e_reset_rx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, |
1035 | bool dim_enabled); | |
1036 | bool mlx5e_reset_rx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, | |
1037 | bool dim_enabled, bool keep_dim_state); | |
1038 | ||
db05815b | 1039 | struct mlx5e_sq_param; |
db05815b | 1040 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, |
1742b3d5 | 1041 | struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, |
db05815b MM |
1042 | struct mlx5e_xdpsq *sq, bool is_redirect); |
1043 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); | |
1044 | ||
4d0b7ef9 | 1045 | struct mlx5e_create_cq_param { |
db52aa6d TT |
1046 | struct net_device *netdev; |
1047 | struct workqueue_struct *wq; | |
4d0b7ef9 AL |
1048 | struct napi_struct *napi; |
1049 | struct mlx5e_ch_stats *ch_stats; | |
1050 | int node; | |
1051 | int ix; | |
1052 | }; | |
1053 | ||
db05815b | 1054 | struct mlx5e_cq_param; |
db52aa6d | 1055 | int mlx5e_open_cq(struct mlx5_core_dev *mdev, struct dim_cq_moder moder, |
4d0b7ef9 AL |
1056 | struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, |
1057 | struct mlx5e_cq *cq); | |
db05815b | 1058 | void mlx5e_close_cq(struct mlx5e_cq *cq); |
445a25f6 RR |
1059 | int mlx5e_modify_cq_period_mode(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, |
1060 | u8 cq_period_mode); | |
1061 | int mlx5e_modify_cq_moderation(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, | |
1062 | u16 cq_period, u16 cq_max_count, u8 cq_period_mode); | |
db05815b | 1063 | |
f62b8bb8 AV |
1064 | int mlx5e_open_locked(struct net_device *netdev); |
1065 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d | 1066 | |
2e642afb MM |
1067 | void mlx5e_trigger_napi_icosq(struct mlx5e_channel *c); |
1068 | void mlx5e_trigger_napi_sched(struct napi_struct *napi); | |
1069 | ||
55c2503d SM |
1070 | int mlx5e_open_channels(struct mlx5e_priv *priv, |
1071 | struct mlx5e_channels *chs); | |
1072 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 | 1073 | |
dca147b3 | 1074 | /* Function pointer to be used to modify HW or kernel settings while |
2e20a151 SM |
1075 | * switching channels |
1076 | */ | |
b9ab5d0e MM |
1077 | typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); |
1078 | #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ | |
1079 | int fn##_ctx(struct mlx5e_priv *priv, void *context) \ | |
1080 | { \ | |
1081 | return fn(priv); \ | |
1082 | } | |
484c1ada | 1083 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
94872d4e MM |
1084 | int mlx5e_safe_switch_params(struct mlx5e_priv *priv, |
1085 | struct mlx5e_params *new_params, | |
1086 | mlx5e_fp_preactivate preactivate, | |
1087 | void *context, bool reset); | |
214baf22 | 1088 | int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); |
b9ab5d0e | 1089 | int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); |
bcee0937 | 1090 | int mlx5e_update_tc_and_tx_queues_ctx(struct mlx5e_priv *priv, void *context); |
603f4a45 SM |
1091 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
1092 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
885b8cfb | 1093 | int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); |
55c2503d | 1094 | |
d9ba64de | 1095 | int mlx5e_flush_rq(struct mlx5e_rq *rq, int curr_state); |
be5323c8 AL |
1096 | void mlx5e_activate_rq(struct mlx5e_rq *rq); |
1097 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
be5323c8 AL |
1098 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); |
1099 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); | |
9908aa29 | 1100 | |
de8650a8 EBE |
1101 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
1102 | struct mlx5e_modify_sq_param *p); | |
214baf22 MM |
1103 | int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, |
1104 | struct mlx5e_params *params, struct mlx5e_sq_param *param, | |
e0ee6891 TT |
1105 | struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, |
1106 | struct mlx5e_sq_stats *sq_stats); | |
de8650a8 | 1107 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); |
145e5637 EBE |
1108 | void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); |
1109 | void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); | |
de8650a8 | 1110 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); |
145e5637 EBE |
1111 | int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); |
1112 | void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); | |
1113 | struct mlx5e_create_sq_param; | |
1114 | int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, | |
1115 | struct mlx5e_sq_param *param, | |
1116 | struct mlx5e_create_sq_param *csp, | |
214baf22 | 1117 | u16 qos_queue_group_id, |
145e5637 EBE |
1118 | u32 *sqn); |
1119 | void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); | |
214baf22 | 1120 | void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); |
de8650a8 | 1121 | |
445a25f6 RR |
1122 | bool mlx5e_reset_tx_moderation(struct dim_cq_moder *cq_moder, u8 cq_period_mode, |
1123 | bool dim_enabled); | |
1124 | bool mlx5e_reset_tx_channels_moderation(struct mlx5e_channels *chs, u8 cq_period_mode, | |
1125 | bool dim_enabled, bool keep_dim_state); | |
1126 | ||
e3cfc7e6 MS |
1127 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
1128 | { | |
1129 | return MLX5_CAP_ETH(mdev, swp) && | |
1130 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
1131 | } | |
1132 | ||
f62b8bb8 | 1133 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac | 1134 | |
0e1e03c0 | 1135 | int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); |
25461ce8 | 1136 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev, bool create_tises); |
b50d292b | 1137 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); |
80639b19 ES |
1138 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, |
1139 | bool enable_mc_lb); | |
17347d54 | 1140 | void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); |
1afff42c | 1141 | |
bc81b9d3 | 1142 | /* common netdev helpers */ |
1462e48d RD |
1143 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1144 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1145 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1146 | struct mlx5e_rq *drop_rq); | |
1147 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
1148 | ||
2b257a6e | 1149 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); |
5426a0b2 SM |
1150 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); |
1151 | ||
b36cdb42 | 1152 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1153 | int mlx5e_close(struct net_device *netdev); |
1154 | int mlx5e_open(struct net_device *netdev); | |
cb67b832 | 1155 | |
cdeef2b1 | 1156 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 | 1157 | |
d9ee0491 | 1158 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
b9ab5d0e | 1159 | int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); |
250a42b6 | 1160 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
b9ab5d0e | 1161 | mlx5e_fp_preactivate preactivate); |
18a2b7f9 | 1162 | void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); |
250a42b6 | 1163 | |
076b0936 ES |
1164 | /* ethtool helpers */ |
1165 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1166 | struct ethtool_drvinfo *drvinfo); | |
1167 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
30f8d238 | 1168 | u32 stringset, u8 *data); |
076b0936 ES |
1169 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); |
1170 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1171 | struct ethtool_stats *stats, u64 *data); | |
1172 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
07071e47 GP |
1173 | struct ethtool_ringparam *param, |
1174 | struct kernel_ethtool_ringparam *kernel_param); | |
076b0936 | 1175 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, |
ab666b52 GP |
1176 | struct ethtool_ringparam *param, |
1177 | struct netlink_ext_ack *extack); | |
076b0936 ES |
1178 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, |
1179 | struct ethtool_channels *ch); | |
1180 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1181 | struct ethtool_channels *ch); | |
1182 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
bc541621 | 1183 | struct ethtool_coalesce *coal, |
29a943d7 GP |
1184 | struct kernel_ethtool_coalesce *kernel_coal, |
1185 | struct netlink_ext_ack *extack); | |
076b0936 | 1186 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, |
bc541621 SM |
1187 | struct ethtool_coalesce *coal, |
1188 | struct kernel_ethtool_coalesce *kernel_coal, | |
1189 | struct netlink_ext_ack *extack); | |
651ebaad RR |
1190 | int mlx5e_get_per_queue_coalesce(struct net_device *dev, u32 queue, |
1191 | struct ethtool_coalesce *coal); | |
1192 | int mlx5e_set_per_queue_coalesce(struct net_device *dev, u32 queue, | |
1193 | struct ethtool_coalesce *coal); | |
a5355de8 OG |
1194 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1195 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e | 1196 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
2111375b | 1197 | struct kernel_ethtool_ts_info *info); |
f43d48d1 EBE |
1198 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1199 | struct ethtool_flash *flash); | |
076b0936 | 1200 | |
2c3b5bee | 1201 | /* mlx5e generic netdev management API */ |
040ee617 AH |
1202 | static inline bool |
1203 | mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) | |
1204 | { | |
1205 | return !is_kdump_kernel() && | |
1206 | MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); | |
1207 | } | |
1208 | ||
6d0ba493 | 1209 | int mlx5e_get_pf_num_tirs(struct mlx5_core_dev *mdev); |
c9fd1e33 | 1210 | int mlx5e_priv_init(struct mlx5e_priv *priv, |
9d758d4a | 1211 | const struct mlx5e_profile *profile, |
c9fd1e33 RD |
1212 | struct net_device *netdev, |
1213 | struct mlx5_core_dev *mdev); | |
1214 | void mlx5e_priv_cleanup(struct mlx5e_priv *priv); | |
3ef14e46 | 1215 | struct net_device * |
1958c2bd | 1216 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile); |
2c3b5bee SM |
1217 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1218 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1219 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
c4d7eb57 SM |
1220 | int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, |
1221 | const struct mlx5e_profile *new_profile, void *new_ppriv); | |
7a9fb35e | 1222 | void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); |
6d7ee2ed | 1223 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
3ef14e46 | 1224 | void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); |
073caf50 | 1225 | |
4d5ab0ad | 1226 | void mlx5e_set_xdp_feature(struct net_device *netdev); |
073caf50 OG |
1227 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, |
1228 | struct net_device *netdev, | |
1229 | netdev_features_t features); | |
d3cbd425 | 1230 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); |
073caf50 OG |
1231 | #ifdef CONFIG_MLX5_ESWITCH |
1232 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1233 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1234 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1235 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1236 | #endif | |
8518d05b | 1237 | int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey); |
1afff42c | 1238 | #endif /* __MLX5_EN_H__ */ |