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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/mlx5/driver.h> | |
36 | #include <linux/mlx5/qp.h> | |
37 | #include <linux/mlx5/cq.h> | |
38 | #include "vport.h" | |
39 | #include "wq.h" | |
40 | #include "transobj.h" | |
41 | #include "mlx5_core.h" | |
42 | ||
43 | #define MLX5E_MAX_NUM_TC 8 | |
44 | ||
45 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7 | |
46 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
47 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
48 | ||
49 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7 | |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa | |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
52 | ||
53 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (16 * 1024) | |
54 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 | |
55 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
56 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
57 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
58 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
59 | #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7 | |
60 | #define MLX5E_PARAMS_MIN_MTU 46 | |
61 | ||
62 | #define MLX5E_TX_CQ_POLL_BUDGET 128 | |
63 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
64 | ||
65 | static const char vport_strings[][ETH_GSTRING_LEN] = { | |
66 | /* vport statistics */ | |
67 | "rx_packets", | |
68 | "rx_bytes", | |
69 | "tx_packets", | |
70 | "tx_bytes", | |
71 | "rx_error_packets", | |
72 | "rx_error_bytes", | |
73 | "tx_error_packets", | |
74 | "tx_error_bytes", | |
75 | "rx_unicast_packets", | |
76 | "rx_unicast_bytes", | |
77 | "tx_unicast_packets", | |
78 | "tx_unicast_bytes", | |
79 | "rx_multicast_packets", | |
80 | "rx_multicast_bytes", | |
81 | "tx_multicast_packets", | |
82 | "tx_multicast_bytes", | |
83 | "rx_broadcast_packets", | |
84 | "rx_broadcast_bytes", | |
85 | "tx_broadcast_packets", | |
86 | "tx_broadcast_bytes", | |
87 | ||
88 | /* SW counters */ | |
89 | "tso_packets", | |
90 | "tso_bytes", | |
91 | "lro_packets", | |
92 | "lro_bytes", | |
93 | "rx_csum_good", | |
94 | "rx_csum_none", | |
95 | "tx_csum_offload", | |
96 | "tx_queue_stopped", | |
97 | "tx_queue_wake", | |
98 | "tx_queue_dropped", | |
99 | "rx_wqe_err", | |
100 | }; | |
101 | ||
102 | struct mlx5e_vport_stats { | |
103 | /* HW counters */ | |
104 | u64 rx_packets; | |
105 | u64 rx_bytes; | |
106 | u64 tx_packets; | |
107 | u64 tx_bytes; | |
108 | u64 rx_error_packets; | |
109 | u64 rx_error_bytes; | |
110 | u64 tx_error_packets; | |
111 | u64 tx_error_bytes; | |
112 | u64 rx_unicast_packets; | |
113 | u64 rx_unicast_bytes; | |
114 | u64 tx_unicast_packets; | |
115 | u64 tx_unicast_bytes; | |
116 | u64 rx_multicast_packets; | |
117 | u64 rx_multicast_bytes; | |
118 | u64 tx_multicast_packets; | |
119 | u64 tx_multicast_bytes; | |
120 | u64 rx_broadcast_packets; | |
121 | u64 rx_broadcast_bytes; | |
122 | u64 tx_broadcast_packets; | |
123 | u64 tx_broadcast_bytes; | |
124 | ||
125 | /* SW counters */ | |
126 | u64 tso_packets; | |
127 | u64 tso_bytes; | |
128 | u64 lro_packets; | |
129 | u64 lro_bytes; | |
130 | u64 rx_csum_good; | |
131 | u64 rx_csum_none; | |
132 | u64 tx_csum_offload; | |
133 | u64 tx_queue_stopped; | |
134 | u64 tx_queue_wake; | |
135 | u64 tx_queue_dropped; | |
136 | u64 rx_wqe_err; | |
137 | ||
138 | #define NUM_VPORT_COUNTERS 31 | |
139 | }; | |
140 | ||
141 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { | |
142 | "packets", | |
143 | "csum_none", | |
144 | "lro_packets", | |
145 | "lro_bytes", | |
146 | "wqe_err" | |
147 | }; | |
148 | ||
149 | struct mlx5e_rq_stats { | |
150 | u64 packets; | |
151 | u64 csum_none; | |
152 | u64 lro_packets; | |
153 | u64 lro_bytes; | |
154 | u64 wqe_err; | |
155 | #define NUM_RQ_STATS 5 | |
156 | }; | |
157 | ||
158 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
159 | "packets", | |
160 | "tso_packets", | |
161 | "tso_bytes", | |
162 | "csum_offload_none", | |
163 | "stopped", | |
164 | "wake", | |
165 | "dropped", | |
166 | "nop" | |
167 | }; | |
168 | ||
169 | struct mlx5e_sq_stats { | |
170 | u64 packets; | |
171 | u64 tso_packets; | |
172 | u64 tso_bytes; | |
173 | u64 csum_offload_none; | |
174 | u64 stopped; | |
175 | u64 wake; | |
176 | u64 dropped; | |
177 | u64 nop; | |
178 | #define NUM_SQ_STATS 8 | |
179 | }; | |
180 | ||
181 | struct mlx5e_stats { | |
182 | struct mlx5e_vport_stats vport; | |
183 | }; | |
184 | ||
185 | struct mlx5e_params { | |
186 | u8 log_sq_size; | |
187 | u8 log_rq_size; | |
188 | u16 num_channels; | |
189 | u8 default_vlan_prio; | |
190 | u8 num_tc; | |
191 | u16 rx_cq_moderation_usec; | |
192 | u16 rx_cq_moderation_pkts; | |
193 | u16 tx_cq_moderation_usec; | |
194 | u16 tx_cq_moderation_pkts; | |
195 | u16 min_rx_wqes; | |
196 | u16 rx_hash_log_tbl_sz; | |
197 | bool lro_en; | |
198 | u32 lro_wqe_sz; | |
199 | }; | |
200 | ||
201 | enum { | |
202 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
203 | }; | |
204 | ||
205 | enum cq_flags { | |
206 | MLX5E_CQ_HAS_CQES = 1, | |
207 | }; | |
208 | ||
209 | struct mlx5e_cq { | |
210 | /* data path - accessed per cqe */ | |
211 | struct mlx5_cqwq wq; | |
212 | void *sqrq; | |
213 | unsigned long flags; | |
214 | ||
215 | /* data path - accessed per napi poll */ | |
216 | struct napi_struct *napi; | |
217 | struct mlx5_core_cq mcq; | |
218 | struct mlx5e_channel *channel; | |
219 | ||
220 | /* control */ | |
221 | struct mlx5_wq_ctrl wq_ctrl; | |
222 | } ____cacheline_aligned_in_smp; | |
223 | ||
224 | struct mlx5e_rq { | |
225 | /* data path */ | |
226 | struct mlx5_wq_ll wq; | |
227 | u32 wqe_sz; | |
228 | struct sk_buff **skb; | |
229 | ||
230 | struct device *pdev; | |
231 | struct net_device *netdev; | |
232 | struct mlx5e_rq_stats stats; | |
233 | struct mlx5e_cq cq; | |
234 | ||
235 | unsigned long state; | |
236 | int ix; | |
237 | ||
238 | /* control */ | |
239 | struct mlx5_wq_ctrl wq_ctrl; | |
240 | u32 rqn; | |
241 | struct mlx5e_channel *channel; | |
242 | } ____cacheline_aligned_in_smp; | |
243 | ||
244 | struct mlx5e_tx_skb_cb { | |
245 | u32 num_bytes; | |
246 | u8 num_wqebbs; | |
247 | u8 num_dma; | |
248 | }; | |
249 | ||
250 | #define MLX5E_TX_SKB_CB(__skb) ((struct mlx5e_tx_skb_cb *)__skb->cb) | |
251 | ||
252 | struct mlx5e_sq_dma { | |
253 | dma_addr_t addr; | |
254 | u32 size; | |
255 | }; | |
256 | ||
257 | enum { | |
258 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
259 | }; | |
260 | ||
261 | struct mlx5e_sq { | |
262 | /* data path */ | |
263 | ||
264 | /* dirtied @completion */ | |
265 | u16 cc; | |
266 | u32 dma_fifo_cc; | |
267 | ||
268 | /* dirtied @xmit */ | |
269 | u16 pc ____cacheline_aligned_in_smp; | |
270 | u32 dma_fifo_pc; | |
271 | u32 bf_offset; | |
272 | struct mlx5e_sq_stats stats; | |
273 | ||
274 | struct mlx5e_cq cq; | |
275 | ||
276 | /* pointers to per packet info: write@xmit, read@completion */ | |
277 | struct sk_buff **skb; | |
278 | struct mlx5e_sq_dma *dma_fifo; | |
279 | ||
280 | /* read only */ | |
281 | struct mlx5_wq_cyc wq; | |
282 | u32 dma_fifo_mask; | |
283 | void __iomem *uar_map; | |
284 | struct netdev_queue *txq; | |
285 | u32 sqn; | |
286 | u32 bf_buf_size; | |
287 | struct device *pdev; | |
288 | __be32 mkey_be; | |
289 | unsigned long state; | |
290 | ||
291 | /* control path */ | |
292 | struct mlx5_wq_ctrl wq_ctrl; | |
293 | struct mlx5_uar uar; | |
294 | struct mlx5e_channel *channel; | |
295 | int tc; | |
296 | } ____cacheline_aligned_in_smp; | |
297 | ||
298 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
299 | { | |
300 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
301 | (sq->cc == sq->pc)); | |
302 | } | |
303 | ||
304 | enum channel_flags { | |
305 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
306 | }; | |
307 | ||
308 | struct mlx5e_channel { | |
309 | /* data path */ | |
310 | struct mlx5e_rq rq; | |
311 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
312 | struct napi_struct napi; | |
313 | struct device *pdev; | |
314 | struct net_device *netdev; | |
315 | __be32 mkey_be; | |
316 | u8 num_tc; | |
317 | unsigned long flags; | |
318 | ||
319 | /* control */ | |
320 | struct mlx5e_priv *priv; | |
321 | int ix; | |
322 | int cpu; | |
323 | }; | |
324 | ||
325 | enum mlx5e_traffic_types { | |
326 | MLX5E_TT_IPV4_TCP = 0, | |
327 | MLX5E_TT_IPV6_TCP = 1, | |
328 | MLX5E_TT_IPV4_UDP = 2, | |
329 | MLX5E_TT_IPV6_UDP = 3, | |
330 | MLX5E_TT_IPV4 = 4, | |
331 | MLX5E_TT_IPV6 = 5, | |
332 | MLX5E_TT_ANY = 6, | |
333 | MLX5E_NUM_TT = 7, | |
334 | }; | |
335 | ||
336 | enum { | |
337 | MLX5E_RQT_SPREADING = 0, | |
338 | MLX5E_RQT_DEFAULT_RQ = 1, | |
339 | MLX5E_NUM_RQT = 2, | |
340 | }; | |
341 | ||
342 | struct mlx5e_eth_addr_info { | |
343 | u8 addr[ETH_ALEN + 2]; | |
344 | u32 tt_vec; | |
345 | u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */ | |
346 | }; | |
347 | ||
348 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
349 | ||
350 | struct mlx5e_eth_addr_db { | |
351 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
352 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
353 | struct mlx5e_eth_addr_info broadcast; | |
354 | struct mlx5e_eth_addr_info allmulti; | |
355 | struct mlx5e_eth_addr_info promisc; | |
356 | bool broadcast_enabled; | |
357 | bool allmulti_enabled; | |
358 | bool promisc_enabled; | |
359 | }; | |
360 | ||
361 | enum { | |
362 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
363 | MLX5E_STATE_OPENED, | |
364 | }; | |
365 | ||
366 | struct mlx5e_vlan_db { | |
367 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; | |
368 | u32 active_vlans_ft_ix[VLAN_N_VID]; | |
369 | u32 untagged_rule_ft_ix; | |
370 | u32 any_vlan_rule_ft_ix; | |
371 | bool filter_disabled; | |
372 | }; | |
373 | ||
374 | struct mlx5e_flow_table { | |
375 | void *vlan; | |
376 | void *main; | |
377 | }; | |
378 | ||
379 | struct mlx5e_priv { | |
380 | /* priv data path fields - start */ | |
381 | int order_base_2_num_channels; | |
382 | int queue_mapping_channel_mask; | |
383 | int num_tc; | |
384 | int default_vlan_prio; | |
385 | /* priv data path fields - end */ | |
386 | ||
387 | unsigned long state; | |
388 | struct mutex state_lock; /* Protects Interface state */ | |
389 | struct mlx5_uar cq_uar; | |
390 | u32 pdn; | |
391 | struct mlx5_core_mr mr; | |
392 | ||
393 | struct mlx5e_channel **channel; | |
394 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
395 | u32 rqtn; | |
396 | u32 tirn[MLX5E_NUM_TT]; | |
397 | ||
398 | struct mlx5e_flow_table ft; | |
399 | struct mlx5e_eth_addr_db eth_addr; | |
400 | struct mlx5e_vlan_db vlan; | |
401 | ||
402 | struct mlx5e_params params; | |
403 | spinlock_t async_events_spinlock; /* sync hw events */ | |
404 | struct work_struct update_carrier_work; | |
405 | struct work_struct set_rx_mode_work; | |
406 | struct delayed_work update_stats_work; | |
407 | ||
408 | struct mlx5_core_dev *mdev; | |
409 | struct net_device *netdev; | |
410 | struct mlx5e_stats stats; | |
411 | }; | |
412 | ||
413 | #define MLX5E_NET_IP_ALIGN 2 | |
414 | ||
415 | struct mlx5e_tx_wqe { | |
416 | struct mlx5_wqe_ctrl_seg ctrl; | |
417 | struct mlx5_wqe_eth_seg eth; | |
418 | }; | |
419 | ||
420 | struct mlx5e_rx_wqe { | |
421 | struct mlx5_wqe_srq_next_seg next; | |
422 | struct mlx5_wqe_data_seg data; | |
423 | }; | |
424 | ||
425 | enum mlx5e_link_mode { | |
426 | MLX5E_1000BASE_CX_SGMII = 0, | |
427 | MLX5E_1000BASE_KX = 1, | |
428 | MLX5E_10GBASE_CX4 = 2, | |
429 | MLX5E_10GBASE_KX4 = 3, | |
430 | MLX5E_10GBASE_KR = 4, | |
431 | MLX5E_20GBASE_KR2 = 5, | |
432 | MLX5E_40GBASE_CR4 = 6, | |
433 | MLX5E_40GBASE_KR4 = 7, | |
434 | MLX5E_56GBASE_R4 = 8, | |
435 | MLX5E_10GBASE_CR = 12, | |
436 | MLX5E_10GBASE_SR = 13, | |
437 | MLX5E_10GBASE_ER = 14, | |
438 | MLX5E_40GBASE_SR4 = 15, | |
439 | MLX5E_40GBASE_LR4 = 16, | |
440 | MLX5E_100GBASE_CR4 = 20, | |
441 | MLX5E_100GBASE_SR4 = 21, | |
442 | MLX5E_100GBASE_KR4 = 22, | |
443 | MLX5E_100GBASE_LR4 = 23, | |
444 | MLX5E_100BASE_TX = 24, | |
445 | MLX5E_100BASE_T = 25, | |
446 | MLX5E_10GBASE_T = 26, | |
447 | MLX5E_25GBASE_CR = 27, | |
448 | MLX5E_25GBASE_KR = 28, | |
449 | MLX5E_25GBASE_SR = 29, | |
450 | MLX5E_50GBASE_CR2 = 30, | |
451 | MLX5E_50GBASE_KR2 = 31, | |
452 | MLX5E_LINK_MODES_NUMBER, | |
453 | }; | |
454 | ||
455 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
456 | ||
457 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, | |
458 | void *accel_priv, select_queue_fallback_t fallback); | |
459 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
460 | netdev_tx_t mlx5e_xmit_multi_tc(struct sk_buff *skb, struct net_device *dev); | |
461 | ||
462 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
463 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
464 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
465 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
466 | bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); | |
467 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); | |
468 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
469 | ||
470 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
471 | ||
472 | int mlx5e_open_flow_table(struct mlx5e_priv *priv); | |
473 | void mlx5e_close_flow_table(struct mlx5e_priv *priv); | |
474 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); | |
475 | void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv); | |
476 | void mlx5e_set_rx_mode_work(struct work_struct *work); | |
477 | ||
478 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, | |
479 | u16 vid); | |
480 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
481 | u16 vid); | |
482 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
483 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
484 | int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv); | |
485 | void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv); | |
486 | ||
487 | int mlx5e_open_locked(struct net_device *netdev); | |
488 | int mlx5e_close_locked(struct net_device *netdev); | |
489 | int mlx5e_update_priv_params(struct mlx5e_priv *priv, | |
490 | struct mlx5e_params *new_params); | |
491 | ||
492 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
493 | struct mlx5e_tx_wqe *wqe) | |
494 | { | |
495 | /* ensure wqe is visible to device before updating doorbell record */ | |
496 | dma_wmb(); | |
497 | ||
498 | *sq->wq.db = cpu_to_be32(sq->pc); | |
499 | ||
500 | /* ensure doorbell record is visible to device before ringing the | |
501 | * doorbell | |
502 | */ | |
503 | wmb(); | |
504 | ||
505 | mlx5_write64((__be32 *)&wqe->ctrl, | |
506 | sq->uar_map + MLX5_BF_OFFSET + sq->bf_offset, | |
507 | NULL); | |
508 | ||
509 | sq->bf_offset ^= sq->bf_buf_size; | |
510 | } | |
511 | ||
512 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
513 | { | |
514 | struct mlx5_core_cq *mcq; | |
515 | ||
516 | mcq = &cq->mcq; | |
517 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
518 | } | |
519 | ||
520 | extern const struct ethtool_ops mlx5e_ethtool_ops; |