Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
e8f887ac | 46 | #include <linux/rhashtable.h> |
f62b8bb8 | 47 | #include "wq.h" |
f62b8bb8 | 48 | #include "mlx5_core.h" |
9218b44d | 49 | #include "en_stats.h" |
f62b8bb8 | 50 | |
1cabe6b0 MG |
51 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
52 | ||
f62b8bb8 AV |
53 | #define MLX5E_MAX_NUM_TC 8 |
54 | ||
e842b100 | 55 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
56 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
57 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
58 | ||
e842b100 | 59 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
60 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
61 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
62 | ||
461017cb TT |
63 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1 |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4 | |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 | |
66 | ||
461017cb | 67 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */ |
d9d9f156 TT |
68 | #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */ |
69 | #define MLX5_MPWRQ_LOG_WQE_SZ 17 | |
461017cb TT |
70 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
71 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
72 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
73 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
74 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
bc77b240 TT |
75 | #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \ |
76 | BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW)) | |
77 | #define MLX5_UMR_ALIGN (2048) | |
461017cb TT |
78 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128) |
79 | ||
d9a40271 | 80 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
81 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
82 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
83 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
84 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
85 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 86 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 87 | |
936896e9 AS |
88 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
89 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
90 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
91 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
92 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 93 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 94 | |
86d722ad | 95 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 96 | |
461017cb TT |
97 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
98 | { | |
99 | switch (wq_type) { | |
100 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
101 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
102 | wq_size / 2); | |
103 | default: | |
104 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
105 | wq_size / 2); | |
106 | } | |
107 | } | |
108 | ||
109 | static inline int mlx5_min_log_rq_size(int wq_type) | |
110 | { | |
111 | switch (wq_type) { | |
112 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
113 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
114 | default: | |
115 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
116 | } | |
117 | } | |
118 | ||
119 | static inline int mlx5_max_log_rq_size(int wq_type) | |
120 | { | |
121 | switch (wq_type) { | |
122 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
123 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
124 | default: | |
125 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
126 | } | |
127 | } | |
128 | ||
2f48af12 TT |
129 | struct mlx5e_tx_wqe { |
130 | struct mlx5_wqe_ctrl_seg ctrl; | |
131 | struct mlx5_wqe_eth_seg eth; | |
132 | }; | |
133 | ||
134 | struct mlx5e_rx_wqe { | |
135 | struct mlx5_wqe_srq_next_seg next; | |
136 | struct mlx5_wqe_data_seg data; | |
137 | }; | |
86d722ad | 138 | |
bc77b240 TT |
139 | struct mlx5e_umr_wqe { |
140 | struct mlx5_wqe_ctrl_seg ctrl; | |
141 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
142 | struct mlx5_mkey_seg mkc; | |
143 | struct mlx5_wqe_data_seg data; | |
144 | }; | |
145 | ||
08fb1dac SM |
146 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
147 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
148 | #endif |
149 | ||
f62b8bb8 AV |
150 | struct mlx5e_params { |
151 | u8 log_sq_size; | |
461017cb | 152 | u8 rq_wq_type; |
d9d9f156 TT |
153 | u8 mpwqe_log_stride_sz; |
154 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
155 | u8 log_rq_size; |
156 | u16 num_channels; | |
f62b8bb8 | 157 | u8 num_tc; |
7219ab34 TT |
158 | bool rx_cqe_compress_admin; |
159 | bool rx_cqe_compress; | |
f62b8bb8 AV |
160 | u16 rx_cq_moderation_usec; |
161 | u16 rx_cq_moderation_pkts; | |
162 | u16 tx_cq_moderation_usec; | |
163 | u16 tx_cq_moderation_pkts; | |
164 | u16 min_rx_wqes; | |
f62b8bb8 AV |
165 | bool lro_en; |
166 | u32 lro_wqe_sz; | |
58d52291 | 167 | u16 tx_max_inline; |
2d75b2bc AS |
168 | u8 rss_hfunc; |
169 | u8 toeplitz_hash_key[40]; | |
170 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 171 | bool vlan_strip_disable; |
08fb1dac SM |
172 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
173 | struct ieee_ets ets; | |
174 | #endif | |
f62b8bb8 AV |
175 | }; |
176 | ||
ef9814de EBE |
177 | struct mlx5e_tstamp { |
178 | rwlock_t lock; | |
179 | struct cyclecounter cycles; | |
180 | struct timecounter clock; | |
181 | struct hwtstamp_config hwtstamp_config; | |
182 | u32 nominal_c_mult; | |
183 | unsigned long overflow_period; | |
184 | struct delayed_work overflow_work; | |
185 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
186 | struct ptp_clock *ptp; |
187 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
188 | }; |
189 | ||
f62b8bb8 AV |
190 | enum { |
191 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
bc77b240 | 192 | MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, |
6cd392a0 | 193 | MLX5E_RQ_STATE_FLUSH_TIMEOUT, |
f62b8bb8 AV |
194 | }; |
195 | ||
f62b8bb8 AV |
196 | struct mlx5e_cq { |
197 | /* data path - accessed per cqe */ | |
198 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
199 | |
200 | /* data path - accessed per napi poll */ | |
201 | struct napi_struct *napi; | |
202 | struct mlx5_core_cq mcq; | |
203 | struct mlx5e_channel *channel; | |
50cfa25a | 204 | struct mlx5e_priv *priv; |
f62b8bb8 | 205 | |
7219ab34 TT |
206 | /* cqe decompression */ |
207 | struct mlx5_cqe64 title; | |
208 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
209 | u8 mini_arr_idx; | |
210 | u16 decmprs_left; | |
211 | u16 decmprs_wqe_counter; | |
212 | ||
f62b8bb8 AV |
213 | /* control */ |
214 | struct mlx5_wq_ctrl wq_ctrl; | |
215 | } ____cacheline_aligned_in_smp; | |
216 | ||
2f48af12 TT |
217 | struct mlx5e_rq; |
218 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq, | |
219 | struct mlx5_cqe64 *cqe); | |
220 | typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, | |
221 | u16 ix); | |
222 | ||
6cd392a0 DJ |
223 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix); |
224 | ||
461017cb TT |
225 | struct mlx5e_dma_info { |
226 | struct page *page; | |
227 | dma_addr_t addr; | |
228 | }; | |
229 | ||
f62b8bb8 AV |
230 | struct mlx5e_rq { |
231 | /* data path */ | |
232 | struct mlx5_wq_ll wq; | |
233 | u32 wqe_sz; | |
234 | struct sk_buff **skb; | |
461017cb | 235 | struct mlx5e_mpw_info *wqe_info; |
bc77b240 TT |
236 | __be32 mkey_be; |
237 | __be32 umr_mkey_be; | |
f62b8bb8 AV |
238 | |
239 | struct device *pdev; | |
240 | struct net_device *netdev; | |
ef9814de | 241 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
242 | struct mlx5e_rq_stats stats; |
243 | struct mlx5e_cq cq; | |
2f48af12 TT |
244 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
245 | mlx5e_fp_alloc_wqe alloc_wqe; | |
6cd392a0 | 246 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
247 | |
248 | unsigned long state; | |
249 | int ix; | |
250 | ||
251 | /* control */ | |
252 | struct mlx5_wq_ctrl wq_ctrl; | |
461017cb | 253 | u8 wq_type; |
d9d9f156 TT |
254 | u32 mpwqe_stride_sz; |
255 | u32 mpwqe_num_strides; | |
f62b8bb8 AV |
256 | u32 rqn; |
257 | struct mlx5e_channel *channel; | |
50cfa25a | 258 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
259 | } ____cacheline_aligned_in_smp; |
260 | ||
bc77b240 TT |
261 | struct mlx5e_umr_dma_info { |
262 | __be64 *mtt; | |
263 | __be64 *mtt_no_align; | |
264 | dma_addr_t mtt_addr; | |
265 | struct mlx5e_dma_info *dma_info; | |
266 | }; | |
267 | ||
268 | struct mlx5e_mpw_info { | |
269 | union { | |
270 | struct mlx5e_dma_info dma_info; | |
271 | struct mlx5e_umr_dma_info umr; | |
272 | }; | |
273 | u16 consumed_strides; | |
274 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
275 | ||
276 | void (*dma_pre_sync)(struct device *pdev, | |
277 | struct mlx5e_mpw_info *wi, | |
278 | u32 wqe_offset, u32 len); | |
d9d9f156 | 279 | void (*add_skb_frag)(struct mlx5e_rq *rq, |
bc77b240 TT |
280 | struct sk_buff *skb, |
281 | struct mlx5e_mpw_info *wi, | |
282 | u32 page_idx, u32 frag_offset, u32 len); | |
283 | void (*copy_skb_header)(struct device *pdev, | |
284 | struct sk_buff *skb, | |
285 | struct mlx5e_mpw_info *wi, | |
286 | u32 page_idx, u32 offset, | |
287 | u32 headlen); | |
288 | void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); | |
289 | }; | |
290 | ||
34802a42 | 291 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
292 | u32 num_bytes; |
293 | u8 num_wqebbs; | |
294 | u8 num_dma; | |
295 | }; | |
296 | ||
d4e28cbd AS |
297 | enum mlx5e_dma_map_type { |
298 | MLX5E_DMA_MAP_SINGLE, | |
299 | MLX5E_DMA_MAP_PAGE | |
300 | }; | |
301 | ||
f62b8bb8 | 302 | struct mlx5e_sq_dma { |
d4e28cbd AS |
303 | dma_addr_t addr; |
304 | u32 size; | |
305 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
306 | }; |
307 | ||
308 | enum { | |
309 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
0ba42241 | 310 | MLX5E_SQ_STATE_BF_ENABLE, |
29429f33 | 311 | MLX5E_SQ_STATE_TX_TIMEOUT, |
f62b8bb8 AV |
312 | }; |
313 | ||
d3c9bc27 TT |
314 | struct mlx5e_ico_wqe_info { |
315 | u8 opcode; | |
316 | u8 num_wqebbs; | |
317 | }; | |
318 | ||
f62b8bb8 AV |
319 | struct mlx5e_sq { |
320 | /* data path */ | |
321 | ||
322 | /* dirtied @completion */ | |
323 | u16 cc; | |
324 | u32 dma_fifo_cc; | |
325 | ||
326 | /* dirtied @xmit */ | |
327 | u16 pc ____cacheline_aligned_in_smp; | |
328 | u32 dma_fifo_pc; | |
88a85f99 AS |
329 | u16 bf_offset; |
330 | u16 prev_cc; | |
331 | u8 bf_budget; | |
f62b8bb8 AV |
332 | struct mlx5e_sq_stats stats; |
333 | ||
334 | struct mlx5e_cq cq; | |
335 | ||
336 | /* pointers to per packet info: write@xmit, read@completion */ | |
337 | struct sk_buff **skb; | |
338 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 339 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
340 | |
341 | /* read only */ | |
342 | struct mlx5_wq_cyc wq; | |
343 | u32 dma_fifo_mask; | |
344 | void __iomem *uar_map; | |
345 | struct netdev_queue *txq; | |
346 | u32 sqn; | |
88a85f99 | 347 | u16 bf_buf_size; |
12be4b21 SM |
348 | u16 max_inline; |
349 | u16 edge; | |
f62b8bb8 | 350 | struct device *pdev; |
ef9814de | 351 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
352 | __be32 mkey_be; |
353 | unsigned long state; | |
354 | ||
355 | /* control path */ | |
356 | struct mlx5_wq_ctrl wq_ctrl; | |
357 | struct mlx5_uar uar; | |
358 | struct mlx5e_channel *channel; | |
359 | int tc; | |
d3c9bc27 | 360 | struct mlx5e_ico_wqe_info *ico_wqe_info; |
f62b8bb8 AV |
361 | } ____cacheline_aligned_in_smp; |
362 | ||
363 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
364 | { | |
365 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
366 | (sq->cc == sq->pc)); | |
367 | } | |
368 | ||
369 | enum channel_flags { | |
370 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
371 | }; | |
372 | ||
373 | struct mlx5e_channel { | |
374 | /* data path */ | |
375 | struct mlx5e_rq rq; | |
376 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
d3c9bc27 | 377 | struct mlx5e_sq icosq; /* internal control operations */ |
f62b8bb8 AV |
378 | struct napi_struct napi; |
379 | struct device *pdev; | |
380 | struct net_device *netdev; | |
381 | __be32 mkey_be; | |
382 | u8 num_tc; | |
383 | unsigned long flags; | |
384 | ||
385 | /* control */ | |
386 | struct mlx5e_priv *priv; | |
387 | int ix; | |
388 | int cpu; | |
389 | }; | |
390 | ||
391 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
392 | MLX5E_TT_IPV4_TCP, |
393 | MLX5E_TT_IPV6_TCP, | |
394 | MLX5E_TT_IPV4_UDP, | |
395 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
396 | MLX5E_TT_IPV4_IPSEC_AH, |
397 | MLX5E_TT_IPV6_IPSEC_AH, | |
398 | MLX5E_TT_IPV4_IPSEC_ESP, | |
399 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
400 | MLX5E_TT_IPV4, |
401 | MLX5E_TT_IPV6, | |
402 | MLX5E_TT_ANY, | |
403 | MLX5E_NUM_TT, | |
1da36696 | 404 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
405 | }; |
406 | ||
acff797c | 407 | enum { |
e0f46eb9 | 408 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
409 | MLX5E_STATE_OPENED, |
410 | MLX5E_STATE_DESTROYING, | |
411 | }; | |
412 | ||
413 | struct mlx5e_vxlan_db { | |
414 | spinlock_t lock; /* protect vxlan table */ | |
415 | struct radix_tree_root tree; | |
416 | }; | |
417 | ||
33cfaaa8 | 418 | struct mlx5e_l2_rule { |
f62b8bb8 | 419 | u8 addr[ETH_ALEN + 2]; |
33cfaaa8 | 420 | struct mlx5_flow_rule *rule; |
f62b8bb8 AV |
421 | }; |
422 | ||
acff797c MG |
423 | struct mlx5e_flow_table { |
424 | int num_groups; | |
425 | struct mlx5_flow_table *t; | |
426 | struct mlx5_flow_group **g; | |
427 | }; | |
428 | ||
33cfaaa8 | 429 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 430 | |
acff797c MG |
431 | struct mlx5e_tc_table { |
432 | struct mlx5_flow_table *t; | |
433 | ||
434 | struct rhashtable_params ht_params; | |
435 | struct rhashtable ht; | |
f62b8bb8 AV |
436 | }; |
437 | ||
acff797c MG |
438 | struct mlx5e_vlan_table { |
439 | struct mlx5e_flow_table ft; | |
aad9e6e4 | 440 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
441 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
442 | struct mlx5_flow_rule *untagged_rule; | |
443 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
444 | bool filter_disabled; |
445 | }; | |
446 | ||
33cfaaa8 MG |
447 | struct mlx5e_l2_table { |
448 | struct mlx5e_flow_table ft; | |
449 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
450 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
451 | struct mlx5e_l2_rule broadcast; | |
452 | struct mlx5e_l2_rule allmulti; | |
453 | struct mlx5e_l2_rule promisc; | |
454 | bool broadcast_enabled; | |
455 | bool allmulti_enabled; | |
456 | bool promisc_enabled; | |
457 | }; | |
458 | ||
459 | /* L3/L4 traffic type classifier */ | |
460 | struct mlx5e_ttc_table { | |
461 | struct mlx5e_flow_table ft; | |
462 | struct mlx5_flow_rule *rules[MLX5E_NUM_TT]; | |
463 | }; | |
464 | ||
18c908e4 MG |
465 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
466 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
467 | struct arfs_table { |
468 | struct mlx5e_flow_table ft; | |
469 | struct mlx5_flow_rule *default_rule; | |
18c908e4 | 470 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
471 | }; |
472 | ||
473 | enum arfs_type { | |
474 | ARFS_IPV4_TCP, | |
475 | ARFS_IPV6_TCP, | |
476 | ARFS_IPV4_UDP, | |
477 | ARFS_IPV6_UDP, | |
478 | ARFS_NUM_TYPES, | |
479 | }; | |
480 | ||
481 | struct mlx5e_arfs_tables { | |
482 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
483 | /* Protect aRFS rules list */ |
484 | spinlock_t arfs_lock; | |
485 | struct list_head rules; | |
486 | int last_filter_id; | |
487 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
488 | }; |
489 | ||
490 | /* NIC prio FTS */ | |
491 | enum { | |
492 | MLX5E_VLAN_FT_LEVEL = 0, | |
493 | MLX5E_L2_FT_LEVEL, | |
494 | MLX5E_TTC_FT_LEVEL, | |
495 | MLX5E_ARFS_FT_LEVEL | |
496 | }; | |
497 | ||
acff797c MG |
498 | struct mlx5e_flow_steering { |
499 | struct mlx5_flow_namespace *ns; | |
500 | struct mlx5e_tc_table tc; | |
501 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
502 | struct mlx5e_l2_table l2; |
503 | struct mlx5e_ttc_table ttc; | |
1cabe6b0 | 504 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
505 | }; |
506 | ||
1da36696 TT |
507 | struct mlx5e_direct_tir { |
508 | u32 tirn; | |
509 | u32 rqtn; | |
510 | }; | |
511 | ||
acff797c MG |
512 | enum { |
513 | MLX5E_TC_PRIO = 0, | |
514 | MLX5E_NIC_PRIO | |
515 | }; | |
516 | ||
f62b8bb8 AV |
517 | struct mlx5e_priv { |
518 | /* priv data path fields - start */ | |
03289b88 | 519 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 520 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
521 | /* priv data path fields - end */ |
522 | ||
523 | unsigned long state; | |
524 | struct mutex state_lock; /* Protects Interface state */ | |
525 | struct mlx5_uar cq_uar; | |
526 | u32 pdn; | |
3191e05f | 527 | u32 tdn; |
a606b0f6 | 528 | struct mlx5_core_mkey mkey; |
bc77b240 | 529 | struct mlx5_core_mkey umr_mkey; |
50cfa25a | 530 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
531 | |
532 | struct mlx5e_channel **channel; | |
533 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
1da36696 TT |
534 | u32 indir_rqtn; |
535 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
536 | struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; | |
f62b8bb8 | 537 | |
acff797c | 538 | struct mlx5e_flow_steering fs; |
b3f63c3d | 539 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 AV |
540 | |
541 | struct mlx5e_params params; | |
7bb29755 | 542 | struct workqueue_struct *wq; |
f62b8bb8 AV |
543 | struct work_struct update_carrier_work; |
544 | struct work_struct set_rx_mode_work; | |
3947ca18 | 545 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
546 | struct delayed_work update_stats_work; |
547 | ||
548 | struct mlx5_core_dev *mdev; | |
549 | struct net_device *netdev; | |
550 | struct mlx5e_stats stats; | |
ef9814de | 551 | struct mlx5e_tstamp tstamp; |
593cf338 | 552 | u16 q_counter; |
f62b8bb8 AV |
553 | }; |
554 | ||
f62b8bb8 AV |
555 | enum mlx5e_link_mode { |
556 | MLX5E_1000BASE_CX_SGMII = 0, | |
557 | MLX5E_1000BASE_KX = 1, | |
558 | MLX5E_10GBASE_CX4 = 2, | |
559 | MLX5E_10GBASE_KX4 = 3, | |
560 | MLX5E_10GBASE_KR = 4, | |
561 | MLX5E_20GBASE_KR2 = 5, | |
562 | MLX5E_40GBASE_CR4 = 6, | |
563 | MLX5E_40GBASE_KR4 = 7, | |
564 | MLX5E_56GBASE_R4 = 8, | |
565 | MLX5E_10GBASE_CR = 12, | |
566 | MLX5E_10GBASE_SR = 13, | |
567 | MLX5E_10GBASE_ER = 14, | |
568 | MLX5E_40GBASE_SR4 = 15, | |
569 | MLX5E_40GBASE_LR4 = 16, | |
570 | MLX5E_100GBASE_CR4 = 20, | |
571 | MLX5E_100GBASE_SR4 = 21, | |
572 | MLX5E_100GBASE_KR4 = 22, | |
573 | MLX5E_100GBASE_LR4 = 23, | |
574 | MLX5E_100BASE_TX = 24, | |
6e4c2189 | 575 | MLX5E_1000BASE_T = 25, |
f62b8bb8 AV |
576 | MLX5E_10GBASE_T = 26, |
577 | MLX5E_25GBASE_CR = 27, | |
578 | MLX5E_25GBASE_KR = 28, | |
579 | MLX5E_25GBASE_SR = 29, | |
580 | MLX5E_50GBASE_CR2 = 30, | |
581 | MLX5E_50GBASE_KR2 = 31, | |
582 | MLX5E_LINK_MODES_NUMBER, | |
583 | }; | |
584 | ||
585 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
586 | ||
12be4b21 | 587 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
588 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
589 | void *accel_priv, select_queue_fallback_t fallback); | |
590 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
591 | |
592 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
593 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
594 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 595 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 596 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
29429f33 | 597 | void mlx5e_free_tx_descs(struct mlx5e_sq *sq); |
6cd392a0 | 598 | void mlx5e_free_rx_descs(struct mlx5e_rq *rq); |
461017cb | 599 | |
2f48af12 | 600 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 601 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 602 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
2f48af12 | 603 | int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
461017cb | 604 | int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix); |
6cd392a0 DJ |
605 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
606 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
bc77b240 TT |
607 | void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq); |
608 | void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
609 | struct mlx5_cqe64 *cqe, | |
610 | u16 byte_cnt, | |
611 | struct mlx5e_mpw_info *wi, | |
612 | struct sk_buff *skb); | |
613 | void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
614 | struct mlx5_cqe64 *cqe, | |
615 | u16 byte_cnt, | |
616 | struct mlx5e_mpw_info *wi, | |
617 | struct sk_buff *skb); | |
618 | void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq, | |
619 | struct mlx5e_mpw_info *wi); | |
620 | void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, | |
621 | struct mlx5e_mpw_info *wi); | |
f62b8bb8 AV |
622 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); |
623 | ||
624 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
625 | ||
acff797c MG |
626 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
627 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 628 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 629 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
f62b8bb8 AV |
630 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
631 | ||
ef9814de EBE |
632 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
633 | struct skb_shared_hwtstamps *hwts); | |
634 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
635 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
636 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
637 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
7219ab34 | 638 | void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val); |
ef9814de | 639 | |
f62b8bb8 AV |
640 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
641 | u16 vid); | |
642 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
643 | u16 vid); | |
644 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
645 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 646 | |
36350114 GP |
647 | int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd); |
648 | ||
1da36696 | 649 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix); |
bdfc028d | 650 | void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv); |
2d75b2bc | 651 | |
f62b8bb8 AV |
652 | int mlx5e_open_locked(struct net_device *netdev); |
653 | int mlx5e_close_locked(struct net_device *netdev); | |
d8c9660d TT |
654 | void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, |
655 | u32 *indirection_rqt, int len, | |
85082dba | 656 | int num_channels); |
b797a684 | 657 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 AV |
658 | |
659 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
bc77b240 | 660 | struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz) |
f62b8bb8 | 661 | { |
88a85f99 AS |
662 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
663 | ||
f62b8bb8 AV |
664 | /* ensure wqe is visible to device before updating doorbell record */ |
665 | dma_wmb(); | |
666 | ||
667 | *sq->wq.db = cpu_to_be32(sq->pc); | |
668 | ||
669 | /* ensure doorbell record is visible to device before ringing the | |
670 | * doorbell | |
671 | */ | |
672 | wmb(); | |
0ba42241 | 673 | if (bf_sz) |
bc77b240 | 674 | __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz); |
0ba42241 | 675 | else |
bc77b240 | 676 | mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL); |
0ba42241 ML |
677 | /* flush the write-combining mapped buffer */ |
678 | wmb(); | |
f62b8bb8 AV |
679 | |
680 | sq->bf_offset ^= sq->bf_buf_size; | |
681 | } | |
682 | ||
683 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
684 | { | |
685 | struct mlx5_core_cq *mcq; | |
686 | ||
687 | mcq = &cq->mcq; | |
688 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
689 | } | |
690 | ||
3435ab59 AS |
691 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
692 | { | |
693 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
694 | MLX5E_MAX_NUM_CHANNELS); | |
695 | } | |
696 | ||
bc77b240 TT |
697 | static inline int mlx5e_get_mtt_octw(int npages) |
698 | { | |
699 | return ALIGN(npages, 8) / 2; | |
700 | } | |
701 | ||
f62b8bb8 | 702 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
703 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
704 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
705 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
706 | #endif | |
707 | ||
1cabe6b0 MG |
708 | #ifndef CONFIG_RFS_ACCEL |
709 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
710 | { | |
711 | return 0; | |
712 | } | |
713 | ||
714 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
715 | |
716 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
717 | { | |
718 | return -ENOTSUPP; | |
719 | } | |
720 | ||
721 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
722 | { | |
723 | return -ENOTSUPP; | |
724 | } | |
1cabe6b0 MG |
725 | #else |
726 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
727 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
728 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
729 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
730 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
731 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
732 | #endif |
733 | ||
58d52291 | 734 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
1afff42c MF |
735 | |
736 | #endif /* __MLX5_EN_H__ */ |