[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h

/*
 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __MLX5_EN_H__
#define __MLX5_EN_H__

#include <linux/if_vlan.h>
#include <linux/etherdevice.h>
#include <linux/timecounter.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/cq.h>
#include <linux/mlx5/port.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/transobj.h>
#include "wq.h"
#include "mlx5_core.h"

#define MLX5E_MAX_NUM_TC	8

#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd

#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd

#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80

#define MLX5E_LOG_INDIR_RQT_SIZE       0x7
#define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
#define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
#define MLX5E_TX_CQ_POLL_BUDGET        128
#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
#define MLX5E_SQ_BF_BUDGET             16

#define MLX5E_NUM_MAIN_GROUPS 9

#ifdef CONFIG_MLX5_CORE_EN_DCB
#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
#define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
#endif

static const char vport_strings[][ETH_GSTRING_LEN] = {
	/* vport statistics */
	"rx_packets",
	"rx_bytes",
	"tx_packets",
	"tx_bytes",
	"rx_error_packets",
	"rx_error_bytes",
	"tx_error_packets",
	"tx_error_bytes",
	"rx_unicast_packets",
	"rx_unicast_bytes",
	"tx_unicast_packets",
	"tx_unicast_bytes",
	"rx_multicast_packets",
	"rx_multicast_bytes",
	"tx_multicast_packets",
	"tx_multicast_bytes",
	"rx_broadcast_packets",
	"rx_broadcast_bytes",
	"tx_broadcast_packets",
	"tx_broadcast_bytes",

	/* SW counters */
	"tso_packets",
	"tso_bytes",
	"tso_inner_packets",
	"tso_inner_bytes",
	"lro_packets",
	"lro_bytes",
	"rx_csum_good",
	"rx_csum_none",
	"rx_csum_sw",
	"tx_csum_offload",
	"tx_csum_inner",
	"tx_queue_stopped",
	"tx_queue_wake",
	"tx_queue_dropped",
	"rx_wqe_err",
};

struct mlx5e_vport_stats {
	/* HW counters */
	u64 rx_packets;
	u64 rx_bytes;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_error_packets;
	u64 rx_error_bytes;
	u64 tx_error_packets;
	u64 tx_error_bytes;
	u64 rx_unicast_packets;
	u64 rx_unicast_bytes;
	u64 tx_unicast_packets;
	u64 tx_unicast_bytes;
	u64 rx_multicast_packets;
	u64 rx_multicast_bytes;
	u64 tx_multicast_packets;
	u64 tx_multicast_bytes;
	u64 rx_broadcast_packets;
	u64 rx_broadcast_bytes;
	u64 tx_broadcast_packets;
	u64 tx_broadcast_bytes;

	/* SW counters */
	u64 tso_packets;
	u64 tso_bytes;
	u64 tso_inner_packets;
	u64 tso_inner_bytes;
	u64 lro_packets;
	u64 lro_bytes;
	u64 rx_csum_good;
	u64 rx_csum_none;
	u64 rx_csum_sw;
	u64 tx_csum_offload;
	u64 tx_csum_inner;
	u64 tx_queue_stopped;
	u64 tx_queue_wake;
	u64 tx_queue_dropped;
	u64 rx_wqe_err;

#define NUM_VPORT_COUNTERS     35
};

static const char pport_strings[][ETH_GSTRING_LEN] = {
	/* IEEE802.3 counters */
	"frames_tx",
	"frames_rx",
	"check_seq_err",
	"alignment_err",
	"octets_tx",
	"octets_received",
	"multicast_xmitted",
	"broadcast_xmitted",
	"multicast_rx",
	"broadcast_rx",
	"in_range_len_errors",
	"out_of_range_len",
	"too_long_errors",
	"symbol_err",
	"mac_control_tx",
	"mac_control_rx",
	"unsupported_op_rx",
	"pause_ctrl_rx",
	"pause_ctrl_tx",

	/* RFC2863 counters */
	"in_octets",
	"in_ucast_pkts",
	"in_discards",
	"in_errors",
	"in_unknown_protos",
	"out_octets",
	"out_ucast_pkts",
	"out_discards",
	"out_errors",
	"in_multicast_pkts",
	"in_broadcast_pkts",
	"out_multicast_pkts",
	"out_broadcast_pkts",

	/* RFC2819 counters */
	"drop_events",
	"octets",
	"pkts",
	"broadcast_pkts",
	"multicast_pkts",
	"crc_align_errors",
	"undersize_pkts",
	"oversize_pkts",
	"fragments",
	"jabbers",
	"collisions",
	"p64octets",
	"p65to127octets",
	"p128to255octets",
	"p256to511octets",
	"p512to1023octets",
	"p1024to1518octets",
	"p1519to2047octets",
	"p2048to4095octets",
	"p4096to8191octets",
	"p8192to10239octets",
};

#define NUM_IEEE_802_3_COUNTERS		19
#define NUM_RFC_2863_COUNTERS		13
#define NUM_RFC_2819_COUNTERS		21
#define NUM_PPORT_COUNTERS		(NUM_IEEE_802_3_COUNTERS + \
					 NUM_RFC_2863_COUNTERS + \
					 NUM_RFC_2819_COUNTERS)

struct mlx5e_pport_stats {
	__be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
	__be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
	__be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
};

static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
	"packets",
	"csum_none",
	"csum_sw",
	"lro_packets",
	"lro_bytes",
	"wqe_err"
};

struct mlx5e_rq_stats {
	u64 packets;
	u64 csum_none;
	u64 csum_sw;
	u64 lro_packets;
	u64 lro_bytes;
	u64 wqe_err;
#define NUM_RQ_STATS 6
};

static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
	"packets",
	"tso_packets",
	"tso_bytes",
	"tso_inner_packets",
	"tso_inner_bytes",
	"csum_offload_inner",
	"nop",
	"csum_offload_none",
	"stopped",
	"wake",
	"dropped",
};

struct mlx5e_sq_stats {
	/* commonly accessed in data path */
	u64 packets;
	u64 tso_packets;
	u64 tso_bytes;
	u64 tso_inner_packets;
	u64 tso_inner_bytes;
	u64 csum_offload_inner;
	u64 nop;
	/* less likely accessed in data path */
	u64 csum_offload_none;
	u64 stopped;
	u64 wake;
	u64 dropped;
#define NUM_SQ_STATS 11
};

struct mlx5e_stats {
	struct mlx5e_vport_stats   vport;
	struct mlx5e_pport_stats   pport;
};

struct mlx5e_params {
	u8  log_sq_size;
	u8  log_rq_size;
	u16 num_channels;
	u8  num_tc;
	u16 rx_cq_moderation_usec;
	u16 rx_cq_moderation_pkts;
	u16 tx_cq_moderation_usec;
	u16 tx_cq_moderation_pkts;
	u16 min_rx_wqes;
	bool lro_en;
	u32 lro_wqe_sz;
	u16 tx_max_inline;
	u8  rss_hfunc;
	u8  toeplitz_hash_key[40];
	u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
#ifdef CONFIG_MLX5_CORE_EN_DCB
	struct ieee_ets ets;
#endif
};

struct mlx5e_tstamp {
	rwlock_t                   lock;
	struct cyclecounter        cycles;
	struct timecounter         clock;
	struct hwtstamp_config     hwtstamp_config;
	u32                        nominal_c_mult;
	unsigned long              overflow_period;
	struct delayed_work        overflow_work;
	struct mlx5_core_dev      *mdev;
	struct ptp_clock          *ptp;
	struct ptp_clock_info      ptp_info;
};

enum {
	MLX5E_RQ_STATE_POST_WQES_ENABLE,
};

enum cq_flags {
	MLX5E_CQ_HAS_CQES = 1,
};

struct mlx5e_cq {
	/* data path - accessed per cqe */
	struct mlx5_cqwq           wq;
	unsigned long              flags;

	/* data path - accessed per napi poll */
	struct napi_struct        *napi;
	struct mlx5_core_cq        mcq;
	struct mlx5e_channel      *channel;
	struct mlx5e_priv         *priv;

	/* control */
	struct mlx5_wq_ctrl        wq_ctrl;
} ____cacheline_aligned_in_smp;

struct mlx5e_rq {
	/* data path */
	struct mlx5_wq_ll      wq;
	u32                    wqe_sz;
	struct sk_buff       **skb;

	struct device         *pdev;
	struct net_device     *netdev;
	struct mlx5e_tstamp   *tstamp;
	struct mlx5e_rq_stats  stats;
	struct mlx5e_cq        cq;

	unsigned long          state;
	int                    ix;

	/* control */
	struct mlx5_wq_ctrl    wq_ctrl;
	u32                    rqn;
	struct mlx5e_channel  *channel;
	struct mlx5e_priv     *priv;
} ____cacheline_aligned_in_smp;

struct mlx5e_tx_wqe_info {
	u32 num_bytes;
	u8  num_wqebbs;
	u8  num_dma;
};

enum mlx5e_dma_map_type {
	MLX5E_DMA_MAP_SINGLE,
	MLX5E_DMA_MAP_PAGE
};

struct mlx5e_sq_dma {
	dma_addr_t              addr;
	u32                     size;
	enum mlx5e_dma_map_type type;
};

enum {
	MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
};

struct mlx5e_sq {
	/* data path */

	/* dirtied @completion */
	u16                        cc;
	u32                        dma_fifo_cc;

	/* dirtied @xmit */
	u16                        pc ____cacheline_aligned_in_smp;
	u32                        dma_fifo_pc;
	u16                        bf_offset;
	u16                        prev_cc;
	u8                         bf_budget;
	struct mlx5e_sq_stats      stats;

	struct mlx5e_cq            cq;

	/* pointers to per packet info: write@xmit, read@completion */
	struct sk_buff           **skb;
	struct mlx5e_sq_dma       *dma_fifo;
	struct mlx5e_tx_wqe_info  *wqe_info;

	/* read only */
	struct mlx5_wq_cyc         wq;
	u32                        dma_fifo_mask;
	void __iomem              *uar_map;
	void __iomem              *uar_bf_map;
	struct netdev_queue       *txq;
	u32                        sqn;
	u16                        bf_buf_size;
	u16                        max_inline;
	u16                        edge;
	struct device             *pdev;
	struct mlx5e_tstamp       *tstamp;
	__be32                     mkey_be;
	unsigned long              state;

	/* control path */
	struct mlx5_wq_ctrl        wq_ctrl;
	struct mlx5_uar            uar;
	struct mlx5e_channel      *channel;
	int                        tc;
} ____cacheline_aligned_in_smp;

static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
{
	return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
		(sq->cc  == sq->pc));
}

enum channel_flags {
	MLX5E_CHANNEL_NAPI_SCHED = 1,
};

struct mlx5e_channel {
	/* data path */
	struct mlx5e_rq            rq;
	struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
	struct napi_struct         napi;
	struct device             *pdev;
	struct net_device         *netdev;
	__be32                     mkey_be;
	u8                         num_tc;
	unsigned long              flags;

	/* control */
	struct mlx5e_priv         *priv;
	int                        ix;
	int                        cpu;
};

enum mlx5e_traffic_types {
	MLX5E_TT_IPV4_TCP,
	MLX5E_TT_IPV6_TCP,
	MLX5E_TT_IPV4_UDP,
	MLX5E_TT_IPV6_UDP,
	MLX5E_TT_IPV4_IPSEC_AH,
	MLX5E_TT_IPV6_IPSEC_AH,
	MLX5E_TT_IPV4_IPSEC_ESP,
	MLX5E_TT_IPV6_IPSEC_ESP,
	MLX5E_TT_IPV4,
	MLX5E_TT_IPV6,
	MLX5E_TT_ANY,
	MLX5E_NUM_TT,
};

enum mlx5e_rqt_ix {
	MLX5E_INDIRECTION_RQT,
	MLX5E_SINGLE_RQ_RQT,
	MLX5E_NUM_RQT,
};

struct mlx5e_eth_addr_info {
	u8  addr[ETH_ALEN + 2];
	u32 tt_vec;
	struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
};

#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)

struct mlx5e_eth_addr_db {
	struct hlist_head          netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
	struct hlist_head          netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
	struct mlx5e_eth_addr_info broadcast;
	struct mlx5e_eth_addr_info allmulti;
	struct mlx5e_eth_addr_info promisc;
	bool                       broadcast_enabled;
	bool                       allmulti_enabled;
	bool                       promisc_enabled;
};

enum {
	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
	MLX5E_STATE_OPENED,
	MLX5E_STATE_DESTROYING,
};

struct mlx5e_vlan_db {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct mlx5_flow_rule	*active_vlans_rule[VLAN_N_VID];
	struct mlx5_flow_rule	*untagged_rule;
	struct mlx5_flow_rule	*any_vlan_rule;
	bool          filter_disabled;
};

struct mlx5e_vxlan_db {
	spinlock_t			lock; /* protect vxlan table */
	struct radix_tree_root		tree;
};

struct mlx5e_flow_table {
	int num_groups;
	struct mlx5_flow_table		*t;
	struct mlx5_flow_group		**g;
};

struct mlx5e_flow_tables {
	struct mlx5_flow_namespace	*ns;
	struct mlx5e_flow_table		vlan;
	struct mlx5e_flow_table		main;
};

struct mlx5e_priv {
	/* priv data path fields - start */
	struct mlx5e_sq            **txq_to_sq_map;
	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
	/* priv data path fields - end */

	unsigned long              state;
	struct mutex               state_lock; /* Protects Interface state */
	struct mlx5_uar            cq_uar;
	u32                        pdn;
	u32                        tdn;
	struct mlx5_core_mr        mr;
	struct mlx5e_rq            drop_rq;

	struct mlx5e_channel     **channel;
	u32                        tisn[MLX5E_MAX_NUM_TC];
	u32                        rqtn[MLX5E_NUM_RQT];
	u32                        tirn[MLX5E_NUM_TT];

	struct mlx5e_flow_tables   fts;
	struct mlx5e_eth_addr_db   eth_addr;
	struct mlx5e_vlan_db       vlan;
	struct mlx5e_vxlan_db      vxlan;

	struct mlx5e_params        params;
	struct work_struct         update_carrier_work;
	struct work_struct         set_rx_mode_work;
	struct delayed_work        update_stats_work;

	struct mlx5_core_dev      *mdev;
	struct net_device         *netdev;
	struct mlx5e_stats         stats;
	struct mlx5e_tstamp        tstamp;
};

#define MLX5E_NET_IP_ALIGN 2

struct mlx5e_tx_wqe {
	struct mlx5_wqe_ctrl_seg ctrl;
	struct mlx5_wqe_eth_seg  eth;
};

struct mlx5e_rx_wqe {
	struct mlx5_wqe_srq_next_seg  next;
	struct mlx5_wqe_data_seg      data;
};

enum mlx5e_link_mode {
	MLX5E_1000BASE_CX_SGMII	 = 0,
	MLX5E_1000BASE_KX	 = 1,
	MLX5E_10GBASE_CX4	 = 2,
	MLX5E_10GBASE_KX4	 = 3,
	MLX5E_10GBASE_KR	 = 4,
	MLX5E_20GBASE_KR2	 = 5,
	MLX5E_40GBASE_CR4	 = 6,
	MLX5E_40GBASE_KR4	 = 7,
	MLX5E_56GBASE_R4	 = 8,
	MLX5E_10GBASE_CR	 = 12,
	MLX5E_10GBASE_SR	 = 13,
	MLX5E_10GBASE_ER	 = 14,
	MLX5E_40GBASE_SR4	 = 15,
	MLX5E_40GBASE_LR4	 = 16,
	MLX5E_100GBASE_CR4	 = 20,
	MLX5E_100GBASE_SR4	 = 21,
	MLX5E_100GBASE_KR4	 = 22,
	MLX5E_100GBASE_LR4	 = 23,
	MLX5E_100BASE_TX	 = 24,
	MLX5E_100BASE_T		 = 25,
	MLX5E_10GBASE_T		 = 26,
	MLX5E_25GBASE_CR	 = 27,
	MLX5E_25GBASE_KR	 = 28,
	MLX5E_25GBASE_SR	 = 29,
	MLX5E_50GBASE_CR2	 = 30,
	MLX5E_50GBASE_KR2	 = 31,
	MLX5E_LINK_MODES_NUMBER,
};

#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)

void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
		       void *accel_priv, select_queue_fallback_t fallback);
netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);

void mlx5e_completion_event(struct mlx5_core_cq *mcq);
void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
int mlx5e_napi_poll(struct napi_struct *napi, int budget);
bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);

void mlx5e_update_stats(struct mlx5e_priv *priv);

int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
void mlx5e_set_rx_mode_work(struct work_struct *work);

void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
			struct skb_shared_hwtstamps *hwts);
void mlx5e_timestamp_init(struct mlx5e_priv *priv);
void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);

int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
			  u16 vid);
int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
			   u16 vid);
void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);

int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);

int mlx5e_open_locked(struct net_device *netdev);
int mlx5e_close_locked(struct net_device *netdev);

static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
				      struct mlx5e_tx_wqe *wqe, int bf_sz)
{
	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;

	/* ensure wqe is visible to device before updating doorbell record */
	dma_wmb();

	*sq->wq.db = cpu_to_be32(sq->pc);

	/* ensure doorbell record is visible to device before ringing the
	 * doorbell
	 */
	wmb();

	if (bf_sz) {
		__iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);

		/* flush the write-combining mapped buffer */
		wmb();

	} else {
		mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
	}

	sq->bf_offset ^= sq->bf_buf_size;
}

static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
{
	struct mlx5_core_cq *mcq;

	mcq = &cq->mcq;
	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
}

static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
{
	return min_t(int, mdev->priv.eq_table.num_comp_vectors,
		     MLX5E_MAX_NUM_CHANNELS);
}

extern const struct ethtool_ops mlx5e_ethtool_ops;
#ifdef CONFIG_MLX5_CORE_EN_DCB
extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
#endif

u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);

#endif /* __MLX5_EN_H__ */
Commit	Line	Data
f62b8bb8	1	/*
1afff42c	2	* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8 AV	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
1afff42c MF	32	#ifndef __MLX5_EN_H__
1afff42c MF	33	#define __MLX5_EN_H__
f62b8bb8 AV	34
	35	#include <linux/if_vlan.h>
	36	#include <linux/etherdevice.h>
ef9814de EBE	37	#include <linux/timecounter.h>
ef9814de EBE	38	#include <linux/net_tstamp.h>
3d8c38af	39	#include <linux/ptp_clock_kernel.h>
f62b8bb8 AV	40	#include <linux/mlx5/driver.h>
	41	#include <linux/mlx5/qp.h>
	42	#include <linux/mlx5/cq.h>
ada68c31	43	#include <linux/mlx5/port.h>
d18a9470	44	#include <linux/mlx5/vport.h>
8d7f9ecb	45	#include <linux/mlx5/transobj.h>
f62b8bb8	46	#include "wq.h"
f62b8bb8 AV	47	#include "mlx5_core.h"
	48
	49	#define MLX5E_MAX_NUM_TC 8
	50
e842b100	51	#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
f62b8bb8 AV	52	#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
	53	#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
	54
e842b100	55	#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
f62b8bb8 AV	56	#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
	57	#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
	58
d9a40271	59	#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
f62b8bb8 AV	60	#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
	61	#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
	62	#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
	63	#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
	64	#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
f62b8bb8	65
936896e9 AS	66	#define MLX5E_LOG_INDIR_RQT_SIZE 0x7
	67	#define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
	68	#define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
f62b8bb8 AV	69	#define MLX5E_TX_CQ_POLL_BUDGET 128
f62b8bb8 AV	70	#define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
88a85f99	71	#define MLX5E_SQ_BF_BUDGET 16
f62b8bb8	72
86d722ad MG	73	#define MLX5E_NUM_MAIN_GROUPS 9
86d722ad MG	74
08fb1dac SM	75	#ifdef CONFIG_MLX5_CORE_EN_DCB
	76	#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
	77	#define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
	78	#endif
	79
f62b8bb8 AV	80	static const char vport_strings[][ETH_GSTRING_LEN] = {
	81	/* vport statistics */
	82	"rx_packets",
	83	"rx_bytes",
	84	"tx_packets",
	85	"tx_bytes",
	86	"rx_error_packets",
	87	"rx_error_bytes",
	88	"tx_error_packets",
	89	"tx_error_bytes",
	90	"rx_unicast_packets",
	91	"rx_unicast_bytes",
	92	"tx_unicast_packets",
	93	"tx_unicast_bytes",
	94	"rx_multicast_packets",
	95	"rx_multicast_bytes",
	96	"tx_multicast_packets",
	97	"tx_multicast_bytes",
	98	"rx_broadcast_packets",
	99	"rx_broadcast_bytes",
	100	"tx_broadcast_packets",
	101	"tx_broadcast_bytes",
	102
	103	/* SW counters */
	104	"tso_packets",
	105	"tso_bytes",
89db09eb MF	106	"tso_inner_packets",
89db09eb MF	107	"tso_inner_bytes",
f62b8bb8 AV	108	"lro_packets",
	109	"lro_bytes",
	110	"rx_csum_good",
	111	"rx_csum_none",
bbceefce	112	"rx_csum_sw",
f62b8bb8	113	"tx_csum_offload",
89db09eb	114	"tx_csum_inner",
f62b8bb8 AV	115	"tx_queue_stopped",
	116	"tx_queue_wake",
	117	"tx_queue_dropped",
	118	"rx_wqe_err",
	119	};
	120
	121	struct mlx5e_vport_stats {
	122	/* HW counters */
	123	u64 rx_packets;
	124	u64 rx_bytes;
	125	u64 tx_packets;
	126	u64 tx_bytes;
	127	u64 rx_error_packets;
	128	u64 rx_error_bytes;
	129	u64 tx_error_packets;
	130	u64 tx_error_bytes;
	131	u64 rx_unicast_packets;
	132	u64 rx_unicast_bytes;
	133	u64 tx_unicast_packets;
	134	u64 tx_unicast_bytes;
	135	u64 rx_multicast_packets;
	136	u64 rx_multicast_bytes;
	137	u64 tx_multicast_packets;
	138	u64 tx_multicast_bytes;
	139	u64 rx_broadcast_packets;
	140	u64 rx_broadcast_bytes;
	141	u64 tx_broadcast_packets;
	142	u64 tx_broadcast_bytes;
	143
	144	/* SW counters */
	145	u64 tso_packets;
	146	u64 tso_bytes;
89db09eb MF	147	u64 tso_inner_packets;
89db09eb MF	148	u64 tso_inner_bytes;
f62b8bb8 AV	149	u64 lro_packets;
	150	u64 lro_bytes;
	151	u64 rx_csum_good;
	152	u64 rx_csum_none;
bbceefce	153	u64 rx_csum_sw;
f62b8bb8	154	u64 tx_csum_offload;
89db09eb	155	u64 tx_csum_inner;
f62b8bb8 AV	156	u64 tx_queue_stopped;
	157	u64 tx_queue_wake;
	158	u64 tx_queue_dropped;
	159	u64 rx_wqe_err;
	160
89db09eb	161	#define NUM_VPORT_COUNTERS 35
f62b8bb8 AV	162	};
f62b8bb8 AV	163
efea389d GP	164	static const char pport_strings[][ETH_GSTRING_LEN] = {
	165	/* IEEE802.3 counters */
	166	"frames_tx",
	167	"frames_rx",
	168	"check_seq_err",
	169	"alignment_err",
	170	"octets_tx",
	171	"octets_received",
	172	"multicast_xmitted",
	173	"broadcast_xmitted",
	174	"multicast_rx",
	175	"broadcast_rx",
	176	"in_range_len_errors",
	177	"out_of_range_len",
	178	"too_long_errors",
	179	"symbol_err",
	180	"mac_control_tx",
	181	"mac_control_rx",
	182	"unsupported_op_rx",
	183	"pause_ctrl_rx",
	184	"pause_ctrl_tx",
	185
	186	/* RFC2863 counters */
	187	"in_octets",
	188	"in_ucast_pkts",
	189	"in_discards",
	190	"in_errors",
	191	"in_unknown_protos",
	192	"out_octets",
	193	"out_ucast_pkts",
	194	"out_discards",
	195	"out_errors",
	196	"in_multicast_pkts",
	197	"in_broadcast_pkts",
	198	"out_multicast_pkts",
	199	"out_broadcast_pkts",
	200
	201	/* RFC2819 counters */
	202	"drop_events",
	203	"octets",
	204	"pkts",
	205	"broadcast_pkts",
	206	"multicast_pkts",
	207	"crc_align_errors",
	208	"undersize_pkts",
	209	"oversize_pkts",
	210	"fragments",
	211	"jabbers",
	212	"collisions",
	213	"p64octets",
	214	"p65to127octets",
	215	"p128to255octets",
	216	"p256to511octets",
	217	"p512to1023octets",
	218	"p1024to1518octets",
	219	"p1519to2047octets",
	220	"p2048to4095octets",
	221	"p4096to8191octets",
	222	"p8192to10239octets",
	223	};
	224
	225	#define NUM_IEEE_802_3_COUNTERS 19
	226	#define NUM_RFC_2863_COUNTERS 13
	227	#define NUM_RFC_2819_COUNTERS 21
228	#define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
229	NUM_RFC_2863_COUNTERS + \
230	NUM_RFC_2819_COUNTERS)
231
232	struct mlx5e_pport_stats {
233	__be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
234	__be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
235	__be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
236	};
237
f62b8bb8 AV	238	static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
	239	"packets",
	240	"csum_none",
bbceefce	241	"csum_sw",
f62b8bb8 AV	242	"lro_packets",
	243	"lro_bytes",
	244	"wqe_err"
	245	};
	246
	247	struct mlx5e_rq_stats {
	248	u64 packets;
	249	u64 csum_none;
bbceefce	250	u64 csum_sw;
f62b8bb8 AV	251	u64 lro_packets;
	252	u64 lro_bytes;
	253	u64 wqe_err;
bbceefce	254	#define NUM_RQ_STATS 6
f62b8bb8 AV	255	};
	256
	257	static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
	258	"packets",
	259	"tso_packets",
	260	"tso_bytes",
89db09eb MF	261	"tso_inner_packets",
89db09eb MF	262	"tso_inner_bytes",
89db09eb	263	"csum_offload_inner",
c89fb18b TT	264	"nop",
c89fb18b TT	265	"csum_offload_none",
f62b8bb8 AV	266	"stopped",
	267	"wake",
	268	"dropped",
f62b8bb8 AV	269	};
	270
	271	struct mlx5e_sq_stats {
c89fb18b	272	/* commonly accessed in data path */
f62b8bb8 AV	273	u64 packets;
	274	u64 tso_packets;
	275	u64 tso_bytes;
89db09eb MF	276	u64 tso_inner_packets;
89db09eb MF	277	u64 tso_inner_bytes;
89db09eb	278	u64 csum_offload_inner;
c89fb18b TT	279	u64 nop;
	280	/* less likely accessed in data path */
	281	u64 csum_offload_none;
f62b8bb8 AV	282	u64 stopped;
	283	u64 wake;
	284	u64 dropped;
89db09eb	285	#define NUM_SQ_STATS 11
f62b8bb8 AV	286	};
	287
	288	struct mlx5e_stats {
	289	struct mlx5e_vport_stats vport;
efea389d	290	struct mlx5e_pport_stats pport;
f62b8bb8 AV	291	};
	292
	293	struct mlx5e_params {
	294	u8 log_sq_size;
	295	u8 log_rq_size;
	296	u16 num_channels;
f62b8bb8 AV	297	u8 num_tc;
	298	u16 rx_cq_moderation_usec;
	299	u16 rx_cq_moderation_pkts;
	300	u16 tx_cq_moderation_usec;
	301	u16 tx_cq_moderation_pkts;
	302	u16 min_rx_wqes;
f62b8bb8 AV	303	bool lro_en;
f62b8bb8 AV	304	u32 lro_wqe_sz;
58d52291	305	u16 tx_max_inline;
2d75b2bc AS	306	u8 rss_hfunc;
	307	u8 toeplitz_hash_key[40];
	308	u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
08fb1dac SM	309	#ifdef CONFIG_MLX5_CORE_EN_DCB
	310	struct ieee_ets ets;
	311	#endif
f62b8bb8 AV	312	};
f62b8bb8 AV	313
ef9814de EBE	314	struct mlx5e_tstamp {
	315	rwlock_t lock;
	316	struct cyclecounter cycles;
	317	struct timecounter clock;
	318	struct hwtstamp_config hwtstamp_config;
	319	u32 nominal_c_mult;
	320	unsigned long overflow_period;
	321	struct delayed_work overflow_work;
	322	struct mlx5_core_dev *mdev;
3d8c38af EBE	323	struct ptp_clock *ptp;
3d8c38af EBE	324	struct ptp_clock_info ptp_info;
ef9814de EBE	325	};
ef9814de EBE	326
f62b8bb8 AV	327	enum {
	328	MLX5E_RQ_STATE_POST_WQES_ENABLE,
	329	};
	330
	331	enum cq_flags {
	332	MLX5E_CQ_HAS_CQES = 1,
	333	};
	334
	335	struct mlx5e_cq {
	336	/* data path - accessed per cqe */
	337	struct mlx5_cqwq wq;
f62b8bb8 AV	338	unsigned long flags;
	339
	340	/* data path - accessed per napi poll */
	341	struct napi_struct *napi;
	342	struct mlx5_core_cq mcq;
	343	struct mlx5e_channel *channel;
50cfa25a	344	struct mlx5e_priv *priv;
f62b8bb8 AV	345
	346	/* control */
	347	struct mlx5_wq_ctrl wq_ctrl;
	348	} ____cacheline_aligned_in_smp;
	349
	350	struct mlx5e_rq {
	351	/* data path */
	352	struct mlx5_wq_ll wq;
	353	u32 wqe_sz;
	354	struct sk_buff **skb;
	355
	356	struct device *pdev;
	357	struct net_device *netdev;
ef9814de	358	struct mlx5e_tstamp *tstamp;
f62b8bb8 AV	359	struct mlx5e_rq_stats stats;
	360	struct mlx5e_cq cq;
	361
	362	unsigned long state;
	363	int ix;
	364
	365	/* control */
	366	struct mlx5_wq_ctrl wq_ctrl;
	367	u32 rqn;
	368	struct mlx5e_channel *channel;
50cfa25a	369	struct mlx5e_priv *priv;
f62b8bb8 AV	370	} ____cacheline_aligned_in_smp;
f62b8bb8 AV	371
34802a42	372	struct mlx5e_tx_wqe_info {
f62b8bb8 AV	373	u32 num_bytes;
	374	u8 num_wqebbs;
	375	u8 num_dma;
	376	};
	377
d4e28cbd AS	378	enum mlx5e_dma_map_type {
	379	MLX5E_DMA_MAP_SINGLE,
	380	MLX5E_DMA_MAP_PAGE
	381	};
	382
f62b8bb8	383	struct mlx5e_sq_dma {
d4e28cbd AS	384	dma_addr_t addr;
	385	u32 size;
	386	enum mlx5e_dma_map_type type;
f62b8bb8 AV	387	};
	388
	389	enum {
	390	MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
	391	};
	392
	393	struct mlx5e_sq {
	394	/* data path */
	395
	396	/* dirtied @completion */
	397	u16 cc;
	398	u32 dma_fifo_cc;
	399
	400	/* dirtied @xmit */
	401	u16 pc ____cacheline_aligned_in_smp;
	402	u32 dma_fifo_pc;
88a85f99 AS	403	u16 bf_offset;
	404	u16 prev_cc;
	405	u8 bf_budget;
f62b8bb8 AV	406	struct mlx5e_sq_stats stats;
	407
	408	struct mlx5e_cq cq;
	409
	410	/* pointers to per packet info: write@xmit, read@completion */
	411	struct sk_buff **skb;
	412	struct mlx5e_sq_dma *dma_fifo;
34802a42	413	struct mlx5e_tx_wqe_info *wqe_info;
f62b8bb8 AV	414
	415	/* read only */
	416	struct mlx5_wq_cyc wq;
	417	u32 dma_fifo_mask;
	418	void __iomem *uar_map;
88a85f99	419	void __iomem *uar_bf_map;
f62b8bb8 AV	420	struct netdev_queue *txq;
f62b8bb8 AV	421	u32 sqn;
88a85f99	422	u16 bf_buf_size;
12be4b21 SM	423	u16 max_inline;
12be4b21 SM	424	u16 edge;
f62b8bb8	425	struct device *pdev;
ef9814de	426	struct mlx5e_tstamp *tstamp;
f62b8bb8 AV	427	__be32 mkey_be;
	428	unsigned long state;
	429
	430	/* control path */
	431	struct mlx5_wq_ctrl wq_ctrl;
	432	struct mlx5_uar uar;
	433	struct mlx5e_channel *channel;
	434	int tc;
	435	} ____cacheline_aligned_in_smp;
	436
	437	static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
	438	{
	439	return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) \|\|
	440	(sq->cc == sq->pc));
	441	}
	442
	443	enum channel_flags {
	444	MLX5E_CHANNEL_NAPI_SCHED = 1,
	445	};
	446
	447	struct mlx5e_channel {
	448	/* data path */
	449	struct mlx5e_rq rq;
	450	struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
	451	struct napi_struct napi;
	452	struct device *pdev;
	453	struct net_device *netdev;
	454	__be32 mkey_be;
	455	u8 num_tc;
	456	unsigned long flags;
	457
	458	/* control */
	459	struct mlx5e_priv *priv;
	460	int ix;
	461	int cpu;
	462	};
	463
	464	enum mlx5e_traffic_types {
5a6f8aef AS	465	MLX5E_TT_IPV4_TCP,
	466	MLX5E_TT_IPV6_TCP,
	467	MLX5E_TT_IPV4_UDP,
	468	MLX5E_TT_IPV6_UDP,
a741749f AS	469	MLX5E_TT_IPV4_IPSEC_AH,
	470	MLX5E_TT_IPV6_IPSEC_AH,
	471	MLX5E_TT_IPV4_IPSEC_ESP,
	472	MLX5E_TT_IPV6_IPSEC_ESP,
5a6f8aef AS	473	MLX5E_TT_IPV4,
	474	MLX5E_TT_IPV6,
	475	MLX5E_TT_ANY,
	476	MLX5E_NUM_TT,
f62b8bb8 AV	477	};
f62b8bb8 AV	478
4cbeaff5 AS	479	enum mlx5e_rqt_ix {
	480	MLX5E_INDIRECTION_RQT,
	481	MLX5E_SINGLE_RQ_RQT,
	482	MLX5E_NUM_RQT,
f62b8bb8 AV	483	};
	484
	485	struct mlx5e_eth_addr_info {
	486	u8 addr[ETH_ALEN + 2];
	487	u32 tt_vec;
86d722ad	488	struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
f62b8bb8 AV	489	};
	490
	491	#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
	492
	493	struct mlx5e_eth_addr_db {
	494	struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
	495	struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
	496	struct mlx5e_eth_addr_info broadcast;
	497	struct mlx5e_eth_addr_info allmulti;
	498	struct mlx5e_eth_addr_info promisc;
	499	bool broadcast_enabled;
	500	bool allmulti_enabled;
	501	bool promisc_enabled;
	502	};
	503
	504	enum {
	505	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
	506	MLX5E_STATE_OPENED,
9b37b07f	507	MLX5E_STATE_DESTROYING,
f62b8bb8 AV	508	};
	509
	510	struct mlx5e_vlan_db {
aad9e6e4	511	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
86d722ad MG	512	struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
	513	struct mlx5_flow_rule *untagged_rule;
	514	struct mlx5_flow_rule *any_vlan_rule;
f62b8bb8 AV	515	bool filter_disabled;
	516	};
	517
b3f63c3d MF	518	struct mlx5e_vxlan_db {
	519	spinlock_t lock; /* protect vxlan table */
	520	struct radix_tree_root tree;
	521	};
	522
f62b8bb8	523	struct mlx5e_flow_table {
86d722ad MG	524	int num_groups;
	525	struct mlx5_flow_table *t;
	526	struct mlx5_flow_group **g;
	527	};
	528
	529	struct mlx5e_flow_tables {
	530	struct mlx5_flow_namespace *ns;
	531	struct mlx5e_flow_table vlan;
	532	struct mlx5e_flow_table main;
f62b8bb8 AV	533	};
	534
	535	struct mlx5e_priv {
	536	/* priv data path fields - start */
03289b88	537	struct mlx5e_sq **txq_to_sq_map;
5283af89	538	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
f62b8bb8 AV	539	/* priv data path fields - end */
	540
	541	unsigned long state;
	542	struct mutex state_lock; /* Protects Interface state */
	543	struct mlx5_uar cq_uar;
	544	u32 pdn;
3191e05f	545	u32 tdn;
f62b8bb8	546	struct mlx5_core_mr mr;
50cfa25a	547	struct mlx5e_rq drop_rq;
f62b8bb8 AV	548
	549	struct mlx5e_channel **channel;
	550	u32 tisn[MLX5E_MAX_NUM_TC];
4cbeaff5	551	u32 rqtn[MLX5E_NUM_RQT];
f62b8bb8 AV	552	u32 tirn[MLX5E_NUM_TT];
f62b8bb8 AV	553
86d722ad	554	struct mlx5e_flow_tables fts;
f62b8bb8 AV	555	struct mlx5e_eth_addr_db eth_addr;
f62b8bb8 AV	556	struct mlx5e_vlan_db vlan;
b3f63c3d	557	struct mlx5e_vxlan_db vxlan;
f62b8bb8 AV	558
f62b8bb8 AV	559	struct mlx5e_params params;
f62b8bb8 AV	560	struct work_struct update_carrier_work;
	561	struct work_struct set_rx_mode_work;
	562	struct delayed_work update_stats_work;
	563
	564	struct mlx5_core_dev *mdev;
	565	struct net_device *netdev;
	566	struct mlx5e_stats stats;
ef9814de	567	struct mlx5e_tstamp tstamp;
f62b8bb8 AV	568	};
	569
	570	#define MLX5E_NET_IP_ALIGN 2
	571
	572	struct mlx5e_tx_wqe {
	573	struct mlx5_wqe_ctrl_seg ctrl;
	574	struct mlx5_wqe_eth_seg eth;
	575	};
	576
	577	struct mlx5e_rx_wqe {
	578	struct mlx5_wqe_srq_next_seg next;
	579	struct mlx5_wqe_data_seg data;
	580	};
	581
	582	enum mlx5e_link_mode {
	583	MLX5E_1000BASE_CX_SGMII = 0,
	584	MLX5E_1000BASE_KX = 1,
	585	MLX5E_10GBASE_CX4 = 2,
	586	MLX5E_10GBASE_KX4 = 3,
	587	MLX5E_10GBASE_KR = 4,
	588	MLX5E_20GBASE_KR2 = 5,
	589	MLX5E_40GBASE_CR4 = 6,
	590	MLX5E_40GBASE_KR4 = 7,
	591	MLX5E_56GBASE_R4 = 8,
	592	MLX5E_10GBASE_CR = 12,
	593	MLX5E_10GBASE_SR = 13,
	594	MLX5E_10GBASE_ER = 14,
	595	MLX5E_40GBASE_SR4 = 15,
	596	MLX5E_40GBASE_LR4 = 16,
	597	MLX5E_100GBASE_CR4 = 20,
	598	MLX5E_100GBASE_SR4 = 21,
	599	MLX5E_100GBASE_KR4 = 22,
	600	MLX5E_100GBASE_LR4 = 23,
	601	MLX5E_100BASE_TX = 24,
	602	MLX5E_100BASE_T = 25,
	603	MLX5E_10GBASE_T = 26,
	604	MLX5E_25GBASE_CR = 27,
	605	MLX5E_25GBASE_KR = 28,
	606	MLX5E_25GBASE_SR = 29,
	607	MLX5E_50GBASE_CR2 = 30,
	608	MLX5E_50GBASE_KR2 = 31,
	609	MLX5E_LINK_MODES_NUMBER,
	610	};
	611
	612	#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
	613
12be4b21	614	void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
f62b8bb8 AV	615	u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb,
	616	void *accel_priv, select_queue_fallback_t fallback);
	617	netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev);
f62b8bb8 AV	618
	619	void mlx5e_completion_event(struct mlx5_core_cq *mcq);
	620	void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
	621	int mlx5e_napi_poll(struct napi_struct *napi, int budget);
	622	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
44fb6fbb	623	int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
f62b8bb8 AV	624	bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
	625	struct mlx5_cqe64 mlx5e_get_cqe(struct mlx5e_cq cq);
	626
	627	void mlx5e_update_stats(struct mlx5e_priv *priv);
	628
40ab6a6e AS	629	int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
40ab6a6e AS	630	void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
f62b8bb8	631	void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
f62b8bb8 AV	632	void mlx5e_set_rx_mode_work(struct work_struct *work);
f62b8bb8 AV	633
ef9814de EBE	634	void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
	635	struct skb_shared_hwtstamps *hwts);
	636	void mlx5e_timestamp_init(struct mlx5e_priv *priv);
	637	void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
	638	int mlx5e_hwstamp_set(struct net_device dev, struct ifreq ifr);
	639	int mlx5e_hwstamp_get(struct net_device dev, struct ifreq ifr);
	640
f62b8bb8 AV	641	int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
	642	u16 vid);
	643	int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
	644	u16 vid);
	645	void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
	646	void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
f62b8bb8	647
2d75b2bc AS	648	int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
2d75b2bc AS	649
f62b8bb8 AV	650	int mlx5e_open_locked(struct net_device *netdev);
f62b8bb8 AV	651	int mlx5e_close_locked(struct net_device *netdev);
f62b8bb8 AV	652
f62b8bb8 AV	653	static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
88a85f99	654	struct mlx5e_tx_wqe *wqe, int bf_sz)
f62b8bb8	655	{
88a85f99 AS	656	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
88a85f99 AS	657
f62b8bb8 AV	658	/* ensure wqe is visible to device before updating doorbell record */
	659	dma_wmb();
	660
	661	*sq->wq.db = cpu_to_be32(sq->pc);
	662
	663	/* ensure doorbell record is visible to device before ringing the
	664	* doorbell
	665	*/
	666	wmb();
	667
88a85f99 AS	668	if (bf_sz) {
	669	__iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
	670
	671	/* flush the write-combining mapped buffer */
	672	wmb();
	673
	674	} else {
	675	mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
	676	}
f62b8bb8 AV	677
	678	sq->bf_offset ^= sq->bf_buf_size;
	679	}
	680
	681	static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
	682	{
	683	struct mlx5_core_cq *mcq;
	684
	685	mcq = &cq->mcq;
	686	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
	687	}
	688
3435ab59 AS	689	static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
	690	{
	691	return min_t(int, mdev->priv.eq_table.num_comp_vectors,
	692	MLX5E_MAX_NUM_CHANNELS);
	693	}
	694
f62b8bb8	695	extern const struct ethtool_ops mlx5e_ethtool_ops;
08fb1dac SM	696	#ifdef CONFIG_MLX5_CORE_EN_DCB
	697	extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
	698	int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv priv, struct ieee_ets ets);
	699	#endif
	700
58d52291	701	u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1afff42c MF	702
1afff42c MF	703	#endif /* __MLX5_EN_H__ */