Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
48935bbb | 39 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
40 | #include <linux/mlx5/driver.h> |
41 | #include <linux/mlx5/qp.h> | |
42 | #include <linux/mlx5/cq.h> | |
ada68c31 | 43 | #include <linux/mlx5/port.h> |
d18a9470 | 44 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 45 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 46 | #include <linux/mlx5/fs.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
18a2b7f9 | 48 | #include <net/udp_tunnel.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4f75da36 | 51 | #include <linux/dim.h> |
8ff57c18 | 52 | #include <linux/bits.h> |
f62b8bb8 | 53 | #include "wq.h" |
f62b8bb8 | 54 | #include "mlx5_core.h" |
9218b44d | 55 | #include "en_stats.h" |
3f3ab178 | 56 | #include "en/dcbnl.h" |
fe6d86b3 | 57 | #include "en/fs.h" |
214baf22 | 58 | #include "en/qos.h" |
cef35af3 | 59 | #include "lib/hv_vhca.h" |
432119de | 60 | #include "lib/clock.h" |
3f22d6c7 | 61 | #include "en/rx_res.h" |
f62b8bb8 | 62 | |
4d8fcf21 | 63 | extern const struct net_device_ops mlx5e_netdev_ops; |
60bbf7ee JDB |
64 | struct page_pool; |
65 | ||
bb909416 IL |
66 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
67 | #define MLX5E_METADATA_ETHER_LEN 8 | |
68 | ||
1cabe6b0 MG |
69 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
70 | ||
c139dbfd ES |
71 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
72 | ||
472a1e44 TT |
73 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
74 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 75 | |
f62b8bb8 AV |
76 | #define MLX5E_MAX_NUM_TC 8 |
77 | ||
1bfecfca | 78 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
79 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
80 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 81 | |
94816278 TT |
82 | #define MLX5E_RX_MAX_HEAD (256) |
83 | ||
f32f5bd2 DJ |
84 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
85 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
86 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
87 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
94816278 TT |
88 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) \ |
89 | MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, order_base_2(MLX5E_RX_MAX_HEAD)) | |
f32f5bd2 | 90 | |
7e426671 | 91 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
92 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
93 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
94 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b | 95 | |
d5dd03b2 TT |
96 | #define MLX5_ALIGN_MTTS(mtts) (ALIGN(mtts, 8)) |
97 | #define MLX5_ALIGNED_MTTS_OCTW(mtts) ((mtts) / 2) | |
98 | #define MLX5_MTT_OCTW(mtts) (MLX5_ALIGNED_MTTS_OCTW(MLX5_ALIGN_MTTS(mtts))) | |
c3c94023 AL |
99 | /* Add another page to MLX5E_REQUIRED_WQE_MTTS as a buffer between |
100 | * WQEs, This page will absorb write overflow by the hardware, when | |
101 | * receiving packets larger than MTU. These oversize packets are | |
102 | * dropped by the driver at a later stage. | |
103 | */ | |
d5dd03b2 | 104 | #define MLX5E_REQUIRED_WQE_MTTS (MLX5_ALIGN_MTTS(MLX5_MPWRQ_PAGES_PER_WQE + 1)) |
73281b78 TT |
105 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
106 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
107 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
108 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
109 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
110 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
111 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
112 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
113 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
114 | ||
069d1146 TT |
115 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
116 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
117 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
118 | ||
73281b78 TT |
119 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
120 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
121 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
122 | ||
069d1146 | 123 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
124 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
125 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
126 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
127 | ||
128 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 129 | |
2b029556 SM |
130 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
131 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
132 | ||
f62b8bb8 | 133 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 134 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
135 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
136 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 137 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
138 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
139 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 140 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 141 | |
b4e029da | 142 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
507f0c81 | 143 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 | 144 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
db05815b | 145 | #define MLX5E_TX_XSK_POLL_BUDGET 64 |
db75373c | 146 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 147 | |
ea3886ca TT |
148 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
149 | (sizeof(struct mlx5e_umr_wqe) + \ | |
150 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
151 | MLX5_UMR_MTT_ALIGNMENT)) | |
152 | #define MLX5E_UMR_WQEBBS \ | |
153 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
2f48af12 | 154 | |
79c48764 GP |
155 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
156 | ||
157 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
158 | do { \ | |
159 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
160 | netdev_warn(priv->netdev, format, \ | |
161 | ##__VA_ARGS__); \ | |
162 | } while (0) | |
163 | ||
214baf22 MM |
164 | #define mlx5e_state_dereference(priv, p) \ |
165 | rcu_dereference_protected((p), lockdep_is_held(&(priv)->state_lock)) | |
166 | ||
db05815b MM |
167 | enum mlx5e_rq_group { |
168 | MLX5E_RQ_GROUP_REGULAR, | |
169 | MLX5E_RQ_GROUP_XSK, | |
694826e3 | 170 | #define MLX5E_NUM_RQ_GROUPS(g) (1 + MLX5E_RQ_GROUP_##g) |
db05815b | 171 | }; |
79c48764 | 172 | |
45f171b1 MM |
173 | static inline u8 mlx5e_get_num_lag_ports(struct mlx5_core_dev *mdev) |
174 | { | |
175 | if (mlx5_lag_is_lacp_owner(mdev)) | |
176 | return 1; | |
177 | ||
178 | return clamp_t(u8, MLX5_CAP_GEN(mdev, num_lag_ports), 1, MLX5_MAX_PORTS); | |
179 | } | |
180 | ||
461017cb TT |
181 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
182 | { | |
183 | switch (wq_type) { | |
184 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
185 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
186 | wq_size / 2); | |
187 | default: | |
188 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
189 | wq_size / 2); | |
190 | } | |
191 | } | |
192 | ||
779d986d | 193 | /* Use this function to get max num channels (rxqs/txqs) only to create netdev */ |
48935bbb SM |
194 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
195 | { | |
196 | return is_kdump_kernel() ? | |
197 | MLX5E_MIN_NUM_CHANNELS : | |
f2f3df55 | 198 | min_t(int, mlx5_comp_vectors_count(mdev), MLX5E_MAX_NUM_CHANNELS); |
48935bbb SM |
199 | } |
200 | ||
2f48af12 TT |
201 | struct mlx5e_tx_wqe { |
202 | struct mlx5_wqe_ctrl_seg ctrl; | |
7d0d0d86 TT |
203 | struct mlx5_wqe_eth_seg eth; |
204 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 TT |
205 | }; |
206 | ||
99cbfa93 | 207 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 208 | struct mlx5_wqe_srq_next_seg next; |
339ffae5 | 209 | struct mlx5_wqe_data_seg data[]; |
99cbfa93 TT |
210 | }; |
211 | ||
212 | struct mlx5e_rx_wqe_cyc { | |
213 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 214 | }; |
86d722ad | 215 | |
bc77b240 TT |
216 | struct mlx5e_umr_wqe { |
217 | struct mlx5_wqe_ctrl_seg ctrl; | |
218 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
219 | struct mlx5_mkey_seg mkc; | |
7d0d0d86 | 220 | struct mlx5_mtt inline_mtts[0]; |
bc77b240 TT |
221 | }; |
222 | ||
d605d668 KH |
223 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
224 | ||
4e59e288 | 225 | enum mlx5e_priv_flag { |
8ff57c18 TT |
226 | MLX5E_PFLAG_RX_CQE_BASED_MODER, |
227 | MLX5E_PFLAG_TX_CQE_BASED_MODER, | |
228 | MLX5E_PFLAG_RX_CQE_COMPRESS, | |
229 | MLX5E_PFLAG_RX_STRIDING_RQ, | |
230 | MLX5E_PFLAG_RX_NO_CSUM_COMPLETE, | |
6277053a | 231 | MLX5E_PFLAG_XDP_TX_MPWQE, |
5af75c74 | 232 | MLX5E_PFLAG_SKB_TX_MPWQE, |
145e5637 | 233 | MLX5E_PFLAG_TX_PORT_TS, |
8ff57c18 | 234 | MLX5E_NUM_PFLAGS, /* Keep last */ |
4e59e288 GP |
235 | }; |
236 | ||
6a9764ef | 237 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
238 | do { \ |
239 | if (enable) \ | |
8ff57c18 | 240 | (params)->pflags |= BIT(pflag); \ |
59ece1c9 | 241 | else \ |
8ff57c18 | 242 | (params)->pflags &= ~(BIT(pflag)); \ |
4e59e288 GP |
243 | } while (0) |
244 | ||
8ff57c18 | 245 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (BIT(pflag)))) |
59ece1c9 | 246 | |
f62b8bb8 AV |
247 | struct mlx5e_params { |
248 | u8 log_sq_size; | |
461017cb | 249 | u8 rq_wq_type; |
73281b78 | 250 | u8 log_rq_mtu_frames; |
f62b8bb8 | 251 | u16 num_channels; |
f62b8bb8 | 252 | u8 num_tc; |
9bcc8606 | 253 | bool rx_cqe_compress_def; |
69dad68d | 254 | bool tunneled_offload_en; |
8960b389 TG |
255 | struct dim_cq_moder rx_cq_moderation; |
256 | struct dim_cq_moder tx_cq_moderation; | |
f62b8bb8 | 257 | bool lro_en; |
cff92d7c | 258 | u8 tx_min_inline_mode; |
36350114 | 259 | bool vlan_strip_disable; |
102722fc | 260 | bool scatter_fcs_en; |
9a317425 | 261 | bool rx_dim_enabled; |
cbce4f44 | 262 | bool tx_dim_enabled; |
2b029556 | 263 | u32 lro_timeout; |
59ece1c9 | 264 | u32 pflags; |
6a9764ef | 265 | struct bpf_prog *xdp_prog; |
db05815b | 266 | struct mlx5e_xsk *xsk; |
472a1e44 TT |
267 | unsigned int sw_mtu; |
268 | int hard_mtu; | |
960fbfe2 | 269 | bool ptp_rx; |
f62b8bb8 AV |
270 | }; |
271 | ||
272 | enum { | |
c0f1147d | 273 | MLX5E_RQ_STATE_ENABLED, |
8276ea13 | 274 | MLX5E_RQ_STATE_RECOVERING, |
cb3c7fd4 | 275 | MLX5E_RQ_STATE_AM, |
b856df28 | 276 | MLX5E_RQ_STATE_NO_CSUM_COMPLETE, |
db849faa | 277 | MLX5E_RQ_STATE_CSUM_FULL, /* cqe_csum_full hw bit is set */ |
a2907436 | 278 | MLX5E_RQ_STATE_FPGA_TLS, /* FPGA TLS enabled */ |
b7cf0806 | 279 | MLX5E_RQ_STATE_MINI_CQE_HW_STRIDX /* set when mini_cqe_resp_stride_index cap is used */ |
f62b8bb8 AV |
280 | }; |
281 | ||
f62b8bb8 AV |
282 | struct mlx5e_cq { |
283 | /* data path - accessed per cqe */ | |
284 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
285 | |
286 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 287 | u16 event_ctr; |
f62b8bb8 AV |
288 | struct napi_struct *napi; |
289 | struct mlx5_core_cq mcq; | |
4d0b7ef9 | 290 | struct mlx5e_ch_stats *ch_stats; |
f62b8bb8 | 291 | |
79d356ef | 292 | /* control */ |
4d0b7ef9 | 293 | struct net_device *netdev; |
79d356ef | 294 | struct mlx5_core_dev *mdev; |
4d0b7ef9 | 295 | struct mlx5e_priv *priv; |
79d356ef TT |
296 | struct mlx5_wq_ctrl wq_ctrl; |
297 | } ____cacheline_aligned_in_smp; | |
298 | ||
299 | struct mlx5e_cq_decomp { | |
7219ab34 TT |
300 | /* cqe decompression */ |
301 | struct mlx5_cqe64 title; | |
302 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
303 | u8 mini_arr_idx; | |
79d356ef TT |
304 | u16 left; |
305 | u16 wqe_counter; | |
f62b8bb8 AV |
306 | } ____cacheline_aligned_in_smp; |
307 | ||
eba2db2b SM |
308 | enum mlx5e_dma_map_type { |
309 | MLX5E_DMA_MAP_SINGLE, | |
310 | MLX5E_DMA_MAP_PAGE | |
311 | }; | |
312 | ||
313 | struct mlx5e_sq_dma { | |
314 | dma_addr_t addr; | |
315 | u32 size; | |
316 | enum mlx5e_dma_map_type type; | |
317 | }; | |
318 | ||
319 | enum { | |
320 | MLX5E_SQ_STATE_ENABLED, | |
5af75c74 | 321 | MLX5E_SQ_STATE_MPWQE, |
db75373c | 322 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 323 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 324 | MLX5E_SQ_STATE_AM, |
b431302e | 325 | MLX5E_SQ_STATE_VLAN_NEED_L2_INLINE, |
e7e0004a | 326 | MLX5E_SQ_STATE_PENDING_XSK_TX, |
e9ce991b | 327 | MLX5E_SQ_STATE_PENDING_TLS_RX_RESYNC, |
eba2db2b SM |
328 | }; |
329 | ||
b39fe61e MM |
330 | struct mlx5e_tx_mpwqe { |
331 | /* Current MPWQE session */ | |
332 | struct mlx5e_tx_wqe *wqe; | |
5af75c74 | 333 | u32 bytes_count; |
b39fe61e MM |
334 | u8 ds_count; |
335 | u8 pkt_count; | |
336 | u8 inline_on; | |
337 | }; | |
338 | ||
0b676aae EBE |
339 | struct mlx5e_skb_fifo { |
340 | struct sk_buff **fifo; | |
341 | u16 *pc; | |
342 | u16 *cc; | |
343 | u16 mask; | |
344 | }; | |
345 | ||
145e5637 EBE |
346 | struct mlx5e_ptpsq; |
347 | ||
31391048 | 348 | struct mlx5e_txqsq { |
eba2db2b SM |
349 | /* data path */ |
350 | ||
351 | /* dirtied @completion */ | |
352 | u16 cc; | |
338c46c6 | 353 | u16 skb_fifo_cc; |
eba2db2b | 354 | u32 dma_fifo_cc; |
8960b389 | 355 | struct dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
356 | |
357 | /* dirtied @xmit */ | |
358 | u16 pc ____cacheline_aligned_in_smp; | |
338c46c6 | 359 | u16 skb_fifo_pc; |
eba2db2b | 360 | u32 dma_fifo_pc; |
5af75c74 | 361 | struct mlx5e_tx_mpwqe mpwqe; |
eba2db2b SM |
362 | |
363 | struct mlx5e_cq cq; | |
364 | ||
eba2db2b SM |
365 | /* read only */ |
366 | struct mlx5_wq_cyc wq; | |
367 | u32 dma_fifo_mask; | |
05909bab | 368 | struct mlx5e_sq_stats *stats; |
9a3956da TT |
369 | struct { |
370 | struct mlx5e_sq_dma *dma_fifo; | |
0b676aae | 371 | struct mlx5e_skb_fifo skb_fifo; |
9a3956da TT |
372 | struct mlx5e_tx_wqe_info *wqe_info; |
373 | } db; | |
eba2db2b SM |
374 | void __iomem *uar_map; |
375 | struct netdev_queue *txq; | |
376 | u32 sqn; | |
01614d4f | 377 | u16 stop_room; |
eba2db2b | 378 | u8 min_inline_mode; |
eba2db2b | 379 | struct device *pdev; |
eba2db2b SM |
380 | __be32 mkey_be; |
381 | unsigned long state; | |
84d1bb2b | 382 | unsigned int hw_mtu; |
7c39afb3 FD |
383 | struct hwtstamp_config *tstamp; |
384 | struct mlx5_clock *clock; | |
4ad40d8e EBE |
385 | struct net_device *netdev; |
386 | struct mlx5_core_dev *mdev; | |
387 | struct mlx5e_priv *priv; | |
eba2db2b SM |
388 | |
389 | /* control path */ | |
390 | struct mlx5_wq_ctrl wq_ctrl; | |
57c70d87 | 391 | int ch_ix; |
acc6c595 | 392 | int txq_ix; |
eba2db2b | 393 | u32 rate_limit; |
de8650a8 | 394 | struct work_struct recover_work; |
145e5637 | 395 | struct mlx5e_ptpsq *ptpsq; |
432119de | 396 | cqe_ts_to_ns ptp_cyc2time; |
31391048 SM |
397 | } ____cacheline_aligned_in_smp; |
398 | ||
c94e4f11 | 399 | struct mlx5e_dma_info { |
db05815b MM |
400 | dma_addr_t addr; |
401 | union { | |
402 | struct page *page; | |
39d6443c | 403 | struct xdp_buff *xsk; |
db05815b | 404 | }; |
c94e4f11 TT |
405 | }; |
406 | ||
d963fa15 MM |
407 | /* XDP packets can be transmitted in different ways. On completion, we need to |
408 | * distinguish between them to clean up things in a proper way. | |
409 | */ | |
410 | enum mlx5e_xdp_xmit_mode { | |
411 | /* An xdp_frame was transmitted due to either XDP_REDIRECT from another | |
412 | * device or XDP_TX from an XSK RQ. The frame has to be unmapped and | |
413 | * returned. | |
414 | */ | |
415 | MLX5E_XDP_XMIT_MODE_FRAME, | |
416 | ||
417 | /* The xdp_frame was created in place as a result of XDP_TX from a | |
418 | * regular RQ. No DMA remapping happened, and the page belongs to us. | |
419 | */ | |
420 | MLX5E_XDP_XMIT_MODE_PAGE, | |
421 | ||
422 | /* No xdp_frame was created at all, the transmit happened from a UMEM | |
423 | * page. The UMEM Completion Ring producer pointer has to be increased. | |
424 | */ | |
425 | MLX5E_XDP_XMIT_MODE_XSK, | |
c94e4f11 TT |
426 | }; |
427 | ||
428 | struct mlx5e_xdp_info { | |
d963fa15 MM |
429 | enum mlx5e_xdp_xmit_mode mode; |
430 | union { | |
431 | struct { | |
432 | struct xdp_frame *xdpf; | |
433 | dma_addr_t dma_addr; | |
434 | } frame; | |
435 | struct { | |
b9673cf5 | 436 | struct mlx5e_rq *rq; |
d963fa15 MM |
437 | struct mlx5e_dma_info di; |
438 | } page; | |
439 | }; | |
440 | }; | |
441 | ||
b39fe61e | 442 | struct mlx5e_xmit_data { |
d963fa15 MM |
443 | dma_addr_t dma_addr; |
444 | void *data; | |
445 | u32 len; | |
c94e4f11 TT |
446 | }; |
447 | ||
fea28dd6 TT |
448 | struct mlx5e_xdp_info_fifo { |
449 | struct mlx5e_xdp_info *xi; | |
450 | u32 *cc; | |
451 | u32 *pc; | |
452 | u32 mask; | |
453 | }; | |
454 | ||
5e0d2eef | 455 | struct mlx5e_xdpsq; |
db05815b | 456 | typedef int (*mlx5e_fp_xmit_xdp_frame_check)(struct mlx5e_xdpsq *); |
d963fa15 | 457 | typedef bool (*mlx5e_fp_xmit_xdp_frame)(struct mlx5e_xdpsq *, |
b39fe61e | 458 | struct mlx5e_xmit_data *, |
db05815b MM |
459 | struct mlx5e_xdp_info *, |
460 | int); | |
d963fa15 | 461 | |
31391048 SM |
462 | struct mlx5e_xdpsq { |
463 | /* data path */ | |
464 | ||
dac0d15f | 465 | /* dirtied @completion */ |
fea28dd6 | 466 | u32 xdpi_fifo_cc; |
31391048 | 467 | u16 cc; |
31391048 | 468 | |
dac0d15f | 469 | /* dirtied @xmit */ |
fea28dd6 TT |
470 | u32 xdpi_fifo_pc ____cacheline_aligned_in_smp; |
471 | u16 pc; | |
b8180392 | 472 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
b39fe61e | 473 | struct mlx5e_tx_mpwqe mpwqe; |
31391048 | 474 | |
dac0d15f | 475 | struct mlx5e_cq cq; |
31391048 SM |
476 | |
477 | /* read only */ | |
1742b3d5 | 478 | struct xsk_buff_pool *xsk_pool; |
31391048 | 479 | struct mlx5_wq_cyc wq; |
890388ad | 480 | struct mlx5e_xdpsq_stats *stats; |
db05815b | 481 | mlx5e_fp_xmit_xdp_frame_check xmit_xdp_frame_check; |
5e0d2eef | 482 | mlx5e_fp_xmit_xdp_frame xmit_xdp_frame; |
dac0d15f | 483 | struct { |
1feeab80 | 484 | struct mlx5e_xdp_wqe_info *wqe_info; |
fea28dd6 | 485 | struct mlx5e_xdp_info_fifo xdpi_fifo; |
dac0d15f | 486 | } db; |
31391048 SM |
487 | void __iomem *uar_map; |
488 | u32 sqn; | |
489 | struct device *pdev; | |
490 | __be32 mkey_be; | |
491 | u8 min_inline_mode; | |
492 | unsigned long state; | |
c94e4f11 | 493 | unsigned int hw_mtu; |
31391048 SM |
494 | |
495 | /* control path */ | |
496 | struct mlx5_wq_ctrl wq_ctrl; | |
497 | struct mlx5e_channel *channel; | |
498 | } ____cacheline_aligned_in_smp; | |
499 | ||
e9ce991b TT |
500 | struct mlx5e_ktls_resync_resp; |
501 | ||
31391048 SM |
502 | struct mlx5e_icosq { |
503 | /* data path */ | |
fd9b4be8 TT |
504 | u16 cc; |
505 | u16 pc; | |
31391048 | 506 | |
fd9b4be8 | 507 | struct mlx5_wqe_ctrl_seg *doorbell_cseg; |
31391048 SM |
508 | struct mlx5e_cq cq; |
509 | ||
510 | /* write@xmit, read@completion */ | |
511 | struct { | |
7d42c8e9 | 512 | struct mlx5e_icosq_wqe_info *wqe_info; |
31391048 SM |
513 | } db; |
514 | ||
515 | /* read only */ | |
516 | struct mlx5_wq_cyc wq; | |
517 | void __iomem *uar_map; | |
518 | u32 sqn; | |
3ff3874f | 519 | u16 reserved_room; |
31391048 | 520 | unsigned long state; |
e9ce991b | 521 | struct mlx5e_ktls_resync_resp *ktls_resync; |
31391048 SM |
522 | |
523 | /* control path */ | |
524 | struct mlx5_wq_ctrl wq_ctrl; | |
525 | struct mlx5e_channel *channel; | |
be5323c8 AL |
526 | |
527 | struct work_struct recover_work; | |
eba2db2b SM |
528 | } ____cacheline_aligned_in_smp; |
529 | ||
accd5883 | 530 | struct mlx5e_wqe_frag_info { |
069d1146 | 531 | struct mlx5e_dma_info *di; |
accd5883 | 532 | u32 offset; |
069d1146 | 533 | bool last_in_page; |
accd5883 TT |
534 | }; |
535 | ||
eba2db2b | 536 | struct mlx5e_umr_dma_info { |
eba2db2b | 537 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
538 | }; |
539 | ||
540 | struct mlx5e_mpw_info { | |
541 | struct mlx5e_umr_dma_info umr; | |
542 | u16 consumed_strides; | |
22f45398 | 543 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
544 | }; |
545 | ||
069d1146 TT |
546 | #define MLX5E_MAX_RX_FRAGS 4 |
547 | ||
4415a031 TT |
548 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
549 | * or a MPWQE (for striding rq). | |
550 | */ | |
551 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
552 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 553 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
554 | struct mlx5e_page_cache { |
555 | u32 head; | |
556 | u32 tail; | |
557 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
558 | }; | |
559 | ||
eba2db2b SM |
560 | struct mlx5e_rq; |
561 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
562 | typedef struct sk_buff * |
563 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
564 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
565 | typedef struct sk_buff * |
566 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
567 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 568 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
569 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
570 | ||
5adf4c47 | 571 | int mlx5e_rq_set_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params, bool xsk); |
5543e989 | 572 | void mlx5e_rq_set_trap_handlers(struct mlx5e_rq *rq, struct mlx5e_params *params); |
5adf4c47 | 573 | |
121e8927 | 574 | enum mlx5e_rq_flag { |
f03590f7 | 575 | MLX5E_RQ_FLAG_XDP_XMIT, |
15143bf5 | 576 | MLX5E_RQ_FLAG_XDP_REDIRECT, |
121e8927 TT |
577 | }; |
578 | ||
069d1146 TT |
579 | struct mlx5e_rq_frag_info { |
580 | int frag_size; | |
581 | int frag_stride; | |
582 | }; | |
583 | ||
584 | struct mlx5e_rq_frags_info { | |
585 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
586 | u8 num_frags; | |
587 | u8 log_num_frags; | |
588 | u8 wqe_bulk; | |
589 | }; | |
590 | ||
f62b8bb8 AV |
591 | struct mlx5e_rq { |
592 | /* data path */ | |
21c59685 | 593 | union { |
accd5883 | 594 | struct { |
069d1146 TT |
595 | struct mlx5_wq_cyc wq; |
596 | struct mlx5e_wqe_frag_info *frags; | |
597 | struct mlx5e_dma_info *di; | |
598 | struct mlx5e_rq_frags_info info; | |
599 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 600 | } wqe; |
21c59685 | 601 | struct { |
422d4c40 | 602 | struct mlx5_wq_ll wq; |
b8a98a4c | 603 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 604 | struct mlx5e_mpw_info *info; |
619a8f2a | 605 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 606 | u16 num_strides; |
fd9b4be8 | 607 | u16 actual_wq_head; |
89e89f7a | 608 | u8 log_stride_sz; |
fd9b4be8 TT |
609 | u8 umr_in_progress; |
610 | u8 umr_last_bulk; | |
ed084fb6 | 611 | u8 umr_completed; |
21c59685 SM |
612 | } mpwqe; |
613 | }; | |
1bfecfca | 614 | struct { |
b45d8b50 | 615 | u16 headroom; |
d628ee4f | 616 | u32 frame0_sz; |
b5503b99 | 617 | u8 map_dir; /* dma map direction */ |
1bfecfca | 618 | } buff; |
f62b8bb8 AV |
619 | |
620 | struct device *pdev; | |
621 | struct net_device *netdev; | |
05909bab | 622 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 623 | struct mlx5e_cq cq; |
79d356ef | 624 | struct mlx5e_cq_decomp cqd; |
4415a031 | 625 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
626 | struct hwtstamp_config *tstamp; |
627 | struct mlx5_clock *clock; | |
521f31af AL |
628 | struct mlx5e_icosq *icosq; |
629 | struct mlx5e_priv *priv; | |
4415a031 | 630 | |
2f48af12 | 631 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 632 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 633 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
634 | |
635 | unsigned long state; | |
636 | int ix; | |
0073c8f7 | 637 | unsigned int hw_mtu; |
f62b8bb8 | 638 | |
8960b389 | 639 | struct dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
640 | |
641 | /* XDP */ | |
fe45386a | 642 | struct bpf_prog __rcu *xdp_prog; |
b9673cf5 | 643 | struct mlx5e_xdpsq *xdpsq; |
121e8927 | 644 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 645 | struct page_pool *page_pool; |
cb3c7fd4 | 646 | |
db05815b | 647 | /* AF_XDP zero-copy */ |
1742b3d5 | 648 | struct xsk_buff_pool *xsk_pool; |
db05815b | 649 | |
8276ea13 AL |
650 | struct work_struct recover_work; |
651 | ||
f62b8bb8 AV |
652 | /* control */ |
653 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 654 | __be32 mkey_be; |
461017cb | 655 | u8 wq_type; |
f62b8bb8 | 656 | u32 rqn; |
a43b25da | 657 | struct mlx5_core_dev *mdev; |
ec8b9981 | 658 | struct mlx5_core_mkey umr_mkey; |
c3c94023 | 659 | struct mlx5e_dma_info wqe_overflow; |
0ddf5432 JDB |
660 | |
661 | /* XDP read-mostly */ | |
662 | struct xdp_rxq_info xdp_rxq; | |
432119de | 663 | cqe_ts_to_ns ptp_cyc2time; |
f62b8bb8 AV |
664 | } ____cacheline_aligned_in_smp; |
665 | ||
db05815b MM |
666 | enum mlx5e_channel_state { |
667 | MLX5E_CHANNEL_STATE_XSK, | |
668 | MLX5E_CHANNEL_NUM_STATES | |
669 | }; | |
670 | ||
f62b8bb8 AV |
671 | struct mlx5e_channel { |
672 | /* data path */ | |
673 | struct mlx5e_rq rq; | |
b9673cf5 | 674 | struct mlx5e_xdpsq rq_xdpsq; |
31391048 SM |
675 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
676 | struct mlx5e_icosq icosq; /* internal control operations */ | |
214baf22 | 677 | struct mlx5e_txqsq __rcu * __rcu *qos_sqs; |
b5503b99 | 678 | bool xdp; |
f62b8bb8 AV |
679 | struct napi_struct napi; |
680 | struct device *pdev; | |
681 | struct net_device *netdev; | |
682 | __be32 mkey_be; | |
214baf22 | 683 | u16 qos_sqs_size; |
f62b8bb8 | 684 | u8 num_tc; |
45f171b1 | 685 | u8 lag_port; |
f62b8bb8 | 686 | |
58b99ee3 TT |
687 | /* XDP_REDIRECT */ |
688 | struct mlx5e_xdpsq xdpsq; | |
689 | ||
db05815b MM |
690 | /* AF_XDP zero-copy */ |
691 | struct mlx5e_rq xskrq; | |
692 | struct mlx5e_xdpsq xsksq; | |
8d94b590 TT |
693 | |
694 | /* Async ICOSQ */ | |
695 | struct mlx5e_icosq async_icosq; | |
696 | /* async_icosq can be accessed from any CPU - the spinlock protects it. */ | |
697 | spinlock_t async_icosq_lock; | |
db05815b | 698 | |
a8c2eb15 | 699 | /* data path - accessed per napi poll */ |
6e745db4 | 700 | const struct cpumask *aff_mask; |
05909bab | 701 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
702 | |
703 | /* control */ | |
704 | struct mlx5e_priv *priv; | |
a43b25da | 705 | struct mlx5_core_dev *mdev; |
7c39afb3 | 706 | struct hwtstamp_config *tstamp; |
db05815b | 707 | DECLARE_BITMAP(state, MLX5E_CHANNEL_NUM_STATES); |
f62b8bb8 | 708 | int ix; |
231243c8 | 709 | int cpu; |
f62b8bb8 AV |
710 | }; |
711 | ||
b0d35de4 | 712 | struct mlx5e_ptp; |
145e5637 | 713 | |
ff9c852f SM |
714 | struct mlx5e_channels { |
715 | struct mlx5e_channel **c; | |
b0d35de4 | 716 | struct mlx5e_ptp *ptp; |
ff9c852f | 717 | unsigned int num; |
6a9764ef | 718 | struct mlx5e_params params; |
ff9c852f SM |
719 | }; |
720 | ||
05909bab EBE |
721 | struct mlx5e_channel_stats { |
722 | struct mlx5e_ch_stats ch; | |
723 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
724 | struct mlx5e_rq_stats rq; | |
db05815b | 725 | struct mlx5e_rq_stats xskrq; |
890388ad | 726 | struct mlx5e_xdpsq_stats rq_xdpsq; |
58b99ee3 | 727 | struct mlx5e_xdpsq_stats xdpsq; |
db05815b | 728 | struct mlx5e_xdpsq_stats xsksq; |
05909bab EBE |
729 | } ____cacheline_aligned_in_smp; |
730 | ||
b0d35de4 | 731 | struct mlx5e_ptp_stats { |
145e5637 EBE |
732 | struct mlx5e_ch_stats ch; |
733 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
1880bc4e | 734 | struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC]; |
a099da8f | 735 | struct mlx5e_rq_stats rq; |
145e5637 EBE |
736 | } ____cacheline_aligned_in_smp; |
737 | ||
acff797c | 738 | enum { |
acff797c MG |
739 | MLX5E_STATE_OPENED, |
740 | MLX5E_STATE_DESTROYING, | |
407e17b1 | 741 | MLX5E_STATE_XDP_TX_ENABLED, |
9cf88808 | 742 | MLX5E_STATE_XDP_ACTIVE, |
acff797c MG |
743 | }; |
744 | ||
acff797c MG |
745 | enum { |
746 | MLX5E_TC_PRIO = 0, | |
747 | MLX5E_NIC_PRIO | |
748 | }; | |
749 | ||
de8650a8 EBE |
750 | struct mlx5e_modify_sq_param { |
751 | int curr_state; | |
752 | int next_state; | |
753 | int rl_update; | |
754 | int rl_index; | |
214baf22 MM |
755 | bool qos_update; |
756 | u16 qos_queue_group_id; | |
de8650a8 EBE |
757 | }; |
758 | ||
cef35af3 EBE |
759 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
760 | struct mlx5e_hv_vhca_stats_agent { | |
761 | struct mlx5_hv_vhca_agent *agent; | |
762 | struct delayed_work work; | |
763 | u16 delay; | |
764 | void *buf; | |
765 | }; | |
766 | #endif | |
767 | ||
db05815b | 768 | struct mlx5e_xsk { |
1742b3d5 MK |
769 | /* XSK buffer pools are stored separately from channels, |
770 | * because we don't want to lose them when channels are | |
771 | * recreated. The kernel also stores buffer pool, but it doesn't | |
772 | * distinguish between zero-copy and non-zero-copy UMEMs, so | |
773 | * rely on our mechanism. | |
db05815b | 774 | */ |
1742b3d5 | 775 | struct xsk_buff_pool **pools; |
db05815b MM |
776 | u16 refcnt; |
777 | bool ever_used; | |
778 | }; | |
779 | ||
3909a12e MM |
780 | /* Temporary storage for variables that are allocated when struct mlx5e_priv is |
781 | * initialized, and used where we can't allocate them because that functions | |
782 | * must not fail. Use with care and make sure the same variable is not used | |
783 | * simultaneously by multiple users. | |
784 | */ | |
785 | struct mlx5e_scratchpad { | |
786 | cpumask_var_t cpumask; | |
787 | }; | |
788 | ||
214baf22 MM |
789 | struct mlx5e_htb { |
790 | DECLARE_HASHTABLE(qos_tc2node, order_base_2(MLX5E_QOS_MAX_LEAF_NODES)); | |
791 | DECLARE_BITMAP(qos_used_qids, MLX5E_QOS_MAX_LEAF_NODES); | |
792 | struct mlx5e_sq_stats **qos_sq_stats; | |
793 | u16 max_qos_sqs; | |
794 | u16 maj_id; | |
795 | u16 defcls; | |
796 | }; | |
797 | ||
5543e989 AL |
798 | struct mlx5e_trap; |
799 | ||
f62b8bb8 AV |
800 | struct mlx5e_priv { |
801 | /* priv data path fields - start */ | |
145e5637 | 802 | /* +1 for port ptp ts */ |
214baf22 MM |
803 | struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC + |
804 | MLX5E_QOS_MAX_LEAF_NODES]; | |
c55d8b10 | 805 | int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
145e5637 | 806 | int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC]; |
2a5e7a13 HN |
807 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
808 | struct mlx5e_dcbx_dp dcbx_dp; | |
809 | #endif | |
f62b8bb8 AV |
810 | /* priv data path fields - end */ |
811 | ||
79c48764 | 812 | u32 msglevel; |
f62b8bb8 AV |
813 | unsigned long state; |
814 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 815 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 816 | |
ff9c852f | 817 | struct mlx5e_channels channels; |
45f171b1 | 818 | u32 tisn[MLX5_MAX_PORTS][MLX5E_MAX_NUM_TC]; |
3f22d6c7 | 819 | struct mlx5e_rx_res *rx_res; |
507f0c81 | 820 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 821 | |
acff797c | 822 | struct mlx5e_flow_steering fs; |
f62b8bb8 | 823 | |
7bb29755 | 824 | struct workqueue_struct *wq; |
f62b8bb8 AV |
825 | struct work_struct update_carrier_work; |
826 | struct work_struct set_rx_mode_work; | |
3947ca18 | 827 | struct work_struct tx_timeout_work; |
cdeef2b1 | 828 | struct work_struct update_stats_work; |
5c7e8bbb ED |
829 | struct work_struct monitor_counters_work; |
830 | struct mlx5_nb monitor_counters_nb; | |
f62b8bb8 AV |
831 | |
832 | struct mlx5_core_dev *mdev; | |
833 | struct net_device *netdev; | |
5543e989 | 834 | struct mlx5e_trap *en_trap; |
f62b8bb8 | 835 | struct mlx5e_stats stats; |
05909bab | 836 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
5543e989 | 837 | struct mlx5e_channel_stats trap_stats; |
b0d35de4 | 838 | struct mlx5e_ptp_stats ptp_stats; |
694826e3 | 839 | u16 max_nch; |
05909bab | 840 | u8 max_opened_tc; |
b0d35de4 | 841 | bool tx_ptp_opened; |
a28359e9 | 842 | bool rx_ptp_opened; |
7c39afb3 | 843 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
844 | u16 q_counter; |
845 | u16 drop_rq_q_counter; | |
7cffaddd | 846 | struct notifier_block events_nb; |
70038b73 | 847 | struct notifier_block blocking_events_nb; |
145e5637 | 848 | int num_tc_x_num_ch; |
7cffaddd | 849 | |
18a2b7f9 | 850 | struct udp_tunnel_nic_info nic_info; |
3a6a931d HN |
851 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
852 | struct mlx5e_dcbx dcbx; | |
853 | #endif | |
854 | ||
6bfd390b | 855 | const struct mlx5e_profile *profile; |
127ea380 | 856 | void *ppriv; |
547eede0 IT |
857 | #ifdef CONFIG_MLX5_EN_IPSEC |
858 | struct mlx5e_ipsec *ipsec; | |
859 | #endif | |
43585a41 IL |
860 | #ifdef CONFIG_MLX5_EN_TLS |
861 | struct mlx5e_tls *tls; | |
862 | #endif | |
de8650a8 | 863 | struct devlink_health_reporter *tx_reporter; |
9032e719 | 864 | struct devlink_health_reporter *rx_reporter; |
db05815b | 865 | struct mlx5e_xsk xsk; |
cef35af3 EBE |
866 | #if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) |
867 | struct mlx5e_hv_vhca_stats_agent stats_agent; | |
868 | #endif | |
3909a12e | 869 | struct mlx5e_scratchpad scratchpad; |
214baf22 | 870 | struct mlx5e_htb htb; |
f62b8bb8 AV |
871 | }; |
872 | ||
5adf4c47 TT |
873 | struct mlx5e_rx_handlers { |
874 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
875 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
876 | }; | |
877 | ||
878 | extern const struct mlx5e_rx_handlers mlx5e_rx_handlers_nic; | |
879 | ||
a43b25da | 880 | struct mlx5e_profile { |
182570b2 | 881 | int (*init)(struct mlx5_core_dev *mdev, |
3ef14e46 | 882 | struct net_device *netdev); |
a43b25da SM |
883 | void (*cleanup)(struct mlx5e_priv *priv); |
884 | int (*init_rx)(struct mlx5e_priv *priv); | |
885 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
886 | int (*init_tx)(struct mlx5e_priv *priv); | |
887 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
888 | void (*enable)(struct mlx5e_priv *priv); | |
889 | void (*disable)(struct mlx5e_priv *priv); | |
a90f88fe | 890 | int (*update_rx)(struct mlx5e_priv *priv); |
a43b25da | 891 | void (*update_stats)(struct mlx5e_priv *priv); |
7ca42c80 | 892 | void (*update_carrier)(struct mlx5e_priv *priv); |
3460c184 | 893 | unsigned int (*stats_grps_num)(struct mlx5e_priv *priv); |
f0ff8e8c | 894 | mlx5e_stats_grp_t *stats_grps; |
5adf4c47 | 895 | const struct mlx5e_rx_handlers *rx_handlers; |
a43b25da | 896 | int max_tc; |
694826e3 | 897 | u8 rq_groups; |
3adb60b6 | 898 | bool rx_ptp_support; |
a43b25da SM |
899 | }; |
900 | ||
665bc539 GP |
901 | void mlx5e_build_ptys2ethtool_map(void); |
902 | ||
2ccb0a79 | 903 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
2ccb0a79 | 904 | |
d9ee0491 | 905 | void mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats); |
b832d4fd | 906 | void mlx5e_fold_sw_stats64(struct mlx5e_priv *priv, struct rtnl_link_stats64 *s); |
f62b8bb8 | 907 | |
33cfaaa8 | 908 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
d605d668 KH |
909 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
910 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
911 | u64 *buf); | |
f62b8bb8 AV |
912 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
913 | ||
1170fbd8 FD |
914 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
915 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 916 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 917 | |
f62b8bb8 AV |
918 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
919 | u16 vid); | |
920 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
921 | u16 vid); | |
237f258c | 922 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 923 | |
a6696735 | 924 | int mlx5e_modify_tirs_hash(struct mlx5e_priv *priv); |
2d75b2bc | 925 | |
db05815b MM |
926 | struct mlx5e_xsk_param; |
927 | ||
928 | struct mlx5e_rq_param; | |
869c5f92 AL |
929 | int mlx5e_open_rq(struct mlx5e_params *params, struct mlx5e_rq_param *param, |
930 | struct mlx5e_xsk_param *xsk, int node, | |
931 | struct mlx5e_rq *rq); | |
db05815b | 932 | int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq, int wait_time); |
db05815b | 933 | void mlx5e_close_rq(struct mlx5e_rq *rq); |
5543e989 AL |
934 | int mlx5e_create_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param); |
935 | void mlx5e_destroy_rq(struct mlx5e_rq *rq); | |
db05815b MM |
936 | |
937 | struct mlx5e_sq_param; | |
938 | int mlx5e_open_icosq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
939 | struct mlx5e_sq_param *param, struct mlx5e_icosq *sq); | |
940 | void mlx5e_close_icosq(struct mlx5e_icosq *sq); | |
941 | int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params, | |
1742b3d5 | 942 | struct mlx5e_sq_param *param, struct xsk_buff_pool *xsk_pool, |
db05815b MM |
943 | struct mlx5e_xdpsq *sq, bool is_redirect); |
944 | void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq); | |
945 | ||
4d0b7ef9 AL |
946 | struct mlx5e_create_cq_param { |
947 | struct napi_struct *napi; | |
948 | struct mlx5e_ch_stats *ch_stats; | |
949 | int node; | |
950 | int ix; | |
951 | }; | |
952 | ||
db05815b | 953 | struct mlx5e_cq_param; |
4d0b7ef9 AL |
954 | int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder, |
955 | struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp, | |
956 | struct mlx5e_cq *cq); | |
db05815b MM |
957 | void mlx5e_close_cq(struct mlx5e_cq *cq); |
958 | ||
f62b8bb8 AV |
959 | int mlx5e_open_locked(struct net_device *netdev); |
960 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
961 | |
962 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
963 | struct mlx5e_channels *chs); | |
964 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 | 965 | |
dca147b3 | 966 | /* Function pointer to be used to modify HW or kernel settings while |
2e20a151 SM |
967 | * switching channels |
968 | */ | |
b9ab5d0e MM |
969 | typedef int (*mlx5e_fp_preactivate)(struct mlx5e_priv *priv, void *context); |
970 | #define MLX5E_DEFINE_PREACTIVATE_WRAPPER_CTX(fn) \ | |
971 | int fn##_ctx(struct mlx5e_priv *priv, void *context) \ | |
972 | { \ | |
973 | return fn(priv); \ | |
974 | } | |
484c1ada | 975 | int mlx5e_safe_reopen_channels(struct mlx5e_priv *priv); |
94872d4e MM |
976 | int mlx5e_safe_switch_params(struct mlx5e_priv *priv, |
977 | struct mlx5e_params *new_params, | |
978 | mlx5e_fp_preactivate preactivate, | |
979 | void *context, bool reset); | |
214baf22 | 980 | int mlx5e_update_tx_netdev_queues(struct mlx5e_priv *priv); |
fe867cac | 981 | int mlx5e_num_channels_changed(struct mlx5e_priv *priv); |
b9ab5d0e | 982 | int mlx5e_num_channels_changed_ctx(struct mlx5e_priv *priv, void *context); |
603f4a45 SM |
983 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
984 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
885b8cfb | 985 | int mlx5e_ptp_rx_manage_fs_ctx(struct mlx5e_priv *priv, void *ctx); |
55c2503d | 986 | |
d4b6c488 | 987 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 988 | int num_channels); |
ebeaf084 | 989 | |
be5323c8 AL |
990 | int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state, int next_state); |
991 | void mlx5e_activate_rq(struct mlx5e_rq *rq); | |
992 | void mlx5e_deactivate_rq(struct mlx5e_rq *rq); | |
be5323c8 AL |
993 | void mlx5e_activate_icosq(struct mlx5e_icosq *icosq); |
994 | void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq); | |
9908aa29 | 995 | |
de8650a8 EBE |
996 | int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn, |
997 | struct mlx5e_modify_sq_param *p); | |
214baf22 MM |
998 | int mlx5e_open_txqsq(struct mlx5e_channel *c, u32 tisn, int txq_ix, |
999 | struct mlx5e_params *params, struct mlx5e_sq_param *param, | |
1000 | struct mlx5e_txqsq *sq, int tc, u16 qos_queue_group_id, u16 qos_qid); | |
de8650a8 | 1001 | void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq); |
145e5637 EBE |
1002 | void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq); |
1003 | void mlx5e_free_txqsq(struct mlx5e_txqsq *sq); | |
de8650a8 | 1004 | void mlx5e_tx_disable_queue(struct netdev_queue *txq); |
145e5637 EBE |
1005 | int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa); |
1006 | void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq); | |
1007 | struct mlx5e_create_sq_param; | |
1008 | int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev, | |
1009 | struct mlx5e_sq_param *param, | |
1010 | struct mlx5e_create_sq_param *csp, | |
214baf22 | 1011 | u16 qos_queue_group_id, |
145e5637 EBE |
1012 | u32 *sqn); |
1013 | void mlx5e_tx_err_cqe_work(struct work_struct *recover_work); | |
214baf22 | 1014 | void mlx5e_close_txqsq(struct mlx5e_txqsq *sq); |
de8650a8 | 1015 | |
e3cfc7e6 MS |
1016 | static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev) |
1017 | { | |
1018 | return MLX5_CAP_ETH(mdev, swp) && | |
1019 | MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); | |
1020 | } | |
1021 | ||
f62b8bb8 | 1022 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac | 1023 | |
b50d292b HHZ |
1024 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1025 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
80639b19 ES |
1026 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb, |
1027 | bool enable_mc_lb); | |
17347d54 | 1028 | void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc); |
1afff42c | 1029 | |
bc81b9d3 | 1030 | /* common netdev helpers */ |
1462e48d RD |
1031 | void mlx5e_create_q_counters(struct mlx5e_priv *priv); |
1032 | void mlx5e_destroy_q_counters(struct mlx5e_priv *priv); | |
1033 | int mlx5e_open_drop_rq(struct mlx5e_priv *priv, | |
1034 | struct mlx5e_rq *drop_rq); | |
1035 | void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq); | |
cf747609 AL |
1036 | int mlx5e_init_di_list(struct mlx5e_rq *rq, int wq_sz, int node); |
1037 | void mlx5e_free_di_list(struct mlx5e_rq *rq); | |
1462e48d | 1038 | |
8f493ffd SM |
1039 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1040 | ||
46dc933c | 1041 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc); |
a16b8e0d | 1042 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); |
8f493ffd | 1043 | |
0570c1c9 MM |
1044 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
1045 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); | |
1046 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); | |
1047 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd | 1048 | |
2b257a6e | 1049 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, void *in, u32 *tisn); |
5426a0b2 SM |
1050 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); |
1051 | ||
cb67b832 | 1052 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
3c145626 | 1053 | void mlx5e_destroy_tises(struct mlx5e_priv *priv); |
a90f88fe | 1054 | int mlx5e_update_nic_rx(struct mlx5e_priv *priv); |
b36cdb42 | 1055 | void mlx5e_update_carrier(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1056 | int mlx5e_close(struct net_device *netdev); |
1057 | int mlx5e_open(struct net_device *netdev); | |
cb67b832 | 1058 | |
cdeef2b1 | 1059 | void mlx5e_queue_update_stats(struct mlx5e_priv *priv); |
3f6d08d1 | 1060 | |
d9ee0491 | 1061 | int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv); |
b9ab5d0e | 1062 | int mlx5e_set_dev_port_mtu_ctx(struct mlx5e_priv *priv, void *context); |
250a42b6 | 1063 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, |
b9ab5d0e | 1064 | mlx5e_fp_preactivate preactivate); |
18a2b7f9 | 1065 | void mlx5e_vxlan_set_netdev_info(struct mlx5e_priv *priv); |
250a42b6 | 1066 | |
076b0936 ES |
1067 | /* ethtool helpers */ |
1068 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1069 | struct ethtool_drvinfo *drvinfo); | |
1070 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1071 | uint32_t stringset, uint8_t *data); | |
1072 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1073 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1074 | struct ethtool_stats *stats, u64 *data); | |
1075 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1076 | struct ethtool_ringparam *param); | |
1077 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1078 | struct ethtool_ringparam *param); | |
1079 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1080 | struct ethtool_channels *ch); | |
1081 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1082 | struct ethtool_channels *ch); | |
1083 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1084 | struct ethtool_coalesce *coal); | |
1085 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1086 | struct ethtool_coalesce *coal); | |
371289b6 OG |
1087 | int mlx5e_ethtool_get_link_ksettings(struct mlx5e_priv *priv, |
1088 | struct ethtool_link_ksettings *link_ksettings); | |
1089 | int mlx5e_ethtool_set_link_ksettings(struct mlx5e_priv *priv, | |
1090 | const struct ethtool_link_ksettings *link_ksettings); | |
01013ad3 VB |
1091 | int mlx5e_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); |
1092 | int mlx5e_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, | |
1093 | const u8 hfunc); | |
b63293e7 VB |
1094 | int mlx5e_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info, |
1095 | u32 *rule_locs); | |
1096 | int mlx5e_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); | |
a5355de8 OG |
1097 | u32 mlx5e_ethtool_get_rxfh_key_size(struct mlx5e_priv *priv); |
1098 | u32 mlx5e_ethtool_get_rxfh_indir_size(struct mlx5e_priv *priv); | |
3844b07e FD |
1099 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1100 | struct ethtool_ts_info *info); | |
f43d48d1 EBE |
1101 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1102 | struct ethtool_flash *flash); | |
371289b6 OG |
1103 | void mlx5e_ethtool_get_pauseparam(struct mlx5e_priv *priv, |
1104 | struct ethtool_pauseparam *pauseparam); | |
1105 | int mlx5e_ethtool_set_pauseparam(struct mlx5e_priv *priv, | |
1106 | struct ethtool_pauseparam *pauseparam); | |
076b0936 | 1107 | |
2c3b5bee | 1108 | /* mlx5e generic netdev management API */ |
c4d7eb57 SM |
1109 | static inline unsigned int |
1110 | mlx5e_calc_max_nch(struct mlx5e_priv *priv, const struct mlx5e_profile *profile) | |
3ef14e46 | 1111 | { |
c4d7eb57 | 1112 | return priv->netdev->num_rx_queues / max_t(u8, profile->rq_groups, 1); |
3ef14e46 SM |
1113 | } |
1114 | ||
040ee617 AH |
1115 | static inline bool |
1116 | mlx5e_tx_mpwqe_supported(struct mlx5_core_dev *mdev) | |
1117 | { | |
1118 | return !is_kdump_kernel() && | |
1119 | MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); | |
1120 | } | |
1121 | ||
c9fd1e33 RD |
1122 | int mlx5e_priv_init(struct mlx5e_priv *priv, |
1123 | struct net_device *netdev, | |
1124 | struct mlx5_core_dev *mdev); | |
1125 | void mlx5e_priv_cleanup(struct mlx5e_priv *priv); | |
3ef14e46 SM |
1126 | struct net_device * |
1127 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, unsigned int txqs, unsigned int rxqs); | |
2c3b5bee SM |
1128 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); |
1129 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1130 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
c4d7eb57 SM |
1131 | int mlx5e_netdev_change_profile(struct mlx5e_priv *priv, |
1132 | const struct mlx5e_profile *new_profile, void *new_ppriv); | |
7a9fb35e | 1133 | void mlx5e_netdev_attach_nic_profile(struct mlx5e_priv *priv); |
6d7ee2ed | 1134 | void mlx5e_set_netdev_mtu_boundaries(struct mlx5e_priv *priv); |
3ef14e46 | 1135 | void mlx5e_build_nic_params(struct mlx5e_priv *priv, struct mlx5e_xsk *xsk, u16 mtu); |
bbeb53b8 AL |
1136 | void mlx5e_build_rss_params(struct mlx5e_rss_params *rss_params, |
1137 | u16 num_channels); | |
9a317425 | 1138 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1139 | void mlx5e_tx_dim_work(struct work_struct *work); |
073caf50 | 1140 | |
073caf50 OG |
1141 | netdev_features_t mlx5e_features_check(struct sk_buff *skb, |
1142 | struct net_device *netdev, | |
1143 | netdev_features_t features); | |
d3cbd425 | 1144 | int mlx5e_set_features(struct net_device *netdev, netdev_features_t features); |
073caf50 OG |
1145 | #ifdef CONFIG_MLX5_ESWITCH |
1146 | int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac); | |
1147 | int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, int max_tx_rate); | |
1148 | int mlx5e_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivi); | |
1149 | int mlx5e_get_vf_stats(struct net_device *dev, int vf, struct ifla_vf_stats *vf_stats); | |
1150 | #endif | |
1afff42c | 1151 | #endif /* __MLX5_EN_H__ */ |