Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
1ae1df3a | 47 | #include <linux/mlx5/fs.h> |
e8f887ac | 48 | #include <linux/rhashtable.h> |
cb67b832 | 49 | #include <net/switchdev.h> |
0ddf5432 | 50 | #include <net/xdp.h> |
4c4dbb4a | 51 | #include <linux/net_dim.h> |
f62b8bb8 | 52 | #include "wq.h" |
f62b8bb8 | 53 | #include "mlx5_core.h" |
9218b44d | 54 | #include "en_stats.h" |
f62b8bb8 | 55 | |
60bbf7ee JDB |
56 | struct page_pool; |
57 | ||
bb909416 IL |
58 | #define MLX5E_METADATA_ETHER_TYPE (0x8CE4) |
59 | #define MLX5E_METADATA_ETHER_LEN 8 | |
60 | ||
1cabe6b0 MG |
61 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
62 | ||
c139dbfd ES |
63 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
64 | ||
472a1e44 TT |
65 | #define MLX5E_HW2SW_MTU(params, hwmtu) ((hwmtu) - ((params)->hard_mtu)) |
66 | #define MLX5E_SW2HW_MTU(params, swmtu) ((swmtu) + ((params)->hard_mtu)) | |
d8bec2b2 | 67 | |
0696d608 | 68 | #define MLX5E_MAX_PRIORITY 8 |
2a5e7a13 | 69 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
70 | #define MLX5E_MAX_NUM_TC 8 |
71 | ||
1bfecfca | 72 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
73 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
74 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 75 | |
f32f5bd2 DJ |
76 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
77 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
78 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
79 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
80 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
81 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
696a97cf EE |
82 | #define MLX5E_MPWQE_STRIDE_SZ(mdev, cqe_cmprs) \ |
83 | (cqe_cmprs ? MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) : \ | |
84 | MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev)) | |
f32f5bd2 | 85 | |
7e426671 | 86 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
87 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
88 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
89 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
90 | |
91 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
73281b78 | 92 | #define MLX5E_REQUIRED_WQE_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) |
b8a98a4c | 93 | #define MLX5E_LOG_ALIGNED_MPWQE_PPW (ilog2(MLX5E_REQUIRED_WQE_MTTS)) |
73281b78 TT |
94 | #define MLX5E_REQUIRED_MTTS(wqes) (wqes * MLX5E_REQUIRED_WQE_MTTS) |
95 | #define MLX5E_MAX_RQ_NUM_MTTS \ | |
96 | ((1 << 16) * 2) /* So that MLX5_MTT_OCTW(num_mtts) fits into u16 */ | |
97 | #define MLX5E_ORDER2_MAX_PACKET_MTU (order_base_2(10 * 1024)) | |
98 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW \ | |
99 | (ilog2(MLX5E_MAX_RQ_NUM_MTTS / MLX5E_REQUIRED_WQE_MTTS)) | |
100 | #define MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW \ | |
101 | (MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW + \ | |
102 | (MLX5_MPWRQ_LOG_WQE_SZ - MLX5E_ORDER2_MAX_PACKET_MTU)) | |
103 | ||
069d1146 TT |
104 | #define MLX5E_MIN_SKB_FRAG_SZ (MLX5_SKB_FRAG_SZ(MLX5_RX_HEADROOM)) |
105 | #define MLX5E_LOG_MAX_RX_WQE_BULK \ | |
106 | (ilog2(PAGE_SIZE / roundup_pow_of_two(MLX5E_MIN_SKB_FRAG_SZ))) | |
107 | ||
73281b78 TT |
108 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
109 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa | |
110 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
111 | ||
069d1146 | 112 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE (1 + MLX5E_LOG_MAX_RX_WQE_BULK) |
73281b78 TT |
113 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
114 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE min_t(u8, 0xd, \ | |
115 | MLX5E_LOG_MAX_RQ_NUM_PACKETS_MPW) | |
116 | ||
117 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 | |
fe4c988b | 118 | |
75aa889f | 119 | #define MLX5E_RX_MAX_HEAD (256) |
461017cb | 120 | |
d9a40271 | 121 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
122 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
123 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
124 | ||
f62b8bb8 | 125 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 126 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
127 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
128 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 129 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
130 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
131 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 132 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 133 | |
936896e9 AS |
134 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
135 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 136 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 137 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 138 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
139 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
140 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
db75373c | 141 | #define MLX5E_SQ_RECOVER_MIN_INTERVAL 500 /* msecs */ |
f62b8bb8 | 142 | |
ea3886ca TT |
143 | #define MLX5E_UMR_WQE_INLINE_SZ \ |
144 | (sizeof(struct mlx5e_umr_wqe) + \ | |
145 | ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(struct mlx5_mtt), \ | |
146 | MLX5_UMR_MTT_ALIGNMENT)) | |
147 | #define MLX5E_UMR_WQEBBS \ | |
148 | (DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_BB)) | |
149 | #define MLX5E_ICOSQ_MAX_WQEBBS MLX5E_UMR_WQEBBS | |
f10b7cc7 | 150 | |
b5503b99 | 151 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 152 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 153 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 154 | |
86d722ad | 155 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 156 | |
79c48764 GP |
157 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
158 | ||
159 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
160 | do { \ | |
161 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
162 | netdev_warn(priv->netdev, format, \ | |
163 | ##__VA_ARGS__); \ | |
164 | } while (0) | |
165 | ||
166 | ||
461017cb TT |
167 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
168 | { | |
169 | switch (wq_type) { | |
170 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
171 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
172 | wq_size / 2); | |
173 | default: | |
174 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
175 | wq_size / 2); | |
176 | } | |
177 | } | |
178 | ||
48935bbb SM |
179 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
180 | { | |
181 | return is_kdump_kernel() ? | |
182 | MLX5E_MIN_NUM_CHANNELS : | |
183 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
184 | MLX5E_MAX_NUM_CHANNELS); | |
185 | } | |
186 | ||
2f48af12 TT |
187 | struct mlx5e_tx_wqe { |
188 | struct mlx5_wqe_ctrl_seg ctrl; | |
189 | struct mlx5_wqe_eth_seg eth; | |
043dc78e | 190 | struct mlx5_wqe_data_seg data[0]; |
2f48af12 TT |
191 | }; |
192 | ||
99cbfa93 | 193 | struct mlx5e_rx_wqe_ll { |
2f48af12 | 194 | struct mlx5_wqe_srq_next_seg next; |
99cbfa93 TT |
195 | struct mlx5_wqe_data_seg data[0]; |
196 | }; | |
197 | ||
198 | struct mlx5e_rx_wqe_cyc { | |
199 | struct mlx5_wqe_data_seg data[0]; | |
2f48af12 | 200 | }; |
86d722ad | 201 | |
bc77b240 TT |
202 | struct mlx5e_umr_wqe { |
203 | struct mlx5_wqe_ctrl_seg ctrl; | |
204 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
205 | struct mlx5_mkey_seg mkc; | |
ea3886ca | 206 | struct mlx5_mtt inline_mtts[0]; |
bc77b240 TT |
207 | }; |
208 | ||
d605d668 KH |
209 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
210 | ||
4e59e288 | 211 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 212 | "rx_cqe_moder", |
0088cbbc | 213 | "tx_cqe_moder", |
9bcc8606 | 214 | "rx_cqe_compress", |
2ccb0a79 | 215 | "rx_striding_rq", |
4e59e288 GP |
216 | }; |
217 | ||
218 | enum mlx5e_priv_flag { | |
9908aa29 | 219 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
0088cbbc TG |
220 | MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1), |
221 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2), | |
2ccb0a79 | 222 | MLX5E_PFLAG_RX_STRIDING_RQ = (1 << 3), |
4e59e288 GP |
223 | }; |
224 | ||
6a9764ef | 225 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
226 | do { \ |
227 | if (enable) \ | |
6a9764ef | 228 | (params)->pflags |= (pflag); \ |
59ece1c9 | 229 | else \ |
6a9764ef | 230 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
231 | } while (0) |
232 | ||
6a9764ef | 233 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 234 | |
08fb1dac SM |
235 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
236 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
237 | #endif |
238 | ||
f62b8bb8 AV |
239 | struct mlx5e_params { |
240 | u8 log_sq_size; | |
461017cb | 241 | u8 rq_wq_type; |
73281b78 | 242 | u8 log_rq_mtu_frames; |
f62b8bb8 | 243 | u16 num_channels; |
f62b8bb8 | 244 | u8 num_tc; |
9bcc8606 | 245 | bool rx_cqe_compress_def; |
9a317425 AG |
246 | struct net_dim_cq_moder rx_cq_moderation; |
247 | struct net_dim_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
248 | bool lro_en; |
249 | u32 lro_wqe_sz; | |
cff92d7c | 250 | u8 tx_min_inline_mode; |
2d75b2bc AS |
251 | u8 rss_hfunc; |
252 | u8 toeplitz_hash_key[40]; | |
253 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 254 | bool vlan_strip_disable; |
102722fc | 255 | bool scatter_fcs_en; |
9a317425 | 256 | bool rx_dim_enabled; |
cbce4f44 | 257 | bool tx_dim_enabled; |
2b029556 | 258 | u32 lro_timeout; |
59ece1c9 | 259 | u32 pflags; |
6a9764ef | 260 | struct bpf_prog *xdp_prog; |
472a1e44 TT |
261 | unsigned int sw_mtu; |
262 | int hard_mtu; | |
f62b8bb8 AV |
263 | }; |
264 | ||
3a6a931d HN |
265 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
266 | struct mlx5e_cee_config { | |
267 | /* bw pct for priority group */ | |
268 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
269 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
270 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
271 | bool pfc_enable; | |
272 | }; | |
273 | ||
274 | enum { | |
275 | MLX5_DCB_CHG_RESET, | |
276 | MLX5_DCB_NO_CHG, | |
277 | MLX5_DCB_CHG_NO_RESET, | |
278 | }; | |
279 | ||
280 | struct mlx5e_dcbx { | |
e207b7e9 | 281 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 282 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 283 | u8 dscp_app_cnt; |
820c2c5e HN |
284 | |
285 | /* The only setting that cannot be read from FW */ | |
286 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 287 | u8 cap; |
0696d608 HN |
288 | |
289 | /* Buffer configuration */ | |
ecdf2dad | 290 | bool manual_buffer; |
0696d608 HN |
291 | u32 cable_len; |
292 | u32 xoff; | |
3a6a931d | 293 | }; |
2a5e7a13 HN |
294 | |
295 | struct mlx5e_dcbx_dp { | |
296 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
297 | u8 trust_state; | |
298 | }; | |
3a6a931d HN |
299 | #endif |
300 | ||
f62b8bb8 | 301 | enum { |
c0f1147d | 302 | MLX5E_RQ_STATE_ENABLED, |
cb3c7fd4 | 303 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
304 | }; |
305 | ||
f62b8bb8 AV |
306 | struct mlx5e_cq { |
307 | /* data path - accessed per cqe */ | |
308 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
309 | |
310 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 311 | u16 event_ctr; |
f62b8bb8 AV |
312 | struct napi_struct *napi; |
313 | struct mlx5_core_cq mcq; | |
314 | struct mlx5e_channel *channel; | |
315 | ||
7219ab34 TT |
316 | /* cqe decompression */ |
317 | struct mlx5_cqe64 title; | |
318 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
319 | u8 mini_arr_idx; | |
320 | u16 decmprs_left; | |
321 | u16 decmprs_wqe_counter; | |
322 | ||
f62b8bb8 | 323 | /* control */ |
a43b25da | 324 | struct mlx5_core_dev *mdev; |
3a2f7033 | 325 | struct mlx5_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
326 | } ____cacheline_aligned_in_smp; |
327 | ||
eba2db2b | 328 | struct mlx5e_tx_wqe_info { |
77bdf895 | 329 | struct sk_buff *skb; |
eba2db2b SM |
330 | u32 num_bytes; |
331 | u8 num_wqebbs; | |
332 | u8 num_dma; | |
333 | }; | |
334 | ||
335 | enum mlx5e_dma_map_type { | |
336 | MLX5E_DMA_MAP_SINGLE, | |
337 | MLX5E_DMA_MAP_PAGE | |
338 | }; | |
339 | ||
340 | struct mlx5e_sq_dma { | |
341 | dma_addr_t addr; | |
342 | u32 size; | |
343 | enum mlx5e_dma_map_type type; | |
344 | }; | |
345 | ||
346 | enum { | |
347 | MLX5E_SQ_STATE_ENABLED, | |
db75373c | 348 | MLX5E_SQ_STATE_RECOVERING, |
2ac9cfe7 | 349 | MLX5E_SQ_STATE_IPSEC, |
cbce4f44 | 350 | MLX5E_SQ_STATE_AM, |
bf239741 | 351 | MLX5E_SQ_STATE_TLS, |
eba2db2b SM |
352 | }; |
353 | ||
354 | struct mlx5e_sq_wqe_info { | |
355 | u8 opcode; | |
eba2db2b | 356 | }; |
2f48af12 | 357 | |
31391048 | 358 | struct mlx5e_txqsq { |
eba2db2b SM |
359 | /* data path */ |
360 | ||
361 | /* dirtied @completion */ | |
362 | u16 cc; | |
363 | u32 dma_fifo_cc; | |
cbce4f44 | 364 | struct net_dim dim; /* Adaptive Moderation */ |
eba2db2b SM |
365 | |
366 | /* dirtied @xmit */ | |
367 | u16 pc ____cacheline_aligned_in_smp; | |
368 | u32 dma_fifo_pc; | |
eba2db2b SM |
369 | |
370 | struct mlx5e_cq cq; | |
371 | ||
31391048 SM |
372 | /* write@xmit, read@completion */ |
373 | struct { | |
31391048 SM |
374 | struct mlx5e_sq_dma *dma_fifo; |
375 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
376 | } db; |
377 | ||
378 | /* read only */ | |
379 | struct mlx5_wq_cyc wq; | |
380 | u32 dma_fifo_mask; | |
05909bab | 381 | struct mlx5e_sq_stats *stats; |
eba2db2b SM |
382 | void __iomem *uar_map; |
383 | struct netdev_queue *txq; | |
384 | u32 sqn; | |
eba2db2b | 385 | u8 min_inline_mode; |
eba2db2b | 386 | struct device *pdev; |
eba2db2b SM |
387 | __be32 mkey_be; |
388 | unsigned long state; | |
7c39afb3 FD |
389 | struct hwtstamp_config *tstamp; |
390 | struct mlx5_clock *clock; | |
eba2db2b SM |
391 | |
392 | /* control path */ | |
393 | struct mlx5_wq_ctrl wq_ctrl; | |
394 | struct mlx5e_channel *channel; | |
acc6c595 | 395 | int txq_ix; |
eba2db2b | 396 | u32 rate_limit; |
db75373c EBE |
397 | struct mlx5e_txqsq_recover { |
398 | struct work_struct recover_work; | |
399 | u64 last_recover; | |
400 | } recover; | |
31391048 SM |
401 | } ____cacheline_aligned_in_smp; |
402 | ||
403 | struct mlx5e_xdpsq { | |
404 | /* data path */ | |
405 | ||
406 | /* dirtied @rx completion */ | |
407 | u16 cc; | |
408 | u16 pc; | |
409 | ||
410 | struct mlx5e_cq cq; | |
411 | ||
412 | /* write@xmit, read@completion */ | |
413 | struct { | |
414 | struct mlx5e_dma_info *di; | |
415 | bool doorbell; | |
5168d732 | 416 | bool redirect_flush; |
31391048 SM |
417 | } db; |
418 | ||
419 | /* read only */ | |
420 | struct mlx5_wq_cyc wq; | |
421 | void __iomem *uar_map; | |
422 | u32 sqn; | |
423 | struct device *pdev; | |
424 | __be32 mkey_be; | |
425 | u8 min_inline_mode; | |
426 | unsigned long state; | |
427 | ||
428 | /* control path */ | |
429 | struct mlx5_wq_ctrl wq_ctrl; | |
430 | struct mlx5e_channel *channel; | |
431 | } ____cacheline_aligned_in_smp; | |
432 | ||
433 | struct mlx5e_icosq { | |
434 | /* data path */ | |
435 | ||
31391048 SM |
436 | /* dirtied @xmit */ |
437 | u16 pc ____cacheline_aligned_in_smp; | |
31391048 SM |
438 | |
439 | struct mlx5e_cq cq; | |
440 | ||
441 | /* write@xmit, read@completion */ | |
442 | struct { | |
443 | struct mlx5e_sq_wqe_info *ico_wqe; | |
444 | } db; | |
445 | ||
446 | /* read only */ | |
447 | struct mlx5_wq_cyc wq; | |
448 | void __iomem *uar_map; | |
449 | u32 sqn; | |
31391048 SM |
450 | unsigned long state; |
451 | ||
452 | /* control path */ | |
453 | struct mlx5_wq_ctrl wq_ctrl; | |
454 | struct mlx5e_channel *channel; | |
eba2db2b SM |
455 | } ____cacheline_aligned_in_smp; |
456 | ||
864b2d71 SM |
457 | static inline bool |
458 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 459 | { |
ddf385e3 | 460 | return (mlx5_wq_cyc_ctr2ix(wq, cc - pc) >= n) || (cc == pc); |
eba2db2b | 461 | } |
6cd392a0 | 462 | |
461017cb TT |
463 | struct mlx5e_dma_info { |
464 | struct page *page; | |
465 | dma_addr_t addr; | |
466 | }; | |
467 | ||
accd5883 | 468 | struct mlx5e_wqe_frag_info { |
069d1146 | 469 | struct mlx5e_dma_info *di; |
accd5883 | 470 | u32 offset; |
069d1146 | 471 | bool last_in_page; |
accd5883 TT |
472 | }; |
473 | ||
eba2db2b | 474 | struct mlx5e_umr_dma_info { |
eba2db2b | 475 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; |
eba2db2b SM |
476 | }; |
477 | ||
478 | struct mlx5e_mpw_info { | |
479 | struct mlx5e_umr_dma_info umr; | |
480 | u16 consumed_strides; | |
22f45398 | 481 | DECLARE_BITMAP(xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE); |
eba2db2b SM |
482 | }; |
483 | ||
069d1146 TT |
484 | #define MLX5E_MAX_RX_FRAGS 4 |
485 | ||
4415a031 TT |
486 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
487 | * or a MPWQE (for striding rq). | |
488 | */ | |
489 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
490 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 491 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
492 | struct mlx5e_page_cache { |
493 | u32 head; | |
494 | u32 tail; | |
495 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
496 | }; | |
497 | ||
eba2db2b SM |
498 | struct mlx5e_rq; |
499 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
619a8f2a TT |
500 | typedef struct sk_buff * |
501 | (*mlx5e_fp_skb_from_cqe_mpwrq)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
502 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
503 | typedef struct sk_buff * |
504 | (*mlx5e_fp_skb_from_cqe)(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
505 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
7cc6d77b | 506 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
507 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
508 | ||
121e8927 TT |
509 | enum mlx5e_rq_flag { |
510 | MLX5E_RQ_FLAG_XDP_XMIT = BIT(0), | |
511 | }; | |
512 | ||
069d1146 TT |
513 | struct mlx5e_rq_frag_info { |
514 | int frag_size; | |
515 | int frag_stride; | |
516 | }; | |
517 | ||
518 | struct mlx5e_rq_frags_info { | |
519 | struct mlx5e_rq_frag_info arr[MLX5E_MAX_RX_FRAGS]; | |
520 | u8 num_frags; | |
521 | u8 log_num_frags; | |
522 | u8 wqe_bulk; | |
523 | }; | |
524 | ||
f62b8bb8 AV |
525 | struct mlx5e_rq { |
526 | /* data path */ | |
21c59685 | 527 | union { |
accd5883 | 528 | struct { |
069d1146 TT |
529 | struct mlx5_wq_cyc wq; |
530 | struct mlx5e_wqe_frag_info *frags; | |
531 | struct mlx5e_dma_info *di; | |
532 | struct mlx5e_rq_frags_info info; | |
533 | mlx5e_fp_skb_from_cqe skb_from_cqe; | |
accd5883 | 534 | } wqe; |
21c59685 | 535 | struct { |
422d4c40 | 536 | struct mlx5_wq_ll wq; |
b8a98a4c | 537 | struct mlx5e_umr_wqe umr_wqe; |
21c59685 | 538 | struct mlx5e_mpw_info *info; |
619a8f2a | 539 | mlx5e_fp_skb_from_cqe_mpwrq skb_from_cqe_mpwrq; |
b45d8b50 | 540 | u16 num_strides; |
89e89f7a | 541 | u8 log_stride_sz; |
a071cb9f | 542 | bool umr_in_progress; |
21c59685 SM |
543 | } mpwqe; |
544 | }; | |
1bfecfca | 545 | struct { |
b45d8b50 | 546 | u16 headroom; |
b5503b99 | 547 | u8 map_dir; /* dma map direction */ |
1bfecfca | 548 | } buff; |
f62b8bb8 | 549 | |
7cc6d77b | 550 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
551 | struct device *pdev; |
552 | struct net_device *netdev; | |
05909bab | 553 | struct mlx5e_rq_stats *stats; |
f62b8bb8 | 554 | struct mlx5e_cq cq; |
4415a031 | 555 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
556 | struct hwtstamp_config *tstamp; |
557 | struct mlx5_clock *clock; | |
4415a031 | 558 | |
2f48af12 | 559 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 560 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 561 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
562 | |
563 | unsigned long state; | |
564 | int ix; | |
565 | ||
9a317425 | 566 | struct net_dim dim; /* Dynamic Interrupt Moderation */ |
31871f87 SM |
567 | |
568 | /* XDP */ | |
86994156 | 569 | struct bpf_prog *xdp_prog; |
472a1e44 | 570 | unsigned int hw_mtu; |
31391048 | 571 | struct mlx5e_xdpsq xdpsq; |
121e8927 | 572 | DECLARE_BITMAP(flags, 8); |
60bbf7ee | 573 | struct page_pool *page_pool; |
cb3c7fd4 | 574 | |
f62b8bb8 AV |
575 | /* control */ |
576 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 577 | __be32 mkey_be; |
461017cb | 578 | u8 wq_type; |
f62b8bb8 | 579 | u32 rqn; |
a43b25da | 580 | struct mlx5_core_dev *mdev; |
ec8b9981 | 581 | struct mlx5_core_mkey umr_mkey; |
0ddf5432 JDB |
582 | |
583 | /* XDP read-mostly */ | |
584 | struct xdp_rxq_info xdp_rxq; | |
f62b8bb8 AV |
585 | } ____cacheline_aligned_in_smp; |
586 | ||
f62b8bb8 AV |
587 | struct mlx5e_channel { |
588 | /* data path */ | |
589 | struct mlx5e_rq rq; | |
31391048 SM |
590 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
591 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 592 | bool xdp; |
f62b8bb8 AV |
593 | struct napi_struct napi; |
594 | struct device *pdev; | |
595 | struct net_device *netdev; | |
596 | __be32 mkey_be; | |
597 | u8 num_tc; | |
f62b8bb8 | 598 | |
a8c2eb15 TT |
599 | /* data path - accessed per napi poll */ |
600 | struct irq_desc *irq_desc; | |
05909bab | 601 | struct mlx5e_ch_stats *stats; |
f62b8bb8 AV |
602 | |
603 | /* control */ | |
604 | struct mlx5e_priv *priv; | |
a43b25da | 605 | struct mlx5_core_dev *mdev; |
7c39afb3 | 606 | struct hwtstamp_config *tstamp; |
f62b8bb8 | 607 | int ix; |
231243c8 | 608 | int cpu; |
f62b8bb8 AV |
609 | }; |
610 | ||
ff9c852f SM |
611 | struct mlx5e_channels { |
612 | struct mlx5e_channel **c; | |
613 | unsigned int num; | |
6a9764ef | 614 | struct mlx5e_params params; |
ff9c852f SM |
615 | }; |
616 | ||
05909bab EBE |
617 | struct mlx5e_channel_stats { |
618 | struct mlx5e_ch_stats ch; | |
619 | struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC]; | |
620 | struct mlx5e_rq_stats rq; | |
621 | } ____cacheline_aligned_in_smp; | |
622 | ||
f62b8bb8 | 623 | enum mlx5e_traffic_types { |
5a6f8aef AS |
624 | MLX5E_TT_IPV4_TCP, |
625 | MLX5E_TT_IPV6_TCP, | |
626 | MLX5E_TT_IPV4_UDP, | |
627 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
628 | MLX5E_TT_IPV4_IPSEC_AH, |
629 | MLX5E_TT_IPV6_IPSEC_AH, | |
630 | MLX5E_TT_IPV4_IPSEC_ESP, | |
631 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
632 | MLX5E_TT_IPV4, |
633 | MLX5E_TT_IPV6, | |
634 | MLX5E_TT_ANY, | |
635 | MLX5E_NUM_TT, | |
1da36696 | 636 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
637 | }; |
638 | ||
7b3722fa GP |
639 | enum mlx5e_tunnel_types { |
640 | MLX5E_TT_IPV4_GRE, | |
641 | MLX5E_TT_IPV6_GRE, | |
642 | MLX5E_NUM_TUNNEL_TT, | |
643 | }; | |
644 | ||
acff797c | 645 | enum { |
e0f46eb9 | 646 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
647 | MLX5E_STATE_OPENED, |
648 | MLX5E_STATE_DESTROYING, | |
649 | }; | |
650 | ||
651 | struct mlx5e_vxlan_db { | |
652 | spinlock_t lock; /* protect vxlan table */ | |
653 | struct radix_tree_root tree; | |
654 | }; | |
655 | ||
33cfaaa8 | 656 | struct mlx5e_l2_rule { |
f62b8bb8 | 657 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 658 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
659 | }; |
660 | ||
acff797c MG |
661 | struct mlx5e_flow_table { |
662 | int num_groups; | |
663 | struct mlx5_flow_table *t; | |
664 | struct mlx5_flow_group **g; | |
665 | }; | |
666 | ||
33cfaaa8 | 667 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 668 | |
acff797c MG |
669 | struct mlx5e_tc_table { |
670 | struct mlx5_flow_table *t; | |
671 | ||
acff797c | 672 | struct rhashtable ht; |
11c9c548 OG |
673 | |
674 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); | |
5c65c564 | 675 | DECLARE_HASHTABLE(hairpin_tbl, 8); |
f62b8bb8 AV |
676 | }; |
677 | ||
acff797c MG |
678 | struct mlx5e_vlan_table { |
679 | struct mlx5e_flow_table ft; | |
03eda954 | 680 | DECLARE_BITMAP(active_cvlans, VLAN_N_VID); |
7d92d580 | 681 | DECLARE_BITMAP(active_svlans, VLAN_N_VID); |
2b52a283 | 682 | struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID]; |
7d92d580 | 683 | struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID]; |
74491de9 | 684 | struct mlx5_flow_handle *untagged_rule; |
8a271746 MHY |
685 | struct mlx5_flow_handle *any_cvlan_rule; |
686 | struct mlx5_flow_handle *any_svlan_rule; | |
2b52a283 | 687 | bool cvlan_filter_disabled; |
f62b8bb8 AV |
688 | }; |
689 | ||
33cfaaa8 MG |
690 | struct mlx5e_l2_table { |
691 | struct mlx5e_flow_table ft; | |
692 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
693 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
694 | struct mlx5e_l2_rule broadcast; | |
695 | struct mlx5e_l2_rule allmulti; | |
696 | struct mlx5e_l2_rule promisc; | |
697 | bool broadcast_enabled; | |
698 | bool allmulti_enabled; | |
699 | bool promisc_enabled; | |
700 | }; | |
701 | ||
702 | /* L3/L4 traffic type classifier */ | |
703 | struct mlx5e_ttc_table { | |
704 | struct mlx5e_flow_table ft; | |
74491de9 | 705 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
7b3722fa | 706 | struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT]; |
33cfaaa8 MG |
707 | }; |
708 | ||
18c908e4 MG |
709 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
710 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
711 | struct arfs_table { |
712 | struct mlx5e_flow_table ft; | |
74491de9 | 713 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 714 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
715 | }; |
716 | ||
717 | enum arfs_type { | |
718 | ARFS_IPV4_TCP, | |
719 | ARFS_IPV6_TCP, | |
720 | ARFS_IPV4_UDP, | |
721 | ARFS_IPV6_UDP, | |
722 | ARFS_NUM_TYPES, | |
723 | }; | |
724 | ||
725 | struct mlx5e_arfs_tables { | |
726 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
727 | /* Protect aRFS rules list */ |
728 | spinlock_t arfs_lock; | |
729 | struct list_head rules; | |
730 | int last_filter_id; | |
731 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
732 | }; |
733 | ||
734 | /* NIC prio FTS */ | |
735 | enum { | |
736 | MLX5E_VLAN_FT_LEVEL = 0, | |
737 | MLX5E_L2_FT_LEVEL, | |
738 | MLX5E_TTC_FT_LEVEL, | |
7b3722fa | 739 | MLX5E_INNER_TTC_FT_LEVEL, |
1cabe6b0 MG |
740 | MLX5E_ARFS_FT_LEVEL |
741 | }; | |
742 | ||
3f6d08d1 OG |
743 | enum { |
744 | MLX5E_TC_FT_LEVEL = 0, | |
745 | MLX5E_TC_TTC_FT_LEVEL, | |
746 | }; | |
747 | ||
6dc6071c MG |
748 | struct mlx5e_ethtool_table { |
749 | struct mlx5_flow_table *ft; | |
750 | int num_rules; | |
751 | }; | |
752 | ||
1174fce8 | 753 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
754 | #define ETHTOOL_NUM_L2_FTS 4 |
755 | ||
756 | struct mlx5e_ethtool_steering { | |
1174fce8 | 757 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
758 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
759 | struct list_head rules; | |
760 | int tot_num_rules; | |
761 | }; | |
762 | ||
acff797c MG |
763 | struct mlx5e_flow_steering { |
764 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 765 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
766 | struct mlx5e_tc_table tc; |
767 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
768 | struct mlx5e_l2_table l2; |
769 | struct mlx5e_ttc_table ttc; | |
7b3722fa | 770 | struct mlx5e_ttc_table inner_ttc; |
1cabe6b0 | 771 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
772 | }; |
773 | ||
398f3351 | 774 | struct mlx5e_rqt { |
1da36696 | 775 | u32 rqtn; |
398f3351 HHZ |
776 | bool enabled; |
777 | }; | |
778 | ||
779 | struct mlx5e_tir { | |
780 | u32 tirn; | |
781 | struct mlx5e_rqt rqt; | |
782 | struct list_head list; | |
1da36696 TT |
783 | }; |
784 | ||
acff797c MG |
785 | enum { |
786 | MLX5E_TC_PRIO = 0, | |
787 | MLX5E_NIC_PRIO | |
788 | }; | |
789 | ||
f62b8bb8 AV |
790 | struct mlx5e_priv { |
791 | /* priv data path fields - start */ | |
acc6c595 SM |
792 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
793 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
794 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
795 | struct mlx5e_dcbx_dp dcbx_dp; | |
796 | #endif | |
f62b8bb8 AV |
797 | /* priv data path fields - end */ |
798 | ||
79c48764 | 799 | u32 msglevel; |
f62b8bb8 AV |
800 | unsigned long state; |
801 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 802 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 803 | |
ff9c852f | 804 | struct mlx5e_channels channels; |
f62b8bb8 | 805 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 806 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 807 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 808 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 809 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
507f0c81 | 810 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
f62b8bb8 | 811 | |
acff797c | 812 | struct mlx5e_flow_steering fs; |
b3f63c3d | 813 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 814 | |
7bb29755 | 815 | struct workqueue_struct *wq; |
f62b8bb8 AV |
816 | struct work_struct update_carrier_work; |
817 | struct work_struct set_rx_mode_work; | |
3947ca18 | 818 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
819 | struct delayed_work update_stats_work; |
820 | ||
821 | struct mlx5_core_dev *mdev; | |
822 | struct net_device *netdev; | |
823 | struct mlx5e_stats stats; | |
05909bab EBE |
824 | struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS]; |
825 | u8 max_opened_tc; | |
7c39afb3 | 826 | struct hwtstamp_config tstamp; |
7cbaf9a3 MS |
827 | u16 q_counter; |
828 | u16 drop_rq_q_counter; | |
3a6a931d HN |
829 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
830 | struct mlx5e_dcbx dcbx; | |
831 | #endif | |
832 | ||
6bfd390b | 833 | const struct mlx5e_profile *profile; |
127ea380 | 834 | void *ppriv; |
547eede0 IT |
835 | #ifdef CONFIG_MLX5_EN_IPSEC |
836 | struct mlx5e_ipsec *ipsec; | |
837 | #endif | |
43585a41 IL |
838 | #ifdef CONFIG_MLX5_EN_TLS |
839 | struct mlx5e_tls *tls; | |
840 | #endif | |
f62b8bb8 AV |
841 | }; |
842 | ||
a43b25da SM |
843 | struct mlx5e_profile { |
844 | void (*init)(struct mlx5_core_dev *mdev, | |
845 | struct net_device *netdev, | |
846 | const struct mlx5e_profile *profile, void *ppriv); | |
847 | void (*cleanup)(struct mlx5e_priv *priv); | |
848 | int (*init_rx)(struct mlx5e_priv *priv); | |
849 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
850 | int (*init_tx)(struct mlx5e_priv *priv); | |
851 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
852 | void (*enable)(struct mlx5e_priv *priv); | |
853 | void (*disable)(struct mlx5e_priv *priv); | |
854 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 855 | void (*update_carrier)(struct mlx5e_priv *priv); |
a43b25da | 856 | int (*max_nch)(struct mlx5_core_dev *mdev); |
20fd0c19 SM |
857 | struct { |
858 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
859 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
860 | } rx_handlers; | |
2a5e7a13 HN |
861 | void (*netdev_registered_init)(struct mlx5e_priv *priv); |
862 | void (*netdev_registered_remove)(struct mlx5e_priv *priv); | |
a43b25da SM |
863 | int max_tc; |
864 | }; | |
865 | ||
665bc539 GP |
866 | void mlx5e_build_ptys2ethtool_map(void); |
867 | ||
f62b8bb8 AV |
868 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
869 | void *accel_priv, select_queue_fallback_t fallback); | |
870 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
bf239741 IL |
871 | netdev_tx_t mlx5e_sq_xmit(struct mlx5e_txqsq *sq, struct sk_buff *skb, |
872 | struct mlx5e_tx_wqe *wqe, u16 pi); | |
f62b8bb8 AV |
873 | |
874 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
875 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
876 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 877 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 878 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 879 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
880 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
881 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 882 | |
2ccb0a79 TT |
883 | bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev); |
884 | bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev, | |
885 | struct mlx5e_params *params); | |
886 | ||
4415a031 TT |
887 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
888 | bool recycle); | |
2f48af12 | 889 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 890 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 891 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
7cc6d77b | 892 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
893 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
894 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 | 895 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); |
619a8f2a TT |
896 | struct sk_buff * |
897 | mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
898 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
899 | struct sk_buff * | |
900 | mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, | |
901 | u16 cqe_bcnt, u32 head_offset, u32 page_idx); | |
069d1146 TT |
902 | struct sk_buff * |
903 | mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
904 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
905 | struct sk_buff * | |
906 | mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe, | |
907 | struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt); | |
f62b8bb8 | 908 | |
19386177 | 909 | void mlx5e_update_stats(struct mlx5e_priv *priv); |
f62b8bb8 | 910 | |
acff797c MG |
911 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
912 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 913 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 914 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
915 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
916 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
917 | u64 *buf); | |
f913a72a MG |
918 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
919 | int location); | |
920 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
921 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
922 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
923 | struct ethtool_rx_flow_spec *fs); | |
924 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
925 | int location); | |
926 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
927 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
928 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
929 | ||
1170fbd8 FD |
930 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
931 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 932 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 933 | |
f62b8bb8 AV |
934 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
935 | u16 vid); | |
936 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
937 | u16 vid); | |
2b52a283 GP |
938 | void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv); |
939 | void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv); | |
237f258c | 940 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); |
f62b8bb8 | 941 | |
a5f97fee SM |
942 | struct mlx5e_redirect_rqt_param { |
943 | bool is_rss; | |
944 | union { | |
945 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
946 | struct { | |
947 | u8 hfunc; | |
948 | struct mlx5e_channels *channels; | |
949 | } rss; /* RSS data */ | |
950 | }; | |
951 | }; | |
952 | ||
953 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
954 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
955 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
956 | enum mlx5e_traffic_types tt, | |
7b3722fa | 957 | void *tirc, bool inner); |
2d75b2bc | 958 | |
f62b8bb8 AV |
959 | int mlx5e_open_locked(struct net_device *netdev); |
960 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
961 | |
962 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
963 | struct mlx5e_channels *chs); | |
964 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
965 | |
966 | /* Function pointer to be used to modify WH settings while | |
967 | * switching channels | |
968 | */ | |
969 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 970 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
971 | struct mlx5e_channels *new_chs, |
972 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
973 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
974 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 975 | |
d4b6c488 | 976 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 977 | int num_channels); |
0088cbbc TG |
978 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
979 | u8 cq_period_mode); | |
9908aa29 TT |
980 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
981 | u8 cq_period_mode); | |
2ccb0a79 | 982 | void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params); |
696a97cf | 983 | void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev, |
2a0f561b | 984 | struct mlx5e_params *params); |
9908aa29 | 985 | |
7b3722fa GP |
986 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
987 | { | |
988 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
989 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
990 | } | |
991 | ||
bf239741 IL |
992 | static inline void mlx5e_sq_fetch_wqe(struct mlx5e_txqsq *sq, |
993 | struct mlx5e_tx_wqe **wqe, | |
994 | u16 *pi) | |
995 | { | |
ddf385e3 | 996 | struct mlx5_wq_cyc *wq = &sq->wq; |
bf239741 | 997 | |
ddf385e3 | 998 | *pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc); |
bf239741 IL |
999 | *wqe = mlx5_wq_cyc_get_wqe(wq, *pi); |
1000 | memset(*wqe, 0, sizeof(**wqe)); | |
1001 | } | |
1002 | ||
864b2d71 SM |
1003 | static inline |
1004 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 1005 | { |
ddf385e3 | 1006 | u16 pi = mlx5_wq_cyc_ctr2ix(wq, *pc); |
864b2d71 SM |
1007 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); |
1008 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
1009 | ||
1010 | memset(cseg, 0, sizeof(*cseg)); | |
1011 | ||
1012 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
1013 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
1014 | ||
1015 | (*pc)++; | |
1016 | ||
1017 | return wqe; | |
1018 | } | |
1019 | ||
1020 | static inline | |
1021 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
1022 | void __iomem *uar_map, | |
1023 | struct mlx5_wqe_ctrl_seg *ctrl) | |
1024 | { | |
1025 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
1026 | /* ensure wqe is visible to device before updating doorbell record */ |
1027 | dma_wmb(); | |
1028 | ||
864b2d71 | 1029 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
1030 | |
1031 | /* ensure doorbell record is visible to device before ringing the | |
1032 | * doorbell | |
1033 | */ | |
1034 | wmb(); | |
f62b8bb8 | 1035 | |
864b2d71 | 1036 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
1037 | } |
1038 | ||
1039 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
1040 | { | |
1041 | struct mlx5_core_cq *mcq; | |
1042 | ||
1043 | mcq = &cq->mcq; | |
5fe9dec0 | 1044 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
1045 | } |
1046 | ||
1047 | extern const struct ethtool_ops mlx5e_ethtool_ops; | |
08fb1dac SM |
1048 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
1049 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
1050 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1051 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1052 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1053 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1054 | #endif |
1055 | ||
1cabe6b0 MG |
1056 | #ifndef CONFIG_RFS_ACCEL |
1057 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
1058 | { | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
1063 | |
1064 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
1065 | { | |
9eb78923 | 1066 | return -EOPNOTSUPP; |
45bf454a MG |
1067 | } |
1068 | ||
1069 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
1070 | { | |
9eb78923 | 1071 | return -EOPNOTSUPP; |
45bf454a | 1072 | } |
1cabe6b0 MG |
1073 | #else |
1074 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
1075 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
1076 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
1077 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
1078 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
1079 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
1080 | #endif |
1081 | ||
724b2aa1 HHZ |
1082 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1083 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1084 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1085 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1086 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1087 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1088 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1089 | |
bc81b9d3 | 1090 | /* common netdev helpers */ |
8f493ffd SM |
1091 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1092 | ||
1093 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); | |
1094 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); | |
1095 | ||
cb67b832 | 1096 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1097 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1098 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1099 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1100 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1101 | ||
1ae1df3a OG |
1102 | struct ttc_params { |
1103 | struct mlx5_flow_table_attr ft_attr; | |
1104 | u32 any_tt_tirn; | |
1105 | u32 indir_tirn[MLX5E_NUM_INDIR_TIRS]; | |
1106 | struct mlx5e_ttc_table *inner_ttc; | |
1107 | }; | |
1108 | ||
1109 | void mlx5e_set_ttc_basic_params(struct mlx5e_priv *priv, struct ttc_params *ttc_params); | |
1110 | void mlx5e_set_ttc_ft_params(struct ttc_params *ttc_params); | |
1111 | void mlx5e_set_inner_ttc_ft_params(struct ttc_params *ttc_params); | |
1112 | ||
1113 | int mlx5e_create_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, | |
1114 | struct mlx5e_ttc_table *ttc); | |
1115 | void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv, | |
1116 | struct mlx5e_ttc_table *ttc); | |
bc81b9d3 | 1117 | |
1ae1df3a OG |
1118 | int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv, struct ttc_params *params, |
1119 | struct mlx5e_ttc_table *ttc); | |
1120 | void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv, | |
1121 | struct mlx5e_ttc_table *ttc); | |
458821c7 | 1122 | |
5426a0b2 SM |
1123 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1124 | u32 underlay_qpn, u32 *tisn); | |
1125 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1126 | ||
cb67b832 HHZ |
1127 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
1128 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1129 | int mlx5e_close(struct net_device *netdev); | |
1130 | int mlx5e_open(struct net_device *netdev); | |
1131 | void mlx5e_update_stats_work(struct work_struct *work); | |
cb67b832 | 1132 | |
3f6d08d1 OG |
1133 | int mlx5e_bits_invert(unsigned long a, int size); |
1134 | ||
250a42b6 AN |
1135 | typedef int (*change_hw_mtu_cb)(struct mlx5e_priv *priv); |
1136 | int mlx5e_change_mtu(struct net_device *netdev, int new_mtu, | |
1137 | change_hw_mtu_cb set_mtu_cb); | |
1138 | ||
076b0936 ES |
1139 | /* ethtool helpers */ |
1140 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1141 | struct ethtool_drvinfo *drvinfo); | |
1142 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1143 | uint32_t stringset, uint8_t *data); | |
1144 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1145 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1146 | struct ethtool_stats *stats, u64 *data); | |
1147 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1148 | struct ethtool_ringparam *param); | |
1149 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1150 | struct ethtool_ringparam *param); | |
1151 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1152 | struct ethtool_channels *ch); | |
1153 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1154 | struct ethtool_channels *ch); | |
1155 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1156 | struct ethtool_coalesce *coal); | |
1157 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1158 | struct ethtool_coalesce *coal); | |
3844b07e FD |
1159 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1160 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1161 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1162 | struct ethtool_flash *flash); | |
076b0936 | 1163 | |
2c3b5bee SM |
1164 | /* mlx5e generic netdev management API */ |
1165 | struct net_device* | |
1166 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
1167 | void *ppriv); | |
1168 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |
1169 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1170 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
1171 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
1172 | struct mlx5e_params *params, | |
472a1e44 | 1173 | u16 max_channels, u16 mtu); |
fbcb127e | 1174 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
9a317425 | 1175 | void mlx5e_rx_dim_work(struct work_struct *work); |
cbce4f44 | 1176 | void mlx5e_tx_dim_work(struct work_struct *work); |
1afff42c | 1177 | #endif /* __MLX5_EN_H__ */ |