Commit | Line | Data |
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f62b8bb8 AV |
1 | /* |
2 | * Copyright (c) 2015, Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #include <linux/if_vlan.h> | |
34 | #include <linux/etherdevice.h> | |
ef9814de EBE |
35 | #include <linux/timecounter.h> |
36 | #include <linux/net_tstamp.h> | |
3d8c38af | 37 | #include <linux/ptp_clock_kernel.h> |
f62b8bb8 AV |
38 | #include <linux/mlx5/driver.h> |
39 | #include <linux/mlx5/qp.h> | |
40 | #include <linux/mlx5/cq.h> | |
ada68c31 | 41 | #include <linux/mlx5/port.h> |
d18a9470 | 42 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 43 | #include <linux/mlx5/transobj.h> |
f62b8bb8 | 44 | #include "wq.h" |
f62b8bb8 AV |
45 | #include "mlx5_core.h" |
46 | ||
47 | #define MLX5E_MAX_NUM_TC 8 | |
48 | ||
e842b100 | 49 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
50 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
51 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
52 | ||
e842b100 | 53 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
54 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
55 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
56 | ||
d9a40271 | 57 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
f62b8bb8 AV |
58 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
59 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 | |
60 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
61 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 | |
62 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
f62b8bb8 | 63 | |
936896e9 AS |
64 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
65 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
66 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) | |
f62b8bb8 AV |
67 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
68 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
88a85f99 | 69 | #define MLX5E_SQ_BF_BUDGET 16 |
f62b8bb8 | 70 | |
86d722ad MG |
71 | #define MLX5E_NUM_MAIN_GROUPS 9 |
72 | ||
08fb1dac SM |
73 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
74 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
75 | #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */ | |
76 | #endif | |
77 | ||
f62b8bb8 AV |
78 | static const char vport_strings[][ETH_GSTRING_LEN] = { |
79 | /* vport statistics */ | |
80 | "rx_packets", | |
81 | "rx_bytes", | |
82 | "tx_packets", | |
83 | "tx_bytes", | |
84 | "rx_error_packets", | |
85 | "rx_error_bytes", | |
86 | "tx_error_packets", | |
87 | "tx_error_bytes", | |
88 | "rx_unicast_packets", | |
89 | "rx_unicast_bytes", | |
90 | "tx_unicast_packets", | |
91 | "tx_unicast_bytes", | |
92 | "rx_multicast_packets", | |
93 | "rx_multicast_bytes", | |
94 | "tx_multicast_packets", | |
95 | "tx_multicast_bytes", | |
96 | "rx_broadcast_packets", | |
97 | "rx_broadcast_bytes", | |
98 | "tx_broadcast_packets", | |
99 | "tx_broadcast_bytes", | |
100 | ||
101 | /* SW counters */ | |
102 | "tso_packets", | |
103 | "tso_bytes", | |
104 | "lro_packets", | |
105 | "lro_bytes", | |
106 | "rx_csum_good", | |
107 | "rx_csum_none", | |
bbceefce | 108 | "rx_csum_sw", |
f62b8bb8 AV |
109 | "tx_csum_offload", |
110 | "tx_queue_stopped", | |
111 | "tx_queue_wake", | |
112 | "tx_queue_dropped", | |
113 | "rx_wqe_err", | |
114 | }; | |
115 | ||
116 | struct mlx5e_vport_stats { | |
117 | /* HW counters */ | |
118 | u64 rx_packets; | |
119 | u64 rx_bytes; | |
120 | u64 tx_packets; | |
121 | u64 tx_bytes; | |
122 | u64 rx_error_packets; | |
123 | u64 rx_error_bytes; | |
124 | u64 tx_error_packets; | |
125 | u64 tx_error_bytes; | |
126 | u64 rx_unicast_packets; | |
127 | u64 rx_unicast_bytes; | |
128 | u64 tx_unicast_packets; | |
129 | u64 tx_unicast_bytes; | |
130 | u64 rx_multicast_packets; | |
131 | u64 rx_multicast_bytes; | |
132 | u64 tx_multicast_packets; | |
133 | u64 tx_multicast_bytes; | |
134 | u64 rx_broadcast_packets; | |
135 | u64 rx_broadcast_bytes; | |
136 | u64 tx_broadcast_packets; | |
137 | u64 tx_broadcast_bytes; | |
138 | ||
139 | /* SW counters */ | |
140 | u64 tso_packets; | |
141 | u64 tso_bytes; | |
142 | u64 lro_packets; | |
143 | u64 lro_bytes; | |
144 | u64 rx_csum_good; | |
145 | u64 rx_csum_none; | |
bbceefce | 146 | u64 rx_csum_sw; |
f62b8bb8 AV |
147 | u64 tx_csum_offload; |
148 | u64 tx_queue_stopped; | |
149 | u64 tx_queue_wake; | |
150 | u64 tx_queue_dropped; | |
151 | u64 rx_wqe_err; | |
152 | ||
bbceefce | 153 | #define NUM_VPORT_COUNTERS 32 |
f62b8bb8 AV |
154 | }; |
155 | ||
efea389d GP |
156 | static const char pport_strings[][ETH_GSTRING_LEN] = { |
157 | /* IEEE802.3 counters */ | |
158 | "frames_tx", | |
159 | "frames_rx", | |
160 | "check_seq_err", | |
161 | "alignment_err", | |
162 | "octets_tx", | |
163 | "octets_received", | |
164 | "multicast_xmitted", | |
165 | "broadcast_xmitted", | |
166 | "multicast_rx", | |
167 | "broadcast_rx", | |
168 | "in_range_len_errors", | |
169 | "out_of_range_len", | |
170 | "too_long_errors", | |
171 | "symbol_err", | |
172 | "mac_control_tx", | |
173 | "mac_control_rx", | |
174 | "unsupported_op_rx", | |
175 | "pause_ctrl_rx", | |
176 | "pause_ctrl_tx", | |
177 | ||
178 | /* RFC2863 counters */ | |
179 | "in_octets", | |
180 | "in_ucast_pkts", | |
181 | "in_discards", | |
182 | "in_errors", | |
183 | "in_unknown_protos", | |
184 | "out_octets", | |
185 | "out_ucast_pkts", | |
186 | "out_discards", | |
187 | "out_errors", | |
188 | "in_multicast_pkts", | |
189 | "in_broadcast_pkts", | |
190 | "out_multicast_pkts", | |
191 | "out_broadcast_pkts", | |
192 | ||
193 | /* RFC2819 counters */ | |
194 | "drop_events", | |
195 | "octets", | |
196 | "pkts", | |
197 | "broadcast_pkts", | |
198 | "multicast_pkts", | |
199 | "crc_align_errors", | |
200 | "undersize_pkts", | |
201 | "oversize_pkts", | |
202 | "fragments", | |
203 | "jabbers", | |
204 | "collisions", | |
205 | "p64octets", | |
206 | "p65to127octets", | |
207 | "p128to255octets", | |
208 | "p256to511octets", | |
209 | "p512to1023octets", | |
210 | "p1024to1518octets", | |
211 | "p1519to2047octets", | |
212 | "p2048to4095octets", | |
213 | "p4096to8191octets", | |
214 | "p8192to10239octets", | |
215 | }; | |
216 | ||
217 | #define NUM_IEEE_802_3_COUNTERS 19 | |
218 | #define NUM_RFC_2863_COUNTERS 13 | |
219 | #define NUM_RFC_2819_COUNTERS 21 | |
220 | #define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \ | |
221 | NUM_RFC_2863_COUNTERS + \ | |
222 | NUM_RFC_2819_COUNTERS) | |
223 | ||
224 | struct mlx5e_pport_stats { | |
225 | __be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS]; | |
226 | __be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS]; | |
227 | __be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS]; | |
228 | }; | |
229 | ||
f62b8bb8 AV |
230 | static const char rq_stats_strings[][ETH_GSTRING_LEN] = { |
231 | "packets", | |
232 | "csum_none", | |
bbceefce | 233 | "csum_sw", |
f62b8bb8 AV |
234 | "lro_packets", |
235 | "lro_bytes", | |
236 | "wqe_err" | |
237 | }; | |
238 | ||
239 | struct mlx5e_rq_stats { | |
240 | u64 packets; | |
241 | u64 csum_none; | |
bbceefce | 242 | u64 csum_sw; |
f62b8bb8 AV |
243 | u64 lro_packets; |
244 | u64 lro_bytes; | |
245 | u64 wqe_err; | |
bbceefce | 246 | #define NUM_RQ_STATS 6 |
f62b8bb8 AV |
247 | }; |
248 | ||
249 | static const char sq_stats_strings[][ETH_GSTRING_LEN] = { | |
250 | "packets", | |
251 | "tso_packets", | |
252 | "tso_bytes", | |
253 | "csum_offload_none", | |
254 | "stopped", | |
255 | "wake", | |
256 | "dropped", | |
257 | "nop" | |
258 | }; | |
259 | ||
260 | struct mlx5e_sq_stats { | |
261 | u64 packets; | |
262 | u64 tso_packets; | |
263 | u64 tso_bytes; | |
264 | u64 csum_offload_none; | |
265 | u64 stopped; | |
266 | u64 wake; | |
267 | u64 dropped; | |
268 | u64 nop; | |
269 | #define NUM_SQ_STATS 8 | |
270 | }; | |
271 | ||
272 | struct mlx5e_stats { | |
273 | struct mlx5e_vport_stats vport; | |
efea389d | 274 | struct mlx5e_pport_stats pport; |
f62b8bb8 AV |
275 | }; |
276 | ||
277 | struct mlx5e_params { | |
278 | u8 log_sq_size; | |
279 | u8 log_rq_size; | |
280 | u16 num_channels; | |
f62b8bb8 AV |
281 | u8 num_tc; |
282 | u16 rx_cq_moderation_usec; | |
283 | u16 rx_cq_moderation_pkts; | |
284 | u16 tx_cq_moderation_usec; | |
285 | u16 tx_cq_moderation_pkts; | |
286 | u16 min_rx_wqes; | |
f62b8bb8 AV |
287 | bool lro_en; |
288 | u32 lro_wqe_sz; | |
58d52291 | 289 | u16 tx_max_inline; |
2d75b2bc AS |
290 | u8 rss_hfunc; |
291 | u8 toeplitz_hash_key[40]; | |
292 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
08fb1dac SM |
293 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
294 | struct ieee_ets ets; | |
295 | #endif | |
f62b8bb8 AV |
296 | }; |
297 | ||
ef9814de EBE |
298 | struct mlx5e_tstamp { |
299 | rwlock_t lock; | |
300 | struct cyclecounter cycles; | |
301 | struct timecounter clock; | |
302 | struct hwtstamp_config hwtstamp_config; | |
303 | u32 nominal_c_mult; | |
304 | unsigned long overflow_period; | |
305 | struct delayed_work overflow_work; | |
306 | struct mlx5_core_dev *mdev; | |
3d8c38af EBE |
307 | struct ptp_clock *ptp; |
308 | struct ptp_clock_info ptp_info; | |
ef9814de EBE |
309 | }; |
310 | ||
f62b8bb8 AV |
311 | enum { |
312 | MLX5E_RQ_STATE_POST_WQES_ENABLE, | |
313 | }; | |
314 | ||
315 | enum cq_flags { | |
316 | MLX5E_CQ_HAS_CQES = 1, | |
317 | }; | |
318 | ||
319 | struct mlx5e_cq { | |
320 | /* data path - accessed per cqe */ | |
321 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
322 | unsigned long flags; |
323 | ||
324 | /* data path - accessed per napi poll */ | |
325 | struct napi_struct *napi; | |
326 | struct mlx5_core_cq mcq; | |
327 | struct mlx5e_channel *channel; | |
50cfa25a | 328 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
329 | |
330 | /* control */ | |
331 | struct mlx5_wq_ctrl wq_ctrl; | |
332 | } ____cacheline_aligned_in_smp; | |
333 | ||
334 | struct mlx5e_rq { | |
335 | /* data path */ | |
336 | struct mlx5_wq_ll wq; | |
337 | u32 wqe_sz; | |
338 | struct sk_buff **skb; | |
339 | ||
340 | struct device *pdev; | |
341 | struct net_device *netdev; | |
ef9814de | 342 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
343 | struct mlx5e_rq_stats stats; |
344 | struct mlx5e_cq cq; | |
345 | ||
346 | unsigned long state; | |
347 | int ix; | |
348 | ||
349 | /* control */ | |
350 | struct mlx5_wq_ctrl wq_ctrl; | |
351 | u32 rqn; | |
352 | struct mlx5e_channel *channel; | |
50cfa25a | 353 | struct mlx5e_priv *priv; |
f62b8bb8 AV |
354 | } ____cacheline_aligned_in_smp; |
355 | ||
34802a42 | 356 | struct mlx5e_tx_wqe_info { |
f62b8bb8 AV |
357 | u32 num_bytes; |
358 | u8 num_wqebbs; | |
359 | u8 num_dma; | |
360 | }; | |
361 | ||
d4e28cbd AS |
362 | enum mlx5e_dma_map_type { |
363 | MLX5E_DMA_MAP_SINGLE, | |
364 | MLX5E_DMA_MAP_PAGE | |
365 | }; | |
366 | ||
f62b8bb8 | 367 | struct mlx5e_sq_dma { |
d4e28cbd AS |
368 | dma_addr_t addr; |
369 | u32 size; | |
370 | enum mlx5e_dma_map_type type; | |
f62b8bb8 AV |
371 | }; |
372 | ||
373 | enum { | |
374 | MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, | |
375 | }; | |
376 | ||
377 | struct mlx5e_sq { | |
378 | /* data path */ | |
379 | ||
380 | /* dirtied @completion */ | |
381 | u16 cc; | |
382 | u32 dma_fifo_cc; | |
383 | ||
384 | /* dirtied @xmit */ | |
385 | u16 pc ____cacheline_aligned_in_smp; | |
386 | u32 dma_fifo_pc; | |
88a85f99 AS |
387 | u16 bf_offset; |
388 | u16 prev_cc; | |
389 | u8 bf_budget; | |
f62b8bb8 AV |
390 | struct mlx5e_sq_stats stats; |
391 | ||
392 | struct mlx5e_cq cq; | |
393 | ||
394 | /* pointers to per packet info: write@xmit, read@completion */ | |
395 | struct sk_buff **skb; | |
396 | struct mlx5e_sq_dma *dma_fifo; | |
34802a42 | 397 | struct mlx5e_tx_wqe_info *wqe_info; |
f62b8bb8 AV |
398 | |
399 | /* read only */ | |
400 | struct mlx5_wq_cyc wq; | |
401 | u32 dma_fifo_mask; | |
402 | void __iomem *uar_map; | |
88a85f99 | 403 | void __iomem *uar_bf_map; |
f62b8bb8 AV |
404 | struct netdev_queue *txq; |
405 | u32 sqn; | |
88a85f99 | 406 | u16 bf_buf_size; |
12be4b21 SM |
407 | u16 max_inline; |
408 | u16 edge; | |
f62b8bb8 | 409 | struct device *pdev; |
ef9814de | 410 | struct mlx5e_tstamp *tstamp; |
f62b8bb8 AV |
411 | __be32 mkey_be; |
412 | unsigned long state; | |
413 | ||
414 | /* control path */ | |
415 | struct mlx5_wq_ctrl wq_ctrl; | |
416 | struct mlx5_uar uar; | |
417 | struct mlx5e_channel *channel; | |
418 | int tc; | |
419 | } ____cacheline_aligned_in_smp; | |
420 | ||
421 | static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n) | |
422 | { | |
423 | return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) || | |
424 | (sq->cc == sq->pc)); | |
425 | } | |
426 | ||
427 | enum channel_flags { | |
428 | MLX5E_CHANNEL_NAPI_SCHED = 1, | |
429 | }; | |
430 | ||
431 | struct mlx5e_channel { | |
432 | /* data path */ | |
433 | struct mlx5e_rq rq; | |
434 | struct mlx5e_sq sq[MLX5E_MAX_NUM_TC]; | |
435 | struct napi_struct napi; | |
436 | struct device *pdev; | |
437 | struct net_device *netdev; | |
438 | __be32 mkey_be; | |
439 | u8 num_tc; | |
440 | unsigned long flags; | |
441 | ||
442 | /* control */ | |
443 | struct mlx5e_priv *priv; | |
444 | int ix; | |
445 | int cpu; | |
446 | }; | |
447 | ||
448 | enum mlx5e_traffic_types { | |
5a6f8aef AS |
449 | MLX5E_TT_IPV4_TCP, |
450 | MLX5E_TT_IPV6_TCP, | |
451 | MLX5E_TT_IPV4_UDP, | |
452 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
453 | MLX5E_TT_IPV4_IPSEC_AH, |
454 | MLX5E_TT_IPV6_IPSEC_AH, | |
455 | MLX5E_TT_IPV4_IPSEC_ESP, | |
456 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
457 | MLX5E_TT_IPV4, |
458 | MLX5E_TT_IPV6, | |
459 | MLX5E_TT_ANY, | |
460 | MLX5E_NUM_TT, | |
f62b8bb8 AV |
461 | }; |
462 | ||
4cbeaff5 AS |
463 | enum mlx5e_rqt_ix { |
464 | MLX5E_INDIRECTION_RQT, | |
465 | MLX5E_SINGLE_RQ_RQT, | |
466 | MLX5E_NUM_RQT, | |
f62b8bb8 AV |
467 | }; |
468 | ||
469 | struct mlx5e_eth_addr_info { | |
470 | u8 addr[ETH_ALEN + 2]; | |
471 | u32 tt_vec; | |
86d722ad | 472 | struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT]; |
f62b8bb8 AV |
473 | }; |
474 | ||
475 | #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE) | |
476 | ||
477 | struct mlx5e_eth_addr_db { | |
478 | struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
479 | struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE]; | |
480 | struct mlx5e_eth_addr_info broadcast; | |
481 | struct mlx5e_eth_addr_info allmulti; | |
482 | struct mlx5e_eth_addr_info promisc; | |
483 | bool broadcast_enabled; | |
484 | bool allmulti_enabled; | |
485 | bool promisc_enabled; | |
486 | }; | |
487 | ||
488 | enum { | |
489 | MLX5E_STATE_ASYNC_EVENTS_ENABLE, | |
490 | MLX5E_STATE_OPENED, | |
9b37b07f | 491 | MLX5E_STATE_DESTROYING, |
f62b8bb8 AV |
492 | }; |
493 | ||
494 | struct mlx5e_vlan_db { | |
aad9e6e4 | 495 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
86d722ad MG |
496 | struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID]; |
497 | struct mlx5_flow_rule *untagged_rule; | |
498 | struct mlx5_flow_rule *any_vlan_rule; | |
f62b8bb8 AV |
499 | bool filter_disabled; |
500 | }; | |
501 | ||
502 | struct mlx5e_flow_table { | |
86d722ad MG |
503 | int num_groups; |
504 | struct mlx5_flow_table *t; | |
505 | struct mlx5_flow_group **g; | |
506 | }; | |
507 | ||
508 | struct mlx5e_flow_tables { | |
509 | struct mlx5_flow_namespace *ns; | |
510 | struct mlx5e_flow_table vlan; | |
511 | struct mlx5e_flow_table main; | |
f62b8bb8 AV |
512 | }; |
513 | ||
514 | struct mlx5e_priv { | |
515 | /* priv data path fields - start */ | |
03289b88 | 516 | struct mlx5e_sq **txq_to_sq_map; |
5283af89 | 517 | int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; |
f62b8bb8 AV |
518 | /* priv data path fields - end */ |
519 | ||
520 | unsigned long state; | |
521 | struct mutex state_lock; /* Protects Interface state */ | |
522 | struct mlx5_uar cq_uar; | |
523 | u32 pdn; | |
3191e05f | 524 | u32 tdn; |
f62b8bb8 | 525 | struct mlx5_core_mr mr; |
50cfa25a | 526 | struct mlx5e_rq drop_rq; |
f62b8bb8 AV |
527 | |
528 | struct mlx5e_channel **channel; | |
529 | u32 tisn[MLX5E_MAX_NUM_TC]; | |
4cbeaff5 | 530 | u32 rqtn[MLX5E_NUM_RQT]; |
f62b8bb8 AV |
531 | u32 tirn[MLX5E_NUM_TT]; |
532 | ||
86d722ad | 533 | struct mlx5e_flow_tables fts; |
f62b8bb8 AV |
534 | struct mlx5e_eth_addr_db eth_addr; |
535 | struct mlx5e_vlan_db vlan; | |
536 | ||
537 | struct mlx5e_params params; | |
538 | spinlock_t async_events_spinlock; /* sync hw events */ | |
539 | struct work_struct update_carrier_work; | |
540 | struct work_struct set_rx_mode_work; | |
541 | struct delayed_work update_stats_work; | |
542 | ||
543 | struct mlx5_core_dev *mdev; | |
544 | struct net_device *netdev; | |
545 | struct mlx5e_stats stats; | |
ef9814de | 546 | struct mlx5e_tstamp tstamp; |
f62b8bb8 AV |
547 | }; |
548 | ||
549 | #define MLX5E_NET_IP_ALIGN 2 | |
550 | ||
551 | struct mlx5e_tx_wqe { | |
552 | struct mlx5_wqe_ctrl_seg ctrl; | |
553 | struct mlx5_wqe_eth_seg eth; | |
554 | }; | |
555 | ||
556 | struct mlx5e_rx_wqe { | |
557 | struct mlx5_wqe_srq_next_seg next; | |
558 | struct mlx5_wqe_data_seg data; | |
559 | }; | |
560 | ||
561 | enum mlx5e_link_mode { | |
562 | MLX5E_1000BASE_CX_SGMII = 0, | |
563 | MLX5E_1000BASE_KX = 1, | |
564 | MLX5E_10GBASE_CX4 = 2, | |
565 | MLX5E_10GBASE_KX4 = 3, | |
566 | MLX5E_10GBASE_KR = 4, | |
567 | MLX5E_20GBASE_KR2 = 5, | |
568 | MLX5E_40GBASE_CR4 = 6, | |
569 | MLX5E_40GBASE_KR4 = 7, | |
570 | MLX5E_56GBASE_R4 = 8, | |
571 | MLX5E_10GBASE_CR = 12, | |
572 | MLX5E_10GBASE_SR = 13, | |
573 | MLX5E_10GBASE_ER = 14, | |
574 | MLX5E_40GBASE_SR4 = 15, | |
575 | MLX5E_40GBASE_LR4 = 16, | |
576 | MLX5E_100GBASE_CR4 = 20, | |
577 | MLX5E_100GBASE_SR4 = 21, | |
578 | MLX5E_100GBASE_KR4 = 22, | |
579 | MLX5E_100GBASE_LR4 = 23, | |
580 | MLX5E_100BASE_TX = 24, | |
581 | MLX5E_100BASE_T = 25, | |
582 | MLX5E_10GBASE_T = 26, | |
583 | MLX5E_25GBASE_CR = 27, | |
584 | MLX5E_25GBASE_KR = 28, | |
585 | MLX5E_25GBASE_SR = 29, | |
586 | MLX5E_50GBASE_CR2 = 30, | |
587 | MLX5E_50GBASE_KR2 = 31, | |
588 | MLX5E_LINK_MODES_NUMBER, | |
589 | }; | |
590 | ||
591 | #define MLX5E_PROT_MASK(link_mode) (1 << link_mode) | |
592 | ||
12be4b21 | 593 | void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw); |
f62b8bb8 AV |
594 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
595 | void *accel_priv, select_queue_fallback_t fallback); | |
596 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
597 | |
598 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
599 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
600 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
601 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq); | |
44fb6fbb | 602 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
f62b8bb8 AV |
603 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
604 | struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq); | |
605 | ||
606 | void mlx5e_update_stats(struct mlx5e_priv *priv); | |
607 | ||
40ab6a6e AS |
608 | int mlx5e_create_flow_tables(struct mlx5e_priv *priv); |
609 | void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv); | |
f62b8bb8 | 610 | void mlx5e_init_eth_addr(struct mlx5e_priv *priv); |
f62b8bb8 AV |
611 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
612 | ||
ef9814de EBE |
613 | void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp, |
614 | struct skb_shared_hwtstamps *hwts); | |
615 | void mlx5e_timestamp_init(struct mlx5e_priv *priv); | |
616 | void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv); | |
617 | int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr); | |
618 | int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr); | |
619 | ||
f62b8bb8 AV |
620 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
621 | u16 vid); | |
622 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
623 | u16 vid); | |
624 | void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv); | |
625 | void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv); | |
f62b8bb8 | 626 | |
2d75b2bc AS |
627 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix); |
628 | ||
f62b8bb8 AV |
629 | int mlx5e_open_locked(struct net_device *netdev); |
630 | int mlx5e_close_locked(struct net_device *netdev); | |
f62b8bb8 AV |
631 | |
632 | static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq, | |
88a85f99 | 633 | struct mlx5e_tx_wqe *wqe, int bf_sz) |
f62b8bb8 | 634 | { |
88a85f99 AS |
635 | u16 ofst = MLX5_BF_OFFSET + sq->bf_offset; |
636 | ||
f62b8bb8 AV |
637 | /* ensure wqe is visible to device before updating doorbell record */ |
638 | dma_wmb(); | |
639 | ||
640 | *sq->wq.db = cpu_to_be32(sq->pc); | |
641 | ||
642 | /* ensure doorbell record is visible to device before ringing the | |
643 | * doorbell | |
644 | */ | |
645 | wmb(); | |
646 | ||
88a85f99 AS |
647 | if (bf_sz) { |
648 | __iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz); | |
649 | ||
650 | /* flush the write-combining mapped buffer */ | |
651 | wmb(); | |
652 | ||
653 | } else { | |
654 | mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL); | |
655 | } | |
f62b8bb8 AV |
656 | |
657 | sq->bf_offset ^= sq->bf_buf_size; | |
658 | } | |
659 | ||
660 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
661 | { | |
662 | struct mlx5_core_cq *mcq; | |
663 | ||
664 | mcq = &cq->mcq; | |
665 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc); | |
666 | } | |
667 | ||
3435ab59 AS |
668 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
669 | { | |
670 | return min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
671 | MLX5E_MAX_NUM_CHANNELS); | |
672 | } | |
673 | ||
f62b8bb8 | 674 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
675 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
676 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
677 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
678 | #endif | |
679 | ||
58d52291 | 680 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |