Commit | Line | Data |
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f62b8bb8 | 1 | /* |
1afff42c | 2 | * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved. |
f62b8bb8 AV |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
1afff42c MF |
32 | #ifndef __MLX5_EN_H__ |
33 | #define __MLX5_EN_H__ | |
f62b8bb8 AV |
34 | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/etherdevice.h> | |
ef9814de EBE |
37 | #include <linux/timecounter.h> |
38 | #include <linux/net_tstamp.h> | |
3d8c38af | 39 | #include <linux/ptp_clock_kernel.h> |
48935bbb | 40 | #include <linux/crash_dump.h> |
f62b8bb8 AV |
41 | #include <linux/mlx5/driver.h> |
42 | #include <linux/mlx5/qp.h> | |
43 | #include <linux/mlx5/cq.h> | |
ada68c31 | 44 | #include <linux/mlx5/port.h> |
d18a9470 | 45 | #include <linux/mlx5/vport.h> |
8d7f9ecb | 46 | #include <linux/mlx5/transobj.h> |
e8f887ac | 47 | #include <linux/rhashtable.h> |
cb67b832 | 48 | #include <net/switchdev.h> |
f62b8bb8 | 49 | #include "wq.h" |
f62b8bb8 | 50 | #include "mlx5_core.h" |
9218b44d | 51 | #include "en_stats.h" |
f62b8bb8 | 52 | |
1cabe6b0 MG |
53 | #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) |
54 | ||
c139dbfd ES |
55 | #define MLX5E_ETH_HARD_MTU (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
56 | ||
57 | #define MLX5E_HW2SW_MTU(priv, hwmtu) ((hwmtu) - ((priv)->hard_mtu)) | |
58 | #define MLX5E_SW2HW_MTU(priv, swmtu) ((swmtu) + ((priv)->hard_mtu)) | |
d8bec2b2 | 59 | |
2a5e7a13 | 60 | #define MLX5E_MAX_DSCP 64 |
f62b8bb8 AV |
61 | #define MLX5E_MAX_NUM_TC 8 |
62 | ||
e842b100 | 63 | #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6 |
f62b8bb8 AV |
64 | #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa |
65 | #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd | |
66 | ||
e842b100 | 67 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1 |
f62b8bb8 AV |
68 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa |
69 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd | |
70 | ||
d1c61e6d | 71 | #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x2 |
7e426671 | 72 | #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x3 |
461017cb TT |
73 | #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6 |
74 | ||
1bfecfca | 75 | #define MLX5_RX_HEADROOM NET_SKB_PAD |
78aedd32 TT |
76 | #define MLX5_SKB_FRAG_SZ(len) (SKB_DATA_ALIGN(len) + \ |
77 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) | |
1bfecfca | 78 | |
f32f5bd2 DJ |
79 | #define MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev) \ |
80 | (6 + MLX5_CAP_GEN(mdev, cache_line_128byte)) /* HW restriction */ | |
81 | #define MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, req) \ | |
82 | max_t(u32, MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(mdev), req) | |
83 | #define MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 6) | |
84 | #define MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(mdev) MLX5_MPWRQ_LOG_STRIDE_SZ(mdev, 8) | |
85 | ||
7e426671 | 86 | #define MLX5_MPWRQ_LOG_WQE_SZ 18 |
461017cb TT |
87 | #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \ |
88 | MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0) | |
89 | #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER) | |
90 | #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \ | |
91 | MLX5_MPWRQ_WQE_PAGE_ORDER) | |
fe4c988b SM |
92 | |
93 | #define MLX5_MTT_OCTW(npages) (ALIGN(npages, 8) / 2) | |
ec8b9981 TT |
94 | #define MLX5E_REQUIRED_MTTS(wqes) \ |
95 | (wqes * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8)) | |
96 | #define MLX5E_VALID_NUM_MTTS(num_mtts) (MLX5_MTT_OCTW(num_mtts) - 1 <= U16_MAX) | |
fe4c988b | 97 | |
bc77b240 | 98 | #define MLX5_UMR_ALIGN (2048) |
cbad8cdd | 99 | #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (256) |
461017cb | 100 | |
d9a40271 | 101 | #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024) |
2b029556 SM |
102 | #define MLX5E_DEFAULT_LRO_TIMEOUT 32 |
103 | #define MLX5E_LRO_TIMEOUT_ARR_SIZE 4 | |
104 | ||
f62b8bb8 | 105 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10 |
9908aa29 | 106 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3 |
f62b8bb8 AV |
107 | #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20 |
108 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10 | |
0088cbbc | 109 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE 0x10 |
f62b8bb8 AV |
110 | #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20 |
111 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80 | |
461017cb | 112 | #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2 |
f62b8bb8 | 113 | |
936896e9 AS |
114 | #define MLX5E_LOG_INDIR_RQT_SIZE 0x7 |
115 | #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE) | |
b4e029da | 116 | #define MLX5E_MIN_NUM_CHANNELS 0x1 |
936896e9 | 117 | #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1) |
507f0c81 | 118 | #define MLX5E_MAX_NUM_SQS (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC) |
f62b8bb8 AV |
119 | #define MLX5E_TX_CQ_POLL_BUDGET 128 |
120 | #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */ | |
121 | ||
f10b7cc7 SM |
122 | #define MLX5E_ICOSQ_MAX_WQEBBS \ |
123 | (DIV_ROUND_UP(sizeof(struct mlx5e_umr_wqe), MLX5_SEND_WQE_BB)) | |
124 | ||
b5503b99 | 125 | #define MLX5E_XDP_MIN_INLINE (ETH_HLEN + VLAN_HLEN) |
b5503b99 | 126 | #define MLX5E_XDP_TX_DS_COUNT \ |
b70149dd | 127 | ((sizeof(struct mlx5e_tx_wqe) / MLX5_SEND_WQE_DS) + 1 /* SG DS */) |
b5503b99 | 128 | |
86d722ad | 129 | #define MLX5E_NUM_MAIN_GROUPS 9 |
2f48af12 | 130 | |
79c48764 GP |
131 | #define MLX5E_MSG_LEVEL NETIF_MSG_LINK |
132 | ||
133 | #define mlx5e_dbg(mlevel, priv, format, ...) \ | |
134 | do { \ | |
135 | if (NETIF_MSG_##mlevel & (priv)->msglevel) \ | |
136 | netdev_warn(priv->netdev, format, \ | |
137 | ##__VA_ARGS__); \ | |
138 | } while (0) | |
139 | ||
140 | ||
461017cb TT |
141 | static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size) |
142 | { | |
143 | switch (wq_type) { | |
144 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
145 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW, | |
146 | wq_size / 2); | |
147 | default: | |
148 | return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES, | |
149 | wq_size / 2); | |
150 | } | |
151 | } | |
152 | ||
153 | static inline int mlx5_min_log_rq_size(int wq_type) | |
154 | { | |
155 | switch (wq_type) { | |
156 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
157 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW; | |
158 | default: | |
159 | return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE; | |
160 | } | |
161 | } | |
162 | ||
163 | static inline int mlx5_max_log_rq_size(int wq_type) | |
164 | { | |
165 | switch (wq_type) { | |
166 | case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ: | |
167 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW; | |
168 | default: | |
169 | return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE; | |
170 | } | |
171 | } | |
172 | ||
48935bbb SM |
173 | static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev) |
174 | { | |
175 | return is_kdump_kernel() ? | |
176 | MLX5E_MIN_NUM_CHANNELS : | |
177 | min_t(int, mdev->priv.eq_table.num_comp_vectors, | |
178 | MLX5E_MAX_NUM_CHANNELS); | |
179 | } | |
180 | ||
2f48af12 TT |
181 | struct mlx5e_tx_wqe { |
182 | struct mlx5_wqe_ctrl_seg ctrl; | |
183 | struct mlx5_wqe_eth_seg eth; | |
184 | }; | |
185 | ||
186 | struct mlx5e_rx_wqe { | |
187 | struct mlx5_wqe_srq_next_seg next; | |
188 | struct mlx5_wqe_data_seg data; | |
189 | }; | |
86d722ad | 190 | |
bc77b240 TT |
191 | struct mlx5e_umr_wqe { |
192 | struct mlx5_wqe_ctrl_seg ctrl; | |
193 | struct mlx5_wqe_umr_ctrl_seg uctrl; | |
194 | struct mlx5_mkey_seg mkc; | |
195 | struct mlx5_wqe_data_seg data; | |
196 | }; | |
197 | ||
d605d668 KH |
198 | extern const char mlx5e_self_tests[][ETH_GSTRING_LEN]; |
199 | ||
4e59e288 | 200 | static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = { |
9908aa29 | 201 | "rx_cqe_moder", |
0088cbbc | 202 | "tx_cqe_moder", |
9bcc8606 | 203 | "rx_cqe_compress", |
4e59e288 GP |
204 | }; |
205 | ||
206 | enum mlx5e_priv_flag { | |
9908aa29 | 207 | MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0), |
0088cbbc TG |
208 | MLX5E_PFLAG_TX_CQE_BASED_MODER = (1 << 1), |
209 | MLX5E_PFLAG_RX_CQE_COMPRESS = (1 << 2), | |
4e59e288 GP |
210 | }; |
211 | ||
6a9764ef | 212 | #define MLX5E_SET_PFLAG(params, pflag, enable) \ |
59ece1c9 SD |
213 | do { \ |
214 | if (enable) \ | |
6a9764ef | 215 | (params)->pflags |= (pflag); \ |
59ece1c9 | 216 | else \ |
6a9764ef | 217 | (params)->pflags &= ~(pflag); \ |
4e59e288 GP |
218 | } while (0) |
219 | ||
6a9764ef | 220 | #define MLX5E_GET_PFLAG(params, pflag) (!!((params)->pflags & (pflag))) |
59ece1c9 | 221 | |
08fb1dac SM |
222 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
223 | #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */ | |
08fb1dac SM |
224 | #endif |
225 | ||
9908aa29 TT |
226 | struct mlx5e_cq_moder { |
227 | u16 usec; | |
228 | u16 pkts; | |
0088cbbc | 229 | u8 cq_period_mode; |
9908aa29 TT |
230 | }; |
231 | ||
f62b8bb8 AV |
232 | struct mlx5e_params { |
233 | u8 log_sq_size; | |
461017cb | 234 | u8 rq_wq_type; |
bce2b2bf | 235 | u16 rq_headroom; |
d9d9f156 TT |
236 | u8 mpwqe_log_stride_sz; |
237 | u8 mpwqe_log_num_strides; | |
f62b8bb8 AV |
238 | u8 log_rq_size; |
239 | u16 num_channels; | |
f62b8bb8 | 240 | u8 num_tc; |
9bcc8606 | 241 | bool rx_cqe_compress_def; |
9908aa29 TT |
242 | struct mlx5e_cq_moder rx_cq_moderation; |
243 | struct mlx5e_cq_moder tx_cq_moderation; | |
f62b8bb8 AV |
244 | bool lro_en; |
245 | u32 lro_wqe_sz; | |
58d52291 | 246 | u16 tx_max_inline; |
cff92d7c | 247 | u8 tx_min_inline_mode; |
2d75b2bc AS |
248 | u8 rss_hfunc; |
249 | u8 toeplitz_hash_key[40]; | |
250 | u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE]; | |
36350114 | 251 | bool vlan_strip_disable; |
102722fc | 252 | bool scatter_fcs_en; |
cb3c7fd4 | 253 | bool rx_am_enabled; |
2b029556 | 254 | u32 lro_timeout; |
59ece1c9 | 255 | u32 pflags; |
6a9764ef | 256 | struct bpf_prog *xdp_prog; |
f62b8bb8 AV |
257 | }; |
258 | ||
3a6a931d HN |
259 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
260 | struct mlx5e_cee_config { | |
261 | /* bw pct for priority group */ | |
262 | u8 pg_bw_pct[CEE_DCBX_MAX_PGS]; | |
263 | u8 prio_to_pg_map[CEE_DCBX_MAX_PRIO]; | |
264 | bool pfc_setting[CEE_DCBX_MAX_PRIO]; | |
265 | bool pfc_enable; | |
266 | }; | |
267 | ||
268 | enum { | |
269 | MLX5_DCB_CHG_RESET, | |
270 | MLX5_DCB_NO_CHG, | |
271 | MLX5_DCB_CHG_NO_RESET, | |
272 | }; | |
273 | ||
274 | struct mlx5e_dcbx { | |
e207b7e9 | 275 | enum mlx5_dcbx_oper_mode mode; |
3a6a931d | 276 | struct mlx5e_cee_config cee_cfg; /* pending configuration */ |
2a5e7a13 | 277 | u8 dscp_app_cnt; |
820c2c5e HN |
278 | |
279 | /* The only setting that cannot be read from FW */ | |
280 | u8 tc_tsa[IEEE_8021QAZ_MAX_TCS]; | |
9e10bf1d | 281 | u8 cap; |
3a6a931d | 282 | }; |
2a5e7a13 HN |
283 | |
284 | struct mlx5e_dcbx_dp { | |
285 | u8 dscp2prio[MLX5E_MAX_DSCP]; | |
286 | u8 trust_state; | |
287 | }; | |
3a6a931d HN |
288 | #endif |
289 | ||
f62b8bb8 | 290 | enum { |
c0f1147d | 291 | MLX5E_RQ_STATE_ENABLED, |
cb3c7fd4 | 292 | MLX5E_RQ_STATE_AM, |
f62b8bb8 AV |
293 | }; |
294 | ||
a1eaba4c TT |
295 | #define MLX5E_TEST_BIT(state, nr) (state & BIT(nr)) |
296 | ||
f62b8bb8 AV |
297 | struct mlx5e_cq { |
298 | /* data path - accessed per cqe */ | |
299 | struct mlx5_cqwq wq; | |
f62b8bb8 AV |
300 | |
301 | /* data path - accessed per napi poll */ | |
cb3c7fd4 | 302 | u16 event_ctr; |
f62b8bb8 AV |
303 | struct napi_struct *napi; |
304 | struct mlx5_core_cq mcq; | |
305 | struct mlx5e_channel *channel; | |
306 | ||
7219ab34 TT |
307 | /* cqe decompression */ |
308 | struct mlx5_cqe64 title; | |
309 | struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE]; | |
310 | u8 mini_arr_idx; | |
311 | u16 decmprs_left; | |
312 | u16 decmprs_wqe_counter; | |
313 | ||
f62b8bb8 | 314 | /* control */ |
a43b25da | 315 | struct mlx5_core_dev *mdev; |
1c1b5228 | 316 | struct mlx5_frag_wq_ctrl wq_ctrl; |
f62b8bb8 AV |
317 | } ____cacheline_aligned_in_smp; |
318 | ||
eba2db2b | 319 | struct mlx5e_tx_wqe_info { |
77bdf895 | 320 | struct sk_buff *skb; |
eba2db2b SM |
321 | u32 num_bytes; |
322 | u8 num_wqebbs; | |
323 | u8 num_dma; | |
324 | }; | |
325 | ||
326 | enum mlx5e_dma_map_type { | |
327 | MLX5E_DMA_MAP_SINGLE, | |
328 | MLX5E_DMA_MAP_PAGE | |
329 | }; | |
330 | ||
331 | struct mlx5e_sq_dma { | |
332 | dma_addr_t addr; | |
333 | u32 size; | |
334 | enum mlx5e_dma_map_type type; | |
335 | }; | |
336 | ||
337 | enum { | |
338 | MLX5E_SQ_STATE_ENABLED, | |
2ac9cfe7 | 339 | MLX5E_SQ_STATE_IPSEC, |
eba2db2b SM |
340 | }; |
341 | ||
342 | struct mlx5e_sq_wqe_info { | |
343 | u8 opcode; | |
eba2db2b | 344 | }; |
2f48af12 | 345 | |
31391048 | 346 | struct mlx5e_txqsq { |
eba2db2b SM |
347 | /* data path */ |
348 | ||
349 | /* dirtied @completion */ | |
350 | u16 cc; | |
351 | u32 dma_fifo_cc; | |
352 | ||
353 | /* dirtied @xmit */ | |
354 | u16 pc ____cacheline_aligned_in_smp; | |
355 | u32 dma_fifo_pc; | |
356 | struct mlx5e_sq_stats stats; | |
357 | ||
358 | struct mlx5e_cq cq; | |
359 | ||
31391048 SM |
360 | /* write@xmit, read@completion */ |
361 | struct { | |
31391048 SM |
362 | struct mlx5e_sq_dma *dma_fifo; |
363 | struct mlx5e_tx_wqe_info *wqe_info; | |
eba2db2b SM |
364 | } db; |
365 | ||
366 | /* read only */ | |
367 | struct mlx5_wq_cyc wq; | |
368 | u32 dma_fifo_mask; | |
369 | void __iomem *uar_map; | |
370 | struct netdev_queue *txq; | |
371 | u32 sqn; | |
372 | u16 max_inline; | |
373 | u8 min_inline_mode; | |
374 | u16 edge; | |
375 | struct device *pdev; | |
eba2db2b SM |
376 | __be32 mkey_be; |
377 | unsigned long state; | |
7c39afb3 FD |
378 | struct hwtstamp_config *tstamp; |
379 | struct mlx5_clock *clock; | |
eba2db2b SM |
380 | |
381 | /* control path */ | |
382 | struct mlx5_wq_ctrl wq_ctrl; | |
383 | struct mlx5e_channel *channel; | |
acc6c595 | 384 | int txq_ix; |
eba2db2b | 385 | u32 rate_limit; |
31391048 SM |
386 | } ____cacheline_aligned_in_smp; |
387 | ||
388 | struct mlx5e_xdpsq { | |
389 | /* data path */ | |
390 | ||
391 | /* dirtied @rx completion */ | |
392 | u16 cc; | |
393 | u16 pc; | |
394 | ||
395 | struct mlx5e_cq cq; | |
396 | ||
397 | /* write@xmit, read@completion */ | |
398 | struct { | |
399 | struct mlx5e_dma_info *di; | |
400 | bool doorbell; | |
401 | } db; | |
402 | ||
403 | /* read only */ | |
404 | struct mlx5_wq_cyc wq; | |
405 | void __iomem *uar_map; | |
406 | u32 sqn; | |
407 | struct device *pdev; | |
408 | __be32 mkey_be; | |
409 | u8 min_inline_mode; | |
410 | unsigned long state; | |
411 | ||
412 | /* control path */ | |
413 | struct mlx5_wq_ctrl wq_ctrl; | |
414 | struct mlx5e_channel *channel; | |
415 | } ____cacheline_aligned_in_smp; | |
416 | ||
417 | struct mlx5e_icosq { | |
418 | /* data path */ | |
419 | ||
31391048 SM |
420 | /* dirtied @xmit */ |
421 | u16 pc ____cacheline_aligned_in_smp; | |
31391048 SM |
422 | |
423 | struct mlx5e_cq cq; | |
424 | ||
425 | /* write@xmit, read@completion */ | |
426 | struct { | |
427 | struct mlx5e_sq_wqe_info *ico_wqe; | |
428 | } db; | |
429 | ||
430 | /* read only */ | |
431 | struct mlx5_wq_cyc wq; | |
432 | void __iomem *uar_map; | |
433 | u32 sqn; | |
434 | u16 edge; | |
31391048 SM |
435 | __be32 mkey_be; |
436 | unsigned long state; | |
437 | ||
438 | /* control path */ | |
439 | struct mlx5_wq_ctrl wq_ctrl; | |
440 | struct mlx5e_channel *channel; | |
eba2db2b SM |
441 | } ____cacheline_aligned_in_smp; |
442 | ||
864b2d71 SM |
443 | static inline bool |
444 | mlx5e_wqc_has_room_for(struct mlx5_wq_cyc *wq, u16 cc, u16 pc, u16 n) | |
eba2db2b | 445 | { |
864b2d71 | 446 | return (((wq->sz_m1 & (cc - pc)) >= n) || (cc == pc)); |
eba2db2b | 447 | } |
6cd392a0 | 448 | |
461017cb TT |
449 | struct mlx5e_dma_info { |
450 | struct page *page; | |
451 | dma_addr_t addr; | |
452 | }; | |
453 | ||
accd5883 TT |
454 | struct mlx5e_wqe_frag_info { |
455 | struct mlx5e_dma_info di; | |
456 | u32 offset; | |
457 | }; | |
458 | ||
eba2db2b SM |
459 | struct mlx5e_umr_dma_info { |
460 | __be64 *mtt; | |
461 | dma_addr_t mtt_addr; | |
462 | struct mlx5e_dma_info dma_info[MLX5_MPWRQ_PAGES_PER_WQE]; | |
463 | struct mlx5e_umr_wqe wqe; | |
464 | }; | |
465 | ||
466 | struct mlx5e_mpw_info { | |
467 | struct mlx5e_umr_dma_info umr; | |
468 | u16 consumed_strides; | |
469 | u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE]; | |
470 | }; | |
471 | ||
cb3c7fd4 GR |
472 | struct mlx5e_rx_am_stats { |
473 | int ppms; /* packets per msec */ | |
c3164d2f | 474 | int bpms; /* bytes per msec */ |
cb3c7fd4 GR |
475 | int epms; /* events per msec */ |
476 | }; | |
477 | ||
478 | struct mlx5e_rx_am_sample { | |
53acd76c TG |
479 | ktime_t time; |
480 | u32 pkt_ctr; | |
481 | u32 byte_ctr; | |
482 | u16 event_ctr; | |
cb3c7fd4 GR |
483 | }; |
484 | ||
485 | struct mlx5e_rx_am { /* Adaptive Moderation */ | |
486 | u8 state; | |
487 | struct mlx5e_rx_am_stats prev_stats; | |
488 | struct mlx5e_rx_am_sample start_sample; | |
489 | struct work_struct work; | |
490 | u8 profile_ix; | |
491 | u8 mode; | |
492 | u8 tune_state; | |
493 | u8 steps_right; | |
494 | u8 steps_left; | |
495 | u8 tired; | |
496 | }; | |
497 | ||
4415a031 TT |
498 | /* a single cache unit is capable to serve one napi call (for non-striding rq) |
499 | * or a MPWQE (for striding rq). | |
500 | */ | |
501 | #define MLX5E_CACHE_UNIT (MLX5_MPWRQ_PAGES_PER_WQE > NAPI_POLL_WEIGHT ? \ | |
502 | MLX5_MPWRQ_PAGES_PER_WQE : NAPI_POLL_WEIGHT) | |
29c2849e | 503 | #define MLX5E_CACHE_SIZE (4 * roundup_pow_of_two(MLX5E_CACHE_UNIT)) |
4415a031 TT |
504 | struct mlx5e_page_cache { |
505 | u32 head; | |
506 | u32 tail; | |
507 | struct mlx5e_dma_info page_cache[MLX5E_CACHE_SIZE]; | |
508 | }; | |
509 | ||
eba2db2b SM |
510 | struct mlx5e_rq; |
511 | typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq*, struct mlx5_cqe64*); | |
7cc6d77b | 512 | typedef bool (*mlx5e_fp_post_rx_wqes)(struct mlx5e_rq *rq); |
eba2db2b SM |
513 | typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq*, u16); |
514 | ||
f62b8bb8 AV |
515 | struct mlx5e_rq { |
516 | /* data path */ | |
517 | struct mlx5_wq_ll wq; | |
1bfecfca | 518 | |
21c59685 | 519 | union { |
accd5883 TT |
520 | struct { |
521 | struct mlx5e_wqe_frag_info *frag_info; | |
522 | u32 frag_sz; /* max possible skb frag_sz */ | |
b45d8b50 TT |
523 | union { |
524 | bool page_reuse; | |
525 | bool xdp_xmit; | |
526 | }; | |
accd5883 | 527 | } wqe; |
21c59685 SM |
528 | struct { |
529 | struct mlx5e_mpw_info *info; | |
530 | void *mtt_no_align; | |
b45d8b50 | 531 | u16 num_strides; |
89e89f7a | 532 | u8 log_stride_sz; |
a071cb9f | 533 | bool umr_in_progress; |
21c59685 SM |
534 | } mpwqe; |
535 | }; | |
1bfecfca | 536 | struct { |
b45d8b50 | 537 | u16 headroom; |
1bfecfca | 538 | u8 page_order; |
b5503b99 | 539 | u8 map_dir; /* dma map direction */ |
1bfecfca | 540 | } buff; |
f62b8bb8 | 541 | |
7cc6d77b | 542 | struct mlx5e_channel *channel; |
f62b8bb8 AV |
543 | struct device *pdev; |
544 | struct net_device *netdev; | |
545 | struct mlx5e_rq_stats stats; | |
546 | struct mlx5e_cq cq; | |
4415a031 | 547 | struct mlx5e_page_cache page_cache; |
7c39afb3 FD |
548 | struct hwtstamp_config *tstamp; |
549 | struct mlx5_clock *clock; | |
4415a031 | 550 | |
2f48af12 | 551 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; |
7cc6d77b | 552 | mlx5e_fp_post_rx_wqes post_wqes; |
6cd392a0 | 553 | mlx5e_fp_dealloc_wqe dealloc_wqe; |
f62b8bb8 AV |
554 | |
555 | unsigned long state; | |
556 | int ix; | |
557 | ||
cb3c7fd4 | 558 | struct mlx5e_rx_am am; /* Adaptive Moderation */ |
31871f87 SM |
559 | |
560 | /* XDP */ | |
86994156 | 561 | struct bpf_prog *xdp_prog; |
31391048 | 562 | struct mlx5e_xdpsq xdpsq; |
cb3c7fd4 | 563 | |
f62b8bb8 AV |
564 | /* control */ |
565 | struct mlx5_wq_ctrl wq_ctrl; | |
b45d8b50 | 566 | __be32 mkey_be; |
461017cb | 567 | u8 wq_type; |
f62b8bb8 | 568 | u32 rqn; |
a43b25da | 569 | struct mlx5_core_dev *mdev; |
ec8b9981 | 570 | struct mlx5_core_mkey umr_mkey; |
f62b8bb8 AV |
571 | } ____cacheline_aligned_in_smp; |
572 | ||
f62b8bb8 AV |
573 | struct mlx5e_channel { |
574 | /* data path */ | |
575 | struct mlx5e_rq rq; | |
31391048 SM |
576 | struct mlx5e_txqsq sq[MLX5E_MAX_NUM_TC]; |
577 | struct mlx5e_icosq icosq; /* internal control operations */ | |
b5503b99 | 578 | bool xdp; |
f62b8bb8 AV |
579 | struct napi_struct napi; |
580 | struct device *pdev; | |
581 | struct net_device *netdev; | |
582 | __be32 mkey_be; | |
583 | u8 num_tc; | |
f62b8bb8 | 584 | |
a8c2eb15 TT |
585 | /* data path - accessed per napi poll */ |
586 | struct irq_desc *irq_desc; | |
f62b8bb8 AV |
587 | |
588 | /* control */ | |
589 | struct mlx5e_priv *priv; | |
a43b25da | 590 | struct mlx5_core_dev *mdev; |
7c39afb3 | 591 | struct hwtstamp_config *tstamp; |
f62b8bb8 | 592 | int ix; |
231243c8 | 593 | int cpu; |
f62b8bb8 AV |
594 | }; |
595 | ||
ff9c852f SM |
596 | struct mlx5e_channels { |
597 | struct mlx5e_channel **c; | |
598 | unsigned int num; | |
6a9764ef | 599 | struct mlx5e_params params; |
ff9c852f SM |
600 | }; |
601 | ||
f62b8bb8 | 602 | enum mlx5e_traffic_types { |
5a6f8aef AS |
603 | MLX5E_TT_IPV4_TCP, |
604 | MLX5E_TT_IPV6_TCP, | |
605 | MLX5E_TT_IPV4_UDP, | |
606 | MLX5E_TT_IPV6_UDP, | |
a741749f AS |
607 | MLX5E_TT_IPV4_IPSEC_AH, |
608 | MLX5E_TT_IPV6_IPSEC_AH, | |
609 | MLX5E_TT_IPV4_IPSEC_ESP, | |
610 | MLX5E_TT_IPV6_IPSEC_ESP, | |
5a6f8aef AS |
611 | MLX5E_TT_IPV4, |
612 | MLX5E_TT_IPV6, | |
613 | MLX5E_TT_ANY, | |
614 | MLX5E_NUM_TT, | |
1da36696 | 615 | MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, |
f62b8bb8 AV |
616 | }; |
617 | ||
7b3722fa GP |
618 | enum mlx5e_tunnel_types { |
619 | MLX5E_TT_IPV4_GRE, | |
620 | MLX5E_TT_IPV6_GRE, | |
621 | MLX5E_NUM_TUNNEL_TT, | |
622 | }; | |
623 | ||
acff797c | 624 | enum { |
e0f46eb9 | 625 | MLX5E_STATE_ASYNC_EVENTS_ENABLED, |
acff797c MG |
626 | MLX5E_STATE_OPENED, |
627 | MLX5E_STATE_DESTROYING, | |
628 | }; | |
629 | ||
630 | struct mlx5e_vxlan_db { | |
631 | spinlock_t lock; /* protect vxlan table */ | |
632 | struct radix_tree_root tree; | |
633 | }; | |
634 | ||
33cfaaa8 | 635 | struct mlx5e_l2_rule { |
f62b8bb8 | 636 | u8 addr[ETH_ALEN + 2]; |
74491de9 | 637 | struct mlx5_flow_handle *rule; |
f62b8bb8 AV |
638 | }; |
639 | ||
acff797c MG |
640 | struct mlx5e_flow_table { |
641 | int num_groups; | |
642 | struct mlx5_flow_table *t; | |
643 | struct mlx5_flow_group **g; | |
644 | }; | |
645 | ||
33cfaaa8 | 646 | #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE) |
f62b8bb8 | 647 | |
acff797c MG |
648 | struct mlx5e_tc_table { |
649 | struct mlx5_flow_table *t; | |
650 | ||
651 | struct rhashtable_params ht_params; | |
652 | struct rhashtable ht; | |
11c9c548 OG |
653 | |
654 | DECLARE_HASHTABLE(mod_hdr_tbl, 8); | |
f62b8bb8 AV |
655 | }; |
656 | ||
acff797c MG |
657 | struct mlx5e_vlan_table { |
658 | struct mlx5e_flow_table ft; | |
03eda954 | 659 | DECLARE_BITMAP(active_cvlans, VLAN_N_VID); |
7d92d580 | 660 | DECLARE_BITMAP(active_svlans, VLAN_N_VID); |
2b52a283 | 661 | struct mlx5_flow_handle *active_cvlans_rule[VLAN_N_VID]; |
7d92d580 | 662 | struct mlx5_flow_handle *active_svlans_rule[VLAN_N_VID]; |
74491de9 | 663 | struct mlx5_flow_handle *untagged_rule; |
8a271746 MHY |
664 | struct mlx5_flow_handle *any_cvlan_rule; |
665 | struct mlx5_flow_handle *any_svlan_rule; | |
2b52a283 | 666 | bool cvlan_filter_disabled; |
f62b8bb8 AV |
667 | }; |
668 | ||
33cfaaa8 MG |
669 | struct mlx5e_l2_table { |
670 | struct mlx5e_flow_table ft; | |
671 | struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE]; | |
672 | struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE]; | |
673 | struct mlx5e_l2_rule broadcast; | |
674 | struct mlx5e_l2_rule allmulti; | |
675 | struct mlx5e_l2_rule promisc; | |
676 | bool broadcast_enabled; | |
677 | bool allmulti_enabled; | |
678 | bool promisc_enabled; | |
679 | }; | |
680 | ||
681 | /* L3/L4 traffic type classifier */ | |
682 | struct mlx5e_ttc_table { | |
683 | struct mlx5e_flow_table ft; | |
74491de9 | 684 | struct mlx5_flow_handle *rules[MLX5E_NUM_TT]; |
7b3722fa | 685 | struct mlx5_flow_handle *tunnel_rules[MLX5E_NUM_TUNNEL_TT]; |
33cfaaa8 MG |
686 | }; |
687 | ||
18c908e4 MG |
688 | #define ARFS_HASH_SHIFT BITS_PER_BYTE |
689 | #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE) | |
1cabe6b0 MG |
690 | struct arfs_table { |
691 | struct mlx5e_flow_table ft; | |
74491de9 | 692 | struct mlx5_flow_handle *default_rule; |
18c908e4 | 693 | struct hlist_head rules_hash[ARFS_HASH_SIZE]; |
1cabe6b0 MG |
694 | }; |
695 | ||
696 | enum arfs_type { | |
697 | ARFS_IPV4_TCP, | |
698 | ARFS_IPV6_TCP, | |
699 | ARFS_IPV4_UDP, | |
700 | ARFS_IPV6_UDP, | |
701 | ARFS_NUM_TYPES, | |
702 | }; | |
703 | ||
704 | struct mlx5e_arfs_tables { | |
705 | struct arfs_table arfs_tables[ARFS_NUM_TYPES]; | |
18c908e4 MG |
706 | /* Protect aRFS rules list */ |
707 | spinlock_t arfs_lock; | |
708 | struct list_head rules; | |
709 | int last_filter_id; | |
710 | struct workqueue_struct *wq; | |
1cabe6b0 MG |
711 | }; |
712 | ||
713 | /* NIC prio FTS */ | |
714 | enum { | |
715 | MLX5E_VLAN_FT_LEVEL = 0, | |
716 | MLX5E_L2_FT_LEVEL, | |
717 | MLX5E_TTC_FT_LEVEL, | |
7b3722fa | 718 | MLX5E_INNER_TTC_FT_LEVEL, |
1cabe6b0 MG |
719 | MLX5E_ARFS_FT_LEVEL |
720 | }; | |
721 | ||
6dc6071c MG |
722 | struct mlx5e_ethtool_table { |
723 | struct mlx5_flow_table *ft; | |
724 | int num_rules; | |
725 | }; | |
726 | ||
1174fce8 | 727 | #define ETHTOOL_NUM_L3_L4_FTS 7 |
6dc6071c MG |
728 | #define ETHTOOL_NUM_L2_FTS 4 |
729 | ||
730 | struct mlx5e_ethtool_steering { | |
1174fce8 | 731 | struct mlx5e_ethtool_table l3_l4_ft[ETHTOOL_NUM_L3_L4_FTS]; |
6dc6071c MG |
732 | struct mlx5e_ethtool_table l2_ft[ETHTOOL_NUM_L2_FTS]; |
733 | struct list_head rules; | |
734 | int tot_num_rules; | |
735 | }; | |
736 | ||
acff797c MG |
737 | struct mlx5e_flow_steering { |
738 | struct mlx5_flow_namespace *ns; | |
6dc6071c | 739 | struct mlx5e_ethtool_steering ethtool; |
acff797c MG |
740 | struct mlx5e_tc_table tc; |
741 | struct mlx5e_vlan_table vlan; | |
33cfaaa8 MG |
742 | struct mlx5e_l2_table l2; |
743 | struct mlx5e_ttc_table ttc; | |
7b3722fa | 744 | struct mlx5e_ttc_table inner_ttc; |
1cabe6b0 | 745 | struct mlx5e_arfs_tables arfs; |
f62b8bb8 AV |
746 | }; |
747 | ||
398f3351 | 748 | struct mlx5e_rqt { |
1da36696 | 749 | u32 rqtn; |
398f3351 HHZ |
750 | bool enabled; |
751 | }; | |
752 | ||
753 | struct mlx5e_tir { | |
754 | u32 tirn; | |
755 | struct mlx5e_rqt rqt; | |
756 | struct list_head list; | |
1da36696 TT |
757 | }; |
758 | ||
acff797c MG |
759 | enum { |
760 | MLX5E_TC_PRIO = 0, | |
761 | MLX5E_NIC_PRIO | |
762 | }; | |
763 | ||
f62b8bb8 AV |
764 | struct mlx5e_priv { |
765 | /* priv data path fields - start */ | |
acc6c595 SM |
766 | struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC]; |
767 | int channel_tc2txq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC]; | |
2a5e7a13 HN |
768 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
769 | struct mlx5e_dcbx_dp dcbx_dp; | |
770 | #endif | |
f62b8bb8 AV |
771 | /* priv data path fields - end */ |
772 | ||
79c48764 | 773 | u32 msglevel; |
f62b8bb8 AV |
774 | unsigned long state; |
775 | struct mutex state_lock; /* Protects Interface state */ | |
50cfa25a | 776 | struct mlx5e_rq drop_rq; |
f62b8bb8 | 777 | |
ff9c852f | 778 | struct mlx5e_channels channels; |
f62b8bb8 | 779 | u32 tisn[MLX5E_MAX_NUM_TC]; |
398f3351 | 780 | struct mlx5e_rqt indir_rqt; |
724b2aa1 | 781 | struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS]; |
7b3722fa | 782 | struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS]; |
724b2aa1 | 783 | struct mlx5e_tir direct_tir[MLX5E_MAX_NUM_CHANNELS]; |
507f0c81 | 784 | u32 tx_rates[MLX5E_MAX_NUM_SQS]; |
c139dbfd | 785 | int hard_mtu; |
f62b8bb8 | 786 | |
acff797c | 787 | struct mlx5e_flow_steering fs; |
b3f63c3d | 788 | struct mlx5e_vxlan_db vxlan; |
f62b8bb8 | 789 | |
7bb29755 | 790 | struct workqueue_struct *wq; |
f62b8bb8 AV |
791 | struct work_struct update_carrier_work; |
792 | struct work_struct set_rx_mode_work; | |
3947ca18 | 793 | struct work_struct tx_timeout_work; |
f62b8bb8 AV |
794 | struct delayed_work update_stats_work; |
795 | ||
796 | struct mlx5_core_dev *mdev; | |
797 | struct net_device *netdev; | |
798 | struct mlx5e_stats stats; | |
7c39afb3 | 799 | struct hwtstamp_config tstamp; |
593cf338 | 800 | u16 q_counter; |
3a6a931d HN |
801 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
802 | struct mlx5e_dcbx dcbx; | |
803 | #endif | |
804 | ||
6bfd390b | 805 | const struct mlx5e_profile *profile; |
127ea380 | 806 | void *ppriv; |
547eede0 IT |
807 | #ifdef CONFIG_MLX5_EN_IPSEC |
808 | struct mlx5e_ipsec *ipsec; | |
809 | #endif | |
f62b8bb8 AV |
810 | }; |
811 | ||
a43b25da SM |
812 | struct mlx5e_profile { |
813 | void (*init)(struct mlx5_core_dev *mdev, | |
814 | struct net_device *netdev, | |
815 | const struct mlx5e_profile *profile, void *ppriv); | |
816 | void (*cleanup)(struct mlx5e_priv *priv); | |
817 | int (*init_rx)(struct mlx5e_priv *priv); | |
818 | void (*cleanup_rx)(struct mlx5e_priv *priv); | |
819 | int (*init_tx)(struct mlx5e_priv *priv); | |
820 | void (*cleanup_tx)(struct mlx5e_priv *priv); | |
821 | void (*enable)(struct mlx5e_priv *priv); | |
822 | void (*disable)(struct mlx5e_priv *priv); | |
823 | void (*update_stats)(struct mlx5e_priv *priv); | |
7ca42c80 | 824 | void (*update_carrier)(struct mlx5e_priv *priv); |
a43b25da | 825 | int (*max_nch)(struct mlx5_core_dev *mdev); |
20fd0c19 SM |
826 | struct { |
827 | mlx5e_fp_handle_rx_cqe handle_rx_cqe; | |
828 | mlx5e_fp_handle_rx_cqe handle_rx_cqe_mpwqe; | |
829 | } rx_handlers; | |
2a5e7a13 HN |
830 | void (*netdev_registered_init)(struct mlx5e_priv *priv); |
831 | void (*netdev_registered_remove)(struct mlx5e_priv *priv); | |
a43b25da SM |
832 | int max_tc; |
833 | }; | |
834 | ||
665bc539 GP |
835 | void mlx5e_build_ptys2ethtool_map(void); |
836 | ||
f62b8bb8 AV |
837 | u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb, |
838 | void *accel_priv, select_queue_fallback_t fallback); | |
839 | netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev); | |
f62b8bb8 AV |
840 | |
841 | void mlx5e_completion_event(struct mlx5_core_cq *mcq); | |
842 | void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event); | |
843 | int mlx5e_napi_poll(struct napi_struct *napi, int budget); | |
8ec736e5 | 844 | bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget); |
44fb6fbb | 845 | int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget); |
1c4bf940 | 846 | bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq *cq); |
31391048 SM |
847 | void mlx5e_free_txqsq_descs(struct mlx5e_txqsq *sq); |
848 | void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq *sq); | |
461017cb | 849 | |
4415a031 TT |
850 | void mlx5e_page_release(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info, |
851 | bool recycle); | |
2f48af12 | 852 | void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
461017cb | 853 | void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe); |
f62b8bb8 | 854 | bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq); |
7cc6d77b | 855 | bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq); |
6cd392a0 DJ |
856 | void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix); |
857 | void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix); | |
7e426671 | 858 | void mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi); |
f62b8bb8 | 859 | |
cb3c7fd4 GR |
860 | void mlx5e_rx_am(struct mlx5e_rq *rq); |
861 | void mlx5e_rx_am_work(struct work_struct *work); | |
862 | struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode); | |
863 | ||
3834a5e6 | 864 | void mlx5e_update_stats(struct mlx5e_priv *priv, bool full); |
f62b8bb8 | 865 | |
acff797c MG |
866 | int mlx5e_create_flow_steering(struct mlx5e_priv *priv); |
867 | void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv); | |
33cfaaa8 | 868 | void mlx5e_init_l2_addr(struct mlx5e_priv *priv); |
1cabe6b0 | 869 | void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft); |
d605d668 KH |
870 | int mlx5e_self_test_num(struct mlx5e_priv *priv); |
871 | void mlx5e_self_test(struct net_device *ndev, struct ethtool_test *etest, | |
872 | u64 *buf); | |
f913a72a MG |
873 | int mlx5e_ethtool_get_flow(struct mlx5e_priv *priv, struct ethtool_rxnfc *info, |
874 | int location); | |
875 | int mlx5e_ethtool_get_all_flows(struct mlx5e_priv *priv, | |
876 | struct ethtool_rxnfc *info, u32 *rule_locs); | |
6dc6071c MG |
877 | int mlx5e_ethtool_flow_replace(struct mlx5e_priv *priv, |
878 | struct ethtool_rx_flow_spec *fs); | |
879 | int mlx5e_ethtool_flow_remove(struct mlx5e_priv *priv, | |
880 | int location); | |
881 | void mlx5e_ethtool_init_steering(struct mlx5e_priv *priv); | |
882 | void mlx5e_ethtool_cleanup_steering(struct mlx5e_priv *priv); | |
f62b8bb8 AV |
883 | void mlx5e_set_rx_mode_work(struct work_struct *work); |
884 | ||
1170fbd8 FD |
885 | int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr); |
886 | int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr); | |
be7e87f9 | 887 | int mlx5e_modify_rx_cqe_compression_locked(struct mlx5e_priv *priv, bool val); |
ef9814de | 888 | |
f62b8bb8 AV |
889 | int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto, |
890 | u16 vid); | |
891 | int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto, | |
892 | u16 vid); | |
2b52a283 GP |
893 | void mlx5e_enable_cvlan_filter(struct mlx5e_priv *priv); |
894 | void mlx5e_disable_cvlan_filter(struct mlx5e_priv *priv); | |
7c39afb3 | 895 | void mlx5e_timestamp_set(struct mlx5e_priv *priv); |
f62b8bb8 | 896 | |
a5f97fee SM |
897 | struct mlx5e_redirect_rqt_param { |
898 | bool is_rss; | |
899 | union { | |
900 | u32 rqn; /* Direct RQN (Non-RSS) */ | |
901 | struct { | |
902 | u8 hfunc; | |
903 | struct mlx5e_channels *channels; | |
904 | } rss; /* RSS data */ | |
905 | }; | |
906 | }; | |
907 | ||
908 | int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, | |
909 | struct mlx5e_redirect_rqt_param rrp); | |
6a9764ef SM |
910 | void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params, |
911 | enum mlx5e_traffic_types tt, | |
7b3722fa | 912 | void *tirc, bool inner); |
2d75b2bc | 913 | |
f62b8bb8 AV |
914 | int mlx5e_open_locked(struct net_device *netdev); |
915 | int mlx5e_close_locked(struct net_device *netdev); | |
55c2503d SM |
916 | |
917 | int mlx5e_open_channels(struct mlx5e_priv *priv, | |
918 | struct mlx5e_channels *chs); | |
919 | void mlx5e_close_channels(struct mlx5e_channels *chs); | |
2e20a151 SM |
920 | |
921 | /* Function pointer to be used to modify WH settings while | |
922 | * switching channels | |
923 | */ | |
924 | typedef int (*mlx5e_fp_hw_modify)(struct mlx5e_priv *priv); | |
55c2503d | 925 | void mlx5e_switch_priv_channels(struct mlx5e_priv *priv, |
2e20a151 SM |
926 | struct mlx5e_channels *new_chs, |
927 | mlx5e_fp_hw_modify hw_modify); | |
603f4a45 SM |
928 | void mlx5e_activate_priv_channels(struct mlx5e_priv *priv); |
929 | void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv); | |
55c2503d | 930 | |
d4b6c488 | 931 | void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len, |
85082dba | 932 | int num_channels); |
b797a684 | 933 | int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); |
f62b8bb8 | 934 | |
0088cbbc TG |
935 | void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, |
936 | u8 cq_period_mode); | |
9908aa29 TT |
937 | void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, |
938 | u8 cq_period_mode); | |
6a9764ef SM |
939 | void mlx5e_set_rq_type_params(struct mlx5_core_dev *mdev, |
940 | struct mlx5e_params *params, u8 rq_type); | |
9908aa29 | 941 | |
7b3722fa GP |
942 | static inline bool mlx5e_tunnel_inner_ft_supported(struct mlx5_core_dev *mdev) |
943 | { | |
944 | return (MLX5_CAP_ETH(mdev, tunnel_stateless_gre) && | |
945 | MLX5_CAP_FLOWTABLE_NIC_RX(mdev, ft_field_support.inner_ip_version)); | |
946 | } | |
947 | ||
864b2d71 SM |
948 | static inline |
949 | struct mlx5e_tx_wqe *mlx5e_post_nop(struct mlx5_wq_cyc *wq, u32 sqn, u16 *pc) | |
f62b8bb8 | 950 | { |
864b2d71 SM |
951 | u16 pi = *pc & wq->sz_m1; |
952 | struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(wq, pi); | |
953 | struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl; | |
954 | ||
955 | memset(cseg, 0, sizeof(*cseg)); | |
956 | ||
957 | cseg->opmod_idx_opcode = cpu_to_be32((*pc << 8) | MLX5_OPCODE_NOP); | |
958 | cseg->qpn_ds = cpu_to_be32((sqn << 8) | 0x01); | |
959 | ||
960 | (*pc)++; | |
961 | ||
962 | return wqe; | |
963 | } | |
964 | ||
965 | static inline | |
966 | void mlx5e_notify_hw(struct mlx5_wq_cyc *wq, u16 pc, | |
967 | void __iomem *uar_map, | |
968 | struct mlx5_wqe_ctrl_seg *ctrl) | |
969 | { | |
970 | ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE; | |
f62b8bb8 AV |
971 | /* ensure wqe is visible to device before updating doorbell record */ |
972 | dma_wmb(); | |
973 | ||
864b2d71 | 974 | *wq->db = cpu_to_be32(pc); |
f62b8bb8 AV |
975 | |
976 | /* ensure doorbell record is visible to device before ringing the | |
977 | * doorbell | |
978 | */ | |
979 | wmb(); | |
f62b8bb8 | 980 | |
864b2d71 | 981 | mlx5_write64((__be32 *)ctrl, uar_map, NULL); |
f62b8bb8 AV |
982 | } |
983 | ||
984 | static inline void mlx5e_cq_arm(struct mlx5e_cq *cq) | |
985 | { | |
986 | struct mlx5_core_cq *mcq; | |
987 | ||
988 | mcq = &cq->mcq; | |
5fe9dec0 | 989 | mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, cq->wq.cc); |
f62b8bb8 AV |
990 | } |
991 | ||
7e426671 TT |
992 | static inline u32 mlx5e_get_wqe_mtt_offset(struct mlx5e_rq *rq, u16 wqe_ix) |
993 | { | |
ec8b9981 | 994 | return wqe_ix * ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8); |
7e426671 TT |
995 | } |
996 | ||
f62b8bb8 | 997 | extern const struct ethtool_ops mlx5e_ethtool_ops; |
08fb1dac SM |
998 | #ifdef CONFIG_MLX5_CORE_EN_DCB |
999 | extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops; | |
1000 | int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets); | |
e207b7e9 | 1001 | void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv); |
2a5e7a13 HN |
1002 | void mlx5e_dcbnl_init_app(struct mlx5e_priv *priv); |
1003 | void mlx5e_dcbnl_delete_app(struct mlx5e_priv *priv); | |
08fb1dac SM |
1004 | #endif |
1005 | ||
1cabe6b0 MG |
1006 | #ifndef CONFIG_RFS_ACCEL |
1007 | static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv) | |
1008 | { | |
1009 | return 0; | |
1010 | } | |
1011 | ||
1012 | static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {} | |
45bf454a MG |
1013 | |
1014 | static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv) | |
1015 | { | |
9eb78923 | 1016 | return -EOPNOTSUPP; |
45bf454a MG |
1017 | } |
1018 | ||
1019 | static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv) | |
1020 | { | |
9eb78923 | 1021 | return -EOPNOTSUPP; |
45bf454a | 1022 | } |
1cabe6b0 MG |
1023 | #else |
1024 | int mlx5e_arfs_create_tables(struct mlx5e_priv *priv); | |
1025 | void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv); | |
45bf454a MG |
1026 | int mlx5e_arfs_enable(struct mlx5e_priv *priv); |
1027 | int mlx5e_arfs_disable(struct mlx5e_priv *priv); | |
18c908e4 MG |
1028 | int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
1029 | u16 rxq_index, u32 flow_id); | |
1cabe6b0 MG |
1030 | #endif |
1031 | ||
58d52291 | 1032 | u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev); |
724b2aa1 HHZ |
1033 | int mlx5e_create_tir(struct mlx5_core_dev *mdev, |
1034 | struct mlx5e_tir *tir, u32 *in, int inlen); | |
1035 | void mlx5e_destroy_tir(struct mlx5_core_dev *mdev, | |
1036 | struct mlx5e_tir *tir); | |
b50d292b HHZ |
1037 | int mlx5e_create_mdev_resources(struct mlx5_core_dev *mdev); |
1038 | void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev); | |
b676f653 | 1039 | int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb); |
1afff42c | 1040 | |
bc81b9d3 | 1041 | /* common netdev helpers */ |
8f493ffd SM |
1042 | int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv); |
1043 | ||
1044 | int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv); | |
1045 | void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv); | |
1046 | ||
cb67b832 | 1047 | int mlx5e_create_direct_rqts(struct mlx5e_priv *priv); |
8f493ffd | 1048 | void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv); |
cb67b832 HHZ |
1049 | int mlx5e_create_direct_tirs(struct mlx5e_priv *priv); |
1050 | void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv); | |
8f493ffd SM |
1051 | void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt); |
1052 | ||
50854114 | 1053 | int mlx5e_create_ttc_table(struct mlx5e_priv *priv); |
bc81b9d3 SM |
1054 | void mlx5e_destroy_ttc_table(struct mlx5e_priv *priv); |
1055 | ||
458821c7 FD |
1056 | int mlx5e_create_inner_ttc_table(struct mlx5e_priv *priv); |
1057 | void mlx5e_destroy_inner_ttc_table(struct mlx5e_priv *priv); | |
1058 | ||
5426a0b2 SM |
1059 | int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc, |
1060 | u32 underlay_qpn, u32 *tisn); | |
1061 | void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn); | |
1062 | ||
cb67b832 HHZ |
1063 | int mlx5e_create_tises(struct mlx5e_priv *priv); |
1064 | void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv); | |
1065 | int mlx5e_close(struct net_device *netdev); | |
1066 | int mlx5e_open(struct net_device *netdev); | |
1067 | void mlx5e_update_stats_work(struct work_struct *work); | |
2b029556 | 1068 | u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout); |
cb67b832 | 1069 | |
076b0936 ES |
1070 | /* ethtool helpers */ |
1071 | void mlx5e_ethtool_get_drvinfo(struct mlx5e_priv *priv, | |
1072 | struct ethtool_drvinfo *drvinfo); | |
1073 | void mlx5e_ethtool_get_strings(struct mlx5e_priv *priv, | |
1074 | uint32_t stringset, uint8_t *data); | |
1075 | int mlx5e_ethtool_get_sset_count(struct mlx5e_priv *priv, int sset); | |
1076 | void mlx5e_ethtool_get_ethtool_stats(struct mlx5e_priv *priv, | |
1077 | struct ethtool_stats *stats, u64 *data); | |
1078 | void mlx5e_ethtool_get_ringparam(struct mlx5e_priv *priv, | |
1079 | struct ethtool_ringparam *param); | |
1080 | int mlx5e_ethtool_set_ringparam(struct mlx5e_priv *priv, | |
1081 | struct ethtool_ringparam *param); | |
1082 | void mlx5e_ethtool_get_channels(struct mlx5e_priv *priv, | |
1083 | struct ethtool_channels *ch); | |
1084 | int mlx5e_ethtool_set_channels(struct mlx5e_priv *priv, | |
1085 | struct ethtool_channels *ch); | |
1086 | int mlx5e_ethtool_get_coalesce(struct mlx5e_priv *priv, | |
1087 | struct ethtool_coalesce *coal); | |
1088 | int mlx5e_ethtool_set_coalesce(struct mlx5e_priv *priv, | |
1089 | struct ethtool_coalesce *coal); | |
3844b07e FD |
1090 | int mlx5e_ethtool_get_ts_info(struct mlx5e_priv *priv, |
1091 | struct ethtool_ts_info *info); | |
3ffaabec OG |
1092 | int mlx5e_ethtool_flash_device(struct mlx5e_priv *priv, |
1093 | struct ethtool_flash *flash); | |
076b0936 | 1094 | |
d6c862ba JP |
1095 | int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
1096 | void *cb_priv); | |
717503b9 | 1097 | |
2c3b5bee SM |
1098 | /* mlx5e generic netdev management API */ |
1099 | struct net_device* | |
1100 | mlx5e_create_netdev(struct mlx5_core_dev *mdev, const struct mlx5e_profile *profile, | |
1101 | void *ppriv); | |
1102 | int mlx5e_attach_netdev(struct mlx5e_priv *priv); | |
1103 | void mlx5e_detach_netdev(struct mlx5e_priv *priv); | |
1104 | void mlx5e_destroy_netdev(struct mlx5e_priv *priv); | |
8f493ffd SM |
1105 | void mlx5e_build_nic_params(struct mlx5_core_dev *mdev, |
1106 | struct mlx5e_params *params, | |
1107 | u16 max_channels); | |
fbcb127e | 1108 | u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev); |
1afff42c | 1109 | #endif /* __MLX5_EN_H__ */ |