[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h

/*
 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
#ifndef __MLX5_EN_H__
#define __MLX5_EN_H__

#include <linux/if_vlan.h>
#include <linux/etherdevice.h>
#include <linux/timecounter.h>
#include <linux/net_tstamp.h>
#include <linux/ptp_clock_kernel.h>
#include <linux/mlx5/driver.h>
#include <linux/mlx5/qp.h>
#include <linux/mlx5/cq.h>
#include <linux/mlx5/port.h>
#include <linux/mlx5/vport.h>
#include <linux/mlx5/transobj.h>
#include "wq.h"
#include "mlx5_core.h"

#define MLX5E_MAX_NUM_TC	8

#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE                0x6
#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE                0xa
#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE                0xd

#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE                0x1
#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE                0xa
#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE                0xd

#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10
#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10
#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES                0x80

#define MLX5E_LOG_INDIR_RQT_SIZE       0x7
#define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)
#define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)
#define MLX5E_TX_CQ_POLL_BUDGET        128
#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */
#define MLX5E_SQ_BF_BUDGET             16

#define MLX5E_NUM_MAIN_GROUPS 9

#ifdef CONFIG_MLX5_CORE_EN_DCB
#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
#define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */
#endif

static const char vport_strings[][ETH_GSTRING_LEN] = {
	/* vport statistics */
	"rx_packets",
	"rx_bytes",
	"tx_packets",
	"tx_bytes",
	"rx_error_packets",
	"rx_error_bytes",
	"tx_error_packets",
	"tx_error_bytes",
	"rx_unicast_packets",
	"rx_unicast_bytes",
	"tx_unicast_packets",
	"tx_unicast_bytes",
	"rx_multicast_packets",
	"rx_multicast_bytes",
	"tx_multicast_packets",
	"tx_multicast_bytes",
	"rx_broadcast_packets",
	"rx_broadcast_bytes",
	"tx_broadcast_packets",
	"tx_broadcast_bytes",

	/* SW counters */
	"tso_packets",
	"tso_bytes",
	"lro_packets",
	"lro_bytes",
	"rx_csum_good",
	"rx_csum_none",
	"rx_csum_sw",
	"tx_csum_offload",
	"tx_queue_stopped",
	"tx_queue_wake",
	"tx_queue_dropped",
	"rx_wqe_err",
};

struct mlx5e_vport_stats {
	/* HW counters */
	u64 rx_packets;
	u64 rx_bytes;
	u64 tx_packets;
	u64 tx_bytes;
	u64 rx_error_packets;
	u64 rx_error_bytes;
	u64 tx_error_packets;
	u64 tx_error_bytes;
	u64 rx_unicast_packets;
	u64 rx_unicast_bytes;
	u64 tx_unicast_packets;
	u64 tx_unicast_bytes;
	u64 rx_multicast_packets;
	u64 rx_multicast_bytes;
	u64 tx_multicast_packets;
	u64 tx_multicast_bytes;
	u64 rx_broadcast_packets;
	u64 rx_broadcast_bytes;
	u64 tx_broadcast_packets;
	u64 tx_broadcast_bytes;

	/* SW counters */
	u64 tso_packets;
	u64 tso_bytes;
	u64 lro_packets;
	u64 lro_bytes;
	u64 rx_csum_good;
	u64 rx_csum_none;
	u64 rx_csum_sw;
	u64 tx_csum_offload;
	u64 tx_queue_stopped;
	u64 tx_queue_wake;
	u64 tx_queue_dropped;
	u64 rx_wqe_err;

#define NUM_VPORT_COUNTERS     32
};

static const char pport_strings[][ETH_GSTRING_LEN] = {
	/* IEEE802.3 counters */
	"frames_tx",
	"frames_rx",
	"check_seq_err",
	"alignment_err",
	"octets_tx",
	"octets_received",
	"multicast_xmitted",
	"broadcast_xmitted",
	"multicast_rx",
	"broadcast_rx",
	"in_range_len_errors",
	"out_of_range_len",
	"too_long_errors",
	"symbol_err",
	"mac_control_tx",
	"mac_control_rx",
	"unsupported_op_rx",
	"pause_ctrl_rx",
	"pause_ctrl_tx",

	/* RFC2863 counters */
	"in_octets",
	"in_ucast_pkts",
	"in_discards",
	"in_errors",
	"in_unknown_protos",
	"out_octets",
	"out_ucast_pkts",
	"out_discards",
	"out_errors",
	"in_multicast_pkts",
	"in_broadcast_pkts",
	"out_multicast_pkts",
	"out_broadcast_pkts",

	/* RFC2819 counters */
	"drop_events",
	"octets",
	"pkts",
	"broadcast_pkts",
	"multicast_pkts",
	"crc_align_errors",
	"undersize_pkts",
	"oversize_pkts",
	"fragments",
	"jabbers",
	"collisions",
	"p64octets",
	"p65to127octets",
	"p128to255octets",
	"p256to511octets",
	"p512to1023octets",
	"p1024to1518octets",
	"p1519to2047octets",
	"p2048to4095octets",
	"p4096to8191octets",
	"p8192to10239octets",
};

#define NUM_IEEE_802_3_COUNTERS		19
#define NUM_RFC_2863_COUNTERS		13
#define NUM_RFC_2819_COUNTERS		21
#define NUM_PPORT_COUNTERS		(NUM_IEEE_802_3_COUNTERS + \
					 NUM_RFC_2863_COUNTERS + \
					 NUM_RFC_2819_COUNTERS)

struct mlx5e_pport_stats {
	__be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
	__be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
	__be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
};

static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
	"packets",
	"csum_none",
	"csum_sw",
	"lro_packets",
	"lro_bytes",
	"wqe_err"
};

struct mlx5e_rq_stats {
	u64 packets;
	u64 csum_none;
	u64 csum_sw;
	u64 lro_packets;
	u64 lro_bytes;
	u64 wqe_err;
#define NUM_RQ_STATS 6
};

static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
	"packets",
	"tso_packets",
	"tso_bytes",
	"csum_offload_none",
	"stopped",
	"wake",
	"dropped",
	"nop"
};

struct mlx5e_sq_stats {
	u64 packets;
	u64 tso_packets;
	u64 tso_bytes;
	u64 csum_offload_none;
	u64 stopped;
	u64 wake;
	u64 dropped;
	u64 nop;
#define NUM_SQ_STATS 8
};

struct mlx5e_stats {
	struct mlx5e_vport_stats   vport;
	struct mlx5e_pport_stats   pport;
};

struct mlx5e_params {
	u8  log_sq_size;
	u8  log_rq_size;
	u16 num_channels;
	u8  num_tc;
	u16 rx_cq_moderation_usec;
	u16 rx_cq_moderation_pkts;
	u16 tx_cq_moderation_usec;
	u16 tx_cq_moderation_pkts;
	u16 min_rx_wqes;
	bool lro_en;
	u32 lro_wqe_sz;
	u16 tx_max_inline;
	u8  rss_hfunc;
	u8  toeplitz_hash_key[40];
	u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
#ifdef CONFIG_MLX5_CORE_EN_DCB
	struct ieee_ets ets;
#endif
};

struct mlx5e_tstamp {
	rwlock_t                   lock;
	struct cyclecounter        cycles;
	struct timecounter         clock;
	struct hwtstamp_config     hwtstamp_config;
	u32                        nominal_c_mult;
	unsigned long              overflow_period;
	struct delayed_work        overflow_work;
	struct mlx5_core_dev      *mdev;
	struct ptp_clock          *ptp;
	struct ptp_clock_info      ptp_info;
};

enum {
	MLX5E_RQ_STATE_POST_WQES_ENABLE,
};

enum cq_flags {
	MLX5E_CQ_HAS_CQES = 1,
};

struct mlx5e_cq {
	/* data path - accessed per cqe */
	struct mlx5_cqwq           wq;
	unsigned long              flags;

	/* data path - accessed per napi poll */
	struct napi_struct        *napi;
	struct mlx5_core_cq        mcq;
	struct mlx5e_channel      *channel;
	struct mlx5e_priv         *priv;

	/* control */
	struct mlx5_wq_ctrl        wq_ctrl;
} ____cacheline_aligned_in_smp;

struct mlx5e_rq {
	/* data path */
	struct mlx5_wq_ll      wq;
	u32                    wqe_sz;
	struct sk_buff       **skb;

	struct device         *pdev;
	struct net_device     *netdev;
	struct mlx5e_tstamp   *tstamp;
	struct mlx5e_rq_stats  stats;
	struct mlx5e_cq        cq;

	unsigned long          state;
	int                    ix;

	/* control */
	struct mlx5_wq_ctrl    wq_ctrl;
	u32                    rqn;
	struct mlx5e_channel  *channel;
	struct mlx5e_priv     *priv;
} ____cacheline_aligned_in_smp;

struct mlx5e_tx_wqe_info {
	u32 num_bytes;
	u8  num_wqebbs;
	u8  num_dma;
};

enum mlx5e_dma_map_type {
	MLX5E_DMA_MAP_SINGLE,
	MLX5E_DMA_MAP_PAGE
};

struct mlx5e_sq_dma {
	dma_addr_t              addr;
	u32                     size;
	enum mlx5e_dma_map_type type;
};

enum {
	MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
};

struct mlx5e_sq {
	/* data path */

	/* dirtied @completion */
	u16                        cc;
	u32                        dma_fifo_cc;

	/* dirtied @xmit */
	u16                        pc ____cacheline_aligned_in_smp;
	u32                        dma_fifo_pc;
	u16                        bf_offset;
	u16                        prev_cc;
	u8                         bf_budget;
	struct mlx5e_sq_stats      stats;

	struct mlx5e_cq            cq;

	/* pointers to per packet info: write@xmit, read@completion */
	struct sk_buff           **skb;
	struct mlx5e_sq_dma       *dma_fifo;
	struct mlx5e_tx_wqe_info  *wqe_info;

	/* read only */
	struct mlx5_wq_cyc         wq;
	u32                        dma_fifo_mask;
	void __iomem              *uar_map;
	void __iomem              *uar_bf_map;
	struct netdev_queue       *txq;
	u32                        sqn;
	u16                        bf_buf_size;
	u16                        max_inline;
	u16                        edge;
	struct device             *pdev;
	struct mlx5e_tstamp       *tstamp;
	__be32                     mkey_be;
	unsigned long              state;

	/* control path */
	struct mlx5_wq_ctrl        wq_ctrl;
	struct mlx5_uar            uar;
	struct mlx5e_channel      *channel;
	int                        tc;
} ____cacheline_aligned_in_smp;

static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
{
	return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
		(sq->cc  == sq->pc));
}

enum channel_flags {
	MLX5E_CHANNEL_NAPI_SCHED = 1,
};

struct mlx5e_channel {
	/* data path */
	struct mlx5e_rq            rq;
	struct mlx5e_sq            sq[MLX5E_MAX_NUM_TC];
	struct napi_struct         napi;
	struct device             *pdev;
	struct net_device         *netdev;
	__be32                     mkey_be;
	u8                         num_tc;
	unsigned long              flags;

	/* control */
	struct mlx5e_priv         *priv;
	int                        ix;
	int                        cpu;
};

enum mlx5e_traffic_types {
	MLX5E_TT_IPV4_TCP,
	MLX5E_TT_IPV6_TCP,
	MLX5E_TT_IPV4_UDP,
	MLX5E_TT_IPV6_UDP,
	MLX5E_TT_IPV4_IPSEC_AH,
	MLX5E_TT_IPV6_IPSEC_AH,
	MLX5E_TT_IPV4_IPSEC_ESP,
	MLX5E_TT_IPV6_IPSEC_ESP,
	MLX5E_TT_IPV4,
	MLX5E_TT_IPV6,
	MLX5E_TT_ANY,
	MLX5E_NUM_TT,
};

enum mlx5e_rqt_ix {
	MLX5E_INDIRECTION_RQT,
	MLX5E_SINGLE_RQ_RQT,
	MLX5E_NUM_RQT,
};

struct mlx5e_eth_addr_info {
	u8  addr[ETH_ALEN + 2];
	u32 tt_vec;
	struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
};

#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)

struct mlx5e_eth_addr_db {
	struct hlist_head          netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
	struct hlist_head          netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
	struct mlx5e_eth_addr_info broadcast;
	struct mlx5e_eth_addr_info allmulti;
	struct mlx5e_eth_addr_info promisc;
	bool                       broadcast_enabled;
	bool                       allmulti_enabled;
	bool                       promisc_enabled;
};

enum {
	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
	MLX5E_STATE_OPENED,
	MLX5E_STATE_DESTROYING,
};

struct mlx5e_vlan_db {
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	struct mlx5_flow_rule	*active_vlans_rule[VLAN_N_VID];
	struct mlx5_flow_rule	*untagged_rule;
	struct mlx5_flow_rule	*any_vlan_rule;
	bool          filter_disabled;
};

struct mlx5e_flow_table {
	int num_groups;
	struct mlx5_flow_table		*t;
	struct mlx5_flow_group		**g;
};

struct mlx5e_flow_tables {
	struct mlx5_flow_namespace	*ns;
	struct mlx5e_flow_table		vlan;
	struct mlx5e_flow_table		main;
};

struct mlx5e_priv {
	/* priv data path fields - start */
	struct mlx5e_sq            **txq_to_sq_map;
	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
	/* priv data path fields - end */

	unsigned long              state;
	struct mutex               state_lock; /* Protects Interface state */
	struct mlx5_uar            cq_uar;
	u32                        pdn;
	u32                        tdn;
	struct mlx5_core_mr        mr;
	struct mlx5e_rq            drop_rq;

	struct mlx5e_channel     **channel;
	u32                        tisn[MLX5E_MAX_NUM_TC];
	u32                        rqtn[MLX5E_NUM_RQT];
	u32                        tirn[MLX5E_NUM_TT];

	struct mlx5e_flow_tables   fts;
	struct mlx5e_eth_addr_db   eth_addr;
	struct mlx5e_vlan_db       vlan;

	struct mlx5e_params        params;
	spinlock_t                 async_events_spinlock; /* sync hw events */
	struct work_struct         update_carrier_work;
	struct work_struct         set_rx_mode_work;
	struct delayed_work        update_stats_work;

	struct mlx5_core_dev      *mdev;
	struct net_device         *netdev;
	struct mlx5e_stats         stats;
	struct mlx5e_tstamp        tstamp;
};

#define MLX5E_NET_IP_ALIGN 2

struct mlx5e_tx_wqe {
	struct mlx5_wqe_ctrl_seg ctrl;
	struct mlx5_wqe_eth_seg  eth;
};

struct mlx5e_rx_wqe {
	struct mlx5_wqe_srq_next_seg  next;
	struct mlx5_wqe_data_seg      data;
};

enum mlx5e_link_mode {
	MLX5E_1000BASE_CX_SGMII	 = 0,
	MLX5E_1000BASE_KX	 = 1,
	MLX5E_10GBASE_CX4	 = 2,
	MLX5E_10GBASE_KX4	 = 3,
	MLX5E_10GBASE_KR	 = 4,
	MLX5E_20GBASE_KR2	 = 5,
	MLX5E_40GBASE_CR4	 = 6,
	MLX5E_40GBASE_KR4	 = 7,
	MLX5E_56GBASE_R4	 = 8,
	MLX5E_10GBASE_CR	 = 12,
	MLX5E_10GBASE_SR	 = 13,
	MLX5E_10GBASE_ER	 = 14,
	MLX5E_40GBASE_SR4	 = 15,
	MLX5E_40GBASE_LR4	 = 16,
	MLX5E_100GBASE_CR4	 = 20,
	MLX5E_100GBASE_SR4	 = 21,
	MLX5E_100GBASE_KR4	 = 22,
	MLX5E_100GBASE_LR4	 = 23,
	MLX5E_100BASE_TX	 = 24,
	MLX5E_100BASE_T		 = 25,
	MLX5E_10GBASE_T		 = 26,
	MLX5E_25GBASE_CR	 = 27,
	MLX5E_25GBASE_KR	 = 28,
	MLX5E_25GBASE_SR	 = 29,
	MLX5E_50GBASE_CR2	 = 30,
	MLX5E_50GBASE_KR2	 = 31,
	MLX5E_LINK_MODES_NUMBER,
};

#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)

void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
		       void *accel_priv, select_queue_fallback_t fallback);
netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);

void mlx5e_completion_event(struct mlx5_core_cq *mcq);
void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
int mlx5e_napi_poll(struct napi_struct *napi, int budget);
bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);

void mlx5e_update_stats(struct mlx5e_priv *priv);

int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
void mlx5e_set_rx_mode_work(struct work_struct *work);

void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
			struct skb_shared_hwtstamps *hwts);
void mlx5e_timestamp_init(struct mlx5e_priv *priv);
void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);

int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
			  u16 vid);
int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
			   u16 vid);
void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);

int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);

int mlx5e_open_locked(struct net_device *netdev);
int mlx5e_close_locked(struct net_device *netdev);

static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
				      struct mlx5e_tx_wqe *wqe, int bf_sz)
{
	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;

	/* ensure wqe is visible to device before updating doorbell record */
	dma_wmb();

	*sq->wq.db = cpu_to_be32(sq->pc);

	/* ensure doorbell record is visible to device before ringing the
	 * doorbell
	 */
	wmb();

	if (bf_sz) {
		__iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);

		/* flush the write-combining mapped buffer */
		wmb();

	} else {
		mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
	}

	sq->bf_offset ^= sq->bf_buf_size;
}

static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
{
	struct mlx5_core_cq *mcq;

	mcq = &cq->mcq;
	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
}

static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
{
	return min_t(int, mdev->priv.eq_table.num_comp_vectors,
		     MLX5E_MAX_NUM_CHANNELS);
}

extern const struct ethtool_ops mlx5e_ethtool_ops;
#ifdef CONFIG_MLX5_CORE_EN_DCB
extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
#endif

u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);

#endif /* __MLX5_EN_H__ */
Commit	Line	Data
f62b8bb8	1	/*
1afff42c	2	* Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
f62b8bb8 AV	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
1afff42c MF	32	#ifndef __MLX5_EN_H__
1afff42c MF	33	#define __MLX5_EN_H__
f62b8bb8 AV	34
	35	#include <linux/if_vlan.h>
	36	#include <linux/etherdevice.h>
ef9814de EBE	37	#include <linux/timecounter.h>
ef9814de EBE	38	#include <linux/net_tstamp.h>
3d8c38af	39	#include <linux/ptp_clock_kernel.h>
f62b8bb8 AV	40	#include <linux/mlx5/driver.h>
	41	#include <linux/mlx5/qp.h>
	42	#include <linux/mlx5/cq.h>
ada68c31	43	#include <linux/mlx5/port.h>
d18a9470	44	#include <linux/mlx5/vport.h>
8d7f9ecb	45	#include <linux/mlx5/transobj.h>
f62b8bb8	46	#include "wq.h"
f62b8bb8 AV	47	#include "mlx5_core.h"
	48
	49	#define MLX5E_MAX_NUM_TC 8
	50
e842b100	51	#define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
f62b8bb8 AV	52	#define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
	53	#define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
	54
e842b100	55	#define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
f62b8bb8 AV	56	#define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
	57	#define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
	58
d9a40271	59	#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
f62b8bb8 AV	60	#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
	61	#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
	62	#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
	63	#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
	64	#define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
f62b8bb8	65
936896e9 AS	66	#define MLX5E_LOG_INDIR_RQT_SIZE 0x7
	67	#define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
	68	#define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
f62b8bb8 AV	69	#define MLX5E_TX_CQ_POLL_BUDGET 128
f62b8bb8 AV	70	#define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
88a85f99	71	#define MLX5E_SQ_BF_BUDGET 16
f62b8bb8	72
86d722ad MG	73	#define MLX5E_NUM_MAIN_GROUPS 9
86d722ad MG	74
08fb1dac SM	75	#ifdef CONFIG_MLX5_CORE_EN_DCB
	76	#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
	77	#define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
	78	#endif
	79
f62b8bb8 AV	80	static const char vport_strings[][ETH_GSTRING_LEN] = {
	81	/* vport statistics */
	82	"rx_packets",
	83	"rx_bytes",
	84	"tx_packets",
	85	"tx_bytes",
	86	"rx_error_packets",
	87	"rx_error_bytes",
	88	"tx_error_packets",
	89	"tx_error_bytes",
	90	"rx_unicast_packets",
	91	"rx_unicast_bytes",
	92	"tx_unicast_packets",
	93	"tx_unicast_bytes",
	94	"rx_multicast_packets",
	95	"rx_multicast_bytes",
	96	"tx_multicast_packets",
	97	"tx_multicast_bytes",
	98	"rx_broadcast_packets",
	99	"rx_broadcast_bytes",
	100	"tx_broadcast_packets",
	101	"tx_broadcast_bytes",
	102
	103	/* SW counters */
	104	"tso_packets",
	105	"tso_bytes",
	106	"lro_packets",
	107	"lro_bytes",
	108	"rx_csum_good",
	109	"rx_csum_none",
bbceefce	110	"rx_csum_sw",
f62b8bb8 AV	111	"tx_csum_offload",
	112	"tx_queue_stopped",
	113	"tx_queue_wake",
	114	"tx_queue_dropped",
	115	"rx_wqe_err",
	116	};
	117
	118	struct mlx5e_vport_stats {
	119	/* HW counters */
	120	u64 rx_packets;
	121	u64 rx_bytes;
	122	u64 tx_packets;
	123	u64 tx_bytes;
	124	u64 rx_error_packets;
	125	u64 rx_error_bytes;
	126	u64 tx_error_packets;
	127	u64 tx_error_bytes;
	128	u64 rx_unicast_packets;
	129	u64 rx_unicast_bytes;
	130	u64 tx_unicast_packets;
	131	u64 tx_unicast_bytes;
	132	u64 rx_multicast_packets;
	133	u64 rx_multicast_bytes;
	134	u64 tx_multicast_packets;
	135	u64 tx_multicast_bytes;
	136	u64 rx_broadcast_packets;
	137	u64 rx_broadcast_bytes;
	138	u64 tx_broadcast_packets;
	139	u64 tx_broadcast_bytes;
	140
	141	/* SW counters */
	142	u64 tso_packets;
	143	u64 tso_bytes;
	144	u64 lro_packets;
	145	u64 lro_bytes;
	146	u64 rx_csum_good;
	147	u64 rx_csum_none;
bbceefce	148	u64 rx_csum_sw;
f62b8bb8 AV	149	u64 tx_csum_offload;
	150	u64 tx_queue_stopped;
	151	u64 tx_queue_wake;
	152	u64 tx_queue_dropped;
	153	u64 rx_wqe_err;
	154
bbceefce	155	#define NUM_VPORT_COUNTERS 32
f62b8bb8 AV	156	};
f62b8bb8 AV	157
efea389d GP	158	static const char pport_strings[][ETH_GSTRING_LEN] = {
	159	/* IEEE802.3 counters */
	160	"frames_tx",
	161	"frames_rx",
	162	"check_seq_err",
	163	"alignment_err",
	164	"octets_tx",
	165	"octets_received",
	166	"multicast_xmitted",
	167	"broadcast_xmitted",
	168	"multicast_rx",
	169	"broadcast_rx",
	170	"in_range_len_errors",
	171	"out_of_range_len",
	172	"too_long_errors",
	173	"symbol_err",
	174	"mac_control_tx",
	175	"mac_control_rx",
	176	"unsupported_op_rx",
	177	"pause_ctrl_rx",
	178	"pause_ctrl_tx",
	179
	180	/* RFC2863 counters */
	181	"in_octets",
	182	"in_ucast_pkts",
	183	"in_discards",
	184	"in_errors",
	185	"in_unknown_protos",
	186	"out_octets",
	187	"out_ucast_pkts",
	188	"out_discards",
	189	"out_errors",
	190	"in_multicast_pkts",
	191	"in_broadcast_pkts",
	192	"out_multicast_pkts",
	193	"out_broadcast_pkts",
	194
	195	/* RFC2819 counters */
	196	"drop_events",
	197	"octets",
	198	"pkts",
	199	"broadcast_pkts",
	200	"multicast_pkts",
	201	"crc_align_errors",
	202	"undersize_pkts",
	203	"oversize_pkts",
	204	"fragments",
	205	"jabbers",
	206	"collisions",
	207	"p64octets",
	208	"p65to127octets",
	209	"p128to255octets",
	210	"p256to511octets",
	211	"p512to1023octets",
	212	"p1024to1518octets",
	213	"p1519to2047octets",
	214	"p2048to4095octets",
	215	"p4096to8191octets",
	216	"p8192to10239octets",
	217	};
	218
	219	#define NUM_IEEE_802_3_COUNTERS 19
	220	#define NUM_RFC_2863_COUNTERS 13
	221	#define NUM_RFC_2819_COUNTERS 21
222	#define NUM_PPORT_COUNTERS (NUM_IEEE_802_3_COUNTERS + \
223	NUM_RFC_2863_COUNTERS + \
224	NUM_RFC_2819_COUNTERS)
225
226	struct mlx5e_pport_stats {
227	__be64 IEEE_802_3_counters[NUM_IEEE_802_3_COUNTERS];
228	__be64 RFC_2863_counters[NUM_RFC_2863_COUNTERS];
229	__be64 RFC_2819_counters[NUM_RFC_2819_COUNTERS];
230	};
231
f62b8bb8 AV	232	static const char rq_stats_strings[][ETH_GSTRING_LEN] = {
	233	"packets",
	234	"csum_none",
bbceefce	235	"csum_sw",
f62b8bb8 AV	236	"lro_packets",
	237	"lro_bytes",
	238	"wqe_err"
	239	};
	240
	241	struct mlx5e_rq_stats {
	242	u64 packets;
	243	u64 csum_none;
bbceefce	244	u64 csum_sw;
f62b8bb8 AV	245	u64 lro_packets;
	246	u64 lro_bytes;
	247	u64 wqe_err;
bbceefce	248	#define NUM_RQ_STATS 6
f62b8bb8 AV	249	};
	250
	251	static const char sq_stats_strings[][ETH_GSTRING_LEN] = {
	252	"packets",
	253	"tso_packets",
	254	"tso_bytes",
	255	"csum_offload_none",
	256	"stopped",
	257	"wake",
	258	"dropped",
	259	"nop"
	260	};
	261
	262	struct mlx5e_sq_stats {
	263	u64 packets;
	264	u64 tso_packets;
	265	u64 tso_bytes;
	266	u64 csum_offload_none;
	267	u64 stopped;
	268	u64 wake;
	269	u64 dropped;
	270	u64 nop;
	271	#define NUM_SQ_STATS 8
	272	};
	273
	274	struct mlx5e_stats {
	275	struct mlx5e_vport_stats vport;
efea389d	276	struct mlx5e_pport_stats pport;
f62b8bb8 AV	277	};
	278
	279	struct mlx5e_params {
	280	u8 log_sq_size;
	281	u8 log_rq_size;
	282	u16 num_channels;
f62b8bb8 AV	283	u8 num_tc;
	284	u16 rx_cq_moderation_usec;
	285	u16 rx_cq_moderation_pkts;
	286	u16 tx_cq_moderation_usec;
	287	u16 tx_cq_moderation_pkts;
	288	u16 min_rx_wqes;
f62b8bb8 AV	289	bool lro_en;
f62b8bb8 AV	290	u32 lro_wqe_sz;
58d52291	291	u16 tx_max_inline;
2d75b2bc AS	292	u8 rss_hfunc;
	293	u8 toeplitz_hash_key[40];
	294	u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
08fb1dac SM	295	#ifdef CONFIG_MLX5_CORE_EN_DCB
	296	struct ieee_ets ets;
	297	#endif
f62b8bb8 AV	298	};
f62b8bb8 AV	299
ef9814de EBE	300	struct mlx5e_tstamp {
	301	rwlock_t lock;
	302	struct cyclecounter cycles;
	303	struct timecounter clock;
	304	struct hwtstamp_config hwtstamp_config;
	305	u32 nominal_c_mult;
	306	unsigned long overflow_period;
	307	struct delayed_work overflow_work;
	308	struct mlx5_core_dev *mdev;
3d8c38af EBE	309	struct ptp_clock *ptp;
3d8c38af EBE	310	struct ptp_clock_info ptp_info;
ef9814de EBE	311	};
ef9814de EBE	312
f62b8bb8 AV	313	enum {
	314	MLX5E_RQ_STATE_POST_WQES_ENABLE,
	315	};
	316
	317	enum cq_flags {
	318	MLX5E_CQ_HAS_CQES = 1,
	319	};
	320
	321	struct mlx5e_cq {
	322	/* data path - accessed per cqe */
	323	struct mlx5_cqwq wq;
f62b8bb8 AV	324	unsigned long flags;
	325
	326	/* data path - accessed per napi poll */
	327	struct napi_struct *napi;
	328	struct mlx5_core_cq mcq;
	329	struct mlx5e_channel *channel;
50cfa25a	330	struct mlx5e_priv *priv;
f62b8bb8 AV	331
	332	/* control */
	333	struct mlx5_wq_ctrl wq_ctrl;
	334	} ____cacheline_aligned_in_smp;
	335
	336	struct mlx5e_rq {
	337	/* data path */
	338	struct mlx5_wq_ll wq;
	339	u32 wqe_sz;
	340	struct sk_buff **skb;
	341
	342	struct device *pdev;
	343	struct net_device *netdev;
ef9814de	344	struct mlx5e_tstamp *tstamp;
f62b8bb8 AV	345	struct mlx5e_rq_stats stats;
	346	struct mlx5e_cq cq;
	347
	348	unsigned long state;
	349	int ix;
	350
	351	/* control */
	352	struct mlx5_wq_ctrl wq_ctrl;
	353	u32 rqn;
	354	struct mlx5e_channel *channel;
50cfa25a	355	struct mlx5e_priv *priv;
f62b8bb8 AV	356	} ____cacheline_aligned_in_smp;
f62b8bb8 AV	357
34802a42	358	struct mlx5e_tx_wqe_info {
f62b8bb8 AV	359	u32 num_bytes;
	360	u8 num_wqebbs;
	361	u8 num_dma;
	362	};
	363
d4e28cbd AS	364	enum mlx5e_dma_map_type {
	365	MLX5E_DMA_MAP_SINGLE,
	366	MLX5E_DMA_MAP_PAGE
	367	};
	368
f62b8bb8	369	struct mlx5e_sq_dma {
d4e28cbd AS	370	dma_addr_t addr;
	371	u32 size;
	372	enum mlx5e_dma_map_type type;
f62b8bb8 AV	373	};
	374
	375	enum {
	376	MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
	377	};
	378
	379	struct mlx5e_sq {
	380	/* data path */
	381
	382	/* dirtied @completion */
	383	u16 cc;
	384	u32 dma_fifo_cc;
	385
	386	/* dirtied @xmit */
	387	u16 pc ____cacheline_aligned_in_smp;
	388	u32 dma_fifo_pc;
88a85f99 AS	389	u16 bf_offset;
	390	u16 prev_cc;
	391	u8 bf_budget;
f62b8bb8 AV	392	struct mlx5e_sq_stats stats;
	393
	394	struct mlx5e_cq cq;
	395
	396	/* pointers to per packet info: write@xmit, read@completion */
	397	struct sk_buff **skb;
	398	struct mlx5e_sq_dma *dma_fifo;
34802a42	399	struct mlx5e_tx_wqe_info *wqe_info;
f62b8bb8 AV	400
	401	/* read only */
	402	struct mlx5_wq_cyc wq;
	403	u32 dma_fifo_mask;
	404	void __iomem *uar_map;
88a85f99	405	void __iomem *uar_bf_map;
f62b8bb8 AV	406	struct netdev_queue *txq;
f62b8bb8 AV	407	u32 sqn;
88a85f99	408	u16 bf_buf_size;
12be4b21 SM	409	u16 max_inline;
12be4b21 SM	410	u16 edge;
f62b8bb8	411	struct device *pdev;
ef9814de	412	struct mlx5e_tstamp *tstamp;
f62b8bb8 AV	413	__be32 mkey_be;
	414	unsigned long state;
	415
	416	/* control path */
	417	struct mlx5_wq_ctrl wq_ctrl;
	418	struct mlx5_uar uar;
	419	struct mlx5e_channel *channel;
	420	int tc;
	421	} ____cacheline_aligned_in_smp;
	422
	423	static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
	424	{
	425	return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) \|\|
	426	(sq->cc == sq->pc));
	427	}
	428
	429	enum channel_flags {
	430	MLX5E_CHANNEL_NAPI_SCHED = 1,
	431	};
	432
	433	struct mlx5e_channel {
	434	/* data path */
	435	struct mlx5e_rq rq;
	436	struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
	437	struct napi_struct napi;
	438	struct device *pdev;
	439	struct net_device *netdev;
	440	__be32 mkey_be;
	441	u8 num_tc;
	442	unsigned long flags;
	443
	444	/* control */
	445	struct mlx5e_priv *priv;
	446	int ix;
	447	int cpu;
	448	};
	449
	450	enum mlx5e_traffic_types {
5a6f8aef AS	451	MLX5E_TT_IPV4_TCP,
	452	MLX5E_TT_IPV6_TCP,
	453	MLX5E_TT_IPV4_UDP,
	454	MLX5E_TT_IPV6_UDP,
a741749f AS	455	MLX5E_TT_IPV4_IPSEC_AH,
	456	MLX5E_TT_IPV6_IPSEC_AH,
	457	MLX5E_TT_IPV4_IPSEC_ESP,
	458	MLX5E_TT_IPV6_IPSEC_ESP,
5a6f8aef AS	459	MLX5E_TT_IPV4,
	460	MLX5E_TT_IPV6,
	461	MLX5E_TT_ANY,
	462	MLX5E_NUM_TT,
f62b8bb8 AV	463	};
f62b8bb8 AV	464
4cbeaff5 AS	465	enum mlx5e_rqt_ix {
	466	MLX5E_INDIRECTION_RQT,
	467	MLX5E_SINGLE_RQ_RQT,
	468	MLX5E_NUM_RQT,
f62b8bb8 AV	469	};
	470
	471	struct mlx5e_eth_addr_info {
	472	u8 addr[ETH_ALEN + 2];
	473	u32 tt_vec;
86d722ad	474	struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
f62b8bb8 AV	475	};
	476
	477	#define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
	478
	479	struct mlx5e_eth_addr_db {
	480	struct hlist_head netdev_uc[MLX5E_ETH_ADDR_HASH_SIZE];
	481	struct hlist_head netdev_mc[MLX5E_ETH_ADDR_HASH_SIZE];
	482	struct mlx5e_eth_addr_info broadcast;
	483	struct mlx5e_eth_addr_info allmulti;
	484	struct mlx5e_eth_addr_info promisc;
	485	bool broadcast_enabled;
	486	bool allmulti_enabled;
	487	bool promisc_enabled;
	488	};
	489
	490	enum {
	491	MLX5E_STATE_ASYNC_EVENTS_ENABLE,
	492	MLX5E_STATE_OPENED,
9b37b07f	493	MLX5E_STATE_DESTROYING,
f62b8bb8 AV	494	};
	495
	496	struct mlx5e_vlan_db {
aad9e6e4	497	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
86d722ad MG	498	struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
	499	struct mlx5_flow_rule *untagged_rule;
	500	struct mlx5_flow_rule *any_vlan_rule;
f62b8bb8 AV	501	bool filter_disabled;
	502	};
	503
	504	struct mlx5e_flow_table {
86d722ad MG	505	int num_groups;
	506	struct mlx5_flow_table *t;
	507	struct mlx5_flow_group **g;
	508	};
	509
	510	struct mlx5e_flow_tables {
	511	struct mlx5_flow_namespace *ns;
	512	struct mlx5e_flow_table vlan;
	513	struct mlx5e_flow_table main;
f62b8bb8 AV	514	};
	515
	516	struct mlx5e_priv {
	517	/* priv data path fields - start */
03289b88	518	struct mlx5e_sq **txq_to_sq_map;
5283af89	519	int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
f62b8bb8 AV	520	/* priv data path fields - end */
	521
	522	unsigned long state;
	523	struct mutex state_lock; /* Protects Interface state */
	524	struct mlx5_uar cq_uar;
	525	u32 pdn;
3191e05f	526	u32 tdn;
f62b8bb8	527	struct mlx5_core_mr mr;
50cfa25a	528	struct mlx5e_rq drop_rq;
f62b8bb8 AV	529
	530	struct mlx5e_channel **channel;
	531	u32 tisn[MLX5E_MAX_NUM_TC];
4cbeaff5	532	u32 rqtn[MLX5E_NUM_RQT];
f62b8bb8 AV	533	u32 tirn[MLX5E_NUM_TT];
f62b8bb8 AV	534
86d722ad	535	struct mlx5e_flow_tables fts;
f62b8bb8 AV	536	struct mlx5e_eth_addr_db eth_addr;
	537	struct mlx5e_vlan_db vlan;
	538
	539	struct mlx5e_params params;
	540	spinlock_t async_events_spinlock; /* sync hw events */
	541	struct work_struct update_carrier_work;
	542	struct work_struct set_rx_mode_work;
	543	struct delayed_work update_stats_work;
	544
	545	struct mlx5_core_dev *mdev;
	546	struct net_device *netdev;
	547	struct mlx5e_stats stats;
ef9814de	548	struct mlx5e_tstamp tstamp;
f62b8bb8 AV	549	};
	550
	551	#define MLX5E_NET_IP_ALIGN 2
	552
	553	struct mlx5e_tx_wqe {
	554	struct mlx5_wqe_ctrl_seg ctrl;
	555	struct mlx5_wqe_eth_seg eth;
	556	};
	557
	558	struct mlx5e_rx_wqe {
	559	struct mlx5_wqe_srq_next_seg next;
	560	struct mlx5_wqe_data_seg data;
	561	};
	562
	563	enum mlx5e_link_mode {
	564	MLX5E_1000BASE_CX_SGMII = 0,
	565	MLX5E_1000BASE_KX = 1,
	566	MLX5E_10GBASE_CX4 = 2,
	567	MLX5E_10GBASE_KX4 = 3,
	568	MLX5E_10GBASE_KR = 4,
	569	MLX5E_20GBASE_KR2 = 5,
	570	MLX5E_40GBASE_CR4 = 6,
	571	MLX5E_40GBASE_KR4 = 7,
	572	MLX5E_56GBASE_R4 = 8,
	573	MLX5E_10GBASE_CR = 12,
	574	MLX5E_10GBASE_SR = 13,
	575	MLX5E_10GBASE_ER = 14,
	576	MLX5E_40GBASE_SR4 = 15,
	577	MLX5E_40GBASE_LR4 = 16,
	578	MLX5E_100GBASE_CR4 = 20,
	579	MLX5E_100GBASE_SR4 = 21,
	580	MLX5E_100GBASE_KR4 = 22,
	581	MLX5E_100GBASE_LR4 = 23,
	582	MLX5E_100BASE_TX = 24,
	583	MLX5E_100BASE_T = 25,
	584	MLX5E_10GBASE_T = 26,
	585	MLX5E_25GBASE_CR = 27,
	586	MLX5E_25GBASE_KR = 28,
	587	MLX5E_25GBASE_SR = 29,
	588	MLX5E_50GBASE_CR2 = 30,
	589	MLX5E_50GBASE_KR2 = 31,
	590	MLX5E_LINK_MODES_NUMBER,
	591	};
	592
	593	#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
	594
12be4b21	595	void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
f62b8bb8 AV	596	u16 mlx5e_select_queue(struct net_device dev, struct sk_buff skb,
	597	void *accel_priv, select_queue_fallback_t fallback);
	598	netdev_tx_t mlx5e_xmit(struct sk_buff skb, struct net_device dev);
f62b8bb8 AV	599
	600	void mlx5e_completion_event(struct mlx5_core_cq *mcq);
	601	void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
	602	int mlx5e_napi_poll(struct napi_struct *napi, int budget);
	603	bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq);
44fb6fbb	604	int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
f62b8bb8 AV	605	bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
	606	struct mlx5_cqe64 mlx5e_get_cqe(struct mlx5e_cq cq);
	607
	608	void mlx5e_update_stats(struct mlx5e_priv *priv);
	609
40ab6a6e AS	610	int mlx5e_create_flow_tables(struct mlx5e_priv *priv);
40ab6a6e AS	611	void mlx5e_destroy_flow_tables(struct mlx5e_priv *priv);
f62b8bb8	612	void mlx5e_init_eth_addr(struct mlx5e_priv *priv);
f62b8bb8 AV	613	void mlx5e_set_rx_mode_work(struct work_struct *work);
f62b8bb8 AV	614
ef9814de EBE	615	void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
	616	struct skb_shared_hwtstamps *hwts);
	617	void mlx5e_timestamp_init(struct mlx5e_priv *priv);
	618	void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
	619	int mlx5e_hwstamp_set(struct net_device dev, struct ifreq ifr);
	620	int mlx5e_hwstamp_get(struct net_device dev, struct ifreq ifr);
	621
f62b8bb8 AV	622	int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
	623	u16 vid);
	624	int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
	625	u16 vid);
	626	void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
	627	void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
f62b8bb8	628
2d75b2bc AS	629	int mlx5e_redirect_rqt(struct mlx5e_priv *priv, enum mlx5e_rqt_ix rqt_ix);
2d75b2bc AS	630
f62b8bb8 AV	631	int mlx5e_open_locked(struct net_device *netdev);
f62b8bb8 AV	632	int mlx5e_close_locked(struct net_device *netdev);
f62b8bb8 AV	633
f62b8bb8 AV	634	static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
88a85f99	635	struct mlx5e_tx_wqe *wqe, int bf_sz)
f62b8bb8	636	{
88a85f99 AS	637	u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
88a85f99 AS	638
f62b8bb8 AV	639	/* ensure wqe is visible to device before updating doorbell record */
	640	dma_wmb();
	641
	642	*sq->wq.db = cpu_to_be32(sq->pc);
	643
	644	/* ensure doorbell record is visible to device before ringing the
	645	* doorbell
	646	*/
	647	wmb();
	648
88a85f99 AS	649	if (bf_sz) {
	650	__iowrite64_copy(sq->uar_bf_map + ofst, &wqe->ctrl, bf_sz);
	651
	652	/* flush the write-combining mapped buffer */
	653	wmb();
	654
	655	} else {
	656	mlx5_write64((__be32 *)&wqe->ctrl, sq->uar_map + ofst, NULL);
	657	}
f62b8bb8 AV	658
	659	sq->bf_offset ^= sq->bf_buf_size;
	660	}
	661
	662	static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
	663	{
	664	struct mlx5_core_cq *mcq;
	665
	666	mcq = &cq->mcq;
	667	mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
	668	}
	669
3435ab59 AS	670	static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
	671	{
	672	return min_t(int, mdev->priv.eq_table.num_comp_vectors,
	673	MLX5E_MAX_NUM_CHANNELS);
	674	}
	675
f62b8bb8	676	extern const struct ethtool_ops mlx5e_ethtool_ops;
08fb1dac SM	677	#ifdef CONFIG_MLX5_CORE_EN_DCB
	678	extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
	679	int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv priv, struct ieee_ets ets);
	680	#endif
	681
58d52291	682	u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
1afff42c MF	683
1afff42c MF	684	#endif /* __MLX5_EN_H__ */