[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en / tc / post_act.c

// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.

#include "en/tc_priv.h"
#include "en_tc.h"
#include "post_act.h"
#include "mlx5_core.h"
#include "fs_core.h"

struct mlx5e_post_act {
	enum mlx5_flow_namespace_type ns_type;
	struct mlx5_fs_chains *chains;
	struct mlx5_flow_table *ft;
	struct mlx5e_priv *priv;
	struct xarray ids;
};

struct mlx5e_post_act_handle {
	enum mlx5_flow_namespace_type ns_type;
	struct mlx5_flow_attr *attr;
	struct mlx5_flow_handle *rule;
	u32 id;
};

#define MLX5_POST_ACTION_BITS MLX5_REG_MAPPING_MBITS(FTEID_TO_REG)
#define MLX5_POST_ACTION_MASK MLX5_REG_MAPPING_MASK(FTEID_TO_REG)
#define MLX5_POST_ACTION_MAX MLX5_POST_ACTION_MASK

struct mlx5e_post_act *
mlx5e_tc_post_act_init(struct mlx5e_priv *priv, struct mlx5_fs_chains *chains,
		       enum mlx5_flow_namespace_type ns_type)
{
	enum fs_flow_table_type table_type = ns_type == MLX5_FLOW_NAMESPACE_FDB ?
					     FS_FT_FDB : FS_FT_NIC_RX;
	struct mlx5e_post_act *post_act;
	int err;

	if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ignore_flow_level, table_type)) {
		if (priv->mdev->coredev_type != MLX5_COREDEV_VF)
			mlx5_core_warn(priv->mdev, "firmware level support is missing\n");
		err = -EOPNOTSUPP;
		goto err_check;
	}

	post_act = kzalloc(sizeof(*post_act), GFP_KERNEL);
	if (!post_act) {
		err = -ENOMEM;
		goto err_check;
	}
	post_act->ft = mlx5_chains_create_global_table(chains);
	if (IS_ERR(post_act->ft)) {
		err = PTR_ERR(post_act->ft);
		mlx5_core_warn(priv->mdev, "failed to create post action table, err: %d\n", err);
		goto err_ft;
	}
	post_act->chains = chains;
	post_act->ns_type = ns_type;
	post_act->priv = priv;
	xa_init_flags(&post_act->ids, XA_FLAGS_ALLOC1);
	return post_act;

err_ft:
	kfree(post_act);
err_check:
	return ERR_PTR(err);
}

void
mlx5e_tc_post_act_destroy(struct mlx5e_post_act *post_act)
{
	if (IS_ERR_OR_NULL(post_act))
		return;

	xa_destroy(&post_act->ids);
	mlx5_chains_destroy_global_table(post_act->chains, post_act->ft);
	kfree(post_act);
}

int
mlx5e_tc_post_act_offload(struct mlx5e_post_act *post_act,
			  struct mlx5e_post_act_handle *handle)
{
	struct mlx5_flow_spec *spec;
	int err;

	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
	if (!spec)
		return -ENOMEM;

	/* Post action rule matches on fte_id and executes original rule's tc rule action */
	mlx5e_tc_match_to_reg_match(spec, FTEID_TO_REG, handle->id, MLX5_POST_ACTION_MASK);

	handle->rule = mlx5e_tc_rule_offload(post_act->priv, spec, handle->attr);
	if (IS_ERR(handle->rule)) {
		err = PTR_ERR(handle->rule);
		netdev_warn(post_act->priv->netdev, "Failed to add post action rule");
		goto err_rule;
	}

	kvfree(spec);
	return 0;

err_rule:
	kvfree(spec);
	return err;
}

struct mlx5e_post_act_handle *
mlx5e_tc_post_act_add(struct mlx5e_post_act *post_act, struct mlx5_flow_attr *attr)
{
	u32 attr_sz = ns_to_attr_sz(post_act->ns_type);
	struct mlx5e_post_act_handle *handle;
	struct mlx5_flow_attr *post_attr;
	int err;

	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
	post_attr = mlx5_alloc_flow_attr(post_act->ns_type);
	if (!handle || !post_attr) {
		kfree(post_attr);
		kfree(handle);
		return ERR_PTR(-ENOMEM);
	}

	memcpy(post_attr, attr, attr_sz);
	post_attr->chain = 0;
	post_attr->prio = 0;
	post_attr->ft = post_act->ft;
	post_attr->inner_match_level = MLX5_MATCH_NONE;
	post_attr->outer_match_level = MLX5_MATCH_NONE;
	post_attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_DECAP;

	handle->ns_type = post_act->ns_type;
	/* Splits were handled before post action */
	if (handle->ns_type == MLX5_FLOW_NAMESPACE_FDB)
		post_attr->esw_attr->split_count = 0;

	err = xa_alloc(&post_act->ids, &handle->id, post_attr,
		       XA_LIMIT(1, MLX5_POST_ACTION_MAX), GFP_KERNEL);
	if (err)
		goto err_xarray;

	handle->attr = post_attr;

	return handle;

err_xarray:
	kfree(post_attr);
	kfree(handle);
	return ERR_PTR(err);
}

void
mlx5e_tc_post_act_unoffload(struct mlx5e_post_act *post_act,
			    struct mlx5e_post_act_handle *handle)
{
	mlx5e_tc_rule_unoffload(post_act->priv, handle->rule, handle->attr);
	handle->rule = NULL;
}

void
mlx5e_tc_post_act_del(struct mlx5e_post_act *post_act, struct mlx5e_post_act_handle *handle)
{
	if (!IS_ERR_OR_NULL(handle->rule))
		mlx5e_tc_post_act_unoffload(post_act, handle);
	xa_erase(&post_act->ids, handle->id);
	kfree(handle->attr);
	kfree(handle);
}

struct mlx5_flow_table *
mlx5e_tc_post_act_get_ft(struct mlx5e_post_act *post_act)
{
	return post_act->ft;
}

/* Allocate a header modify action to write the post action handle fte id to a register. */
int
mlx5e_tc_post_act_set_handle(struct mlx5_core_dev *dev,
			     struct mlx5e_post_act_handle *handle,
			     struct mlx5e_tc_mod_hdr_acts *acts)
{
	return mlx5e_tc_match_to_reg_set(dev, acts, handle->ns_type, FTEID_TO_REG, handle->id);
}
Commit	Line	Data
6f0b692a CM	1	// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
	2	// Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
	3
7843bd60	4	#include "en/tc_priv.h"
f0da4daa	5	#include "en_tc.h"
6f0b692a CM	6	#include "post_act.h"
6f0b692a CM	7	#include "mlx5_core.h"
ae2ee3be	8	#include "fs_core.h"
6f0b692a CM	9
	10	struct mlx5e_post_act {
	11	enum mlx5_flow_namespace_type ns_type;
	12	struct mlx5_fs_chains *chains;
	13	struct mlx5_flow_table *ft;
	14	struct mlx5e_priv *priv;
f0da4daa	15	struct xarray ids;
6f0b692a CM	16	};
6f0b692a CM	17
f0da4daa CM	18	struct mlx5e_post_act_handle {
	19	enum mlx5_flow_namespace_type ns_type;
	20	struct mlx5_flow_attr *attr;
	21	struct mlx5_flow_handle *rule;
	22	u32 id;
	23	};
	24
17c5da03 JL	25	#define MLX5_POST_ACTION_BITS MLX5_REG_MAPPING_MBITS(FTEID_TO_REG)
	26	#define MLX5_POST_ACTION_MASK MLX5_REG_MAPPING_MASK(FTEID_TO_REG)
	27	#define MLX5_POST_ACTION_MAX MLX5_POST_ACTION_MASK
f0da4daa	28
6f0b692a CM	29	struct mlx5e_post_act *
	30	mlx5e_tc_post_act_init(struct mlx5e_priv priv, struct mlx5_fs_chains chains,
	31	enum mlx5_flow_namespace_type ns_type)
	32	{
ae2ee3be PB	33	enum fs_flow_table_type table_type = ns_type == MLX5_FLOW_NAMESPACE_FDB ?
ae2ee3be PB	34	FS_FT_FDB : FS_FT_NIC_RX;
6f0b692a CM	35	struct mlx5e_post_act *post_act;
	36	int err;
	37
ae2ee3be PB	38	if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ignore_flow_level, table_type)) {
	39	if (priv->mdev->coredev_type != MLX5_COREDEV_VF)
	40	mlx5_core_warn(priv->mdev, "firmware level support is missing\n");
6f0b692a CM	41	err = -EOPNOTSUPP;
	42	goto err_check;
	43	}
	44
	45	post_act = kzalloc(sizeof(*post_act), GFP_KERNEL);
	46	if (!post_act) {
	47	err = -ENOMEM;
	48	goto err_check;
	49	}
	50	post_act->ft = mlx5_chains_create_global_table(chains);
	51	if (IS_ERR(post_act->ft)) {
	52	err = PTR_ERR(post_act->ft);
	53	mlx5_core_warn(priv->mdev, "failed to create post action table, err: %d\n", err);
	54	goto err_ft;
	55	}
	56	post_act->chains = chains;
	57	post_act->ns_type = ns_type;
	58	post_act->priv = priv;
f0da4daa	59	xa_init_flags(&post_act->ids, XA_FLAGS_ALLOC1);
6f0b692a CM	60	return post_act;
	61
	62	err_ft:
	63	kfree(post_act);
	64	err_check:
	65	return ERR_PTR(err);
	66	}
	67
	68	void
	69	mlx5e_tc_post_act_destroy(struct mlx5e_post_act *post_act)
	70	{
	71	if (IS_ERR_OR_NULL(post_act))
	72	return;
	73
f0da4daa	74	xa_destroy(&post_act->ids);
6f0b692a CM	75	mlx5_chains_destroy_global_table(post_act->chains, post_act->ft);
	76	kfree(post_act);
	77	}
f0da4daa	78
314e1105 RD	79	int
	80	mlx5e_tc_post_act_offload(struct mlx5e_post_act *post_act,
	81	struct mlx5e_post_act_handle *handle)
	82	{
	83	struct mlx5_flow_spec *spec;
	84	int err;
	85
	86	spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
	87	if (!spec)
	88	return -ENOMEM;
	89
	90	/* Post action rule matches on fte_id and executes original rule's tc rule action */
	91	mlx5e_tc_match_to_reg_match(spec, FTEID_TO_REG, handle->id, MLX5_POST_ACTION_MASK);
	92
7843bd60	93	handle->rule = mlx5e_tc_rule_offload(post_act->priv, spec, handle->attr);
314e1105 RD	94	if (IS_ERR(handle->rule)) {
	95	err = PTR_ERR(handle->rule);
	96	netdev_warn(post_act->priv->netdev, "Failed to add post action rule");
	97	goto err_rule;
	98	}
	99
	100	kvfree(spec);
	101	return 0;
	102
	103	err_rule:
	104	kvfree(spec);
	105	return err;
	106	}
	107
f0da4daa CM	108	struct mlx5e_post_act_handle *
	109	mlx5e_tc_post_act_add(struct mlx5e_post_act post_act, struct mlx5_flow_attr attr)
	110	{
	111	u32 attr_sz = ns_to_attr_sz(post_act->ns_type);
314e1105 RD	112	struct mlx5e_post_act_handle *handle;
314e1105 RD	113	struct mlx5_flow_attr *post_attr;
f0da4daa CM	114	int err;
	115
	116	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
f0da4daa	117	post_attr = mlx5_alloc_flow_attr(post_act->ns_type);
314e1105	118	if (!handle \|\| !post_attr) {
f0da4daa	119	kfree(post_attr);
f0da4daa CM	120	kfree(handle);
	121	return ERR_PTR(-ENOMEM);
	122	}
	123
	124	memcpy(post_attr, attr, attr_sz);
	125	post_attr->chain = 0;
	126	post_attr->prio = 0;
	127	post_attr->ft = post_act->ft;
	128	post_attr->inner_match_level = MLX5_MATCH_NONE;
	129	post_attr->outer_match_level = MLX5_MATCH_NONE;
a8128326	130	post_attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_DECAP;
f0da4daa CM	131
	132	handle->ns_type = post_act->ns_type;
	133	/* Splits were handled before post action */
	134	if (handle->ns_type == MLX5_FLOW_NAMESPACE_FDB)
	135	post_attr->esw_attr->split_count = 0;
	136
	137	err = xa_alloc(&post_act->ids, &handle->id, post_attr,
	138	XA_LIMIT(1, MLX5_POST_ACTION_MAX), GFP_KERNEL);
	139	if (err)
	140	goto err_xarray;
	141
f0da4daa CM	142	handle->attr = post_attr;
f0da4daa CM	143
f0da4daa CM	144	return handle;
f0da4daa CM	145
f0da4daa CM	146	err_xarray:
f0da4daa CM	147	kfree(post_attr);
f0da4daa CM	148	kfree(handle);
	149	return ERR_PTR(err);
	150	}
	151
	152	void
314e1105 RD	153	mlx5e_tc_post_act_unoffload(struct mlx5e_post_act *post_act,
314e1105 RD	154	struct mlx5e_post_act_handle *handle)
f0da4daa	155	{
7843bd60	156	mlx5e_tc_rule_unoffload(post_act->priv, handle->rule, handle->attr);
314e1105 RD	157	handle->rule = NULL;
	158	}
	159
	160	void
	161	mlx5e_tc_post_act_del(struct mlx5e_post_act post_act, struct mlx5e_post_act_handle handle)
	162	{
	163	if (!IS_ERR_OR_NULL(handle->rule))
	164	mlx5e_tc_post_act_unoffload(post_act, handle);
f0da4daa CM	165	xa_erase(&post_act->ids, handle->id);
	166	kfree(handle->attr);
	167	kfree(handle);
	168	}
	169
	170	struct mlx5_flow_table *
	171	mlx5e_tc_post_act_get_ft(struct mlx5e_post_act *post_act)
	172	{
	173	return post_act->ft;
	174	}
	175
	176	/* Allocate a header modify action to write the post action handle fte id to a register. */
	177	int
	178	mlx5e_tc_post_act_set_handle(struct mlx5_core_dev *dev,
	179	struct mlx5e_post_act_handle *handle,
	180	struct mlx5e_tc_mod_hdr_acts *acts)
	181	{
	182	return mlx5e_tc_match_to_reg_set(dev, acts, handle->ns_type, FTEID_TO_REG, handle->id);
	183	}