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net/mlx5_core: Use coherent memory for command interface page
[linux-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / cmd.c
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#include <asm-generic/kmap_types.h>
34#include <linux/module.h>
e126ba97
EC		 35#include <linux/errno.h>
36#include <linux/pci.h>
37#include <linux/dma-mapping.h>
38#include <linux/slab.h>
39#include <linux/delay.h>
40#include <linux/random.h>
41#include <linux/io-mapping.h>
42#include <linux/mlx5/driver.h>
43#include <linux/debugfs.h>
44
45#include "mlx5_core.h"
46
47enum {
0a324f31 48 CMD_IF_REV = 5,
e126ba97
EC		 49};
50
51enum {
52 CMD_MODE_POLLING,
53 CMD_MODE_EVENTS
54};
55
56enum {
57 NUM_LONG_LISTS = 2,
58 NUM_MED_LISTS = 64,
59 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
60 MLX5_CMD_DATA_BLOCK_SIZE,
61 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
62};
63
64enum {
65 MLX5_CMD_DELIVERY_STAT_OK = 0x0,
66 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1,
67 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2,
68 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3,
69 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4,
70 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5,
71 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6,
72 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7,
73 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8,
74 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9,
75 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10,
76};
77
78enum {
79 MLX5_CMD_STAT_OK = 0x0,
80 MLX5_CMD_STAT_INT_ERR = 0x1,
81 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
82 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
83 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
84 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
85 MLX5_CMD_STAT_RES_BUSY = 0x6,
86 MLX5_CMD_STAT_LIM_ERR = 0x8,
87 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
88 MLX5_CMD_STAT_IX_ERR = 0xa,
89 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
90 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
91 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
92 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
93 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
94 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
95};
96
97static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
98 struct mlx5_cmd_msg *in,
99 struct mlx5_cmd_msg *out,
746b5583 100 void *uout, int uout_size,
e126ba97
EC		 101 mlx5_cmd_cbk_t cbk,
102 void *context, int page_queue)
103{
104 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
105 struct mlx5_cmd_work_ent *ent;
106
107 ent = kzalloc(sizeof(*ent), alloc_flags);
108 if (!ent)
109 return ERR_PTR(-ENOMEM);
110
111 ent->in = in;
112 ent->out = out;
746b5583
EC		 113 ent->uout = uout;
114 ent->uout_size = uout_size;
e126ba97
EC		 115 ent->callback = cbk;
116 ent->context = context;
117 ent->cmd = cmd;
118 ent->page_queue = page_queue;
119
120 return ent;
121}
122
123static u8 alloc_token(struct mlx5_cmd *cmd)
124{
125 u8 token;
126
127 spin_lock(&cmd->token_lock);
128 token = cmd->token++ % 255 + 1;
129 spin_unlock(&cmd->token_lock);
130
131 return token;
132}
133
134static int alloc_ent(struct mlx5_cmd *cmd)
135{
136 unsigned long flags;
137 int ret;
138
139 spin_lock_irqsave(&cmd->alloc_lock, flags);
140 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
141 if (ret < cmd->max_reg_cmds)
142 clear_bit(ret, &cmd->bitmask);
143 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
144
145 return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
146}
147
148static void free_ent(struct mlx5_cmd *cmd, int idx)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&cmd->alloc_lock, flags);
153 set_bit(idx, &cmd->bitmask);
154 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
155}
156
157static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
158{
159 return cmd->cmd_buf + (idx << cmd->log_stride);
160}
161
162static u8 xor8_buf(void *buf, int len)
163{
164 u8 *ptr = buf;
165 u8 sum = 0;
166 int i;
167
168 for (i = 0; i < len; i++)
169 sum ^= ptr[i];
170
171 return sum;
172}
173
174static int verify_block_sig(struct mlx5_cmd_prot_block *block)
175{
176 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
177 return -EINVAL;
178
179 if (xor8_buf(block, sizeof(*block)) != 0xff)
180 return -EINVAL;
181
182 return 0;
183}
184
c1868b82
EC		 185static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
186 int csum)
e126ba97
EC		 187{
188 block->token = token;
c1868b82
EC		 189 if (csum) {
190 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
191 sizeof(block->data) - 2);
192 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
193 }
e126ba97
EC		 194}
195
c1868b82 196static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
e126ba97
EC		 197{
198 struct mlx5_cmd_mailbox *next = msg->next;
199
200 while (next) {
c1868b82 201 calc_block_sig(next->buf, token, csum);
e126ba97
EC		 202 next = next->next;
203 }
204}
205
c1868b82 206static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
e126ba97
EC		 207{
208 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
c1868b82
EC		 209 calc_chain_sig(ent->in, ent->token, csum);
210 calc_chain_sig(ent->out, ent->token, csum);
e126ba97
EC		 211}
212
213static void poll_timeout(struct mlx5_cmd_work_ent *ent)
214{
215 unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
216 u8 own;
217
218 do {
219 own = ent->lay->status_own;
220 if (!(own & CMD_OWNER_HW)) {
221 ent->ret = 0;
222 return;
223 }
224 usleep_range(5000, 10000);
225 } while (time_before(jiffies, poll_end));
226
227 ent->ret = -ETIMEDOUT;
228}
229
230static void free_cmd(struct mlx5_cmd_work_ent *ent)
231{
232 kfree(ent);
233}
234
235
236static int verify_signature(struct mlx5_cmd_work_ent *ent)
237{
238 struct mlx5_cmd_mailbox *next = ent->out->next;
239 int err;
240 u8 sig;
241
242 sig = xor8_buf(ent->lay, sizeof(*ent->lay));
243 if (sig != 0xff)
244 return -EINVAL;
245
246 while (next) {
247 err = verify_block_sig(next->buf);
248 if (err)
249 return err;
250
251 next = next->next;
252 }
253
254 return 0;
255}
256
257static void dump_buf(void *buf, int size, int data_only, int offset)
258{
259 __be32 *p = buf;
260 int i;
261
262 for (i = 0; i < size; i += 16) {
263 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
264 be32_to_cpu(p[1]), be32_to_cpu(p[2]),
265 be32_to_cpu(p[3]));
266 p += 4;
267 offset += 16;
268 }
269 if (!data_only)
270 pr_debug("\n");
271}
272
273const char *mlx5_command_str(int command)
274{
275 switch (command) {
276 case MLX5_CMD_OP_QUERY_HCA_CAP:
277 return "QUERY_HCA_CAP";
278
279 case MLX5_CMD_OP_SET_HCA_CAP:
280 return "SET_HCA_CAP";
281
282 case MLX5_CMD_OP_QUERY_ADAPTER:
283 return "QUERY_ADAPTER";
284
285 case MLX5_CMD_OP_INIT_HCA:
286 return "INIT_HCA";
287
288 case MLX5_CMD_OP_TEARDOWN_HCA:
289 return "TEARDOWN_HCA";
290
cd23b14b
EC		 291 case MLX5_CMD_OP_ENABLE_HCA:
292 return "MLX5_CMD_OP_ENABLE_HCA";
293
294 case MLX5_CMD_OP_DISABLE_HCA:
295 return "MLX5_CMD_OP_DISABLE_HCA";
296
e126ba97
EC		 297 case MLX5_CMD_OP_QUERY_PAGES:
298 return "QUERY_PAGES";
299
300 case MLX5_CMD_OP_MANAGE_PAGES:
301 return "MANAGE_PAGES";
302
303 case MLX5_CMD_OP_CREATE_MKEY:
304 return "CREATE_MKEY";
305
306 case MLX5_CMD_OP_QUERY_MKEY:
307 return "QUERY_MKEY";
308
309 case MLX5_CMD_OP_DESTROY_MKEY:
310 return "DESTROY_MKEY";
311
312 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
313 return "QUERY_SPECIAL_CONTEXTS";
314
315 case MLX5_CMD_OP_CREATE_EQ:
316 return "CREATE_EQ";
317
318 case MLX5_CMD_OP_DESTROY_EQ:
319 return "DESTROY_EQ";
320
321 case MLX5_CMD_OP_QUERY_EQ:
322 return "QUERY_EQ";
323
324 case MLX5_CMD_OP_CREATE_CQ:
325 return "CREATE_CQ";
326
327 case MLX5_CMD_OP_DESTROY_CQ:
328 return "DESTROY_CQ";
329
330 case MLX5_CMD_OP_QUERY_CQ:
331 return "QUERY_CQ";
332
333 case MLX5_CMD_OP_MODIFY_CQ:
334 return "MODIFY_CQ";
335
336 case MLX5_CMD_OP_CREATE_QP:
337 return "CREATE_QP";
338
339 case MLX5_CMD_OP_DESTROY_QP:
340 return "DESTROY_QP";
341
342 case MLX5_CMD_OP_RST2INIT_QP:
343 return "RST2INIT_QP";
344
345 case MLX5_CMD_OP_INIT2RTR_QP:
346 return "INIT2RTR_QP";
347
348 case MLX5_CMD_OP_RTR2RTS_QP:
349 return "RTR2RTS_QP";
350
351 case MLX5_CMD_OP_RTS2RTS_QP:
352 return "RTS2RTS_QP";
353
354 case MLX5_CMD_OP_SQERR2RTS_QP:
355 return "SQERR2RTS_QP";
356
357 case MLX5_CMD_OP_2ERR_QP:
358 return "2ERR_QP";
359
e126ba97
EC		 360 case MLX5_CMD_OP_2RST_QP:
361 return "2RST_QP";
362
363 case MLX5_CMD_OP_QUERY_QP:
364 return "QUERY_QP";
365
e126ba97
EC		 366 case MLX5_CMD_OP_MAD_IFC:
367 return "MAD_IFC";
368
369 case MLX5_CMD_OP_INIT2INIT_QP:
370 return "INIT2INIT_QP";
371
e126ba97
EC		 372 case MLX5_CMD_OP_CREATE_PSV:
373 return "CREATE_PSV";
374
375 case MLX5_CMD_OP_DESTROY_PSV:
376 return "DESTROY_PSV";
377
e126ba97
EC		 378 case MLX5_CMD_OP_CREATE_SRQ:
379 return "CREATE_SRQ";
380
381 case MLX5_CMD_OP_DESTROY_SRQ:
382 return "DESTROY_SRQ";
383
384 case MLX5_CMD_OP_QUERY_SRQ:
385 return "QUERY_SRQ";
386
387 case MLX5_CMD_OP_ARM_RQ:
388 return "ARM_RQ";
389
390 case MLX5_CMD_OP_RESIZE_SRQ:
391 return "RESIZE_SRQ";
392
393 case MLX5_CMD_OP_ALLOC_PD:
394 return "ALLOC_PD";
395
396 case MLX5_CMD_OP_DEALLOC_PD:
397 return "DEALLOC_PD";
398
399 case MLX5_CMD_OP_ALLOC_UAR:
400 return "ALLOC_UAR";
401
402 case MLX5_CMD_OP_DEALLOC_UAR:
403 return "DEALLOC_UAR";
404
405 case MLX5_CMD_OP_ATTACH_TO_MCG:
406 return "ATTACH_TO_MCG";
407
408 case MLX5_CMD_OP_DETACH_FROM_MCG:
409 return "DETACH_FROM_MCG";
410
411 case MLX5_CMD_OP_ALLOC_XRCD:
412 return "ALLOC_XRCD";
413
414 case MLX5_CMD_OP_DEALLOC_XRCD:
415 return "DEALLOC_XRCD";
416
417 case MLX5_CMD_OP_ACCESS_REG:
418 return "MLX5_CMD_OP_ACCESS_REG";
419
420 default: return "unknown command opcode";
421 }
422}
423
424static void dump_command(struct mlx5_core_dev *dev,
425 struct mlx5_cmd_work_ent *ent, int input)
426{
427 u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
428 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
429 struct mlx5_cmd_mailbox *next = msg->next;
430 int data_only;
f241e749 431 u32 offset = 0;
e126ba97
EC		 432 int dump_len;
433
434 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
435
436 if (data_only)
437 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
438 "dump command data %s(0x%x) %s\n",
439 mlx5_command_str(op), op,
440 input ? "INPUT" : "OUTPUT");
441 else
442 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
443 mlx5_command_str(op), op,
444 input ? "INPUT" : "OUTPUT");
445
446 if (data_only) {
447 if (input) {
448 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
449 offset += sizeof(ent->lay->in);
450 } else {
451 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
452 offset += sizeof(ent->lay->out);
453 }
454 } else {
455 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
456 offset += sizeof(*ent->lay);
457 }
458
459 while (next && offset < msg->len) {
460 if (data_only) {
461 dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
462 dump_buf(next->buf, dump_len, 1, offset);
463 offset += MLX5_CMD_DATA_BLOCK_SIZE;
464 } else {
465 mlx5_core_dbg(dev, "command block:\n");
466 dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
467 offset += sizeof(struct mlx5_cmd_prot_block);
468 }
469 next = next->next;
470 }
471
472 if (data_only)
473 pr_debug("\n");
474}
475
476static void cmd_work_handler(struct work_struct *work)
477{
478 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
479 struct mlx5_cmd *cmd = ent->cmd;
480 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
481 struct mlx5_cmd_layout *lay;
482 struct semaphore *sem;
483
484 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
485 down(sem);
486 if (!ent->page_queue) {
487 ent->idx = alloc_ent(cmd);
488 if (ent->idx < 0) {
489 mlx5_core_err(dev, "failed to allocate command entry\n");
490 up(sem);
491 return;
492 }
493 } else {
494 ent->idx = cmd->max_reg_cmds;
495 }
496
497 ent->token = alloc_token(cmd);
498 cmd->ent_arr[ent->idx] = ent;
499 lay = get_inst(cmd, ent->idx);
500 ent->lay = lay;
501 memset(lay, 0, sizeof(*lay));
502 memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
746b5583 503 ent->op = be32_to_cpu(lay->in[0]) >> 16;
e126ba97
EC		 504 if (ent->in->next)
505 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
506 lay->inlen = cpu_to_be32(ent->in->len);
507 if (ent->out->next)
508 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
509 lay->outlen = cpu_to_be32(ent->out->len);
510 lay->type = MLX5_PCI_CMD_XPORT;
511 lay->token = ent->token;
512 lay->status_own = CMD_OWNER_HW;
c1868b82 513 set_signature(ent, !cmd->checksum_disabled);
e126ba97 514 dump_command(dev, ent, 1);
14a70046 515 ent->ts1 = ktime_get_ns();
e126ba97
EC		 516
517 /* ring doorbell after the descriptor is valid */
518 wmb();
519 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
520 mlx5_core_dbg(dev, "write 0x%x to command doorbell\n", 1 << ent->idx);
521 mmiowb();
522 if (cmd->mode == CMD_MODE_POLLING) {
523 poll_timeout(ent);
524 /* make sure we read the descriptor after ownership is SW */
525 rmb();
526 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
527 }
528}
529
530static const char *deliv_status_to_str(u8 status)
531{
532 switch (status) {
533 case MLX5_CMD_DELIVERY_STAT_OK:
534 return "no errors";
535 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
536 return "signature error";
537 case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
538 return "token error";
539 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
540 return "bad block number";
541 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
542 return "output pointer not aligned to block size";
543 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
544 return "input pointer not aligned to block size";
545 case MLX5_CMD_DELIVERY_STAT_FW_ERR:
546 return "firmware internal error";
547 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
548 return "command input length error";
549 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
550 return "command ouput length error";
551 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
552 return "reserved fields not cleared";
553 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
554 return "bad command descriptor type";
555 default:
556 return "unknown status code";
557 }
558}
559
560static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
561{
562 struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
563
564 return be16_to_cpu(hdr->opcode);
565}
566
567static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
568{
569 unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
570 struct mlx5_cmd *cmd = &dev->cmd;
571 int err;
572
573 if (cmd->mode == CMD_MODE_POLLING) {
574 wait_for_completion(&ent->done);
575 err = ent->ret;
576 } else {
577 if (!wait_for_completion_timeout(&ent->done, timeout))
578 err = -ETIMEDOUT;
579 else
580 err = 0;
581 }
582 if (err == -ETIMEDOUT) {
583 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
584 mlx5_command_str(msg_to_opcode(ent->in)),
585 msg_to_opcode(ent->in));
586 }
1a91de28
JP		 587 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
588 err, deliv_status_to_str(ent->status), ent->status);
e126ba97
EC		 589
590 return err;
591}
592
593/* Notes:
594 * 1. Callback functions may not sleep
595 * 2. page queue commands do not support asynchrous completion
596 */
597static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
746b5583
EC		 598 struct mlx5_cmd_msg *out, void *uout, int uout_size,
599 mlx5_cmd_cbk_t callback,
e126ba97
EC		 600 void *context, int page_queue, u8 *status)
601{
602 struct mlx5_cmd *cmd = &dev->cmd;
603 struct mlx5_cmd_work_ent *ent;
e126ba97
EC		 604 struct mlx5_cmd_stats *stats;
605 int err = 0;
606 s64 ds;
607 u16 op;
608
609 if (callback && page_queue)
610 return -EINVAL;
611
746b5583
EC		 612 ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
613 page_queue);
e126ba97
EC		 614 if (IS_ERR(ent))
615 return PTR_ERR(ent);
616
617 if (!callback)
618 init_completion(&ent->done);
619
620 INIT_WORK(&ent->work, cmd_work_handler);
621 if (page_queue) {
622 cmd_work_handler(&ent->work);
623 } else if (!queue_work(cmd->wq, &ent->work)) {
624 mlx5_core_warn(dev, "failed to queue work\n");
625 err = -ENOMEM;
626 goto out_free;
627 }
628
629 if (!callback) {
630 err = wait_func(dev, ent);
631 if (err == -ETIMEDOUT)
632 goto out;
633
14a70046 634 ds = ent->ts2 - ent->ts1;
e126ba97
EC		 635 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
636 if (op < ARRAY_SIZE(cmd->stats)) {
637 stats = &cmd->stats[op];
746b5583 638 spin_lock_irq(&stats->lock);
e126ba97
EC		 639 stats->sum += ds;
640 ++stats->n;
746b5583 641 spin_unlock_irq(&stats->lock);
e126ba97
EC		 642 }
643 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
644 "fw exec time for %s is %lld nsec\n",
645 mlx5_command_str(op), ds);
646 *status = ent->status;
647 free_cmd(ent);
648 }
649
650 return err;
651
652out_free:
653 free_cmd(ent);
654out:
655 return err;
656}
657
658static ssize_t dbg_write(struct file *filp, const char __user *buf,
659 size_t count, loff_t *pos)
660{
661 struct mlx5_core_dev *dev = filp->private_data;
662 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
663 char lbuf[3];
664 int err;
665
666 if (!dbg->in_msg || !dbg->out_msg)
667 return -ENOMEM;
668
669 if (copy_from_user(lbuf, buf, sizeof(lbuf)))
5e631a03 670 return -EFAULT;
e126ba97
EC		 671
672 lbuf[sizeof(lbuf) - 1] = 0;
673
674 if (strcmp(lbuf, "go"))
675 return -EINVAL;
676
677 err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
678
679 return err ? err : count;
680}
681
682
683static const struct file_operations fops = {
684 .owner = THIS_MODULE,
685 .open = simple_open,
686 .write = dbg_write,
687};
688
689static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
690{
691 struct mlx5_cmd_prot_block *block;
692 struct mlx5_cmd_mailbox *next;
693 int copy;
694
695 if (!to || !from)
696 return -ENOMEM;
697
698 copy = min_t(int, size, sizeof(to->first.data));
699 memcpy(to->first.data, from, copy);
700 size -= copy;
701 from += copy;
702
703 next = to->next;
704 while (size) {
705 if (!next) {
706 /* this is a BUG */
707 return -ENOMEM;
708 }
709
710 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
711 block = next->buf;
712 memcpy(block->data, from, copy);
713 from += copy;
714 size -= copy;
715 next = next->next;
716 }
717
718 return 0;
719}
720
721static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
722{
723 struct mlx5_cmd_prot_block *block;
724 struct mlx5_cmd_mailbox *next;
725 int copy;
726
727 if (!to || !from)
728 return -ENOMEM;
729
730 copy = min_t(int, size, sizeof(from->first.data));
731 memcpy(to, from->first.data, copy);
732 size -= copy;
733 to += copy;
734
735 next = from->next;
736 while (size) {
737 if (!next) {
738 /* this is a BUG */
739 return -ENOMEM;
740 }
741
742 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
743 block = next->buf;
e126ba97
EC		 744
745 memcpy(to, block->data, copy);
746 to += copy;
747 size -= copy;
748 next = next->next;
749 }
750
751 return 0;
752}
753
754static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
755 gfp_t flags)
756{
757 struct mlx5_cmd_mailbox *mailbox;
758
759 mailbox = kmalloc(sizeof(*mailbox), flags);
760 if (!mailbox)
761 return ERR_PTR(-ENOMEM);
762
763 mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
764 &mailbox->dma);
765 if (!mailbox->buf) {
766 mlx5_core_dbg(dev, "failed allocation\n");
767 kfree(mailbox);
768 return ERR_PTR(-ENOMEM);
769 }
770 memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
771 mailbox->next = NULL;
772
773 return mailbox;
774}
775
776static void free_cmd_box(struct mlx5_core_dev *dev,
777 struct mlx5_cmd_mailbox *mailbox)
778{
779 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
780 kfree(mailbox);
781}
782
783static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
784 gfp_t flags, int size)
785{
786 struct mlx5_cmd_mailbox *tmp, *head = NULL;
787 struct mlx5_cmd_prot_block *block;
788 struct mlx5_cmd_msg *msg;
789 int blen;
790 int err;
791 int n;
792 int i;
793
746b5583 794 msg = kzalloc(sizeof(*msg), flags);
e126ba97
EC		 795 if (!msg)
796 return ERR_PTR(-ENOMEM);
797
798 blen = size - min_t(int, sizeof(msg->first.data), size);
799 n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
800
801 for (i = 0; i < n; i++) {
802 tmp = alloc_cmd_box(dev, flags);
803 if (IS_ERR(tmp)) {
804 mlx5_core_warn(dev, "failed allocating block\n");
805 err = PTR_ERR(tmp);
806 goto err_alloc;
807 }
808
809 block = tmp->buf;
810 tmp->next = head;
811 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
812 block->block_num = cpu_to_be32(n - i - 1);
813 head = tmp;
814 }
815 msg->next = head;
816 msg->len = size;
817 return msg;
818
819err_alloc:
820 while (head) {
821 tmp = head->next;
822 free_cmd_box(dev, head);
823 head = tmp;
824 }
825 kfree(msg);
826
827 return ERR_PTR(err);
828}
829
830static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
831 struct mlx5_cmd_msg *msg)
832{
833 struct mlx5_cmd_mailbox *head = msg->next;
834 struct mlx5_cmd_mailbox *next;
835
836 while (head) {
837 next = head->next;
838 free_cmd_box(dev, head);
839 head = next;
840 }
841 kfree(msg);
842}
843
844static ssize_t data_write(struct file *filp, const char __user *buf,
845 size_t count, loff_t *pos)
846{
847 struct mlx5_core_dev *dev = filp->private_data;
848 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
849 void *ptr;
850 int err;
851
852 if (*pos != 0)
853 return -EINVAL;
854
855 kfree(dbg->in_msg);
856 dbg->in_msg = NULL;
857 dbg->inlen = 0;
858
859 ptr = kzalloc(count, GFP_KERNEL);
860 if (!ptr)
861 return -ENOMEM;
862
863 if (copy_from_user(ptr, buf, count)) {
5e631a03 864 err = -EFAULT;
e126ba97
EC		 865 goto out;
866 }
867 dbg->in_msg = ptr;
868 dbg->inlen = count;
869
870 *pos = count;
871
872 return count;
873
874out:
875 kfree(ptr);
876 return err;
877}
878
879static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
880 loff_t *pos)
881{
882 struct mlx5_core_dev *dev = filp->private_data;
883 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
884 int copy;
885
886 if (*pos)
887 return 0;
888
889 if (!dbg->out_msg)
890 return -ENOMEM;
891
892 copy = min_t(int, count, dbg->outlen);
893 if (copy_to_user(buf, dbg->out_msg, copy))
5e631a03 894 return -EFAULT;
e126ba97
EC		 895
896 *pos += copy;
897
898 return copy;
899}
900
901static const struct file_operations dfops = {
902 .owner = THIS_MODULE,
903 .open = simple_open,
904 .write = data_write,
905 .read = data_read,
906};
907
908static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
909 loff_t *pos)
910{
911 struct mlx5_core_dev *dev = filp->private_data;
912 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
913 char outlen[8];
914 int err;
915
916 if (*pos)
917 return 0;
918
919 err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
920 if (err < 0)
921 return err;
922
923 if (copy_to_user(buf, &outlen, err))
5e631a03 924 return -EFAULT;
e126ba97
EC		 925
926 *pos += err;
927
928 return err;
929}
930
931static ssize_t outlen_write(struct file *filp, const char __user *buf,
932 size_t count, loff_t *pos)
933{
934 struct mlx5_core_dev *dev = filp->private_data;
935 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
936 char outlen_str[8];
937 int outlen;
938 void *ptr;
939 int err;
940
941 if (*pos != 0 || count > 6)
942 return -EINVAL;
943
944 kfree(dbg->out_msg);
945 dbg->out_msg = NULL;
946 dbg->outlen = 0;
947
948 if (copy_from_user(outlen_str, buf, count))
5e631a03 949 return -EFAULT;
e126ba97
EC		 950
951 outlen_str[7] = 0;
952
953 err = sscanf(outlen_str, "%d", &outlen);
954 if (err < 0)
955 return err;
956
957 ptr = kzalloc(outlen, GFP_KERNEL);
958 if (!ptr)
959 return -ENOMEM;
960
961 dbg->out_msg = ptr;
962 dbg->outlen = outlen;
963
964 *pos = count;
965
966 return count;
967}
968
969static const struct file_operations olfops = {
970 .owner = THIS_MODULE,
971 .open = simple_open,
972 .write = outlen_write,
973 .read = outlen_read,
974};
975
976static void set_wqname(struct mlx5_core_dev *dev)
977{
978 struct mlx5_cmd *cmd = &dev->cmd;
979
980 snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
981 dev_name(&dev->pdev->dev));
982}
983
984static void clean_debug_files(struct mlx5_core_dev *dev)
985{
986 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
987
988 if (!mlx5_debugfs_root)
989 return;
990
991 mlx5_cmdif_debugfs_cleanup(dev);
992 debugfs_remove_recursive(dbg->dbg_root);
993}
994
995static int create_debugfs_files(struct mlx5_core_dev *dev)
996{
997 struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
998 int err = -ENOMEM;
999
1000 if (!mlx5_debugfs_root)
1001 return 0;
1002
1003 dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1004 if (!dbg->dbg_root)
1005 return err;
1006
1007 dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1008 dev, &dfops);
1009 if (!dbg->dbg_in)
1010 goto err_dbg;
1011
1012 dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1013 dev, &dfops);
1014 if (!dbg->dbg_out)
1015 goto err_dbg;
1016
1017 dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1018 dev, &olfops);
1019 if (!dbg->dbg_outlen)
1020 goto err_dbg;
1021
1022 dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1023 &dbg->status);
1024 if (!dbg->dbg_status)
1025 goto err_dbg;
1026
1027 dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1028 if (!dbg->dbg_run)
1029 goto err_dbg;
1030
1031 mlx5_cmdif_debugfs_init(dev);
1032
1033 return 0;
1034
1035err_dbg:
1036 clean_debug_files(dev);
1037 return err;
1038}
1039
1040void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1041{
1042 struct mlx5_cmd *cmd = &dev->cmd;
1043 int i;
1044
1045 for (i = 0; i < cmd->max_reg_cmds; i++)
1046 down(&cmd->sem);
1047
1048 down(&cmd->pages_sem);
1049
1050 flush_workqueue(cmd->wq);
1051
1052 cmd->mode = CMD_MODE_EVENTS;
1053
1054 up(&cmd->pages_sem);
1055 for (i = 0; i < cmd->max_reg_cmds; i++)
1056 up(&cmd->sem);
1057}
1058
1059void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1060{
1061 struct mlx5_cmd *cmd = &dev->cmd;
1062 int i;
1063
1064 for (i = 0; i < cmd->max_reg_cmds; i++)
1065 down(&cmd->sem);
1066
1067 down(&cmd->pages_sem);
1068
1069 flush_workqueue(cmd->wq);
1070 cmd->mode = CMD_MODE_POLLING;
1071
1072 up(&cmd->pages_sem);
1073 for (i = 0; i < cmd->max_reg_cmds; i++)
1074 up(&cmd->sem);
1075}
1076
746b5583
EC		 1077static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1078{
1079 unsigned long flags;
1080
1081 if (msg->cache) {
1082 spin_lock_irqsave(&msg->cache->lock, flags);
1083 list_add_tail(&msg->list, &msg->cache->head);
1084 spin_unlock_irqrestore(&msg->cache->lock, flags);
1085 } else {
1086 mlx5_free_cmd_msg(dev, msg);
1087 }
1088}
1089
e126ba97
EC		 1090void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector)
1091{
1092 struct mlx5_cmd *cmd = &dev->cmd;
1093 struct mlx5_cmd_work_ent *ent;
1094 mlx5_cmd_cbk_t callback;
1095 void *context;
1096 int err;
1097 int i;
746b5583
EC		 1098 s64 ds;
1099 struct mlx5_cmd_stats *stats;
1100 unsigned long flags;
e126ba97
EC		 1101
1102 for (i = 0; i < (1 << cmd->log_sz); i++) {
1103 if (test_bit(i, &vector)) {
11940c87
DC		 1104 struct semaphore *sem;
1105
e126ba97 1106 ent = cmd->ent_arr[i];
11940c87
DC		 1107 if (ent->page_queue)
1108 sem = &cmd->pages_sem;
1109 else
1110 sem = &cmd->sem;
14a70046 1111 ent->ts2 = ktime_get_ns();
e126ba97
EC		 1112 memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1113 dump_command(dev, ent, 0);
1114 if (!ent->ret) {
1115 if (!cmd->checksum_disabled)
1116 ent->ret = verify_signature(ent);
1117 else
1118 ent->ret = 0;
1119 ent->status = ent->lay->status_own >> 1;
1120 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1121 ent->ret, deliv_status_to_str(ent->status), ent->status);
1122 }
1123 free_ent(cmd, ent->idx);
1124 if (ent->callback) {
14a70046 1125 ds = ent->ts2 - ent->ts1;
746b5583
EC		 1126 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1127 stats = &cmd->stats[ent->op];
1128 spin_lock_irqsave(&stats->lock, flags);
1129 stats->sum += ds;
1130 ++stats->n;
1131 spin_unlock_irqrestore(&stats->lock, flags);
1132 }
1133
e126ba97
EC		 1134 callback = ent->callback;
1135 context = ent->context;
1136 err = ent->ret;
746b5583
EC		 1137 if (!err)
1138 err = mlx5_copy_from_msg(ent->uout,
1139 ent->out,
1140 ent->uout_size);
1141
1142 mlx5_free_cmd_msg(dev, ent->out);
1143 free_msg(dev, ent->in);
1144
e126ba97
EC		 1145 free_cmd(ent);
1146 callback(err, context);
1147 } else {
1148 complete(&ent->done);
1149 }
11940c87 1150 up(sem);
e126ba97
EC		 1151 }
1152 }
1153}
1154EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1155
1156static int status_to_err(u8 status)
1157{
1158 return status ? -1 : 0; /* TBD more meaningful codes */
1159}
1160
746b5583
EC		 1161static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1162 gfp_t gfp)
e126ba97
EC		 1163{
1164 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1165 struct mlx5_cmd *cmd = &dev->cmd;
1166 struct cache_ent *ent = NULL;
1167
1168 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1169 ent = &cmd->cache.large;
1170 else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1171 ent = &cmd->cache.med;
1172
1173 if (ent) {
746b5583 1174 spin_lock_irq(&ent->lock);
e126ba97
EC		 1175 if (!list_empty(&ent->head)) {
1176 msg = list_entry(ent->head.next, typeof(*msg), list);
1177 /* For cached lists, we must explicitly state what is
1178 * the real size
1179 */
1180 msg->len = in_size;
1181 list_del(&msg->list);
1182 }
746b5583 1183 spin_unlock_irq(&ent->lock);
e126ba97
EC		 1184 }
1185
1186 if (IS_ERR(msg))
746b5583 1187 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
e126ba97
EC		 1188
1189 return msg;
1190}
1191
e126ba97
EC		 1192static int is_manage_pages(struct mlx5_inbox_hdr *in)
1193{
1194 return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1195}
1196
746b5583
EC		 1197static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1198 int out_size, mlx5_cmd_cbk_t callback, void *context)
e126ba97
EC		 1199{
1200 struct mlx5_cmd_msg *inb;
1201 struct mlx5_cmd_msg *outb;
1202 int pages_queue;
746b5583 1203 gfp_t gfp;
e126ba97
EC		 1204 int err;
1205 u8 status = 0;
1206
1207 pages_queue = is_manage_pages(in);
746b5583 1208 gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
e126ba97 1209
746b5583 1210 inb = alloc_msg(dev, in_size, gfp);
e126ba97
EC		 1211 if (IS_ERR(inb)) {
1212 err = PTR_ERR(inb);
1213 return err;
1214 }
1215
1216 err = mlx5_copy_to_msg(inb, in, in_size);
1217 if (err) {
1218 mlx5_core_warn(dev, "err %d\n", err);
1219 goto out_in;
1220 }
1221
746b5583 1222 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
e126ba97
EC		 1223 if (IS_ERR(outb)) {
1224 err = PTR_ERR(outb);
1225 goto out_in;
1226 }
1227
746b5583
EC		 1228 err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1229 pages_queue, &status);
e126ba97
EC		 1230 if (err)
1231 goto out_out;
1232
1233 mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1234 if (status) {
1235 err = status_to_err(status);
1236 goto out_out;
1237 }
1238
1239 err = mlx5_copy_from_msg(out, outb, out_size);
1240
1241out_out:
746b5583
EC		 1242 if (!callback)
1243 mlx5_free_cmd_msg(dev, outb);
e126ba97
EC		 1244
1245out_in:
746b5583
EC		 1246 if (!callback)
1247 free_msg(dev, inb);
e126ba97
EC		 1248 return err;
1249}
746b5583
EC		 1250
1251int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1252 int out_size)
1253{
1254 return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1255}
e126ba97
EC		 1256EXPORT_SYMBOL(mlx5_cmd_exec);
1257
746b5583
EC		 1258int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1259 void *out, int out_size, mlx5_cmd_cbk_t callback,
1260 void *context)
1261{
1262 return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1263}
1264EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1265
e126ba97
EC		 1266static void destroy_msg_cache(struct mlx5_core_dev *dev)
1267{
1268 struct mlx5_cmd *cmd = &dev->cmd;
1269 struct mlx5_cmd_msg *msg;
1270 struct mlx5_cmd_msg *n;
1271
1272 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1273 list_del(&msg->list);
1274 mlx5_free_cmd_msg(dev, msg);
1275 }
1276
1277 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1278 list_del(&msg->list);
1279 mlx5_free_cmd_msg(dev, msg);
1280 }
1281}
1282
1283static int create_msg_cache(struct mlx5_core_dev *dev)
1284{
1285 struct mlx5_cmd *cmd = &dev->cmd;
1286 struct mlx5_cmd_msg *msg;
1287 int err;
1288 int i;
1289
1290 spin_lock_init(&cmd->cache.large.lock);
1291 INIT_LIST_HEAD(&cmd->cache.large.head);
1292 spin_lock_init(&cmd->cache.med.lock);
1293 INIT_LIST_HEAD(&cmd->cache.med.head);
1294
1295 for (i = 0; i < NUM_LONG_LISTS; i++) {
1296 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1297 if (IS_ERR(msg)) {
1298 err = PTR_ERR(msg);
1299 goto ex_err;
1300 }
1301 msg->cache = &cmd->cache.large;
1302 list_add_tail(&msg->list, &cmd->cache.large.head);
1303 }
1304
1305 for (i = 0; i < NUM_MED_LISTS; i++) {
1306 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1307 if (IS_ERR(msg)) {
1308 err = PTR_ERR(msg);
1309 goto ex_err;
1310 }
1311 msg->cache = &cmd->cache.med;
1312 list_add_tail(&msg->list, &cmd->cache.med.head);
1313 }
1314
1315 return 0;
1316
1317ex_err:
1318 destroy_msg_cache(dev);
1319 return err;
1320}
1321
64599cca
EC		 1322static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1323{
1324 struct device *ddev = &dev->pdev->dev;
1325
1326 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1327 &cmd->alloc_dma, GFP_KERNEL);
1328 if (!cmd->cmd_alloc_buf)
1329 return -ENOMEM;
1330
1331 /* make sure it is aligned to 4K */
1332 if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1333 cmd->cmd_buf = cmd->cmd_alloc_buf;
1334 cmd->dma = cmd->alloc_dma;
1335 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1336 return 0;
1337 }
1338
1339 dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1340 cmd->alloc_dma);
1341 cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1342 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1343 &cmd->alloc_dma, GFP_KERNEL);
1344 if (!cmd->cmd_alloc_buf)
1345 return -ENOMEM;
1346
1347 cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1348 cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1349 cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1350 return 0;
1351}
1352
1353static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1354{
1355 struct device *ddev = &dev->pdev->dev;
1356
1357 dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1358 cmd->alloc_dma);
1359}
1360
e126ba97
EC		 1361int mlx5_cmd_init(struct mlx5_core_dev *dev)
1362{
1363 int size = sizeof(struct mlx5_cmd_prot_block);
1364 int align = roundup_pow_of_two(size);
1365 struct mlx5_cmd *cmd = &dev->cmd;
1366 u32 cmd_h, cmd_l;
1367 u16 cmd_if_rev;
1368 int err;
1369 int i;
1370
1371 cmd_if_rev = cmdif_rev(dev);
1372 if (cmd_if_rev != CMD_IF_REV) {
1373 dev_err(&dev->pdev->dev,
1374 "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1375 CMD_IF_REV, cmd_if_rev);
1376 return -EINVAL;
1377 }
1378
1379 cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1380 if (!cmd->pool)
1381 return -ENOMEM;
1382
64599cca
EC		 1383 err = alloc_cmd_page(dev, cmd);
1384 if (err)
e126ba97 1385 goto err_free_pool;
e126ba97
EC		 1386
1387 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1388 cmd->log_sz = cmd_l >> 4 & 0xf;
1389 cmd->log_stride = cmd_l & 0xf;
1390 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1391 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1392 1 << cmd->log_sz);
1393 err = -EINVAL;
64599cca 1394 goto err_free_page;
e126ba97
EC		 1395 }
1396
2d446d18 1397 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
e126ba97
EC		 1398 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1399 err = -EINVAL;
64599cca 1400 goto err_free_page;
e126ba97
EC		 1401 }
1402
c1868b82 1403 cmd->checksum_disabled = 1;
e126ba97
EC		 1404 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1405 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1406
1407 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1408 if (cmd->cmdif_rev > CMD_IF_REV) {
1409 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1410 CMD_IF_REV, cmd->cmdif_rev);
1411 err = -ENOTSUPP;
64599cca 1412 goto err_free_page;
e126ba97
EC		 1413 }
1414
1415 spin_lock_init(&cmd->alloc_lock);
1416 spin_lock_init(&cmd->token_lock);
1417 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1418 spin_lock_init(&cmd->stats[i].lock);
1419
1420 sema_init(&cmd->sem, cmd->max_reg_cmds);
1421 sema_init(&cmd->pages_sem, 1);
1422
1423 cmd_h = (u32)((u64)(cmd->dma) >> 32);
1424 cmd_l = (u32)(cmd->dma);
1425 if (cmd_l & 0xfff) {
1426 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1427 err = -ENOMEM;
64599cca 1428 goto err_free_page;
e126ba97
EC		 1429 }
1430
1431 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1432 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1433
1434 /* Make sure firmware sees the complete address before we proceed */
1435 wmb();
1436
1437 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1438
1439 cmd->mode = CMD_MODE_POLLING;
1440
1441 err = create_msg_cache(dev);
1442 if (err) {
1443 dev_err(&dev->pdev->dev, "failed to create command cache\n");
64599cca 1444 goto err_free_page;
e126ba97
EC		 1445 }
1446
1447 set_wqname(dev);
1448 cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1449 if (!cmd->wq) {
1450 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1451 err = -ENOMEM;
1452 goto err_cache;
1453 }
1454
1455 err = create_debugfs_files(dev);
1456 if (err) {
1457 err = -ENOMEM;
1458 goto err_wq;
1459 }
1460
1461 return 0;
1462
1463err_wq:
1464 destroy_workqueue(cmd->wq);
1465
1466err_cache:
1467 destroy_msg_cache(dev);
1468
64599cca
EC		 1469err_free_page:
1470 free_cmd_page(dev, cmd);
e126ba97
EC		 1471
1472err_free_pool:
1473 pci_pool_destroy(cmd->pool);
1474
1475 return err;
1476}
1477EXPORT_SYMBOL(mlx5_cmd_init);
1478
1479void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1480{
1481 struct mlx5_cmd *cmd = &dev->cmd;
1482
1483 clean_debug_files(dev);
1484 destroy_workqueue(cmd->wq);
1485 destroy_msg_cache(dev);
64599cca 1486 free_cmd_page(dev, cmd);
e126ba97
EC		 1487 pci_pool_destroy(cmd->pool);
1488}
1489EXPORT_SYMBOL(mlx5_cmd_cleanup);
1490
1491static const char *cmd_status_str(u8 status)
1492{
1493 switch (status) {
1494 case MLX5_CMD_STAT_OK:
1495 return "OK";
1496 case MLX5_CMD_STAT_INT_ERR:
1497 return "internal error";
1498 case MLX5_CMD_STAT_BAD_OP_ERR:
1499 return "bad operation";
1500 case MLX5_CMD_STAT_BAD_PARAM_ERR:
1501 return "bad parameter";
1502 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1503 return "bad system state";
1504 case MLX5_CMD_STAT_BAD_RES_ERR:
1505 return "bad resource";
1506 case MLX5_CMD_STAT_RES_BUSY:
1507 return "resource busy";
1508 case MLX5_CMD_STAT_LIM_ERR:
1509 return "limits exceeded";
1510 case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1511 return "bad resource state";
1512 case MLX5_CMD_STAT_IX_ERR:
1513 return "bad index";
1514 case MLX5_CMD_STAT_NO_RES_ERR:
1515 return "no resources";
1516 case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1517 return "bad input length";
1518 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1519 return "bad output length";
1520 case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1521 return "bad QP state";
1522 case MLX5_CMD_STAT_BAD_PKT_ERR:
1523 return "bad packet (discarded)";
1524 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1525 return "bad size too many outstanding CQEs";
1526 default:
1527 return "unknown status";
1528 }
1529}
1530
c7a08ac7 1531static int cmd_status_to_err(u8 status)
e126ba97 1532{
c7a08ac7 1533 switch (status) {
e126ba97
EC		 1534 case MLX5_CMD_STAT_OK: return 0;
1535 case MLX5_CMD_STAT_INT_ERR: return -EIO;
1536 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL;
1537 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL;
1538 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO;
1539 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL;
1540 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY;
9c865131 1541 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM;
e126ba97
EC		 1542 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL;
1543 case MLX5_CMD_STAT_IX_ERR: return -EINVAL;
1544 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN;
1545 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO;
1546 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO;
1547 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL;
1548 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL;
1549 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL;
1550 default: return -EIO;
1551 }
1552}
c7a08ac7
EC		 1553
1554/* this will be available till all the commands use set/get macros */
1555int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1556{
1557 if (!hdr->status)
1558 return 0;
1559
1560 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1561 cmd_status_str(hdr->status), hdr->status,
1562 be32_to_cpu(hdr->syndrome));
1563
1564 return cmd_status_to_err(hdr->status);
1565}
b775516b
EC		 1566
1567int mlx5_cmd_status_to_err_v2(void *ptr)
1568{
1569 u32 syndrome;
1570 u8 status;
1571
1572 status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1573 if (!status)
1574 return 0;
1575
1576 syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1577
1578 pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1579 cmd_status_str(status), status, syndrome);
1580
1581 return cmd_status_to_err(status);
1582}
Linux 6.x block layer and io_uring tree(s)