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net/mlx4: Fix the check in attaching steering rules
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / qp.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
5a0e3ad6 36#include <linux/gfp.h>
ee40fa06 37#include <linux/export.h>
fe9a2603 38
225c7b1f
RD		 39#include <linux/mlx4/cmd.h>
40#include <linux/mlx4/qp.h>
41
42#include "mlx4.h"
43#include "icm.h"
44
ddae0349
EE		 45/* QP to support BF should have bits 6,7 cleared */
46#define MLX4_BF_QP_SKIP_MASK 0xc0
47#define MLX4_MAX_BF_QP_RANGE 0x40
48
225c7b1f
RD		 49void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type)
50{
51 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
52 struct mlx4_qp *qp;
53
54 spin_lock(&qp_table->lock);
55
56 qp = __mlx4_qp_lookup(dev, qpn);
57 if (qp)
58 atomic_inc(&qp->refcount);
59
60 spin_unlock(&qp_table->lock);
61
62 if (!qp) {
fe9a2603 63 mlx4_dbg(dev, "Async event for none existent QP %08x\n", qpn);
225c7b1f
RD		 64 return;
65 }
66
67 qp->event(qp, event_type);
68
69 if (atomic_dec_and_test(&qp->refcount))
70 complete(&qp->free);
71}
72
980e9001 73/* used for INIT/CLOSE port logic */
47605df9 74static int is_master_qp0(struct mlx4_dev *dev, struct mlx4_qp *qp, int *real_qp0, int *proxy_qp0)
fe9a2603 75{
47605df9 76 /* this procedure is called after we already know we are on the master */
980e9001 77 /* qp0 is either the proxy qp0, or the real qp0 */
47605df9
JM		 78 u32 pf_proxy_offset = dev->phys_caps.base_proxy_sqpn + 8 * mlx4_master_func_num(dev);
79 *proxy_qp0 = qp->qpn >= pf_proxy_offset && qp->qpn <= pf_proxy_offset + 1;
980e9001 80
47605df9
JM		 81 *real_qp0 = qp->qpn >= dev->phys_caps.base_sqpn &&
82 qp->qpn <= dev->phys_caps.base_sqpn + 1;
980e9001
JM		 83
84 return *real_qp0 || *proxy_qp0;
fe9a2603
JM		 85}
86
87static int __mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
88 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
89 struct mlx4_qp_context *context,
90 enum mlx4_qp_optpar optpar,
91 int sqd_event, struct mlx4_qp *qp, int native)
225c7b1f
RD		 92{
93 static const u16 op[MLX4_QP_NUM_STATE][MLX4_QP_NUM_STATE] = {
94 [MLX4_QP_STATE_RST] = {
95 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
96 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
97 [MLX4_QP_STATE_INIT] = MLX4_CMD_RST2INIT_QP,
98 },
99 [MLX4_QP_STATE_INIT] = {
100 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
101 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
102 [MLX4_QP_STATE_INIT] = MLX4_CMD_INIT2INIT_QP,
103 [MLX4_QP_STATE_RTR] = MLX4_CMD_INIT2RTR_QP,
104 },
105 [MLX4_QP_STATE_RTR] = {
106 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
107 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
108 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTR2RTS_QP,
109 },
110 [MLX4_QP_STATE_RTS] = {
111 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
112 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
113 [MLX4_QP_STATE_RTS] = MLX4_CMD_RTS2RTS_QP,
114 [MLX4_QP_STATE_SQD] = MLX4_CMD_RTS2SQD_QP,
115 },
116 [MLX4_QP_STATE_SQD] = {
117 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
118 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
119 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQD2RTS_QP,
120 [MLX4_QP_STATE_SQD] = MLX4_CMD_SQD2SQD_QP,
121 },
122 [MLX4_QP_STATE_SQER] = {
123 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
124 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
125 [MLX4_QP_STATE_RTS] = MLX4_CMD_SQERR2RTS_QP,
126 },
127 [MLX4_QP_STATE_ERR] = {
128 [MLX4_QP_STATE_RST] = MLX4_CMD_2RST_QP,
129 [MLX4_QP_STATE_ERR] = MLX4_CMD_2ERR_QP,
130 }
131 };
132
fe9a2603 133 struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f
RD		 134 struct mlx4_cmd_mailbox *mailbox;
135 int ret = 0;
980e9001
JM		 136 int real_qp0 = 0;
137 int proxy_qp0 = 0;
fe9a2603 138 u8 port;
225c7b1f 139
9ed87fd3 140 if (cur_state >= MLX4_QP_NUM_STATE || new_state >= MLX4_QP_NUM_STATE ||
225c7b1f
RD		 141 !op[cur_state][new_state])
142 return -EINVAL;
143
fe9a2603
JM		 144 if (op[cur_state][new_state] == MLX4_CMD_2RST_QP) {
145 ret = mlx4_cmd(dev, 0, qp->qpn, 2,
146 MLX4_CMD_2RST_QP, MLX4_CMD_TIME_CLASS_A, native);
147 if (mlx4_is_master(dev) && cur_state != MLX4_QP_STATE_ERR &&
148 cur_state != MLX4_QP_STATE_RST &&
47605df9 149 is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
fe9a2603 150 port = (qp->qpn & 1) + 1;
980e9001
JM		 151 if (proxy_qp0)
152 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
153 else
154 priv->mfunc.master.qp0_state[port].qp0_active = 0;
fe9a2603
JM		 155 }
156 return ret;
157 }
225c7b1f
RD		 158
159 mailbox = mlx4_alloc_cmd_mailbox(dev);
160 if (IS_ERR(mailbox))
161 return PTR_ERR(mailbox);
162
163 if (cur_state == MLX4_QP_STATE_RST && new_state == MLX4_QP_STATE_INIT) {
164 u64 mtt_addr = mlx4_mtt_addr(dev, mtt);
165 context->mtt_base_addr_h = mtt_addr >> 32;
166 context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
167 context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
168 }
169
3f723f42
MS		 170 if ((cur_state == MLX4_QP_STATE_RTR) &&
171 (new_state == MLX4_QP_STATE_RTS) &&
172 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
173 context->roce_entropy =
174 cpu_to_be16(mlx4_qp_roce_entropy(dev, qp->qpn));
175
225c7b1f
RD		 176 *(__be32 *) mailbox->buf = cpu_to_be32(optpar);
177 memcpy(mailbox->buf + 8, context, sizeof *context);
178
179 ((struct mlx4_qp_context *) (mailbox->buf + 8))->local_qpn =
180 cpu_to_be32(qp->qpn);
181
eb41049f 182 ret = mlx4_cmd(dev, mailbox->dma,
fe9a2603 183 qp->qpn | (!!sqd_event << 31),
225c7b1f 184 new_state == MLX4_QP_STATE_RST ? 2 : 0,
fe9a2603 185 op[cur_state][new_state], MLX4_CMD_TIME_CLASS_C, native);
225c7b1f 186
47605df9 187 if (mlx4_is_master(dev) && is_master_qp0(dev, qp, &real_qp0, &proxy_qp0)) {
980e9001
JM		 188 port = (qp->qpn & 1) + 1;
189 if (cur_state != MLX4_QP_STATE_ERR &&
190 cur_state != MLX4_QP_STATE_RST &&
191 new_state == MLX4_QP_STATE_ERR) {
192 if (proxy_qp0)
193 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 0;
194 else
195 priv->mfunc.master.qp0_state[port].qp0_active = 0;
196 } else if (new_state == MLX4_QP_STATE_RTR) {
197 if (proxy_qp0)
198 priv->mfunc.master.qp0_state[port].proxy_qp0_active = 1;
199 else
200 priv->mfunc.master.qp0_state[port].qp0_active = 1;
201 }
202 }
203
225c7b1f
RD		 204 mlx4_free_cmd_mailbox(dev, mailbox);
205 return ret;
206}
fe9a2603
JM		 207
208int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
209 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
210 struct mlx4_qp_context *context,
211 enum mlx4_qp_optpar optpar,
212 int sqd_event, struct mlx4_qp *qp)
213{
214 return __mlx4_qp_modify(dev, mtt, cur_state, new_state, context,
215 optpar, sqd_event, qp, 0);
216}
225c7b1f
RD		 217EXPORT_SYMBOL_GPL(mlx4_qp_modify);
218
c82e9aa0 219int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
ddae0349 220 int *base, u8 flags)
a3cdcbfa 221{
d57febe1 222 u32 uid;
ddae0349
EE		 223 int bf_qp = !!(flags & (u8)MLX4_RESERVE_ETH_BF_QP);
224
a3cdcbfa
YP		 225 struct mlx4_priv *priv = mlx4_priv(dev);
226 struct mlx4_qp_table *qp_table = &priv->qp_table;
a3cdcbfa 227
ddae0349
EE		 228 if (cnt > MLX4_MAX_BF_QP_RANGE && bf_qp)
229 return -ENOMEM;
230
d57febe1
MB		 231 uid = MLX4_QP_TABLE_ZONE_GENERAL;
232 if (flags & (u8)MLX4_RESERVE_A0_QP) {
233 if (bf_qp)
234 uid = MLX4_QP_TABLE_ZONE_RAW_ETH;
235 else
236 uid = MLX4_QP_TABLE_ZONE_RSS;
237 }
238
239 *base = mlx4_zone_alloc_entries(qp_table->zones, uid, cnt, align,
240 bf_qp ? MLX4_BF_QP_SKIP_MASK : 0, NULL);
fe9a2603 241 if (*base == -1)
a3cdcbfa
YP		 242 return -ENOMEM;
243
a3cdcbfa
YP		 244 return 0;
245}
fe9a2603 246
ddae0349
EE		 247int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
248 int *base, u8 flags)
fe9a2603 249{
e7dbeba8 250 u64 in_param = 0;
fe9a2603
JM		 251 u64 out_param;
252 int err;
253
ddae0349
EE		 254 /* Turn off all unsupported QP allocation flags */
255 flags &= dev->caps.alloc_res_qp_mask;
256
fe9a2603 257 if (mlx4_is_mfunc(dev)) {
ddae0349 258 set_param_l(&in_param, (((u32)flags) << 24) | (u32)cnt);
fe9a2603
JM		 259 set_param_h(&in_param, align);
260 err = mlx4_cmd_imm(dev, in_param, &out_param,
261 RES_QP, RES_OP_RESERVE,
262 MLX4_CMD_ALLOC_RES,
263 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
264 if (err)
265 return err;
266
267 *base = get_param_l(&out_param);
268 return 0;
269 }
ddae0349 270 return __mlx4_qp_reserve_range(dev, cnt, align, base, flags);
fe9a2603 271}
a3cdcbfa
YP		 272EXPORT_SYMBOL_GPL(mlx4_qp_reserve_range);
273
c82e9aa0 274void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
a3cdcbfa
YP		 275{
276 struct mlx4_priv *priv = mlx4_priv(dev);
277 struct mlx4_qp_table *qp_table = &priv->qp_table;
a3cdcbfa 278
fe9a2603
JM		 279 if (mlx4_is_qp_reserved(dev, (u32) base_qpn))
280 return;
d57febe1 281 mlx4_zone_free_entries_unique(qp_table->zones, base_qpn, cnt);
a3cdcbfa 282}
fe9a2603
JM		 283
284void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt)
285{
e7dbeba8 286 u64 in_param = 0;
fe9a2603
JM		 287 int err;
288
289 if (mlx4_is_mfunc(dev)) {
290 set_param_l(&in_param, base_qpn);
291 set_param_h(&in_param, cnt);
292 err = mlx4_cmd(dev, in_param, RES_QP, RES_OP_RESERVE,
293 MLX4_CMD_FREE_RES,
294 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
295 if (err) {
1a91de28
JP		 296 mlx4_warn(dev, "Failed to release qp range base:%d cnt:%d\n",
297 base_qpn, cnt);
fe9a2603
JM		 298 }
299 } else
300 __mlx4_qp_release_range(dev, base_qpn, cnt);
301}
a3cdcbfa
YP		 302EXPORT_SYMBOL_GPL(mlx4_qp_release_range);
303
40f2287b 304int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
225c7b1f
RD		 305{
306 struct mlx4_priv *priv = mlx4_priv(dev);
307 struct mlx4_qp_table *qp_table = &priv->qp_table;
308 int err;
309
40f2287b 310 err = mlx4_table_get(dev, &qp_table->qp_table, qpn, gfp);
225c7b1f
RD		 311 if (err)
312 goto err_out;
313
40f2287b 314 err = mlx4_table_get(dev, &qp_table->auxc_table, qpn, gfp);
225c7b1f
RD		 315 if (err)
316 goto err_put_qp;
317
40f2287b 318 err = mlx4_table_get(dev, &qp_table->altc_table, qpn, gfp);
225c7b1f
RD		 319 if (err)
320 goto err_put_auxc;
321
40f2287b 322 err = mlx4_table_get(dev, &qp_table->rdmarc_table, qpn, gfp);
225c7b1f
RD		 323 if (err)
324 goto err_put_altc;
325
40f2287b 326 err = mlx4_table_get(dev, &qp_table->cmpt_table, qpn, gfp);
225c7b1f
RD		 327 if (err)
328 goto err_put_rdmarc;
329
225c7b1f
RD		 330 return 0;
331
225c7b1f 332err_put_rdmarc:
fe9a2603 333 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
225c7b1f
RD		 334
335err_put_altc:
fe9a2603 336 mlx4_table_put(dev, &qp_table->altc_table, qpn);
225c7b1f
RD		 337
338err_put_auxc:
fe9a2603 339 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
225c7b1f
RD		 340
341err_put_qp:
fe9a2603 342 mlx4_table_put(dev, &qp_table->qp_table, qpn);
225c7b1f
RD		 343
344err_out:
225c7b1f
RD		 345 return err;
346}
fe9a2603 347
4e2c341b 348static int mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp)
fe9a2603 349{
e7dbeba8 350 u64 param = 0;
fe9a2603
JM		 351
352 if (mlx4_is_mfunc(dev)) {
353 set_param_l(&param, qpn);
354 return mlx4_cmd_imm(dev, param, &param, RES_QP, RES_OP_MAP_ICM,
355 MLX4_CMD_ALLOC_RES, MLX4_CMD_TIME_CLASS_A,
356 MLX4_CMD_WRAPPED);
357 }
40f2287b 358 return __mlx4_qp_alloc_icm(dev, qpn, gfp);
fe9a2603
JM		 359}
360
c82e9aa0 361void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
fe9a2603
JM		 362{
363 struct mlx4_priv *priv = mlx4_priv(dev);
364 struct mlx4_qp_table *qp_table = &priv->qp_table;
365
366 mlx4_table_put(dev, &qp_table->cmpt_table, qpn);
367 mlx4_table_put(dev, &qp_table->rdmarc_table, qpn);
368 mlx4_table_put(dev, &qp_table->altc_table, qpn);
369 mlx4_table_put(dev, &qp_table->auxc_table, qpn);
370 mlx4_table_put(dev, &qp_table->qp_table, qpn);
371}
372
373static void mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn)
374{
e7dbeba8 375 u64 in_param = 0;
fe9a2603
JM		 376
377 if (mlx4_is_mfunc(dev)) {
378 set_param_l(&in_param, qpn);
379 if (mlx4_cmd(dev, in_param, RES_QP, RES_OP_MAP_ICM,
380 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
381 MLX4_CMD_WRAPPED))
382 mlx4_warn(dev, "Failed to free icm of qp:%d\n", qpn);
383 } else
384 __mlx4_qp_free_icm(dev, qpn);
385}
386
6dc06c08
TB		 387struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
388{
389 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
390 struct mlx4_qp *qp;
391
392 spin_lock(&qp_table->lock);
393
394 qp = __mlx4_qp_lookup(dev, qpn);
395
396 spin_unlock(&qp_table->lock);
397 return qp;
398}
399
40f2287b 400int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, gfp_t gfp)
fe9a2603
JM		 401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_qp_table *qp_table = &priv->qp_table;
404 int err;
405
406 if (!qpn)
407 return -EINVAL;
408
409 qp->qpn = qpn;
410
40f2287b 411 err = mlx4_qp_alloc_icm(dev, qpn, gfp);
fe9a2603
JM		 412 if (err)
413 return err;
414
415 spin_lock_irq(&qp_table->lock);
416 err = radix_tree_insert(&dev->qp_table_tree, qp->qpn &
417 (dev->caps.num_qps - 1), qp);
418 spin_unlock_irq(&qp_table->lock);
419 if (err)
420 goto err_icm;
421
422 atomic_set(&qp->refcount, 1);
423 init_completion(&qp->free);
424
425 return 0;
426
427err_icm:
428 mlx4_qp_free_icm(dev, qpn);
429 return err;
430}
431
225c7b1f
RD		 432EXPORT_SYMBOL_GPL(mlx4_qp_alloc);
433
09e05c3f 434int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
ce8d9e0d
MB		 435 enum mlx4_update_qp_attr attr,
436 struct mlx4_update_qp_params *params)
437{
438 struct mlx4_cmd_mailbox *mailbox;
439 struct mlx4_update_qp_context *cmd;
440 u64 pri_addr_path_mask = 0;
09e05c3f 441 u64 qp_mask = 0;
ce8d9e0d
MB		 442 int err = 0;
443
a5b3c56e
JM		 444 if (!attr || (attr & ~MLX4_UPDATE_QP_SUPPORTED_ATTRS))
445 return -EINVAL;
446
ce8d9e0d
MB		 447 mailbox = mlx4_alloc_cmd_mailbox(dev);
448 if (IS_ERR(mailbox))
449 return PTR_ERR(mailbox);
450
451 cmd = (struct mlx4_update_qp_context *)mailbox->buf;
452
ce8d9e0d
MB		 453 if (attr & MLX4_UPDATE_QP_SMAC) {
454 pri_addr_path_mask |= 1ULL << MLX4_UPD_QP_PATH_MASK_MAC_INDEX;
455 cmd->qp_context.pri_path.grh_mylmc = params->smac_index;
456 }
457
9a892835
MG		 458 if (attr & MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB) {
459 if (!(dev->caps.flags2
460 & MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB)) {
461 mlx4_warn(dev,
462 "Trying to set src check LB, but it isn't supported\n");
423b3aec 463 err = -EOPNOTSUPP;
9a892835
MG		 464 goto out;
465 }
466 pri_addr_path_mask |=
467 1ULL << MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB;
468 if (params->flags &
469 MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB) {
470 cmd->qp_context.pri_path.fl |=
471 MLX4_FL_ETH_SRC_CHECK_MC_LB;
472 }
473 }
474
09e05c3f
MB		 475 if (attr & MLX4_UPDATE_QP_VSD) {
476 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_VSD;
477 if (params->flags & MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE)
478 cmd->qp_context.param3 |= cpu_to_be32(MLX4_STRIP_VLAN);
479 }
480
fc31e256
OG		 481 if (attr & MLX4_UPDATE_QP_RATE_LIMIT) {
482 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_RATE_LIMIT;
483 cmd->qp_context.rate_limit_params = cpu_to_be16((params->rate_unit << 14) | params->rate_val);
484 }
485
08068cd5
IS		 486 if (attr & MLX4_UPDATE_QP_QOS_VPORT) {
487 qp_mask |= 1ULL << MLX4_UPD_QP_MASK_QOS_VPP;
488 cmd->qp_context.qos_vport = params->qos_vport;
489 }
490
ce8d9e0d 491 cmd->primary_addr_path_mask = cpu_to_be64(pri_addr_path_mask);
09e05c3f 492 cmd->qp_mask = cpu_to_be64(qp_mask);
ce8d9e0d 493
09e05c3f 494 err = mlx4_cmd(dev, mailbox->dma, qpn & 0xffffff, 0,
ce8d9e0d
MB		 495 MLX4_CMD_UPDATE_QP, MLX4_CMD_TIME_CLASS_A,
496 MLX4_CMD_NATIVE);
9a892835 497out:
ce8d9e0d
MB		 498 mlx4_free_cmd_mailbox(dev, mailbox);
499 return err;
500}
501EXPORT_SYMBOL_GPL(mlx4_update_qp);
502
225c7b1f
RD		 503void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp)
504{
505 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
506 unsigned long flags;
507
508 spin_lock_irqsave(&qp_table->lock, flags);
509 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1));
510 spin_unlock_irqrestore(&qp_table->lock, flags);
511}
512EXPORT_SYMBOL_GPL(mlx4_qp_remove);
513
514void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp)
515{
225c7b1f
RD		 516 if (atomic_dec_and_test(&qp->refcount))
517 complete(&qp->free);
518 wait_for_completion(&qp->free);
519
fe9a2603 520 mlx4_qp_free_icm(dev, qp->qpn);
225c7b1f
RD		 521}
522EXPORT_SYMBOL_GPL(mlx4_qp_free);
523
524static int mlx4_CONF_SPECIAL_QP(struct mlx4_dev *dev, u32 base_qpn)
525{
526 return mlx4_cmd(dev, 0, base_qpn, 0, MLX4_CMD_CONF_SPECIAL_QP,
f9baff50 527 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 528}
529
d57febe1
MB		 530#define MLX4_QP_TABLE_RSS_ETH_PRIORITY 2
531#define MLX4_QP_TABLE_RAW_ETH_PRIORITY 1
532#define MLX4_QP_TABLE_RAW_ETH_SIZE 256
533
534static int mlx4_create_zones(struct mlx4_dev *dev,
535 u32 reserved_bottom_general,
536 u32 reserved_top_general,
537 u32 reserved_bottom_rss,
538 u32 start_offset_rss,
539 u32 max_table_offset)
540{
541 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
542 struct mlx4_bitmap (*bitmap)[MLX4_QP_TABLE_ZONE_NUM] = NULL;
543 int bitmap_initialized = 0;
544 u32 last_offset;
545 int k;
546 int err;
547
548 qp_table->zones = mlx4_zone_allocator_create(MLX4_ZONE_ALLOC_FLAGS_NO_OVERLAP);
549
550 if (NULL == qp_table->zones)
551 return -ENOMEM;
552
553 bitmap = kmalloc(sizeof(*bitmap), GFP_KERNEL);
554
555 if (NULL == bitmap) {
556 err = -ENOMEM;
557 goto free_zone;
558 }
559
560 err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_GENERAL, dev->caps.num_qps,
561 (1 << 23) - 1, reserved_bottom_general,
562 reserved_top_general);
563
564 if (err)
565 goto free_bitmap;
566
567 ++bitmap_initialized;
568
569 err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_GENERAL,
570 MLX4_ZONE_FALLBACK_TO_HIGHER_PRIO |
571 MLX4_ZONE_USE_RR, 0,
572 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_GENERAL);
573
574 if (err)
575 goto free_bitmap;
576
577 err = mlx4_bitmap_init(*bitmap + MLX4_QP_TABLE_ZONE_RSS,
578 reserved_bottom_rss,
579 reserved_bottom_rss - 1,
580 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
581 reserved_bottom_rss - start_offset_rss);
582
583 if (err)
584 goto free_bitmap;
585
586 ++bitmap_initialized;
587
588 err = mlx4_zone_add_one(qp_table->zones, *bitmap + MLX4_QP_TABLE_ZONE_RSS,
589 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
590 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
591 MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RSS_ETH_PRIORITY,
592 0, qp_table->zones_uids + MLX4_QP_TABLE_ZONE_RSS);
593
594 if (err)
595 goto free_bitmap;
596
597 last_offset = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
598 /* We have a single zone for the A0 steering QPs area of the FW. This area
599 * needs to be split into subareas. One set of subareas is for RSS QPs
600 * (in which qp number bits 6 and/or 7 are set); the other set of subareas
601 * is for RAW_ETH QPs, which require that both bits 6 and 7 are zero.
602 * Currently, the values returned by the FW (A0 steering area starting qp number
603 * and A0 steering area size) are such that there are only two subareas -- one
604 * for RSS and one for RAW_ETH.
605 */
606 for (k = MLX4_QP_TABLE_ZONE_RSS + 1; k < sizeof(*bitmap)/sizeof((*bitmap)[0]);
607 k++) {
608 int size;
609 u32 offset = start_offset_rss;
610 u32 bf_mask;
611 u32 requested_size;
612
613 /* Assuming MLX4_BF_QP_SKIP_MASK is consecutive ones, this calculates
614 * a mask of all LSB bits set until (and not including) the first
615 * set bit of MLX4_BF_QP_SKIP_MASK. For example, if MLX4_BF_QP_SKIP_MASK
616 * is 0xc0, bf_mask will be 0x3f.
617 */
618 bf_mask = (MLX4_BF_QP_SKIP_MASK & ~(MLX4_BF_QP_SKIP_MASK - 1)) - 1;
619 requested_size = min((u32)MLX4_QP_TABLE_RAW_ETH_SIZE, bf_mask + 1);
620
621 if (((last_offset & MLX4_BF_QP_SKIP_MASK) &&
622 ((int)(max_table_offset - last_offset)) >=
623 roundup_pow_of_two(MLX4_BF_QP_SKIP_MASK)) ||
624 (!(last_offset & MLX4_BF_QP_SKIP_MASK) &&
625 !((last_offset + requested_size - 1) &
626 MLX4_BF_QP_SKIP_MASK)))
627 size = requested_size;
628 else {
629 u32 candidate_offset =
630 (last_offset | MLX4_BF_QP_SKIP_MASK | bf_mask) + 1;
631
632 if (last_offset & MLX4_BF_QP_SKIP_MASK)
633 last_offset = candidate_offset;
634
635 /* From this point, the BF bits are 0 */
636
637 if (last_offset > max_table_offset) {
638 /* need to skip */
639 size = -1;
640 } else {
641 size = min3(max_table_offset - last_offset,
642 bf_mask - (last_offset & bf_mask),
643 requested_size);
644 if (size < requested_size) {
645 int candidate_size;
646
647 candidate_size = min3(
648 max_table_offset - candidate_offset,
649 bf_mask - (last_offset & bf_mask),
650 requested_size);
651
652 /* We will not take this path if last_offset was
653 * already set above to candidate_offset
654 */
655 if (candidate_size > size) {
656 last_offset = candidate_offset;
657 size = candidate_size;
658 }
659 }
660 }
661 }
662
663 if (size > 0) {
664 /* mlx4_bitmap_alloc_range will find a contiguous range of "size"
665 * QPs in which both bits 6 and 7 are zero, because we pass it the
666 * MLX4_BF_SKIP_MASK).
667 */
668 offset = mlx4_bitmap_alloc_range(
669 *bitmap + MLX4_QP_TABLE_ZONE_RSS,
670 size, 1,
671 MLX4_BF_QP_SKIP_MASK);
672
673 if (offset == (u32)-1) {
674 err = -ENOMEM;
675 break;
676 }
677
678 last_offset = offset + size;
679
680 err = mlx4_bitmap_init(*bitmap + k, roundup_pow_of_two(size),
681 roundup_pow_of_two(size) - 1, 0,
682 roundup_pow_of_two(size) - size);
683 } else {
684 /* Add an empty bitmap, we'll allocate from different zones (since
685 * at least one is reserved)
686 */
687 err = mlx4_bitmap_init(*bitmap + k, 1,
688 MLX4_QP_TABLE_RAW_ETH_SIZE - 1, 0,
689 0);
690 mlx4_bitmap_alloc_range(*bitmap + k, 1, 1, 0);
691 }
692
693 if (err)
694 break;
695
696 ++bitmap_initialized;
697
698 err = mlx4_zone_add_one(qp_table->zones, *bitmap + k,
699 MLX4_ZONE_ALLOW_ALLOC_FROM_LOWER_PRIO |
700 MLX4_ZONE_ALLOW_ALLOC_FROM_EQ_PRIO |
701 MLX4_ZONE_USE_RR, MLX4_QP_TABLE_RAW_ETH_PRIORITY,
702 offset, qp_table->zones_uids + k);
703
704 if (err)
705 break;
706 }
707
708 if (err)
709 goto free_bitmap;
710
711 qp_table->bitmap_gen = *bitmap;
712
713 return err;
714
715free_bitmap:
716 for (k = 0; k < bitmap_initialized; k++)
717 mlx4_bitmap_cleanup(*bitmap + k);
718 kfree(bitmap);
719free_zone:
720 mlx4_zone_allocator_destroy(qp_table->zones);
721 return err;
722}
723
724static void mlx4_cleanup_qp_zones(struct mlx4_dev *dev)
725{
726 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
727
728 if (qp_table->zones) {
729 int i;
730
731 for (i = 0;
732 i < sizeof(qp_table->zones_uids)/sizeof(qp_table->zones_uids[0]);
733 i++) {
734 struct mlx4_bitmap *bitmap =
735 mlx4_zone_get_bitmap(qp_table->zones,
736 qp_table->zones_uids[i]);
737
738 mlx4_zone_remove_one(qp_table->zones, qp_table->zones_uids[i]);
739 if (NULL == bitmap)
740 continue;
741
742 mlx4_bitmap_cleanup(bitmap);
743 }
744 mlx4_zone_allocator_destroy(qp_table->zones);
745 kfree(qp_table->bitmap_gen);
746 qp_table->bitmap_gen = NULL;
747 qp_table->zones = NULL;
748 }
749}
750
3d73c288 751int mlx4_init_qp_table(struct mlx4_dev *dev)
225c7b1f
RD		 752{
753 struct mlx4_qp_table *qp_table = &mlx4_priv(dev)->qp_table;
754 int err;
93fc9e1b 755 int reserved_from_top = 0;
ab256e5a 756 int reserved_from_bot;
47605df9 757 int k;
d57febe1
MB		 758 int fixed_reserved_from_bot_rv = 0;
759 int bottom_reserved_for_rss_bitmap;
7d077cd3
MB		 760 u32 max_table_offset = dev->caps.dmfs_high_rate_qpn_base +
761 dev->caps.dmfs_high_rate_qpn_range;
225c7b1f
RD		 762
763 spin_lock_init(&qp_table->lock);
764 INIT_RADIX_TREE(&dev->qp_table_tree, GFP_ATOMIC);
fe9a2603
JM		 765 if (mlx4_is_slave(dev))
766 return 0;
225c7b1f 767
d57febe1 768 /* We reserve 2 extra QPs per port for the special QPs. The
225c7b1f
RD		 769 * block of special QPs must be aligned to a multiple of 8, so
770 * round up.
0a1405da
SH		 771 *
772 * We also reserve the MSB of the 24-bit QP number to indicate
773 * that a QP is an XRC QP.
225c7b1f 774 */
d57febe1
MB		 775 for (k = 0; k <= MLX4_QP_REGION_BOTTOM; k++)
776 fixed_reserved_from_bot_rv += dev->caps.reserved_qps_cnt[k];
777
778 if (fixed_reserved_from_bot_rv < max_table_offset)
779 fixed_reserved_from_bot_rv = max_table_offset;
780
781 /* We reserve at least 1 extra for bitmaps that we don't have enough space for*/
782 bottom_reserved_for_rss_bitmap =
783 roundup_pow_of_two(fixed_reserved_from_bot_rv + 1);
784 dev->phys_caps.base_sqpn = ALIGN(bottom_reserved_for_rss_bitmap, 8);
93fc9e1b
YP		 785
786 {
787 int sort[MLX4_NUM_QP_REGION];
2df1cafa 788 int i, j;
93fc9e1b
YP		 789 int last_base = dev->caps.num_qps;
790
791 for (i = 1; i < MLX4_NUM_QP_REGION; ++i)
792 sort[i] = i;
793
d57febe1
MB		 794 for (i = MLX4_NUM_QP_REGION; i > MLX4_QP_REGION_BOTTOM; --i) {
795 for (j = MLX4_QP_REGION_BOTTOM + 2; j < i; ++j) {
93fc9e1b 796 if (dev->caps.reserved_qps_cnt[sort[j]] >
2df1cafa
FF		 797 dev->caps.reserved_qps_cnt[sort[j - 1]])
798 swap(sort[j], sort[j - 1]);
93fc9e1b
YP		 799 }
800 }
801
d57febe1 802 for (i = MLX4_QP_REGION_BOTTOM + 1; i < MLX4_NUM_QP_REGION; ++i) {
93fc9e1b
YP		 803 last_base -= dev->caps.reserved_qps_cnt[sort[i]];
804 dev->caps.reserved_qps_base[sort[i]] = last_base;
805 reserved_from_top +=
806 dev->caps.reserved_qps_cnt[sort[i]];
807 }
93fc9e1b
YP		 808 }
809
e2c76824
JM		 810 /* Reserve 8 real SQPs in both native and SRIOV modes.
811 * In addition, in SRIOV mode, reserve 8 proxy SQPs per function
812 * (for all PFs and VFs), and 8 corresponding tunnel QPs.
813 * Each proxy SQP works opposite its own tunnel QP.
814 *
815 * The QPs are arranged as follows:
816 * a. 8 real SQPs
817 * b. All the proxy SQPs (8 per function)
818 * c. All the tunnel QPs (8 per function)
819 */
ab256e5a
DB		 820 reserved_from_bot = mlx4_num_reserved_sqps(dev);
821 if (reserved_from_bot + reserved_from_top > dev->caps.num_qps) {
822 mlx4_err(dev, "Number of reserved QPs is higher than number of QPs\n");
823 return -EINVAL;
824 }
e2c76824 825
d57febe1
MB		 826 err = mlx4_create_zones(dev, reserved_from_bot, reserved_from_bot,
827 bottom_reserved_for_rss_bitmap,
828 fixed_reserved_from_bot_rv,
829 max_table_offset);
830
47605df9
JM		 831 if (err)
832 return err;
e2c76824 833
e2c76824 834 if (mlx4_is_mfunc(dev)) {
47605df9
JM		 835 /* for PPF use */
836 dev->phys_caps.base_proxy_sqpn = dev->phys_caps.base_sqpn + 8;
837 dev->phys_caps.base_tunnel_sqpn = dev->phys_caps.base_sqpn + 8 + 8 * MLX4_MFUNC_MAX;
838
839 /* In mfunc, calculate proxy and tunnel qp offsets for the PF here,
840 * since the PF does not call mlx4_slave_caps */
841 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
842 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
843 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
844 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
845
846 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
847 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
848 err = -ENOMEM;
849 goto err_mem;
850 }
e2c76824 851
47605df9
JM		 852 for (k = 0; k < dev->caps.num_ports; k++) {
853 dev->caps.qp0_proxy[k] = dev->phys_caps.base_proxy_sqpn +
854 8 * mlx4_master_func_num(dev) + k;
855 dev->caps.qp0_tunnel[k] = dev->caps.qp0_proxy[k] + 8 * MLX4_MFUNC_MAX;
856 dev->caps.qp1_proxy[k] = dev->phys_caps.base_proxy_sqpn +
857 8 * mlx4_master_func_num(dev) + MLX4_MAX_PORTS + k;
858 dev->caps.qp1_tunnel[k] = dev->caps.qp1_proxy[k] + 8 * MLX4_MFUNC_MAX;
859 }
860 }
861
862
863 err = mlx4_CONF_SPECIAL_QP(dev, dev->phys_caps.base_sqpn);
225c7b1f 864 if (err)
47605df9 865 goto err_mem;
d57febe1
MB		 866
867 return err;
225c7b1f 868
47605df9
JM		 869err_mem:
870 kfree(dev->caps.qp0_tunnel);
871 kfree(dev->caps.qp0_proxy);
872 kfree(dev->caps.qp1_tunnel);
873 kfree(dev->caps.qp1_proxy);
874 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
875 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
d57febe1 876 mlx4_cleanup_qp_zones(dev);
47605df9 877 return err;
225c7b1f
RD		 878}
879
880void mlx4_cleanup_qp_table(struct mlx4_dev *dev)
881{
fe9a2603
JM		 882 if (mlx4_is_slave(dev))
883 return;
884
225c7b1f 885 mlx4_CONF_SPECIAL_QP(dev, 0);
d57febe1
MB		 886
887 mlx4_cleanup_qp_zones(dev);
225c7b1f 888}
6a775e2b
JM		 889
890int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
891 struct mlx4_qp_context *context)
892{
893 struct mlx4_cmd_mailbox *mailbox;
894 int err;
895
896 mailbox = mlx4_alloc_cmd_mailbox(dev);
897 if (IS_ERR(mailbox))
898 return PTR_ERR(mailbox);
899
900 err = mlx4_cmd_box(dev, 0, mailbox->dma, qp->qpn, 0,
f9baff50
JM		 901 MLX4_CMD_QUERY_QP, MLX4_CMD_TIME_CLASS_A,
902 MLX4_CMD_WRAPPED);
6a775e2b
JM		 903 if (!err)
904 memcpy(context, mailbox->buf + 8, sizeof *context);
905
906 mlx4_free_cmd_mailbox(dev, mailbox);
907 return err;
908}
909EXPORT_SYMBOL_GPL(mlx4_qp_query);
910
ed4d3c10
YP		 911int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
912 struct mlx4_qp_context *context,
913 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state)
914{
915 int err;
916 int i;
917 enum mlx4_qp_state states[] = {
918 MLX4_QP_STATE_RST,
919 MLX4_QP_STATE_INIT,
920 MLX4_QP_STATE_RTR,
921 MLX4_QP_STATE_RTS
922 };
923
924 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) {
925 context->flags &= cpu_to_be32(~(0xf << 28));
926 context->flags |= cpu_to_be32(states[i + 1] << 28);
53f33ae2
MS		 927 if (states[i + 1] != MLX4_QP_STATE_RTR)
928 context->params2 &= ~MLX4_QP_BIT_FPP;
ed4d3c10
YP		 929 err = mlx4_qp_modify(dev, mtt, states[i], states[i + 1],
930 context, 0, 0, qp);
931 if (err) {
1a91de28 932 mlx4_err(dev, "Failed to bring QP to state: %d with error: %d\n",
ed4d3c10
YP		 933 states[i + 1], err);
934 return err;
935 }
936
937 *qp_state = states[i + 1];
938 }
939
940 return 0;
941}
942EXPORT_SYMBOL_GPL(mlx4_qp_to_ready);
3f723f42
MS		 943
944u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn)
945{
946 struct mlx4_qp_context context;
947 struct mlx4_qp qp;
948 int err;
949
950 qp.qpn = qpn;
951 err = mlx4_qp_query(dev, &qp, &context);
952 if (!err) {
953 u32 dest_qpn = be32_to_cpu(context.remote_qpn) & 0xffffff;
954 u16 folded_dst = folded_qp(dest_qpn);
955 u16 folded_src = folded_qp(qpn);
956
957 return (dest_qpn != qpn) ?
958 ((folded_dst ^ folded_src) | 0xC000) :
959 folded_src | 0xC000;
960 }
961 return 0xdead;
962}
Linux 6.x block layer and io_uring tree(s)