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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
225c7b1f | 35 | #include <linux/errno.h> |
ee40fa06 | 36 | #include <linux/export.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
ea51b377 | 38 | #include <linux/kernel.h> |
89dd86db | 39 | #include <linux/vmalloc.h> |
225c7b1f RD |
40 | |
41 | #include <linux/mlx4/cmd.h> | |
42 | ||
43 | #include "mlx4.h" | |
44 | #include "icm.h" | |
45 | ||
225c7b1f RD |
46 | static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order) |
47 | { | |
48 | int o; | |
49 | int m; | |
50 | u32 seg; | |
51 | ||
52 | spin_lock(&buddy->lock); | |
53 | ||
e4044cfc RD |
54 | for (o = order; o <= buddy->max_order; ++o) |
55 | if (buddy->num_free[o]) { | |
56 | m = 1 << (buddy->max_order - o); | |
57 | seg = find_first_bit(buddy->bits[o], m); | |
58 | if (seg < m) | |
59 | goto found; | |
60 | } | |
225c7b1f RD |
61 | |
62 | spin_unlock(&buddy->lock); | |
63 | return -1; | |
64 | ||
65 | found: | |
66 | clear_bit(seg, buddy->bits[o]); | |
e4044cfc | 67 | --buddy->num_free[o]; |
225c7b1f RD |
68 | |
69 | while (o > order) { | |
70 | --o; | |
71 | seg <<= 1; | |
72 | set_bit(seg ^ 1, buddy->bits[o]); | |
e4044cfc | 73 | ++buddy->num_free[o]; |
225c7b1f RD |
74 | } |
75 | ||
76 | spin_unlock(&buddy->lock); | |
77 | ||
78 | seg <<= order; | |
79 | ||
80 | return seg; | |
81 | } | |
82 | ||
83 | static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order) | |
84 | { | |
85 | seg >>= order; | |
86 | ||
87 | spin_lock(&buddy->lock); | |
88 | ||
89 | while (test_bit(seg ^ 1, buddy->bits[order])) { | |
90 | clear_bit(seg ^ 1, buddy->bits[order]); | |
e4044cfc | 91 | --buddy->num_free[order]; |
225c7b1f RD |
92 | seg >>= 1; |
93 | ++order; | |
94 | } | |
95 | ||
96 | set_bit(seg, buddy->bits[order]); | |
e4044cfc | 97 | ++buddy->num_free[order]; |
225c7b1f RD |
98 | |
99 | spin_unlock(&buddy->lock); | |
100 | } | |
101 | ||
e8f9b2ed | 102 | static int mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order) |
225c7b1f RD |
103 | { |
104 | int i, s; | |
105 | ||
106 | buddy->max_order = max_order; | |
107 | spin_lock_init(&buddy->lock); | |
108 | ||
96f17d59 | 109 | buddy->bits = kcalloc(buddy->max_order + 1, sizeof (long *), |
225c7b1f | 110 | GFP_KERNEL); |
a8312755 | 111 | buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free, |
e4044cfc RD |
112 | GFP_KERNEL); |
113 | if (!buddy->bits || !buddy->num_free) | |
225c7b1f RD |
114 | goto err_out; |
115 | ||
116 | for (i = 0; i <= buddy->max_order; ++i) { | |
117 | s = BITS_TO_LONGS(1 << (buddy->max_order - i)); | |
96f17d59 | 118 | buddy->bits[i] = kcalloc(s, sizeof (long), GFP_KERNEL | __GFP_NOWARN); |
89dd86db | 119 | if (!buddy->bits[i]) { |
96f17d59 | 120 | buddy->bits[i] = vzalloc(s * sizeof(long)); |
89dd86db YH |
121 | if (!buddy->bits[i]) |
122 | goto err_out_free; | |
123 | } | |
225c7b1f RD |
124 | } |
125 | ||
126 | set_bit(0, buddy->bits[buddy->max_order]); | |
e4044cfc | 127 | buddy->num_free[buddy->max_order] = 1; |
225c7b1f RD |
128 | |
129 | return 0; | |
130 | ||
131 | err_out_free: | |
132 | for (i = 0; i <= buddy->max_order; ++i) | |
89dd86db YH |
133 | if (buddy->bits[i] && is_vmalloc_addr(buddy->bits[i])) |
134 | vfree(buddy->bits[i]); | |
135 | else | |
136 | kfree(buddy->bits[i]); | |
225c7b1f | 137 | |
e4044cfc | 138 | err_out: |
225c7b1f | 139 | kfree(buddy->bits); |
e4044cfc | 140 | kfree(buddy->num_free); |
225c7b1f | 141 | |
225c7b1f RD |
142 | return -ENOMEM; |
143 | } | |
144 | ||
145 | static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy) | |
146 | { | |
147 | int i; | |
148 | ||
149 | for (i = 0; i <= buddy->max_order; ++i) | |
89dd86db YH |
150 | if (is_vmalloc_addr(buddy->bits[i])) |
151 | vfree(buddy->bits[i]); | |
152 | else | |
153 | kfree(buddy->bits[i]); | |
225c7b1f RD |
154 | |
155 | kfree(buddy->bits); | |
e4044cfc | 156 | kfree(buddy->num_free); |
225c7b1f RD |
157 | } |
158 | ||
c82e9aa0 | 159 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
225c7b1f RD |
160 | { |
161 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
162 | u32 seg; | |
2b8fb286 MA |
163 | int seg_order; |
164 | u32 offset; | |
225c7b1f | 165 | |
2b8fb286 MA |
166 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
167 | ||
168 | seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, seg_order); | |
225c7b1f RD |
169 | if (seg == -1) |
170 | return -1; | |
171 | ||
2b8fb286 MA |
172 | offset = seg * (1 << log_mtts_per_seg); |
173 | ||
174 | if (mlx4_table_get_range(dev, &mr_table->mtt_table, offset, | |
175 | offset + (1 << order) - 1)) { | |
176 | mlx4_buddy_free(&mr_table->mtt_buddy, seg, seg_order); | |
225c7b1f RD |
177 | return -1; |
178 | } | |
179 | ||
2b8fb286 | 180 | return offset; |
225c7b1f RD |
181 | } |
182 | ||
ea51b377 JM |
183 | static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order) |
184 | { | |
e7dbeba8 | 185 | u64 in_param = 0; |
ea51b377 JM |
186 | u64 out_param; |
187 | int err; | |
188 | ||
189 | if (mlx4_is_mfunc(dev)) { | |
190 | set_param_l(&in_param, order); | |
191 | err = mlx4_cmd_imm(dev, in_param, &out_param, RES_MTT, | |
192 | RES_OP_RESERVE_AND_MAP, | |
193 | MLX4_CMD_ALLOC_RES, | |
194 | MLX4_CMD_TIME_CLASS_A, | |
195 | MLX4_CMD_WRAPPED); | |
196 | if (err) | |
197 | return -1; | |
198 | return get_param_l(&out_param); | |
199 | } | |
200 | return __mlx4_alloc_mtt_range(dev, order); | |
201 | } | |
202 | ||
225c7b1f RD |
203 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, |
204 | struct mlx4_mtt *mtt) | |
205 | { | |
206 | int i; | |
207 | ||
208 | if (!npages) { | |
209 | mtt->order = -1; | |
210 | mtt->page_shift = MLX4_ICM_PAGE_SHIFT; | |
211 | return 0; | |
212 | } else | |
213 | mtt->page_shift = page_shift; | |
214 | ||
2b8fb286 | 215 | for (mtt->order = 0, i = 1; i < npages; i <<= 1) |
225c7b1f RD |
216 | ++mtt->order; |
217 | ||
2b8fb286 MA |
218 | mtt->offset = mlx4_alloc_mtt_range(dev, mtt->order); |
219 | if (mtt->offset == -1) | |
225c7b1f RD |
220 | return -ENOMEM; |
221 | ||
222 | return 0; | |
223 | } | |
224 | EXPORT_SYMBOL_GPL(mlx4_mtt_init); | |
225 | ||
2b8fb286 | 226 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
225c7b1f | 227 | { |
2b8fb286 MA |
228 | u32 first_seg; |
229 | int seg_order; | |
225c7b1f RD |
230 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; |
231 | ||
2b8fb286 MA |
232 | seg_order = max_t(int, order - log_mtts_per_seg, 0); |
233 | first_seg = offset / (1 << log_mtts_per_seg); | |
234 | ||
235 | mlx4_buddy_free(&mr_table->mtt_buddy, first_seg, seg_order); | |
1e27ca69 MA |
236 | mlx4_table_put_range(dev, &mr_table->mtt_table, offset, |
237 | offset + (1 << order) - 1); | |
ea51b377 JM |
238 | } |
239 | ||
2b8fb286 | 240 | static void mlx4_free_mtt_range(struct mlx4_dev *dev, u32 offset, int order) |
ea51b377 | 241 | { |
e7dbeba8 | 242 | u64 in_param = 0; |
ea51b377 JM |
243 | int err; |
244 | ||
245 | if (mlx4_is_mfunc(dev)) { | |
2b8fb286 | 246 | set_param_l(&in_param, offset); |
ea51b377 JM |
247 | set_param_h(&in_param, order); |
248 | err = mlx4_cmd(dev, in_param, RES_MTT, RES_OP_RESERVE_AND_MAP, | |
249 | MLX4_CMD_FREE_RES, | |
250 | MLX4_CMD_TIME_CLASS_A, | |
251 | MLX4_CMD_WRAPPED); | |
252 | if (err) | |
1a91de28 JP |
253 | mlx4_warn(dev, "Failed to free mtt range at:%d order:%d\n", |
254 | offset, order); | |
ea51b377 JM |
255 | return; |
256 | } | |
2b8fb286 | 257 | __mlx4_free_mtt_range(dev, offset, order); |
ea51b377 JM |
258 | } |
259 | ||
260 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
261 | { | |
225c7b1f RD |
262 | if (mtt->order < 0) |
263 | return; | |
264 | ||
2b8fb286 | 265 | mlx4_free_mtt_range(dev, mtt->offset, mtt->order); |
225c7b1f RD |
266 | } |
267 | EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup); | |
268 | ||
269 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt) | |
270 | { | |
2b8fb286 | 271 | return (u64) mtt->offset * dev->caps.mtt_entry_sz; |
225c7b1f RD |
272 | } |
273 | EXPORT_SYMBOL_GPL(mlx4_mtt_addr); | |
274 | ||
275 | static u32 hw_index_to_key(u32 ind) | |
276 | { | |
277 | return (ind >> 24) | (ind << 8); | |
278 | } | |
279 | ||
280 | static u32 key_to_hw_index(u32 key) | |
281 | { | |
282 | return (key << 24) | (key >> 8); | |
283 | } | |
284 | ||
285 | static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
286 | int mpt_index) | |
287 | { | |
eb41049f | 288 | return mlx4_cmd(dev, mailbox->dma, mpt_index, |
ea51b377 JM |
289 | 0, MLX4_CMD_SW2HW_MPT, MLX4_CMD_TIME_CLASS_B, |
290 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
291 | } |
292 | ||
293 | static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
294 | int mpt_index) | |
295 | { | |
296 | return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, | |
f9baff50 JM |
297 | !mailbox, MLX4_CMD_HW2SW_MPT, |
298 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED); | |
225c7b1f RD |
299 | } |
300 | ||
e630664c MB |
301 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
302 | struct mlx4_mpt_entry ***mpt_entry) | |
303 | { | |
304 | int err; | |
305 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
306 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
307 | ||
308 | /* Make sure that at this point we have single-threaded access only */ | |
309 | ||
310 | if (mmr->enabled != MLX4_MPT_EN_HW) | |
311 | return -EINVAL; | |
312 | ||
313 | err = mlx4_HW2SW_MPT(dev, NULL, key); | |
314 | ||
315 | if (err) { | |
316 | mlx4_warn(dev, "HW2SW_MPT failed (%d).", err); | |
317 | mlx4_warn(dev, "Most likely the MR has MWs bound to it.\n"); | |
318 | return err; | |
319 | } | |
320 | ||
321 | mmr->enabled = MLX4_MPT_EN_SW; | |
322 | ||
323 | if (!mlx4_is_mfunc(dev)) { | |
324 | **mpt_entry = mlx4_table_find( | |
325 | &mlx4_priv(dev)->mr_table.dmpt_table, | |
326 | key, NULL); | |
327 | } else { | |
328 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
329 | if (IS_ERR_OR_NULL(mailbox)) | |
330 | return PTR_ERR(mailbox); | |
331 | ||
332 | err = mlx4_cmd_box(dev, 0, mailbox->dma, key, | |
333 | 0, MLX4_CMD_QUERY_MPT, | |
334 | MLX4_CMD_TIME_CLASS_B, | |
335 | MLX4_CMD_WRAPPED); | |
336 | ||
337 | if (err) | |
338 | goto free_mailbox; | |
339 | ||
340 | *mpt_entry = (struct mlx4_mpt_entry **)&mailbox->buf; | |
341 | } | |
342 | ||
343 | if (!(*mpt_entry) || !(**mpt_entry)) { | |
344 | err = -ENOMEM; | |
345 | goto free_mailbox; | |
346 | } | |
347 | ||
348 | return 0; | |
349 | ||
350 | free_mailbox: | |
351 | mlx4_free_cmd_mailbox(dev, mailbox); | |
352 | return err; | |
353 | } | |
354 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_get_mpt); | |
355 | ||
356 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
357 | struct mlx4_mpt_entry **mpt_entry) | |
358 | { | |
359 | int err; | |
360 | ||
361 | if (!mlx4_is_mfunc(dev)) { | |
362 | /* Make sure any changes to this entry are flushed */ | |
363 | wmb(); | |
364 | ||
365 | *(u8 *)(*mpt_entry) = MLX4_MPT_STATUS_HW; | |
366 | ||
367 | /* Make sure the new status is written */ | |
368 | wmb(); | |
369 | ||
370 | err = mlx4_SYNC_TPT(dev); | |
371 | } else { | |
372 | int key = key_to_hw_index(mmr->key) & (dev->caps.num_mpts - 1); | |
373 | ||
374 | struct mlx4_cmd_mailbox *mailbox = | |
375 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
376 | buf); | |
377 | ||
378 | err = mlx4_SW2HW_MPT(dev, mailbox, key); | |
379 | } | |
380 | ||
381 | mmr->pd = be32_to_cpu((*mpt_entry)->pd_flags) & MLX4_MPT_PD_MASK; | |
382 | if (!err) | |
383 | mmr->enabled = MLX4_MPT_EN_HW; | |
384 | return err; | |
385 | } | |
386 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_write_mpt); | |
387 | ||
388 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
389 | struct mlx4_mpt_entry **mpt_entry) | |
390 | { | |
391 | if (mlx4_is_mfunc(dev)) { | |
392 | struct mlx4_cmd_mailbox *mailbox = | |
393 | container_of((void *)mpt_entry, struct mlx4_cmd_mailbox, | |
394 | buf); | |
395 | mlx4_free_cmd_mailbox(dev, mailbox); | |
396 | } | |
397 | } | |
398 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_put_mpt); | |
399 | ||
400 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
401 | u32 pdn) | |
402 | { | |
403 | u32 pd_flags = be32_to_cpu(mpt_entry->pd_flags); | |
404 | /* The wrapper function will put the slave's id here */ | |
405 | if (mlx4_is_mfunc(dev)) | |
406 | pd_flags &= ~MLX4_MPT_PD_VF_MASK; | |
407 | mpt_entry->pd_flags = cpu_to_be32((pd_flags & ~MLX4_MPT_PD_MASK) | | |
408 | (pdn & MLX4_MPT_PD_MASK) | |
409 | | MLX4_MPT_PD_FLAG_EN_INV); | |
410 | return 0; | |
411 | } | |
412 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_pd); | |
413 | ||
414 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
415 | struct mlx4_mpt_entry *mpt_entry, | |
416 | u32 access) | |
417 | { | |
418 | u32 flags = (be32_to_cpu(mpt_entry->flags) & ~MLX4_PERM_MASK) | | |
419 | (access & MLX4_PERM_MASK); | |
420 | ||
421 | mpt_entry->flags = cpu_to_be32(flags); | |
422 | return 0; | |
423 | } | |
424 | EXPORT_SYMBOL_GPL(mlx4_mr_hw_change_access); | |
425 | ||
66431a7d | 426 | static int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, |
ea51b377 JM |
427 | u64 iova, u64 size, u32 access, int npages, |
428 | int page_shift, struct mlx4_mr *mr) | |
429 | { | |
225c7b1f RD |
430 | mr->iova = iova; |
431 | mr->size = size; | |
432 | mr->pd = pd; | |
433 | mr->access = access; | |
b20e519a | 434 | mr->enabled = MLX4_MPT_DISABLED; |
ea51b377 JM |
435 | mr->key = hw_index_to_key(mridx); |
436 | ||
437 | return mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); | |
438 | } | |
ea51b377 JM |
439 | |
440 | static int mlx4_WRITE_MTT(struct mlx4_dev *dev, | |
441 | struct mlx4_cmd_mailbox *mailbox, | |
442 | int num_entries) | |
443 | { | |
444 | return mlx4_cmd(dev, mailbox->dma, num_entries, 0, MLX4_CMD_WRITE_MTT, | |
445 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
446 | } | |
447 | ||
b20e519a | 448 | int __mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
449 | { |
450 | struct mlx4_priv *priv = mlx4_priv(dev); | |
451 | ||
452 | return mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap); | |
453 | } | |
225c7b1f | 454 | |
b20e519a | 455 | static int mlx4_mpt_reserve(struct mlx4_dev *dev) |
ea51b377 JM |
456 | { |
457 | u64 out_param; | |
458 | ||
459 | if (mlx4_is_mfunc(dev)) { | |
460 | if (mlx4_cmd_imm(dev, 0, &out_param, RES_MPT, RES_OP_RESERVE, | |
461 | MLX4_CMD_ALLOC_RES, | |
462 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
463 | return -1; | |
464 | return get_param_l(&out_param); | |
465 | } | |
b20e519a | 466 | return __mlx4_mpt_reserve(dev); |
ea51b377 JM |
467 | } |
468 | ||
b20e519a | 469 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
470 | { |
471 | struct mlx4_priv *priv = mlx4_priv(dev); | |
472 | ||
7c6d74d2 | 473 | mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index, MLX4_NO_RR); |
ea51b377 JM |
474 | } |
475 | ||
b20e519a | 476 | static void mlx4_mpt_release(struct mlx4_dev *dev, u32 index) |
ea51b377 | 477 | { |
e7dbeba8 | 478 | u64 in_param = 0; |
ea51b377 JM |
479 | |
480 | if (mlx4_is_mfunc(dev)) { | |
481 | set_param_l(&in_param, index); | |
482 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_RESERVE, | |
483 | MLX4_CMD_FREE_RES, | |
484 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED)) | |
485 | mlx4_warn(dev, "Failed to release mr index:%d\n", | |
486 | index); | |
487 | return; | |
488 | } | |
b20e519a | 489 | __mlx4_mpt_release(dev, index); |
ea51b377 JM |
490 | } |
491 | ||
40f2287b | 492 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp) |
ea51b377 JM |
493 | { |
494 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
495 | ||
40f2287b | 496 | return mlx4_table_get(dev, &mr_table->dmpt_table, index, gfp); |
ea51b377 JM |
497 | } |
498 | ||
40f2287b | 499 | static int mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp) |
ea51b377 | 500 | { |
e7dbeba8 | 501 | u64 param = 0; |
ea51b377 JM |
502 | |
503 | if (mlx4_is_mfunc(dev)) { | |
504 | set_param_l(¶m, index); | |
505 | return mlx4_cmd_imm(dev, param, ¶m, RES_MPT, RES_OP_MAP_ICM, | |
506 | MLX4_CMD_ALLOC_RES, | |
507 | MLX4_CMD_TIME_CLASS_A, | |
508 | MLX4_CMD_WRAPPED); | |
509 | } | |
40f2287b | 510 | return __mlx4_mpt_alloc_icm(dev, index, gfp); |
ea51b377 JM |
511 | } |
512 | ||
b20e519a | 513 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 JM |
514 | { |
515 | struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table; | |
516 | ||
517 | mlx4_table_put(dev, &mr_table->dmpt_table, index); | |
518 | } | |
519 | ||
b20e519a | 520 | static void mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index) |
ea51b377 | 521 | { |
e7dbeba8 | 522 | u64 in_param = 0; |
ea51b377 JM |
523 | |
524 | if (mlx4_is_mfunc(dev)) { | |
525 | set_param_l(&in_param, index); | |
526 | if (mlx4_cmd(dev, in_param, RES_MPT, RES_OP_MAP_ICM, | |
527 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
528 | MLX4_CMD_WRAPPED)) | |
529 | mlx4_warn(dev, "Failed to free icm of mr index:%d\n", | |
530 | index); | |
531 | return; | |
532 | } | |
b20e519a | 533 | return __mlx4_mpt_free_icm(dev, index); |
ea51b377 JM |
534 | } |
535 | ||
536 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
537 | int npages, int page_shift, struct mlx4_mr *mr) | |
538 | { | |
539 | u32 index; | |
540 | int err; | |
541 | ||
b20e519a | 542 | index = mlx4_mpt_reserve(dev); |
ea51b377 JM |
543 | if (index == -1) |
544 | return -ENOMEM; | |
545 | ||
546 | err = mlx4_mr_alloc_reserved(dev, index, pd, iova, size, | |
547 | access, npages, page_shift, mr); | |
225c7b1f | 548 | if (err) |
b20e519a | 549 | mlx4_mpt_release(dev, index); |
225c7b1f | 550 | |
225c7b1f RD |
551 | return err; |
552 | } | |
553 | EXPORT_SYMBOL_GPL(mlx4_mr_alloc); | |
554 | ||
61083720 | 555 | static int mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr) |
225c7b1f | 556 | { |
225c7b1f RD |
557 | int err; |
558 | ||
b20e519a | 559 | if (mr->enabled == MLX4_MPT_EN_HW) { |
225c7b1f RD |
560 | err = mlx4_HW2SW_MPT(dev, NULL, |
561 | key_to_hw_index(mr->key) & | |
562 | (dev->caps.num_mpts - 1)); | |
61083720 | 563 | if (err) { |
1a91de28 JP |
564 | mlx4_warn(dev, "HW2SW_MPT failed (%d), MR has MWs bound to it\n", |
565 | err); | |
61083720 SM |
566 | return err; |
567 | } | |
225c7b1f | 568 | |
b20e519a | 569 | mr->enabled = MLX4_MPT_EN_SW; |
ea51b377 | 570 | } |
225c7b1f | 571 | mlx4_mtt_cleanup(dev, &mr->mtt); |
61083720 SM |
572 | |
573 | return 0; | |
ea51b377 | 574 | } |
ea51b377 | 575 | |
61083720 | 576 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr) |
ea51b377 | 577 | { |
61083720 SM |
578 | int ret; |
579 | ||
580 | ret = mlx4_mr_free_reserved(dev, mr); | |
581 | if (ret) | |
582 | return ret; | |
ea51b377 | 583 | if (mr->enabled) |
b20e519a SM |
584 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
585 | mlx4_mpt_release(dev, key_to_hw_index(mr->key)); | |
61083720 SM |
586 | |
587 | return 0; | |
225c7b1f RD |
588 | } |
589 | EXPORT_SYMBOL_GPL(mlx4_mr_free); | |
590 | ||
e630664c MB |
591 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr) |
592 | { | |
593 | mlx4_mtt_cleanup(dev, &mr->mtt); | |
594 | } | |
595 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_cleanup); | |
596 | ||
597 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
598 | u64 iova, u64 size, int npages, | |
599 | int page_shift, struct mlx4_mpt_entry *mpt_entry) | |
600 | { | |
601 | int err; | |
602 | ||
603 | mpt_entry->start = cpu_to_be64(mr->iova); | |
604 | mpt_entry->length = cpu_to_be64(mr->size); | |
605 | mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift); | |
606 | ||
607 | err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt); | |
608 | if (err) | |
609 | return err; | |
610 | ||
611 | if (mr->mtt.order < 0) { | |
612 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
613 | mpt_entry->mtt_addr = 0; | |
614 | } else { | |
615 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, | |
616 | &mr->mtt)); | |
617 | if (mr->mtt.page_shift == 0) | |
618 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); | |
619 | } | |
620 | mr->enabled = MLX4_MPT_EN_SW; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | EXPORT_SYMBOL_GPL(mlx4_mr_rereg_mem_write); | |
625 | ||
225c7b1f RD |
626 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr) |
627 | { | |
225c7b1f RD |
628 | struct mlx4_cmd_mailbox *mailbox; |
629 | struct mlx4_mpt_entry *mpt_entry; | |
630 | int err; | |
631 | ||
40f2287b | 632 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mr->key), GFP_KERNEL); |
225c7b1f RD |
633 | if (err) |
634 | return err; | |
635 | ||
636 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
637 | if (IS_ERR(mailbox)) { | |
638 | err = PTR_ERR(mailbox); | |
639 | goto err_table; | |
640 | } | |
641 | mpt_entry = mailbox->buf; | |
95d04f07 | 642 | mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_MIO | |
225c7b1f RD |
643 | MLX4_MPT_FLAG_REGION | |
644 | mr->access); | |
225c7b1f RD |
645 | |
646 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key)); | |
95d04f07 | 647 | mpt_entry->pd_flags = cpu_to_be32(mr->pd | MLX4_MPT_PD_FLAG_EN_INV); |
225c7b1f RD |
648 | mpt_entry->start = cpu_to_be64(mr->iova); |
649 | mpt_entry->length = cpu_to_be64(mr->size); | |
650 | mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift); | |
95d04f07 | 651 | |
b2d9308a JM |
652 | if (mr->mtt.order < 0) { |
653 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL); | |
2b8fb286 | 654 | mpt_entry->mtt_addr = 0; |
95d04f07 | 655 | } else { |
2b8fb286 MA |
656 | mpt_entry->mtt_addr = cpu_to_be64(mlx4_mtt_addr(dev, |
657 | &mr->mtt)); | |
95d04f07 RD |
658 | } |
659 | ||
660 | if (mr->mtt.order >= 0 && mr->mtt.page_shift == 0) { | |
661 | /* fast register MR in free state */ | |
662 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
c9257433 VS |
663 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_FAST_REG | |
664 | MLX4_MPT_PD_FLAG_RAE); | |
2b8fb286 | 665 | mpt_entry->mtt_sz = cpu_to_be32(1 << mr->mtt.order); |
95d04f07 RD |
666 | } else { |
667 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS); | |
668 | } | |
225c7b1f RD |
669 | |
670 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
671 | key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1)); | |
672 | if (err) { | |
673 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
674 | goto err_cmd; | |
675 | } | |
b20e519a | 676 | mr->enabled = MLX4_MPT_EN_HW; |
225c7b1f RD |
677 | |
678 | mlx4_free_cmd_mailbox(dev, mailbox); | |
679 | ||
680 | return 0; | |
681 | ||
682 | err_cmd: | |
683 | mlx4_free_cmd_mailbox(dev, mailbox); | |
684 | ||
685 | err_table: | |
b20e519a | 686 | mlx4_mpt_free_icm(dev, key_to_hw_index(mr->key)); |
225c7b1f RD |
687 | return err; |
688 | } | |
689 | EXPORT_SYMBOL_GPL(mlx4_mr_enable); | |
690 | ||
d7bb58fb JM |
691 | static int mlx4_write_mtt_chunk(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
692 | int start_index, int npages, u64 *page_list) | |
225c7b1f | 693 | { |
d7bb58fb JM |
694 | struct mlx4_priv *priv = mlx4_priv(dev); |
695 | __be64 *mtts; | |
696 | dma_addr_t dma_handle; | |
697 | int i; | |
d7bb58fb | 698 | |
2b8fb286 MA |
699 | mtts = mlx4_table_find(&priv->mr_table.mtt_table, mtt->offset + |
700 | start_index, &dma_handle); | |
d7bb58fb | 701 | |
d7bb58fb JM |
702 | if (!mtts) |
703 | return -ENOMEM; | |
704 | ||
e727f5cd RD |
705 | dma_sync_single_for_cpu(&dev->pdev->dev, dma_handle, |
706 | npages * sizeof (u64), DMA_TO_DEVICE); | |
707 | ||
d7bb58fb JM |
708 | for (i = 0; i < npages; ++i) |
709 | mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
710 | ||
e727f5cd RD |
711 | dma_sync_single_for_device(&dev->pdev->dev, dma_handle, |
712 | npages * sizeof (u64), DMA_TO_DEVICE); | |
d7bb58fb JM |
713 | |
714 | return 0; | |
225c7b1f RD |
715 | } |
716 | ||
c82e9aa0 | 717 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
ea51b377 | 718 | int start_index, int npages, u64 *page_list) |
225c7b1f | 719 | { |
ea51b377 | 720 | int err = 0; |
d7bb58fb | 721 | int chunk; |
2b8fb286 MA |
722 | int mtts_per_page; |
723 | int max_mtts_first_page; | |
724 | ||
725 | /* compute how may mtts fit in the first page */ | |
726 | mtts_per_page = PAGE_SIZE / sizeof(u64); | |
727 | max_mtts_first_page = mtts_per_page - (mtt->offset + start_index) | |
728 | % mtts_per_page; | |
729 | ||
730 | chunk = min_t(int, max_mtts_first_page, npages); | |
225c7b1f | 731 | |
225c7b1f | 732 | while (npages > 0) { |
d7bb58fb | 733 | err = mlx4_write_mtt_chunk(dev, mtt, start_index, chunk, page_list); |
225c7b1f | 734 | if (err) |
d7bb58fb | 735 | return err; |
d7bb58fb JM |
736 | npages -= chunk; |
737 | start_index += chunk; | |
738 | page_list += chunk; | |
2b8fb286 MA |
739 | |
740 | chunk = min_t(int, mtts_per_page, npages); | |
225c7b1f | 741 | } |
ea51b377 JM |
742 | return err; |
743 | } | |
225c7b1f | 744 | |
ea51b377 JM |
745 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
746 | int start_index, int npages, u64 *page_list) | |
747 | { | |
748 | struct mlx4_cmd_mailbox *mailbox = NULL; | |
749 | __be64 *inbox = NULL; | |
750 | int chunk; | |
751 | int err = 0; | |
752 | int i; | |
753 | ||
754 | if (mtt->order < 0) | |
755 | return -EINVAL; | |
756 | ||
757 | if (mlx4_is_mfunc(dev)) { | |
758 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
759 | if (IS_ERR(mailbox)) | |
760 | return PTR_ERR(mailbox); | |
761 | inbox = mailbox->buf; | |
762 | ||
763 | while (npages > 0) { | |
2b8fb286 MA |
764 | chunk = min_t(int, MLX4_MAILBOX_SIZE / sizeof(u64) - 2, |
765 | npages); | |
766 | inbox[0] = cpu_to_be64(mtt->offset + start_index); | |
ea51b377 JM |
767 | inbox[1] = 0; |
768 | for (i = 0; i < chunk; ++i) | |
769 | inbox[i + 2] = cpu_to_be64(page_list[i] | | |
770 | MLX4_MTT_FLAG_PRESENT); | |
771 | err = mlx4_WRITE_MTT(dev, mailbox, chunk); | |
772 | if (err) { | |
773 | mlx4_free_cmd_mailbox(dev, mailbox); | |
774 | return err; | |
775 | } | |
776 | ||
777 | npages -= chunk; | |
778 | start_index += chunk; | |
779 | page_list += chunk; | |
780 | } | |
781 | mlx4_free_cmd_mailbox(dev, mailbox); | |
782 | return err; | |
783 | } | |
784 | ||
785 | return __mlx4_write_mtt(dev, mtt, start_index, npages, page_list); | |
225c7b1f RD |
786 | } |
787 | EXPORT_SYMBOL_GPL(mlx4_write_mtt); | |
788 | ||
789 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 790 | struct mlx4_buf *buf, gfp_t gfp) |
225c7b1f RD |
791 | { |
792 | u64 *page_list; | |
793 | int err; | |
794 | int i; | |
795 | ||
40f2287b JK |
796 | page_list = kmalloc(buf->npages * sizeof *page_list, |
797 | gfp); | |
225c7b1f RD |
798 | if (!page_list) |
799 | return -ENOMEM; | |
800 | ||
801 | for (i = 0; i < buf->npages; ++i) | |
802 | if (buf->nbufs == 1) | |
b57aacfa | 803 | page_list[i] = buf->direct.map + (i << buf->page_shift); |
225c7b1f | 804 | else |
b57aacfa | 805 | page_list[i] = buf->page_list[i].map; |
225c7b1f RD |
806 | |
807 | err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list); | |
808 | ||
809 | kfree(page_list); | |
810 | return err; | |
811 | } | |
812 | EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt); | |
813 | ||
804d6a89 SM |
814 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
815 | struct mlx4_mw *mw) | |
816 | { | |
817 | u32 index; | |
818 | ||
819 | if ((type == MLX4_MW_TYPE_1 && | |
820 | !(dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)) || | |
821 | (type == MLX4_MW_TYPE_2 && | |
822 | !(dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN))) | |
823 | return -ENOTSUPP; | |
824 | ||
825 | index = mlx4_mpt_reserve(dev); | |
826 | if (index == -1) | |
827 | return -ENOMEM; | |
828 | ||
829 | mw->key = hw_index_to_key(index); | |
830 | mw->pd = pd; | |
831 | mw->type = type; | |
832 | mw->enabled = MLX4_MPT_DISABLED; | |
833 | ||
834 | return 0; | |
835 | } | |
836 | EXPORT_SYMBOL_GPL(mlx4_mw_alloc); | |
837 | ||
838 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
839 | { | |
840 | struct mlx4_cmd_mailbox *mailbox; | |
841 | struct mlx4_mpt_entry *mpt_entry; | |
842 | int err; | |
843 | ||
40f2287b | 844 | err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key), GFP_KERNEL); |
804d6a89 SM |
845 | if (err) |
846 | return err; | |
847 | ||
848 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
849 | if (IS_ERR(mailbox)) { | |
850 | err = PTR_ERR(mailbox); | |
851 | goto err_table; | |
852 | } | |
853 | mpt_entry = mailbox->buf; | |
854 | ||
804d6a89 SM |
855 | /* Note that the MLX4_MPT_FLAG_REGION bit in mpt_entry->flags is turned |
856 | * off, thus creating a memory window and not a memory region. | |
857 | */ | |
858 | mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key)); | |
859 | mpt_entry->pd_flags = cpu_to_be32(mw->pd); | |
860 | if (mw->type == MLX4_MW_TYPE_2) { | |
861 | mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_FREE); | |
862 | mpt_entry->qpn = cpu_to_be32(MLX4_MPT_QP_FLAG_BOUND_QP); | |
863 | mpt_entry->pd_flags |= cpu_to_be32(MLX4_MPT_PD_FLAG_EN_INV); | |
864 | } | |
865 | ||
866 | err = mlx4_SW2HW_MPT(dev, mailbox, | |
867 | key_to_hw_index(mw->key) & | |
868 | (dev->caps.num_mpts - 1)); | |
869 | if (err) { | |
870 | mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err); | |
871 | goto err_cmd; | |
872 | } | |
873 | mw->enabled = MLX4_MPT_EN_HW; | |
874 | ||
875 | mlx4_free_cmd_mailbox(dev, mailbox); | |
876 | ||
877 | return 0; | |
878 | ||
879 | err_cmd: | |
880 | mlx4_free_cmd_mailbox(dev, mailbox); | |
881 | ||
882 | err_table: | |
883 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
884 | return err; | |
885 | } | |
886 | EXPORT_SYMBOL_GPL(mlx4_mw_enable); | |
887 | ||
888 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw) | |
889 | { | |
890 | int err; | |
891 | ||
892 | if (mw->enabled == MLX4_MPT_EN_HW) { | |
893 | err = mlx4_HW2SW_MPT(dev, NULL, | |
894 | key_to_hw_index(mw->key) & | |
895 | (dev->caps.num_mpts - 1)); | |
896 | if (err) | |
897 | mlx4_warn(dev, "xxx HW2SW_MPT failed (%d)\n", err); | |
898 | ||
899 | mw->enabled = MLX4_MPT_EN_SW; | |
900 | } | |
901 | if (mw->enabled) | |
902 | mlx4_mpt_free_icm(dev, key_to_hw_index(mw->key)); | |
903 | mlx4_mpt_release(dev, key_to_hw_index(mw->key)); | |
904 | } | |
905 | EXPORT_SYMBOL_GPL(mlx4_mw_free); | |
906 | ||
3d73c288 | 907 | int mlx4_init_mr_table(struct mlx4_dev *dev) |
225c7b1f | 908 | { |
ea51b377 JM |
909 | struct mlx4_priv *priv = mlx4_priv(dev); |
910 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f RD |
911 | int err; |
912 | ||
ea51b377 JM |
913 | /* Nothing to do for slaves - all MR handling is forwarded |
914 | * to the master */ | |
915 | if (mlx4_is_slave(dev)) | |
916 | return 0; | |
917 | ||
a30f1bc5 JM |
918 | if (!is_power_of_2(dev->caps.num_mpts)) |
919 | return -EINVAL; | |
920 | ||
225c7b1f | 921 | err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts, |
93fc9e1b | 922 | ~0, dev->caps.reserved_mrws, 0); |
225c7b1f RD |
923 | if (err) |
924 | return err; | |
925 | ||
926 | err = mlx4_buddy_init(&mr_table->mtt_buddy, | |
3de819e6 | 927 | ilog2((u32)dev->caps.num_mtts / |
2b8fb286 | 928 | (1 << log_mtts_per_seg))); |
225c7b1f RD |
929 | if (err) |
930 | goto err_buddy; | |
931 | ||
932 | if (dev->caps.reserved_mtts) { | |
ea51b377 JM |
933 | priv->reserved_mtts = |
934 | mlx4_alloc_mtt_range(dev, | |
935 | fls(dev->caps.reserved_mtts - 1)); | |
936 | if (priv->reserved_mtts < 0) { | |
1a91de28 | 937 | mlx4_warn(dev, "MTT table of order %u is too small\n", |
225c7b1f RD |
938 | mr_table->mtt_buddy.max_order); |
939 | err = -ENOMEM; | |
940 | goto err_reserve_mtts; | |
941 | } | |
942 | } | |
943 | ||
944 | return 0; | |
945 | ||
946 | err_reserve_mtts: | |
947 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); | |
948 | ||
949 | err_buddy: | |
950 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
951 | ||
952 | return err; | |
953 | } | |
954 | ||
955 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev) | |
956 | { | |
ea51b377 JM |
957 | struct mlx4_priv *priv = mlx4_priv(dev); |
958 | struct mlx4_mr_table *mr_table = &priv->mr_table; | |
225c7b1f | 959 | |
ea51b377 JM |
960 | if (mlx4_is_slave(dev)) |
961 | return; | |
962 | if (priv->reserved_mtts >= 0) | |
963 | mlx4_free_mtt_range(dev, priv->reserved_mtts, | |
964 | fls(dev->caps.reserved_mtts - 1)); | |
225c7b1f RD |
965 | mlx4_buddy_cleanup(&mr_table->mtt_buddy); |
966 | mlx4_bitmap_cleanup(&mr_table->mpt_bitmap); | |
967 | } | |
8ad11fb6 JM |
968 | |
969 | static inline int mlx4_check_fmr(struct mlx4_fmr *fmr, u64 *page_list, | |
970 | int npages, u64 iova) | |
971 | { | |
972 | int i, page_mask; | |
973 | ||
974 | if (npages > fmr->max_pages) | |
975 | return -EINVAL; | |
976 | ||
977 | page_mask = (1 << fmr->page_shift) - 1; | |
978 | ||
979 | /* We are getting page lists, so va must be page aligned. */ | |
980 | if (iova & page_mask) | |
981 | return -EINVAL; | |
982 | ||
983 | /* Trust the user not to pass misaligned data in page_list */ | |
984 | if (0) | |
985 | for (i = 0; i < npages; ++i) { | |
986 | if (page_list[i] & ~page_mask) | |
987 | return -EINVAL; | |
988 | } | |
989 | ||
990 | if (fmr->maps >= fmr->max_maps) | |
991 | return -EINVAL; | |
992 | ||
993 | return 0; | |
994 | } | |
995 | ||
996 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, | |
997 | int npages, u64 iova, u32 *lkey, u32 *rkey) | |
998 | { | |
999 | u32 key; | |
1000 | int i, err; | |
1001 | ||
1002 | err = mlx4_check_fmr(fmr, page_list, npages, iova); | |
1003 | if (err) | |
1004 | return err; | |
1005 | ||
1006 | ++fmr->maps; | |
1007 | ||
1008 | key = key_to_hw_index(fmr->mr.key); | |
1009 | key += dev->caps.num_mpts; | |
1010 | *lkey = *rkey = fmr->mr.key = hw_index_to_key(key); | |
1011 | ||
1012 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_SW; | |
1013 | ||
1014 | /* Make sure MPT status is visible before writing MTT entries */ | |
1015 | wmb(); | |
1016 | ||
e727f5cd RD |
1017 | dma_sync_single_for_cpu(&dev->pdev->dev, fmr->dma_handle, |
1018 | npages * sizeof(u64), DMA_TO_DEVICE); | |
1019 | ||
8ad11fb6 JM |
1020 | for (i = 0; i < npages; ++i) |
1021 | fmr->mtts[i] = cpu_to_be64(page_list[i] | MLX4_MTT_FLAG_PRESENT); | |
1022 | ||
e727f5cd RD |
1023 | dma_sync_single_for_device(&dev->pdev->dev, fmr->dma_handle, |
1024 | npages * sizeof(u64), DMA_TO_DEVICE); | |
8ad11fb6 JM |
1025 | |
1026 | fmr->mpt->key = cpu_to_be32(key); | |
1027 | fmr->mpt->lkey = cpu_to_be32(key); | |
1028 | fmr->mpt->length = cpu_to_be64(npages * (1ull << fmr->page_shift)); | |
1029 | fmr->mpt->start = cpu_to_be64(iova); | |
1030 | ||
1031 | /* Make MTT entries are visible before setting MPT status */ | |
1032 | wmb(); | |
1033 | ||
1034 | *(u8 *) fmr->mpt = MLX4_MPT_STATUS_HW; | |
1035 | ||
1036 | /* Make sure MPT status is visible before consumer can use FMR */ | |
1037 | wmb(); | |
1038 | ||
1039 | return 0; | |
1040 | } | |
1041 | EXPORT_SYMBOL_GPL(mlx4_map_phys_fmr); | |
1042 | ||
1043 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1044 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr) | |
1045 | { | |
1046 | struct mlx4_priv *priv = mlx4_priv(dev); | |
8ad11fb6 JM |
1047 | int err = -ENOMEM; |
1048 | ||
a5bbe892 EC |
1049 | if (max_maps > dev->caps.max_fmr_maps) |
1050 | return -EINVAL; | |
1051 | ||
c5057ddc | 1052 | if (page_shift < (ffs(dev->caps.page_size_cap) - 1) || page_shift >= 32) |
8ad11fb6 JM |
1053 | return -EINVAL; |
1054 | ||
1055 | /* All MTTs must fit in the same page */ | |
1056 | if (max_pages * sizeof *fmr->mtts > PAGE_SIZE) | |
1057 | return -EINVAL; | |
1058 | ||
1059 | fmr->page_shift = page_shift; | |
1060 | fmr->max_pages = max_pages; | |
1061 | fmr->max_maps = max_maps; | |
1062 | fmr->maps = 0; | |
1063 | ||
1064 | err = mlx4_mr_alloc(dev, pd, 0, 0, access, max_pages, | |
1065 | page_shift, &fmr->mr); | |
1066 | if (err) | |
1067 | return err; | |
1068 | ||
8ad11fb6 | 1069 | fmr->mtts = mlx4_table_find(&priv->mr_table.mtt_table, |
2b8fb286 | 1070 | fmr->mr.mtt.offset, |
8ad11fb6 | 1071 | &fmr->dma_handle); |
2b8fb286 | 1072 | |
8ad11fb6 JM |
1073 | if (!fmr->mtts) { |
1074 | err = -ENOMEM; | |
1075 | goto err_free; | |
1076 | } | |
1077 | ||
8ad11fb6 JM |
1078 | return 0; |
1079 | ||
1080 | err_free: | |
61083720 | 1081 | (void) mlx4_mr_free(dev, &fmr->mr); |
8ad11fb6 JM |
1082 | return err; |
1083 | } | |
1084 | EXPORT_SYMBOL_GPL(mlx4_fmr_alloc); | |
1085 | ||
1086 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1087 | { | |
11e75a74 JM |
1088 | struct mlx4_priv *priv = mlx4_priv(dev); |
1089 | int err; | |
1090 | ||
1091 | err = mlx4_mr_enable(dev, &fmr->mr); | |
1092 | if (err) | |
1093 | return err; | |
1094 | ||
1095 | fmr->mpt = mlx4_table_find(&priv->mr_table.dmpt_table, | |
1096 | key_to_hw_index(fmr->mr.key), NULL); | |
1097 | if (!fmr->mpt) | |
1098 | return -ENOMEM; | |
1099 | ||
1100 | return 0; | |
8ad11fb6 JM |
1101 | } |
1102 | EXPORT_SYMBOL_GPL(mlx4_fmr_enable); | |
1103 | ||
1104 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1105 | u32 *lkey, u32 *rkey) | |
1106 | { | |
ea51b377 JM |
1107 | struct mlx4_cmd_mailbox *mailbox; |
1108 | int err; | |
1109 | ||
8ad11fb6 JM |
1110 | if (!fmr->maps) |
1111 | return; | |
1112 | ||
8ad11fb6 JM |
1113 | fmr->maps = 0; |
1114 | ||
ea51b377 JM |
1115 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1116 | if (IS_ERR(mailbox)) { | |
1117 | err = PTR_ERR(mailbox); | |
c20862c8 | 1118 | pr_warn("mlx4_ib: mlx4_alloc_cmd_mailbox failed (%d)\n", err); |
ea51b377 JM |
1119 | return; |
1120 | } | |
1121 | ||
1122 | err = mlx4_HW2SW_MPT(dev, NULL, | |
1123 | key_to_hw_index(fmr->mr.key) & | |
1124 | (dev->caps.num_mpts - 1)); | |
1125 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1126 | if (err) { | |
c20862c8 | 1127 | pr_warn("mlx4_ib: mlx4_HW2SW_MPT failed (%d)\n", err); |
ea51b377 JM |
1128 | return; |
1129 | } | |
b20e519a | 1130 | fmr->mr.enabled = MLX4_MPT_EN_SW; |
8ad11fb6 JM |
1131 | } |
1132 | EXPORT_SYMBOL_GPL(mlx4_fmr_unmap); | |
1133 | ||
1134 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr) | |
1135 | { | |
61083720 SM |
1136 | int ret; |
1137 | ||
8ad11fb6 JM |
1138 | if (fmr->maps) |
1139 | return -EBUSY; | |
1140 | ||
61083720 SM |
1141 | ret = mlx4_mr_free(dev, &fmr->mr); |
1142 | if (ret) | |
1143 | return ret; | |
b20e519a | 1144 | fmr->mr.enabled = MLX4_MPT_DISABLED; |
8ad11fb6 JM |
1145 | |
1146 | return 0; | |
1147 | } | |
1148 | EXPORT_SYMBOL_GPL(mlx4_fmr_free); | |
1149 | ||
1150 | int mlx4_SYNC_TPT(struct mlx4_dev *dev) | |
1151 | { | |
f9baff50 | 1152 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_SYNC_TPT, 1000, |
5e92d803 | 1153 | MLX4_CMD_NATIVE); |
8ad11fb6 JM |
1154 | } |
1155 | EXPORT_SYMBOL_GPL(mlx4_SYNC_TPT); |