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net/mlx4: Add reference counting to MAC registeration
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
0ff1fb65
HHZ		 57#define MLX4_FS_UDP_UC_EN (1 << 1)
58#define MLX4_FS_TCP_UC_EN (1 << 2)
59#define MLX4_FS_NUM_OF_L2_ADDR 8
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17)
62
e448834e
SM		 63#define INIT_HCA_TPT_MW_ENABLE (1 << 7)
64
e5395e92
AV		 65#define MLX4_NUM_UP 8
66#define MLX4_NUM_TC 8
67#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
68#define MLX4_RATELIMIT_DEFAULT 0xffff
69
70struct mlx4_set_port_prio2tc_context {
71 u8 prio2tc[4];
72};
73
74struct mlx4_port_scheduler_tc_cfg_be {
75 __be16 pg;
76 __be16 bw_precentage;
77 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
78 __be16 max_bw_value;
79};
80
81struct mlx4_set_port_scheduler_context {
82 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
83};
84
225c7b1f
RD		 85enum {
86 MLX4_HCR_BASE = 0x80680,
87 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 88 MLX4_CLR_INT_SIZE = 0x00008,
89 MLX4_SLAVE_COMM_BASE = 0x0,
ddd8a6c1
EE		 90 MLX4_COMM_PAGESIZE = 0x1000,
91 MLX4_CLOCK_SIZE = 0x00008
225c7b1f
RD		 92};
93
225c7b1f 94enum {
3c439b55
JM		 95 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10,
96 MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7,
97 MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12,
98 MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2),
0ec2c0f8 99 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 100};
101
225c7b1f
RD		 102enum {
103 MLX4_NUM_PDS = 1 << 15
104};
105
106enum {
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
111 MLX4_CMPT_NUM_TYPE
112};
113
114enum {
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
117};
118
b20e519a
SM		 119enum mlx4_mpt_state {
120 MLX4_MPT_DISABLED = 0,
121 MLX4_MPT_EN_HW,
122 MLX4_MPT_EN_SW
623ed84b
JM		 123};
124
125#define MLX4_COMM_TIME 10000
126enum {
127 MLX4_COMM_CMD_RESET,
128 MLX4_COMM_CMD_VHCR0,
129 MLX4_COMM_CMD_VHCR1,
130 MLX4_COMM_CMD_VHCR2,
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
134};
135
136/*The flag indicates that the slave should delay the RESET cmd*/
137#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138/*indicates how many retries will be done if we are in the middle of FLR*/
139#define NUM_OF_RESET_RETRIES 10
140#define SLEEP_TIME_IN_RESET (2 * 1000)
141enum mlx4_resource {
142 RES_QP,
143 RES_CQ,
144 RES_SRQ,
145 RES_XRCD,
146 RES_MPT,
147 RES_MTT,
148 RES_MAC,
149 RES_VLAN,
150 RES_EQ,
151 RES_COUNTER,
1b9c6b06 152 RES_FS_RULE,
623ed84b
JM		 153 MLX4_NUM_OF_RESOURCE_TYPE
154};
155
156enum mlx4_alloc_mode {
157 RES_OP_RESERVE,
158 RES_OP_RESERVE_AND_MAP,
159 RES_OP_MAP_ICM,
160};
161
b8924951
JM		 162enum mlx4_res_tracker_free_type {
163 RES_TR_FREE_ALL,
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
166};
623ed84b
JM		 167
168/*
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
171 *
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
176 */
177struct mlx4_vhcr {
178 u64 in_param;
179 u64 out_param;
180 u32 in_modifier;
181 u32 errno;
182 u16 op;
183 u16 token;
184 u8 op_modifier;
185 u8 e_bit;
186};
187
188struct mlx4_vhcr_cmd {
189 __be64 in_param;
190 __be32 in_modifier;
191 __be64 out_param;
192 __be16 token;
193 u16 reserved;
194 u8 status;
195 u8 flags;
196 __be16 opcode;
197};
198
199struct mlx4_cmd_info {
200 u16 opcode;
201 bool has_inbox;
202 bool has_outbox;
203 bool out_is_imm;
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
211};
212
225c7b1f
RD		 213#ifdef CONFIG_MLX4_DEBUG
214extern int mlx4_debug_level;
7b0f5df4
RD		 215#else /* CONFIG_MLX4_DEBUG */
216#define mlx4_debug_level (0)
217#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 218
219#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 220do { \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
223} while (0)
225c7b1f 224
225c7b1f 225#define mlx4_err(mdev, format, arg...) \
0a645e80 226 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 227#define mlx4_info(mdev, format, arg...) \
0a645e80 228 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 229#define mlx4_warn(mdev, format, arg...) \
0a645e80 230 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 231
0ec2c0f8 232extern int mlx4_log_num_mgm_entry_size;
2b8fb286 233extern int log_mtts_per_seg;
0ec2c0f8 234
623ed84b
JM		 235#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236#define ALL_SLAVES 0xff
237
225c7b1f
RD		 238struct mlx4_bitmap {
239 u32 last;
240 u32 top;
241 u32 max;
93fc9e1b 242 u32 reserved_top;
225c7b1f 243 u32 mask;
42d1e017 244 u32 avail;
225c7b1f
RD		 245 spinlock_t lock;
246 unsigned long *table;
247};
248
249struct mlx4_buddy {
250 unsigned long **bits;
e4044cfc 251 unsigned int *num_free;
3de819e6 252 u32 max_order;
225c7b1f
RD		 253 spinlock_t lock;
254};
255
256struct mlx4_icm;
257
258struct mlx4_icm_table {
259 u64 virt;
260 int num_icm;
3de819e6 261 u32 num_obj;
225c7b1f
RD		 262 int obj_size;
263 int lowmem;
5b0bf5e2 264 int coherent;
225c7b1f
RD		 265 struct mutex mutex;
266 struct mlx4_icm **icm;
267};
268
cc1ade94
SM		 269#define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
270#define MLX4_MPT_FLAG_FREE (0x3UL << 28)
271#define MLX4_MPT_FLAG_MIO (1 << 17)
272#define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
273#define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
274#define MLX4_MPT_FLAG_REGION (1 << 8)
275
276#define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27)
277#define MLX4_MPT_PD_FLAG_RAE (1 << 28)
278#define MLX4_MPT_PD_FLAG_EN_INV (3 << 24)
279
280#define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7)
281
282#define MLX4_MPT_STATUS_SW 0xF0
283#define MLX4_MPT_STATUS_HW 0x00
284
c82e9aa0
EC		 285/*
286 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
287 */
288struct mlx4_mpt_entry {
289 __be32 flags;
290 __be32 qpn;
291 __be32 key;
292 __be32 pd_flags;
293 __be64 start;
294 __be64 length;
295 __be32 lkey;
296 __be32 win_cnt;
297 u8 reserved1[3];
298 u8 mtt_rep;
2b8fb286 299 __be64 mtt_addr;
c82e9aa0
EC		 300 __be32 mtt_sz;
301 __be32 entity_size;
302 __be32 first_byte_offset;
303} __packed;
304
305/*
306 * Must be packed because start is 64 bits but only aligned to 32 bits.
307 */
308struct mlx4_eq_context {
309 __be32 flags;
310 u16 reserved1[3];
311 __be16 page_offset;
312 u8 log_eq_size;
313 u8 reserved2[4];
314 u8 eq_period;
315 u8 reserved3;
316 u8 eq_max_count;
317 u8 reserved4[3];
318 u8 intr;
319 u8 log_page_size;
320 u8 reserved5[2];
321 u8 mtt_base_addr_h;
322 __be32 mtt_base_addr_l;
323 u32 reserved6[2];
324 __be32 consumer_index;
325 __be32 producer_index;
326 u32 reserved7[4];
327};
328
329struct mlx4_cq_context {
330 __be32 flags;
331 u16 reserved1[3];
332 __be16 page_offset;
333 __be32 logsize_usrpage;
334 __be16 cq_period;
335 __be16 cq_max_count;
336 u8 reserved2[3];
337 u8 comp_eqn;
338 u8 log_page_size;
339 u8 reserved3[2];
340 u8 mtt_base_addr_h;
341 __be32 mtt_base_addr_l;
342 __be32 last_notified_index;
343 __be32 solicit_producer_index;
344 __be32 consumer_index;
345 __be32 producer_index;
346 u32 reserved4[2];
347 __be64 db_rec_addr;
348};
349
350struct mlx4_srq_context {
351 __be32 state_logsize_srqn;
352 u8 logstride;
353 u8 reserved1;
354 __be16 xrcd;
355 __be32 pg_offset_cqn;
356 u32 reserved2;
357 u8 log_page_size;
358 u8 reserved3[2];
359 u8 mtt_base_addr_h;
360 __be32 mtt_base_addr_l;
361 __be32 pd;
362 __be16 limit_watermark;
363 __be16 wqe_cnt;
364 u16 reserved4;
365 __be16 wqe_counter;
366 u32 reserved5;
367 __be64 db_rec_addr;
368};
369
225c7b1f
RD		 370struct mlx4_eq {
371 struct mlx4_dev *dev;
372 void __iomem *doorbell;
373 int eqn;
374 u32 cons_index;
375 u16 irq;
376 u16 have_irq;
377 int nent;
378 struct mlx4_buf_list *page_list;
379 struct mlx4_mtt mtt;
380};
381
623ed84b
JM		 382struct mlx4_slave_eqe {
383 u8 type;
384 u8 port;
385 u32 param;
386};
387
388struct mlx4_slave_event_eq_info {
803143fb 389 int eqn;
623ed84b 390 u16 token;
623ed84b
JM		 391};
392
225c7b1f
RD		 393struct mlx4_profile {
394 int num_qp;
395 int rdmarc_per_qp;
396 int num_srq;
397 int num_cq;
398 int num_mcg;
399 int num_mpt;
db5a7a65 400 unsigned num_mtt;
225c7b1f
RD		 401};
402
403struct mlx4_fw {
404 u64 clr_int_base;
405 u64 catas_offset;
623ed84b 406 u64 comm_base;
ddd8a6c1 407 u64 clock_offset;
225c7b1f
RD		 408 struct mlx4_icm *fw_icm;
409 struct mlx4_icm *aux_icm;
410 u32 catas_size;
411 u16 fw_pages;
412 u8 clr_int_bar;
413 u8 catas_bar;
623ed84b 414 u8 comm_bar;
ddd8a6c1 415 u8 clock_bar;
623ed84b
JM		 416};
417
418struct mlx4_comm {
419 u32 slave_write;
420 u32 slave_read;
225c7b1f
RD		 421};
422
ffe455ad
EE		 423enum {
424 MLX4_MCAST_CONFIG = 0,
425 MLX4_MCAST_DISABLE = 1,
426 MLX4_MCAST_ENABLE = 2,
427};
428
623ed84b
JM		 429#define VLAN_FLTR_SIZE 128
430
431struct mlx4_vlan_fltr {
432 __be32 entry[VLAN_FLTR_SIZE];
433};
434
ffe455ad
EE		 435struct mlx4_mcast_entry {
436 struct list_head list;
437 u64 addr;
438};
439
b12d93d6
YP		 440struct mlx4_promisc_qp {
441 struct list_head list;
442 u32 qpn;
443};
444
445struct mlx4_steer_index {
446 struct list_head list;
447 unsigned int index;
448 struct list_head duplicates;
449};
450
803143fb
MA		 451#define MLX4_EVENT_TYPES_NUM 64
452
623ed84b
JM		 453struct mlx4_slave_state {
454 u8 comm_toggle;
455 u8 last_cmd;
456 u8 init_port_mask;
457 bool active;
458 u8 function;
459 dma_addr_t vhcr_dma;
460 u16 mtu[MLX4_MAX_PORTS + 1];
461 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
462 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
463 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
464 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 465 /* event type to eq number lookup */
466 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 467 u16 eq_pi;
468 u16 eq_ci;
469 spinlock_t lock;
470 /*initialized via the kzalloc*/
471 u8 is_slave_going_down;
472 u32 cookie;
993c401e 473 enum slave_port_state port_state[MLX4_MAX_PORTS + 1];
623ed84b
JM		 474};
475
476struct slave_list {
477 struct mutex mutex;
478 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
479};
480
481struct mlx4_resource_tracker {
482 spinlock_t lock;
483 /* tree for each resources */
4af1c048 484 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 485 /* num_of_slave's lists, one per slave */
486 struct slave_list *slave_list;
487};
488
489#define SLAVE_EVENT_EQ_SIZE 128
490struct mlx4_slave_event_eq {
491 u32 eqn;
492 u32 cons;
493 u32 prod;
992e8e6e 494 spinlock_t event_lock;
623ed84b
JM		 495 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
496};
497
498struct mlx4_master_qp0_state {
499 int proxy_qp0_active;
500 int qp0_active;
501 int port_active;
502};
503
504struct mlx4_mfunc_master_ctx {
505 struct mlx4_slave_state *slave_state;
506 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
507 int init_port_ref[MLX4_MAX_PORTS + 1];
508 u16 max_mtu[MLX4_MAX_PORTS + 1];
509 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
510 struct mlx4_resource_tracker res_tracker;
511 struct workqueue_struct *comm_wq;
512 struct work_struct comm_work;
513 struct work_struct slave_event_work;
514 struct work_struct slave_flr_event_work;
515 spinlock_t slave_state_lock;
f5311ac1 516 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 517 struct mlx4_eqe cmd_eqe;
518 struct mlx4_slave_event_eq slave_eq;
519 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
520};
521
522struct mlx4_mfunc {
523 struct mlx4_comm __iomem *comm;
524 struct mlx4_vhcr_cmd *vhcr;
525 dma_addr_t vhcr_dma;
526
527 struct mlx4_mfunc_master_ctx master;
528};
529
225c7b1f
RD		 530struct mlx4_cmd {
531 struct pci_pool *pool;
532 void __iomem *hcr;
533 struct mutex hcr_mutex;
f3d4c89e 534 struct mutex slave_cmd_mutex;
225c7b1f
RD		 535 struct semaphore poll_sem;
536 struct semaphore event_sem;
537 int max_cmds;
538 spinlock_t context_lock;
539 int free_head;
540 struct mlx4_cmd_context *context;
541 u16 token_mask;
542 u8 use_events;
543 u8 toggle;
623ed84b 544 u8 comm_toggle;
225c7b1f
RD		 545};
546
547struct mlx4_uar_table {
548 struct mlx4_bitmap bitmap;
549};
550
551struct mlx4_mr_table {
552 struct mlx4_bitmap mpt_bitmap;
553 struct mlx4_buddy mtt_buddy;
554 u64 mtt_base;
555 u64 mpt_base;
556 struct mlx4_icm_table mtt_table;
557 struct mlx4_icm_table dmpt_table;
558};
559
560struct mlx4_cq_table {
561 struct mlx4_bitmap bitmap;
562 spinlock_t lock;
563 struct radix_tree_root tree;
564 struct mlx4_icm_table table;
565 struct mlx4_icm_table cmpt_table;
566};
567
568struct mlx4_eq_table {
569 struct mlx4_bitmap bitmap;
b8dd786f 570 char *irq_names;
225c7b1f 571 void __iomem *clr_int;
b8dd786f 572 void __iomem **uar_map;
225c7b1f 573 u32 clr_mask;
b8dd786f 574 struct mlx4_eq *eq;
fa0681d2 575 struct mlx4_icm_table table;
225c7b1f
RD		 576 struct mlx4_icm_table cmpt_table;
577 int have_irq;
578 u8 inta_pin;
579};
580
581struct mlx4_srq_table {
582 struct mlx4_bitmap bitmap;
583 spinlock_t lock;
584 struct radix_tree_root tree;
585 struct mlx4_icm_table table;
586 struct mlx4_icm_table cmpt_table;
587};
588
589struct mlx4_qp_table {
590 struct mlx4_bitmap bitmap;
591 u32 rdmarc_base;
592 int rdmarc_shift;
593 spinlock_t lock;
594 struct mlx4_icm_table qp_table;
595 struct mlx4_icm_table auxc_table;
596 struct mlx4_icm_table altc_table;
597 struct mlx4_icm_table rdmarc_table;
598 struct mlx4_icm_table cmpt_table;
599};
600
601struct mlx4_mcg_table {
602 struct mutex mutex;
603 struct mlx4_bitmap bitmap;
604 struct mlx4_icm_table table;
605};
606
607struct mlx4_catas_err {
608 u32 __iomem *map;
ee49bd93
JM		 609 struct timer_list timer;
610 struct list_head list;
225c7b1f
RD		 611};
612
2a2336f8
YP		 613#define MLX4_MAX_MAC_NUM 128
614#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
615
616struct mlx4_mac_table {
617 __be64 entries[MLX4_MAX_MAC_NUM];
618 int refs[MLX4_MAX_MAC_NUM];
619 struct mutex mutex;
620 int total;
621 int max;
622};
623
624#define MLX4_MAX_VLAN_NUM 128
625#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
626
627struct mlx4_vlan_table {
628 __be32 entries[MLX4_MAX_VLAN_NUM];
629 int refs[MLX4_MAX_VLAN_NUM];
630 struct mutex mutex;
631 int total;
632 int max;
633};
634
ffe455ad
EE		 635#define SET_PORT_GEN_ALL_VALID 0x7
636#define SET_PORT_PROMISC_SHIFT 31
637#define SET_PORT_MC_PROMISC_SHIFT 30
638
639enum {
640 MCAST_DIRECT_ONLY = 0,
641 MCAST_DIRECT = 1,
642 MCAST_DEFAULT = 2
643};
644
645
646struct mlx4_set_port_general_context {
647 u8 reserved[3];
648 u8 flags;
649 u16 reserved2;
650 __be16 mtu;
651 u8 pptx;
652 u8 pfctx;
653 u16 reserved3;
654 u8 pprx;
655 u8 pfcrx;
656 u16 reserved4;
657};
658
659struct mlx4_set_port_rqp_calc_context {
660 __be32 base_qpn;
661 u8 rererved;
662 u8 n_mac;
663 u8 n_vlan;
664 u8 n_prio;
665 u8 reserved2[3];
666 u8 mac_miss;
667 u8 intra_no_vlan;
668 u8 no_vlan;
669 u8 intra_vlan_miss;
670 u8 vlan_miss;
671 u8 reserved3[3];
672 u8 no_vlan_prio;
673 __be32 promisc;
674 __be32 mcast;
675};
676
2a2336f8
YP		 677struct mlx4_port_info {
678 struct mlx4_dev *dev;
679 int port;
7ff93f8b
YP		 680 char dev_name[16];
681 struct device_attribute port_attr;
682 enum mlx4_port_type tmp_type;
096335b3
OG		 683 char dev_mtu_name[16];
684 struct device_attribute port_mtu_attr;
2a2336f8
YP		 685 struct mlx4_mac_table mac_table;
686 struct mlx4_vlan_table vlan_table;
1679200f 687 int base_qpn;
2a2336f8
YP		 688};
689
27bf91d6
YP		 690struct mlx4_sense {
691 struct mlx4_dev *dev;
692 u8 do_sense_port[MLX4_MAX_PORTS + 1];
693 u8 sense_allowed[MLX4_MAX_PORTS + 1];
694 struct delayed_work sense_poll;
695};
696
0b7ca5a9
YP		 697struct mlx4_msix_ctl {
698 u64 pool_bm;
730c41d5 699 struct mutex pool_lock;
0b7ca5a9
YP		 700};
701
b12d93d6
YP		 702struct mlx4_steer {
703 struct list_head promisc_qps[MLX4_NUM_STEERS];
704 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 705};
706
a8edc3bf
HHZ		 707struct mlx4_net_trans_rule_hw_ctrl {
708 __be32 ctrl;
015465f8
HHZ		 709 u8 rsvd1;
710 u8 funcid;
711 u8 vep;
712 u8 port;
a8edc3bf 713 __be32 qpn;
015465f8 714 __be32 rsvd2;
a8edc3bf
HHZ		 715};
716
717struct mlx4_net_trans_rule_hw_ib {
718 u8 size;
719 u8 rsvd1;
720 __be16 id;
721 u32 rsvd2;
722 __be32 qpn;
723 __be32 qpn_mask;
724 u8 dst_gid[16];
725 u8 dst_gid_msk[16];
726} __packed;
727
728struct mlx4_net_trans_rule_hw_eth {
729 u8 size;
730 u8 rsvd;
731 __be16 id;
732 u8 rsvd1[6];
733 u8 dst_mac[6];
734 u16 rsvd2;
735 u8 dst_mac_msk[6];
736 u16 rsvd3;
737 u8 src_mac[6];
738 u16 rsvd4;
739 u8 src_mac_msk[6];
740 u8 rsvd5;
741 u8 ether_type_enable;
742 __be16 ether_type;
743 __be16 vlan_id_msk;
744 __be16 vlan_id;
745} __packed;
746
747struct mlx4_net_trans_rule_hw_tcp_udp {
748 u8 size;
749 u8 rsvd;
750 __be16 id;
751 __be16 rsvd1[3];
752 __be16 dst_port;
753 __be16 rsvd2;
754 __be16 dst_port_msk;
755 __be16 rsvd3;
756 __be16 src_port;
757 __be16 rsvd4;
758 __be16 src_port_msk;
759} __packed;
760
761struct mlx4_net_trans_rule_hw_ipv4 {
762 u8 size;
763 u8 rsvd;
764 __be16 id;
765 __be32 rsvd1;
766 __be32 dst_ip;
767 __be32 dst_ip_msk;
768 __be32 src_ip;
769 __be32 src_ip_msk;
770} __packed;
771
772struct _rule_hw {
773 union {
774 struct {
775 u8 size;
776 u8 rsvd;
777 __be16 id;
778 };
779 struct mlx4_net_trans_rule_hw_eth eth;
780 struct mlx4_net_trans_rule_hw_ib ib;
781 struct mlx4_net_trans_rule_hw_ipv4 ipv4;
782 struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp;
783 };
784};
785
839f1243
RD		 786enum {
787 MLX4_PCI_DEV_IS_VF = 1 << 0,
ca3e57a5 788 MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1,
839f1243
RD		 789};
790
225c7b1f
RD		 791struct mlx4_priv {
792 struct mlx4_dev dev;
793
794 struct list_head dev_list;
795 struct list_head ctx_list;
796 spinlock_t ctx_lock;
797
839f1243
RD		 798 int pci_dev_data;
799
6296883c
YP		 800 struct list_head pgdir_list;
801 struct mutex pgdir_mutex;
802
225c7b1f
RD		 803 struct mlx4_fw fw;
804 struct mlx4_cmd cmd;
623ed84b 805 struct mlx4_mfunc mfunc;
225c7b1f
RD		 806
807 struct mlx4_bitmap pd_bitmap;
012a8ff5 808 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 809 struct mlx4_uar_table uar_table;
810 struct mlx4_mr_table mr_table;
811 struct mlx4_cq_table cq_table;
812 struct mlx4_eq_table eq_table;
813 struct mlx4_srq_table srq_table;
814 struct mlx4_qp_table qp_table;
815 struct mlx4_mcg_table mcg_table;
f2a3f6a3 816 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 817
818 struct mlx4_catas_err catas_err;
819
820 void __iomem *clr_base;
821
822 struct mlx4_uar driver_uar;
823 void __iomem *kar;
2a2336f8 824 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 825 struct mlx4_sense sense;
7ff93f8b 826 struct mutex port_mutex;
0b7ca5a9 827 struct mlx4_msix_ctl msix_ctl;
b12d93d6 828 struct mlx4_steer *steer;
c1b43dca
EC		 829 struct list_head bf_list;
830 struct mutex bf_mutex;
831 struct io_mapping *bf_mapping;
ddd8a6c1 832 void __iomem *clock_mapping;
ea51b377 833 int reserved_mtts;
0ff1fb65 834 int fs_hash_mode;
54679e14 835 u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS];
afa8fd1d 836 __be64 slave_node_guids[MLX4_MFUNC_MAX];
54679e14 837
225c7b1f
RD		 838};
839
840static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
841{
842 return container_of(dev, struct mlx4_priv, dev);
843}
844
27bf91d6
YP		 845#define MLX4_SENSE_RANGE (HZ * 3)
846
847extern struct workqueue_struct *mlx4_wq;
848
225c7b1f
RD		 849u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
850void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 851u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
852void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 853u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 854int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
855 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 856void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
857
858int mlx4_reset(struct mlx4_dev *dev);
859
b8dd786f
YP		 860int mlx4_alloc_eq_table(struct mlx4_dev *dev);
861void mlx4_free_eq_table(struct mlx4_dev *dev);
862
225c7b1f 863int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 864int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 865int mlx4_init_uar_table(struct mlx4_dev *dev);
866int mlx4_init_mr_table(struct mlx4_dev *dev);
867int mlx4_init_eq_table(struct mlx4_dev *dev);
868int mlx4_init_cq_table(struct mlx4_dev *dev);
869int mlx4_init_qp_table(struct mlx4_dev *dev);
870int mlx4_init_srq_table(struct mlx4_dev *dev);
871int mlx4_init_mcg_table(struct mlx4_dev *dev);
872
873void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 874void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 875void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
876void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
877void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
878void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
879void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
880void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
881void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 882int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
883void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
884int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
885void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
886int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
887void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
b20e519a
SM		 888int __mlx4_mpt_reserve(struct mlx4_dev *dev);
889void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index);
890int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index);
891void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index);
c82e9aa0
EC		 892u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
893void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 894
623ed84b
JM		 895int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
896 struct mlx4_vhcr *vhcr,
897 struct mlx4_cmd_mailbox *inbox,
898 struct mlx4_cmd_mailbox *outbox,
899 struct mlx4_cmd_info *cmd);
900int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
901 struct mlx4_vhcr *vhcr,
902 struct mlx4_cmd_mailbox *inbox,
903 struct mlx4_cmd_mailbox *outbox,
904 struct mlx4_cmd_info *cmd);
905int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
906 struct mlx4_vhcr *vhcr,
907 struct mlx4_cmd_mailbox *inbox,
908 struct mlx4_cmd_mailbox *outbox,
909 struct mlx4_cmd_info *cmd);
910int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
911 struct mlx4_vhcr *vhcr,
912 struct mlx4_cmd_mailbox *inbox,
913 struct mlx4_cmd_mailbox *outbox,
914 struct mlx4_cmd_info *cmd);
915int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
916 struct mlx4_vhcr *vhcr,
917 struct mlx4_cmd_mailbox *inbox,
918 struct mlx4_cmd_mailbox *outbox,
919 struct mlx4_cmd_info *cmd);
920int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
921 struct mlx4_vhcr *vhcr,
922 struct mlx4_cmd_mailbox *inbox,
923 struct mlx4_cmd_mailbox *outbox,
924 struct mlx4_cmd_info *cmd);
925int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
926 struct mlx4_vhcr *vhcr,
927 struct mlx4_cmd_mailbox *inbox,
928 struct mlx4_cmd_mailbox *outbox,
929 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 930int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
931 int *base);
932void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
933int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
934void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
c82e9aa0
EC		 935int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
936 int start_index, int npages, u64 *page_list);
ba062d52
JM		 937int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
938void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
939int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
940void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 941
ee49bd93
JM		 942void mlx4_start_catas_poll(struct mlx4_dev *dev);
943void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 944void mlx4_catas_init(void);
ee49bd93 945int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 946int mlx4_register_device(struct mlx4_dev *dev);
947void mlx4_unregister_device(struct mlx4_dev *dev);
00f5ce99
JM		 948void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type,
949 unsigned long param);
225c7b1f
RD		 950
951struct mlx4_dev_cap;
952struct mlx4_init_hca_param;
953
954u64 mlx4_make_profile(struct mlx4_dev *dev,
955 struct mlx4_profile *request,
956 struct mlx4_dev_cap *dev_cap,
957 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 958void mlx4_master_comm_channel(struct work_struct *work);
959void mlx4_gen_slave_eqe(struct work_struct *work);
960void mlx4_master_handle_slave_flr(struct work_struct *work);
961
962int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
974 struct mlx4_cmd_mailbox *outbox,
975 struct mlx4_cmd_info *cmd);
976int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
977 struct mlx4_vhcr *vhcr,
978 struct mlx4_cmd_mailbox *inbox,
979 struct mlx4_cmd_mailbox *outbox,
980 struct mlx4_cmd_info *cmd);
981int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
982 struct mlx4_vhcr *vhcr,
983 struct mlx4_cmd_mailbox *inbox,
984 struct mlx4_cmd_mailbox *outbox,
985 struct mlx4_cmd_info *cmd);
986int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
987 struct mlx4_vhcr *vhcr,
988 struct mlx4_cmd_mailbox *inbox,
989 struct mlx4_cmd_mailbox *outbox,
990 struct mlx4_cmd_info *cmd);
991int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
992 struct mlx4_vhcr *vhcr,
993 struct mlx4_cmd_mailbox *inbox,
994 struct mlx4_cmd_mailbox *outbox,
995 struct mlx4_cmd_info *cmd);
996int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
997 struct mlx4_vhcr *vhcr,
998 struct mlx4_cmd_mailbox *inbox,
999 struct mlx4_cmd_mailbox *outbox,
1000 struct mlx4_cmd_info *cmd);
1001int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1002 struct mlx4_vhcr *vhcr,
1003 struct mlx4_cmd_mailbox *inbox,
1004 struct mlx4_cmd_mailbox *outbox,
1005 struct mlx4_cmd_info *cmd);
1006int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
1007 struct mlx4_vhcr *vhcr,
1008 struct mlx4_cmd_mailbox *inbox,
1009 struct mlx4_cmd_mailbox *outbox,
1010 struct mlx4_cmd_info *cmd);
1011int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1012 struct mlx4_vhcr *vhcr,
1013 struct mlx4_cmd_mailbox *inbox,
1014 struct mlx4_cmd_mailbox *outbox,
1015 struct mlx4_cmd_info *cmd);
1016int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1017 struct mlx4_vhcr *vhcr,
1018 struct mlx4_cmd_mailbox *inbox,
1019 struct mlx4_cmd_mailbox *outbox,
1020 struct mlx4_cmd_info *cmd);
1021int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1022 struct mlx4_vhcr *vhcr,
1023 struct mlx4_cmd_mailbox *inbox,
1024 struct mlx4_cmd_mailbox *outbox,
1025 struct mlx4_cmd_info *cmd);
1026int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
1027 struct mlx4_vhcr *vhcr,
1028 struct mlx4_cmd_mailbox *inbox,
1029 struct mlx4_cmd_mailbox *outbox,
1030 struct mlx4_cmd_info *cmd);
1031int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
1032 struct mlx4_vhcr *vhcr,
1033 struct mlx4_cmd_mailbox *inbox,
1034 struct mlx4_cmd_mailbox *outbox,
1035 struct mlx4_cmd_info *cmd);
1036int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1037 struct mlx4_vhcr *vhcr,
1038 struct mlx4_cmd_mailbox *inbox,
1039 struct mlx4_cmd_mailbox *outbox,
1040 struct mlx4_cmd_info *cmd);
54679e14
JM		 1041int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
1042 struct mlx4_vhcr *vhcr,
1043 struct mlx4_cmd_mailbox *inbox,
1044 struct mlx4_cmd_mailbox *outbox,
1045 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1046int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
1047 struct mlx4_vhcr *vhcr,
1048 struct mlx4_cmd_mailbox *inbox,
1049 struct mlx4_cmd_mailbox *outbox,
1050 struct mlx4_cmd_info *cmd);
54679e14
JM		 1051int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1052 struct mlx4_vhcr *vhcr,
1053 struct mlx4_cmd_mailbox *inbox,
1054 struct mlx4_cmd_mailbox *outbox,
1055 struct mlx4_cmd_info *cmd);
1056int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1057 struct mlx4_vhcr *vhcr,
1058 struct mlx4_cmd_mailbox *inbox,
1059 struct mlx4_cmd_mailbox *outbox,
1060 struct mlx4_cmd_info *cmd);
1061int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1062 struct mlx4_vhcr *vhcr,
1063 struct mlx4_cmd_mailbox *inbox,
1064 struct mlx4_cmd_mailbox *outbox,
1065 struct mlx4_cmd_info *cmd);
1066int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave,
1067 struct mlx4_vhcr *vhcr,
1068 struct mlx4_cmd_mailbox *inbox,
1069 struct mlx4_cmd_mailbox *outbox,
1070 struct mlx4_cmd_info *cmd);
1071int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
1076int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave,
1077 struct mlx4_vhcr *vhcr,
1078 struct mlx4_cmd_mailbox *inbox,
1079 struct mlx4_cmd_mailbox *outbox,
1080 struct mlx4_cmd_info *cmd);
1081int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1086int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1087 struct mlx4_vhcr *vhcr,
1088 struct mlx4_cmd_mailbox *inbox,
1089 struct mlx4_cmd_mailbox *outbox,
1090 struct mlx4_cmd_info *cmd);
54679e14
JM		 1091int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1096
1097int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 1098
225c7b1f
RD		 1099int mlx4_cmd_init(struct mlx4_dev *dev);
1100void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 1101int mlx4_multi_func_init(struct mlx4_dev *dev);
1102void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1103void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1104int mlx4_cmd_use_events(struct mlx4_dev *dev);
1105void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1106
ab9c17a0
JM		 1107int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1108 unsigned long timeout);
1109
225c7b1f
RD		 1110void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1111void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1112
1113void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1114
1115void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1116
1117void mlx4_handle_catas_err(struct mlx4_dev *dev);
1118
ab6dc30d
YP		 1119int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1120 enum mlx4_port_type *type);
27bf91d6
YP		 1121void mlx4_do_sense_ports(struct mlx4_dev *dev,
1122 enum mlx4_port_type *stype,
1123 enum mlx4_port_type *defaults);
1124void mlx4_start_sense(struct mlx4_dev *dev);
1125void mlx4_stop_sense(struct mlx4_dev *dev);
1126void mlx4_sense_init(struct mlx4_dev *dev);
1127int mlx4_check_port_params(struct mlx4_dev *dev,
1128 enum mlx4_port_type *port_type);
1129int mlx4_change_port_types(struct mlx4_dev *dev,
1130 enum mlx4_port_type *port_types);
1131
2a2336f8
YP		 1132void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1133void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1134
6634961c 1135int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz);
623ed84b
JM		 1136/* resource tracker functions*/
1137int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1138 enum mlx4_resource resource_type,
aa1ec3dd 1139 u64 resource_id, int *slave);
623ed84b
JM		 1140void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1141int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1142
b8924951
JM		 1143void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1144 enum mlx4_res_tracker_free_type type);
623ed84b 1145
b91cb3eb
JM		 1146int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1147 struct mlx4_vhcr *vhcr,
1148 struct mlx4_cmd_mailbox *inbox,
1149 struct mlx4_cmd_mailbox *outbox,
1150 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1151int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1152 struct mlx4_vhcr *vhcr,
1153 struct mlx4_cmd_mailbox *inbox,
1154 struct mlx4_cmd_mailbox *outbox,
1155 struct mlx4_cmd_info *cmd);
1156int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1157 struct mlx4_vhcr *vhcr,
1158 struct mlx4_cmd_mailbox *inbox,
1159 struct mlx4_cmd_mailbox *outbox,
1160 struct mlx4_cmd_info *cmd);
1161int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1162 struct mlx4_vhcr *vhcr,
1163 struct mlx4_cmd_mailbox *inbox,
1164 struct mlx4_cmd_mailbox *outbox,
1165 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1166int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1167 struct mlx4_vhcr *vhcr,
1168 struct mlx4_cmd_mailbox *inbox,
1169 struct mlx4_cmd_mailbox *outbox,
1170 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1171int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1172 struct mlx4_vhcr *vhcr,
1173 struct mlx4_cmd_mailbox *inbox,
1174 struct mlx4_cmd_mailbox *outbox,
1175 struct mlx4_cmd_info *cmd);
9a5aa622 1176int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1177
6634961c
JM		 1178int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1179 int *gid_tbl_len, int *pkey_tbl_len);
623ed84b
JM		 1180
1181int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1182 struct mlx4_vhcr *vhcr,
1183 struct mlx4_cmd_mailbox *inbox,
1184 struct mlx4_cmd_mailbox *outbox,
1185 struct mlx4_cmd_info *cmd);
1186
1187int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1188 struct mlx4_vhcr *vhcr,
1189 struct mlx4_cmd_mailbox *inbox,
1190 struct mlx4_cmd_mailbox *outbox,
1191 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1192int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1193 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1194int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1195 int block_mcast_loopback, enum mlx4_protocol prot,
1196 enum mlx4_steer_type steer);
fd91c49f
HHZ		 1197int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp,
1198 u8 gid[16], u8 port,
1199 int block_mcast_loopback,
1200 enum mlx4_protocol prot, u64 *reg_id);
623ed84b
JM		 1201int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1202 struct mlx4_vhcr *vhcr,
1203 struct mlx4_cmd_mailbox *inbox,
1204 struct mlx4_cmd_mailbox *outbox,
1205 struct mlx4_cmd_info *cmd);
1206int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1207 struct mlx4_vhcr *vhcr,
1208 struct mlx4_cmd_mailbox *inbox,
1209 struct mlx4_cmd_mailbox *outbox,
1210 struct mlx4_cmd_info *cmd);
1211int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1212 int port, void *buf);
1213int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1214 struct mlx4_cmd_mailbox *outbox);
1215int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1216 struct mlx4_vhcr *vhcr,
1217 struct mlx4_cmd_mailbox *inbox,
1218 struct mlx4_cmd_mailbox *outbox,
1219 struct mlx4_cmd_info *cmd);
1220int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1221 struct mlx4_vhcr *vhcr,
1222 struct mlx4_cmd_mailbox *inbox,
1223 struct mlx4_cmd_mailbox *outbox,
1224 struct mlx4_cmd_info *cmd);
1225int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1226 struct mlx4_vhcr *vhcr,
1227 struct mlx4_cmd_mailbox *inbox,
1228 struct mlx4_cmd_mailbox *outbox,
1229 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1230int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1231 struct mlx4_vhcr *vhcr,
1232 struct mlx4_cmd_mailbox *inbox,
1233 struct mlx4_cmd_mailbox *outbox,
1234 struct mlx4_cmd_info *cmd);
1235int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1236 struct mlx4_vhcr *vhcr,
1237 struct mlx4_cmd_mailbox *inbox,
1238 struct mlx4_cmd_mailbox *outbox,
1239 struct mlx4_cmd_info *cmd);
f5311ac1 1240
0ec2c0f8
EE		 1241int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1242int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1243
5cc914f1
MA		 1244static inline void set_param_l(u64 *arg, u32 val)
1245{
e7dbeba8 1246 *arg = (*arg & 0xffffffff00000000ULL) | (u64) val;
5cc914f1
MA		 1247}
1248
1249static inline void set_param_h(u64 *arg, u32 val)
1250{
1251 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1252}
1253
1254static inline u32 get_param_l(u64 *arg)
1255{
1256 return (u32) (*arg & 0xffffffff);
1257}
1258
1259static inline u32 get_param_h(u64 *arg)
1260{
1261 return (u32)(*arg >> 32);
1262}
1263
c82e9aa0
EC		 1264static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1265{
1266 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1267}
1268
f5311ac1
JM		 1269#define NOT_MASKED_PD_BITS 17
1270
225c7b1f 1271#endif /* MLX4_H */
Linux 6.x block layer and io_uring tree(s)