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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
4af1c048 42#include <linux/rbtree.h>
ee49bd93 43#include <linux/timer.h>
3142788b 44#include <linux/semaphore.h>
27bf91d6 45#include <linux/workqueue.h>
225c7b1f
RD		 46
47#include <linux/mlx4/device.h>
37608eea 48#include <linux/mlx4/driver.h>
225c7b1f 49#include <linux/mlx4/doorbell.h>
623ed84b 50#include <linux/mlx4/cmd.h>
225c7b1f
RD		 51
52#define DRV_NAME "mlx4_core"
ab9c17a0 53#define PFX DRV_NAME ": "
7d4b6bcc
YP		 54#define DRV_VERSION "1.1"
55#define DRV_RELDATE "Dec, 2011"
225c7b1f 56
0ff1fb65
HHZ		 57#define MLX4_FS_UDP_UC_EN (1 << 1)
58#define MLX4_FS_TCP_UC_EN (1 << 2)
59#define MLX4_FS_NUM_OF_L2_ADDR 8
60#define MLX4_FS_MGM_LOG_ENTRY_SIZE 7
61#define MLX4_FS_NUM_MCG (1 << 17)
62
63enum {
64 MLX4_FS_L2_HASH = 0,
65 MLX4_FS_L2_L3_L4_HASH,
66};
67
e5395e92
AV		 68#define MLX4_NUM_UP 8
69#define MLX4_NUM_TC 8
70#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
71#define MLX4_RATELIMIT_DEFAULT 0xffff
72
73struct mlx4_set_port_prio2tc_context {
74 u8 prio2tc[4];
75};
76
77struct mlx4_port_scheduler_tc_cfg_be {
78 __be16 pg;
79 __be16 bw_precentage;
80 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
81 __be16 max_bw_value;
82};
83
84struct mlx4_set_port_scheduler_context {
85 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
86};
87
225c7b1f
RD		 88enum {
89 MLX4_HCR_BASE = 0x80680,
90 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 91 MLX4_CLR_INT_SIZE = 0x00008,
92 MLX4_SLAVE_COMM_BASE = 0x0,
93 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 94};
95
225c7b1f 96enum {
0ec2c0f8
EE		 97 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
98 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
99 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 100};
101
225c7b1f
RD		 102enum {
103 MLX4_NUM_PDS = 1 << 15
104};
105
106enum {
107 MLX4_CMPT_TYPE_QP = 0,
108 MLX4_CMPT_TYPE_SRQ = 1,
109 MLX4_CMPT_TYPE_CQ = 2,
110 MLX4_CMPT_TYPE_EQ = 3,
111 MLX4_CMPT_NUM_TYPE
112};
113
114enum {
115 MLX4_CMPT_SHIFT = 24,
116 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
117};
118
623ed84b
JM		 119enum mlx4_mr_state {
120 MLX4_MR_DISABLED = 0,
121 MLX4_MR_EN_HW,
122 MLX4_MR_EN_SW
123};
124
125#define MLX4_COMM_TIME 10000
126enum {
127 MLX4_COMM_CMD_RESET,
128 MLX4_COMM_CMD_VHCR0,
129 MLX4_COMM_CMD_VHCR1,
130 MLX4_COMM_CMD_VHCR2,
131 MLX4_COMM_CMD_VHCR_EN,
132 MLX4_COMM_CMD_VHCR_POST,
133 MLX4_COMM_CMD_FLR = 254
134};
135
136/*The flag indicates that the slave should delay the RESET cmd*/
137#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
138/*indicates how many retries will be done if we are in the middle of FLR*/
139#define NUM_OF_RESET_RETRIES 10
140#define SLEEP_TIME_IN_RESET (2 * 1000)
141enum mlx4_resource {
142 RES_QP,
143 RES_CQ,
144 RES_SRQ,
145 RES_XRCD,
146 RES_MPT,
147 RES_MTT,
148 RES_MAC,
149 RES_VLAN,
150 RES_EQ,
151 RES_COUNTER,
1b9c6b06 152 RES_FS_RULE,
623ed84b
JM		 153 MLX4_NUM_OF_RESOURCE_TYPE
154};
155
156enum mlx4_alloc_mode {
157 RES_OP_RESERVE,
158 RES_OP_RESERVE_AND_MAP,
159 RES_OP_MAP_ICM,
160};
161
b8924951
JM		 162enum mlx4_res_tracker_free_type {
163 RES_TR_FREE_ALL,
164 RES_TR_FREE_SLAVES_ONLY,
165 RES_TR_FREE_STRUCTS_ONLY,
166};
623ed84b
JM		 167
168/*
169 *Virtual HCR structures.
170 * mlx4_vhcr is the sw representation, in machine endianess
171 *
172 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
173 * to FW to go through communication channel.
174 * It is big endian, and has the same structure as the physical HCR
175 * used by command interface
176 */
177struct mlx4_vhcr {
178 u64 in_param;
179 u64 out_param;
180 u32 in_modifier;
181 u32 errno;
182 u16 op;
183 u16 token;
184 u8 op_modifier;
185 u8 e_bit;
186};
187
188struct mlx4_vhcr_cmd {
189 __be64 in_param;
190 __be32 in_modifier;
191 __be64 out_param;
192 __be16 token;
193 u16 reserved;
194 u8 status;
195 u8 flags;
196 __be16 opcode;
197};
198
199struct mlx4_cmd_info {
200 u16 opcode;
201 bool has_inbox;
202 bool has_outbox;
203 bool out_is_imm;
204 bool encode_slave_id;
205 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
206 struct mlx4_cmd_mailbox *inbox);
207 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
208 struct mlx4_cmd_mailbox *inbox,
209 struct mlx4_cmd_mailbox *outbox,
210 struct mlx4_cmd_info *cmd);
211};
212
225c7b1f
RD		 213#ifdef CONFIG_MLX4_DEBUG
214extern int mlx4_debug_level;
7b0f5df4
RD		 215#else /* CONFIG_MLX4_DEBUG */
216#define mlx4_debug_level (0)
217#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 218
219#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 220do { \
221 if (mlx4_debug_level) \
222 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
223} while (0)
225c7b1f 224
225c7b1f 225#define mlx4_err(mdev, format, arg...) \
0a645e80 226 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 227#define mlx4_info(mdev, format, arg...) \
0a645e80 228 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 229#define mlx4_warn(mdev, format, arg...) \
0a645e80 230 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 231
0ec2c0f8 232extern int mlx4_log_num_mgm_entry_size;
2b8fb286 233extern int log_mtts_per_seg;
0ec2c0f8 234
623ed84b
JM		 235#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
236#define ALL_SLAVES 0xff
237
225c7b1f
RD		 238struct mlx4_bitmap {
239 u32 last;
240 u32 top;
241 u32 max;
93fc9e1b 242 u32 reserved_top;
225c7b1f 243 u32 mask;
42d1e017 244 u32 avail;
225c7b1f
RD		 245 spinlock_t lock;
246 unsigned long *table;
247};
248
249struct mlx4_buddy {
250 unsigned long **bits;
e4044cfc 251 unsigned int *num_free;
225c7b1f
RD		 252 int max_order;
253 spinlock_t lock;
254};
255
256struct mlx4_icm;
257
258struct mlx4_icm_table {
259 u64 virt;
260 int num_icm;
261 int num_obj;
262 int obj_size;
263 int lowmem;
5b0bf5e2 264 int coherent;
225c7b1f
RD		 265 struct mutex mutex;
266 struct mlx4_icm **icm;
267};
268
c82e9aa0
EC		 269/*
270 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
271 */
272struct mlx4_mpt_entry {
273 __be32 flags;
274 __be32 qpn;
275 __be32 key;
276 __be32 pd_flags;
277 __be64 start;
278 __be64 length;
279 __be32 lkey;
280 __be32 win_cnt;
281 u8 reserved1[3];
282 u8 mtt_rep;
2b8fb286 283 __be64 mtt_addr;
c82e9aa0
EC		 284 __be32 mtt_sz;
285 __be32 entity_size;
286 __be32 first_byte_offset;
287} __packed;
288
289/*
290 * Must be packed because start is 64 bits but only aligned to 32 bits.
291 */
292struct mlx4_eq_context {
293 __be32 flags;
294 u16 reserved1[3];
295 __be16 page_offset;
296 u8 log_eq_size;
297 u8 reserved2[4];
298 u8 eq_period;
299 u8 reserved3;
300 u8 eq_max_count;
301 u8 reserved4[3];
302 u8 intr;
303 u8 log_page_size;
304 u8 reserved5[2];
305 u8 mtt_base_addr_h;
306 __be32 mtt_base_addr_l;
307 u32 reserved6[2];
308 __be32 consumer_index;
309 __be32 producer_index;
310 u32 reserved7[4];
311};
312
313struct mlx4_cq_context {
314 __be32 flags;
315 u16 reserved1[3];
316 __be16 page_offset;
317 __be32 logsize_usrpage;
318 __be16 cq_period;
319 __be16 cq_max_count;
320 u8 reserved2[3];
321 u8 comp_eqn;
322 u8 log_page_size;
323 u8 reserved3[2];
324 u8 mtt_base_addr_h;
325 __be32 mtt_base_addr_l;
326 __be32 last_notified_index;
327 __be32 solicit_producer_index;
328 __be32 consumer_index;
329 __be32 producer_index;
330 u32 reserved4[2];
331 __be64 db_rec_addr;
332};
333
334struct mlx4_srq_context {
335 __be32 state_logsize_srqn;
336 u8 logstride;
337 u8 reserved1;
338 __be16 xrcd;
339 __be32 pg_offset_cqn;
340 u32 reserved2;
341 u8 log_page_size;
342 u8 reserved3[2];
343 u8 mtt_base_addr_h;
344 __be32 mtt_base_addr_l;
345 __be32 pd;
346 __be16 limit_watermark;
347 __be16 wqe_cnt;
348 u16 reserved4;
349 __be16 wqe_counter;
350 u32 reserved5;
351 __be64 db_rec_addr;
352};
353
623ed84b
JM		 354struct mlx4_eqe {
355 u8 reserved1;
356 u8 type;
357 u8 reserved2;
358 u8 subtype;
359 union {
360 u32 raw[6];
361 struct {
362 __be32 cqn;
363 } __packed comp;
364 struct {
365 u16 reserved1;
366 __be16 token;
367 u32 reserved2;
368 u8 reserved3[3];
369 u8 status;
370 __be64 out_param;
371 } __packed cmd;
372 struct {
373 __be32 qpn;
374 } __packed qp;
375 struct {
376 __be32 srqn;
377 } __packed srq;
378 struct {
379 __be32 cqn;
380 u32 reserved1;
381 u8 reserved2[3];
382 u8 syndrome;
383 } __packed cq_err;
384 struct {
385 u32 reserved1[2];
386 __be32 port;
387 } __packed port_change;
388 struct {
389 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
390 u32 reserved;
391 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
392 } __packed comm_channel_arm;
393 struct {
394 u8 port;
395 u8 reserved[3];
396 __be64 mac;
397 } __packed mac_update;
398 struct {
399 u8 port;
400 } __packed sw_event;
401 struct {
402 __be32 slave_id;
403 } __packed flr_event;
5984be90
JM		 404 struct {
405 __be16 current_temperature;
406 __be16 warning_threshold;
407 } __packed warming;
623ed84b
JM		 408 } event;
409 u8 slave_id;
410 u8 reserved3[2];
411 u8 owner;
412} __packed;
413
225c7b1f
RD		 414struct mlx4_eq {
415 struct mlx4_dev *dev;
416 void __iomem *doorbell;
417 int eqn;
418 u32 cons_index;
419 u16 irq;
420 u16 have_irq;
421 int nent;
422 struct mlx4_buf_list *page_list;
423 struct mlx4_mtt mtt;
424};
425
623ed84b
JM		 426struct mlx4_slave_eqe {
427 u8 type;
428 u8 port;
429 u32 param;
430};
431
432struct mlx4_slave_event_eq_info {
803143fb 433 int eqn;
623ed84b 434 u16 token;
623ed84b
JM		 435};
436
225c7b1f
RD		 437struct mlx4_profile {
438 int num_qp;
439 int rdmarc_per_qp;
440 int num_srq;
441 int num_cq;
442 int num_mcg;
443 int num_mpt;
db5a7a65 444 unsigned num_mtt;
225c7b1f
RD		 445};
446
447struct mlx4_fw {
448 u64 clr_int_base;
449 u64 catas_offset;
623ed84b 450 u64 comm_base;
225c7b1f
RD		 451 struct mlx4_icm *fw_icm;
452 struct mlx4_icm *aux_icm;
453 u32 catas_size;
454 u16 fw_pages;
455 u8 clr_int_bar;
456 u8 catas_bar;
623ed84b
JM		 457 u8 comm_bar;
458};
459
460struct mlx4_comm {
461 u32 slave_write;
462 u32 slave_read;
225c7b1f
RD		 463};
464
ffe455ad
EE		 465enum {
466 MLX4_MCAST_CONFIG = 0,
467 MLX4_MCAST_DISABLE = 1,
468 MLX4_MCAST_ENABLE = 2,
469};
470
623ed84b
JM		 471#define VLAN_FLTR_SIZE 128
472
473struct mlx4_vlan_fltr {
474 __be32 entry[VLAN_FLTR_SIZE];
475};
476
ffe455ad
EE		 477struct mlx4_mcast_entry {
478 struct list_head list;
479 u64 addr;
480};
481
b12d93d6
YP		 482struct mlx4_promisc_qp {
483 struct list_head list;
484 u32 qpn;
485};
486
487struct mlx4_steer_index {
488 struct list_head list;
489 unsigned int index;
490 struct list_head duplicates;
491};
492
803143fb
MA		 493#define MLX4_EVENT_TYPES_NUM 64
494
623ed84b
JM		 495struct mlx4_slave_state {
496 u8 comm_toggle;
497 u8 last_cmd;
498 u8 init_port_mask;
499 bool active;
500 u8 function;
501 dma_addr_t vhcr_dma;
502 u16 mtu[MLX4_MAX_PORTS + 1];
503 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
504 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
505 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
506 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 507 /* event type to eq number lookup */
508 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 509 u16 eq_pi;
510 u16 eq_ci;
511 spinlock_t lock;
512 /*initialized via the kzalloc*/
513 u8 is_slave_going_down;
514 u32 cookie;
515};
516
517struct slave_list {
518 struct mutex mutex;
519 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
520};
521
522struct mlx4_resource_tracker {
523 spinlock_t lock;
524 /* tree for each resources */
4af1c048 525 struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
623ed84b
JM		 526 /* num_of_slave's lists, one per slave */
527 struct slave_list *slave_list;
528};
529
530#define SLAVE_EVENT_EQ_SIZE 128
531struct mlx4_slave_event_eq {
532 u32 eqn;
533 u32 cons;
534 u32 prod;
535 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
536};
537
538struct mlx4_master_qp0_state {
539 int proxy_qp0_active;
540 int qp0_active;
541 int port_active;
542};
543
544struct mlx4_mfunc_master_ctx {
545 struct mlx4_slave_state *slave_state;
546 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
547 int init_port_ref[MLX4_MAX_PORTS + 1];
548 u16 max_mtu[MLX4_MAX_PORTS + 1];
549 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
550 struct mlx4_resource_tracker res_tracker;
551 struct workqueue_struct *comm_wq;
552 struct work_struct comm_work;
553 struct work_struct slave_event_work;
554 struct work_struct slave_flr_event_work;
555 spinlock_t slave_state_lock;
f5311ac1 556 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 557 struct mlx4_eqe cmd_eqe;
558 struct mlx4_slave_event_eq slave_eq;
559 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
560};
561
562struct mlx4_mfunc {
563 struct mlx4_comm __iomem *comm;
564 struct mlx4_vhcr_cmd *vhcr;
565 dma_addr_t vhcr_dma;
566
567 struct mlx4_mfunc_master_ctx master;
568};
569
225c7b1f
RD		 570struct mlx4_cmd {
571 struct pci_pool *pool;
572 void __iomem *hcr;
573 struct mutex hcr_mutex;
574 struct semaphore poll_sem;
575 struct semaphore event_sem;
623ed84b 576 struct semaphore slave_sem;
225c7b1f
RD		 577 int max_cmds;
578 spinlock_t context_lock;
579 int free_head;
580 struct mlx4_cmd_context *context;
581 u16 token_mask;
582 u8 use_events;
583 u8 toggle;
623ed84b 584 u8 comm_toggle;
225c7b1f
RD		 585};
586
587struct mlx4_uar_table {
588 struct mlx4_bitmap bitmap;
589};
590
591struct mlx4_mr_table {
592 struct mlx4_bitmap mpt_bitmap;
593 struct mlx4_buddy mtt_buddy;
594 u64 mtt_base;
595 u64 mpt_base;
596 struct mlx4_icm_table mtt_table;
597 struct mlx4_icm_table dmpt_table;
598};
599
600struct mlx4_cq_table {
601 struct mlx4_bitmap bitmap;
602 spinlock_t lock;
603 struct radix_tree_root tree;
604 struct mlx4_icm_table table;
605 struct mlx4_icm_table cmpt_table;
606};
607
608struct mlx4_eq_table {
609 struct mlx4_bitmap bitmap;
b8dd786f 610 char *irq_names;
225c7b1f 611 void __iomem *clr_int;
b8dd786f 612 void __iomem **uar_map;
225c7b1f 613 u32 clr_mask;
b8dd786f 614 struct mlx4_eq *eq;
fa0681d2 615 struct mlx4_icm_table table;
225c7b1f
RD		 616 struct mlx4_icm_table cmpt_table;
617 int have_irq;
618 u8 inta_pin;
619};
620
621struct mlx4_srq_table {
622 struct mlx4_bitmap bitmap;
623 spinlock_t lock;
624 struct radix_tree_root tree;
625 struct mlx4_icm_table table;
626 struct mlx4_icm_table cmpt_table;
627};
628
629struct mlx4_qp_table {
630 struct mlx4_bitmap bitmap;
631 u32 rdmarc_base;
632 int rdmarc_shift;
633 spinlock_t lock;
634 struct mlx4_icm_table qp_table;
635 struct mlx4_icm_table auxc_table;
636 struct mlx4_icm_table altc_table;
637 struct mlx4_icm_table rdmarc_table;
638 struct mlx4_icm_table cmpt_table;
639};
640
641struct mlx4_mcg_table {
642 struct mutex mutex;
643 struct mlx4_bitmap bitmap;
644 struct mlx4_icm_table table;
645};
646
647struct mlx4_catas_err {
648 u32 __iomem *map;
ee49bd93
JM		 649 struct timer_list timer;
650 struct list_head list;
225c7b1f
RD		 651};
652
2a2336f8
YP		 653#define MLX4_MAX_MAC_NUM 128
654#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
655
656struct mlx4_mac_table {
657 __be64 entries[MLX4_MAX_MAC_NUM];
658 int refs[MLX4_MAX_MAC_NUM];
659 struct mutex mutex;
660 int total;
661 int max;
662};
663
664#define MLX4_MAX_VLAN_NUM 128
665#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
666
667struct mlx4_vlan_table {
668 __be32 entries[MLX4_MAX_VLAN_NUM];
669 int refs[MLX4_MAX_VLAN_NUM];
670 struct mutex mutex;
671 int total;
672 int max;
673};
674
ffe455ad
EE		 675#define SET_PORT_GEN_ALL_VALID 0x7
676#define SET_PORT_PROMISC_SHIFT 31
677#define SET_PORT_MC_PROMISC_SHIFT 30
678
679enum {
680 MCAST_DIRECT_ONLY = 0,
681 MCAST_DIRECT = 1,
682 MCAST_DEFAULT = 2
683};
684
685
686struct mlx4_set_port_general_context {
687 u8 reserved[3];
688 u8 flags;
689 u16 reserved2;
690 __be16 mtu;
691 u8 pptx;
692 u8 pfctx;
693 u16 reserved3;
694 u8 pprx;
695 u8 pfcrx;
696 u16 reserved4;
697};
698
699struct mlx4_set_port_rqp_calc_context {
700 __be32 base_qpn;
701 u8 rererved;
702 u8 n_mac;
703 u8 n_vlan;
704 u8 n_prio;
705 u8 reserved2[3];
706 u8 mac_miss;
707 u8 intra_no_vlan;
708 u8 no_vlan;
709 u8 intra_vlan_miss;
710 u8 vlan_miss;
711 u8 reserved3[3];
712 u8 no_vlan_prio;
713 __be32 promisc;
714 __be32 mcast;
715};
716
1679200f
YP		 717struct mlx4_mac_entry {
718 u64 mac;
0ff1fb65 719 u64 reg_id;
1679200f
YP		 720};
721
2a2336f8
YP		 722struct mlx4_port_info {
723 struct mlx4_dev *dev;
724 int port;
7ff93f8b
YP		 725 char dev_name[16];
726 struct device_attribute port_attr;
727 enum mlx4_port_type tmp_type;
096335b3
OG		 728 char dev_mtu_name[16];
729 struct device_attribute port_mtu_attr;
2a2336f8 730 struct mlx4_mac_table mac_table;
1679200f 731 struct radix_tree_root mac_tree;
2a2336f8 732 struct mlx4_vlan_table vlan_table;
1679200f 733 int base_qpn;
2a2336f8
YP		 734};
735
27bf91d6
YP		 736struct mlx4_sense {
737 struct mlx4_dev *dev;
738 u8 do_sense_port[MLX4_MAX_PORTS + 1];
739 u8 sense_allowed[MLX4_MAX_PORTS + 1];
740 struct delayed_work sense_poll;
741};
742
0b7ca5a9
YP		 743struct mlx4_msix_ctl {
744 u64 pool_bm;
730c41d5 745 struct mutex pool_lock;
0b7ca5a9
YP		 746};
747
b12d93d6
YP		 748struct mlx4_steer {
749 struct list_head promisc_qps[MLX4_NUM_STEERS];
750 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 751};
752
225c7b1f
RD		 753struct mlx4_priv {
754 struct mlx4_dev dev;
755
756 struct list_head dev_list;
757 struct list_head ctx_list;
758 spinlock_t ctx_lock;
759
6296883c
YP		 760 struct list_head pgdir_list;
761 struct mutex pgdir_mutex;
762
225c7b1f
RD		 763 struct mlx4_fw fw;
764 struct mlx4_cmd cmd;
623ed84b 765 struct mlx4_mfunc mfunc;
225c7b1f
RD		 766
767 struct mlx4_bitmap pd_bitmap;
012a8ff5 768 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 769 struct mlx4_uar_table uar_table;
770 struct mlx4_mr_table mr_table;
771 struct mlx4_cq_table cq_table;
772 struct mlx4_eq_table eq_table;
773 struct mlx4_srq_table srq_table;
774 struct mlx4_qp_table qp_table;
775 struct mlx4_mcg_table mcg_table;
f2a3f6a3 776 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 777
778 struct mlx4_catas_err catas_err;
779
780 void __iomem *clr_base;
781
782 struct mlx4_uar driver_uar;
783 void __iomem *kar;
2a2336f8 784 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 785 struct mlx4_sense sense;
7ff93f8b 786 struct mutex port_mutex;
0b7ca5a9 787 struct mlx4_msix_ctl msix_ctl;
b12d93d6 788 struct mlx4_steer *steer;
c1b43dca
EC		 789 struct list_head bf_list;
790 struct mutex bf_mutex;
791 struct io_mapping *bf_mapping;
ea51b377 792 int reserved_mtts;
0ff1fb65 793 int fs_hash_mode;
225c7b1f
RD		 794};
795
796static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
797{
798 return container_of(dev, struct mlx4_priv, dev);
799}
800
27bf91d6
YP		 801#define MLX4_SENSE_RANGE (HZ * 3)
802
803extern struct workqueue_struct *mlx4_wq;
804
225c7b1f
RD		 805u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
806void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 807u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
808void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 809u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 810int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
811 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 812void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
813
814int mlx4_reset(struct mlx4_dev *dev);
815
b8dd786f
YP		 816int mlx4_alloc_eq_table(struct mlx4_dev *dev);
817void mlx4_free_eq_table(struct mlx4_dev *dev);
818
225c7b1f 819int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 820int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 821int mlx4_init_uar_table(struct mlx4_dev *dev);
822int mlx4_init_mr_table(struct mlx4_dev *dev);
823int mlx4_init_eq_table(struct mlx4_dev *dev);
824int mlx4_init_cq_table(struct mlx4_dev *dev);
825int mlx4_init_qp_table(struct mlx4_dev *dev);
826int mlx4_init_srq_table(struct mlx4_dev *dev);
827int mlx4_init_mcg_table(struct mlx4_dev *dev);
828
829void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 830void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 831void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
832void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
833void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
834void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
835void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
836void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
837void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 838int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
839void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
840int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
841void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
842int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
843void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
844int __mlx4_mr_reserve(struct mlx4_dev *dev);
845void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
846int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
847void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
848u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
849void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 850
623ed84b
JM		 851int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
852 struct mlx4_vhcr *vhcr,
853 struct mlx4_cmd_mailbox *inbox,
854 struct mlx4_cmd_mailbox *outbox,
855 struct mlx4_cmd_info *cmd);
856int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
857 struct mlx4_vhcr *vhcr,
858 struct mlx4_cmd_mailbox *inbox,
859 struct mlx4_cmd_mailbox *outbox,
860 struct mlx4_cmd_info *cmd);
861int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
871int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
872 struct mlx4_vhcr *vhcr,
873 struct mlx4_cmd_mailbox *inbox,
874 struct mlx4_cmd_mailbox *outbox,
875 struct mlx4_cmd_info *cmd);
876int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
877 struct mlx4_vhcr *vhcr,
878 struct mlx4_cmd_mailbox *inbox,
879 struct mlx4_cmd_mailbox *outbox,
880 struct mlx4_cmd_info *cmd);
881int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 886int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
887 int *base);
888void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
889int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
890void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
891int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
892int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
893 int start_index, int npages, u64 *page_list);
ba062d52
JM		 894int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
895void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
896int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
897void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 898
ee49bd93
JM		 899void mlx4_start_catas_poll(struct mlx4_dev *dev);
900void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 901void mlx4_catas_init(void);
ee49bd93 902int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 903int mlx4_register_device(struct mlx4_dev *dev);
904void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 905void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 906
907struct mlx4_dev_cap;
908struct mlx4_init_hca_param;
909
910u64 mlx4_make_profile(struct mlx4_dev *dev,
911 struct mlx4_profile *request,
912 struct mlx4_dev_cap *dev_cap,
913 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 914void mlx4_master_comm_channel(struct work_struct *work);
915void mlx4_gen_slave_eqe(struct work_struct *work);
916void mlx4_master_handle_slave_flr(struct work_struct *work);
917
918int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
919 struct mlx4_vhcr *vhcr,
920 struct mlx4_cmd_mailbox *inbox,
921 struct mlx4_cmd_mailbox *outbox,
922 struct mlx4_cmd_info *cmd);
923int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
924 struct mlx4_vhcr *vhcr,
925 struct mlx4_cmd_mailbox *inbox,
926 struct mlx4_cmd_mailbox *outbox,
927 struct mlx4_cmd_info *cmd);
928int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
929 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd);
997int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd);
1002int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd);
1007
1008int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 1009
225c7b1f
RD		 1010int mlx4_cmd_init(struct mlx4_dev *dev);
1011void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 1012int mlx4_multi_func_init(struct mlx4_dev *dev);
1013void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 1014void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1015int mlx4_cmd_use_events(struct mlx4_dev *dev);
1016void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1017
ab9c17a0
JM		 1018int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1019 unsigned long timeout);
1020
225c7b1f
RD		 1021void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1022void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1023
1024void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1025
1026void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1027
1028void mlx4_handle_catas_err(struct mlx4_dev *dev);
1029
ab6dc30d
YP		 1030int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1031 enum mlx4_port_type *type);
27bf91d6
YP		 1032void mlx4_do_sense_ports(struct mlx4_dev *dev,
1033 enum mlx4_port_type *stype,
1034 enum mlx4_port_type *defaults);
1035void mlx4_start_sense(struct mlx4_dev *dev);
1036void mlx4_stop_sense(struct mlx4_dev *dev);
1037void mlx4_sense_init(struct mlx4_dev *dev);
1038int mlx4_check_port_params(struct mlx4_dev *dev,
1039 enum mlx4_port_type *port_type);
1040int mlx4_change_port_types(struct mlx4_dev *dev,
1041 enum mlx4_port_type *port_types);
1042
2a2336f8
YP		 1043void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1044void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1045
7ff93f8b 1046int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 1047/* resource tracker functions*/
1048int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1049 enum mlx4_resource resource_type,
aa1ec3dd 1050 u64 resource_id, int *slave);
623ed84b
JM		 1051void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1052int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1053
b8924951
JM		 1054void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1055 enum mlx4_res_tracker_free_type type);
623ed84b 1056
b91cb3eb
JM		 1057int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1062int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1063 struct mlx4_vhcr *vhcr,
1064 struct mlx4_cmd_mailbox *inbox,
1065 struct mlx4_cmd_mailbox *outbox,
1066 struct mlx4_cmd_info *cmd);
1067int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1068 struct mlx4_vhcr *vhcr,
1069 struct mlx4_cmd_mailbox *inbox,
1070 struct mlx4_cmd_mailbox *outbox,
1071 struct mlx4_cmd_info *cmd);
1072int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1073 struct mlx4_vhcr *vhcr,
1074 struct mlx4_cmd_mailbox *inbox,
1075 struct mlx4_cmd_mailbox *outbox,
1076 struct mlx4_cmd_info *cmd);
b91cb3eb
JM		 1077int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd);
623ed84b
JM		 1082int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1083 struct mlx4_vhcr *vhcr,
1084 struct mlx4_cmd_mailbox *inbox,
1085 struct mlx4_cmd_mailbox *outbox,
1086 struct mlx4_cmd_info *cmd);
9a5aa622 1087int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1088
623ed84b
JM		 1089
1090int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1091 struct mlx4_vhcr *vhcr,
1092 struct mlx4_cmd_mailbox *inbox,
1093 struct mlx4_cmd_mailbox *outbox,
1094 struct mlx4_cmd_info *cmd);
1095
1096int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1097 struct mlx4_vhcr *vhcr,
1098 struct mlx4_cmd_mailbox *inbox,
1099 struct mlx4_cmd_mailbox *outbox,
1100 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1101int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1102 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1103int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1104 int block_mcast_loopback, enum mlx4_protocol prot,
1105 enum mlx4_steer_type steer);
623ed84b
JM		 1106int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1107 struct mlx4_vhcr *vhcr,
1108 struct mlx4_cmd_mailbox *inbox,
1109 struct mlx4_cmd_mailbox *outbox,
1110 struct mlx4_cmd_info *cmd);
1111int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1112 struct mlx4_vhcr *vhcr,
1113 struct mlx4_cmd_mailbox *inbox,
1114 struct mlx4_cmd_mailbox *outbox,
1115 struct mlx4_cmd_info *cmd);
1116int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1117 int port, void *buf);
1118int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1119 struct mlx4_cmd_mailbox *outbox);
1120int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1121 struct mlx4_vhcr *vhcr,
1122 struct mlx4_cmd_mailbox *inbox,
1123 struct mlx4_cmd_mailbox *outbox,
1124 struct mlx4_cmd_info *cmd);
1125int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1126 struct mlx4_vhcr *vhcr,
1127 struct mlx4_cmd_mailbox *inbox,
1128 struct mlx4_cmd_mailbox *outbox,
1129 struct mlx4_cmd_info *cmd);
1130int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1131 struct mlx4_vhcr *vhcr,
1132 struct mlx4_cmd_mailbox *inbox,
1133 struct mlx4_cmd_mailbox *outbox,
1134 struct mlx4_cmd_info *cmd);
8fcfb4db
HHZ		 1135int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1136 struct mlx4_vhcr *vhcr,
1137 struct mlx4_cmd_mailbox *inbox,
1138 struct mlx4_cmd_mailbox *outbox,
1139 struct mlx4_cmd_info *cmd);
1140int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave,
1141 struct mlx4_vhcr *vhcr,
1142 struct mlx4_cmd_mailbox *inbox,
1143 struct mlx4_cmd_mailbox *outbox,
1144 struct mlx4_cmd_info *cmd);
f5311ac1 1145
0ec2c0f8
EE		 1146int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1147int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1148
5cc914f1
MA		 1149static inline void set_param_l(u64 *arg, u32 val)
1150{
1151 *((u32 *)arg) = val;
1152}
1153
1154static inline void set_param_h(u64 *arg, u32 val)
1155{
1156 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1157}
1158
1159static inline u32 get_param_l(u64 *arg)
1160{
1161 return (u32) (*arg & 0xffffffff);
1162}
1163
1164static inline u32 get_param_h(u64 *arg)
1165{
1166 return (u32)(*arg >> 32);
1167}
1168
c82e9aa0
EC		 1169static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1170{
1171 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1172}
1173
f5311ac1
JM		 1174#define NOT_MASKED_PD_BITS 17
1175
225c7b1f 1176#endif /* MLX4_H */
Linux 6.x block layer and io_uring tree(s)