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Linux 6.17-rc6
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
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225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
691223ec 37#include <linux/kernel.h>
225c7b1f
RD		 38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
5a0e3ad6 42#include <linux/slab.h>
c1b43dca 43#include <linux/io-mapping.h>
ab9c17a0 44#include <linux/delay.h>
10b1c04e 45#include <linux/etherdevice.h>
09d4d087 46#include <net/devlink.h>
225c7b1f 47
48962f5c 48#include <uapi/rdma/mlx4-abi.h>
225c7b1f
RD		 49#include <linux/mlx4/device.h>
50#include <linux/mlx4/doorbell.h>
51
e0e3265a
MZ		 52#include <rdma/ib_verbs.h>
53
225c7b1f
RD		 54#include "mlx4.h"
55#include "fw.h"
56#include "icm.h"
57
58MODULE_AUTHOR("Roland Dreier");
59MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
60MODULE_LICENSE("Dual BSD/GPL");
61MODULE_VERSION(DRV_VERSION);
62
27bf91d6
YP		 63struct workqueue_struct *mlx4_wq;
64
225c7b1f
RD		 65#ifdef CONFIG_MLX4_DEBUG
66
92a59ad0 67int mlx4_debug_level; /* 0 by default */
225c7b1f
RD		 68module_param_named(debug_level, mlx4_debug_level, int, 0644);
69MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
70
71#endif /* CONFIG_MLX4_DEBUG */
72
73#ifdef CONFIG_PCI_MSI
74
08fb1055 75static int msi_x = 1;
225c7b1f 76module_param(msi_x, int, 0444);
e5732838 77MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x");
225c7b1f
RD		 78
79#else /* CONFIG_PCI_MSI */
80
81#define msi_x (0)
82
83#endif /* CONFIG_PCI_MSI */
84
dd41cc3b 85static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 86static int num_vfs_argc;
92a59ad0 87module_param_array(num_vfs, byte, &num_vfs_argc, 0444);
dd41cc3b
MB		 88MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
89 "num_vfs=port1,port2,port1+2");
90
91static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 92static int probe_vfs_argc;
dd41cc3b
MB		 93module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
94MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
95 "probe_vf=port1,port2,port1+2");
ab9c17a0 96
3b68067b 97static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 98module_param_named(log_num_mgm_entry_size,
99 mlx4_log_num_mgm_entry_size, int, 0444);
100MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
101 " of qp per mcg, for example:"
3c439b55 102 " 10 gives 248.range: 7 <="
0ff1fb65 103 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 104 " To activate device managed"
105 " flow steering when available, set to -1");
0ec2c0f8 106
be902ab1 107static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 108module_param(enable_64b_cqe_eqe, bool, 0444);
109MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 110 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 111
76e39ccf
EC		 112static bool enable_4k_uar;
113module_param(enable_4k_uar, bool, 0444);
114MODULE_PARM_DESC(enable_4k_uar,
115 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
116
77507aa2 117#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 118 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
119 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 120
55ad3592
YH		 121#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
122
f57e6848 123static char mlx4_version[] =
225c7b1f 124 DRV_NAME ": Mellanox ConnectX core driver v"
cea2a6d8 125 DRV_VERSION "\n";
225c7b1f 126
3f2c5fb2 127static const struct mlx4_profile default_profile = {
ab9c17a0 128 .num_qp = 1 << 18,
225c7b1f 129 .num_srq = 1 << 16,
c9f2ba5e 130 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 131 .num_cq = 1 << 16,
132 .num_mcg = 1 << 13,
ab9c17a0 133 .num_mpt = 1 << 19,
6cc9c6fb 134 .num_mtt = 1 << 20, /* It is really num mtt segments */
225c7b1f
RD		 135};
136
3f2c5fb2 137static const struct mlx4_profile low_mem_profile = {
2599d858
AV		 138 .num_qp = 1 << 17,
139 .num_srq = 1 << 6,
140 .rdmarc_per_qp = 1 << 4,
141 .num_cq = 1 << 8,
142 .num_mcg = 1 << 8,
143 .num_mpt = 1 << 9,
144 .num_mtt = 1 << 7,
145};
146
ab9c17a0 147static int log_num_mac = 7;
93fc9e1b
YP		 148module_param_named(log_num_mac, log_num_mac, int, 0444);
149MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
150
151static int log_num_vlan;
152module_param_named(log_num_vlan, log_num_vlan, int, 0444);
153MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 154/* Log2 max number of VLANs per ETH port (0-7) */
155#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 156#define MLX4_MIN_LOG_NUM_VLANS 0
157#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 158
eb939922 159static bool use_prio;
93fc9e1b 160module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 161MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 162
7cc77bf4 163int log_mtts_per_seg = ilog2(1);
ab6bf42e 164module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
7cc77bf4
TT		 165MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
166 "(0-7) (default: 0)");
ab6bf42e 167
8d0fc7b6 168static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 169static int arr_argc = 2;
170module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 171MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
172 "1 for IB, 2 for Ethernet");
ab9c17a0 173
97989356
AV		 174static atomic_t pf_loading = ATOMIC_INIT(0);
175
bd1b51dc
MS		 176static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id,
177 struct devlink_param_gset_ctx *ctx)
178{
179 ctx->val.vbool = !!mlx4_internal_err_reset;
180 return 0;
181}
182
183static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id,
5625ca56
MP		 184 struct devlink_param_gset_ctx *ctx,
185 struct netlink_ext_ack *extack)
bd1b51dc
MS		 186{
187 mlx4_internal_err_reset = ctx->val.vbool;
188 return 0;
189}
190
3c641ba4
AV		 191static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id,
192 struct devlink_param_gset_ctx *ctx)
193{
194 struct mlx4_priv *priv = devlink_priv(devlink);
195 struct mlx4_dev *dev = &priv->dev;
196
197 ctx->val.vbool = dev->persist->crdump.snapshot_enable;
198 return 0;
199}
200
201static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id,
5625ca56
MP		 202 struct devlink_param_gset_ctx *ctx,
203 struct netlink_ext_ack *extack)
3c641ba4
AV		 204{
205 struct mlx4_priv *priv = devlink_priv(devlink);
206 struct mlx4_dev *dev = &priv->dev;
207
208 dev->persist->crdump.snapshot_enable = ctx->val.vbool;
209 return 0;
210}
211
bd1b51dc
MS		 212static int
213mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id,
214 union devlink_param_value val,
215 struct netlink_ext_ack *extack)
216{
217 u32 value = val.vu32;
218
219 if (value < 1 || value > 128)
220 return -ERANGE;
221
222 if (!is_power_of_2(value)) {
223 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2");
224 return -EINVAL;
225 }
226
227 return 0;
228}
229
230enum mlx4_devlink_param_id {
231 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
232 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
233 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
234};
235
236static const struct devlink_param mlx4_devlink_params[] = {
237 DEVLINK_PARAM_GENERIC(INT_ERR_RESET,
238 BIT(DEVLINK_PARAM_CMODE_RUNTIME) |
239 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
240 mlx4_devlink_ierr_reset_get,
241 mlx4_devlink_ierr_reset_set, NULL),
242 DEVLINK_PARAM_GENERIC(MAX_MACS,
243 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
244 NULL, NULL, mlx4_devlink_max_macs_validate),
3c641ba4
AV		 245 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT,
246 BIT(DEVLINK_PARAM_CMODE_RUNTIME) |
247 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
248 mlx4_devlink_crdump_snapshot_get,
249 mlx4_devlink_crdump_snapshot_set, NULL),
bd1b51dc
MS		 250 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
251 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL,
252 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
253 NULL, NULL, NULL),
254 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
255 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL,
256 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
257 NULL, NULL, NULL),
258};
259
bd1b51dc
MS		 260static void mlx4_devlink_set_params_init_values(struct devlink *devlink)
261{
262 union devlink_param_value value;
263
264 value.vbool = !!mlx4_internal_err_reset;
075935f0
JP		 265 devl_param_driverinit_value_set(devlink,
266 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET,
267 value);
bd1b51dc
MS		 268
269 value.vu32 = 1UL << log_num_mac;
075935f0
JP		 270 devl_param_driverinit_value_set(devlink,
271 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
272 value);
bd1b51dc
MS		 273
274 value.vbool = enable_64b_cqe_eqe;
075935f0
JP		 275 devl_param_driverinit_value_set(devlink,
276 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
277 value);
bd1b51dc
MS		 278
279 value.vbool = enable_4k_uar;
075935f0
JP		 280 devl_param_driverinit_value_set(devlink,
281 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
282 value);
3c641ba4
AV		 283
284 value.vbool = false;
075935f0
JP		 285 devl_param_driverinit_value_set(devlink,
286 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT,
287 value);
bd1b51dc
MS		 288}
289
85743f1e
HN		 290static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
291 struct mlx4_dev_cap *dev_cap)
292{
293 /* The reserved_uars is calculated by system page size unit.
294 * Therefore, adjustment is added when the uar page size is less
295 * than the system page size
296 */
297 dev->caps.reserved_uars =
298 max_t(int,
299 mlx4_get_num_reserved_uar(dev),
300 dev_cap->reserved_uars /
301 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
302}
303
27bf91d6
YP		 304int mlx4_check_port_params(struct mlx4_dev *dev,
305 enum mlx4_port_type *port_type)
7ff93f8b
YP		 306{
307 int i;
308
0b997657
YS		 309 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
310 for (i = 0; i < dev->caps.num_ports - 1; i++) {
311 if (port_type[i] != port_type[i + 1]) {
1a91de28 312 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
95aac2cd 313 return -EOPNOTSUPP;
27bf91d6 314 }
7ff93f8b
YP		 315 }
316 }
7ff93f8b
YP		 317
318 for (i = 0; i < dev->caps.num_ports; i++) {
319 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 320 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
321 i + 1);
95aac2cd 322 return -EOPNOTSUPP;
7ff93f8b
YP		 323 }
324 }
325 return 0;
326}
327
328static void mlx4_set_port_mask(struct mlx4_dev *dev)
329{
330 int i;
331
7ff93f8b 332 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 333 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 334}
f2a3f6a3 335
7ae0e400
MB		 336enum {
337 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
338};
339
340static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
341{
342 int err = 0;
343 struct mlx4_func func;
344
345 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
346 err = mlx4_QUERY_FUNC(dev, &func, 0);
347 if (err) {
348 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
349 return err;
350 }
351 dev_cap->max_eqs = func.max_eq;
352 dev_cap->reserved_eqs = func.rsvd_eqs;
353 dev_cap->reserved_uars = func.rsvd_uars;
354 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
355 }
356 return err;
357}
358
77507aa2
IS		 359static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
360{
361 struct mlx4_caps *dev_cap = &dev->caps;
362
363 /* FW not supporting or cancelled by user */
364 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
365 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
366 return;
367
368 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
369 * When FW has NCSI it may decide not to report 64B CQE/EQEs
370 */
371 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
372 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
373 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
374 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
375 return;
376 }
377
378 if (cache_line_size() == 128 || cache_line_size() == 256) {
379 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
380 /* Changing the real data inside CQE size to 32B */
381 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
382 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
383
384 if (mlx4_is_master(dev))
385 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
386 } else {
0fab541a
OG		 387 if (cache_line_size() != 32 && cache_line_size() != 64)
388 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 389 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
390 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
391 }
392}
393
431df8c7
MB		 394static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
395 struct mlx4_port_cap *port_cap)
396{
397 dev->caps.vl_cap[port] = port_cap->max_vl;
398 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
399 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
400 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
401 /* set gid and pkey table operating lengths by default
402 * to non-sriov values
403 */
404 dev->caps.gid_table_len[port] = port_cap->max_gids;
405 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
406 dev->caps.port_width_cap[port] = port_cap->max_port_width;
407 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
af7d5185 408 dev->caps.max_tc_eth = port_cap->max_tc_eth;
431df8c7
MB		 409 dev->caps.def_mac[port] = port_cap->def_mac;
410 dev->caps.supported_type[port] = port_cap->supported_port_types;
411 dev->caps.suggested_type[port] = port_cap->suggested_type;
412 dev->caps.default_sense[port] = port_cap->default_sense;
413 dev->caps.trans_type[port] = port_cap->trans_type;
414 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
415 dev->caps.wavelength[port] = port_cap->wavelength;
416 dev->caps.trans_code[port] = port_cap->trans_code;
417
418 return 0;
419}
420
421static int mlx4_dev_port(struct mlx4_dev *dev, int port,
422 struct mlx4_port_cap *port_cap)
423{
424 int err = 0;
425
426 err = mlx4_QUERY_PORT(dev, port, port_cap);
427
428 if (err)
429 mlx4_err(dev, "QUERY_PORT command failed.\n");
430
431 return err;
432}
433
78500b8c
MM		 434static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
435{
436 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
437 return;
438
439 if (mlx4_is_mfunc(dev)) {
440 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
441 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
442 return;
443 }
444
445 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
446 mlx4_dbg(dev,
447 "Keep FCS is not supported - Disabling Ignore FCS");
448 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
449 return;
450 }
451}
452
431df8c7 453#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 454static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 455{
456 int err;
5ae2a7a8 457 int i;
225c7b1f
RD		 458
459 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
460 if (err) {
1a91de28 461 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 462 return err;
463 }
c78e25ed 464 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 465
466 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 467 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 468 dev_cap->min_page_sz, PAGE_SIZE);
469 return -ENODEV;
470 }
471 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 472 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 473 dev_cap->num_ports, MLX4_MAX_PORTS);
474 return -ENODEV;
475 }
476
872bf2fb 477 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 478 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 479 dev_cap->uar_size,
872bf2fb
YH		 480 (unsigned long long)
481 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 482 return -ENODEV;
483 }
484
485 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 486 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
487 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
488 dev->caps.num_sys_eqs :
489 MLX4_MAX_EQ_NUM;
5ae2a7a8 490 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 491 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
492 if (err) {
493 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
494 return err;
495 }
5ae2a7a8
RD		 496 }
497
404e5a12 498 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user;
ab9c17a0 499 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 500 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 501 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
502 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
503 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
504 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
505 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
506 dev->caps.max_wqes = dev_cap->max_qp_sz;
507 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 508 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
509 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
510 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
511 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
512 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 513 /*
514 * Subtract 1 from the limit because we need to allocate a
57d0f00d 515 * spare CQE to enable resizing the CQ.
225c7b1f
RD		 516 */
517 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
518 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
519 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 520 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 521 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0 522
225c7b1f 523 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 524 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
525 dev_cap->reserved_xrcds : 0;
526 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
527 dev_cap->max_xrcds : 0;
2b8fb286
MA		 528 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
529
149983af 530 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 531 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
532 dev->caps.flags = dev_cap->flags;
b3416f44 533 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 534 dev->caps.bmme_flags = dev_cap->bmme_flags;
535 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 536 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 537 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 538 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
c994f778
IK		 539 dev->caps.wol_port[1] = dev_cap->wol_port[1];
540 dev->caps.wol_port[2] = dev_cap->wol_port[2];
523f9eb1 541 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs;
225c7b1f 542
85743f1e
HN		 543 /* Save uar page shift */
544 if (!mlx4_is_slave(dev)) {
545 /* Virtual PCI function needs to determine UAR page size from
546 * firmware. Only master PCI function can set the uar page size
547 */
ca3d89a3 548 if (enable_4k_uar || !dev->persist->num_vfs)
76e39ccf
EC		 549 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
550 else
551 dev->uar_page_shift = PAGE_SHIFT;
552
85743f1e
HN		 553 mlx4_set_num_reserved_uars(dev, dev_cap);
554 }
555
77fc29c4
HHZ		 556 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
557 struct mlx4_init_hca_param hca_param;
558
559 memset(&hca_param, 0, sizeof(hca_param));
560 err = mlx4_QUERY_HCA(dev, &hca_param);
561 /* Turn off PHV_EN flag in case phv_check_en is set.
562 * phv_check_en is a HW check that parse the packet and verify
563 * phv bit was reported correctly in the wqe. To allow QinQ
564 * PHV_EN flag should be set and phv_check_en must be cleared
565 * otherwise QinQ packets will be drop by the HW.
566 */
567 if (err || hca_param.phv_check_en)
568 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
569 }
570
ca3e57a5
RD		 571 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
572 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 573 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 574 /* Don't do sense port on multifunction devices (for now at least) */
575 if (mlx4_is_mfunc(dev))
576 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 577
2599d858
AV		 578 if (mlx4_low_memory_profile()) {
579 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
580 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
581 } else {
582 dev->caps.log_num_macs = log_num_mac;
583 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
584 }
93fc9e1b
YP		 585
586 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 587 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
588 if (dev->caps.supported_type[i]) {
589 /* if only ETH is supported - assign ETH */
590 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
591 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 592 /* if only IB is supported, assign IB */
ab9c17a0 593 else if (dev->caps.supported_type[i] ==
105c320f
JM		 594 MLX4_PORT_TYPE_IB)
595 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 596 else {
105c320f
JM		 597 /* if IB and ETH are supported, we set the port
598 * type according to user selection of port type;
599 * if user selected none, take the FW hint */
600 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 601 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
602 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 603 else
105c320f 604 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 605 }
606 }
8d0fc7b6
YP		 607 /*
608 * Link sensing is allowed on the port if 3 conditions are true:
609 * 1. Both protocols are supported on the port.
610 * 2. Different types are supported on the port
611 * 3. FW declared that it supports link sensing
612 */
27bf91d6 613 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 614 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 615 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 616 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 617
8d0fc7b6
YP		 618 /*
619 * If "default_sense" bit is set, we move the port to "AUTO" mode
620 * and perform sense_port FW command to try and set the correct
621 * port type from beginning
622 */
46c46747 623 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 624 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
625 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
626 mlx4_SENSE_PORT(dev, i, &sensed_port);
627 if (sensed_port != MLX4_PORT_TYPE_NONE)
628 dev->caps.port_type[i] = sensed_port;
629 } else {
630 dev->caps.possible_type[i] = dev->caps.port_type[i];
631 }
632
431df8c7
MB		 633 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
634 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 635 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 636 i, 1 << dev->caps.log_num_macs);
637 }
431df8c7
MB		 638 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
639 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 640 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 641 i, 1 << dev->caps.log_num_vlans);
642 }
643 }
644
ac0a72a3
OG		 645 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
646 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
647 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
648 mlx4_warn(dev,
649 "Granular QoS per VF not supported with IB/Eth configuration\n");
650 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
651 }
652
47d8417f 653 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 654
93fc9e1b
YP		 655 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
656 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
657 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
658 (1 << dev->caps.log_num_macs) *
659 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 660 dev->caps.num_ports;
661 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 662
663 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
664 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
665 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
666 else
667 dev->caps.dmfs_high_rate_qpn_base =
668 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
669
670 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
671 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
672 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
673 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
674 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
675 } else {
676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
677 dev->caps.dmfs_high_rate_qpn_base =
678 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
679 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
680 }
681
fc31e256
OG		 682 dev->caps.rl_caps = dev_cap->rl_caps;
683
d57febe1 684 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 685 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 686
687 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
688 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
689 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
690 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
691
e2c76824 692 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 693
b3051320 694 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 695 if (dev_cap->flags &
696 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
697 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
698 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
699 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
700 }
77507aa2
IS		 701
702 if (dev_cap->flags2 &
703 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
704 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
705 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
706 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
707 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
708 }
08ff3235
OG		 709 }
710
f97b4b5d 711 if ((dev->caps.flags &
08ff3235
OG		 712 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
713 mlx4_is_master(dev))
714 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
715
ddae0349 716 if (!mlx4_is_slave(dev)) {
77507aa2 717 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 718 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 719 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
720 MLX4_RESERVE_A0_QP;
3742cc65
IS		 721
722 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
723 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
724 mlx4_warn(dev, "Old device ETS support detected\n");
725 mlx4_warn(dev, "Consider upgrading device FW.\n");
726 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
727 }
728
ddae0349
EE		 729 } else {
730 dev->caps.alloc_res_qp_mask = 0;
731 }
77507aa2 732
78500b8c
MM		 733 mlx4_enable_ignore_fcs(dev);
734
225c7b1f
RD		 735 return 0;
736}
b912b2f8 737
ab9c17a0
JM		 738/*The function checks if there are live vf, return the num of them*/
739static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
740{
741 struct mlx4_priv *priv = mlx4_priv(dev);
742 struct mlx4_slave_state *s_state;
743 int i;
744 int ret = 0;
745
746 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
747 s_state = &priv->mfunc.master.slave_state[i];
748 if (s_state->active && s_state->last_cmd !=
749 MLX4_COMM_CMD_RESET) {
750 mlx4_warn(dev, "%s: slave: %d is still active\n",
751 __func__, i);
752 ret++;
753 }
754 }
755 return ret;
756}
757
396f2feb
JM		 758int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
759{
760 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 761
762 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
763 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 764 return -EINVAL;
765
47605df9 766 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 767 /* tunnel qp */
47605df9 768 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 769 else
47605df9 770 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 771 *qkey = qk;
772 return 0;
773}
774EXPORT_SYMBOL(mlx4_get_parav_qkey);
775
54679e14
JM		 776void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
777{
778 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
779
780 if (!mlx4_is_master(dev))
781 return;
782
783 priv->virt2phys_pkey[slave][port - 1][i] = val;
784}
785EXPORT_SYMBOL(mlx4_sync_pkey_table);
786
afa8fd1d
JM		 787void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
788{
789 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
790
791 if (!mlx4_is_master(dev))
792 return;
793
794 priv->slave_node_guids[slave] = guid;
795}
796EXPORT_SYMBOL(mlx4_put_slave_node_guid);
797
798__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
799{
800 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
801
802 if (!mlx4_is_master(dev))
803 return 0;
804
805 return priv->slave_node_guids[slave];
806}
807EXPORT_SYMBOL(mlx4_get_slave_node_guid);
808
e10903b0 809int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 810{
811 struct mlx4_priv *priv = mlx4_priv(dev);
812 struct mlx4_slave_state *s_slave;
813
814 if (!mlx4_is_master(dev))
815 return 0;
816
817 s_slave = &priv->mfunc.master.slave_state[slave];
818 return !!s_slave->active;
819}
820EXPORT_SYMBOL(mlx4_is_slave_active);
821
10b1c04e
JM		 822void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
823 struct _rule_hw *eth_header)
824{
825 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
826 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
827 struct mlx4_net_trans_rule_hw_eth *eth =
828 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
829 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
830 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
831 next_rule->rsvd == 0;
832
833 if (last_rule)
834 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
835 }
836}
837EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
838
7b8157be
JM		 839static void slave_adjust_steering_mode(struct mlx4_dev *dev,
840 struct mlx4_dev_cap *dev_cap,
841 struct mlx4_init_hca_param *hca_param)
842{
843 dev->caps.steering_mode = hca_param->steering_mode;
844 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
845 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
846 dev->caps.fs_log_max_ucast_qp_range_size =
847 dev_cap->fs_log_max_ucast_qp_range_size;
848 } else
849 dev->caps.num_qp_per_mgm =
850 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
851
852 mlx4_dbg(dev, "Steering mode is: %s\n",
853 mlx4_steering_mode_str(dev->caps.steering_mode));
854}
855
c73c8b1e
EBE		 856static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
857{
858 kfree(dev->caps.spec_qps);
859 dev->caps.spec_qps = NULL;
860}
861
862static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
863{
39868926 864 struct mlx4_func_cap *func_cap;
c73c8b1e
EBE		 865 struct mlx4_caps *caps = &dev->caps;
866 int i, err = 0;
867
868 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
869 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
870
871 if (!func_cap || !caps->spec_qps) {
872 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
873 err = -ENOMEM;
874 goto err_mem;
875 }
876
877 for (i = 1; i <= caps->num_ports; ++i) {
878 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
879 if (err) {
880 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
881 i, err);
882 goto err_mem;
883 }
884 caps->spec_qps[i - 1] = func_cap->spec_qps;
885 caps->port_mask[i] = caps->port_type[i];
886 caps->phys_port_id[i] = func_cap->phys_port_id;
887 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
888 &caps->gid_table_len[i],
889 &caps->pkey_table_len[i]);
890 if (err) {
891 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
892 i, err);
893 goto err_mem;
894 }
895 }
896
897err_mem:
898 if (err)
899 mlx4_slave_destroy_special_qp_cap(dev);
900 kfree(func_cap);
901 return err;
902}
903
ab9c17a0
JM		 904static int mlx4_slave_cap(struct mlx4_dev *dev)
905{
906 int err;
907 u32 page_size;
39868926
RJ		 908 struct mlx4_dev_cap *dev_cap;
909 struct mlx4_func_cap *func_cap;
910 struct mlx4_init_hca_param *hca_param;
c73c8b1e
EBE		 911
912 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
913 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
914 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
915 if (!hca_param || !func_cap || !dev_cap) {
916 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
917 err = -ENOMEM;
918 goto free_mem;
919 }
ab9c17a0 920
c73c8b1e 921 err = mlx4_QUERY_HCA(dev, hca_param);
ab9c17a0 922 if (err) {
1a91de28 923 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
c73c8b1e 924 goto free_mem;
ab9c17a0
JM		 925 }
926
483e0132
EP		 927 /* fail if the hca has an unknown global capability
928 * at this time global_caps should be always zeroed
929 */
c73c8b1e 930 if (hca_param->global_caps) {
ab9c17a0 931 mlx4_err(dev, "Unknown hca global capabilities\n");
c73c8b1e
EBE		 932 err = -EINVAL;
933 goto free_mem;
ab9c17a0
JM		 934 }
935
c73c8b1e 936 dev->caps.hca_core_clock = hca_param->hca_core_clock;
ddd8a6c1 937
c73c8b1e
EBE		 938 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
939 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 940 if (err) {
1a91de28 941 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
c73c8b1e 942 goto free_mem;
ab9c17a0
JM		 943 }
944
b91cb3eb
JM		 945 err = mlx4_QUERY_FW(dev);
946 if (err)
1a91de28 947 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 948
ab9c17a0
JM		 949 page_size = ~dev->caps.page_size_cap + 1;
950 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
951 if (page_size > PAGE_SIZE) {
1a91de28 952 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0 953 page_size, PAGE_SIZE);
c73c8b1e
EBE		 954 err = -ENODEV;
955 goto free_mem;
ab9c17a0
JM		 956 }
957
85743f1e 958 /* Set uar_page_shift for VF */
c73c8b1e 959 dev->uar_page_shift = hca_param->uar_page_sz + 12;
ab9c17a0 960
85743f1e
HN		 961 /* Make sure the master uar page size is valid */
962 if (dev->uar_page_shift > PAGE_SHIFT) {
963 mlx4_err(dev,
964 "Invalid configuration: uar page size is larger than system page size\n");
c73c8b1e
EBE		 965 err = -ENODEV;
966 goto free_mem;
ab9c17a0
JM		 967 }
968
85743f1e 969 /* Set reserved_uars based on the uar_page_shift */
c73c8b1e 970 mlx4_set_num_reserved_uars(dev, dev_cap);
85743f1e
HN		 971
972 /* Although uar page size in FW differs from system page size,
973 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
974 * still works with assumption that uar page size == system page size
975 */
976 dev->caps.uar_page_size = PAGE_SIZE;
977
c73c8b1e 978 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
ab9c17a0 979 if (err) {
1a91de28
JP		 980 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
981 err);
c73c8b1e 982 goto free_mem;
ab9c17a0
JM		 983 }
984
c73c8b1e 985 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
ab9c17a0 986 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3 987 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
c73c8b1e
EBE		 988 func_cap->pf_context_behaviour,
989 PF_CONTEXT_BEHAVIOUR_MASK);
990 err = -EINVAL;
991 goto free_mem;
992 }
993
994 dev->caps.num_ports = func_cap->num_ports;
995 dev->quotas.qp = func_cap->qp_quota;
996 dev->quotas.srq = func_cap->srq_quota;
997 dev->quotas.cq = func_cap->cq_quota;
998 dev->quotas.mpt = func_cap->mpt_quota;
999 dev->quotas.mtt = func_cap->mtt_quota;
1000 dev->caps.num_qps = 1 << hca_param->log_num_qps;
1001 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
1002 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
1003 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
1004 dev->caps.num_eqs = func_cap->max_eq;
1005 dev->caps.reserved_eqs = func_cap->reserved_eq;
1006 dev->caps.reserved_lkey = func_cap->reserved_lkey;
ab9c17a0
JM		 1007 dev->caps.num_pds = MLX4_NUM_PDS;
1008 dev->caps.num_mgms = 0;
1009 dev->caps.num_amgms = 0;
1010
ab9c17a0 1011 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 1012 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
1013 dev->caps.num_ports, MLX4_MAX_PORTS);
542deb88
CIK		 1014 err = -ENODEV;
1015 goto free_mem;
ab9c17a0
JM		 1016 }
1017
2b3ddf27
JM		 1018 mlx4_replace_zero_macs(dev);
1019
c73c8b1e
EBE		 1020 err = mlx4_slave_special_qp_cap(dev);
1021 if (err) {
1022 mlx4_err(dev, "Set special QP caps failed. aborting\n");
1023 goto free_mem;
6634961c 1024 }
6230bb23 1025
ab9c17a0
JM		 1026 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1027 dev->caps.reserved_uars) >
872bf2fb
YH		 1028 pci_resource_len(dev->persist->pdev,
1029 2)) {
1a91de28 1030 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 1031 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 1032 (unsigned long long)
1033 pci_resource_len(dev->persist->pdev, 2));
d49c2197 1034 err = -ENOMEM;
47605df9 1035 goto err_mem;
ab9c17a0
JM		 1036 }
1037
c73c8b1e 1038 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
08ff3235
OG		 1039 dev->caps.eqe_size = 64;
1040 dev->caps.eqe_factor = 1;
1041 } else {
1042 dev->caps.eqe_size = 32;
1043 dev->caps.eqe_factor = 0;
1044 }
1045
c73c8b1e 1046 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
08ff3235 1047 dev->caps.cqe_size = 64;
77507aa2 1048 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1049 } else {
1050 dev->caps.cqe_size = 32;
1051 }
1052
c73c8b1e
EBE		 1053 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
1054 dev->caps.eqe_size = hca_param->eqe_size;
77507aa2
IS		 1055 dev->caps.eqe_factor = 0;
1056 }
1057
c73c8b1e
EBE		 1058 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
1059 dev->caps.cqe_size = hca_param->cqe_size;
77507aa2
IS		 1060 /* User still need to know when CQE > 32B */
1061 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1062 }
1063
f9bd2d7f 1064 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1065 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 1066
be599603
MS		 1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1068 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
1069
c73c8b1e 1070 slave_adjust_steering_mode(dev, dev_cap, hca_param);
802f42a8 1071 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
c73c8b1e 1072 hca_param->rss_ip_frags ? "on" : "off");
7b8157be 1073
c73c8b1e 1074 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
ddae0349
EE		 1075 dev->caps.bf_reg_size)
1076 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1077
c73c8b1e 1078 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
d57febe1
MB		 1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1080
47605df9 1081err_mem:
c73c8b1e
EBE		 1082 if (err)
1083 mlx4_slave_destroy_special_qp_cap(dev);
1084free_mem:
1085 kfree(hca_param);
1086 kfree(func_cap);
1087 kfree(dev_cap);
47605df9 1088 return err;
ab9c17a0 1089}
225c7b1f 1090
7ff93f8b
YP		 1091/*
1092 * Change the port configuration of the device.
1093 * Every user of this function must hold the port mutex.
1094 */
27bf91d6
YP		 1095int mlx4_change_port_types(struct mlx4_dev *dev,
1096 enum mlx4_port_type *port_types)
7ff93f8b
YP		 1097{
1098 int err = 0;
1099 int change = 0;
1100 int port;
1101
1102 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1103 /* Change the port type only if the new type is different
1104 * from the current, and not set to Auto */
3d8f9308 1105 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1106 change = 1;
7ff93f8b
YP		 1107 }
1108 if (change) {
1109 mlx4_unregister_device(dev);
1110 for (port = 1; port <= dev->caps.num_ports; port++) {
1111 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1112 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1113 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1114 if (err) {
1a91de28
JP		 1115 mlx4_err(dev, "Failed to set port %d, aborting\n",
1116 port);
7ff93f8b
YP		 1117 goto out;
1118 }
1119 }
1120 mlx4_set_port_mask(dev);
1121 err = mlx4_register_device(dev);
b046ffe5
EP		 1122 if (err) {
1123 mlx4_err(dev, "Failed to register device\n");
1124 goto out;
1125 }
7ff93f8b
YP		 1126 }
1127
1128out:
1129 return err;
1130}
1131
1132static ssize_t show_port_type(struct device *dev,
1133 struct device_attribute *attr,
1134 char *buf)
1135{
1136 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1137 port_attr);
1138 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1139 char type[8];
1140
1141 sprintf(type, "%s",
1142 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1143 "ib" : "eth");
1144 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1145 sprintf(buf, "auto (%s)\n", type);
1146 else
1147 sprintf(buf, "%s\n", type);
7ff93f8b 1148
27bf91d6 1149 return strlen(buf);
7ff93f8b
YP		 1150}
1151
b2facd95
JP		 1152static int __set_port_type(struct mlx4_port_info *info,
1153 enum mlx4_port_type port_type)
7ff93f8b 1154{
7ff93f8b
YP		 1155 struct mlx4_dev *mdev = info->dev;
1156 struct mlx4_priv *priv = mlx4_priv(mdev);
1157 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1158 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 1159 int i;
1160 int err = 0;
1161
33a1f8b1
MG		 1162 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1163 mlx4_err(mdev,
1164 "Requested port type for port %d is not supported on this HCA\n",
1165 info->port);
95aac2cd 1166 return -EOPNOTSUPP;
33a1f8b1
MG		 1167 }
1168
27bf91d6 1169 mlx4_stop_sense(mdev);
7ff93f8b 1170 mutex_lock(&priv->port_mutex);
b2facd95
JP		 1171 info->tmp_type = port_type;
1172
27bf91d6
YP		 1173 /* Possible type is always the one that was delivered */
1174 mdev->caps.possible_type[info->port] = info->tmp_type;
1175
1176 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1177 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1178 mdev->caps.possible_type[i+1];
1179 if (types[i] == MLX4_PORT_TYPE_AUTO)
1180 types[i] = mdev->caps.port_type[i+1];
1181 }
7ff93f8b 1182
58a60168
YP		 1183 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1184 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1185 for (i = 1; i <= mdev->caps.num_ports; i++) {
1186 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1187 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
95aac2cd 1188 err = -EOPNOTSUPP;
27bf91d6
YP		 1189 }
1190 }
1191 }
1192 if (err) {
1a91de28 1193 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1194 goto out;
1195 }
1196
1197 mlx4_do_sense_ports(mdev, new_types, types);
1198
1199 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1200 if (err)
1201 goto out;
1202
27bf91d6
YP		 1203 /* We are about to apply the changes after the configuration
1204 * was verified, no need to remember the temporary types
1205 * any more */
1206 for (i = 0; i < mdev->caps.num_ports; i++)
1207 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1208
27bf91d6 1209 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1210
1211out:
27bf91d6 1212 mlx4_start_sense(mdev);
7ff93f8b 1213 mutex_unlock(&priv->port_mutex);
95aac2cd 1214
b2facd95
JP		 1215 return err;
1216}
1217
1218static ssize_t set_port_type(struct device *dev,
1219 struct device_attribute *attr,
1220 const char *buf, size_t count)
1221{
1222 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1223 port_attr);
1224 struct mlx4_dev *mdev = info->dev;
1225 enum mlx4_port_type port_type;
1226 static DEFINE_MUTEX(set_port_type_mutex);
1227 int err;
1228
1229 mutex_lock(&set_port_type_mutex);
1230
1231 if (!strcmp(buf, "ib\n")) {
1232 port_type = MLX4_PORT_TYPE_IB;
1233 } else if (!strcmp(buf, "eth\n")) {
1234 port_type = MLX4_PORT_TYPE_ETH;
1235 } else if (!strcmp(buf, "auto\n")) {
1236 port_type = MLX4_PORT_TYPE_AUTO;
1237 } else {
1238 mlx4_err(mdev, "%s is not supported port type\n", buf);
1239 err = -EINVAL;
1240 goto err_out;
1241 }
1242
1243 err = __set_port_type(info, port_type);
1244
0a984556
AV		 1245err_out:
1246 mutex_unlock(&set_port_type_mutex);
1247
7ff93f8b
YP		 1248 return err ? err : count;
1249}
1250
096335b3
OG		 1251static inline int int_to_ibta_mtu(int mtu)
1252{
1253 switch (mtu) {
1254 case 256: return IB_MTU_256;
1255 case 512: return IB_MTU_512;
1256 case 1024: return IB_MTU_1024;
1257 case 2048: return IB_MTU_2048;
1258 case 4096: return IB_MTU_4096;
1259 default: return -1;
1260 }
1261}
1262
e0e3265a 1263static inline int ibta_mtu_to_int(enum ib_mtu mtu)
096335b3
OG		 1264{
1265 switch (mtu) {
1266 case IB_MTU_256: return 256;
1267 case IB_MTU_512: return 512;
1268 case IB_MTU_1024: return 1024;
1269 case IB_MTU_2048: return 2048;
1270 case IB_MTU_4096: return 4096;
1271 default: return -1;
1272 }
1273}
1274
1275static ssize_t show_port_ib_mtu(struct device *dev,
1276 struct device_attribute *attr,
1277 char *buf)
1278{
1279 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1280 port_mtu_attr);
1281 struct mlx4_dev *mdev = info->dev;
1282
1283 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1284 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1285
1286 sprintf(buf, "%d\n",
1287 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1288 return strlen(buf);
1289}
1290
1291static ssize_t set_port_ib_mtu(struct device *dev,
1292 struct device_attribute *attr,
1293 const char *buf, size_t count)
1294{
1295 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1296 port_mtu_attr);
1297 struct mlx4_dev *mdev = info->dev;
1298 struct mlx4_priv *priv = mlx4_priv(mdev);
1299 int err, port, mtu, ibta_mtu = -1;
1300
1301 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1302 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1303 return -EINVAL;
1304 }
1305
618fad95
DB		 1306 err = kstrtoint(buf, 0, &mtu);
1307 if (!err)
096335b3
OG		 1308 ibta_mtu = int_to_ibta_mtu(mtu);
1309
618fad95 1310 if (err || ibta_mtu < 0) {
096335b3
OG		 1311 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1312 return -EINVAL;
1313 }
1314
1315 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1316
1317 mlx4_stop_sense(mdev);
1318 mutex_lock(&priv->port_mutex);
1319 mlx4_unregister_device(mdev);
1320 for (port = 1; port <= mdev->caps.num_ports; port++) {
1321 mlx4_CLOSE_PORT(mdev, port);
6634961c 1322 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1323 if (err) {
1a91de28
JP		 1324 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1325 port);
096335b3
OG		 1326 goto err_set_port;
1327 }
1328 }
1329 err = mlx4_register_device(mdev);
1330err_set_port:
1331 mutex_unlock(&priv->port_mutex);
1332 mlx4_start_sense(mdev);
1333 return err ? err : count;
1334}
1335
e57968a1
MS		 1336/* bond for multi-function device */
1337#define MAX_MF_BOND_ALLOWED_SLAVES 63
1338static int mlx4_mf_bond(struct mlx4_dev *dev)
1339{
1340 int err = 0;
00ada910 1341 int nvfs;
e57968a1
MS		 1342 struct mlx4_slaves_pport slaves_port1;
1343 struct mlx4_slaves_pport slaves_port2;
e57968a1
MS		 1344
1345 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1346 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
e57968a1
MS		 1347
1348 /* only single port vfs are allowed */
623a7138
CJ		 1349 if (bitmap_weight_and(slaves_port1.slaves, slaves_port2.slaves,
1350 dev->persist->num_vfs + 1) > 1) {
e57968a1
MS		 1351 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1352 return -EINVAL;
1353 }
1354
00ada910
MS		 1355 /* number of virtual functions is number of total functions minus one
1356 * physical function for each port.
1357 */
1358 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1359 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1360
e57968a1 1361 /* limit on maximum allowed VFs */
00ada910
MS		 1362 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1363 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1364 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
e57968a1 1365 return -EINVAL;
00ada910 1366 }
e57968a1
MS		 1367
1368 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1369 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1370 return -EINVAL;
1371 }
1372
1373 err = mlx4_bond_mac_table(dev);
1374 if (err)
1375 return err;
1376 err = mlx4_bond_vlan_table(dev);
1377 if (err)
1378 goto err1;
1379 err = mlx4_bond_fs_rules(dev);
1380 if (err)
1381 goto err2;
1382
1383 return 0;
1384err2:
1385 (void)mlx4_unbond_vlan_table(dev);
1386err1:
1387 (void)mlx4_unbond_mac_table(dev);
1388 return err;
1389}
1390
1391static int mlx4_mf_unbond(struct mlx4_dev *dev)
1392{
1393 int ret, ret1;
1394
1395 ret = mlx4_unbond_fs_rules(dev);
1396 if (ret)
26ff7585 1397 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret);
e57968a1
MS		 1398 ret1 = mlx4_unbond_mac_table(dev);
1399 if (ret1) {
1400 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1401 ret = ret1;
1402 }
1403 ret1 = mlx4_unbond_vlan_table(dev);
1404 if (ret1) {
1405 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1406 ret = ret1;
1407 }
1408 return ret;
1409}
1410
e2fb47d4 1411static int mlx4_bond(struct mlx4_dev *dev)
53f33ae2
MS		 1412{
1413 int ret = 0;
1414 struct mlx4_priv *priv = mlx4_priv(dev);
1415
1416 mutex_lock(&priv->bond_mutex);
1417
e57968a1 1418 if (!mlx4_is_bonded(dev)) {
53f33ae2 1419 ret = mlx4_do_bond(dev, true);
e57968a1
MS		 1420 if (ret)
1421 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1422 if (!ret && mlx4_is_master(dev)) {
1423 ret = mlx4_mf_bond(dev);
1424 if (ret) {
1425 mlx4_err(dev, "bond for multifunction failed\n");
1426 mlx4_do_bond(dev, false);
1427 }
1428 }
1429 }
53f33ae2
MS		 1430
1431 mutex_unlock(&priv->bond_mutex);
e57968a1 1432 if (!ret)
53f33ae2 1433 mlx4_dbg(dev, "Device is bonded\n");
e57968a1 1434
53f33ae2
MS		 1435 return ret;
1436}
53f33ae2 1437
e2fb47d4 1438static int mlx4_unbond(struct mlx4_dev *dev)
53f33ae2
MS		 1439{
1440 int ret = 0;
1441 struct mlx4_priv *priv = mlx4_priv(dev);
1442
1443 mutex_lock(&priv->bond_mutex);
1444
e57968a1
MS		 1445 if (mlx4_is_bonded(dev)) {
1446 int ret2 = 0;
1447
53f33ae2 1448 ret = mlx4_do_bond(dev, false);
e57968a1
MS		 1449 if (ret)
1450 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1451 if (mlx4_is_master(dev))
1452 ret2 = mlx4_mf_unbond(dev);
1453 if (ret2) {
1454 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1455 ret = ret2;
1456 }
1457 }
53f33ae2
MS		 1458
1459 mutex_unlock(&priv->bond_mutex);
e57968a1 1460 if (!ret)
53f33ae2 1461 mlx4_dbg(dev, "Device is unbonded\n");
e57968a1 1462
53f33ae2
MS		 1463 return ret;
1464}
53f33ae2 1465
e2fb47d4 1466static int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
53f33ae2
MS		 1467{
1468 u8 port1 = v2p->port1;
1469 u8 port2 = v2p->port2;
1470 struct mlx4_priv *priv = mlx4_priv(dev);
1471 int err;
1472
1473 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
423b3aec 1474 return -EOPNOTSUPP;
53f33ae2
MS		 1475
1476 mutex_lock(&priv->bond_mutex);
1477
1478 /* zero means keep current mapping for this port */
1479 if (port1 == 0)
1480 port1 = priv->v2p.port1;
1481 if (port2 == 0)
1482 port2 = priv->v2p.port2;
1483
1484 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1485 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1486 (port1 == 2 && port2 == 1)) {
1487 /* besides boundary checks cross mapping makes
1488 * no sense and therefore not allowed */
1489 err = -EINVAL;
1490 } else if ((port1 == priv->v2p.port1) &&
1491 (port2 == priv->v2p.port2)) {
1492 err = 0;
1493 } else {
1494 err = mlx4_virt2phy_port_map(dev, port1, port2);
1495 if (!err) {
1496 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1497 port1, port2);
1498 priv->v2p.port1 = port1;
1499 priv->v2p.port2 = port2;
1500 } else {
6cc9c6fb 1501 mlx4_err(dev, "Failed to change port map: %d\n", err);
53f33ae2
MS		 1502 }
1503 }
1504
1505 mutex_unlock(&priv->bond_mutex);
1506 return err;
1507}
e2fb47d4
PP		 1508
1509struct mlx4_bond {
1510 struct work_struct work;
1511 struct mlx4_dev *dev;
1512 int is_bonded;
1513 struct mlx4_port_map port_map;
1514};
1515
1516static void mlx4_bond_work(struct work_struct *work)
1517{
1518 struct mlx4_bond *bond = container_of(work, struct mlx4_bond, work);
1519 int err = 0;
1520
1521 if (bond->is_bonded) {
1522 if (!mlx4_is_bonded(bond->dev)) {
1523 err = mlx4_bond(bond->dev);
1524 if (err)
1525 mlx4_err(bond->dev, "Fail to bond device\n");
1526 }
1527 if (!err) {
1528 err = mlx4_port_map_set(bond->dev, &bond->port_map);
1529 if (err)
1530 mlx4_err(bond->dev,
1531 "Fail to set port map [%d][%d]: %d\n",
1532 bond->port_map.port1,
1533 bond->port_map.port2, err);
1534 }
1535 } else if (mlx4_is_bonded(bond->dev)) {
1536 err = mlx4_unbond(bond->dev);
1537 if (err)
1538 mlx4_err(bond->dev, "Fail to unbond device\n");
1539 }
1540 put_device(&bond->dev->persist->pdev->dev);
1541 kfree(bond);
1542}
1543
1544int mlx4_queue_bond_work(struct mlx4_dev *dev, int is_bonded, u8 v2p_p1,
1545 u8 v2p_p2)
1546{
1547 struct mlx4_bond *bond;
1548
1549 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
1550 if (!bond)
1551 return -ENOMEM;
1552
1553 INIT_WORK(&bond->work, mlx4_bond_work);
1554 get_device(&dev->persist->pdev->dev);
1555 bond->dev = dev;
1556 bond->is_bonded = is_bonded;
1557 bond->port_map.port1 = v2p_p1;
1558 bond->port_map.port2 = v2p_p2;
1559 queue_work(mlx4_wq, &bond->work);
1560 return 0;
1561}
1562EXPORT_SYMBOL(mlx4_queue_bond_work);
53f33ae2 1563
e8f9b2ed 1564static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1565{
1566 struct mlx4_priv *priv = mlx4_priv(dev);
1567 int err;
1568
1569 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1570 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1571 if (!priv->fw.fw_icm) {
1a91de28 1572 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1573 return -ENOMEM;
1574 }
1575
1576 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1577 if (err) {
1a91de28 1578 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1579 goto err_free;
1580 }
1581
1582 err = mlx4_RUN_FW(dev);
1583 if (err) {
1a91de28 1584 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1585 goto err_unmap_fa;
1586 }
1587
1588 return 0;
1589
1590err_unmap_fa:
1591 mlx4_UNMAP_FA(dev);
1592
1593err_free:
5b0bf5e2 1594 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1595 return err;
1596}
1597
e8f9b2ed
RD		 1598static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1599 int cmpt_entry_sz)
225c7b1f
RD		 1600{
1601 struct mlx4_priv *priv = mlx4_priv(dev);
1602 int err;
ab9c17a0 1603 int num_eqs;
225c7b1f
RD		 1604
1605 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1606 cmpt_base +
1607 ((u64) (MLX4_CMPT_TYPE_QP *
1608 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1609 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1610 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1611 0, 0);
225c7b1f
RD		 1612 if (err)
1613 goto err;
1614
1615 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1616 cmpt_base +
1617 ((u64) (MLX4_CMPT_TYPE_SRQ *
1618 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1619 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1620 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1621 if (err)
1622 goto err_qp;
1623
1624 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1625 cmpt_base +
1626 ((u64) (MLX4_CMPT_TYPE_CQ *
1627 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1628 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1629 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1630 if (err)
1631 goto err_srq;
1632
7ae0e400 1633 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1634 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1635 cmpt_base +
1636 ((u64) (MLX4_CMPT_TYPE_EQ *
1637 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1638 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1639 if (err)
1640 goto err_cq;
1641
1642 return 0;
1643
1644err_cq:
1645 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1646
1647err_srq:
1648 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1649
1650err_qp:
1651 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1652
1653err:
1654 return err;
1655}
1656
3d73c288
RD		 1657static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1658 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1659{
1660 struct mlx4_priv *priv = mlx4_priv(dev);
1661 u64 aux_pages;
ab9c17a0 1662 int num_eqs;
225c7b1f
RD		 1663 int err;
1664
1665 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1666 if (err) {
1a91de28 1667 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1668 return err;
1669 }
1670
1a91de28 1671 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1672 (unsigned long long) icm_size >> 10,
1673 (unsigned long long) aux_pages << 2);
1674
1675 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1676 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1677 if (!priv->fw.aux_icm) {
1a91de28 1678 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1679 return -ENOMEM;
1680 }
1681
1682 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1683 if (err) {
1a91de28 1684 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1685 goto err_free_aux;
1686 }
1687
1688 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1689 if (err) {
1a91de28 1690 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1691 goto err_unmap_aux;
1692 }
1693
ab9c17a0 1694
7ae0e400 1695 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1696 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1697 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1698 num_eqs, num_eqs, 0, 0);
225c7b1f 1699 if (err) {
1a91de28 1700 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1701 goto err_unmap_cmpt;
1702 }
1703
d7bb58fb
JM		 1704 /*
1705 * Reserved MTT entries must be aligned up to a cacheline
1706 * boundary, since the FW will write to them, while the driver
1707 * writes to all other MTT entries. (The variable
1708 * dev->caps.mtt_entry_sz below is really the MTT segment
1709 * size, not the raw entry size)
1710 */
1711 dev->caps.reserved_mtts =
1712 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1713 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1714
225c7b1f
RD		 1715 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1716 init_hca->mtt_base,
1717 dev->caps.mtt_entry_sz,
2b8fb286 1718 dev->caps.num_mtts,
5b0bf5e2 1719 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1720 if (err) {
1a91de28 1721 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1722 goto err_unmap_eq;
1723 }
1724
1725 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1726 init_hca->dmpt_base,
1727 dev_cap->dmpt_entry_sz,
1728 dev->caps.num_mpts,
5b0bf5e2 1729 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1730 if (err) {
1a91de28 1731 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1732 goto err_unmap_mtt;
1733 }
1734
1735 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1736 init_hca->qpc_base,
1737 dev_cap->qpc_entry_sz,
1738 dev->caps.num_qps,
93fc9e1b
YP		 1739 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1740 0, 0);
225c7b1f 1741 if (err) {
1a91de28 1742 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1743 goto err_unmap_dmpt;
1744 }
1745
1746 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1747 init_hca->auxc_base,
1748 dev_cap->aux_entry_sz,
1749 dev->caps.num_qps,
93fc9e1b
YP		 1750 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1751 0, 0);
225c7b1f 1752 if (err) {
1a91de28 1753 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1754 goto err_unmap_qp;
1755 }
1756
1757 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1758 init_hca->altc_base,
1759 dev_cap->altc_entry_sz,
1760 dev->caps.num_qps,
93fc9e1b
YP		 1761 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1762 0, 0);
225c7b1f 1763 if (err) {
1a91de28 1764 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1765 goto err_unmap_auxc;
1766 }
1767
1768 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1769 init_hca->rdmarc_base,
1770 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1771 dev->caps.num_qps,
93fc9e1b
YP		 1772 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1773 0, 0);
225c7b1f
RD		 1774 if (err) {
1775 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1776 goto err_unmap_altc;
1777 }
1778
1779 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1780 init_hca->cqc_base,
1781 dev_cap->cqc_entry_sz,
1782 dev->caps.num_cqs,
5b0bf5e2 1783 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1784 if (err) {
1a91de28 1785 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1786 goto err_unmap_rdmarc;
1787 }
1788
1789 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1790 init_hca->srqc_base,
1791 dev_cap->srq_entry_sz,
1792 dev->caps.num_srqs,
5b0bf5e2 1793 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1794 if (err) {
1a91de28 1795 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1796 goto err_unmap_cq;
1797 }
1798
1799 /*
0ff1fb65
HHZ		 1800 * For flow steering device managed mode it is required to use
1801 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1802 * required, but for simplicity just map the whole multicast
1803 * group table now. The table isn't very big and it's a lot
1804 * easier than trying to track ref counts.
225c7b1f
RD		 1805 */
1806 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1807 init_hca->mc_base,
1808 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1809 dev->caps.num_mgms + dev->caps.num_amgms,
1810 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1811 0, 0);
225c7b1f 1812 if (err) {
1a91de28 1813 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1814 goto err_unmap_srq;
1815 }
1816
1817 return 0;
1818
1819err_unmap_srq:
1820 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1821
1822err_unmap_cq:
1823 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1824
1825err_unmap_rdmarc:
1826 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1827
1828err_unmap_altc:
1829 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1830
1831err_unmap_auxc:
1832 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1833
1834err_unmap_qp:
1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1836
1837err_unmap_dmpt:
1838 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1839
1840err_unmap_mtt:
1841 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1842
1843err_unmap_eq:
fa0681d2 1844 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1845
1846err_unmap_cmpt:
1847 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1848 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1849 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1850 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1851
1852err_unmap_aux:
1853 mlx4_UNMAP_ICM_AUX(dev);
1854
1855err_free_aux:
5b0bf5e2 1856 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1857
1858 return err;
1859}
1860
1861static void mlx4_free_icms(struct mlx4_dev *dev)
1862{
1863 struct mlx4_priv *priv = mlx4_priv(dev);
1864
1865 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1866 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1867 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1868 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1869 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1870 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1871 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1872 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1873 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1874 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1875 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1876 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1877 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1878 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1879
1880 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1881 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1882}
1883
ab9c17a0
JM		 1884static void mlx4_slave_exit(struct mlx4_dev *dev)
1885{
1886 struct mlx4_priv *priv = mlx4_priv(dev);
1887
f3d4c89e 1888 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1889 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1890 MLX4_COMM_TIME))
1a91de28 1891 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1892 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1893}
1894
c1b43dca
EC		 1895static int map_bf_area(struct mlx4_dev *dev)
1896{
1897 struct mlx4_priv *priv = mlx4_priv(dev);
1898 resource_size_t bf_start;
1899 resource_size_t bf_len;
1900 int err = 0;
1901
3d747473
JM		 1902 if (!dev->caps.bf_reg_size)
1903 return -ENXIO;
1904
872bf2fb 1905 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1906 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1907 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1908 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1909 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1910 if (!priv->bf_mapping)
1911 err = -ENOMEM;
1912
1913 return err;
1914}
1915
1916static void unmap_bf_area(struct mlx4_dev *dev)
1917{
1918 if (mlx4_priv(dev)->bf_mapping)
1919 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1920}
1921
a5a1d1c2 1922u64 mlx4_read_clock(struct mlx4_dev *dev)
ec693d47
AV		 1923{
1924 u32 clockhi, clocklo, clockhi1;
a5a1d1c2 1925 u64 cycles;
ec693d47
AV		 1926 int i;
1927 struct mlx4_priv *priv = mlx4_priv(dev);
1928
1929 for (i = 0; i < 10; i++) {
1930 clockhi = swab32(readl(priv->clock_mapping));
1931 clocklo = swab32(readl(priv->clock_mapping + 4));
1932 clockhi1 = swab32(readl(priv->clock_mapping));
1933 if (clockhi == clockhi1)
1934 break;
1935 }
1936
1937 cycles = (u64) clockhi << 32 | (u64) clocklo;
1938
1939 return cycles;
1940}
1941EXPORT_SYMBOL_GPL(mlx4_read_clock);
1942
1943
ddd8a6c1
EE		 1944static int map_internal_clock(struct mlx4_dev *dev)
1945{
1946 struct mlx4_priv *priv = mlx4_priv(dev);
1947
1948 priv->clock_mapping =
872bf2fb
YH		 1949 ioremap(pci_resource_start(dev->persist->pdev,
1950 priv->fw.clock_bar) +
ddd8a6c1
EE		 1951 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1952
1953 if (!priv->clock_mapping)
1954 return -ENOMEM;
1955
1956 return 0;
1957}
1958
52033cfb
MB		 1959int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1960 struct mlx4_clock_params *params)
1961{
1962 struct mlx4_priv *priv = mlx4_priv(dev);
1963
1964 if (mlx4_is_slave(dev))
423b3aec 1965 return -EOPNOTSUPP;
52033cfb 1966
404e5a12
SD		 1967 if (!dev->caps.map_clock_to_user) {
1968 mlx4_dbg(dev, "Map clock to user is not supported.\n");
1969 return -EOPNOTSUPP;
1970 }
1971
52033cfb
MB		 1972 if (!params)
1973 return -EINVAL;
1974
1975 params->bar = priv->fw.clock_bar;
1976 params->offset = priv->fw.clock_offset;
1977 params->size = MLX4_CLOCK_SIZE;
1978
1979 return 0;
1980}
1981EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1982
ddd8a6c1
EE		 1983static void unmap_internal_clock(struct mlx4_dev *dev)
1984{
1985 struct mlx4_priv *priv = mlx4_priv(dev);
1986
1987 if (priv->clock_mapping)
1988 iounmap(priv->clock_mapping);
1989}
1990
225c7b1f
RD		 1991static void mlx4_close_hca(struct mlx4_dev *dev)
1992{
ddd8a6c1 1993 unmap_internal_clock(dev);
c1b43dca 1994 unmap_bf_area(dev);
ab9c17a0
JM		 1995 if (mlx4_is_slave(dev))
1996 mlx4_slave_exit(dev);
1997 else {
1998 mlx4_CLOSE_HCA(dev, 0);
1999 mlx4_free_icms(dev);
a0eacca9
MB		 2000 }
2001}
2002
2003static void mlx4_close_fw(struct mlx4_dev *dev)
2004{
2005 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2006 mlx4_UNMAP_FA(dev);
2007 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
2008 }
2009}
2010
55ad3592
YH		 2011static int mlx4_comm_check_offline(struct mlx4_dev *dev)
2012{
2013#define COMM_CHAN_OFFLINE_OFFSET 0x09
2014
2015 u32 comm_flags;
2016 u32 offline_bit;
2017 unsigned long end;
2018 struct mlx4_priv *priv = mlx4_priv(dev);
2019
2020 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
2021 while (time_before(jiffies, end)) {
2022 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
2023 MLX4_COMM_CHAN_FLAGS));
2024 offline_bit = (comm_flags &
2025 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
2026 if (!offline_bit)
2027 return 0;
4cbe4dac
JM		 2028
2029 /* If device removal has been requested,
2030 * do not continue retrying.
2031 */
2032 if (dev->persist->interface_state &
2033 MLX4_INTERFACE_STATE_NOWAIT)
2034 break;
2035
55ad3592
YH		 2036 /* There are cases as part of AER/Reset flow that PF needs
2037 * around 100 msec to load. We therefore sleep for 100 msec
2038 * to allow other tasks to make use of that CPU during this
2039 * time interval.
2040 */
2041 msleep(100);
2042 }
2043 mlx4_err(dev, "Communication channel is offline.\n");
2044 return -EIO;
2045}
2046
2047static void mlx4_reset_vf_support(struct mlx4_dev *dev)
2048{
2049#define COMM_CHAN_RST_OFFSET 0x1e
2050
2051 struct mlx4_priv *priv = mlx4_priv(dev);
2052 u32 comm_rst;
2053 u32 comm_caps;
2054
2055 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
2056 MLX4_COMM_CHAN_CAPS));
2057 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
2058
2059 if (comm_rst)
2060 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2061}
2062
ab9c17a0
JM		 2063static int mlx4_init_slave(struct mlx4_dev *dev)
2064{
2065 struct mlx4_priv *priv = mlx4_priv(dev);
2066 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 2067 int ret_from_reset = 0;
2068 u32 slave_read;
2069 u32 cmd_channel_ver;
2070
97989356 2071 if (atomic_read(&pf_loading)) {
1a91de28 2072 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 2073 return -EPROBE_DEFER;
2074 }
2075
f3d4c89e 2076 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2077 priv->cmd.max_cmds = 1;
55ad3592
YH		 2078 if (mlx4_comm_check_offline(dev)) {
2079 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
2080 goto err_offline;
2081 }
2082
2083 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 2084 mlx4_warn(dev, "Sending reset\n");
2085 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 2086 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 2087 /* if we are in the middle of flr the slave will try
2088 * NUM_OF_RESET_RETRIES times before leaving.*/
2089 if (ret_from_reset) {
2090 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 2091 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 2092 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2093 return -EPROBE_DEFER;
ab9c17a0
JM		 2094 } else
2095 goto err;
2096 }
2097
2098 /* check the driver version - the slave I/F revision
2099 * must match the master's */
2100 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2101 cmd_channel_ver = mlx4_comm_get_version();
2102
2103 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2104 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 2105 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 2106 goto err;
2107 }
2108
2109 mlx4_warn(dev, "Sending vhcr0\n");
2110 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 2111 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2112 goto err;
2113 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 2114 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2115 goto err;
2116 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 2117 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2118 goto err;
0cd93027
YH		 2119 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2120 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2121 goto err;
f3d4c89e
RD		 2122
2123 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 2124 return 0;
2125
2126err:
0cd93027 2127 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 2128err_offline:
f3d4c89e 2129 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2130 return -EIO;
225c7b1f
RD		 2131}
2132
6634961c
JM		 2133static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2134{
2135 int i;
2136
2137 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 2138 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2139 dev->caps.gid_table_len[i] =
449fc488 2140 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 2141 else
2142 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 2143 dev->caps.pkey_table_len[i] =
2144 dev->phys_caps.pkey_phys_table_len[i] - 1;
2145 }
2146}
2147
3c439b55
JM		 2148static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2149{
2150 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2151
2152 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2153 i++) {
2154 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2155 break;
2156 }
2157
2158 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2159}
2160
7d077cd3
MB		 2161static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2162{
2163 switch (dmfs_high_steer_mode) {
2164 case MLX4_STEERING_DMFS_A0_DEFAULT:
2165 return "default performance";
2166
2167 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2168 return "dynamic hybrid mode";
2169
2170 case MLX4_STEERING_DMFS_A0_STATIC:
2171 return "performance optimized for limited rule configuration (static)";
2172
2173 case MLX4_STEERING_DMFS_A0_DISABLE:
2174 return "disabled performance optimized steering";
2175
2176 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2177 return "performance optimized steering not supported";
2178
2179 default:
2180 return "Unrecognized mode";
2181 }
2182}
2183
2184#define MLX4_DMFS_A0_STEERING (1UL << 2)
2185
7b8157be
JM		 2186static void choose_steering_mode(struct mlx4_dev *dev,
2187 struct mlx4_dev_cap *dev_cap)
2188{
7d077cd3
MB		 2189 if (mlx4_log_num_mgm_entry_size <= 0) {
2190 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2191 if (dev->caps.dmfs_high_steer_mode ==
2192 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2193 mlx4_err(dev, "DMFS high rate mode not supported\n");
2194 else
2195 dev->caps.dmfs_high_steer_mode =
2196 MLX4_STEERING_DMFS_A0_STATIC;
2197 }
2198 }
2199
2200 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 2201 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 2202 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 2203 (dev_cap->fs_max_num_qp_per_entry >=
2204 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 2205 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2206 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2207 dev->oper_log_mgm_entry_size =
2208 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 2209 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2210 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2211 dev->caps.fs_log_max_ucast_qp_range_size =
2212 dev_cap->fs_log_max_ucast_qp_range_size;
2213 } else {
7d077cd3
MB		 2214 if (dev->caps.dmfs_high_steer_mode !=
2215 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2216 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 2217 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2218 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2219 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2220 else {
2221 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2222
2223 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2224 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 2225 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 2226 }
3c439b55
JM		 2227 dev->oper_log_mgm_entry_size =
2228 mlx4_log_num_mgm_entry_size > 0 ?
2229 mlx4_log_num_mgm_entry_size :
2230 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 2231 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2232 }
1a91de28 2233 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 2234 mlx4_steering_mode_str(dev->caps.steering_mode),
2235 dev->oper_log_mgm_entry_size,
2236 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 2237}
2238
7ffdf726
OG		 2239static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2240 struct mlx4_dev_cap *dev_cap)
2241{
2242 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 2243 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 2244 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2245 else
2246 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2247
2248 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2249 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2250}
2251
7d077cd3
MB		 2252static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2253{
2254 int i;
2255 struct mlx4_port_cap port_cap;
2256
2257 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2258 return -EINVAL;
2259
2260 for (i = 1; i <= dev->caps.num_ports; i++) {
2261 if (mlx4_dev_port(dev, i, &port_cap)) {
2262 mlx4_err(dev,
f4b752a6 2263 "QUERY_DEV_CAP command failed, can't verify DMFS high rate steering.\n");
7d077cd3
MB		 2264 } else if ((dev->caps.dmfs_high_steer_mode !=
2265 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2266 (port_cap.dmfs_optimized_state ==
2267 !!(dev->caps.dmfs_high_steer_mode ==
2268 MLX4_STEERING_DMFS_A0_DISABLE))) {
2269 mlx4_err(dev,
2270 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2271 dmfs_high_rate_steering_mode_str(
2272 dev->caps.dmfs_high_steer_mode),
2273 (port_cap.dmfs_optimized_state ?
2274 "enabled" : "disabled"));
2275 }
2276 }
2277
2278 return 0;
2279}
2280
a0eacca9 2281static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2282{
2d928651 2283 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2284 int err = 0;
225c7b1f 2285
ab9c17a0
JM		 2286 if (!mlx4_is_slave(dev)) {
2287 err = mlx4_QUERY_FW(dev);
2288 if (err) {
2289 if (err == -EACCES)
1a91de28 2290 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2291 else
1a91de28 2292 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2293 return err;
ab9c17a0 2294 }
225c7b1f 2295
ab9c17a0
JM		 2296 err = mlx4_load_fw(dev);
2297 if (err) {
1a91de28 2298 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2299 return err;
ab9c17a0 2300 }
225c7b1f 2301
ab9c17a0
JM		 2302 mlx4_cfg.log_pg_sz_m = 1;
2303 mlx4_cfg.log_pg_sz = 0;
2304 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2305 if (err)
2306 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2307 }
2d928651 2308
a0eacca9
MB		 2309 return err;
2310}
2311
2312static int mlx4_init_hca(struct mlx4_dev *dev)
2313{
2314 struct mlx4_priv *priv = mlx4_priv(dev);
9eed21c0
AB		 2315 struct mlx4_init_hca_param *init_hca = NULL;
2316 struct mlx4_dev_cap *dev_cap = NULL;
a0eacca9 2317 struct mlx4_adapter adapter;
a0eacca9 2318 struct mlx4_profile profile;
a0eacca9
MB		 2319 u64 icm_size;
2320 struct mlx4_config_dev_params params;
2321 int err;
2322
2323 if (!mlx4_is_slave(dev)) {
9eed21c0
AB		 2324 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2325 init_hca = kzalloc(sizeof(*init_hca), GFP_KERNEL);
2326
2327 if (!dev_cap || !init_hca) {
2328 err = -ENOMEM;
2329 goto out_free;
2330 }
2331
2332 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 2333 if (err) {
1a91de28 2334 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
9eed21c0 2335 goto out_free;
ab9c17a0 2336 }
225c7b1f 2337
9eed21c0
AB		 2338 choose_steering_mode(dev, dev_cap);
2339 choose_tunnel_offload_mode(dev, dev_cap);
7b8157be 2340
7d077cd3
MB		 2341 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2342 mlx4_is_master(dev))
2343 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2344
8e1a28e8
HHZ		 2345 err = mlx4_get_phys_port_id(dev);
2346 if (err)
2347 mlx4_err(dev, "Fail to get physical port id\n");
2348
6634961c
JM		 2349 if (mlx4_is_master(dev))
2350 mlx4_parav_master_pf_caps(dev);
2351
2599d858
AV		 2352 if (mlx4_low_memory_profile()) {
2353 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2354 profile = low_mem_profile;
2355 } else {
2356 profile = default_profile;
2357 }
0ff1fb65
HHZ		 2358 if (dev->caps.steering_mode ==
2359 MLX4_STEERING_MODE_DEVICE_MANAGED)
2360 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2361
9eed21c0
AB		 2362 icm_size = mlx4_make_profile(dev, &profile, dev_cap,
2363 init_hca);
ab9c17a0
JM		 2364 if ((long long) icm_size < 0) {
2365 err = icm_size;
9eed21c0 2366 goto out_free;
ab9c17a0 2367 }
225c7b1f 2368
ca3d89a3 2369 if (enable_4k_uar || !dev->persist->num_vfs) {
9eed21c0 2370 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) +
76e39ccf 2371 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
9eed21c0 2372 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
76e39ccf 2373 } else {
9eed21c0
AB		 2374 init_hca->log_uar_sz = ilog2(dev->caps.num_uars);
2375 init_hca->uar_page_sz = PAGE_SHIFT - 12;
76e39ccf 2376 }
85743f1e 2377
9eed21c0 2378 init_hca->mw_enabled = 0;
e448834e
SM		 2379 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2380 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
9eed21c0 2381 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2382
9eed21c0 2383 err = mlx4_init_icm(dev, dev_cap, init_hca, icm_size);
ab9c17a0 2384 if (err)
9eed21c0 2385 goto out_free;
225c7b1f 2386
9eed21c0 2387 err = mlx4_INIT_HCA(dev, init_hca);
ab9c17a0 2388 if (err) {
1a91de28 2389 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2390 goto err_free_icm;
2391 }
7ae0e400 2392
9eed21c0
AB		 2393 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2394 err = mlx4_query_func(dev, dev_cap);
7ae0e400
MB		 2395 if (err < 0) {
2396 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2397 goto err_close;
7ae0e400 2398 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
9eed21c0
AB		 2399 dev->caps.num_eqs = dev_cap->max_eqs;
2400 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2401 dev->caps.reserved_uars = dev_cap->reserved_uars;
7ae0e400
MB		 2402 }
2403 }
2404
ddd8a6c1
EE		 2405 /*
2406 * If TS is supported by FW
2407 * read HCA frequency by QUERY_HCA command
2408 */
2409 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
9eed21c0 2410 err = mlx4_QUERY_HCA(dev, init_hca);
ddd8a6c1 2411 if (err) {
1a91de28 2412 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2413 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2414 } else {
2415 dev->caps.hca_core_clock =
9eed21c0 2416 init_hca->hca_core_clock;
ddd8a6c1
EE		 2417 }
2418
2419 /* In case we got HCA frequency 0 - disable timestamping
2420 * to avoid dividing by zero
2421 */
2422 if (!dev->caps.hca_core_clock) {
2423 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2424 mlx4_err(dev,
1a91de28 2425 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2426 } else if (map_internal_clock(dev)) {
2427 /*
2428 * Map internal clock,
2429 * in case of failure disable timestamping
2430 */
2431 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2432 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2433 }
2434 }
7d077cd3
MB		 2435
2436 if (dev->caps.dmfs_high_steer_mode !=
2437 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2438 if (mlx4_validate_optimized_steering(dev))
2439 mlx4_warn(dev, "Optimized steering validation failed\n");
2440
2441 if (dev->caps.dmfs_high_steer_mode ==
2442 MLX4_STEERING_DMFS_A0_DISABLE) {
2443 dev->caps.dmfs_high_rate_qpn_base =
2444 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2445 dev->caps.dmfs_high_rate_qpn_range =
2446 MLX4_A0_STEERING_TABLE_SIZE;
2447 }
2448
4931c6ef
SM		 2449 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2450 dmfs_high_rate_steering_mode_str(
7d077cd3
MB		 2451 dev->caps.dmfs_high_steer_mode));
2452 }
ab9c17a0
JM		 2453 } else {
2454 err = mlx4_init_slave(dev);
2455 if (err) {
5efe5355
JM		 2456 if (err != -EPROBE_DEFER)
2457 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2458 return err;
ab9c17a0 2459 }
225c7b1f 2460
ab9c17a0
JM		 2461 err = mlx4_slave_cap(dev);
2462 if (err) {
2463 mlx4_err(dev, "Failed to obtain slave caps\n");
2464 goto err_close;
2465 }
225c7b1f
RD		 2466 }
2467
ab9c17a0
JM		 2468 if (map_bf_area(dev))
2469 mlx4_dbg(dev, "Failed to map blue flame area\n");
2470
2471 /*Only the master set the ports, all the rest got it from it.*/
2472 if (!mlx4_is_slave(dev))
2473 mlx4_set_port_mask(dev);
2474
225c7b1f
RD		 2475 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2476 if (err) {
1a91de28 2477 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2478 goto unmap_bf;
225c7b1f
RD		 2479 }
2480
f8c6455b
SM		 2481 /* Query CONFIG_DEV parameters */
2482 err = mlx4_config_dev_retrieval(dev, &params);
423b3aec 2483 if (err && err != -EOPNOTSUPP) {
f8c6455b
SM		 2484 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2485 } else if (!err) {
2486 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2487 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2488 }
225c7b1f 2489 priv->eq_table.inta_pin = adapter.inta_pin;
31975e27 2490 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
225c7b1f 2491
9eed21c0
AB		 2492 err = 0;
2493 goto out_free;
225c7b1f 2494
bef772eb 2495unmap_bf:
ddd8a6c1 2496 unmap_internal_clock(dev);
bef772eb
AY		 2497 unmap_bf_area(dev);
2498
c73c8b1e
EBE		 2499 if (mlx4_is_slave(dev))
2500 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 2501
225c7b1f 2502err_close:
41929ed2
DB		 2503 if (mlx4_is_slave(dev))
2504 mlx4_slave_exit(dev);
2505 else
2506 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2507
2508err_free_icm:
ab9c17a0
JM		 2509 if (!mlx4_is_slave(dev))
2510 mlx4_free_icms(dev);
225c7b1f 2511
9eed21c0
AB		 2512out_free:
2513 kfree(dev_cap);
2514 kfree(init_hca);
2515
225c7b1f
RD		 2516 return err;
2517}
2518
f2a3f6a3
OG		 2519static int mlx4_init_counters_table(struct mlx4_dev *dev)
2520{
2521 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2522 int nent_pow2;
f2a3f6a3
OG		 2523
2524 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2525 return -ENOENT;
2526
2632d18d
EBE		 2527 if (!dev->caps.max_counters)
2528 return -ENOSPC;
2529
47d8417f
EBE		 2530 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2531 /* reserve last counter index for sink counter */
2532 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2533 nent_pow2 - 1, 0,
2534 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2535}
2536
2537static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2538{
efa6bc91
EBE		 2539 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2540 return;
2541
2632d18d
EBE		 2542 if (!dev->caps.max_counters)
2543 return;
2544
f2a3f6a3
OG		 2545 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2546}
2547
6de5f7f6
EBE		 2548static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2549{
2550 struct mlx4_priv *priv = mlx4_priv(dev);
2551 int port;
2552
2553 for (port = 0; port < dev->caps.num_ports; port++)
2554 if (priv->def_counter[port] != -1)
2555 mlx4_counter_free(dev, priv->def_counter[port]);
2556}
2557
2558static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2559{
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2561 int port, err = 0;
2562 u32 idx;
2563
2564 for (port = 0; port < dev->caps.num_ports; port++)
2565 priv->def_counter[port] = -1;
2566
2567 for (port = 0; port < dev->caps.num_ports; port++) {
f3301870 2568 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
6de5f7f6
EBE		 2569
2570 if (!err || err == -ENOSPC) {
2571 priv->def_counter[port] = idx;
40e47307 2572 err = 0;
6de5f7f6
EBE		 2573 } else if (err == -ENOENT) {
2574 err = 0;
2575 continue;
178d23e3
OG		 2576 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2577 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2578 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2579 MLX4_SINK_COUNTER_INDEX(dev));
2580 err = 0;
6de5f7f6
EBE		 2581 } else {
2582 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2583 __func__, port + 1, err);
2584 mlx4_cleanup_default_counters(dev);
2585 return err;
2586 }
2587
2588 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2589 __func__, priv->def_counter[port], port + 1);
2590 }
2591
2592 return err;
2593}
2594
ba062d52 2595int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2596{
2597 struct mlx4_priv *priv = mlx4_priv(dev);
2598
2599 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2600 return -ENOENT;
2601
2602 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2603 if (*idx == -1) {
2604 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2605 return -ENOSPC;
2606 }
f2a3f6a3
OG		 2607
2608 return 0;
2609}
ba062d52 2610
f3301870 2611int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
ba062d52 2612{
f3301870 2613 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
ba062d52
JM		 2614 u64 out_param;
2615 int err;
2616
2617 if (mlx4_is_mfunc(dev)) {
f3301870 2618 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
ba062d52
JM		 2619 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2620 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2621 if (!err)
2622 *idx = get_param_l(&out_param);
40e47307
TT		 2623 if (WARN_ON(err == -ENOSPC))
2624 err = -EINVAL;
ba062d52
JM		 2625 return err;
2626 }
2627 return __mlx4_counter_alloc(dev, idx);
2628}
f2a3f6a3
OG		 2629EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2630
b72ca7e9
EBE		 2631static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2632 u8 counter_index)
2633{
2634 struct mlx4_cmd_mailbox *if_stat_mailbox;
2635 int err;
2636 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2637
2638 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2639 if (IS_ERR(if_stat_mailbox))
2640 return PTR_ERR(if_stat_mailbox);
2641
2642 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2643 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2644 MLX4_CMD_NATIVE);
2645
2646 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2647 return err;
2648}
2649
ba062d52 2650void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2651{
efa6bc91
EBE		 2652 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2653 return;
2654
6de5f7f6
EBE		 2655 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2656 return;
2657
b72ca7e9
EBE		 2658 __mlx4_clear_if_stat(dev, idx);
2659
7c6d74d2 2660 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2661 return;
2662}
ba062d52
JM		 2663
2664void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2665{
e7dbeba8 2666 u64 in_param = 0;
ba062d52
JM		 2667
2668 if (mlx4_is_mfunc(dev)) {
2669 set_param_l(&in_param, idx);
2670 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2671 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2672 MLX4_CMD_WRAPPED);
2673 return;
2674 }
2675 __mlx4_counter_free(dev, idx);
2676}
f2a3f6a3
OG		 2677EXPORT_SYMBOL_GPL(mlx4_counter_free);
2678
6de5f7f6
EBE		 2679int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2680{
2681 struct mlx4_priv *priv = mlx4_priv(dev);
2682
2683 return priv->def_counter[port - 1];
2684}
2685EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2686
773af94e
YH		 2687void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2688{
2689 struct mlx4_priv *priv = mlx4_priv(dev);
2690
2691 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2692}
2693EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2694
2695__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2696{
2697 struct mlx4_priv *priv = mlx4_priv(dev);
2698
2699 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2700}
2701EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2702
fb517a4f
YH		 2703void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2704{
2705 struct mlx4_priv *priv = mlx4_priv(dev);
2706 __be64 guid;
2707
2708 /* hw GUID */
2709 if (entry == 0)
2710 return;
2711
2712 get_random_bytes((char *)&guid, sizeof(guid));
2713 guid &= ~(cpu_to_be64(1ULL << 56));
2714 guid |= cpu_to_be64(1ULL << 57);
2715 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2716}
2717
3d73c288 2718static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2719{
2720 struct mlx4_priv *priv = mlx4_priv(dev);
2721 int err;
7ff93f8b 2722 int port;
9a5aa622 2723 __be32 ib_port_default_caps;
225c7b1f 2724
225c7b1f
RD		 2725 err = mlx4_init_uar_table(dev);
2726 if (err) {
1a91de28 2727 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
5d4de16c 2728 return err;
225c7b1f
RD		 2729 }
2730
2731 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2732 if (err) {
1a91de28 2733 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2734 goto err_uar_table_free;
2735 }
2736
4979d18f 2737 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2738 if (!priv->kar) {
1a91de28 2739 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2740 err = -ENOMEM;
2741 goto err_uar_free;
2742 }
2743
2744 err = mlx4_init_pd_table(dev);
2745 if (err) {
1a91de28 2746 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2747 goto err_kar_unmap;
2748 }
2749
012a8ff5
SH		 2750 err = mlx4_init_xrcd_table(dev);
2751 if (err) {
1a91de28 2752 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2753 goto err_pd_table_free;
2754 }
2755
225c7b1f
RD		 2756 err = mlx4_init_mr_table(dev);
2757 if (err) {
1a91de28 2758 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2759 goto err_xrcd_table_free;
225c7b1f
RD		 2760 }
2761
fe6f700d
YP		 2762 if (!mlx4_is_slave(dev)) {
2763 err = mlx4_init_mcg_table(dev);
2764 if (err) {
1a91de28 2765 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2766 goto err_mr_table_free;
2767 }
114840c3
JM		 2768 err = mlx4_config_mad_demux(dev);
2769 if (err) {
2770 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2771 goto err_mcg_table_free;
2772 }
fe6f700d
YP		 2773 }
2774
225c7b1f
RD		 2775 err = mlx4_init_eq_table(dev);
2776 if (err) {
1a91de28 2777 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2778 goto err_mcg_table_free;
225c7b1f
RD		 2779 }
2780
2781 err = mlx4_cmd_use_events(dev);
2782 if (err) {
1a91de28 2783 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2784 goto err_eq_table_free;
2785 }
2786
2787 err = mlx4_NOP(dev);
2788 if (err) {
08fb1055 2789 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2790 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2791 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2792 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2793 } else {
1a91de28 2794 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2795 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2796 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2797 }
225c7b1f
RD		 2798
2799 goto err_cmd_poll;
2800 }
2801
2802 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2803
2804 err = mlx4_init_cq_table(dev);
2805 if (err) {
1a91de28 2806 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2807 goto err_cmd_poll;
2808 }
2809
2810 err = mlx4_init_srq_table(dev);
2811 if (err) {
1a91de28 2812 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2813 goto err_cq_table_free;
2814 }
2815
2816 err = mlx4_init_qp_table(dev);
2817 if (err) {
1a91de28 2818 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2819 goto err_srq_table_free;
2820 }
2821
2632d18d
EBE		 2822 if (!mlx4_is_slave(dev)) {
2823 err = mlx4_init_counters_table(dev);
2824 if (err && err != -ENOENT) {
2825 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2826 goto err_qp_table_free;
2827 }
f2a3f6a3
OG		 2828 }
2829
6de5f7f6
EBE		 2830 err = mlx4_allocate_default_counters(dev);
2831 if (err) {
2832 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2833 goto err_counters_table_free;
f2a3f6a3
OG		 2834 }
2835
ab9c17a0
JM		 2836 if (!mlx4_is_slave(dev)) {
2837 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2838 ib_port_default_caps = 0;
2839 err = mlx4_get_port_ib_caps(dev, port,
2840 &ib_port_default_caps);
2841 if (err)
1a91de28
JP		 2842 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2843 port, err);
ab9c17a0
JM		 2844 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2845
2aca1172
JM		 2846 /* initialize per-slave default ib port capabilities */
2847 if (mlx4_is_master(dev)) {
2848 int i;
2849 for (i = 0; i < dev->num_slaves; i++) {
2850 if (i == mlx4_master_func_num(dev))
2851 continue;
2852 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2853 ib_port_default_caps;
2aca1172
JM		 2854 }
2855 }
2856
096335b3
OG		 2857 if (mlx4_is_mfunc(dev))
2858 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2859 else
2860 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2861
6634961c
JM		 2862 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2863 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2864 if (err) {
2865 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2866 port);
6de5f7f6 2867 goto err_default_countes_free;
ab9c17a0 2868 }
7ff93f8b
YP		 2869 }
2870 }
2871
225c7b1f
RD		 2872 return 0;
2873
6de5f7f6
EBE		 2874err_default_countes_free:
2875 mlx4_cleanup_default_counters(dev);
2876
f2a3f6a3 2877err_counters_table_free:
2632d18d
EBE		 2878 if (!mlx4_is_slave(dev))
2879 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2880
225c7b1f
RD		 2881err_qp_table_free:
2882 mlx4_cleanup_qp_table(dev);
2883
2884err_srq_table_free:
2885 mlx4_cleanup_srq_table(dev);
2886
2887err_cq_table_free:
2888 mlx4_cleanup_cq_table(dev);
2889
2890err_cmd_poll:
2891 mlx4_cmd_use_polling(dev);
2892
2893err_eq_table_free:
2894 mlx4_cleanup_eq_table(dev);
2895
fe6f700d
YP		 2896err_mcg_table_free:
2897 if (!mlx4_is_slave(dev))
2898 mlx4_cleanup_mcg_table(dev);
2899
ee49bd93 2900err_mr_table_free:
225c7b1f
RD		 2901 mlx4_cleanup_mr_table(dev);
2902
012a8ff5
SH		 2903err_xrcd_table_free:
2904 mlx4_cleanup_xrcd_table(dev);
2905
225c7b1f
RD		 2906err_pd_table_free:
2907 mlx4_cleanup_pd_table(dev);
2908
2909err_kar_unmap:
2910 iounmap(priv->kar);
2911
2912err_uar_free:
2913 mlx4_uar_free(dev, &priv->driver_uar);
2914
2915err_uar_table_free:
2916 mlx4_cleanup_uar_table(dev);
2917 return err;
2918}
2919
de161803
IS		 2920static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2921{
2922 int requested_cpu = 0;
2923 struct mlx4_priv *priv = mlx4_priv(dev);
2924 struct mlx4_eq *eq;
2925 int off = 0;
2926 int i;
2927
2928 if (eqn > dev->caps.num_comp_vectors)
2929 return -EINVAL;
2930
2931 for (i = 1; i < port; i++)
2932 off += mlx4_get_eqs_per_port(dev, i);
2933
2934 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2935
2936 /* Meaning EQs are shared, and this call comes from the second port */
2937 if (requested_cpu < 0)
2938 return 0;
2939
2940 eq = &priv->eq_table.eq[eqn];
2941
2942 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2943 return -ENOMEM;
2944
2945 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2946
2947 return 0;
2948}
2949
e8f9b2ed 2950static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2951{
2952 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2953 struct msix_entry *entries;
225c7b1f 2954 int i;
c66fa19c 2955 int port = 0;
225c7b1f
RD		 2956
2957 if (msi_x) {
4762010f 2958 int nreq = min3(dev->caps.num_ports *
2959 (int)num_online_cpus() + 1,
2960 dev->caps.num_eqs - dev->caps.reserved_eqs,
2961 MAX_MSIX);
ab9c17a0 2962
e5732838
TT		 2963 if (msi_x > 1)
2964 nreq = min_t(int, nreq, msi_x);
2965
31975e27 2966 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
b8dd786f
YP		 2967 if (!entries)
2968 goto no_msi;
2969
2970 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2971 entries[i].entry = i;
2972
872bf2fb
YH		 2973 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2974 nreq);
66e2f9c1 2975
c66fa19c 2976 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2977 kfree(entries);
225c7b1f 2978 goto no_msi;
0b7ca5a9 2979 }
c66fa19c
MB		 2980 /* 1 is reserved for events (asyncrounous EQ) */
2981 dev->caps.num_comp_vectors = nreq - 1;
2982
2983 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2984 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2985 dev->caps.num_ports);
2986
2987 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2988 if (i == MLX4_EQ_ASYNC)
2989 continue;
2990
2991 priv->eq_table.eq[i].irq =
2992 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2993
85121d6e 2994 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
c66fa19c
MB		 2995 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2996 dev->caps.num_ports);
de161803
IS		 2997 /* We don't set affinity hint when there
2998 * aren't enough EQs
2999 */
c66fa19c
MB		 3000 } else {
3001 set_bit(port,
3002 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 3003 if (mlx4_init_affinity_hint(dev, port + 1, i))
3004 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
3005 i);
c66fa19c
MB		 3006 }
3007 /* We divide the Eqs evenly between the two ports.
3008 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
3009 * refers to the number of Eqs per port
3010 * (i.e eqs_per_port). Theoretically, we would like to
3011 * write something like (i + 1) % eqs_per_port == 0.
3012 * However, since there's an asynchronous Eq, we have
3013 * to skip over it by comparing this condition to
3014 * !!((i + 1) > MLX4_EQ_ASYNC).
3015 */
3016 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
3017 ((i + 1) %
3018 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
3019 !!((i + 1) > MLX4_EQ_ASYNC))
3020 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
3021 * everything is shared anyway.
3022 */
3023 port++;
3024 }
225c7b1f
RD		 3025
3026 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 3027
3028 kfree(entries);
225c7b1f
RD		 3029 return;
3030 }
3031
3032no_msi:
b8dd786f
YP		 3033 dev->caps.num_comp_vectors = 1;
3034
c66fa19c
MB		 3035 BUG_ON(MLX4_EQ_ASYNC >= 2);
3036 for (i = 0; i < 2; ++i) {
872bf2fb 3037 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 3038 if (i != MLX4_EQ_ASYNC) {
3039 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
3040 dev->caps.num_ports);
3041 }
3042 }
225c7b1f
RD		 3043}
3044
65a4c44b
JP		 3045static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3046 enum devlink_port_type port_type)
3047{
3048 struct mlx4_port_info *info = container_of(devlink_port,
3049 struct mlx4_port_info,
3050 devlink_port);
3051 enum mlx4_port_type mlx4_port_type;
3052
3053 switch (port_type) {
3054 case DEVLINK_PORT_TYPE_AUTO:
3055 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3056 break;
3057 case DEVLINK_PORT_TYPE_ETH:
3058 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3059 break;
3060 case DEVLINK_PORT_TYPE_IB:
3061 mlx4_port_type = MLX4_PORT_TYPE_IB;
3062 break;
3063 default:
3064 return -EOPNOTSUPP;
3065 }
3066
3067 return __set_port_type(info, mlx4_port_type);
3068}
3069
8a756d91 3070static const struct devlink_port_ops mlx4_devlink_port_ops = {
65a4c44b 3071 .port_type_set = mlx4_devlink_port_type_set,
8a756d91
JP		 3072};
3073
7ff93f8b 3074static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8 3075{
09d4d087 3076 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2a2336f8 3077 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
09d4d087
JP		 3078 int err;
3079
8a756d91
JP		 3080 err = devl_port_register_with_ops(devlink, &info->devlink_port, port,
3081 &mlx4_devlink_port_ops);
09d4d087
JP		 3082 if (err)
3083 return err;
2a2336f8 3084
0313c7c2
JK		 3085 /* Ethernet and IB drivers will normally set the port type,
3086 * but if they are not built set the type now to prevent
3087 * devlink_port_type_warn() from firing.
3088 */
3089 if (!IS_ENABLED(CONFIG_MLX4_EN) &&
3090 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
c8096578 3091 devlink_port_type_eth_set(&info->devlink_port);
0313c7c2
JK		 3092 else if (!IS_ENABLED(CONFIG_MLX4_INFINIBAND) &&
3093 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
3094 devlink_port_type_ib_set(&info->devlink_port, NULL);
3095
2a2336f8
YP		 3096 info->dev = dev;
3097 info->port = port;
ab9c17a0 3098 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 3099 mlx4_init_mac_table(dev, &info->mac_table);
3100 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 3101 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 3102 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 3103 }
7ff93f8b
YP		 3104
3105 sprintf(info->dev_name, "mlx4_port%d", port);
3106 info->port_attr.attr.name = info->dev_name;
d3757ba4
JP		 3107 if (mlx4_is_mfunc(dev)) {
3108 info->port_attr.attr.mode = 0444;
3109 } else {
3110 info->port_attr.attr.mode = 0644;
ab9c17a0
JM		 3111 info->port_attr.store = set_port_type;
3112 }
7ff93f8b 3113 info->port_attr.show = show_port_type;
3691c964 3114 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 3115
872bf2fb 3116 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 3117 if (err) {
3118 mlx4_err(dev, "Failed to create file for port %d\n", port);
de9d555c 3119 devlink_port_type_clear(&info->devlink_port);
a8c05514 3120 devl_port_unregister(&info->devlink_port);
7ff93f8b 3121 info->port = -1;
57f6f99f 3122 return err;
7ff93f8b
YP		 3123 }
3124
096335b3
OG		 3125 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3126 info->port_mtu_attr.attr.name = info->dev_mtu_name;
d3757ba4
JP		 3127 if (mlx4_is_mfunc(dev)) {
3128 info->port_mtu_attr.attr.mode = 0444;
3129 } else {
3130 info->port_mtu_attr.attr.mode = 0644;
096335b3
OG		 3131 info->port_mtu_attr.store = set_port_ib_mtu;
3132 }
3133 info->port_mtu_attr.show = show_port_ib_mtu;
3134 sysfs_attr_init(&info->port_mtu_attr.attr);
3135
872bf2fb
YH		 3136 err = device_create_file(&dev->persist->pdev->dev,
3137 &info->port_mtu_attr);
096335b3
OG		 3138 if (err) {
3139 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 3140 device_remove_file(&info->dev->persist->pdev->dev,
3141 &info->port_attr);
de9d555c 3142 devlink_port_type_clear(&info->devlink_port);
a8c05514 3143 devl_port_unregister(&info->devlink_port);
096335b3 3144 info->port = -1;
57f6f99f 3145 return err;
096335b3
OG		 3146 }
3147
57f6f99f 3148 return 0;
7ff93f8b
YP		 3149}
3150
3151static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3152{
3153 if (info->port < 0)
3154 return;
3155
872bf2fb
YH		 3156 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3157 device_remove_file(&info->dev->persist->pdev->dev,
3158 &info->port_mtu_attr);
de9d555c 3159 devlink_port_type_clear(&info->devlink_port);
a8c05514 3160 devl_port_unregister(&info->devlink_port);
fba12966 3161
c66fa19c
MB		 3162#ifdef CONFIG_RFS_ACCEL
3163 free_irq_cpu_rmap(info->rmap);
3164 info->rmap = NULL;
3165#endif
2a2336f8
YP		 3166}
3167
b12d93d6
YP		 3168static int mlx4_init_steering(struct mlx4_dev *dev)
3169{
3170 struct mlx4_priv *priv = mlx4_priv(dev);
3171 int num_entries = dev->caps.num_ports;
3172 int i, j;
3173
6396bb22
KC		 3174 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer),
3175 GFP_KERNEL);
b12d93d6
YP		 3176 if (!priv->steer)
3177 return -ENOMEM;
3178
45b51365 3179 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 3180 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3181 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3182 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3183 }
b12d93d6
YP		 3184 return 0;
3185}
3186
3187static void mlx4_clear_steering(struct mlx4_dev *dev)
3188{
3189 struct mlx4_priv *priv = mlx4_priv(dev);
3190 struct mlx4_steer_index *entry, *tmp_entry;
3191 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3192 int num_entries = dev->caps.num_ports;
3193 int i, j;
3194
3195 for (i = 0; i < num_entries; i++) {
3196 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3197 list_for_each_entry_safe(pqp, tmp_pqp,
3198 &priv->steer[i].promisc_qps[j],
3199 list) {
3200 list_del(&pqp->list);
3201 kfree(pqp);
3202 }
3203 list_for_each_entry_safe(entry, tmp_entry,
3204 &priv->steer[i].steer_entries[j],
3205 list) {
3206 list_del(&entry->list);
3207 list_for_each_entry_safe(pqp, tmp_pqp,
3208 &entry->duplicates,
3209 list) {
3210 list_del(&pqp->list);
3211 kfree(pqp);
3212 }
3213 kfree(entry);
3214 }
3215 }
3216 }
3217 kfree(priv->steer);
3218}
3219
ab9c17a0
JM		 3220static int extended_func_num(struct pci_dev *pdev)
3221{
3222 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3223}
3224
3225#define MLX4_OWNER_BASE 0x8069c
3226#define MLX4_OWNER_SIZE 4
3227
3228static int mlx4_get_ownership(struct mlx4_dev *dev)
3229{
3230 void __iomem *owner;
3231 u32 ret;
3232
872bf2fb 3233 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3234 return -EIO;
3235
872bf2fb
YH		 3236 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3237 MLX4_OWNER_BASE,
ab9c17a0
JM		 3238 MLX4_OWNER_SIZE);
3239 if (!owner) {
3240 mlx4_err(dev, "Failed to obtain ownership bit\n");
3241 return -ENOMEM;
3242 }
3243
3244 ret = readl(owner);
3245 iounmap(owner);
3246 return (int) !!ret;
3247}
3248
3249static void mlx4_free_ownership(struct mlx4_dev *dev)
3250{
3251 void __iomem *owner;
3252
872bf2fb 3253 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3254 return;
3255
872bf2fb
YH		 3256 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3257 MLX4_OWNER_BASE,
ab9c17a0
JM		 3258 MLX4_OWNER_SIZE);
3259 if (!owner) {
3260 mlx4_err(dev, "Failed to obtain ownership bit\n");
3261 return;
3262 }
3263 writel(0, owner);
3264 msleep(1000);
3265 iounmap(owner);
3266}
3267
a0eacca9
MB		 3268#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3269 !!((flags) & MLX4_FLAG_MASTER))
3270
3271static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 3272 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 3273{
3274 u64 dev_flags = dev->flags;
da315679 3275 int err = 0;
0beb44b0
CS		 3276 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3277 MLX4_MAX_NUM_VF);
a0eacca9 3278
55ad3592
YH		 3279 if (reset_flow) {
3280 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3281 GFP_KERNEL);
3282 if (!dev->dev_vfs)
3283 goto free_mem;
3284 return dev_flags;
3285 }
3286
da315679
MB		 3287 atomic_inc(&pf_loading);
3288 if (dev->flags & MLX4_FLAG_SRIOV) {
3289 if (existing_vfs != total_vfs) {
3290 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3291 existing_vfs, total_vfs);
3292 total_vfs = existing_vfs;
3293 }
3294 }
3295
6396bb22 3296 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 3297 if (NULL == dev->dev_vfs) {
3298 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3299 goto disable_sriov;
da315679
MB		 3300 }
3301
3302 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 3303 if (total_vfs > fw_enabled_sriov_vfs) {
3304 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3305 total_vfs, fw_enabled_sriov_vfs);
3306 err = -ENOMEM;
3307 goto disable_sriov;
3308 }
da315679
MB		 3309 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3310 err = pci_enable_sriov(pdev, total_vfs);
3311 }
3312 if (err) {
3313 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3314 err);
3315 goto disable_sriov;
3316 } else {
3317 mlx4_warn(dev, "Running in master mode\n");
3318 dev_flags |= MLX4_FLAG_SRIOV |
3319 MLX4_FLAG_MASTER;
3320 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 3321 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 3322 }
3323 return dev_flags;
3324
3325disable_sriov:
da315679 3326 atomic_dec(&pf_loading);
55ad3592 3327free_mem:
872bf2fb 3328 dev->persist->num_vfs = 0;
a0eacca9 3329 kfree(dev->dev_vfs);
92a59ad0 3330 dev->dev_vfs = NULL;
a0eacca9
MB		 3331 return dev_flags & ~MLX4_FLAG_MASTER;
3332}
3333
de966c59
MB		 3334enum {
3335 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3336};
3337
3338static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3339 int *nvfs)
3340{
3341 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3342 /* Checking for 64 VFs as a limitation of CX2 */
3343 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3344 requested_vfs >= 64) {
3345 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3346 requested_vfs);
3347 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3348 }
3349 return 0;
3350}
3351
4bfd2e6e
DJ		 3352static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3353{
3354 struct pci_dev *pdev = dev->persist->pdev;
3355 int err = 0;
3356
3357 mutex_lock(&dev->persist->pci_status_mutex);
3358 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3359 err = pci_enable_device(pdev);
3360 if (!err)
3361 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3362 }
3363 mutex_unlock(&dev->persist->pci_status_mutex);
3364
3365 return err;
3366}
3367
3368static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3369{
3370 struct pci_dev *pdev = dev->persist->pdev;
3371
3372 mutex_lock(&dev->persist->pci_status_mutex);
3373 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3374 pci_disable_device(pdev);
3375 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3376 }
3377 mutex_unlock(&dev->persist->pci_status_mutex);
3378}
3379
e1c00e10 3380static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3381 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3382 int reset_flow)
225c7b1f 3383{
a8c05514 3384 struct devlink *devlink = priv_to_devlink(priv);
225c7b1f 3385 struct mlx4_dev *dev;
e1c00e10 3386 unsigned sum = 0;
225c7b1f 3387 int err;
2a2336f8 3388 int port;
e1c00e10 3389 int i;
7ae0e400 3390 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3391 int existing_vfs = 0;
225c7b1f 3392
60d7ceea 3393 devl_assert_locked(devlink);
e1c00e10 3394 dev = &priv->dev;
225c7b1f 3395
8c2d2b87
PP		 3396 err = mlx4_adev_init(dev);
3397 if (err)
3398 return err;
3399
73d68002
PP		 3400 ATOMIC_INIT_NOTIFIER_HEAD(&priv->event_nh);
3401
7ff93f8b 3402 mutex_init(&priv->port_mutex);
53f33ae2 3403 mutex_init(&priv->bond_mutex);
7ff93f8b 3404
6296883c
YP		 3405 INIT_LIST_HEAD(&priv->pgdir_list);
3406 mutex_init(&priv->pgdir_mutex);
0c5ddb51 3407 spin_lock_init(&priv->cmd.context_lock);
6296883c 3408
c1b43dca
EC		 3409 INIT_LIST_HEAD(&priv->bf_list);
3410 mutex_init(&priv->bf_mutex);
3411
aca7a3ac 3412 dev->rev_id = pdev->revision;
6e7136ed 3413 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3414
ab9c17a0 3415 /* Detect if this device is a virtual function */
839f1243 3416 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3417 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3418 dev->flags |= MLX4_FLAG_SLAVE;
3419 } else {
3420 /* We reset the device and enable SRIOV only for physical
3421 * devices. Try to claim ownership on the device;
3422 * if already taken, skip -- do not allow multiple PFs */
3423 err = mlx4_get_ownership(dev);
3424 if (err) {
3425 if (err < 0)
8c2d2b87 3426 goto err_adev;
ab9c17a0 3427 else {
1a91de28 3428 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
8c2d2b87
PP		 3429 err = -EINVAL;
3430 goto err_adev;
ab9c17a0
JM		 3431 }
3432 }
aca7a3ac 3433
fe6f700d
YP		 3434 atomic_set(&priv->opreq_count, 0);
3435 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3436
ab9c17a0
JM		 3437 /*
3438 * Now reset the HCA before we touch the PCI capabilities or
3439 * attempt a firmware command, since a boot ROM may have left
3440 * the HCA in an undefined state.
3441 */
3442 err = mlx4_reset(dev);
3443 if (err) {
1a91de28 3444 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3445 goto err_sriov;
ab9c17a0 3446 }
7ae0e400
MB		 3447
3448 if (total_vfs) {
7ae0e400 3449 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3450 existing_vfs = pci_num_vf(pdev);
3451 if (existing_vfs)
3452 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3453 dev->persist->num_vfs = total_vfs;
7ae0e400 3454 }
225c7b1f
RD		 3455 }
3456
f6bc11e4
YH		 3457 /* on load remove any previous indication of internal error,
3458 * device is up.
3459 */
3460 dev->persist->state = MLX4_DEVICE_STATE_UP;
3461
ab9c17a0 3462slave_start:
521130d1
EE		 3463 err = mlx4_cmd_init(dev);
3464 if (err) {
1a91de28 3465 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3466 goto err_sriov;
3467 }
3468
3469 /* In slave functions, the communication channel must be initialized
3470 * before posting commands. Also, init num_slaves before calling
3471 * mlx4_init_hca */
3472 if (mlx4_is_mfunc(dev)) {
7ae0e400 3473 if (mlx4_is_master(dev)) {
ab9c17a0 3474 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3475
3476 } else {
ab9c17a0 3477 dev->num_slaves = 0;
f356fcbe
JM		 3478 err = mlx4_multi_func_init(dev);
3479 if (err) {
1a91de28 3480 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3481 goto err_cmd;
3482 }
3483 }
225c7b1f
RD		 3484 }
3485
a0eacca9
MB		 3486 err = mlx4_init_fw(dev);
3487 if (err) {
3488 mlx4_err(dev, "Failed to init fw, aborting.\n");
3489 goto err_mfunc;
3490 }
3491
7ae0e400 3492 if (mlx4_is_master(dev)) {
da315679 3493 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3494 if (!dev_cap) {
3495 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3496
3497 if (!dev_cap) {
3498 err = -ENOMEM;
3499 goto err_fw;
3500 }
3501
3502 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3503 if (err) {
3504 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3505 goto err_fw;
3506 }
3507
de966c59
MB		 3508 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3509 goto err_fw;
3510
7ae0e400 3511 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3512 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3513 total_vfs,
3514 existing_vfs,
3515 reset_flow);
7ae0e400 3516
ed3d2276 3517 mlx4_close_fw(dev);
7ae0e400
MB		 3518 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3519 dev->flags = dev_flags;
3520 if (!SRIOV_VALID_STATE(dev->flags)) {
3521 mlx4_err(dev, "Invalid SRIOV state\n");
3522 goto err_sriov;
3523 }
3524 err = mlx4_reset(dev);
3525 if (err) {
3526 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3527 goto err_sriov;
3528 }
3529 goto slave_start;
3530 }
3531 } else {
3532 /* Legacy mode FW requires SRIOV to be enabled before
3533 * doing QUERY_DEV_CAP, since max_eq's value is different if
3534 * SRIOV is enabled.
3535 */
3536 memset(dev_cap, 0, sizeof(*dev_cap));
3537 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3538 if (err) {
3539 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3540 goto err_fw;
3541 }
de966c59
MB		 3542
3543 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3544 goto err_fw;
7ae0e400
MB		 3545 }
3546 }
3547
225c7b1f 3548 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3549 if (err) {
3550 if (err == -EACCES) {
3551 /* Not primary Physical function
3552 * Running in slave mode */
ffc39f6d 3553 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3554 /* We're not a PF */
3555 if (dev->flags & MLX4_FLAG_SRIOV) {
3556 if (!existing_vfs)
3557 pci_disable_sriov(pdev);
55ad3592 3558 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3559 atomic_dec(&pf_loading);
3560 dev->flags &= ~MLX4_FLAG_SRIOV;
3561 }
3562 if (!mlx4_is_slave(dev))
3563 mlx4_free_ownership(dev);
ab9c17a0
JM		 3564 dev->flags |= MLX4_FLAG_SLAVE;
3565 dev->flags &= ~MLX4_FLAG_MASTER;
3566 goto slave_start;
3567 } else
a0eacca9 3568 goto err_fw;
ab9c17a0
JM		 3569 }
3570
7ae0e400 3571 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3572 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3573 existing_vfs, reset_flow);
7ae0e400
MB		 3574
3575 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3576 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3577 dev->flags = dev_flags;
3578 err = mlx4_cmd_init(dev);
3579 if (err) {
3580 /* Only VHCR is cleaned up, so could still
3581 * send FW commands
3582 */
3583 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3584 goto err_close;
3585 }
3586 } else {
3587 dev->flags = dev_flags;
3588 }
3589
3590 if (!SRIOV_VALID_STATE(dev->flags)) {
3591 mlx4_err(dev, "Invalid SRIOV state\n");
7e4960b3 3592 err = -EINVAL;
7ae0e400
MB		 3593 goto err_close;
3594 }
3595 }
3596
b912b2f8
EP		 3597 /* check if the device is functioning at its maximum possible speed.
3598 * No return code for this call, just warn the user in case of PCI
3599 * express device capabilities are under-satisfied by the bus.
3600 */
83d3459a 3601 if (!mlx4_is_slave(dev))
190b509c 3602 pcie_print_link_status(dev->persist->pdev);
b912b2f8 3603
ab9c17a0
JM		 3604 /* In master functions, the communication channel must be initialized
3605 * after obtaining its address from fw */
3606 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3607 if (dev->caps.num_ports < 2 &&
3608 num_vfs_argc > 1) {
3609 err = -EINVAL;
3610 mlx4_err(dev,
3611 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3612 dev->caps.num_ports);
ab9c17a0
JM		 3613 goto err_close;
3614 }
872bf2fb 3615 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3616
872bf2fb
YH		 3617 for (i = 0;
3618 i < sizeof(dev->persist->nvfs)/
3619 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3620 unsigned j;
3621
872bf2fb 3622 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3623 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3624 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3625 dev->caps.num_ports;
1ab95d37
MB		 3626 }
3627 }
e1c00e10
MD		 3628
3629 /* In master functions, the communication channel
3630 * must be initialized after obtaining its address from fw
3631 */
3632 err = mlx4_multi_func_init(dev);
3633 if (err) {
3634 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3635 goto err_close;
3636 }
ab9c17a0 3637 }
225c7b1f 3638
b8dd786f
YP		 3639 err = mlx4_alloc_eq_table(dev);
3640 if (err)
ab9c17a0 3641 goto err_master_mfunc;
b8dd786f 3642
c66fa19c 3643 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3644 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3645
08fb1055 3646 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3647 if ((mlx4_is_mfunc(dev)) &&
3648 !(dev->flags & MLX4_FLAG_MSI_X)) {
72b8eaab 3649 err = -EOPNOTSUPP;
1a91de28 3650 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3651 goto err_free_eq;
ab9c17a0
JM		 3652 }
3653
3654 if (!mlx4_is_slave(dev)) {
3655 err = mlx4_init_steering(dev);
3656 if (err)
e1c00e10 3657 goto err_disable_msix;
ab9c17a0 3658 }
b12d93d6 3659
6ed63d84
JM		 3660 mlx4_init_quotas(dev);
3661
225c7b1f 3662 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3663 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3664 !mlx4_is_mfunc(dev)) {
08fb1055 3665 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3666 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3667 pci_disable_msix(pdev);
3668 err = mlx4_setup_hca(dev);
3669 }
3670
225c7b1f 3671 if (err)
b12d93d6 3672 goto err_steer;
225c7b1f 3673
55ad3592
YH		 3674 /* When PF resources are ready arm its comm channel to enable
3675 * getting commands
3676 */
3677 if (mlx4_is_master(dev)) {
3678 err = mlx4_ARM_COMM_CHANNEL(dev);
3679 if (err) {
3680 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3681 err);
3682 goto err_steer;
3683 }
3684 }
5a0d0a61 3685
7ff93f8b
YP		 3686 for (port = 1; port <= dev->caps.num_ports; port++) {
3687 err = mlx4_init_port_info(dev, port);
3688 if (err)
3689 goto err_port;
3690 }
2a2336f8 3691
53f33ae2
MS		 3692 priv->v2p.port1 = 1;
3693 priv->v2p.port2 = 2;
3694
225c7b1f
RD		 3695 err = mlx4_register_device(dev);
3696 if (err)
7ff93f8b 3697 goto err_port;
225c7b1f 3698
27bf91d6
YP		 3699 mlx4_sense_init(dev);
3700 mlx4_start_sense(dev);
3701
befdf897 3702 priv->removed = 0;
225c7b1f 3703
55ad3592 3704 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3705 atomic_dec(&pf_loading);
3706
da315679 3707 kfree(dev_cap);
225c7b1f
RD		 3708 return 0;
3709
7ff93f8b 3710err_port:
b4f77264 3711 for (--port; port >= 1; --port)
7ff93f8b
YP		 3712 mlx4_cleanup_port_info(&priv->port[port]);
3713
6de5f7f6 3714 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3715 if (!mlx4_is_slave(dev))
3716 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3717 mlx4_cleanup_qp_table(dev);
3718 mlx4_cleanup_srq_table(dev);
3719 mlx4_cleanup_cq_table(dev);
3720 mlx4_cmd_use_polling(dev);
3721 mlx4_cleanup_eq_table(dev);
fe6f700d 3722 mlx4_cleanup_mcg_table(dev);
225c7b1f 3723 mlx4_cleanup_mr_table(dev);
012a8ff5 3724 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3725 mlx4_cleanup_pd_table(dev);
3726 mlx4_cleanup_uar_table(dev);
3727
b12d93d6 3728err_steer:
ab9c17a0
JM		 3729 if (!mlx4_is_slave(dev))
3730 mlx4_clear_steering(dev);
b12d93d6 3731
e1c00e10
MD		 3732err_disable_msix:
3733 if (dev->flags & MLX4_FLAG_MSI_X)
3734 pci_disable_msix(pdev);
3735
b8dd786f
YP		 3736err_free_eq:
3737 mlx4_free_eq_table(dev);
3738
ab9c17a0 3739err_master_mfunc:
772103e6
JM		 3740 if (mlx4_is_master(dev)) {
3741 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3742 mlx4_multi_func_cleanup(dev);
772103e6 3743 }
ab9c17a0 3744
c73c8b1e
EBE		 3745 if (mlx4_is_slave(dev))
3746 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 3747
225c7b1f
RD		 3748err_close:
3749 mlx4_close_hca(dev);
3750
a0eacca9
MB		 3751err_fw:
3752 mlx4_close_fw(dev);
3753
ab9c17a0
JM		 3754err_mfunc:
3755 if (mlx4_is_slave(dev))
3756 mlx4_multi_func_cleanup(dev);
3757
225c7b1f 3758err_cmd:
ffc39f6d 3759 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3760
ab9c17a0 3761err_sriov:
55ad3592 3762 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3763 pci_disable_sriov(pdev);
55ad3592
YH		 3764 dev->flags &= ~MLX4_FLAG_SRIOV;
3765 }
ab9c17a0 3766
55ad3592 3767 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3768 atomic_dec(&pf_loading);
3769
1ab95d37
MB		 3770 kfree(priv->dev.dev_vfs);
3771
e1c00e10
MD		 3772 if (!mlx4_is_slave(dev))
3773 mlx4_free_ownership(dev);
3774
7ae0e400 3775 kfree(dev_cap);
8c2d2b87
PP		 3776
3777err_adev:
3778 mlx4_adev_cleanup(dev);
e1c00e10
MD		 3779 return err;
3780}
3781
3782static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3783 struct mlx4_priv *priv)
3784{
3785 int err;
3786 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3787 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3788 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3789 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3790 unsigned total_vfs = 0;
3791 unsigned int i;
3792
3793 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3794
4bfd2e6e 3795 err = mlx4_pci_enable_device(&priv->dev);
e1c00e10
MD		 3796 if (err) {
3797 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3798 return err;
3799 }
3800
3801 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3802 * per port, we must limit the number of VFs to 63 (since their are
3803 * 128 MACs)
3804 */
691223ec 3805 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
e1c00e10
MD		 3806 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3807 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3808 if (nvfs[i] < 0) {
3809 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3810 err = -EINVAL;
3811 goto err_disable_pdev;
3812 }
3813 }
691223ec 3814 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
e1c00e10
MD		 3815 i++) {
3816 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3817 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3818 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3819 err = -EINVAL;
3820 goto err_disable_pdev;
3821 }
3822 }
0beb44b0 3823 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3824 dev_err(&pdev->dev,
0beb44b0
CS		 3825 "Requested more VF's (%d) than allowed by hw (%d)\n",
3826 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3827 err = -EINVAL;
3828 goto err_disable_pdev;
3829 }
3830
3831 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3832 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3833 dev_err(&pdev->dev,
0beb44b0 3834 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3835 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3836 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3837 err = -EINVAL;
3838 goto err_disable_pdev;
3839 }
3840 }
3841
3842 /* Check for BARs. */
3843 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3844 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3845 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3846 pci_dev_data, pci_resource_flags(pdev, 0));
3847 err = -ENODEV;
3848 goto err_disable_pdev;
3849 }
3850 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3851 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3852 err = -ENODEV;
3853 goto err_disable_pdev;
3854 }
3855
3856 err = pci_request_regions(pdev, DRV_NAME);
3857 if (err) {
3858 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3859 goto err_disable_pdev;
3860 }
3861
3862 pci_set_master(pdev);
3863
eb9c5c0d 3864 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
e1c00e10
MD		 3865 if (err) {
3866 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
eb9c5c0d 3867 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
e1c00e10
MD		 3868 if (err) {
3869 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3870 goto err_release_regions;
3871 }
3872 }
e1c00e10
MD		 3873
3874 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3875 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3876 /* Detect if this device is a virtual function */
3877 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3878 /* When acting as pf, we normally skip vfs unless explicitly
3879 * requested to probe them.
3880 */
3881 if (total_vfs) {
3882 unsigned vfs_offset = 0;
3883
691223ec 3884 for (i = 0; i < ARRAY_SIZE(nvfs) &&
e1c00e10
MD		 3885 vfs_offset + nvfs[i] < extended_func_num(pdev);
3886 vfs_offset += nvfs[i], i++)
3887 ;
691223ec 3888 if (i == ARRAY_SIZE(nvfs)) {
e1c00e10
MD		 3889 err = -ENODEV;
3890 goto err_release_regions;
3891 }
3892 if ((extended_func_num(pdev) - vfs_offset)
3893 > prb_vf[i]) {
3894 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3895 extended_func_num(pdev));
3896 err = -ENODEV;
3897 goto err_release_regions;
3898 }
3899 }
3900 }
3901
bedc989b 3902 err = mlx4_crdump_init(&priv->dev);
e1c00e10
MD		 3903 if (err)
3904 goto err_release_regions;
ad9a0bf0 3905
bedc989b
AV		 3906 err = mlx4_catas_init(&priv->dev);
3907 if (err)
3908 goto err_crdump;
3909
55ad3592 3910 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3911 if (err)
3912 goto err_catas;
3913
e1c00e10 3914 return 0;
225c7b1f 3915
ad9a0bf0
YH		 3916err_catas:
3917 mlx4_catas_end(&priv->dev);
3918
bedc989b
AV		 3919err_crdump:
3920 mlx4_crdump_end(&priv->dev);
3921
a01df0fe
RD		 3922err_release_regions:
3923 pci_release_regions(pdev);
225c7b1f
RD		 3924
3925err_disable_pdev:
4bfd2e6e 3926 mlx4_pci_disable_device(&priv->dev);
225c7b1f
RD		 3927 return err;
3928}
3929
dfb3c082
MS		 3930static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink)
3931{
3c641ba4
AV		 3932 struct mlx4_priv *priv = devlink_priv(devlink);
3933 struct mlx4_dev *dev = &priv->dev;
3934 struct mlx4_fw_crdump *crdump = &dev->persist->crdump;
dfb3c082
MS		 3935 union devlink_param_value saved_value;
3936 int err;
3937
075935f0
JP		 3938 err = devl_param_driverinit_value_get(devlink,
3939 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET,
3940 &saved_value);
dfb3c082
MS		 3941 if (!err && mlx4_internal_err_reset != saved_value.vbool) {
3942 mlx4_internal_err_reset = saved_value.vbool;
3943 /* Notify on value changed on runtime configuration mode */
075935f0
JP		 3944 devl_param_value_changed(devlink,
3945 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET);
dfb3c082 3946 }
075935f0
JP		 3947 err = devl_param_driverinit_value_get(devlink,
3948 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
3949 &saved_value);
dfb3c082
MS		 3950 if (!err)
3951 log_num_mac = order_base_2(saved_value.vu32);
075935f0
JP		 3952 err = devl_param_driverinit_value_get(devlink,
3953 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
3954 &saved_value);
dfb3c082
MS		 3955 if (!err)
3956 enable_64b_cqe_eqe = saved_value.vbool;
075935f0
JP		 3957 err = devl_param_driverinit_value_get(devlink,
3958 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
3959 &saved_value);
dfb3c082
MS		 3960 if (!err)
3961 enable_4k_uar = saved_value.vbool;
075935f0
JP		 3962 err = devl_param_driverinit_value_get(devlink,
3963 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT,
3964 &saved_value);
3c641ba4
AV		 3965 if (!err && crdump->snapshot_enable != saved_value.vbool) {
3966 crdump->snapshot_enable = saved_value.vbool;
075935f0
JP		 3967 devl_param_value_changed(devlink,
3968 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT);
3c641ba4 3969 }
dfb3c082
MS		 3970}
3971
35c7ff34
JP		 3972static void mlx4_restart_one_down(struct pci_dev *pdev);
3973static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload,
3974 struct devlink *devlink);
3975
070c63f2 3976static int mlx4_devlink_reload_down(struct devlink *devlink, bool netns_change,
ccdf0721 3977 enum devlink_reload_action action,
dc64cc7c 3978 enum devlink_reload_limit limit,
97691069 3979 struct netlink_ext_ack *extack)
dfb3c082
MS		 3980{
3981 struct mlx4_priv *priv = devlink_priv(devlink);
3982 struct mlx4_dev *dev = &priv->dev;
3983 struct mlx4_dev_persistent *persist = dev->persist;
dfb3c082 3984
070c63f2
JP		 3985 if (netns_change) {
3986 NL_SET_ERR_MSG_MOD(extack, "Namespace change is not supported");
3987 return -EOPNOTSUPP;
3988 }
dfb3c082
MS		 3989 if (persist->num_vfs)
3990 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n");
35c7ff34 3991 mlx4_restart_one_down(persist->pdev);
97691069
JP		 3992 return 0;
3993}
3994
ccdf0721 3995static int mlx4_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action,
dc64cc7c
MS		 3996 enum devlink_reload_limit limit, u32 *actions_performed,
3997 struct netlink_ext_ack *extack)
97691069
JP		 3998{
3999 struct mlx4_priv *priv = devlink_priv(devlink);
4000 struct mlx4_dev *dev = &priv->dev;
4001 struct mlx4_dev_persistent *persist = dev->persist;
4002 int err;
4003
ccdf0721 4004 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT);
35c7ff34 4005 err = mlx4_restart_one_up(persist->pdev, true, devlink);
dfb3c082 4006 if (err)
35c7ff34
JP		 4007 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n",
4008 err);
dfb3c082
MS		 4009
4010 return err;
4011}
4012
b2facd95 4013static const struct devlink_ops mlx4_devlink_ops = {
ccdf0721 4014 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT),
97691069
JP		 4015 .reload_down = mlx4_devlink_reload_down,
4016 .reload_up = mlx4_devlink_reload_up,
b2facd95
JP		 4017};
4018
1dd06ae8 4019static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 4020{
09d4d087 4021 struct devlink *devlink;
befdf897
WY		 4022 struct mlx4_priv *priv;
4023 struct mlx4_dev *dev;
e1c00e10 4024 int ret;
befdf897 4025
0a645e80 4026 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 4027
919d13a7 4028 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv), &pdev->dev);
09d4d087 4029 if (!devlink)
befdf897 4030 return -ENOMEM;
60d7ceea 4031 devl_lock(devlink);
09d4d087 4032 priv = devlink_priv(devlink);
befdf897
WY		 4033
4034 dev = &priv->dev;
872bf2fb
YH		 4035 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
4036 if (!dev->persist) {
09d4d087
JP		 4037 ret = -ENOMEM;
4038 goto err_devlink_free;
872bf2fb
YH		 4039 }
4040 dev->persist->pdev = pdev;
4041 dev->persist->dev = dev;
4042 pci_set_drvdata(pdev, dev->persist);
befdf897 4043 priv->pci_dev_data = id->driver_data;
f6bc11e4 4044 mutex_init(&dev->persist->device_state_mutex);
c69453e2 4045 mutex_init(&dev->persist->interface_state_mutex);
4bfd2e6e 4046 mutex_init(&dev->persist->pci_status_mutex);
befdf897 4047
075935f0
JP		 4048 ret = devl_params_register(devlink, mlx4_devlink_params,
4049 ARRAY_SIZE(mlx4_devlink_params));
09d4d087
JP		 4050 if (ret)
4051 goto err_devlink_unregister;
bd1b51dc
MS		 4052 mlx4_devlink_set_params_init_values(devlink);
4053 ret = __mlx4_init_one(pdev, id->driver_data, priv);
4054 if (ret)
4055 goto err_params_unregister;
2ba5fbd6 4056
09d4d087 4057 pci_save_state(pdev);
60d7ceea 4058 devl_unlock(devlink);
1e726859 4059 devlink_register(devlink);
09d4d087
JP		 4060 return 0;
4061
bd1b51dc 4062err_params_unregister:
075935f0
JP		 4063 devl_params_unregister(devlink, mlx4_devlink_params,
4064 ARRAY_SIZE(mlx4_devlink_params));
09d4d087 4065err_devlink_unregister:
09d4d087
JP		 4066 kfree(dev->persist);
4067err_devlink_free:
60d7ceea 4068 devl_unlock(devlink);
09d4d087 4069 devlink_free(devlink);
e1c00e10 4070 return ret;
3d73c288
RD		 4071}
4072
dd0eefe3
YH		 4073static void mlx4_clean_dev(struct mlx4_dev *dev)
4074{
4075 struct mlx4_dev_persistent *persist = dev->persist;
4076 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 4077 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 4078
4079 memset(priv, 0, sizeof(*priv));
4080 priv->dev.persist = persist;
55ad3592 4081 priv->dev.flags = flags;
dd0eefe3
YH		 4082}
4083
e1c00e10 4084static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 4085{
872bf2fb
YH		 4086 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4087 struct mlx4_dev *dev = persist->dev;
225c7b1f 4088 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 4089 int pci_dev_data;
a8c05514 4090 struct devlink *devlink;
dd0eefe3 4091 int p, i;
225c7b1f 4092
a8c05514 4093 devlink = priv_to_devlink(priv);
60d7ceea 4094 devl_assert_locked(devlink);
befdf897
WY		 4095 if (priv->removed)
4096 return;
225c7b1f 4097
dd0eefe3
YH		 4098 /* saving current ports type for further use */
4099 for (i = 0; i < dev->caps.num_ports; i++) {
4100 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
4101 dev->persist->curr_port_poss_type[i] = dev->caps.
4102 possible_type[i + 1];
4103 }
4104
befdf897 4105 pci_dev_data = priv->pci_dev_data;
225c7b1f 4106
befdf897
WY		 4107 mlx4_stop_sense(dev);
4108 mlx4_unregister_device(dev);
225c7b1f 4109
befdf897
WY		 4110 for (p = 1; p <= dev->caps.num_ports; p++) {
4111 mlx4_cleanup_port_info(&priv->port[p]);
4112 mlx4_CLOSE_PORT(dev, p);
4113 }
4114
4115 if (mlx4_is_master(dev))
4116 mlx4_free_resource_tracker(dev,
4117 RES_TR_FREE_SLAVES_ONLY);
4118
6de5f7f6 4119 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 4120 if (!mlx4_is_slave(dev))
4121 mlx4_cleanup_counters_table(dev);
befdf897
WY		 4122 mlx4_cleanup_qp_table(dev);
4123 mlx4_cleanup_srq_table(dev);
4124 mlx4_cleanup_cq_table(dev);
4125 mlx4_cmd_use_polling(dev);
4126 mlx4_cleanup_eq_table(dev);
4127 mlx4_cleanup_mcg_table(dev);
4128 mlx4_cleanup_mr_table(dev);
4129 mlx4_cleanup_xrcd_table(dev);
4130 mlx4_cleanup_pd_table(dev);
225c7b1f 4131
befdf897
WY		 4132 if (mlx4_is_master(dev))
4133 mlx4_free_resource_tracker(dev,
4134 RES_TR_FREE_STRUCTS_ONLY);
47605df9 4135
befdf897
WY		 4136 iounmap(priv->kar);
4137 mlx4_uar_free(dev, &priv->driver_uar);
4138 mlx4_cleanup_uar_table(dev);
4139 if (!mlx4_is_slave(dev))
4140 mlx4_clear_steering(dev);
4141 mlx4_free_eq_table(dev);
4142 if (mlx4_is_master(dev))
4143 mlx4_multi_func_cleanup(dev);
4144 mlx4_close_hca(dev);
a0eacca9 4145 mlx4_close_fw(dev);
befdf897
WY		 4146 if (mlx4_is_slave(dev))
4147 mlx4_multi_func_cleanup(dev);
ffc39f6d 4148 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 4149
befdf897
WY		 4150 if (dev->flags & MLX4_FLAG_MSI_X)
4151 pci_disable_msix(pdev);
befdf897
WY		 4152
4153 if (!mlx4_is_slave(dev))
4154 mlx4_free_ownership(dev);
4155
c73c8b1e 4156 mlx4_slave_destroy_special_qp_cap(dev);
befdf897
WY		 4157 kfree(dev->dev_vfs);
4158
8c2d2b87
PP		 4159 mlx4_adev_cleanup(dev);
4160
dd0eefe3 4161 mlx4_clean_dev(dev);
befdf897
WY		 4162 priv->pci_dev_data = pci_dev_data;
4163 priv->removed = 1;
4164}
4165
4166static void mlx4_remove_one(struct pci_dev *pdev)
4167{
872bf2fb
YH		 4168 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4169 struct mlx4_dev *dev = persist->dev;
befdf897 4170 struct mlx4_priv *priv = mlx4_priv(dev);
09d4d087 4171 struct devlink *devlink = priv_to_devlink(priv);
55ad3592 4172 int active_vfs = 0;
befdf897 4173
1e726859 4174 devlink_unregister(devlink);
a0c76345 4175
60d7ceea 4176 devl_lock(devlink);
4cbe4dac
JM		 4177 if (mlx4_is_slave(dev))
4178 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
4179
c69453e2
YH		 4180 mutex_lock(&persist->interface_state_mutex);
4181 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
4182 mutex_unlock(&persist->interface_state_mutex);
4183
55ad3592
YH		 4184 /* Disabling SR-IOV is not allowed while there are active vf's */
4185 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
4186 active_vfs = mlx4_how_many_lives_vf(dev);
4187 if (active_vfs) {
4188 pr_warn("Removing PF when there are active VF's !!\n");
4189 pr_warn("Will not disable SR-IOV.\n");
4190 }
4191 }
4192
c69453e2
YH		 4193 /* device marked to be under deletion running now without the lock
4194 * letting other tasks to be terminated
4195 */
4196 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4197 mlx4_unload_one(pdev);
4198 else
4199 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 4200 mlx4_catas_end(dev);
bedc989b 4201 mlx4_crdump_end(dev);
55ad3592
YH		 4202 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
4203 mlx4_warn(dev, "Disabling SR-IOV\n");
4204 pci_disable_sriov(pdev);
4205 }
4206
e1c00e10 4207 pci_release_regions(pdev);
4bfd2e6e 4208 mlx4_pci_disable_device(dev);
075935f0
JP		 4209 devl_params_unregister(devlink, mlx4_devlink_params,
4210 ARRAY_SIZE(mlx4_devlink_params));
872bf2fb 4211 kfree(dev->persist);
60d7ceea 4212 devl_unlock(devlink);
09d4d087 4213 devlink_free(devlink);
225c7b1f
RD		 4214}
4215
dd0eefe3
YH		 4216static int restore_current_port_types(struct mlx4_dev *dev,
4217 enum mlx4_port_type *types,
4218 enum mlx4_port_type *poss_types)
4219{
4220 struct mlx4_priv *priv = mlx4_priv(dev);
4221 int err, i;
4222
4223 mlx4_stop_sense(dev);
4224
4225 mutex_lock(&priv->port_mutex);
4226 for (i = 0; i < dev->caps.num_ports; i++)
4227 dev->caps.possible_type[i + 1] = poss_types[i];
4228 err = mlx4_change_port_types(dev, types);
4229 mlx4_start_sense(dev);
4230 mutex_unlock(&priv->port_mutex);
4231
4232 return err;
4233}
4234
35c7ff34
JP		 4235static void mlx4_restart_one_down(struct pci_dev *pdev)
4236{
4237 mlx4_unload_one(pdev);
4238}
4239
4240static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload,
4241 struct devlink *devlink)
ee49bd93 4242{
872bf2fb
YH		 4243 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4244 struct mlx4_dev *dev = persist->dev;
839f1243 4245 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 4246 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4247 int pci_dev_data, err, total_vfs;
839f1243
RD		 4248
4249 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 4250 total_vfs = dev->persist->num_vfs;
4251 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10 4252
dfb3c082
MS		 4253 if (reload)
4254 mlx4_devlink_param_load_driverinit_values(devlink);
55ad3592 4255 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 4256 if (err) {
4257 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4258 __func__, pci_name(pdev), err);
4259 return err;
4260 }
4261
dd0eefe3
YH		 4262 err = restore_current_port_types(dev, dev->persist->curr_port_type,
4263 dev->persist->curr_port_poss_type);
4264 if (err)
4265 mlx4_err(dev, "could not restore original port types (%d)\n",
4266 err);
4267
e1c00e10 4268 return err;
ee49bd93
JM		 4269}
4270
35c7ff34
JP		 4271int mlx4_restart_one(struct pci_dev *pdev)
4272{
4273 mlx4_restart_one_down(pdev);
4274 return mlx4_restart_one_up(pdev, false, NULL);
4275}
4276
c19e4b90
BH		 4277#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4278#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4279#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4280
9baa3c34 4281static const struct pci_device_id mlx4_pci_table[] = {
a1b87145 4282#ifdef CONFIG_MLX4_CORE_GEN2
c19e4b90
BH		 4283 /* MT25408 "Hermon" */
4284 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
4285 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
4286 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
4287 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4288 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4289 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
4290 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
4291 /* MT25458 ConnectX EN 10GBASE-T */
4292 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4293 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
4294 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4295 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4296 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4297 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4298 /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4299 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4300 /* MT25400 Family [ConnectX-2] */
4301 MLX_VF(0x1002), /* Virtual Function */
a1b87145 4302#endif /* CONFIG_MLX4_CORE_GEN2 */
ab9c17a0 4303 /* MT27500 Family [ConnectX-3] */
c19e4b90
BH		 4304 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4305 MLX_VF(0x1004), /* Virtual Function */
4306 MLX_GN(0x1005), /* MT27510 Family */
4307 MLX_GN(0x1006), /* MT27511 Family */
4308 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
4309 MLX_GN(0x1008), /* MT27521 Family */
4310 MLX_GN(0x1009), /* MT27530 Family */
4311 MLX_GN(0x100a), /* MT27531 Family */
4312 MLX_GN(0x100b), /* MT27540 Family */
4313 MLX_GN(0x100c), /* MT27541 Family */
4314 MLX_GN(0x100d), /* MT27550 Family */
4315 MLX_GN(0x100e), /* MT27551 Family */
4316 MLX_GN(0x100f), /* MT27560 Family */
4317 MLX_GN(0x1010), /* MT27561 Family */
4318
4319 /*
4320 * See the mellanox_check_broken_intx_masking() quirk when
4321 * adding devices
4322 */
4323
225c7b1f
RD		 4324 { 0, }
4325};
4326
4327MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4328
57dbf29a
KSS		 4329static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4330 pci_channel_state_t state)
4331{
2ba5fbd6 4332 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
60d7ceea
MS		 4333 struct mlx4_dev *dev = persist->dev;
4334 struct devlink *devlink;
2ba5fbd6
YH		 4335
4336 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4337 mlx4_enter_error_state(persist);
57dbf29a 4338
60d7ceea
MS		 4339 devlink = priv_to_devlink(mlx4_priv(dev));
4340 devl_lock(devlink);
2ba5fbd6
YH		 4341 mutex_lock(&persist->interface_state_mutex);
4342 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4343 mlx4_unload_one(pdev);
4344
4345 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4346 devl_unlock(devlink);
2ba5fbd6
YH		 4347 if (state == pci_channel_io_perm_failure)
4348 return PCI_ERS_RESULT_DISCONNECT;
4349
4bfd2e6e 4350 mlx4_pci_disable_device(persist->dev);
2ba5fbd6 4351 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 4352}
4353
4354static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4355{
2ba5fbd6
YH		 4356 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4357 struct mlx4_dev *dev = persist->dev;
c12833ac 4358 int err;
97a5221f 4359
2ba5fbd6 4360 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4bfd2e6e 4361 err = mlx4_pci_enable_device(dev);
c12833ac
DJ		 4362 if (err) {
4363 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
2ba5fbd6
YH		 4364 return PCI_ERS_RESULT_DISCONNECT;
4365 }
4366
4367 pci_set_master(pdev);
4368 pci_restore_state(pdev);
4369 pci_save_state(pdev);
c12833ac
DJ		 4370 return PCI_ERS_RESULT_RECOVERED;
4371}
4372
4373static void mlx4_pci_resume(struct pci_dev *pdev)
4374{
4375 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4376 struct mlx4_dev *dev = persist->dev;
4377 struct mlx4_priv *priv = mlx4_priv(dev);
4378 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
60d7ceea 4379 struct devlink *devlink;
c12833ac
DJ		 4380 int total_vfs;
4381 int err;
2ba5fbd6 4382
c12833ac 4383 mlx4_err(dev, "%s was called\n", __func__);
2ba5fbd6
YH		 4384 total_vfs = dev->persist->num_vfs;
4385 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4386
60d7ceea
MS		 4387 devlink = priv_to_devlink(priv);
4388 devl_lock(devlink);
2ba5fbd6
YH		 4389 mutex_lock(&persist->interface_state_mutex);
4390 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
c12833ac 4391 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 4392 priv, 1);
c12833ac
DJ		 4393 if (err) {
4394 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4395 __func__, err);
2ba5fbd6
YH		 4396 goto end;
4397 }
4398
c12833ac 4399 err = restore_current_port_types(dev, dev->persist->
2ba5fbd6
YH		 4400 curr_port_type, dev->persist->
4401 curr_port_poss_type);
c12833ac
DJ		 4402 if (err)
4403 mlx4_err(dev, "could not restore original port types (%d)\n", err);
2ba5fbd6
YH		 4404 }
4405end:
4406 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4407 devl_unlock(devlink);
57dbf29a
KSS		 4408}
4409
2ba5fbd6
YH		 4410static void mlx4_shutdown(struct pci_dev *pdev)
4411{
4412 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3cab8c65 4413 struct mlx4_dev *dev = persist->dev;
60d7ceea 4414 struct devlink *devlink;
2ba5fbd6
YH		 4415
4416 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
60d7ceea
MS		 4417 devlink = priv_to_devlink(mlx4_priv(dev));
4418 devl_lock(devlink);
2ba5fbd6 4419 mutex_lock(&persist->interface_state_mutex);
b4353708 4420 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
2ba5fbd6
YH		 4421 mlx4_unload_one(pdev);
4422 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4423 devl_unlock(devlink);
3cab8c65 4424 mlx4_pci_disable_device(dev);
2ba5fbd6
YH		 4425}
4426
3646f0e5 4427static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 4428 .error_detected = mlx4_pci_err_detected,
4429 .slot_reset = mlx4_pci_slot_reset,
c12833ac 4430 .resume = mlx4_pci_resume,
57dbf29a
KSS		 4431};
4432
4e1a6911 4433static int __maybe_unused mlx4_suspend(struct device *dev_d)
86a3e5d0 4434{
0e3e206a 4435 struct pci_dev *pdev = to_pci_dev(dev_d);
86a3e5d0
YH		 4436 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4437 struct mlx4_dev *dev = persist->dev;
60d7ceea 4438 struct devlink *devlink;
86a3e5d0
YH		 4439
4440 mlx4_err(dev, "suspend was called\n");
60d7ceea
MS		 4441 devlink = priv_to_devlink(mlx4_priv(dev));
4442 devl_lock(devlink);
86a3e5d0
YH		 4443 mutex_lock(&persist->interface_state_mutex);
4444 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4445 mlx4_unload_one(pdev);
4446 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4447 devl_unlock(devlink);
86a3e5d0
YH		 4448
4449 return 0;
4450}
4451
4e1a6911 4452static int __maybe_unused mlx4_resume(struct device *dev_d)
86a3e5d0 4453{
0e3e206a 4454 struct pci_dev *pdev = to_pci_dev(dev_d);
86a3e5d0
YH		 4455 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4456 struct mlx4_dev *dev = persist->dev;
4457 struct mlx4_priv *priv = mlx4_priv(dev);
4458 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
60d7ceea 4459 struct devlink *devlink;
86a3e5d0
YH		 4460 int total_vfs;
4461 int ret = 0;
4462
4463 mlx4_err(dev, "resume was called\n");
4464 total_vfs = dev->persist->num_vfs;
4465 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4466
60d7ceea
MS		 4467 devlink = priv_to_devlink(priv);
4468 devl_lock(devlink);
86a3e5d0
YH		 4469 mutex_lock(&persist->interface_state_mutex);
4470 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4471 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs,
4472 nvfs, priv, 1);
4473 if (!ret) {
4474 ret = restore_current_port_types(dev,
4475 dev->persist->curr_port_type,
4476 dev->persist->curr_port_poss_type);
4477 if (ret)
4478 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret);
4479 }
4480 }
4481 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4482 devl_unlock(devlink);
86a3e5d0
YH		 4483
4484 return ret;
4485}
4486
0e3e206a
VG		 4487static SIMPLE_DEV_PM_OPS(mlx4_pm_ops, mlx4_suspend, mlx4_resume);
4488
225c7b1f
RD		 4489static struct pci_driver mlx4_driver = {
4490 .name = DRV_NAME,
4491 .id_table = mlx4_pci_table,
4492 .probe = mlx4_init_one,
2ba5fbd6 4493 .shutdown = mlx4_shutdown,
f57e6848 4494 .remove = mlx4_remove_one,
0e3e206a 4495 .driver.pm = &mlx4_pm_ops,
57dbf29a 4496 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 4497};
4498
7ff93f8b
YP		 4499static int __init mlx4_verify_params(void)
4500{
e5732838
TT		 4501 if (msi_x < 0) {
4502 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
4503 return -1;
4504 }
4505
7ff93f8b 4506 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 4507 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 4508 return -1;
4509 }
4510
cb29688a 4511 if (log_num_vlan != 0)
c20862c8
AV		 4512 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4513 MLX4_LOG_NUM_VLANS);
7ff93f8b 4514
ecc8fb11
AV		 4515 if (use_prio != 0)
4516 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 4517
7cc77bf4 4518 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 4519 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4520 log_mtts_per_seg);
ab6bf42e
EC		 4521 return -1;
4522 }
4523
ab9c17a0
JM		 4524 /* Check if module param for ports type has legal combination */
4525 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 4526 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 4527 port_type_array[0] = true;
4528 }
4529
7d077cd3
MB		 4530 if (mlx4_log_num_mgm_entry_size < -7 ||
4531 (mlx4_log_num_mgm_entry_size > 0 &&
4532 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4533 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4534 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 4535 mlx4_log_num_mgm_entry_size,
4536 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4537 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 4538 return -1;
4539 }
4540
7ff93f8b
YP		 4541 return 0;
4542}
4543
225c7b1f
RD		 4544static int __init mlx4_init(void)
4545{
4546 int ret;
4547
8c2d2b87
PP		 4548 WARN_ONCE(strcmp(MLX4_ADEV_NAME, KBUILD_MODNAME),
4549 "mlx4_core name not in sync with kernel module name");
4550
7ff93f8b
YP		 4551 if (mlx4_verify_params())
4552 return -EINVAL;
4553
27bf91d6
YP		 4554
4555 mlx4_wq = create_singlethread_workqueue("mlx4");
4556 if (!mlx4_wq)
4557 return -ENOMEM;
ee49bd93 4558
225c7b1f 4559 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 4560 if (ret < 0)
4561 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4562 return ret < 0 ? ret : 0;
4563}
4564
4565static void __exit mlx4_cleanup(void)
4566{
4567 pci_unregister_driver(&mlx4_driver);
27bf91d6 4568 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4569}
4570
4571module_init(mlx4_init);
4572module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)