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Merge tag 'sched_ext-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/tj...
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
691223ec 37#include <linux/kernel.h>
225c7b1f
RD		 38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
5a0e3ad6 42#include <linux/slab.h>
c1b43dca 43#include <linux/io-mapping.h>
ab9c17a0 44#include <linux/delay.h>
10b1c04e 45#include <linux/etherdevice.h>
09d4d087 46#include <net/devlink.h>
225c7b1f 47
48962f5c 48#include <uapi/rdma/mlx4-abi.h>
225c7b1f
RD		 49#include <linux/mlx4/device.h>
50#include <linux/mlx4/doorbell.h>
51
52#include "mlx4.h"
53#include "fw.h"
54#include "icm.h"
55
56MODULE_AUTHOR("Roland Dreier");
57MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
58MODULE_LICENSE("Dual BSD/GPL");
59MODULE_VERSION(DRV_VERSION);
60
27bf91d6
YP		 61struct workqueue_struct *mlx4_wq;
62
225c7b1f
RD		 63#ifdef CONFIG_MLX4_DEBUG
64
92a59ad0 65int mlx4_debug_level; /* 0 by default */
225c7b1f
RD		 66module_param_named(debug_level, mlx4_debug_level, int, 0644);
67MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
68
69#endif /* CONFIG_MLX4_DEBUG */
70
71#ifdef CONFIG_PCI_MSI
72
08fb1055 73static int msi_x = 1;
225c7b1f 74module_param(msi_x, int, 0444);
e5732838 75MODULE_PARM_DESC(msi_x, "0 - don't use MSI-X, 1 - use MSI-X, >1 - limit number of MSI-X irqs to msi_x");
225c7b1f
RD		 76
77#else /* CONFIG_PCI_MSI */
78
79#define msi_x (0)
80
81#endif /* CONFIG_PCI_MSI */
82
dd41cc3b 83static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 84static int num_vfs_argc;
92a59ad0 85module_param_array(num_vfs, byte, &num_vfs_argc, 0444);
dd41cc3b
MB		 86MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
87 "num_vfs=port1,port2,port1+2");
88
89static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 90static int probe_vfs_argc;
dd41cc3b
MB		 91module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
92MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
93 "probe_vf=port1,port2,port1+2");
ab9c17a0 94
3b68067b 95static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 96module_param_named(log_num_mgm_entry_size,
97 mlx4_log_num_mgm_entry_size, int, 0444);
98MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
99 " of qp per mcg, for example:"
3c439b55 100 " 10 gives 248.range: 7 <="
0ff1fb65 101 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 102 " To activate device managed"
103 " flow steering when available, set to -1");
0ec2c0f8 104
be902ab1 105static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 106module_param(enable_64b_cqe_eqe, bool, 0444);
107MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 108 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 109
76e39ccf
EC		 110static bool enable_4k_uar;
111module_param(enable_4k_uar, bool, 0444);
112MODULE_PARM_DESC(enable_4k_uar,
113 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
114
77507aa2 115#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 116 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
117 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 118
55ad3592
YH		 119#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
120
f57e6848 121static char mlx4_version[] =
225c7b1f 122 DRV_NAME ": Mellanox ConnectX core driver v"
cea2a6d8 123 DRV_VERSION "\n";
225c7b1f 124
3f2c5fb2 125static const struct mlx4_profile default_profile = {
ab9c17a0 126 .num_qp = 1 << 18,
225c7b1f 127 .num_srq = 1 << 16,
c9f2ba5e 128 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 129 .num_cq = 1 << 16,
130 .num_mcg = 1 << 13,
ab9c17a0 131 .num_mpt = 1 << 19,
6cc9c6fb 132 .num_mtt = 1 << 20, /* It is really num mtt segments */
225c7b1f
RD		 133};
134
3f2c5fb2 135static const struct mlx4_profile low_mem_profile = {
2599d858
AV		 136 .num_qp = 1 << 17,
137 .num_srq = 1 << 6,
138 .rdmarc_per_qp = 1 << 4,
139 .num_cq = 1 << 8,
140 .num_mcg = 1 << 8,
141 .num_mpt = 1 << 9,
142 .num_mtt = 1 << 7,
143};
144
ab9c17a0 145static int log_num_mac = 7;
93fc9e1b
YP		 146module_param_named(log_num_mac, log_num_mac, int, 0444);
147MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
148
149static int log_num_vlan;
150module_param_named(log_num_vlan, log_num_vlan, int, 0444);
151MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 152/* Log2 max number of VLANs per ETH port (0-7) */
153#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 154#define MLX4_MIN_LOG_NUM_VLANS 0
155#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 156
eb939922 157static bool use_prio;
93fc9e1b 158module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 159MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 160
7cc77bf4 161int log_mtts_per_seg = ilog2(1);
ab6bf42e 162module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
7cc77bf4
TT		 163MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment "
164 "(0-7) (default: 0)");
ab6bf42e 165
8d0fc7b6 166static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 167static int arr_argc = 2;
168module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 169MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
170 "1 for IB, 2 for Ethernet");
ab9c17a0 171
97989356
AV		 172static atomic_t pf_loading = ATOMIC_INIT(0);
173
bd1b51dc
MS		 174static int mlx4_devlink_ierr_reset_get(struct devlink *devlink, u32 id,
175 struct devlink_param_gset_ctx *ctx)
176{
177 ctx->val.vbool = !!mlx4_internal_err_reset;
178 return 0;
179}
180
181static int mlx4_devlink_ierr_reset_set(struct devlink *devlink, u32 id,
5625ca56
MP		 182 struct devlink_param_gset_ctx *ctx,
183 struct netlink_ext_ack *extack)
bd1b51dc
MS		 184{
185 mlx4_internal_err_reset = ctx->val.vbool;
186 return 0;
187}
188
3c641ba4
AV		 189static int mlx4_devlink_crdump_snapshot_get(struct devlink *devlink, u32 id,
190 struct devlink_param_gset_ctx *ctx)
191{
192 struct mlx4_priv *priv = devlink_priv(devlink);
193 struct mlx4_dev *dev = &priv->dev;
194
195 ctx->val.vbool = dev->persist->crdump.snapshot_enable;
196 return 0;
197}
198
199static int mlx4_devlink_crdump_snapshot_set(struct devlink *devlink, u32 id,
5625ca56
MP		 200 struct devlink_param_gset_ctx *ctx,
201 struct netlink_ext_ack *extack)
3c641ba4
AV		 202{
203 struct mlx4_priv *priv = devlink_priv(devlink);
204 struct mlx4_dev *dev = &priv->dev;
205
206 dev->persist->crdump.snapshot_enable = ctx->val.vbool;
207 return 0;
208}
209
bd1b51dc
MS		 210static int
211mlx4_devlink_max_macs_validate(struct devlink *devlink, u32 id,
212 union devlink_param_value val,
213 struct netlink_ext_ack *extack)
214{
215 u32 value = val.vu32;
216
217 if (value < 1 || value > 128)
218 return -ERANGE;
219
220 if (!is_power_of_2(value)) {
221 NL_SET_ERR_MSG_MOD(extack, "max_macs supported must be power of 2");
222 return -EINVAL;
223 }
224
225 return 0;
226}
227
228enum mlx4_devlink_param_id {
229 MLX4_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX,
230 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
231 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
232};
233
234static const struct devlink_param mlx4_devlink_params[] = {
235 DEVLINK_PARAM_GENERIC(INT_ERR_RESET,
236 BIT(DEVLINK_PARAM_CMODE_RUNTIME) |
237 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
238 mlx4_devlink_ierr_reset_get,
239 mlx4_devlink_ierr_reset_set, NULL),
240 DEVLINK_PARAM_GENERIC(MAX_MACS,
241 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
242 NULL, NULL, mlx4_devlink_max_macs_validate),
3c641ba4
AV		 243 DEVLINK_PARAM_GENERIC(REGION_SNAPSHOT,
244 BIT(DEVLINK_PARAM_CMODE_RUNTIME) |
245 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
246 mlx4_devlink_crdump_snapshot_get,
247 mlx4_devlink_crdump_snapshot_set, NULL),
bd1b51dc
MS		 248 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
249 "enable_64b_cqe_eqe", DEVLINK_PARAM_TYPE_BOOL,
250 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
251 NULL, NULL, NULL),
252 DEVLINK_PARAM_DRIVER(MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
253 "enable_4k_uar", DEVLINK_PARAM_TYPE_BOOL,
254 BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
255 NULL, NULL, NULL),
256};
257
bd1b51dc
MS		 258static void mlx4_devlink_set_params_init_values(struct devlink *devlink)
259{
260 union devlink_param_value value;
261
262 value.vbool = !!mlx4_internal_err_reset;
075935f0
JP		 263 devl_param_driverinit_value_set(devlink,
264 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET,
265 value);
bd1b51dc
MS		 266
267 value.vu32 = 1UL << log_num_mac;
075935f0
JP		 268 devl_param_driverinit_value_set(devlink,
269 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
270 value);
bd1b51dc
MS		 271
272 value.vbool = enable_64b_cqe_eqe;
075935f0
JP		 273 devl_param_driverinit_value_set(devlink,
274 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
275 value);
bd1b51dc
MS		 276
277 value.vbool = enable_4k_uar;
075935f0
JP		 278 devl_param_driverinit_value_set(devlink,
279 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
280 value);
3c641ba4
AV		 281
282 value.vbool = false;
075935f0
JP		 283 devl_param_driverinit_value_set(devlink,
284 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT,
285 value);
bd1b51dc
MS		 286}
287
85743f1e
HN		 288static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
289 struct mlx4_dev_cap *dev_cap)
290{
291 /* The reserved_uars is calculated by system page size unit.
292 * Therefore, adjustment is added when the uar page size is less
293 * than the system page size
294 */
295 dev->caps.reserved_uars =
296 max_t(int,
297 mlx4_get_num_reserved_uar(dev),
298 dev_cap->reserved_uars /
299 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
300}
301
27bf91d6
YP		 302int mlx4_check_port_params(struct mlx4_dev *dev,
303 enum mlx4_port_type *port_type)
7ff93f8b
YP		 304{
305 int i;
306
0b997657
YS		 307 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
308 for (i = 0; i < dev->caps.num_ports - 1; i++) {
309 if (port_type[i] != port_type[i + 1]) {
1a91de28 310 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
95aac2cd 311 return -EOPNOTSUPP;
27bf91d6 312 }
7ff93f8b
YP		 313 }
314 }
7ff93f8b
YP		 315
316 for (i = 0; i < dev->caps.num_ports; i++) {
317 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 318 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
319 i + 1);
95aac2cd 320 return -EOPNOTSUPP;
7ff93f8b
YP		 321 }
322 }
323 return 0;
324}
325
326static void mlx4_set_port_mask(struct mlx4_dev *dev)
327{
328 int i;
329
7ff93f8b 330 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 331 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 332}
f2a3f6a3 333
7ae0e400
MB		 334enum {
335 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
336};
337
338static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
339{
340 int err = 0;
341 struct mlx4_func func;
342
343 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
344 err = mlx4_QUERY_FUNC(dev, &func, 0);
345 if (err) {
346 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
347 return err;
348 }
349 dev_cap->max_eqs = func.max_eq;
350 dev_cap->reserved_eqs = func.rsvd_eqs;
351 dev_cap->reserved_uars = func.rsvd_uars;
352 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
353 }
354 return err;
355}
356
77507aa2
IS		 357static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
358{
359 struct mlx4_caps *dev_cap = &dev->caps;
360
361 /* FW not supporting or cancelled by user */
362 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
363 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
364 return;
365
366 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
367 * When FW has NCSI it may decide not to report 64B CQE/EQEs
368 */
369 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
370 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
371 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
372 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
373 return;
374 }
375
376 if (cache_line_size() == 128 || cache_line_size() == 256) {
377 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
378 /* Changing the real data inside CQE size to 32B */
379 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
380 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
381
382 if (mlx4_is_master(dev))
383 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
384 } else {
0fab541a
OG		 385 if (cache_line_size() != 32 && cache_line_size() != 64)
386 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 387 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
388 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
389 }
390}
391
431df8c7
MB		 392static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
393 struct mlx4_port_cap *port_cap)
394{
395 dev->caps.vl_cap[port] = port_cap->max_vl;
396 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
397 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
398 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
399 /* set gid and pkey table operating lengths by default
400 * to non-sriov values
401 */
402 dev->caps.gid_table_len[port] = port_cap->max_gids;
403 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
404 dev->caps.port_width_cap[port] = port_cap->max_port_width;
405 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
af7d5185 406 dev->caps.max_tc_eth = port_cap->max_tc_eth;
431df8c7
MB		 407 dev->caps.def_mac[port] = port_cap->def_mac;
408 dev->caps.supported_type[port] = port_cap->supported_port_types;
409 dev->caps.suggested_type[port] = port_cap->suggested_type;
410 dev->caps.default_sense[port] = port_cap->default_sense;
411 dev->caps.trans_type[port] = port_cap->trans_type;
412 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
413 dev->caps.wavelength[port] = port_cap->wavelength;
414 dev->caps.trans_code[port] = port_cap->trans_code;
415
416 return 0;
417}
418
419static int mlx4_dev_port(struct mlx4_dev *dev, int port,
420 struct mlx4_port_cap *port_cap)
421{
422 int err = 0;
423
424 err = mlx4_QUERY_PORT(dev, port, port_cap);
425
426 if (err)
427 mlx4_err(dev, "QUERY_PORT command failed.\n");
428
429 return err;
430}
431
78500b8c
MM		 432static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
433{
434 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
435 return;
436
437 if (mlx4_is_mfunc(dev)) {
438 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
439 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
440 return;
441 }
442
443 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
444 mlx4_dbg(dev,
445 "Keep FCS is not supported - Disabling Ignore FCS");
446 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
447 return;
448 }
449}
450
431df8c7 451#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 452static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 453{
454 int err;
5ae2a7a8 455 int i;
225c7b1f
RD		 456
457 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
458 if (err) {
1a91de28 459 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 460 return err;
461 }
c78e25ed 462 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 463
464 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 465 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 466 dev_cap->min_page_sz, PAGE_SIZE);
467 return -ENODEV;
468 }
469 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 470 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 471 dev_cap->num_ports, MLX4_MAX_PORTS);
472 return -ENODEV;
473 }
474
872bf2fb 475 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 476 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 477 dev_cap->uar_size,
872bf2fb
YH		 478 (unsigned long long)
479 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 480 return -ENODEV;
481 }
482
483 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 484 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
485 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
486 dev->caps.num_sys_eqs :
487 MLX4_MAX_EQ_NUM;
5ae2a7a8 488 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 489 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
490 if (err) {
491 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
492 return err;
493 }
5ae2a7a8
RD		 494 }
495
404e5a12 496 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user;
ab9c17a0 497 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 498 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 499 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
500 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
501 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
502 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
503 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
504 dev->caps.max_wqes = dev_cap->max_qp_sz;
505 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 506 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
507 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
508 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
509 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
510 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 511 /*
512 * Subtract 1 from the limit because we need to allocate a
57d0f00d 513 * spare CQE to enable resizing the CQ.
225c7b1f
RD		 514 */
515 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
516 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
517 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 518 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 519 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0 520
225c7b1f 521 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 522 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
523 dev_cap->reserved_xrcds : 0;
524 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
525 dev_cap->max_xrcds : 0;
2b8fb286
MA		 526 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
527
149983af 528 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 529 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
530 dev->caps.flags = dev_cap->flags;
b3416f44 531 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 532 dev->caps.bmme_flags = dev_cap->bmme_flags;
533 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 534 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 535 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 536 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
c994f778
IK		 537 dev->caps.wol_port[1] = dev_cap->wol_port[1];
538 dev->caps.wol_port[2] = dev_cap->wol_port[2];
523f9eb1 539 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs;
225c7b1f 540
85743f1e
HN		 541 /* Save uar page shift */
542 if (!mlx4_is_slave(dev)) {
543 /* Virtual PCI function needs to determine UAR page size from
544 * firmware. Only master PCI function can set the uar page size
545 */
ca3d89a3 546 if (enable_4k_uar || !dev->persist->num_vfs)
76e39ccf
EC		 547 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
548 else
549 dev->uar_page_shift = PAGE_SHIFT;
550
85743f1e
HN		 551 mlx4_set_num_reserved_uars(dev, dev_cap);
552 }
553
77fc29c4
HHZ		 554 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
555 struct mlx4_init_hca_param hca_param;
556
557 memset(&hca_param, 0, sizeof(hca_param));
558 err = mlx4_QUERY_HCA(dev, &hca_param);
559 /* Turn off PHV_EN flag in case phv_check_en is set.
560 * phv_check_en is a HW check that parse the packet and verify
561 * phv bit was reported correctly in the wqe. To allow QinQ
562 * PHV_EN flag should be set and phv_check_en must be cleared
563 * otherwise QinQ packets will be drop by the HW.
564 */
565 if (err || hca_param.phv_check_en)
566 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
567 }
568
ca3e57a5
RD		 569 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
570 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 571 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 572 /* Don't do sense port on multifunction devices (for now at least) */
573 if (mlx4_is_mfunc(dev))
574 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 575
2599d858
AV		 576 if (mlx4_low_memory_profile()) {
577 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
578 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
579 } else {
580 dev->caps.log_num_macs = log_num_mac;
581 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
582 }
93fc9e1b
YP		 583
584 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 585 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
586 if (dev->caps.supported_type[i]) {
587 /* if only ETH is supported - assign ETH */
588 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
589 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 590 /* if only IB is supported, assign IB */
ab9c17a0 591 else if (dev->caps.supported_type[i] ==
105c320f
JM		 592 MLX4_PORT_TYPE_IB)
593 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 594 else {
105c320f
JM		 595 /* if IB and ETH are supported, we set the port
596 * type according to user selection of port type;
597 * if user selected none, take the FW hint */
598 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 599 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
600 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 601 else
105c320f 602 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 603 }
604 }
8d0fc7b6
YP		 605 /*
606 * Link sensing is allowed on the port if 3 conditions are true:
607 * 1. Both protocols are supported on the port.
608 * 2. Different types are supported on the port
609 * 3. FW declared that it supports link sensing
610 */
27bf91d6 611 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 612 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 613 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 614 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 615
8d0fc7b6
YP		 616 /*
617 * If "default_sense" bit is set, we move the port to "AUTO" mode
618 * and perform sense_port FW command to try and set the correct
619 * port type from beginning
620 */
46c46747 621 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 622 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
623 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
624 mlx4_SENSE_PORT(dev, i, &sensed_port);
625 if (sensed_port != MLX4_PORT_TYPE_NONE)
626 dev->caps.port_type[i] = sensed_port;
627 } else {
628 dev->caps.possible_type[i] = dev->caps.port_type[i];
629 }
630
431df8c7
MB		 631 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
632 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 633 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 634 i, 1 << dev->caps.log_num_macs);
635 }
431df8c7
MB		 636 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
637 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 638 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 639 i, 1 << dev->caps.log_num_vlans);
640 }
641 }
642
ac0a72a3
OG		 643 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
644 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
645 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
646 mlx4_warn(dev,
647 "Granular QoS per VF not supported with IB/Eth configuration\n");
648 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
649 }
650
47d8417f 651 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 652
93fc9e1b
YP		 653 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
654 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
655 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
656 (1 << dev->caps.log_num_macs) *
657 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 658 dev->caps.num_ports;
659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 660
661 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
662 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
663 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
664 else
665 dev->caps.dmfs_high_rate_qpn_base =
666 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
667
668 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
669 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
670 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
671 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
672 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
673 } else {
674 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
675 dev->caps.dmfs_high_rate_qpn_base =
676 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
677 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
678 }
679
fc31e256
OG		 680 dev->caps.rl_caps = dev_cap->rl_caps;
681
d57febe1 682 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 683 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 684
685 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
686 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
688 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
689
e2c76824 690 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 691
b3051320 692 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 693 if (dev_cap->flags &
694 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
695 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
696 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
697 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
698 }
77507aa2
IS		 699
700 if (dev_cap->flags2 &
701 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
702 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
703 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
704 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
705 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
706 }
08ff3235
OG		 707 }
708
f97b4b5d 709 if ((dev->caps.flags &
08ff3235
OG		 710 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
711 mlx4_is_master(dev))
712 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
713
ddae0349 714 if (!mlx4_is_slave(dev)) {
77507aa2 715 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 716 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 717 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
718 MLX4_RESERVE_A0_QP;
3742cc65
IS		 719
720 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
721 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
722 mlx4_warn(dev, "Old device ETS support detected\n");
723 mlx4_warn(dev, "Consider upgrading device FW.\n");
724 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
725 }
726
ddae0349
EE		 727 } else {
728 dev->caps.alloc_res_qp_mask = 0;
729 }
77507aa2 730
78500b8c
MM		 731 mlx4_enable_ignore_fcs(dev);
732
225c7b1f
RD		 733 return 0;
734}
b912b2f8 735
ab9c17a0
JM		 736/*The function checks if there are live vf, return the num of them*/
737static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
738{
739 struct mlx4_priv *priv = mlx4_priv(dev);
740 struct mlx4_slave_state *s_state;
741 int i;
742 int ret = 0;
743
744 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
745 s_state = &priv->mfunc.master.slave_state[i];
746 if (s_state->active && s_state->last_cmd !=
747 MLX4_COMM_CMD_RESET) {
748 mlx4_warn(dev, "%s: slave: %d is still active\n",
749 __func__, i);
750 ret++;
751 }
752 }
753 return ret;
754}
755
396f2feb
JM		 756int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
757{
758 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 759
760 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
761 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 762 return -EINVAL;
763
47605df9 764 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 765 /* tunnel qp */
47605df9 766 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 767 else
47605df9 768 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 769 *qkey = qk;
770 return 0;
771}
772EXPORT_SYMBOL(mlx4_get_parav_qkey);
773
54679e14
JM		 774void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
775{
776 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
777
778 if (!mlx4_is_master(dev))
779 return;
780
781 priv->virt2phys_pkey[slave][port - 1][i] = val;
782}
783EXPORT_SYMBOL(mlx4_sync_pkey_table);
784
afa8fd1d
JM		 785void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
786{
787 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
788
789 if (!mlx4_is_master(dev))
790 return;
791
792 priv->slave_node_guids[slave] = guid;
793}
794EXPORT_SYMBOL(mlx4_put_slave_node_guid);
795
796__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
797{
798 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
799
800 if (!mlx4_is_master(dev))
801 return 0;
802
803 return priv->slave_node_guids[slave];
804}
805EXPORT_SYMBOL(mlx4_get_slave_node_guid);
806
e10903b0 807int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 808{
809 struct mlx4_priv *priv = mlx4_priv(dev);
810 struct mlx4_slave_state *s_slave;
811
812 if (!mlx4_is_master(dev))
813 return 0;
814
815 s_slave = &priv->mfunc.master.slave_state[slave];
816 return !!s_slave->active;
817}
818EXPORT_SYMBOL(mlx4_is_slave_active);
819
10b1c04e
JM		 820void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
821 struct _rule_hw *eth_header)
822{
823 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
824 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
825 struct mlx4_net_trans_rule_hw_eth *eth =
826 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
827 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
828 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
829 next_rule->rsvd == 0;
830
831 if (last_rule)
832 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
833 }
834}
835EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
836
7b8157be
JM		 837static void slave_adjust_steering_mode(struct mlx4_dev *dev,
838 struct mlx4_dev_cap *dev_cap,
839 struct mlx4_init_hca_param *hca_param)
840{
841 dev->caps.steering_mode = hca_param->steering_mode;
842 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
843 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
844 dev->caps.fs_log_max_ucast_qp_range_size =
845 dev_cap->fs_log_max_ucast_qp_range_size;
846 } else
847 dev->caps.num_qp_per_mgm =
848 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
849
850 mlx4_dbg(dev, "Steering mode is: %s\n",
851 mlx4_steering_mode_str(dev->caps.steering_mode));
852}
853
c73c8b1e
EBE		 854static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
855{
856 kfree(dev->caps.spec_qps);
857 dev->caps.spec_qps = NULL;
858}
859
860static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
861{
39868926 862 struct mlx4_func_cap *func_cap;
c73c8b1e
EBE		 863 struct mlx4_caps *caps = &dev->caps;
864 int i, err = 0;
865
866 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
867 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
868
869 if (!func_cap || !caps->spec_qps) {
870 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
871 err = -ENOMEM;
872 goto err_mem;
873 }
874
875 for (i = 1; i <= caps->num_ports; ++i) {
876 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
877 if (err) {
878 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
879 i, err);
880 goto err_mem;
881 }
882 caps->spec_qps[i - 1] = func_cap->spec_qps;
883 caps->port_mask[i] = caps->port_type[i];
884 caps->phys_port_id[i] = func_cap->phys_port_id;
885 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
886 &caps->gid_table_len[i],
887 &caps->pkey_table_len[i]);
888 if (err) {
889 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
890 i, err);
891 goto err_mem;
892 }
893 }
894
895err_mem:
896 if (err)
897 mlx4_slave_destroy_special_qp_cap(dev);
898 kfree(func_cap);
899 return err;
900}
901
ab9c17a0
JM		 902static int mlx4_slave_cap(struct mlx4_dev *dev)
903{
904 int err;
905 u32 page_size;
39868926
RJ		 906 struct mlx4_dev_cap *dev_cap;
907 struct mlx4_func_cap *func_cap;
908 struct mlx4_init_hca_param *hca_param;
c73c8b1e
EBE		 909
910 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
911 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
912 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
913 if (!hca_param || !func_cap || !dev_cap) {
914 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
915 err = -ENOMEM;
916 goto free_mem;
917 }
ab9c17a0 918
c73c8b1e 919 err = mlx4_QUERY_HCA(dev, hca_param);
ab9c17a0 920 if (err) {
1a91de28 921 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
c73c8b1e 922 goto free_mem;
ab9c17a0
JM		 923 }
924
483e0132
EP		 925 /* fail if the hca has an unknown global capability
926 * at this time global_caps should be always zeroed
927 */
c73c8b1e 928 if (hca_param->global_caps) {
ab9c17a0 929 mlx4_err(dev, "Unknown hca global capabilities\n");
c73c8b1e
EBE		 930 err = -EINVAL;
931 goto free_mem;
ab9c17a0
JM		 932 }
933
c73c8b1e 934 dev->caps.hca_core_clock = hca_param->hca_core_clock;
ddd8a6c1 935
c73c8b1e
EBE		 936 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
937 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 938 if (err) {
1a91de28 939 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
c73c8b1e 940 goto free_mem;
ab9c17a0
JM		 941 }
942
b91cb3eb
JM		 943 err = mlx4_QUERY_FW(dev);
944 if (err)
1a91de28 945 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 946
ab9c17a0
JM		 947 page_size = ~dev->caps.page_size_cap + 1;
948 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
949 if (page_size > PAGE_SIZE) {
1a91de28 950 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0 951 page_size, PAGE_SIZE);
c73c8b1e
EBE		 952 err = -ENODEV;
953 goto free_mem;
ab9c17a0
JM		 954 }
955
85743f1e 956 /* Set uar_page_shift for VF */
c73c8b1e 957 dev->uar_page_shift = hca_param->uar_page_sz + 12;
ab9c17a0 958
85743f1e
HN		 959 /* Make sure the master uar page size is valid */
960 if (dev->uar_page_shift > PAGE_SHIFT) {
961 mlx4_err(dev,
962 "Invalid configuration: uar page size is larger than system page size\n");
c73c8b1e
EBE		 963 err = -ENODEV;
964 goto free_mem;
ab9c17a0
JM		 965 }
966
85743f1e 967 /* Set reserved_uars based on the uar_page_shift */
c73c8b1e 968 mlx4_set_num_reserved_uars(dev, dev_cap);
85743f1e
HN		 969
970 /* Although uar page size in FW differs from system page size,
971 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
972 * still works with assumption that uar page size == system page size
973 */
974 dev->caps.uar_page_size = PAGE_SIZE;
975
c73c8b1e 976 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
ab9c17a0 977 if (err) {
1a91de28
JP		 978 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
979 err);
c73c8b1e 980 goto free_mem;
ab9c17a0
JM		 981 }
982
c73c8b1e 983 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
ab9c17a0 984 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3 985 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
c73c8b1e
EBE		 986 func_cap->pf_context_behaviour,
987 PF_CONTEXT_BEHAVIOUR_MASK);
988 err = -EINVAL;
989 goto free_mem;
990 }
991
992 dev->caps.num_ports = func_cap->num_ports;
993 dev->quotas.qp = func_cap->qp_quota;
994 dev->quotas.srq = func_cap->srq_quota;
995 dev->quotas.cq = func_cap->cq_quota;
996 dev->quotas.mpt = func_cap->mpt_quota;
997 dev->quotas.mtt = func_cap->mtt_quota;
998 dev->caps.num_qps = 1 << hca_param->log_num_qps;
999 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
1000 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
1001 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
1002 dev->caps.num_eqs = func_cap->max_eq;
1003 dev->caps.reserved_eqs = func_cap->reserved_eq;
1004 dev->caps.reserved_lkey = func_cap->reserved_lkey;
ab9c17a0
JM		 1005 dev->caps.num_pds = MLX4_NUM_PDS;
1006 dev->caps.num_mgms = 0;
1007 dev->caps.num_amgms = 0;
1008
ab9c17a0 1009 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 1010 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
1011 dev->caps.num_ports, MLX4_MAX_PORTS);
542deb88
CIK		 1012 err = -ENODEV;
1013 goto free_mem;
ab9c17a0
JM		 1014 }
1015
2b3ddf27
JM		 1016 mlx4_replace_zero_macs(dev);
1017
c73c8b1e
EBE		 1018 err = mlx4_slave_special_qp_cap(dev);
1019 if (err) {
1020 mlx4_err(dev, "Set special QP caps failed. aborting\n");
1021 goto free_mem;
6634961c 1022 }
6230bb23 1023
ab9c17a0
JM		 1024 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1025 dev->caps.reserved_uars) >
872bf2fb
YH		 1026 pci_resource_len(dev->persist->pdev,
1027 2)) {
1a91de28 1028 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 1029 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 1030 (unsigned long long)
1031 pci_resource_len(dev->persist->pdev, 2));
d49c2197 1032 err = -ENOMEM;
47605df9 1033 goto err_mem;
ab9c17a0
JM		 1034 }
1035
c73c8b1e 1036 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
08ff3235
OG		 1037 dev->caps.eqe_size = 64;
1038 dev->caps.eqe_factor = 1;
1039 } else {
1040 dev->caps.eqe_size = 32;
1041 dev->caps.eqe_factor = 0;
1042 }
1043
c73c8b1e 1044 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
08ff3235 1045 dev->caps.cqe_size = 64;
77507aa2 1046 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1047 } else {
1048 dev->caps.cqe_size = 32;
1049 }
1050
c73c8b1e
EBE		 1051 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
1052 dev->caps.eqe_size = hca_param->eqe_size;
77507aa2
IS		 1053 dev->caps.eqe_factor = 0;
1054 }
1055
c73c8b1e
EBE		 1056 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
1057 dev->caps.cqe_size = hca_param->cqe_size;
77507aa2
IS		 1058 /* User still need to know when CQE > 32B */
1059 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1060 }
1061
f9bd2d7f 1062 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1063 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 1064
be599603
MS		 1065 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1066 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
1067
c73c8b1e 1068 slave_adjust_steering_mode(dev, dev_cap, hca_param);
802f42a8 1069 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
c73c8b1e 1070 hca_param->rss_ip_frags ? "on" : "off");
7b8157be 1071
c73c8b1e 1072 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
ddae0349
EE		 1073 dev->caps.bf_reg_size)
1074 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1075
c73c8b1e 1076 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
d57febe1
MB		 1077 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1078
47605df9 1079err_mem:
c73c8b1e
EBE		 1080 if (err)
1081 mlx4_slave_destroy_special_qp_cap(dev);
1082free_mem:
1083 kfree(hca_param);
1084 kfree(func_cap);
1085 kfree(dev_cap);
47605df9 1086 return err;
ab9c17a0 1087}
225c7b1f 1088
7ff93f8b
YP		 1089/*
1090 * Change the port configuration of the device.
1091 * Every user of this function must hold the port mutex.
1092 */
27bf91d6
YP		 1093int mlx4_change_port_types(struct mlx4_dev *dev,
1094 enum mlx4_port_type *port_types)
7ff93f8b
YP		 1095{
1096 int err = 0;
1097 int change = 0;
1098 int port;
1099
1100 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1101 /* Change the port type only if the new type is different
1102 * from the current, and not set to Auto */
3d8f9308 1103 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1104 change = 1;
7ff93f8b
YP		 1105 }
1106 if (change) {
1107 mlx4_unregister_device(dev);
1108 for (port = 1; port <= dev->caps.num_ports; port++) {
1109 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1110 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1111 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1112 if (err) {
1a91de28
JP		 1113 mlx4_err(dev, "Failed to set port %d, aborting\n",
1114 port);
7ff93f8b
YP		 1115 goto out;
1116 }
1117 }
1118 mlx4_set_port_mask(dev);
1119 err = mlx4_register_device(dev);
b046ffe5
EP		 1120 if (err) {
1121 mlx4_err(dev, "Failed to register device\n");
1122 goto out;
1123 }
7ff93f8b
YP		 1124 }
1125
1126out:
1127 return err;
1128}
1129
1130static ssize_t show_port_type(struct device *dev,
1131 struct device_attribute *attr,
1132 char *buf)
1133{
1134 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1135 port_attr);
1136 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1137 char type[8];
1138
1139 sprintf(type, "%s",
1140 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1141 "ib" : "eth");
1142 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1143 sprintf(buf, "auto (%s)\n", type);
1144 else
1145 sprintf(buf, "%s\n", type);
7ff93f8b 1146
27bf91d6 1147 return strlen(buf);
7ff93f8b
YP		 1148}
1149
b2facd95
JP		 1150static int __set_port_type(struct mlx4_port_info *info,
1151 enum mlx4_port_type port_type)
7ff93f8b 1152{
7ff93f8b
YP		 1153 struct mlx4_dev *mdev = info->dev;
1154 struct mlx4_priv *priv = mlx4_priv(mdev);
1155 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1156 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 1157 int i;
1158 int err = 0;
1159
33a1f8b1
MG		 1160 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1161 mlx4_err(mdev,
1162 "Requested port type for port %d is not supported on this HCA\n",
1163 info->port);
95aac2cd 1164 return -EOPNOTSUPP;
33a1f8b1
MG		 1165 }
1166
27bf91d6 1167 mlx4_stop_sense(mdev);
7ff93f8b 1168 mutex_lock(&priv->port_mutex);
b2facd95
JP		 1169 info->tmp_type = port_type;
1170
27bf91d6
YP		 1171 /* Possible type is always the one that was delivered */
1172 mdev->caps.possible_type[info->port] = info->tmp_type;
1173
1174 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1175 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1176 mdev->caps.possible_type[i+1];
1177 if (types[i] == MLX4_PORT_TYPE_AUTO)
1178 types[i] = mdev->caps.port_type[i+1];
1179 }
7ff93f8b 1180
58a60168
YP		 1181 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1182 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1183 for (i = 1; i <= mdev->caps.num_ports; i++) {
1184 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1185 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
95aac2cd 1186 err = -EOPNOTSUPP;
27bf91d6
YP		 1187 }
1188 }
1189 }
1190 if (err) {
1a91de28 1191 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1192 goto out;
1193 }
1194
1195 mlx4_do_sense_ports(mdev, new_types, types);
1196
1197 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1198 if (err)
1199 goto out;
1200
27bf91d6
YP		 1201 /* We are about to apply the changes after the configuration
1202 * was verified, no need to remember the temporary types
1203 * any more */
1204 for (i = 0; i < mdev->caps.num_ports; i++)
1205 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1206
27bf91d6 1207 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1208
1209out:
27bf91d6 1210 mlx4_start_sense(mdev);
7ff93f8b 1211 mutex_unlock(&priv->port_mutex);
95aac2cd 1212
b2facd95
JP		 1213 return err;
1214}
1215
1216static ssize_t set_port_type(struct device *dev,
1217 struct device_attribute *attr,
1218 const char *buf, size_t count)
1219{
1220 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1221 port_attr);
1222 struct mlx4_dev *mdev = info->dev;
1223 enum mlx4_port_type port_type;
1224 static DEFINE_MUTEX(set_port_type_mutex);
1225 int err;
1226
1227 mutex_lock(&set_port_type_mutex);
1228
1229 if (!strcmp(buf, "ib\n")) {
1230 port_type = MLX4_PORT_TYPE_IB;
1231 } else if (!strcmp(buf, "eth\n")) {
1232 port_type = MLX4_PORT_TYPE_ETH;
1233 } else if (!strcmp(buf, "auto\n")) {
1234 port_type = MLX4_PORT_TYPE_AUTO;
1235 } else {
1236 mlx4_err(mdev, "%s is not supported port type\n", buf);
1237 err = -EINVAL;
1238 goto err_out;
1239 }
1240
1241 err = __set_port_type(info, port_type);
1242
0a984556
AV		 1243err_out:
1244 mutex_unlock(&set_port_type_mutex);
1245
7ff93f8b
YP		 1246 return err ? err : count;
1247}
1248
096335b3
OG		 1249enum ibta_mtu {
1250 IB_MTU_256 = 1,
1251 IB_MTU_512 = 2,
1252 IB_MTU_1024 = 3,
1253 IB_MTU_2048 = 4,
1254 IB_MTU_4096 = 5
1255};
1256
1257static inline int int_to_ibta_mtu(int mtu)
1258{
1259 switch (mtu) {
1260 case 256: return IB_MTU_256;
1261 case 512: return IB_MTU_512;
1262 case 1024: return IB_MTU_1024;
1263 case 2048: return IB_MTU_2048;
1264 case 4096: return IB_MTU_4096;
1265 default: return -1;
1266 }
1267}
1268
1269static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1270{
1271 switch (mtu) {
1272 case IB_MTU_256: return 256;
1273 case IB_MTU_512: return 512;
1274 case IB_MTU_1024: return 1024;
1275 case IB_MTU_2048: return 2048;
1276 case IB_MTU_4096: return 4096;
1277 default: return -1;
1278 }
1279}
1280
1281static ssize_t show_port_ib_mtu(struct device *dev,
1282 struct device_attribute *attr,
1283 char *buf)
1284{
1285 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1286 port_mtu_attr);
1287 struct mlx4_dev *mdev = info->dev;
1288
1289 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1290 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1291
1292 sprintf(buf, "%d\n",
1293 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1294 return strlen(buf);
1295}
1296
1297static ssize_t set_port_ib_mtu(struct device *dev,
1298 struct device_attribute *attr,
1299 const char *buf, size_t count)
1300{
1301 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1302 port_mtu_attr);
1303 struct mlx4_dev *mdev = info->dev;
1304 struct mlx4_priv *priv = mlx4_priv(mdev);
1305 int err, port, mtu, ibta_mtu = -1;
1306
1307 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1308 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1309 return -EINVAL;
1310 }
1311
618fad95
DB		 1312 err = kstrtoint(buf, 0, &mtu);
1313 if (!err)
096335b3
OG		 1314 ibta_mtu = int_to_ibta_mtu(mtu);
1315
618fad95 1316 if (err || ibta_mtu < 0) {
096335b3
OG		 1317 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1318 return -EINVAL;
1319 }
1320
1321 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1322
1323 mlx4_stop_sense(mdev);
1324 mutex_lock(&priv->port_mutex);
1325 mlx4_unregister_device(mdev);
1326 for (port = 1; port <= mdev->caps.num_ports; port++) {
1327 mlx4_CLOSE_PORT(mdev, port);
6634961c 1328 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1329 if (err) {
1a91de28
JP		 1330 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1331 port);
096335b3
OG		 1332 goto err_set_port;
1333 }
1334 }
1335 err = mlx4_register_device(mdev);
1336err_set_port:
1337 mutex_unlock(&priv->port_mutex);
1338 mlx4_start_sense(mdev);
1339 return err ? err : count;
1340}
1341
e57968a1
MS		 1342/* bond for multi-function device */
1343#define MAX_MF_BOND_ALLOWED_SLAVES 63
1344static int mlx4_mf_bond(struct mlx4_dev *dev)
1345{
1346 int err = 0;
00ada910 1347 int nvfs;
e57968a1
MS		 1348 struct mlx4_slaves_pport slaves_port1;
1349 struct mlx4_slaves_pport slaves_port2;
e57968a1
MS		 1350
1351 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1352 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
e57968a1
MS		 1353
1354 /* only single port vfs are allowed */
623a7138
CJ		 1355 if (bitmap_weight_and(slaves_port1.slaves, slaves_port2.slaves,
1356 dev->persist->num_vfs + 1) > 1) {
e57968a1
MS		 1357 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1358 return -EINVAL;
1359 }
1360
00ada910
MS		 1361 /* number of virtual functions is number of total functions minus one
1362 * physical function for each port.
1363 */
1364 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1365 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1366
e57968a1 1367 /* limit on maximum allowed VFs */
00ada910
MS		 1368 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1369 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1370 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
e57968a1 1371 return -EINVAL;
00ada910 1372 }
e57968a1
MS		 1373
1374 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1375 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1376 return -EINVAL;
1377 }
1378
1379 err = mlx4_bond_mac_table(dev);
1380 if (err)
1381 return err;
1382 err = mlx4_bond_vlan_table(dev);
1383 if (err)
1384 goto err1;
1385 err = mlx4_bond_fs_rules(dev);
1386 if (err)
1387 goto err2;
1388
1389 return 0;
1390err2:
1391 (void)mlx4_unbond_vlan_table(dev);
1392err1:
1393 (void)mlx4_unbond_mac_table(dev);
1394 return err;
1395}
1396
1397static int mlx4_mf_unbond(struct mlx4_dev *dev)
1398{
1399 int ret, ret1;
1400
1401 ret = mlx4_unbond_fs_rules(dev);
1402 if (ret)
26ff7585 1403 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret);
e57968a1
MS		 1404 ret1 = mlx4_unbond_mac_table(dev);
1405 if (ret1) {
1406 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1407 ret = ret1;
1408 }
1409 ret1 = mlx4_unbond_vlan_table(dev);
1410 if (ret1) {
1411 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1412 ret = ret1;
1413 }
1414 return ret;
1415}
1416
e2fb47d4 1417static int mlx4_bond(struct mlx4_dev *dev)
53f33ae2
MS		 1418{
1419 int ret = 0;
1420 struct mlx4_priv *priv = mlx4_priv(dev);
1421
1422 mutex_lock(&priv->bond_mutex);
1423
e57968a1 1424 if (!mlx4_is_bonded(dev)) {
53f33ae2 1425 ret = mlx4_do_bond(dev, true);
e57968a1
MS		 1426 if (ret)
1427 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1428 if (!ret && mlx4_is_master(dev)) {
1429 ret = mlx4_mf_bond(dev);
1430 if (ret) {
1431 mlx4_err(dev, "bond for multifunction failed\n");
1432 mlx4_do_bond(dev, false);
1433 }
1434 }
1435 }
53f33ae2
MS		 1436
1437 mutex_unlock(&priv->bond_mutex);
e57968a1 1438 if (!ret)
53f33ae2 1439 mlx4_dbg(dev, "Device is bonded\n");
e57968a1 1440
53f33ae2
MS		 1441 return ret;
1442}
53f33ae2 1443
e2fb47d4 1444static int mlx4_unbond(struct mlx4_dev *dev)
53f33ae2
MS		 1445{
1446 int ret = 0;
1447 struct mlx4_priv *priv = mlx4_priv(dev);
1448
1449 mutex_lock(&priv->bond_mutex);
1450
e57968a1
MS		 1451 if (mlx4_is_bonded(dev)) {
1452 int ret2 = 0;
1453
53f33ae2 1454 ret = mlx4_do_bond(dev, false);
e57968a1
MS		 1455 if (ret)
1456 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1457 if (mlx4_is_master(dev))
1458 ret2 = mlx4_mf_unbond(dev);
1459 if (ret2) {
1460 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1461 ret = ret2;
1462 }
1463 }
53f33ae2
MS		 1464
1465 mutex_unlock(&priv->bond_mutex);
e57968a1 1466 if (!ret)
53f33ae2 1467 mlx4_dbg(dev, "Device is unbonded\n");
e57968a1 1468
53f33ae2
MS		 1469 return ret;
1470}
53f33ae2 1471
e2fb47d4 1472static int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
53f33ae2
MS		 1473{
1474 u8 port1 = v2p->port1;
1475 u8 port2 = v2p->port2;
1476 struct mlx4_priv *priv = mlx4_priv(dev);
1477 int err;
1478
1479 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
423b3aec 1480 return -EOPNOTSUPP;
53f33ae2
MS		 1481
1482 mutex_lock(&priv->bond_mutex);
1483
1484 /* zero means keep current mapping for this port */
1485 if (port1 == 0)
1486 port1 = priv->v2p.port1;
1487 if (port2 == 0)
1488 port2 = priv->v2p.port2;
1489
1490 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1491 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1492 (port1 == 2 && port2 == 1)) {
1493 /* besides boundary checks cross mapping makes
1494 * no sense and therefore not allowed */
1495 err = -EINVAL;
1496 } else if ((port1 == priv->v2p.port1) &&
1497 (port2 == priv->v2p.port2)) {
1498 err = 0;
1499 } else {
1500 err = mlx4_virt2phy_port_map(dev, port1, port2);
1501 if (!err) {
1502 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1503 port1, port2);
1504 priv->v2p.port1 = port1;
1505 priv->v2p.port2 = port2;
1506 } else {
6cc9c6fb 1507 mlx4_err(dev, "Failed to change port map: %d\n", err);
53f33ae2
MS		 1508 }
1509 }
1510
1511 mutex_unlock(&priv->bond_mutex);
1512 return err;
1513}
e2fb47d4
PP		 1514
1515struct mlx4_bond {
1516 struct work_struct work;
1517 struct mlx4_dev *dev;
1518 int is_bonded;
1519 struct mlx4_port_map port_map;
1520};
1521
1522static void mlx4_bond_work(struct work_struct *work)
1523{
1524 struct mlx4_bond *bond = container_of(work, struct mlx4_bond, work);
1525 int err = 0;
1526
1527 if (bond->is_bonded) {
1528 if (!mlx4_is_bonded(bond->dev)) {
1529 err = mlx4_bond(bond->dev);
1530 if (err)
1531 mlx4_err(bond->dev, "Fail to bond device\n");
1532 }
1533 if (!err) {
1534 err = mlx4_port_map_set(bond->dev, &bond->port_map);
1535 if (err)
1536 mlx4_err(bond->dev,
1537 "Fail to set port map [%d][%d]: %d\n",
1538 bond->port_map.port1,
1539 bond->port_map.port2, err);
1540 }
1541 } else if (mlx4_is_bonded(bond->dev)) {
1542 err = mlx4_unbond(bond->dev);
1543 if (err)
1544 mlx4_err(bond->dev, "Fail to unbond device\n");
1545 }
1546 put_device(&bond->dev->persist->pdev->dev);
1547 kfree(bond);
1548}
1549
1550int mlx4_queue_bond_work(struct mlx4_dev *dev, int is_bonded, u8 v2p_p1,
1551 u8 v2p_p2)
1552{
1553 struct mlx4_bond *bond;
1554
1555 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
1556 if (!bond)
1557 return -ENOMEM;
1558
1559 INIT_WORK(&bond->work, mlx4_bond_work);
1560 get_device(&dev->persist->pdev->dev);
1561 bond->dev = dev;
1562 bond->is_bonded = is_bonded;
1563 bond->port_map.port1 = v2p_p1;
1564 bond->port_map.port2 = v2p_p2;
1565 queue_work(mlx4_wq, &bond->work);
1566 return 0;
1567}
1568EXPORT_SYMBOL(mlx4_queue_bond_work);
53f33ae2 1569
e8f9b2ed 1570static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1571{
1572 struct mlx4_priv *priv = mlx4_priv(dev);
1573 int err;
1574
1575 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1576 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1577 if (!priv->fw.fw_icm) {
1a91de28 1578 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1579 return -ENOMEM;
1580 }
1581
1582 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1583 if (err) {
1a91de28 1584 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1585 goto err_free;
1586 }
1587
1588 err = mlx4_RUN_FW(dev);
1589 if (err) {
1a91de28 1590 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1591 goto err_unmap_fa;
1592 }
1593
1594 return 0;
1595
1596err_unmap_fa:
1597 mlx4_UNMAP_FA(dev);
1598
1599err_free:
5b0bf5e2 1600 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1601 return err;
1602}
1603
e8f9b2ed
RD		 1604static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1605 int cmpt_entry_sz)
225c7b1f
RD		 1606{
1607 struct mlx4_priv *priv = mlx4_priv(dev);
1608 int err;
ab9c17a0 1609 int num_eqs;
225c7b1f
RD		 1610
1611 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1612 cmpt_base +
1613 ((u64) (MLX4_CMPT_TYPE_QP *
1614 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1615 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1616 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1617 0, 0);
225c7b1f
RD		 1618 if (err)
1619 goto err;
1620
1621 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1622 cmpt_base +
1623 ((u64) (MLX4_CMPT_TYPE_SRQ *
1624 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1625 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1626 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1627 if (err)
1628 goto err_qp;
1629
1630 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1631 cmpt_base +
1632 ((u64) (MLX4_CMPT_TYPE_CQ *
1633 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1634 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1635 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1636 if (err)
1637 goto err_srq;
1638
7ae0e400 1639 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1640 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1641 cmpt_base +
1642 ((u64) (MLX4_CMPT_TYPE_EQ *
1643 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1644 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1645 if (err)
1646 goto err_cq;
1647
1648 return 0;
1649
1650err_cq:
1651 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1652
1653err_srq:
1654 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1655
1656err_qp:
1657 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1658
1659err:
1660 return err;
1661}
1662
3d73c288
RD		 1663static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1664 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1665{
1666 struct mlx4_priv *priv = mlx4_priv(dev);
1667 u64 aux_pages;
ab9c17a0 1668 int num_eqs;
225c7b1f
RD		 1669 int err;
1670
1671 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1672 if (err) {
1a91de28 1673 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1674 return err;
1675 }
1676
1a91de28 1677 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1678 (unsigned long long) icm_size >> 10,
1679 (unsigned long long) aux_pages << 2);
1680
1681 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1682 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1683 if (!priv->fw.aux_icm) {
1a91de28 1684 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1685 return -ENOMEM;
1686 }
1687
1688 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1689 if (err) {
1a91de28 1690 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1691 goto err_free_aux;
1692 }
1693
1694 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1695 if (err) {
1a91de28 1696 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1697 goto err_unmap_aux;
1698 }
1699
ab9c17a0 1700
7ae0e400 1701 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1702 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1703 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1704 num_eqs, num_eqs, 0, 0);
225c7b1f 1705 if (err) {
1a91de28 1706 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1707 goto err_unmap_cmpt;
1708 }
1709
d7bb58fb
JM		 1710 /*
1711 * Reserved MTT entries must be aligned up to a cacheline
1712 * boundary, since the FW will write to them, while the driver
1713 * writes to all other MTT entries. (The variable
1714 * dev->caps.mtt_entry_sz below is really the MTT segment
1715 * size, not the raw entry size)
1716 */
1717 dev->caps.reserved_mtts =
1718 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1719 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1720
225c7b1f
RD		 1721 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1722 init_hca->mtt_base,
1723 dev->caps.mtt_entry_sz,
2b8fb286 1724 dev->caps.num_mtts,
5b0bf5e2 1725 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1726 if (err) {
1a91de28 1727 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1728 goto err_unmap_eq;
1729 }
1730
1731 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1732 init_hca->dmpt_base,
1733 dev_cap->dmpt_entry_sz,
1734 dev->caps.num_mpts,
5b0bf5e2 1735 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1736 if (err) {
1a91de28 1737 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1738 goto err_unmap_mtt;
1739 }
1740
1741 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1742 init_hca->qpc_base,
1743 dev_cap->qpc_entry_sz,
1744 dev->caps.num_qps,
93fc9e1b
YP		 1745 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1746 0, 0);
225c7b1f 1747 if (err) {
1a91de28 1748 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1749 goto err_unmap_dmpt;
1750 }
1751
1752 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1753 init_hca->auxc_base,
1754 dev_cap->aux_entry_sz,
1755 dev->caps.num_qps,
93fc9e1b
YP		 1756 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1757 0, 0);
225c7b1f 1758 if (err) {
1a91de28 1759 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1760 goto err_unmap_qp;
1761 }
1762
1763 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1764 init_hca->altc_base,
1765 dev_cap->altc_entry_sz,
1766 dev->caps.num_qps,
93fc9e1b
YP		 1767 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1768 0, 0);
225c7b1f 1769 if (err) {
1a91de28 1770 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1771 goto err_unmap_auxc;
1772 }
1773
1774 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1775 init_hca->rdmarc_base,
1776 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1777 dev->caps.num_qps,
93fc9e1b
YP		 1778 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1779 0, 0);
225c7b1f
RD		 1780 if (err) {
1781 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1782 goto err_unmap_altc;
1783 }
1784
1785 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1786 init_hca->cqc_base,
1787 dev_cap->cqc_entry_sz,
1788 dev->caps.num_cqs,
5b0bf5e2 1789 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1790 if (err) {
1a91de28 1791 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1792 goto err_unmap_rdmarc;
1793 }
1794
1795 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1796 init_hca->srqc_base,
1797 dev_cap->srq_entry_sz,
1798 dev->caps.num_srqs,
5b0bf5e2 1799 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1800 if (err) {
1a91de28 1801 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1802 goto err_unmap_cq;
1803 }
1804
1805 /*
0ff1fb65
HHZ		 1806 * For flow steering device managed mode it is required to use
1807 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1808 * required, but for simplicity just map the whole multicast
1809 * group table now. The table isn't very big and it's a lot
1810 * easier than trying to track ref counts.
225c7b1f
RD		 1811 */
1812 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1813 init_hca->mc_base,
1814 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1815 dev->caps.num_mgms + dev->caps.num_amgms,
1816 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1817 0, 0);
225c7b1f 1818 if (err) {
1a91de28 1819 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1820 goto err_unmap_srq;
1821 }
1822
1823 return 0;
1824
1825err_unmap_srq:
1826 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1827
1828err_unmap_cq:
1829 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1830
1831err_unmap_rdmarc:
1832 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1833
1834err_unmap_altc:
1835 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1836
1837err_unmap_auxc:
1838 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1839
1840err_unmap_qp:
1841 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1842
1843err_unmap_dmpt:
1844 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1845
1846err_unmap_mtt:
1847 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1848
1849err_unmap_eq:
fa0681d2 1850 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1851
1852err_unmap_cmpt:
1853 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1854 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1855 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1856 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1857
1858err_unmap_aux:
1859 mlx4_UNMAP_ICM_AUX(dev);
1860
1861err_free_aux:
5b0bf5e2 1862 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1863
1864 return err;
1865}
1866
1867static void mlx4_free_icms(struct mlx4_dev *dev)
1868{
1869 struct mlx4_priv *priv = mlx4_priv(dev);
1870
1871 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1872 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1873 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1874 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1875 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1876 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1877 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1878 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1879 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1880 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1881 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1882 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1883 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1884 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1885
1886 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1887 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1888}
1889
ab9c17a0
JM		 1890static void mlx4_slave_exit(struct mlx4_dev *dev)
1891{
1892 struct mlx4_priv *priv = mlx4_priv(dev);
1893
f3d4c89e 1894 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1895 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1896 MLX4_COMM_TIME))
1a91de28 1897 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1898 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1899}
1900
c1b43dca
EC		 1901static int map_bf_area(struct mlx4_dev *dev)
1902{
1903 struct mlx4_priv *priv = mlx4_priv(dev);
1904 resource_size_t bf_start;
1905 resource_size_t bf_len;
1906 int err = 0;
1907
3d747473
JM		 1908 if (!dev->caps.bf_reg_size)
1909 return -ENXIO;
1910
872bf2fb 1911 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1912 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1913 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1914 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1915 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1916 if (!priv->bf_mapping)
1917 err = -ENOMEM;
1918
1919 return err;
1920}
1921
1922static void unmap_bf_area(struct mlx4_dev *dev)
1923{
1924 if (mlx4_priv(dev)->bf_mapping)
1925 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1926}
1927
a5a1d1c2 1928u64 mlx4_read_clock(struct mlx4_dev *dev)
ec693d47
AV		 1929{
1930 u32 clockhi, clocklo, clockhi1;
a5a1d1c2 1931 u64 cycles;
ec693d47
AV		 1932 int i;
1933 struct mlx4_priv *priv = mlx4_priv(dev);
1934
1935 for (i = 0; i < 10; i++) {
1936 clockhi = swab32(readl(priv->clock_mapping));
1937 clocklo = swab32(readl(priv->clock_mapping + 4));
1938 clockhi1 = swab32(readl(priv->clock_mapping));
1939 if (clockhi == clockhi1)
1940 break;
1941 }
1942
1943 cycles = (u64) clockhi << 32 | (u64) clocklo;
1944
1945 return cycles;
1946}
1947EXPORT_SYMBOL_GPL(mlx4_read_clock);
1948
1949
ddd8a6c1
EE		 1950static int map_internal_clock(struct mlx4_dev *dev)
1951{
1952 struct mlx4_priv *priv = mlx4_priv(dev);
1953
1954 priv->clock_mapping =
872bf2fb
YH		 1955 ioremap(pci_resource_start(dev->persist->pdev,
1956 priv->fw.clock_bar) +
ddd8a6c1
EE		 1957 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1958
1959 if (!priv->clock_mapping)
1960 return -ENOMEM;
1961
1962 return 0;
1963}
1964
52033cfb
MB		 1965int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1966 struct mlx4_clock_params *params)
1967{
1968 struct mlx4_priv *priv = mlx4_priv(dev);
1969
1970 if (mlx4_is_slave(dev))
423b3aec 1971 return -EOPNOTSUPP;
52033cfb 1972
404e5a12
SD		 1973 if (!dev->caps.map_clock_to_user) {
1974 mlx4_dbg(dev, "Map clock to user is not supported.\n");
1975 return -EOPNOTSUPP;
1976 }
1977
52033cfb
MB		 1978 if (!params)
1979 return -EINVAL;
1980
1981 params->bar = priv->fw.clock_bar;
1982 params->offset = priv->fw.clock_offset;
1983 params->size = MLX4_CLOCK_SIZE;
1984
1985 return 0;
1986}
1987EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1988
ddd8a6c1
EE		 1989static void unmap_internal_clock(struct mlx4_dev *dev)
1990{
1991 struct mlx4_priv *priv = mlx4_priv(dev);
1992
1993 if (priv->clock_mapping)
1994 iounmap(priv->clock_mapping);
1995}
1996
225c7b1f
RD		 1997static void mlx4_close_hca(struct mlx4_dev *dev)
1998{
ddd8a6c1 1999 unmap_internal_clock(dev);
c1b43dca 2000 unmap_bf_area(dev);
ab9c17a0
JM		 2001 if (mlx4_is_slave(dev))
2002 mlx4_slave_exit(dev);
2003 else {
2004 mlx4_CLOSE_HCA(dev, 0);
2005 mlx4_free_icms(dev);
a0eacca9
MB		 2006 }
2007}
2008
2009static void mlx4_close_fw(struct mlx4_dev *dev)
2010{
2011 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2012 mlx4_UNMAP_FA(dev);
2013 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
2014 }
2015}
2016
55ad3592
YH		 2017static int mlx4_comm_check_offline(struct mlx4_dev *dev)
2018{
2019#define COMM_CHAN_OFFLINE_OFFSET 0x09
2020
2021 u32 comm_flags;
2022 u32 offline_bit;
2023 unsigned long end;
2024 struct mlx4_priv *priv = mlx4_priv(dev);
2025
2026 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
2027 while (time_before(jiffies, end)) {
2028 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
2029 MLX4_COMM_CHAN_FLAGS));
2030 offline_bit = (comm_flags &
2031 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
2032 if (!offline_bit)
2033 return 0;
4cbe4dac
JM		 2034
2035 /* If device removal has been requested,
2036 * do not continue retrying.
2037 */
2038 if (dev->persist->interface_state &
2039 MLX4_INTERFACE_STATE_NOWAIT)
2040 break;
2041
55ad3592
YH		 2042 /* There are cases as part of AER/Reset flow that PF needs
2043 * around 100 msec to load. We therefore sleep for 100 msec
2044 * to allow other tasks to make use of that CPU during this
2045 * time interval.
2046 */
2047 msleep(100);
2048 }
2049 mlx4_err(dev, "Communication channel is offline.\n");
2050 return -EIO;
2051}
2052
2053static void mlx4_reset_vf_support(struct mlx4_dev *dev)
2054{
2055#define COMM_CHAN_RST_OFFSET 0x1e
2056
2057 struct mlx4_priv *priv = mlx4_priv(dev);
2058 u32 comm_rst;
2059 u32 comm_caps;
2060
2061 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
2062 MLX4_COMM_CHAN_CAPS));
2063 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
2064
2065 if (comm_rst)
2066 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2067}
2068
ab9c17a0
JM		 2069static int mlx4_init_slave(struct mlx4_dev *dev)
2070{
2071 struct mlx4_priv *priv = mlx4_priv(dev);
2072 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 2073 int ret_from_reset = 0;
2074 u32 slave_read;
2075 u32 cmd_channel_ver;
2076
97989356 2077 if (atomic_read(&pf_loading)) {
1a91de28 2078 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 2079 return -EPROBE_DEFER;
2080 }
2081
f3d4c89e 2082 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2083 priv->cmd.max_cmds = 1;
55ad3592
YH		 2084 if (mlx4_comm_check_offline(dev)) {
2085 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
2086 goto err_offline;
2087 }
2088
2089 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 2090 mlx4_warn(dev, "Sending reset\n");
2091 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 2092 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 2093 /* if we are in the middle of flr the slave will try
2094 * NUM_OF_RESET_RETRIES times before leaving.*/
2095 if (ret_from_reset) {
2096 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 2097 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 2098 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2099 return -EPROBE_DEFER;
ab9c17a0
JM		 2100 } else
2101 goto err;
2102 }
2103
2104 /* check the driver version - the slave I/F revision
2105 * must match the master's */
2106 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2107 cmd_channel_ver = mlx4_comm_get_version();
2108
2109 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2110 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 2111 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 2112 goto err;
2113 }
2114
2115 mlx4_warn(dev, "Sending vhcr0\n");
2116 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 2117 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2118 goto err;
2119 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 2120 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2121 goto err;
2122 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 2123 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2124 goto err;
0cd93027
YH		 2125 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2126 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2127 goto err;
f3d4c89e
RD		 2128
2129 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 2130 return 0;
2131
2132err:
0cd93027 2133 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 2134err_offline:
f3d4c89e 2135 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2136 return -EIO;
225c7b1f
RD		 2137}
2138
6634961c
JM		 2139static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2140{
2141 int i;
2142
2143 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 2144 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2145 dev->caps.gid_table_len[i] =
449fc488 2146 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 2147 else
2148 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 2149 dev->caps.pkey_table_len[i] =
2150 dev->phys_caps.pkey_phys_table_len[i] - 1;
2151 }
2152}
2153
3c439b55
JM		 2154static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2155{
2156 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2157
2158 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2159 i++) {
2160 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2161 break;
2162 }
2163
2164 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2165}
2166
7d077cd3
MB		 2167static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2168{
2169 switch (dmfs_high_steer_mode) {
2170 case MLX4_STEERING_DMFS_A0_DEFAULT:
2171 return "default performance";
2172
2173 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2174 return "dynamic hybrid mode";
2175
2176 case MLX4_STEERING_DMFS_A0_STATIC:
2177 return "performance optimized for limited rule configuration (static)";
2178
2179 case MLX4_STEERING_DMFS_A0_DISABLE:
2180 return "disabled performance optimized steering";
2181
2182 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2183 return "performance optimized steering not supported";
2184
2185 default:
2186 return "Unrecognized mode";
2187 }
2188}
2189
2190#define MLX4_DMFS_A0_STEERING (1UL << 2)
2191
7b8157be
JM		 2192static void choose_steering_mode(struct mlx4_dev *dev,
2193 struct mlx4_dev_cap *dev_cap)
2194{
7d077cd3
MB		 2195 if (mlx4_log_num_mgm_entry_size <= 0) {
2196 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2197 if (dev->caps.dmfs_high_steer_mode ==
2198 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2199 mlx4_err(dev, "DMFS high rate mode not supported\n");
2200 else
2201 dev->caps.dmfs_high_steer_mode =
2202 MLX4_STEERING_DMFS_A0_STATIC;
2203 }
2204 }
2205
2206 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 2207 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 2208 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 2209 (dev_cap->fs_max_num_qp_per_entry >=
2210 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 2211 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2212 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2213 dev->oper_log_mgm_entry_size =
2214 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 2215 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2216 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2217 dev->caps.fs_log_max_ucast_qp_range_size =
2218 dev_cap->fs_log_max_ucast_qp_range_size;
2219 } else {
7d077cd3
MB		 2220 if (dev->caps.dmfs_high_steer_mode !=
2221 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2222 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 2223 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2224 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2225 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2226 else {
2227 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2228
2229 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2230 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 2231 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 2232 }
3c439b55
JM		 2233 dev->oper_log_mgm_entry_size =
2234 mlx4_log_num_mgm_entry_size > 0 ?
2235 mlx4_log_num_mgm_entry_size :
2236 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 2237 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2238 }
1a91de28 2239 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 2240 mlx4_steering_mode_str(dev->caps.steering_mode),
2241 dev->oper_log_mgm_entry_size,
2242 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 2243}
2244
7ffdf726
OG		 2245static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2246 struct mlx4_dev_cap *dev_cap)
2247{
2248 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 2249 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 2250 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2251 else
2252 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2253
2254 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2255 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2256}
2257
7d077cd3
MB		 2258static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2259{
2260 int i;
2261 struct mlx4_port_cap port_cap;
2262
2263 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2264 return -EINVAL;
2265
2266 for (i = 1; i <= dev->caps.num_ports; i++) {
2267 if (mlx4_dev_port(dev, i, &port_cap)) {
2268 mlx4_err(dev,
f4b752a6 2269 "QUERY_DEV_CAP command failed, can't verify DMFS high rate steering.\n");
7d077cd3
MB		 2270 } else if ((dev->caps.dmfs_high_steer_mode !=
2271 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2272 (port_cap.dmfs_optimized_state ==
2273 !!(dev->caps.dmfs_high_steer_mode ==
2274 MLX4_STEERING_DMFS_A0_DISABLE))) {
2275 mlx4_err(dev,
2276 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2277 dmfs_high_rate_steering_mode_str(
2278 dev->caps.dmfs_high_steer_mode),
2279 (port_cap.dmfs_optimized_state ?
2280 "enabled" : "disabled"));
2281 }
2282 }
2283
2284 return 0;
2285}
2286
a0eacca9 2287static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2288{
2d928651 2289 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2290 int err = 0;
225c7b1f 2291
ab9c17a0
JM		 2292 if (!mlx4_is_slave(dev)) {
2293 err = mlx4_QUERY_FW(dev);
2294 if (err) {
2295 if (err == -EACCES)
1a91de28 2296 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2297 else
1a91de28 2298 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2299 return err;
ab9c17a0 2300 }
225c7b1f 2301
ab9c17a0
JM		 2302 err = mlx4_load_fw(dev);
2303 if (err) {
1a91de28 2304 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2305 return err;
ab9c17a0 2306 }
225c7b1f 2307
ab9c17a0
JM		 2308 mlx4_cfg.log_pg_sz_m = 1;
2309 mlx4_cfg.log_pg_sz = 0;
2310 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2311 if (err)
2312 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2313 }
2d928651 2314
a0eacca9
MB		 2315 return err;
2316}
2317
2318static int mlx4_init_hca(struct mlx4_dev *dev)
2319{
2320 struct mlx4_priv *priv = mlx4_priv(dev);
9eed21c0
AB		 2321 struct mlx4_init_hca_param *init_hca = NULL;
2322 struct mlx4_dev_cap *dev_cap = NULL;
a0eacca9 2323 struct mlx4_adapter adapter;
a0eacca9 2324 struct mlx4_profile profile;
a0eacca9
MB		 2325 u64 icm_size;
2326 struct mlx4_config_dev_params params;
2327 int err;
2328
2329 if (!mlx4_is_slave(dev)) {
9eed21c0
AB		 2330 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
2331 init_hca = kzalloc(sizeof(*init_hca), GFP_KERNEL);
2332
2333 if (!dev_cap || !init_hca) {
2334 err = -ENOMEM;
2335 goto out_free;
2336 }
2337
2338 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 2339 if (err) {
1a91de28 2340 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
9eed21c0 2341 goto out_free;
ab9c17a0 2342 }
225c7b1f 2343
9eed21c0
AB		 2344 choose_steering_mode(dev, dev_cap);
2345 choose_tunnel_offload_mode(dev, dev_cap);
7b8157be 2346
7d077cd3
MB		 2347 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2348 mlx4_is_master(dev))
2349 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2350
8e1a28e8
HHZ		 2351 err = mlx4_get_phys_port_id(dev);
2352 if (err)
2353 mlx4_err(dev, "Fail to get physical port id\n");
2354
6634961c
JM		 2355 if (mlx4_is_master(dev))
2356 mlx4_parav_master_pf_caps(dev);
2357
2599d858
AV		 2358 if (mlx4_low_memory_profile()) {
2359 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2360 profile = low_mem_profile;
2361 } else {
2362 profile = default_profile;
2363 }
0ff1fb65
HHZ		 2364 if (dev->caps.steering_mode ==
2365 MLX4_STEERING_MODE_DEVICE_MANAGED)
2366 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2367
9eed21c0
AB		 2368 icm_size = mlx4_make_profile(dev, &profile, dev_cap,
2369 init_hca);
ab9c17a0
JM		 2370 if ((long long) icm_size < 0) {
2371 err = icm_size;
9eed21c0 2372 goto out_free;
ab9c17a0 2373 }
225c7b1f 2374
ca3d89a3 2375 if (enable_4k_uar || !dev->persist->num_vfs) {
9eed21c0 2376 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) +
76e39ccf 2377 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
9eed21c0 2378 init_hca->uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
76e39ccf 2379 } else {
9eed21c0
AB		 2380 init_hca->log_uar_sz = ilog2(dev->caps.num_uars);
2381 init_hca->uar_page_sz = PAGE_SHIFT - 12;
76e39ccf 2382 }
85743f1e 2383
9eed21c0 2384 init_hca->mw_enabled = 0;
e448834e
SM		 2385 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2386 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
9eed21c0 2387 init_hca->mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2388
9eed21c0 2389 err = mlx4_init_icm(dev, dev_cap, init_hca, icm_size);
ab9c17a0 2390 if (err)
9eed21c0 2391 goto out_free;
225c7b1f 2392
9eed21c0 2393 err = mlx4_INIT_HCA(dev, init_hca);
ab9c17a0 2394 if (err) {
1a91de28 2395 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2396 goto err_free_icm;
2397 }
7ae0e400 2398
9eed21c0
AB		 2399 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2400 err = mlx4_query_func(dev, dev_cap);
7ae0e400
MB		 2401 if (err < 0) {
2402 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2403 goto err_close;
7ae0e400 2404 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
9eed21c0
AB		 2405 dev->caps.num_eqs = dev_cap->max_eqs;
2406 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2407 dev->caps.reserved_uars = dev_cap->reserved_uars;
7ae0e400
MB		 2408 }
2409 }
2410
ddd8a6c1
EE		 2411 /*
2412 * If TS is supported by FW
2413 * read HCA frequency by QUERY_HCA command
2414 */
2415 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
9eed21c0 2416 err = mlx4_QUERY_HCA(dev, init_hca);
ddd8a6c1 2417 if (err) {
1a91de28 2418 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2419 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2420 } else {
2421 dev->caps.hca_core_clock =
9eed21c0 2422 init_hca->hca_core_clock;
ddd8a6c1
EE		 2423 }
2424
2425 /* In case we got HCA frequency 0 - disable timestamping
2426 * to avoid dividing by zero
2427 */
2428 if (!dev->caps.hca_core_clock) {
2429 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2430 mlx4_err(dev,
1a91de28 2431 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2432 } else if (map_internal_clock(dev)) {
2433 /*
2434 * Map internal clock,
2435 * in case of failure disable timestamping
2436 */
2437 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2438 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2439 }
2440 }
7d077cd3
MB		 2441
2442 if (dev->caps.dmfs_high_steer_mode !=
2443 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2444 if (mlx4_validate_optimized_steering(dev))
2445 mlx4_warn(dev, "Optimized steering validation failed\n");
2446
2447 if (dev->caps.dmfs_high_steer_mode ==
2448 MLX4_STEERING_DMFS_A0_DISABLE) {
2449 dev->caps.dmfs_high_rate_qpn_base =
2450 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2451 dev->caps.dmfs_high_rate_qpn_range =
2452 MLX4_A0_STEERING_TABLE_SIZE;
2453 }
2454
4931c6ef
SM		 2455 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2456 dmfs_high_rate_steering_mode_str(
7d077cd3
MB		 2457 dev->caps.dmfs_high_steer_mode));
2458 }
ab9c17a0
JM		 2459 } else {
2460 err = mlx4_init_slave(dev);
2461 if (err) {
5efe5355
JM		 2462 if (err != -EPROBE_DEFER)
2463 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2464 return err;
ab9c17a0 2465 }
225c7b1f 2466
ab9c17a0
JM		 2467 err = mlx4_slave_cap(dev);
2468 if (err) {
2469 mlx4_err(dev, "Failed to obtain slave caps\n");
2470 goto err_close;
2471 }
225c7b1f
RD		 2472 }
2473
ab9c17a0
JM		 2474 if (map_bf_area(dev))
2475 mlx4_dbg(dev, "Failed to map blue flame area\n");
2476
2477 /*Only the master set the ports, all the rest got it from it.*/
2478 if (!mlx4_is_slave(dev))
2479 mlx4_set_port_mask(dev);
2480
225c7b1f
RD		 2481 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2482 if (err) {
1a91de28 2483 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2484 goto unmap_bf;
225c7b1f
RD		 2485 }
2486
f8c6455b
SM		 2487 /* Query CONFIG_DEV parameters */
2488 err = mlx4_config_dev_retrieval(dev, &params);
423b3aec 2489 if (err && err != -EOPNOTSUPP) {
f8c6455b
SM		 2490 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2491 } else if (!err) {
2492 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2493 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2494 }
225c7b1f 2495 priv->eq_table.inta_pin = adapter.inta_pin;
31975e27 2496 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
225c7b1f 2497
9eed21c0
AB		 2498 err = 0;
2499 goto out_free;
225c7b1f 2500
bef772eb 2501unmap_bf:
ddd8a6c1 2502 unmap_internal_clock(dev);
bef772eb
AY		 2503 unmap_bf_area(dev);
2504
c73c8b1e
EBE		 2505 if (mlx4_is_slave(dev))
2506 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 2507
225c7b1f 2508err_close:
41929ed2
DB		 2509 if (mlx4_is_slave(dev))
2510 mlx4_slave_exit(dev);
2511 else
2512 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2513
2514err_free_icm:
ab9c17a0
JM		 2515 if (!mlx4_is_slave(dev))
2516 mlx4_free_icms(dev);
225c7b1f 2517
9eed21c0
AB		 2518out_free:
2519 kfree(dev_cap);
2520 kfree(init_hca);
2521
225c7b1f
RD		 2522 return err;
2523}
2524
f2a3f6a3
OG		 2525static int mlx4_init_counters_table(struct mlx4_dev *dev)
2526{
2527 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2528 int nent_pow2;
f2a3f6a3
OG		 2529
2530 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2531 return -ENOENT;
2532
2632d18d
EBE		 2533 if (!dev->caps.max_counters)
2534 return -ENOSPC;
2535
47d8417f
EBE		 2536 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2537 /* reserve last counter index for sink counter */
2538 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2539 nent_pow2 - 1, 0,
2540 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2541}
2542
2543static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2544{
efa6bc91
EBE		 2545 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2546 return;
2547
2632d18d
EBE		 2548 if (!dev->caps.max_counters)
2549 return;
2550
f2a3f6a3
OG		 2551 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2552}
2553
6de5f7f6
EBE		 2554static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2555{
2556 struct mlx4_priv *priv = mlx4_priv(dev);
2557 int port;
2558
2559 for (port = 0; port < dev->caps.num_ports; port++)
2560 if (priv->def_counter[port] != -1)
2561 mlx4_counter_free(dev, priv->def_counter[port]);
2562}
2563
2564static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2565{
2566 struct mlx4_priv *priv = mlx4_priv(dev);
2567 int port, err = 0;
2568 u32 idx;
2569
2570 for (port = 0; port < dev->caps.num_ports; port++)
2571 priv->def_counter[port] = -1;
2572
2573 for (port = 0; port < dev->caps.num_ports; port++) {
f3301870 2574 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
6de5f7f6
EBE		 2575
2576 if (!err || err == -ENOSPC) {
2577 priv->def_counter[port] = idx;
40e47307 2578 err = 0;
6de5f7f6
EBE		 2579 } else if (err == -ENOENT) {
2580 err = 0;
2581 continue;
178d23e3
OG		 2582 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2583 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2584 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2585 MLX4_SINK_COUNTER_INDEX(dev));
2586 err = 0;
6de5f7f6
EBE		 2587 } else {
2588 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2589 __func__, port + 1, err);
2590 mlx4_cleanup_default_counters(dev);
2591 return err;
2592 }
2593
2594 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2595 __func__, priv->def_counter[port], port + 1);
2596 }
2597
2598 return err;
2599}
2600
ba062d52 2601int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2602{
2603 struct mlx4_priv *priv = mlx4_priv(dev);
2604
2605 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2606 return -ENOENT;
2607
2608 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2609 if (*idx == -1) {
2610 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2611 return -ENOSPC;
2612 }
f2a3f6a3
OG		 2613
2614 return 0;
2615}
ba062d52 2616
f3301870 2617int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
ba062d52 2618{
f3301870 2619 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
ba062d52
JM		 2620 u64 out_param;
2621 int err;
2622
2623 if (mlx4_is_mfunc(dev)) {
f3301870 2624 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
ba062d52
JM		 2625 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2626 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2627 if (!err)
2628 *idx = get_param_l(&out_param);
40e47307
TT		 2629 if (WARN_ON(err == -ENOSPC))
2630 err = -EINVAL;
ba062d52
JM		 2631 return err;
2632 }
2633 return __mlx4_counter_alloc(dev, idx);
2634}
f2a3f6a3
OG		 2635EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2636
b72ca7e9
EBE		 2637static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2638 u8 counter_index)
2639{
2640 struct mlx4_cmd_mailbox *if_stat_mailbox;
2641 int err;
2642 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2643
2644 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2645 if (IS_ERR(if_stat_mailbox))
2646 return PTR_ERR(if_stat_mailbox);
2647
2648 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2649 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2650 MLX4_CMD_NATIVE);
2651
2652 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2653 return err;
2654}
2655
ba062d52 2656void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2657{
efa6bc91
EBE		 2658 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2659 return;
2660
6de5f7f6
EBE		 2661 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2662 return;
2663
b72ca7e9
EBE		 2664 __mlx4_clear_if_stat(dev, idx);
2665
7c6d74d2 2666 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2667 return;
2668}
ba062d52
JM		 2669
2670void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2671{
e7dbeba8 2672 u64 in_param = 0;
ba062d52
JM		 2673
2674 if (mlx4_is_mfunc(dev)) {
2675 set_param_l(&in_param, idx);
2676 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2677 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2678 MLX4_CMD_WRAPPED);
2679 return;
2680 }
2681 __mlx4_counter_free(dev, idx);
2682}
f2a3f6a3
OG		 2683EXPORT_SYMBOL_GPL(mlx4_counter_free);
2684
6de5f7f6
EBE		 2685int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2686{
2687 struct mlx4_priv *priv = mlx4_priv(dev);
2688
2689 return priv->def_counter[port - 1];
2690}
2691EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2692
773af94e
YH		 2693void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2694{
2695 struct mlx4_priv *priv = mlx4_priv(dev);
2696
2697 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2698}
2699EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2700
2701__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2702{
2703 struct mlx4_priv *priv = mlx4_priv(dev);
2704
2705 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2706}
2707EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2708
fb517a4f
YH		 2709void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2710{
2711 struct mlx4_priv *priv = mlx4_priv(dev);
2712 __be64 guid;
2713
2714 /* hw GUID */
2715 if (entry == 0)
2716 return;
2717
2718 get_random_bytes((char *)&guid, sizeof(guid));
2719 guid &= ~(cpu_to_be64(1ULL << 56));
2720 guid |= cpu_to_be64(1ULL << 57);
2721 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2722}
2723
3d73c288 2724static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2725{
2726 struct mlx4_priv *priv = mlx4_priv(dev);
2727 int err;
7ff93f8b 2728 int port;
9a5aa622 2729 __be32 ib_port_default_caps;
225c7b1f 2730
225c7b1f
RD		 2731 err = mlx4_init_uar_table(dev);
2732 if (err) {
1a91de28 2733 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
5d4de16c 2734 return err;
225c7b1f
RD		 2735 }
2736
2737 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2738 if (err) {
1a91de28 2739 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2740 goto err_uar_table_free;
2741 }
2742
4979d18f 2743 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2744 if (!priv->kar) {
1a91de28 2745 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2746 err = -ENOMEM;
2747 goto err_uar_free;
2748 }
2749
2750 err = mlx4_init_pd_table(dev);
2751 if (err) {
1a91de28 2752 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2753 goto err_kar_unmap;
2754 }
2755
012a8ff5
SH		 2756 err = mlx4_init_xrcd_table(dev);
2757 if (err) {
1a91de28 2758 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2759 goto err_pd_table_free;
2760 }
2761
225c7b1f
RD		 2762 err = mlx4_init_mr_table(dev);
2763 if (err) {
1a91de28 2764 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2765 goto err_xrcd_table_free;
225c7b1f
RD		 2766 }
2767
fe6f700d
YP		 2768 if (!mlx4_is_slave(dev)) {
2769 err = mlx4_init_mcg_table(dev);
2770 if (err) {
1a91de28 2771 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2772 goto err_mr_table_free;
2773 }
114840c3
JM		 2774 err = mlx4_config_mad_demux(dev);
2775 if (err) {
2776 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2777 goto err_mcg_table_free;
2778 }
fe6f700d
YP		 2779 }
2780
225c7b1f
RD		 2781 err = mlx4_init_eq_table(dev);
2782 if (err) {
1a91de28 2783 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2784 goto err_mcg_table_free;
225c7b1f
RD		 2785 }
2786
2787 err = mlx4_cmd_use_events(dev);
2788 if (err) {
1a91de28 2789 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2790 goto err_eq_table_free;
2791 }
2792
2793 err = mlx4_NOP(dev);
2794 if (err) {
08fb1055 2795 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2796 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2797 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2798 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2799 } else {
1a91de28 2800 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2801 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2802 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2803 }
225c7b1f
RD		 2804
2805 goto err_cmd_poll;
2806 }
2807
2808 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2809
2810 err = mlx4_init_cq_table(dev);
2811 if (err) {
1a91de28 2812 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2813 goto err_cmd_poll;
2814 }
2815
2816 err = mlx4_init_srq_table(dev);
2817 if (err) {
1a91de28 2818 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2819 goto err_cq_table_free;
2820 }
2821
2822 err = mlx4_init_qp_table(dev);
2823 if (err) {
1a91de28 2824 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2825 goto err_srq_table_free;
2826 }
2827
2632d18d
EBE		 2828 if (!mlx4_is_slave(dev)) {
2829 err = mlx4_init_counters_table(dev);
2830 if (err && err != -ENOENT) {
2831 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2832 goto err_qp_table_free;
2833 }
f2a3f6a3
OG		 2834 }
2835
6de5f7f6
EBE		 2836 err = mlx4_allocate_default_counters(dev);
2837 if (err) {
2838 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2839 goto err_counters_table_free;
f2a3f6a3
OG		 2840 }
2841
ab9c17a0
JM		 2842 if (!mlx4_is_slave(dev)) {
2843 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2844 ib_port_default_caps = 0;
2845 err = mlx4_get_port_ib_caps(dev, port,
2846 &ib_port_default_caps);
2847 if (err)
1a91de28
JP		 2848 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2849 port, err);
ab9c17a0
JM		 2850 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2851
2aca1172
JM		 2852 /* initialize per-slave default ib port capabilities */
2853 if (mlx4_is_master(dev)) {
2854 int i;
2855 for (i = 0; i < dev->num_slaves; i++) {
2856 if (i == mlx4_master_func_num(dev))
2857 continue;
2858 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2859 ib_port_default_caps;
2aca1172
JM		 2860 }
2861 }
2862
096335b3
OG		 2863 if (mlx4_is_mfunc(dev))
2864 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2865 else
2866 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2867
6634961c
JM		 2868 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2869 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2870 if (err) {
2871 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2872 port);
6de5f7f6 2873 goto err_default_countes_free;
ab9c17a0 2874 }
7ff93f8b
YP		 2875 }
2876 }
2877
225c7b1f
RD		 2878 return 0;
2879
6de5f7f6
EBE		 2880err_default_countes_free:
2881 mlx4_cleanup_default_counters(dev);
2882
f2a3f6a3 2883err_counters_table_free:
2632d18d
EBE		 2884 if (!mlx4_is_slave(dev))
2885 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2886
225c7b1f
RD		 2887err_qp_table_free:
2888 mlx4_cleanup_qp_table(dev);
2889
2890err_srq_table_free:
2891 mlx4_cleanup_srq_table(dev);
2892
2893err_cq_table_free:
2894 mlx4_cleanup_cq_table(dev);
2895
2896err_cmd_poll:
2897 mlx4_cmd_use_polling(dev);
2898
2899err_eq_table_free:
2900 mlx4_cleanup_eq_table(dev);
2901
fe6f700d
YP		 2902err_mcg_table_free:
2903 if (!mlx4_is_slave(dev))
2904 mlx4_cleanup_mcg_table(dev);
2905
ee49bd93 2906err_mr_table_free:
225c7b1f
RD		 2907 mlx4_cleanup_mr_table(dev);
2908
012a8ff5
SH		 2909err_xrcd_table_free:
2910 mlx4_cleanup_xrcd_table(dev);
2911
225c7b1f
RD		 2912err_pd_table_free:
2913 mlx4_cleanup_pd_table(dev);
2914
2915err_kar_unmap:
2916 iounmap(priv->kar);
2917
2918err_uar_free:
2919 mlx4_uar_free(dev, &priv->driver_uar);
2920
2921err_uar_table_free:
2922 mlx4_cleanup_uar_table(dev);
2923 return err;
2924}
2925
de161803
IS		 2926static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2927{
2928 int requested_cpu = 0;
2929 struct mlx4_priv *priv = mlx4_priv(dev);
2930 struct mlx4_eq *eq;
2931 int off = 0;
2932 int i;
2933
2934 if (eqn > dev->caps.num_comp_vectors)
2935 return -EINVAL;
2936
2937 for (i = 1; i < port; i++)
2938 off += mlx4_get_eqs_per_port(dev, i);
2939
2940 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2941
2942 /* Meaning EQs are shared, and this call comes from the second port */
2943 if (requested_cpu < 0)
2944 return 0;
2945
2946 eq = &priv->eq_table.eq[eqn];
2947
2948 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2949 return -ENOMEM;
2950
2951 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2952
2953 return 0;
2954}
2955
e8f9b2ed 2956static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2957{
2958 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2959 struct msix_entry *entries;
225c7b1f 2960 int i;
c66fa19c 2961 int port = 0;
225c7b1f
RD		 2962
2963 if (msi_x) {
4762010f 2964 int nreq = min3(dev->caps.num_ports *
2965 (int)num_online_cpus() + 1,
2966 dev->caps.num_eqs - dev->caps.reserved_eqs,
2967 MAX_MSIX);
ab9c17a0 2968
e5732838
TT		 2969 if (msi_x > 1)
2970 nreq = min_t(int, nreq, msi_x);
2971
31975e27 2972 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
b8dd786f
YP		 2973 if (!entries)
2974 goto no_msi;
2975
2976 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2977 entries[i].entry = i;
2978
872bf2fb
YH		 2979 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2980 nreq);
66e2f9c1 2981
c66fa19c 2982 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2983 kfree(entries);
225c7b1f 2984 goto no_msi;
0b7ca5a9 2985 }
c66fa19c
MB		 2986 /* 1 is reserved for events (asyncrounous EQ) */
2987 dev->caps.num_comp_vectors = nreq - 1;
2988
2989 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2990 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2991 dev->caps.num_ports);
2992
2993 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2994 if (i == MLX4_EQ_ASYNC)
2995 continue;
2996
2997 priv->eq_table.eq[i].irq =
2998 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2999
85121d6e 3000 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
c66fa19c
MB		 3001 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
3002 dev->caps.num_ports);
de161803
IS		 3003 /* We don't set affinity hint when there
3004 * aren't enough EQs
3005 */
c66fa19c
MB		 3006 } else {
3007 set_bit(port,
3008 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 3009 if (mlx4_init_affinity_hint(dev, port + 1, i))
3010 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
3011 i);
c66fa19c
MB		 3012 }
3013 /* We divide the Eqs evenly between the two ports.
3014 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
3015 * refers to the number of Eqs per port
3016 * (i.e eqs_per_port). Theoretically, we would like to
3017 * write something like (i + 1) % eqs_per_port == 0.
3018 * However, since there's an asynchronous Eq, we have
3019 * to skip over it by comparing this condition to
3020 * !!((i + 1) > MLX4_EQ_ASYNC).
3021 */
3022 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
3023 ((i + 1) %
3024 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
3025 !!((i + 1) > MLX4_EQ_ASYNC))
3026 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
3027 * everything is shared anyway.
3028 */
3029 port++;
3030 }
225c7b1f
RD		 3031
3032 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 3033
3034 kfree(entries);
225c7b1f
RD		 3035 return;
3036 }
3037
3038no_msi:
b8dd786f
YP		 3039 dev->caps.num_comp_vectors = 1;
3040
c66fa19c
MB		 3041 BUG_ON(MLX4_EQ_ASYNC >= 2);
3042 for (i = 0; i < 2; ++i) {
872bf2fb 3043 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 3044 if (i != MLX4_EQ_ASYNC) {
3045 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
3046 dev->caps.num_ports);
3047 }
3048 }
225c7b1f
RD		 3049}
3050
65a4c44b
JP		 3051static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3052 enum devlink_port_type port_type)
3053{
3054 struct mlx4_port_info *info = container_of(devlink_port,
3055 struct mlx4_port_info,
3056 devlink_port);
3057 enum mlx4_port_type mlx4_port_type;
3058
3059 switch (port_type) {
3060 case DEVLINK_PORT_TYPE_AUTO:
3061 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3062 break;
3063 case DEVLINK_PORT_TYPE_ETH:
3064 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3065 break;
3066 case DEVLINK_PORT_TYPE_IB:
3067 mlx4_port_type = MLX4_PORT_TYPE_IB;
3068 break;
3069 default:
3070 return -EOPNOTSUPP;
3071 }
3072
3073 return __set_port_type(info, mlx4_port_type);
3074}
3075
8a756d91 3076static const struct devlink_port_ops mlx4_devlink_port_ops = {
65a4c44b 3077 .port_type_set = mlx4_devlink_port_type_set,
8a756d91
JP		 3078};
3079
7ff93f8b 3080static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8 3081{
09d4d087 3082 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2a2336f8 3083 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
09d4d087
JP		 3084 int err;
3085
8a756d91
JP		 3086 err = devl_port_register_with_ops(devlink, &info->devlink_port, port,
3087 &mlx4_devlink_port_ops);
09d4d087
JP		 3088 if (err)
3089 return err;
2a2336f8 3090
0313c7c2
JK		 3091 /* Ethernet and IB drivers will normally set the port type,
3092 * but if they are not built set the type now to prevent
3093 * devlink_port_type_warn() from firing.
3094 */
3095 if (!IS_ENABLED(CONFIG_MLX4_EN) &&
3096 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
c8096578 3097 devlink_port_type_eth_set(&info->devlink_port);
0313c7c2
JK		 3098 else if (!IS_ENABLED(CONFIG_MLX4_INFINIBAND) &&
3099 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
3100 devlink_port_type_ib_set(&info->devlink_port, NULL);
3101
2a2336f8
YP		 3102 info->dev = dev;
3103 info->port = port;
ab9c17a0 3104 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 3105 mlx4_init_mac_table(dev, &info->mac_table);
3106 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 3107 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 3108 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 3109 }
7ff93f8b
YP		 3110
3111 sprintf(info->dev_name, "mlx4_port%d", port);
3112 info->port_attr.attr.name = info->dev_name;
d3757ba4
JP		 3113 if (mlx4_is_mfunc(dev)) {
3114 info->port_attr.attr.mode = 0444;
3115 } else {
3116 info->port_attr.attr.mode = 0644;
ab9c17a0
JM		 3117 info->port_attr.store = set_port_type;
3118 }
7ff93f8b 3119 info->port_attr.show = show_port_type;
3691c964 3120 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 3121
872bf2fb 3122 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 3123 if (err) {
3124 mlx4_err(dev, "Failed to create file for port %d\n", port);
de9d555c 3125 devlink_port_type_clear(&info->devlink_port);
a8c05514 3126 devl_port_unregister(&info->devlink_port);
7ff93f8b 3127 info->port = -1;
57f6f99f 3128 return err;
7ff93f8b
YP		 3129 }
3130
096335b3
OG		 3131 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3132 info->port_mtu_attr.attr.name = info->dev_mtu_name;
d3757ba4
JP		 3133 if (mlx4_is_mfunc(dev)) {
3134 info->port_mtu_attr.attr.mode = 0444;
3135 } else {
3136 info->port_mtu_attr.attr.mode = 0644;
096335b3
OG		 3137 info->port_mtu_attr.store = set_port_ib_mtu;
3138 }
3139 info->port_mtu_attr.show = show_port_ib_mtu;
3140 sysfs_attr_init(&info->port_mtu_attr.attr);
3141
872bf2fb
YH		 3142 err = device_create_file(&dev->persist->pdev->dev,
3143 &info->port_mtu_attr);
096335b3
OG		 3144 if (err) {
3145 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 3146 device_remove_file(&info->dev->persist->pdev->dev,
3147 &info->port_attr);
de9d555c 3148 devlink_port_type_clear(&info->devlink_port);
a8c05514 3149 devl_port_unregister(&info->devlink_port);
096335b3 3150 info->port = -1;
57f6f99f 3151 return err;
096335b3
OG		 3152 }
3153
57f6f99f 3154 return 0;
7ff93f8b
YP		 3155}
3156
3157static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3158{
3159 if (info->port < 0)
3160 return;
3161
872bf2fb
YH		 3162 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3163 device_remove_file(&info->dev->persist->pdev->dev,
3164 &info->port_mtu_attr);
de9d555c 3165 devlink_port_type_clear(&info->devlink_port);
a8c05514 3166 devl_port_unregister(&info->devlink_port);
fba12966 3167
c66fa19c
MB		 3168#ifdef CONFIG_RFS_ACCEL
3169 free_irq_cpu_rmap(info->rmap);
3170 info->rmap = NULL;
3171#endif
2a2336f8
YP		 3172}
3173
b12d93d6
YP		 3174static int mlx4_init_steering(struct mlx4_dev *dev)
3175{
3176 struct mlx4_priv *priv = mlx4_priv(dev);
3177 int num_entries = dev->caps.num_ports;
3178 int i, j;
3179
6396bb22
KC		 3180 priv->steer = kcalloc(num_entries, sizeof(struct mlx4_steer),
3181 GFP_KERNEL);
b12d93d6
YP		 3182 if (!priv->steer)
3183 return -ENOMEM;
3184
45b51365 3185 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 3186 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3187 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3188 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3189 }
b12d93d6
YP		 3190 return 0;
3191}
3192
3193static void mlx4_clear_steering(struct mlx4_dev *dev)
3194{
3195 struct mlx4_priv *priv = mlx4_priv(dev);
3196 struct mlx4_steer_index *entry, *tmp_entry;
3197 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3198 int num_entries = dev->caps.num_ports;
3199 int i, j;
3200
3201 for (i = 0; i < num_entries; i++) {
3202 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3203 list_for_each_entry_safe(pqp, tmp_pqp,
3204 &priv->steer[i].promisc_qps[j],
3205 list) {
3206 list_del(&pqp->list);
3207 kfree(pqp);
3208 }
3209 list_for_each_entry_safe(entry, tmp_entry,
3210 &priv->steer[i].steer_entries[j],
3211 list) {
3212 list_del(&entry->list);
3213 list_for_each_entry_safe(pqp, tmp_pqp,
3214 &entry->duplicates,
3215 list) {
3216 list_del(&pqp->list);
3217 kfree(pqp);
3218 }
3219 kfree(entry);
3220 }
3221 }
3222 }
3223 kfree(priv->steer);
3224}
3225
ab9c17a0
JM		 3226static int extended_func_num(struct pci_dev *pdev)
3227{
3228 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3229}
3230
3231#define MLX4_OWNER_BASE 0x8069c
3232#define MLX4_OWNER_SIZE 4
3233
3234static int mlx4_get_ownership(struct mlx4_dev *dev)
3235{
3236 void __iomem *owner;
3237 u32 ret;
3238
872bf2fb 3239 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3240 return -EIO;
3241
872bf2fb
YH		 3242 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3243 MLX4_OWNER_BASE,
ab9c17a0
JM		 3244 MLX4_OWNER_SIZE);
3245 if (!owner) {
3246 mlx4_err(dev, "Failed to obtain ownership bit\n");
3247 return -ENOMEM;
3248 }
3249
3250 ret = readl(owner);
3251 iounmap(owner);
3252 return (int) !!ret;
3253}
3254
3255static void mlx4_free_ownership(struct mlx4_dev *dev)
3256{
3257 void __iomem *owner;
3258
872bf2fb 3259 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3260 return;
3261
872bf2fb
YH		 3262 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3263 MLX4_OWNER_BASE,
ab9c17a0
JM		 3264 MLX4_OWNER_SIZE);
3265 if (!owner) {
3266 mlx4_err(dev, "Failed to obtain ownership bit\n");
3267 return;
3268 }
3269 writel(0, owner);
3270 msleep(1000);
3271 iounmap(owner);
3272}
3273
a0eacca9
MB		 3274#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3275 !!((flags) & MLX4_FLAG_MASTER))
3276
3277static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 3278 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 3279{
3280 u64 dev_flags = dev->flags;
da315679 3281 int err = 0;
0beb44b0
CS		 3282 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3283 MLX4_MAX_NUM_VF);
a0eacca9 3284
55ad3592
YH		 3285 if (reset_flow) {
3286 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3287 GFP_KERNEL);
3288 if (!dev->dev_vfs)
3289 goto free_mem;
3290 return dev_flags;
3291 }
3292
da315679
MB		 3293 atomic_inc(&pf_loading);
3294 if (dev->flags & MLX4_FLAG_SRIOV) {
3295 if (existing_vfs != total_vfs) {
3296 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3297 existing_vfs, total_vfs);
3298 total_vfs = existing_vfs;
3299 }
3300 }
3301
6396bb22 3302 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 3303 if (NULL == dev->dev_vfs) {
3304 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3305 goto disable_sriov;
da315679
MB		 3306 }
3307
3308 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 3309 if (total_vfs > fw_enabled_sriov_vfs) {
3310 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3311 total_vfs, fw_enabled_sriov_vfs);
3312 err = -ENOMEM;
3313 goto disable_sriov;
3314 }
da315679
MB		 3315 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3316 err = pci_enable_sriov(pdev, total_vfs);
3317 }
3318 if (err) {
3319 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3320 err);
3321 goto disable_sriov;
3322 } else {
3323 mlx4_warn(dev, "Running in master mode\n");
3324 dev_flags |= MLX4_FLAG_SRIOV |
3325 MLX4_FLAG_MASTER;
3326 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 3327 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 3328 }
3329 return dev_flags;
3330
3331disable_sriov:
da315679 3332 atomic_dec(&pf_loading);
55ad3592 3333free_mem:
872bf2fb 3334 dev->persist->num_vfs = 0;
a0eacca9 3335 kfree(dev->dev_vfs);
92a59ad0 3336 dev->dev_vfs = NULL;
a0eacca9
MB		 3337 return dev_flags & ~MLX4_FLAG_MASTER;
3338}
3339
de966c59
MB		 3340enum {
3341 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3342};
3343
3344static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3345 int *nvfs)
3346{
3347 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3348 /* Checking for 64 VFs as a limitation of CX2 */
3349 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3350 requested_vfs >= 64) {
3351 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3352 requested_vfs);
3353 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3354 }
3355 return 0;
3356}
3357
4bfd2e6e
DJ		 3358static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3359{
3360 struct pci_dev *pdev = dev->persist->pdev;
3361 int err = 0;
3362
3363 mutex_lock(&dev->persist->pci_status_mutex);
3364 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3365 err = pci_enable_device(pdev);
3366 if (!err)
3367 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3368 }
3369 mutex_unlock(&dev->persist->pci_status_mutex);
3370
3371 return err;
3372}
3373
3374static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3375{
3376 struct pci_dev *pdev = dev->persist->pdev;
3377
3378 mutex_lock(&dev->persist->pci_status_mutex);
3379 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3380 pci_disable_device(pdev);
3381 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3382 }
3383 mutex_unlock(&dev->persist->pci_status_mutex);
3384}
3385
e1c00e10 3386static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3387 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3388 int reset_flow)
225c7b1f 3389{
a8c05514 3390 struct devlink *devlink = priv_to_devlink(priv);
225c7b1f 3391 struct mlx4_dev *dev;
e1c00e10 3392 unsigned sum = 0;
225c7b1f 3393 int err;
2a2336f8 3394 int port;
e1c00e10 3395 int i;
7ae0e400 3396 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3397 int existing_vfs = 0;
225c7b1f 3398
60d7ceea 3399 devl_assert_locked(devlink);
e1c00e10 3400 dev = &priv->dev;
225c7b1f 3401
8c2d2b87
PP		 3402 err = mlx4_adev_init(dev);
3403 if (err)
3404 return err;
3405
73d68002
PP		 3406 ATOMIC_INIT_NOTIFIER_HEAD(&priv->event_nh);
3407
7ff93f8b 3408 mutex_init(&priv->port_mutex);
53f33ae2 3409 mutex_init(&priv->bond_mutex);
7ff93f8b 3410
6296883c
YP		 3411 INIT_LIST_HEAD(&priv->pgdir_list);
3412 mutex_init(&priv->pgdir_mutex);
0c5ddb51 3413 spin_lock_init(&priv->cmd.context_lock);
6296883c 3414
c1b43dca
EC		 3415 INIT_LIST_HEAD(&priv->bf_list);
3416 mutex_init(&priv->bf_mutex);
3417
aca7a3ac 3418 dev->rev_id = pdev->revision;
6e7136ed 3419 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3420
ab9c17a0 3421 /* Detect if this device is a virtual function */
839f1243 3422 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3423 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3424 dev->flags |= MLX4_FLAG_SLAVE;
3425 } else {
3426 /* We reset the device and enable SRIOV only for physical
3427 * devices. Try to claim ownership on the device;
3428 * if already taken, skip -- do not allow multiple PFs */
3429 err = mlx4_get_ownership(dev);
3430 if (err) {
3431 if (err < 0)
8c2d2b87 3432 goto err_adev;
ab9c17a0 3433 else {
1a91de28 3434 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
8c2d2b87
PP		 3435 err = -EINVAL;
3436 goto err_adev;
ab9c17a0
JM		 3437 }
3438 }
aca7a3ac 3439
fe6f700d
YP		 3440 atomic_set(&priv->opreq_count, 0);
3441 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3442
ab9c17a0
JM		 3443 /*
3444 * Now reset the HCA before we touch the PCI capabilities or
3445 * attempt a firmware command, since a boot ROM may have left
3446 * the HCA in an undefined state.
3447 */
3448 err = mlx4_reset(dev);
3449 if (err) {
1a91de28 3450 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3451 goto err_sriov;
ab9c17a0 3452 }
7ae0e400
MB		 3453
3454 if (total_vfs) {
7ae0e400 3455 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3456 existing_vfs = pci_num_vf(pdev);
3457 if (existing_vfs)
3458 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3459 dev->persist->num_vfs = total_vfs;
7ae0e400 3460 }
225c7b1f
RD		 3461 }
3462
f6bc11e4
YH		 3463 /* on load remove any previous indication of internal error,
3464 * device is up.
3465 */
3466 dev->persist->state = MLX4_DEVICE_STATE_UP;
3467
ab9c17a0 3468slave_start:
521130d1
EE		 3469 err = mlx4_cmd_init(dev);
3470 if (err) {
1a91de28 3471 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3472 goto err_sriov;
3473 }
3474
3475 /* In slave functions, the communication channel must be initialized
3476 * before posting commands. Also, init num_slaves before calling
3477 * mlx4_init_hca */
3478 if (mlx4_is_mfunc(dev)) {
7ae0e400 3479 if (mlx4_is_master(dev)) {
ab9c17a0 3480 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3481
3482 } else {
ab9c17a0 3483 dev->num_slaves = 0;
f356fcbe
JM		 3484 err = mlx4_multi_func_init(dev);
3485 if (err) {
1a91de28 3486 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3487 goto err_cmd;
3488 }
3489 }
225c7b1f
RD		 3490 }
3491
a0eacca9
MB		 3492 err = mlx4_init_fw(dev);
3493 if (err) {
3494 mlx4_err(dev, "Failed to init fw, aborting.\n");
3495 goto err_mfunc;
3496 }
3497
7ae0e400 3498 if (mlx4_is_master(dev)) {
da315679 3499 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3500 if (!dev_cap) {
3501 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3502
3503 if (!dev_cap) {
3504 err = -ENOMEM;
3505 goto err_fw;
3506 }
3507
3508 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3509 if (err) {
3510 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3511 goto err_fw;
3512 }
3513
de966c59
MB		 3514 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3515 goto err_fw;
3516
7ae0e400 3517 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3518 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3519 total_vfs,
3520 existing_vfs,
3521 reset_flow);
7ae0e400 3522
ed3d2276 3523 mlx4_close_fw(dev);
7ae0e400
MB		 3524 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3525 dev->flags = dev_flags;
3526 if (!SRIOV_VALID_STATE(dev->flags)) {
3527 mlx4_err(dev, "Invalid SRIOV state\n");
3528 goto err_sriov;
3529 }
3530 err = mlx4_reset(dev);
3531 if (err) {
3532 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3533 goto err_sriov;
3534 }
3535 goto slave_start;
3536 }
3537 } else {
3538 /* Legacy mode FW requires SRIOV to be enabled before
3539 * doing QUERY_DEV_CAP, since max_eq's value is different if
3540 * SRIOV is enabled.
3541 */
3542 memset(dev_cap, 0, sizeof(*dev_cap));
3543 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3544 if (err) {
3545 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3546 goto err_fw;
3547 }
de966c59
MB		 3548
3549 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3550 goto err_fw;
7ae0e400
MB		 3551 }
3552 }
3553
225c7b1f 3554 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3555 if (err) {
3556 if (err == -EACCES) {
3557 /* Not primary Physical function
3558 * Running in slave mode */
ffc39f6d 3559 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3560 /* We're not a PF */
3561 if (dev->flags & MLX4_FLAG_SRIOV) {
3562 if (!existing_vfs)
3563 pci_disable_sriov(pdev);
55ad3592 3564 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3565 atomic_dec(&pf_loading);
3566 dev->flags &= ~MLX4_FLAG_SRIOV;
3567 }
3568 if (!mlx4_is_slave(dev))
3569 mlx4_free_ownership(dev);
ab9c17a0
JM		 3570 dev->flags |= MLX4_FLAG_SLAVE;
3571 dev->flags &= ~MLX4_FLAG_MASTER;
3572 goto slave_start;
3573 } else
a0eacca9 3574 goto err_fw;
ab9c17a0
JM		 3575 }
3576
7ae0e400 3577 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3578 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3579 existing_vfs, reset_flow);
7ae0e400
MB		 3580
3581 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3582 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3583 dev->flags = dev_flags;
3584 err = mlx4_cmd_init(dev);
3585 if (err) {
3586 /* Only VHCR is cleaned up, so could still
3587 * send FW commands
3588 */
3589 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3590 goto err_close;
3591 }
3592 } else {
3593 dev->flags = dev_flags;
3594 }
3595
3596 if (!SRIOV_VALID_STATE(dev->flags)) {
3597 mlx4_err(dev, "Invalid SRIOV state\n");
7e4960b3 3598 err = -EINVAL;
7ae0e400
MB		 3599 goto err_close;
3600 }
3601 }
3602
b912b2f8
EP		 3603 /* check if the device is functioning at its maximum possible speed.
3604 * No return code for this call, just warn the user in case of PCI
3605 * express device capabilities are under-satisfied by the bus.
3606 */
83d3459a 3607 if (!mlx4_is_slave(dev))
190b509c 3608 pcie_print_link_status(dev->persist->pdev);
b912b2f8 3609
ab9c17a0
JM		 3610 /* In master functions, the communication channel must be initialized
3611 * after obtaining its address from fw */
3612 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3613 if (dev->caps.num_ports < 2 &&
3614 num_vfs_argc > 1) {
3615 err = -EINVAL;
3616 mlx4_err(dev,
3617 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3618 dev->caps.num_ports);
ab9c17a0
JM		 3619 goto err_close;
3620 }
872bf2fb 3621 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3622
872bf2fb
YH		 3623 for (i = 0;
3624 i < sizeof(dev->persist->nvfs)/
3625 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3626 unsigned j;
3627
872bf2fb 3628 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3629 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3630 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3631 dev->caps.num_ports;
1ab95d37
MB		 3632 }
3633 }
e1c00e10
MD		 3634
3635 /* In master functions, the communication channel
3636 * must be initialized after obtaining its address from fw
3637 */
3638 err = mlx4_multi_func_init(dev);
3639 if (err) {
3640 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3641 goto err_close;
3642 }
ab9c17a0 3643 }
225c7b1f 3644
b8dd786f
YP		 3645 err = mlx4_alloc_eq_table(dev);
3646 if (err)
ab9c17a0 3647 goto err_master_mfunc;
b8dd786f 3648
c66fa19c 3649 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3650 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3651
08fb1055 3652 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3653 if ((mlx4_is_mfunc(dev)) &&
3654 !(dev->flags & MLX4_FLAG_MSI_X)) {
72b8eaab 3655 err = -EOPNOTSUPP;
1a91de28 3656 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3657 goto err_free_eq;
ab9c17a0
JM		 3658 }
3659
3660 if (!mlx4_is_slave(dev)) {
3661 err = mlx4_init_steering(dev);
3662 if (err)
e1c00e10 3663 goto err_disable_msix;
ab9c17a0 3664 }
b12d93d6 3665
6ed63d84
JM		 3666 mlx4_init_quotas(dev);
3667
225c7b1f 3668 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3669 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3670 !mlx4_is_mfunc(dev)) {
08fb1055 3671 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3672 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3673 pci_disable_msix(pdev);
3674 err = mlx4_setup_hca(dev);
3675 }
3676
225c7b1f 3677 if (err)
b12d93d6 3678 goto err_steer;
225c7b1f 3679
55ad3592
YH		 3680 /* When PF resources are ready arm its comm channel to enable
3681 * getting commands
3682 */
3683 if (mlx4_is_master(dev)) {
3684 err = mlx4_ARM_COMM_CHANNEL(dev);
3685 if (err) {
3686 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3687 err);
3688 goto err_steer;
3689 }
3690 }
5a0d0a61 3691
7ff93f8b
YP		 3692 for (port = 1; port <= dev->caps.num_ports; port++) {
3693 err = mlx4_init_port_info(dev, port);
3694 if (err)
3695 goto err_port;
3696 }
2a2336f8 3697
53f33ae2
MS		 3698 priv->v2p.port1 = 1;
3699 priv->v2p.port2 = 2;
3700
225c7b1f
RD		 3701 err = mlx4_register_device(dev);
3702 if (err)
7ff93f8b 3703 goto err_port;
225c7b1f 3704
27bf91d6
YP		 3705 mlx4_sense_init(dev);
3706 mlx4_start_sense(dev);
3707
befdf897 3708 priv->removed = 0;
225c7b1f 3709
55ad3592 3710 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3711 atomic_dec(&pf_loading);
3712
da315679 3713 kfree(dev_cap);
225c7b1f
RD		 3714 return 0;
3715
7ff93f8b 3716err_port:
b4f77264 3717 for (--port; port >= 1; --port)
7ff93f8b
YP		 3718 mlx4_cleanup_port_info(&priv->port[port]);
3719
6de5f7f6 3720 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3721 if (!mlx4_is_slave(dev))
3722 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3723 mlx4_cleanup_qp_table(dev);
3724 mlx4_cleanup_srq_table(dev);
3725 mlx4_cleanup_cq_table(dev);
3726 mlx4_cmd_use_polling(dev);
3727 mlx4_cleanup_eq_table(dev);
fe6f700d 3728 mlx4_cleanup_mcg_table(dev);
225c7b1f 3729 mlx4_cleanup_mr_table(dev);
012a8ff5 3730 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3731 mlx4_cleanup_pd_table(dev);
3732 mlx4_cleanup_uar_table(dev);
3733
b12d93d6 3734err_steer:
ab9c17a0
JM		 3735 if (!mlx4_is_slave(dev))
3736 mlx4_clear_steering(dev);
b12d93d6 3737
e1c00e10
MD		 3738err_disable_msix:
3739 if (dev->flags & MLX4_FLAG_MSI_X)
3740 pci_disable_msix(pdev);
3741
b8dd786f
YP		 3742err_free_eq:
3743 mlx4_free_eq_table(dev);
3744
ab9c17a0 3745err_master_mfunc:
772103e6
JM		 3746 if (mlx4_is_master(dev)) {
3747 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3748 mlx4_multi_func_cleanup(dev);
772103e6 3749 }
ab9c17a0 3750
c73c8b1e
EBE		 3751 if (mlx4_is_slave(dev))
3752 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 3753
225c7b1f
RD		 3754err_close:
3755 mlx4_close_hca(dev);
3756
a0eacca9
MB		 3757err_fw:
3758 mlx4_close_fw(dev);
3759
ab9c17a0
JM		 3760err_mfunc:
3761 if (mlx4_is_slave(dev))
3762 mlx4_multi_func_cleanup(dev);
3763
225c7b1f 3764err_cmd:
ffc39f6d 3765 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3766
ab9c17a0 3767err_sriov:
55ad3592 3768 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3769 pci_disable_sriov(pdev);
55ad3592
YH		 3770 dev->flags &= ~MLX4_FLAG_SRIOV;
3771 }
ab9c17a0 3772
55ad3592 3773 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3774 atomic_dec(&pf_loading);
3775
1ab95d37
MB		 3776 kfree(priv->dev.dev_vfs);
3777
e1c00e10
MD		 3778 if (!mlx4_is_slave(dev))
3779 mlx4_free_ownership(dev);
3780
7ae0e400 3781 kfree(dev_cap);
8c2d2b87
PP		 3782
3783err_adev:
3784 mlx4_adev_cleanup(dev);
e1c00e10
MD		 3785 return err;
3786}
3787
3788static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3789 struct mlx4_priv *priv)
3790{
3791 int err;
3792 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3793 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3794 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3795 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3796 unsigned total_vfs = 0;
3797 unsigned int i;
3798
3799 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3800
4bfd2e6e 3801 err = mlx4_pci_enable_device(&priv->dev);
e1c00e10
MD		 3802 if (err) {
3803 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3804 return err;
3805 }
3806
3807 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3808 * per port, we must limit the number of VFs to 63 (since their are
3809 * 128 MACs)
3810 */
691223ec 3811 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
e1c00e10
MD		 3812 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3813 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3814 if (nvfs[i] < 0) {
3815 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3816 err = -EINVAL;
3817 goto err_disable_pdev;
3818 }
3819 }
691223ec 3820 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
e1c00e10
MD		 3821 i++) {
3822 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3823 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3824 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3825 err = -EINVAL;
3826 goto err_disable_pdev;
3827 }
3828 }
0beb44b0 3829 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3830 dev_err(&pdev->dev,
0beb44b0
CS		 3831 "Requested more VF's (%d) than allowed by hw (%d)\n",
3832 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3833 err = -EINVAL;
3834 goto err_disable_pdev;
3835 }
3836
3837 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3838 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3839 dev_err(&pdev->dev,
0beb44b0 3840 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3841 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3842 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3843 err = -EINVAL;
3844 goto err_disable_pdev;
3845 }
3846 }
3847
3848 /* Check for BARs. */
3849 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3850 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3851 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3852 pci_dev_data, pci_resource_flags(pdev, 0));
3853 err = -ENODEV;
3854 goto err_disable_pdev;
3855 }
3856 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3857 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3858 err = -ENODEV;
3859 goto err_disable_pdev;
3860 }
3861
3862 err = pci_request_regions(pdev, DRV_NAME);
3863 if (err) {
3864 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3865 goto err_disable_pdev;
3866 }
3867
3868 pci_set_master(pdev);
3869
eb9c5c0d 3870 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
e1c00e10
MD		 3871 if (err) {
3872 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
eb9c5c0d 3873 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
e1c00e10
MD		 3874 if (err) {
3875 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3876 goto err_release_regions;
3877 }
3878 }
e1c00e10
MD		 3879
3880 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3881 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3882 /* Detect if this device is a virtual function */
3883 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3884 /* When acting as pf, we normally skip vfs unless explicitly
3885 * requested to probe them.
3886 */
3887 if (total_vfs) {
3888 unsigned vfs_offset = 0;
3889
691223ec 3890 for (i = 0; i < ARRAY_SIZE(nvfs) &&
e1c00e10
MD		 3891 vfs_offset + nvfs[i] < extended_func_num(pdev);
3892 vfs_offset += nvfs[i], i++)
3893 ;
691223ec 3894 if (i == ARRAY_SIZE(nvfs)) {
e1c00e10
MD		 3895 err = -ENODEV;
3896 goto err_release_regions;
3897 }
3898 if ((extended_func_num(pdev) - vfs_offset)
3899 > prb_vf[i]) {
3900 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3901 extended_func_num(pdev));
3902 err = -ENODEV;
3903 goto err_release_regions;
3904 }
3905 }
3906 }
3907
bedc989b 3908 err = mlx4_crdump_init(&priv->dev);
e1c00e10
MD		 3909 if (err)
3910 goto err_release_regions;
ad9a0bf0 3911
bedc989b
AV		 3912 err = mlx4_catas_init(&priv->dev);
3913 if (err)
3914 goto err_crdump;
3915
55ad3592 3916 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3917 if (err)
3918 goto err_catas;
3919
e1c00e10 3920 return 0;
225c7b1f 3921
ad9a0bf0
YH		 3922err_catas:
3923 mlx4_catas_end(&priv->dev);
3924
bedc989b
AV		 3925err_crdump:
3926 mlx4_crdump_end(&priv->dev);
3927
a01df0fe
RD		 3928err_release_regions:
3929 pci_release_regions(pdev);
225c7b1f
RD		 3930
3931err_disable_pdev:
4bfd2e6e 3932 mlx4_pci_disable_device(&priv->dev);
225c7b1f
RD		 3933 return err;
3934}
3935
dfb3c082
MS		 3936static void mlx4_devlink_param_load_driverinit_values(struct devlink *devlink)
3937{
3c641ba4
AV		 3938 struct mlx4_priv *priv = devlink_priv(devlink);
3939 struct mlx4_dev *dev = &priv->dev;
3940 struct mlx4_fw_crdump *crdump = &dev->persist->crdump;
dfb3c082
MS		 3941 union devlink_param_value saved_value;
3942 int err;
3943
075935f0
JP		 3944 err = devl_param_driverinit_value_get(devlink,
3945 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET,
3946 &saved_value);
dfb3c082
MS		 3947 if (!err && mlx4_internal_err_reset != saved_value.vbool) {
3948 mlx4_internal_err_reset = saved_value.vbool;
3949 /* Notify on value changed on runtime configuration mode */
075935f0
JP		 3950 devl_param_value_changed(devlink,
3951 DEVLINK_PARAM_GENERIC_ID_INT_ERR_RESET);
dfb3c082 3952 }
075935f0
JP		 3953 err = devl_param_driverinit_value_get(devlink,
3954 DEVLINK_PARAM_GENERIC_ID_MAX_MACS,
3955 &saved_value);
dfb3c082
MS		 3956 if (!err)
3957 log_num_mac = order_base_2(saved_value.vu32);
075935f0
JP		 3958 err = devl_param_driverinit_value_get(devlink,
3959 MLX4_DEVLINK_PARAM_ID_ENABLE_64B_CQE_EQE,
3960 &saved_value);
dfb3c082
MS		 3961 if (!err)
3962 enable_64b_cqe_eqe = saved_value.vbool;
075935f0
JP		 3963 err = devl_param_driverinit_value_get(devlink,
3964 MLX4_DEVLINK_PARAM_ID_ENABLE_4K_UAR,
3965 &saved_value);
dfb3c082
MS		 3966 if (!err)
3967 enable_4k_uar = saved_value.vbool;
075935f0
JP		 3968 err = devl_param_driverinit_value_get(devlink,
3969 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT,
3970 &saved_value);
3c641ba4
AV		 3971 if (!err && crdump->snapshot_enable != saved_value.vbool) {
3972 crdump->snapshot_enable = saved_value.vbool;
075935f0
JP		 3973 devl_param_value_changed(devlink,
3974 DEVLINK_PARAM_GENERIC_ID_REGION_SNAPSHOT);
3c641ba4 3975 }
dfb3c082
MS		 3976}
3977
35c7ff34
JP		 3978static void mlx4_restart_one_down(struct pci_dev *pdev);
3979static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload,
3980 struct devlink *devlink);
3981
070c63f2 3982static int mlx4_devlink_reload_down(struct devlink *devlink, bool netns_change,
ccdf0721 3983 enum devlink_reload_action action,
dc64cc7c 3984 enum devlink_reload_limit limit,
97691069 3985 struct netlink_ext_ack *extack)
dfb3c082
MS		 3986{
3987 struct mlx4_priv *priv = devlink_priv(devlink);
3988 struct mlx4_dev *dev = &priv->dev;
3989 struct mlx4_dev_persistent *persist = dev->persist;
dfb3c082 3990
070c63f2
JP		 3991 if (netns_change) {
3992 NL_SET_ERR_MSG_MOD(extack, "Namespace change is not supported");
3993 return -EOPNOTSUPP;
3994 }
dfb3c082
MS		 3995 if (persist->num_vfs)
3996 mlx4_warn(persist->dev, "Reload performed on PF, will cause reset on operating Virtual Functions\n");
35c7ff34 3997 mlx4_restart_one_down(persist->pdev);
97691069
JP		 3998 return 0;
3999}
4000
ccdf0721 4001static int mlx4_devlink_reload_up(struct devlink *devlink, enum devlink_reload_action action,
dc64cc7c
MS		 4002 enum devlink_reload_limit limit, u32 *actions_performed,
4003 struct netlink_ext_ack *extack)
97691069
JP		 4004{
4005 struct mlx4_priv *priv = devlink_priv(devlink);
4006 struct mlx4_dev *dev = &priv->dev;
4007 struct mlx4_dev_persistent *persist = dev->persist;
4008 int err;
4009
ccdf0721 4010 *actions_performed = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT);
35c7ff34 4011 err = mlx4_restart_one_up(persist->pdev, true, devlink);
dfb3c082 4012 if (err)
35c7ff34
JP		 4013 mlx4_err(persist->dev, "mlx4_restart_one_up failed, ret=%d\n",
4014 err);
dfb3c082
MS		 4015
4016 return err;
4017}
4018
b2facd95 4019static const struct devlink_ops mlx4_devlink_ops = {
ccdf0721 4020 .reload_actions = BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT),
97691069
JP		 4021 .reload_down = mlx4_devlink_reload_down,
4022 .reload_up = mlx4_devlink_reload_up,
b2facd95
JP		 4023};
4024
1dd06ae8 4025static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 4026{
09d4d087 4027 struct devlink *devlink;
befdf897
WY		 4028 struct mlx4_priv *priv;
4029 struct mlx4_dev *dev;
e1c00e10 4030 int ret;
befdf897 4031
0a645e80 4032 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 4033
919d13a7 4034 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv), &pdev->dev);
09d4d087 4035 if (!devlink)
befdf897 4036 return -ENOMEM;
60d7ceea 4037 devl_lock(devlink);
09d4d087 4038 priv = devlink_priv(devlink);
befdf897
WY		 4039
4040 dev = &priv->dev;
872bf2fb
YH		 4041 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
4042 if (!dev->persist) {
09d4d087
JP		 4043 ret = -ENOMEM;
4044 goto err_devlink_free;
872bf2fb
YH		 4045 }
4046 dev->persist->pdev = pdev;
4047 dev->persist->dev = dev;
4048 pci_set_drvdata(pdev, dev->persist);
befdf897 4049 priv->pci_dev_data = id->driver_data;
f6bc11e4 4050 mutex_init(&dev->persist->device_state_mutex);
c69453e2 4051 mutex_init(&dev->persist->interface_state_mutex);
4bfd2e6e 4052 mutex_init(&dev->persist->pci_status_mutex);
befdf897 4053
075935f0
JP		 4054 ret = devl_params_register(devlink, mlx4_devlink_params,
4055 ARRAY_SIZE(mlx4_devlink_params));
09d4d087
JP		 4056 if (ret)
4057 goto err_devlink_unregister;
bd1b51dc
MS		 4058 mlx4_devlink_set_params_init_values(devlink);
4059 ret = __mlx4_init_one(pdev, id->driver_data, priv);
4060 if (ret)
4061 goto err_params_unregister;
2ba5fbd6 4062
09d4d087 4063 pci_save_state(pdev);
60d7ceea 4064 devl_unlock(devlink);
1e726859 4065 devlink_register(devlink);
09d4d087
JP		 4066 return 0;
4067
bd1b51dc 4068err_params_unregister:
075935f0
JP		 4069 devl_params_unregister(devlink, mlx4_devlink_params,
4070 ARRAY_SIZE(mlx4_devlink_params));
09d4d087 4071err_devlink_unregister:
09d4d087
JP		 4072 kfree(dev->persist);
4073err_devlink_free:
60d7ceea 4074 devl_unlock(devlink);
09d4d087 4075 devlink_free(devlink);
e1c00e10 4076 return ret;
3d73c288
RD		 4077}
4078
dd0eefe3
YH		 4079static void mlx4_clean_dev(struct mlx4_dev *dev)
4080{
4081 struct mlx4_dev_persistent *persist = dev->persist;
4082 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 4083 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 4084
4085 memset(priv, 0, sizeof(*priv));
4086 priv->dev.persist = persist;
55ad3592 4087 priv->dev.flags = flags;
dd0eefe3
YH		 4088}
4089
e1c00e10 4090static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 4091{
872bf2fb
YH		 4092 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4093 struct mlx4_dev *dev = persist->dev;
225c7b1f 4094 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 4095 int pci_dev_data;
a8c05514 4096 struct devlink *devlink;
dd0eefe3 4097 int p, i;
225c7b1f 4098
a8c05514 4099 devlink = priv_to_devlink(priv);
60d7ceea 4100 devl_assert_locked(devlink);
befdf897
WY		 4101 if (priv->removed)
4102 return;
225c7b1f 4103
dd0eefe3
YH		 4104 /* saving current ports type for further use */
4105 for (i = 0; i < dev->caps.num_ports; i++) {
4106 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
4107 dev->persist->curr_port_poss_type[i] = dev->caps.
4108 possible_type[i + 1];
4109 }
4110
befdf897 4111 pci_dev_data = priv->pci_dev_data;
225c7b1f 4112
befdf897
WY		 4113 mlx4_stop_sense(dev);
4114 mlx4_unregister_device(dev);
225c7b1f 4115
befdf897
WY		 4116 for (p = 1; p <= dev->caps.num_ports; p++) {
4117 mlx4_cleanup_port_info(&priv->port[p]);
4118 mlx4_CLOSE_PORT(dev, p);
4119 }
4120
4121 if (mlx4_is_master(dev))
4122 mlx4_free_resource_tracker(dev,
4123 RES_TR_FREE_SLAVES_ONLY);
4124
6de5f7f6 4125 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 4126 if (!mlx4_is_slave(dev))
4127 mlx4_cleanup_counters_table(dev);
befdf897
WY		 4128 mlx4_cleanup_qp_table(dev);
4129 mlx4_cleanup_srq_table(dev);
4130 mlx4_cleanup_cq_table(dev);
4131 mlx4_cmd_use_polling(dev);
4132 mlx4_cleanup_eq_table(dev);
4133 mlx4_cleanup_mcg_table(dev);
4134 mlx4_cleanup_mr_table(dev);
4135 mlx4_cleanup_xrcd_table(dev);
4136 mlx4_cleanup_pd_table(dev);
225c7b1f 4137
befdf897
WY		 4138 if (mlx4_is_master(dev))
4139 mlx4_free_resource_tracker(dev,
4140 RES_TR_FREE_STRUCTS_ONLY);
47605df9 4141
befdf897
WY		 4142 iounmap(priv->kar);
4143 mlx4_uar_free(dev, &priv->driver_uar);
4144 mlx4_cleanup_uar_table(dev);
4145 if (!mlx4_is_slave(dev))
4146 mlx4_clear_steering(dev);
4147 mlx4_free_eq_table(dev);
4148 if (mlx4_is_master(dev))
4149 mlx4_multi_func_cleanup(dev);
4150 mlx4_close_hca(dev);
a0eacca9 4151 mlx4_close_fw(dev);
befdf897
WY		 4152 if (mlx4_is_slave(dev))
4153 mlx4_multi_func_cleanup(dev);
ffc39f6d 4154 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 4155
befdf897
WY		 4156 if (dev->flags & MLX4_FLAG_MSI_X)
4157 pci_disable_msix(pdev);
befdf897
WY		 4158
4159 if (!mlx4_is_slave(dev))
4160 mlx4_free_ownership(dev);
4161
c73c8b1e 4162 mlx4_slave_destroy_special_qp_cap(dev);
befdf897
WY		 4163 kfree(dev->dev_vfs);
4164
8c2d2b87
PP		 4165 mlx4_adev_cleanup(dev);
4166
dd0eefe3 4167 mlx4_clean_dev(dev);
befdf897
WY		 4168 priv->pci_dev_data = pci_dev_data;
4169 priv->removed = 1;
4170}
4171
4172static void mlx4_remove_one(struct pci_dev *pdev)
4173{
872bf2fb
YH		 4174 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4175 struct mlx4_dev *dev = persist->dev;
befdf897 4176 struct mlx4_priv *priv = mlx4_priv(dev);
09d4d087 4177 struct devlink *devlink = priv_to_devlink(priv);
55ad3592 4178 int active_vfs = 0;
befdf897 4179
1e726859 4180 devlink_unregister(devlink);
a0c76345 4181
60d7ceea 4182 devl_lock(devlink);
4cbe4dac
JM		 4183 if (mlx4_is_slave(dev))
4184 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
4185
c69453e2
YH		 4186 mutex_lock(&persist->interface_state_mutex);
4187 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
4188 mutex_unlock(&persist->interface_state_mutex);
4189
55ad3592
YH		 4190 /* Disabling SR-IOV is not allowed while there are active vf's */
4191 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
4192 active_vfs = mlx4_how_many_lives_vf(dev);
4193 if (active_vfs) {
4194 pr_warn("Removing PF when there are active VF's !!\n");
4195 pr_warn("Will not disable SR-IOV.\n");
4196 }
4197 }
4198
c69453e2
YH		 4199 /* device marked to be under deletion running now without the lock
4200 * letting other tasks to be terminated
4201 */
4202 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4203 mlx4_unload_one(pdev);
4204 else
4205 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 4206 mlx4_catas_end(dev);
bedc989b 4207 mlx4_crdump_end(dev);
55ad3592
YH		 4208 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
4209 mlx4_warn(dev, "Disabling SR-IOV\n");
4210 pci_disable_sriov(pdev);
4211 }
4212
e1c00e10 4213 pci_release_regions(pdev);
4bfd2e6e 4214 mlx4_pci_disable_device(dev);
075935f0
JP		 4215 devl_params_unregister(devlink, mlx4_devlink_params,
4216 ARRAY_SIZE(mlx4_devlink_params));
872bf2fb 4217 kfree(dev->persist);
60d7ceea 4218 devl_unlock(devlink);
09d4d087 4219 devlink_free(devlink);
225c7b1f
RD		 4220}
4221
dd0eefe3
YH		 4222static int restore_current_port_types(struct mlx4_dev *dev,
4223 enum mlx4_port_type *types,
4224 enum mlx4_port_type *poss_types)
4225{
4226 struct mlx4_priv *priv = mlx4_priv(dev);
4227 int err, i;
4228
4229 mlx4_stop_sense(dev);
4230
4231 mutex_lock(&priv->port_mutex);
4232 for (i = 0; i < dev->caps.num_ports; i++)
4233 dev->caps.possible_type[i + 1] = poss_types[i];
4234 err = mlx4_change_port_types(dev, types);
4235 mlx4_start_sense(dev);
4236 mutex_unlock(&priv->port_mutex);
4237
4238 return err;
4239}
4240
35c7ff34
JP		 4241static void mlx4_restart_one_down(struct pci_dev *pdev)
4242{
4243 mlx4_unload_one(pdev);
4244}
4245
4246static int mlx4_restart_one_up(struct pci_dev *pdev, bool reload,
4247 struct devlink *devlink)
ee49bd93 4248{
872bf2fb
YH		 4249 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4250 struct mlx4_dev *dev = persist->dev;
839f1243 4251 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 4252 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4253 int pci_dev_data, err, total_vfs;
839f1243
RD		 4254
4255 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 4256 total_vfs = dev->persist->num_vfs;
4257 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10 4258
dfb3c082
MS		 4259 if (reload)
4260 mlx4_devlink_param_load_driverinit_values(devlink);
55ad3592 4261 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 4262 if (err) {
4263 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4264 __func__, pci_name(pdev), err);
4265 return err;
4266 }
4267
dd0eefe3
YH		 4268 err = restore_current_port_types(dev, dev->persist->curr_port_type,
4269 dev->persist->curr_port_poss_type);
4270 if (err)
4271 mlx4_err(dev, "could not restore original port types (%d)\n",
4272 err);
4273
e1c00e10 4274 return err;
ee49bd93
JM		 4275}
4276
35c7ff34
JP		 4277int mlx4_restart_one(struct pci_dev *pdev)
4278{
4279 mlx4_restart_one_down(pdev);
4280 return mlx4_restart_one_up(pdev, false, NULL);
4281}
4282
c19e4b90
BH		 4283#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4284#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4285#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4286
9baa3c34 4287static const struct pci_device_id mlx4_pci_table[] = {
a1b87145 4288#ifdef CONFIG_MLX4_CORE_GEN2
c19e4b90
BH		 4289 /* MT25408 "Hermon" */
4290 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
4291 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
4292 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
4293 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4294 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4295 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
4296 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
4297 /* MT25458 ConnectX EN 10GBASE-T */
4298 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4299 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
4300 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4301 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4302 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4303 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4304 /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4305 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4306 /* MT25400 Family [ConnectX-2] */
4307 MLX_VF(0x1002), /* Virtual Function */
a1b87145 4308#endif /* CONFIG_MLX4_CORE_GEN2 */
ab9c17a0 4309 /* MT27500 Family [ConnectX-3] */
c19e4b90
BH		 4310 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4311 MLX_VF(0x1004), /* Virtual Function */
4312 MLX_GN(0x1005), /* MT27510 Family */
4313 MLX_GN(0x1006), /* MT27511 Family */
4314 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
4315 MLX_GN(0x1008), /* MT27521 Family */
4316 MLX_GN(0x1009), /* MT27530 Family */
4317 MLX_GN(0x100a), /* MT27531 Family */
4318 MLX_GN(0x100b), /* MT27540 Family */
4319 MLX_GN(0x100c), /* MT27541 Family */
4320 MLX_GN(0x100d), /* MT27550 Family */
4321 MLX_GN(0x100e), /* MT27551 Family */
4322 MLX_GN(0x100f), /* MT27560 Family */
4323 MLX_GN(0x1010), /* MT27561 Family */
4324
4325 /*
4326 * See the mellanox_check_broken_intx_masking() quirk when
4327 * adding devices
4328 */
4329
225c7b1f
RD		 4330 { 0, }
4331};
4332
4333MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4334
57dbf29a
KSS		 4335static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4336 pci_channel_state_t state)
4337{
2ba5fbd6 4338 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
60d7ceea
MS		 4339 struct mlx4_dev *dev = persist->dev;
4340 struct devlink *devlink;
2ba5fbd6
YH		 4341
4342 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4343 mlx4_enter_error_state(persist);
57dbf29a 4344
60d7ceea
MS		 4345 devlink = priv_to_devlink(mlx4_priv(dev));
4346 devl_lock(devlink);
2ba5fbd6
YH		 4347 mutex_lock(&persist->interface_state_mutex);
4348 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4349 mlx4_unload_one(pdev);
4350
4351 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4352 devl_unlock(devlink);
2ba5fbd6
YH		 4353 if (state == pci_channel_io_perm_failure)
4354 return PCI_ERS_RESULT_DISCONNECT;
4355
4bfd2e6e 4356 mlx4_pci_disable_device(persist->dev);
2ba5fbd6 4357 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 4358}
4359
4360static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4361{
2ba5fbd6
YH		 4362 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4363 struct mlx4_dev *dev = persist->dev;
c12833ac 4364 int err;
97a5221f 4365
2ba5fbd6 4366 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4bfd2e6e 4367 err = mlx4_pci_enable_device(dev);
c12833ac
DJ		 4368 if (err) {
4369 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
2ba5fbd6
YH		 4370 return PCI_ERS_RESULT_DISCONNECT;
4371 }
4372
4373 pci_set_master(pdev);
4374 pci_restore_state(pdev);
4375 pci_save_state(pdev);
c12833ac
DJ		 4376 return PCI_ERS_RESULT_RECOVERED;
4377}
4378
4379static void mlx4_pci_resume(struct pci_dev *pdev)
4380{
4381 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4382 struct mlx4_dev *dev = persist->dev;
4383 struct mlx4_priv *priv = mlx4_priv(dev);
4384 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
60d7ceea 4385 struct devlink *devlink;
c12833ac
DJ		 4386 int total_vfs;
4387 int err;
2ba5fbd6 4388
c12833ac 4389 mlx4_err(dev, "%s was called\n", __func__);
2ba5fbd6
YH		 4390 total_vfs = dev->persist->num_vfs;
4391 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4392
60d7ceea
MS		 4393 devlink = priv_to_devlink(priv);
4394 devl_lock(devlink);
2ba5fbd6
YH		 4395 mutex_lock(&persist->interface_state_mutex);
4396 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
c12833ac 4397 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 4398 priv, 1);
c12833ac
DJ		 4399 if (err) {
4400 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4401 __func__, err);
2ba5fbd6
YH		 4402 goto end;
4403 }
4404
c12833ac 4405 err = restore_current_port_types(dev, dev->persist->
2ba5fbd6
YH		 4406 curr_port_type, dev->persist->
4407 curr_port_poss_type);
c12833ac
DJ		 4408 if (err)
4409 mlx4_err(dev, "could not restore original port types (%d)\n", err);
2ba5fbd6
YH		 4410 }
4411end:
4412 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4413 devl_unlock(devlink);
57dbf29a
KSS		 4414}
4415
2ba5fbd6
YH		 4416static void mlx4_shutdown(struct pci_dev *pdev)
4417{
4418 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3cab8c65 4419 struct mlx4_dev *dev = persist->dev;
60d7ceea 4420 struct devlink *devlink;
2ba5fbd6
YH		 4421
4422 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
60d7ceea
MS		 4423 devlink = priv_to_devlink(mlx4_priv(dev));
4424 devl_lock(devlink);
2ba5fbd6 4425 mutex_lock(&persist->interface_state_mutex);
b4353708 4426 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
2ba5fbd6
YH		 4427 mlx4_unload_one(pdev);
4428 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4429 devl_unlock(devlink);
3cab8c65 4430 mlx4_pci_disable_device(dev);
2ba5fbd6
YH		 4431}
4432
3646f0e5 4433static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 4434 .error_detected = mlx4_pci_err_detected,
4435 .slot_reset = mlx4_pci_slot_reset,
c12833ac 4436 .resume = mlx4_pci_resume,
57dbf29a
KSS		 4437};
4438
4e1a6911 4439static int __maybe_unused mlx4_suspend(struct device *dev_d)
86a3e5d0 4440{
0e3e206a 4441 struct pci_dev *pdev = to_pci_dev(dev_d);
86a3e5d0
YH		 4442 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4443 struct mlx4_dev *dev = persist->dev;
60d7ceea 4444 struct devlink *devlink;
86a3e5d0
YH		 4445
4446 mlx4_err(dev, "suspend was called\n");
60d7ceea
MS		 4447 devlink = priv_to_devlink(mlx4_priv(dev));
4448 devl_lock(devlink);
86a3e5d0
YH		 4449 mutex_lock(&persist->interface_state_mutex);
4450 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4451 mlx4_unload_one(pdev);
4452 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4453 devl_unlock(devlink);
86a3e5d0
YH		 4454
4455 return 0;
4456}
4457
4e1a6911 4458static int __maybe_unused mlx4_resume(struct device *dev_d)
86a3e5d0 4459{
0e3e206a 4460 struct pci_dev *pdev = to_pci_dev(dev_d);
86a3e5d0
YH		 4461 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4462 struct mlx4_dev *dev = persist->dev;
4463 struct mlx4_priv *priv = mlx4_priv(dev);
4464 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
60d7ceea 4465 struct devlink *devlink;
86a3e5d0
YH		 4466 int total_vfs;
4467 int ret = 0;
4468
4469 mlx4_err(dev, "resume was called\n");
4470 total_vfs = dev->persist->num_vfs;
4471 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4472
60d7ceea
MS		 4473 devlink = priv_to_devlink(priv);
4474 devl_lock(devlink);
86a3e5d0
YH		 4475 mutex_lock(&persist->interface_state_mutex);
4476 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4477 ret = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs,
4478 nvfs, priv, 1);
4479 if (!ret) {
4480 ret = restore_current_port_types(dev,
4481 dev->persist->curr_port_type,
4482 dev->persist->curr_port_poss_type);
4483 if (ret)
4484 mlx4_err(dev, "resume: could not restore original port types (%d)\n", ret);
4485 }
4486 }
4487 mutex_unlock(&persist->interface_state_mutex);
60d7ceea 4488 devl_unlock(devlink);
86a3e5d0
YH		 4489
4490 return ret;
4491}
4492
0e3e206a
VG		 4493static SIMPLE_DEV_PM_OPS(mlx4_pm_ops, mlx4_suspend, mlx4_resume);
4494
225c7b1f
RD		 4495static struct pci_driver mlx4_driver = {
4496 .name = DRV_NAME,
4497 .id_table = mlx4_pci_table,
4498 .probe = mlx4_init_one,
2ba5fbd6 4499 .shutdown = mlx4_shutdown,
f57e6848 4500 .remove = mlx4_remove_one,
0e3e206a 4501 .driver.pm = &mlx4_pm_ops,
57dbf29a 4502 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 4503};
4504
7ff93f8b
YP		 4505static int __init mlx4_verify_params(void)
4506{
e5732838
TT		 4507 if (msi_x < 0) {
4508 pr_warn("mlx4_core: bad msi_x: %d\n", msi_x);
4509 return -1;
4510 }
4511
7ff93f8b 4512 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 4513 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 4514 return -1;
4515 }
4516
cb29688a 4517 if (log_num_vlan != 0)
c20862c8
AV		 4518 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4519 MLX4_LOG_NUM_VLANS);
7ff93f8b 4520
ecc8fb11
AV		 4521 if (use_prio != 0)
4522 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 4523
7cc77bf4 4524 if ((log_mtts_per_seg < 0) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 4525 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4526 log_mtts_per_seg);
ab6bf42e
EC		 4527 return -1;
4528 }
4529
ab9c17a0
JM		 4530 /* Check if module param for ports type has legal combination */
4531 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 4532 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 4533 port_type_array[0] = true;
4534 }
4535
7d077cd3
MB		 4536 if (mlx4_log_num_mgm_entry_size < -7 ||
4537 (mlx4_log_num_mgm_entry_size > 0 &&
4538 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4539 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4540 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 4541 mlx4_log_num_mgm_entry_size,
4542 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4543 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 4544 return -1;
4545 }
4546
7ff93f8b
YP		 4547 return 0;
4548}
4549
225c7b1f
RD		 4550static int __init mlx4_init(void)
4551{
4552 int ret;
4553
8c2d2b87
PP		 4554 WARN_ONCE(strcmp(MLX4_ADEV_NAME, KBUILD_MODNAME),
4555 "mlx4_core name not in sync with kernel module name");
4556
7ff93f8b
YP		 4557 if (mlx4_verify_params())
4558 return -EINVAL;
4559
27bf91d6
YP		 4560
4561 mlx4_wq = create_singlethread_workqueue("mlx4");
4562 if (!mlx4_wq)
4563 return -ENOMEM;
ee49bd93 4564
225c7b1f 4565 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 4566 if (ret < 0)
4567 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4568 return ret < 0 ? ret : 0;
4569}
4570
4571static void __exit mlx4_cleanup(void)
4572{
4573 pci_unregister_driver(&mlx4_driver);
27bf91d6 4574 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4575}
4576
4577module_init(mlx4_init);
4578module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)