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net/mlx4: Add user mac FW update support
[linux-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
10b1c04e 45#include <linux/etherdevice.h>
09d4d087 46#include <net/devlink.h>
225c7b1f
RD		 47
48#include <linux/mlx4/device.h>
49#include <linux/mlx4/doorbell.h>
50
51#include "mlx4.h"
52#include "fw.h"
53#include "icm.h"
54
55MODULE_AUTHOR("Roland Dreier");
56MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
57MODULE_LICENSE("Dual BSD/GPL");
58MODULE_VERSION(DRV_VERSION);
59
27bf91d6
YP		 60struct workqueue_struct *mlx4_wq;
61
225c7b1f
RD		 62#ifdef CONFIG_MLX4_DEBUG
63
64int mlx4_debug_level = 0;
65module_param_named(debug_level, mlx4_debug_level, int, 0644);
66MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
67
68#endif /* CONFIG_MLX4_DEBUG */
69
70#ifdef CONFIG_PCI_MSI
71
08fb1055 72static int msi_x = 1;
225c7b1f
RD		 73module_param(msi_x, int, 0444);
74MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
75
76#else /* CONFIG_PCI_MSI */
77
78#define msi_x (0)
79
80#endif /* CONFIG_PCI_MSI */
81
dd41cc3b 82static uint8_t num_vfs[3] = {0, 0, 0};
effa4bc4 83static int num_vfs_argc;
dd41cc3b
MB		 84module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
85MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
86 "num_vfs=port1,port2,port1+2");
87
88static uint8_t probe_vf[3] = {0, 0, 0};
effa4bc4 89static int probe_vfs_argc;
dd41cc3b
MB		 90module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
91MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
92 "probe_vf=port1,port2,port1+2");
ab9c17a0 93
3b68067b 94static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 95module_param_named(log_num_mgm_entry_size,
96 mlx4_log_num_mgm_entry_size, int, 0444);
97MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
98 " of qp per mcg, for example:"
3c439b55 99 " 10 gives 248.range: 7 <="
0ff1fb65 100 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 101 " To activate device managed"
102 " flow steering when available, set to -1");
0ec2c0f8 103
be902ab1 104static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 105module_param(enable_64b_cqe_eqe, bool, 0444);
106MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 107 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 108
76e39ccf
EC		 109static bool enable_4k_uar;
110module_param(enable_4k_uar, bool, 0444);
111MODULE_PARM_DESC(enable_4k_uar,
112 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
113
77507aa2 114#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
7d077cd3
MB		 115 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
116 MLX4_FUNC_CAP_DMFS_A0_STATIC)
ab9c17a0 117
55ad3592
YH		 118#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
119
f57e6848 120static char mlx4_version[] =
225c7b1f 121 DRV_NAME ": Mellanox ConnectX core driver v"
cea2a6d8 122 DRV_VERSION "\n";
225c7b1f 123
3f2c5fb2 124static const struct mlx4_profile default_profile = {
ab9c17a0 125 .num_qp = 1 << 18,
225c7b1f 126 .num_srq = 1 << 16,
c9f2ba5e 127 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 128 .num_cq = 1 << 16,
129 .num_mcg = 1 << 13,
ab9c17a0 130 .num_mpt = 1 << 19,
9fd7a1e1 131 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 132};
133
3f2c5fb2 134static const struct mlx4_profile low_mem_profile = {
2599d858
AV		 135 .num_qp = 1 << 17,
136 .num_srq = 1 << 6,
137 .rdmarc_per_qp = 1 << 4,
138 .num_cq = 1 << 8,
139 .num_mcg = 1 << 8,
140 .num_mpt = 1 << 9,
141 .num_mtt = 1 << 7,
142};
143
ab9c17a0 144static int log_num_mac = 7;
93fc9e1b
YP		 145module_param_named(log_num_mac, log_num_mac, int, 0444);
146MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
147
148static int log_num_vlan;
149module_param_named(log_num_vlan, log_num_vlan, int, 0444);
150MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 151/* Log2 max number of VLANs per ETH port (0-7) */
152#define MLX4_LOG_NUM_VLANS 7
2599d858
AV		 153#define MLX4_MIN_LOG_NUM_VLANS 0
154#define MLX4_MIN_LOG_NUM_MAC 1
93fc9e1b 155
eb939922 156static bool use_prio;
93fc9e1b 157module_param_named(use_prio, use_prio, bool, 0444);
ecc8fb11 158MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
93fc9e1b 159
2b8fb286 160int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 161module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 162MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 163
8d0fc7b6 164static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 165static int arr_argc = 2;
166module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 167MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
168 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 169
170struct mlx4_port_config {
171 struct list_head list;
172 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
173 struct pci_dev *pdev;
174};
175
97989356
AV		 176static atomic_t pf_loading = ATOMIC_INIT(0);
177
85743f1e
HN		 178static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
179 struct mlx4_dev_cap *dev_cap)
180{
181 /* The reserved_uars is calculated by system page size unit.
182 * Therefore, adjustment is added when the uar page size is less
183 * than the system page size
184 */
185 dev->caps.reserved_uars =
186 max_t(int,
187 mlx4_get_num_reserved_uar(dev),
188 dev_cap->reserved_uars /
189 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
190}
191
27bf91d6
YP		 192int mlx4_check_port_params(struct mlx4_dev *dev,
193 enum mlx4_port_type *port_type)
7ff93f8b
YP		 194{
195 int i;
196
0b997657
YS		 197 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
198 for (i = 0; i < dev->caps.num_ports - 1; i++) {
199 if (port_type[i] != port_type[i + 1]) {
1a91de28 200 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
27bf91d6
YP		 201 return -EINVAL;
202 }
7ff93f8b
YP		 203 }
204 }
7ff93f8b
YP		 205
206 for (i = 0; i < dev->caps.num_ports; i++) {
207 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
1a91de28
JP		 208 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
209 i + 1);
7ff93f8b
YP		 210 return -EINVAL;
211 }
212 }
213 return 0;
214}
215
216static void mlx4_set_port_mask(struct mlx4_dev *dev)
217{
218 int i;
219
7ff93f8b 220 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 221 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 222}
f2a3f6a3 223
7ae0e400
MB		 224enum {
225 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
226};
227
228static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
229{
230 int err = 0;
231 struct mlx4_func func;
232
233 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
234 err = mlx4_QUERY_FUNC(dev, &func, 0);
235 if (err) {
236 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
237 return err;
238 }
239 dev_cap->max_eqs = func.max_eq;
240 dev_cap->reserved_eqs = func.rsvd_eqs;
241 dev_cap->reserved_uars = func.rsvd_uars;
242 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
243 }
244 return err;
245}
246
77507aa2
IS		 247static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
248{
249 struct mlx4_caps *dev_cap = &dev->caps;
250
251 /* FW not supporting or cancelled by user */
252 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
253 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
254 return;
255
256 /* Must have 64B CQE_EQE enabled by FW to use bigger stride
257 * When FW has NCSI it may decide not to report 64B CQE/EQEs
258 */
259 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
260 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
261 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
262 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
263 return;
264 }
265
266 if (cache_line_size() == 128 || cache_line_size() == 256) {
267 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
268 /* Changing the real data inside CQE size to 32B */
269 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
270 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
271
272 if (mlx4_is_master(dev))
273 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
274 } else {
0fab541a
OG		 275 if (cache_line_size() != 32 && cache_line_size() != 64)
276 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
77507aa2
IS		 277 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
278 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
279 }
280}
281
431df8c7
MB		 282static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
283 struct mlx4_port_cap *port_cap)
284{
285 dev->caps.vl_cap[port] = port_cap->max_vl;
286 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
287 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
288 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
289 /* set gid and pkey table operating lengths by default
290 * to non-sriov values
291 */
292 dev->caps.gid_table_len[port] = port_cap->max_gids;
293 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
294 dev->caps.port_width_cap[port] = port_cap->max_port_width;
295 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
af7d5185 296 dev->caps.max_tc_eth = port_cap->max_tc_eth;
431df8c7
MB		 297 dev->caps.def_mac[port] = port_cap->def_mac;
298 dev->caps.supported_type[port] = port_cap->supported_port_types;
299 dev->caps.suggested_type[port] = port_cap->suggested_type;
300 dev->caps.default_sense[port] = port_cap->default_sense;
301 dev->caps.trans_type[port] = port_cap->trans_type;
302 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
303 dev->caps.wavelength[port] = port_cap->wavelength;
304 dev->caps.trans_code[port] = port_cap->trans_code;
305
306 return 0;
307}
308
309static int mlx4_dev_port(struct mlx4_dev *dev, int port,
310 struct mlx4_port_cap *port_cap)
311{
312 int err = 0;
313
314 err = mlx4_QUERY_PORT(dev, port, port_cap);
315
316 if (err)
317 mlx4_err(dev, "QUERY_PORT command failed.\n");
318
319 return err;
320}
321
78500b8c
MM		 322static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
323{
324 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
325 return;
326
327 if (mlx4_is_mfunc(dev)) {
328 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
329 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
330 return;
331 }
332
333 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
334 mlx4_dbg(dev,
335 "Keep FCS is not supported - Disabling Ignore FCS");
336 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
337 return;
338 }
339}
340
431df8c7 341#define MLX4_A0_STEERING_TABLE_SIZE 256
3d73c288 342static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 343{
344 int err;
5ae2a7a8 345 int i;
225c7b1f
RD		 346
347 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
348 if (err) {
1a91de28 349 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
225c7b1f
RD		 350 return err;
351 }
c78e25ed 352 mlx4_dev_cap_dump(dev, dev_cap);
225c7b1f
RD		 353
354 if (dev_cap->min_page_sz > PAGE_SIZE) {
1a91de28 355 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
225c7b1f
RD		 356 dev_cap->min_page_sz, PAGE_SIZE);
357 return -ENODEV;
358 }
359 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
1a91de28 360 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
225c7b1f
RD		 361 dev_cap->num_ports, MLX4_MAX_PORTS);
362 return -ENODEV;
363 }
364
872bf2fb 365 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
1a91de28 366 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
225c7b1f 367 dev_cap->uar_size,
872bf2fb
YH		 368 (unsigned long long)
369 pci_resource_len(dev->persist->pdev, 2));
225c7b1f
RD		 370 return -ENODEV;
371 }
372
373 dev->caps.num_ports = dev_cap->num_ports;
7ae0e400
MB		 374 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
375 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
376 dev->caps.num_sys_eqs :
377 MLX4_MAX_EQ_NUM;
5ae2a7a8 378 for (i = 1; i <= dev->caps.num_ports; ++i) {
431df8c7
MB		 379 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
380 if (err) {
381 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
382 return err;
383 }
5ae2a7a8
RD		 384 }
385
ab9c17a0 386 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 387 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 388 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
389 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
390 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
391 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
392 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
393 dev->caps.max_wqes = dev_cap->max_qp_sz;
394 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 395 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
396 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
397 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
398 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
399 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 400 /*
401 * Subtract 1 from the limit because we need to allocate a
402 * spare CQE so the HCA HW can tell the difference between an
403 * empty CQ and a full CQ.
404 */
405 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
406 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
407 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 408 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 409 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0 410
225c7b1f 411 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 412 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
413 dev_cap->reserved_xrcds : 0;
414 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
415 dev_cap->max_xrcds : 0;
2b8fb286
MA		 416 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
417
149983af 418 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 419 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
420 dev->caps.flags = dev_cap->flags;
b3416f44 421 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 422 dev->caps.bmme_flags = dev_cap->bmme_flags;
423 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 424 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 425 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 426 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
c994f778
IK		 427 dev->caps.wol_port[1] = dev_cap->wol_port[1];
428 dev->caps.wol_port[2] = dev_cap->wol_port[2];
225c7b1f 429
85743f1e
HN		 430 /* Save uar page shift */
431 if (!mlx4_is_slave(dev)) {
432 /* Virtual PCI function needs to determine UAR page size from
433 * firmware. Only master PCI function can set the uar page size
434 */
ca3d89a3 435 if (enable_4k_uar || !dev->persist->num_vfs)
76e39ccf
EC		 436 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
437 else
438 dev->uar_page_shift = PAGE_SHIFT;
439
85743f1e
HN		 440 mlx4_set_num_reserved_uars(dev, dev_cap);
441 }
442
77fc29c4
HHZ		 443 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
444 struct mlx4_init_hca_param hca_param;
445
446 memset(&hca_param, 0, sizeof(hca_param));
447 err = mlx4_QUERY_HCA(dev, &hca_param);
448 /* Turn off PHV_EN flag in case phv_check_en is set.
449 * phv_check_en is a HW check that parse the packet and verify
450 * phv bit was reported correctly in the wqe. To allow QinQ
451 * PHV_EN flag should be set and phv_check_en must be cleared
452 * otherwise QinQ packets will be drop by the HW.
453 */
454 if (err || hca_param.phv_check_en)
455 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
456 }
457
ca3e57a5
RD		 458 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
459 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 460 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 461 /* Don't do sense port on multifunction devices (for now at least) */
462 if (mlx4_is_mfunc(dev))
463 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 464
2599d858
AV		 465 if (mlx4_low_memory_profile()) {
466 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
467 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
468 } else {
469 dev->caps.log_num_macs = log_num_mac;
470 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
471 }
93fc9e1b
YP		 472
473 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 474 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
475 if (dev->caps.supported_type[i]) {
476 /* if only ETH is supported - assign ETH */
477 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
478 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 479 /* if only IB is supported, assign IB */
ab9c17a0 480 else if (dev->caps.supported_type[i] ==
105c320f
JM		 481 MLX4_PORT_TYPE_IB)
482 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 483 else {
105c320f
JM		 484 /* if IB and ETH are supported, we set the port
485 * type according to user selection of port type;
486 * if user selected none, take the FW hint */
487 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 488 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
489 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 490 else
105c320f 491 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 492 }
493 }
8d0fc7b6
YP		 494 /*
495 * Link sensing is allowed on the port if 3 conditions are true:
496 * 1. Both protocols are supported on the port.
497 * 2. Different types are supported on the port
498 * 3. FW declared that it supports link sensing
499 */
27bf91d6 500 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 501 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 502 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 503 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 504
8d0fc7b6
YP		 505 /*
506 * If "default_sense" bit is set, we move the port to "AUTO" mode
507 * and perform sense_port FW command to try and set the correct
508 * port type from beginning
509 */
46c46747 510 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 511 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
512 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
513 mlx4_SENSE_PORT(dev, i, &sensed_port);
514 if (sensed_port != MLX4_PORT_TYPE_NONE)
515 dev->caps.port_type[i] = sensed_port;
516 } else {
517 dev->caps.possible_type[i] = dev->caps.port_type[i];
518 }
519
431df8c7
MB		 520 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
521 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
1a91de28 522 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 523 i, 1 << dev->caps.log_num_macs);
524 }
431df8c7
MB		 525 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
526 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
1a91de28 527 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
93fc9e1b
YP		 528 i, 1 << dev->caps.log_num_vlans);
529 }
530 }
531
ac0a72a3
OG		 532 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
533 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
534 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
535 mlx4_warn(dev,
536 "Granular QoS per VF not supported with IB/Eth configuration\n");
537 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
538 }
539
47d8417f 540 dev->caps.max_counters = dev_cap->max_counters;
f2a3f6a3 541
93fc9e1b
YP		 542 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
543 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
545 (1 << dev->caps.log_num_macs) *
546 (1 << dev->caps.log_num_vlans) *
93fc9e1b
YP		 547 dev->caps.num_ports;
548 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
7d077cd3
MB		 549
550 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
551 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
552 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
553 else
554 dev->caps.dmfs_high_rate_qpn_base =
555 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
556
557 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
558 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
559 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
560 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
561 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
562 } else {
563 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
564 dev->caps.dmfs_high_rate_qpn_base =
565 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
566 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
567 }
568
fc31e256
OG		 569 dev->caps.rl_caps = dev_cap->rl_caps;
570
d57febe1 571 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
7d077cd3 572 dev->caps.dmfs_high_rate_qpn_range;
93fc9e1b
YP		 573
574 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
575 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
576 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
577 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
578
e2c76824 579 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 580
b3051320 581 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 582 if (dev_cap->flags &
583 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
584 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
585 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
586 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
587 }
77507aa2
IS		 588
589 if (dev_cap->flags2 &
590 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
591 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
592 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
593 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
594 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
595 }
08ff3235
OG		 596 }
597
f97b4b5d 598 if ((dev->caps.flags &
08ff3235
OG		 599 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
600 mlx4_is_master(dev))
601 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
602
ddae0349 603 if (!mlx4_is_slave(dev)) {
77507aa2 604 mlx4_enable_cqe_eqe_stride(dev);
ddae0349 605 dev->caps.alloc_res_qp_mask =
d57febe1
MB		 606 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
607 MLX4_RESERVE_A0_QP;
3742cc65
IS		 608
609 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
610 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
611 mlx4_warn(dev, "Old device ETS support detected\n");
612 mlx4_warn(dev, "Consider upgrading device FW.\n");
613 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
614 }
615
ddae0349
EE		 616 } else {
617 dev->caps.alloc_res_qp_mask = 0;
618 }
77507aa2 619
78500b8c
MM		 620 mlx4_enable_ignore_fcs(dev);
621
225c7b1f
RD		 622 return 0;
623}
b912b2f8
EP		 624
625static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
626 enum pci_bus_speed *speed,
627 enum pcie_link_width *width)
628{
629 u32 lnkcap1, lnkcap2;
630 int err1, err2;
631
632#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
633
634 *speed = PCI_SPEED_UNKNOWN;
635 *width = PCIE_LNK_WIDTH_UNKNOWN;
636
872bf2fb
YH		 637 err1 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP,
638 &lnkcap1);
639 err2 = pcie_capability_read_dword(dev->persist->pdev, PCI_EXP_LNKCAP2,
640 &lnkcap2);
b912b2f8
EP		 641 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
642 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
643 *speed = PCIE_SPEED_8_0GT;
644 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
645 *speed = PCIE_SPEED_5_0GT;
646 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
647 *speed = PCIE_SPEED_2_5GT;
648 }
649 if (!err1) {
650 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
651 if (!lnkcap2) { /* pre-r3.0 */
652 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
653 *speed = PCIE_SPEED_5_0GT;
654 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
655 *speed = PCIE_SPEED_2_5GT;
656 }
657 }
658
659 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
660 return err1 ? err1 :
661 err2 ? err2 : -EINVAL;
662 }
663 return 0;
664}
665
666static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
667{
668 enum pcie_link_width width, width_cap;
669 enum pci_bus_speed speed, speed_cap;
670 int err;
671
672#define PCIE_SPEED_STR(speed) \
673 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
674 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
675 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
676 "Unknown")
677
678 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
679 if (err) {
680 mlx4_warn(dev,
681 "Unable to determine PCIe device BW capabilities\n");
682 return;
683 }
684
872bf2fb 685 err = pcie_get_minimum_link(dev->persist->pdev, &speed, &width);
b912b2f8
EP		 686 if (err || speed == PCI_SPEED_UNKNOWN ||
687 width == PCIE_LNK_WIDTH_UNKNOWN) {
688 mlx4_warn(dev,
689 "Unable to determine PCI device chain minimum BW\n");
690 return;
691 }
692
693 if (width != width_cap || speed != speed_cap)
694 mlx4_warn(dev,
695 "PCIe BW is different than device's capability\n");
696
697 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
698 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
699 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
700 width, width_cap);
701 return;
702}
703
ab9c17a0
JM		 704/*The function checks if there are live vf, return the num of them*/
705static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
706{
707 struct mlx4_priv *priv = mlx4_priv(dev);
708 struct mlx4_slave_state *s_state;
709 int i;
710 int ret = 0;
711
712 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
713 s_state = &priv->mfunc.master.slave_state[i];
714 if (s_state->active && s_state->last_cmd !=
715 MLX4_COMM_CMD_RESET) {
716 mlx4_warn(dev, "%s: slave: %d is still active\n",
717 __func__, i);
718 ret++;
719 }
720 }
721 return ret;
722}
723
396f2feb
JM		 724int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
725{
726 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 727
728 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
729 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 730 return -EINVAL;
731
47605df9 732 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 733 /* tunnel qp */
47605df9 734 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 735 else
47605df9 736 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 737 *qkey = qk;
738 return 0;
739}
740EXPORT_SYMBOL(mlx4_get_parav_qkey);
741
54679e14
JM		 742void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
743{
744 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
745
746 if (!mlx4_is_master(dev))
747 return;
748
749 priv->virt2phys_pkey[slave][port - 1][i] = val;
750}
751EXPORT_SYMBOL(mlx4_sync_pkey_table);
752
afa8fd1d
JM		 753void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
754{
755 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
756
757 if (!mlx4_is_master(dev))
758 return;
759
760 priv->slave_node_guids[slave] = guid;
761}
762EXPORT_SYMBOL(mlx4_put_slave_node_guid);
763
764__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
765{
766 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
767
768 if (!mlx4_is_master(dev))
769 return 0;
770
771 return priv->slave_node_guids[slave];
772}
773EXPORT_SYMBOL(mlx4_get_slave_node_guid);
774
e10903b0 775int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 776{
777 struct mlx4_priv *priv = mlx4_priv(dev);
778 struct mlx4_slave_state *s_slave;
779
780 if (!mlx4_is_master(dev))
781 return 0;
782
783 s_slave = &priv->mfunc.master.slave_state[slave];
784 return !!s_slave->active;
785}
786EXPORT_SYMBOL(mlx4_is_slave_active);
787
10b1c04e
JM		 788void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
789 struct _rule_hw *eth_header)
790{
791 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
792 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
793 struct mlx4_net_trans_rule_hw_eth *eth =
794 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
795 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
796 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
797 next_rule->rsvd == 0;
798
799 if (last_rule)
800 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
801 }
802}
803EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
804
7b8157be
JM		 805static void slave_adjust_steering_mode(struct mlx4_dev *dev,
806 struct mlx4_dev_cap *dev_cap,
807 struct mlx4_init_hca_param *hca_param)
808{
809 dev->caps.steering_mode = hca_param->steering_mode;
810 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
811 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
812 dev->caps.fs_log_max_ucast_qp_range_size =
813 dev_cap->fs_log_max_ucast_qp_range_size;
814 } else
815 dev->caps.num_qp_per_mgm =
816 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
817
818 mlx4_dbg(dev, "Steering mode is: %s\n",
819 mlx4_steering_mode_str(dev->caps.steering_mode));
820}
821
c73c8b1e
EBE		 822static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
823{
824 kfree(dev->caps.spec_qps);
825 dev->caps.spec_qps = NULL;
826}
827
828static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
829{
830 struct mlx4_func_cap *func_cap = NULL;
831 struct mlx4_caps *caps = &dev->caps;
832 int i, err = 0;
833
834 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
835 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
836
837 if (!func_cap || !caps->spec_qps) {
838 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
839 err = -ENOMEM;
840 goto err_mem;
841 }
842
843 for (i = 1; i <= caps->num_ports; ++i) {
844 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
845 if (err) {
846 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
847 i, err);
848 goto err_mem;
849 }
850 caps->spec_qps[i - 1] = func_cap->spec_qps;
851 caps->port_mask[i] = caps->port_type[i];
852 caps->phys_port_id[i] = func_cap->phys_port_id;
853 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
854 &caps->gid_table_len[i],
855 &caps->pkey_table_len[i]);
856 if (err) {
857 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
858 i, err);
859 goto err_mem;
860 }
861 }
862
863err_mem:
864 if (err)
865 mlx4_slave_destroy_special_qp_cap(dev);
866 kfree(func_cap);
867 return err;
868}
869
ab9c17a0
JM		 870static int mlx4_slave_cap(struct mlx4_dev *dev)
871{
872 int err;
873 u32 page_size;
c73c8b1e
EBE		 874 struct mlx4_dev_cap *dev_cap = NULL;
875 struct mlx4_func_cap *func_cap = NULL;
876 struct mlx4_init_hca_param *hca_param = NULL;
877
878 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
879 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
880 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
881 if (!hca_param || !func_cap || !dev_cap) {
882 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
883 err = -ENOMEM;
884 goto free_mem;
885 }
ab9c17a0 886
c73c8b1e 887 err = mlx4_QUERY_HCA(dev, hca_param);
ab9c17a0 888 if (err) {
1a91de28 889 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
c73c8b1e 890 goto free_mem;
ab9c17a0
JM		 891 }
892
483e0132
EP		 893 /* fail if the hca has an unknown global capability
894 * at this time global_caps should be always zeroed
895 */
c73c8b1e 896 if (hca_param->global_caps) {
ab9c17a0 897 mlx4_err(dev, "Unknown hca global capabilities\n");
c73c8b1e
EBE		 898 err = -EINVAL;
899 goto free_mem;
ab9c17a0
JM		 900 }
901
c73c8b1e 902 dev->caps.hca_core_clock = hca_param->hca_core_clock;
ddd8a6c1 903
c73c8b1e
EBE		 904 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
905 err = mlx4_dev_cap(dev, dev_cap);
ab9c17a0 906 if (err) {
1a91de28 907 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
c73c8b1e 908 goto free_mem;
ab9c17a0
JM		 909 }
910
b91cb3eb
JM		 911 err = mlx4_QUERY_FW(dev);
912 if (err)
1a91de28 913 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
b91cb3eb 914
ab9c17a0
JM		 915 page_size = ~dev->caps.page_size_cap + 1;
916 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
917 if (page_size > PAGE_SIZE) {
1a91de28 918 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
ab9c17a0 919 page_size, PAGE_SIZE);
c73c8b1e
EBE		 920 err = -ENODEV;
921 goto free_mem;
ab9c17a0
JM		 922 }
923
85743f1e 924 /* Set uar_page_shift for VF */
c73c8b1e 925 dev->uar_page_shift = hca_param->uar_page_sz + 12;
ab9c17a0 926
85743f1e
HN		 927 /* Make sure the master uar page size is valid */
928 if (dev->uar_page_shift > PAGE_SHIFT) {
929 mlx4_err(dev,
930 "Invalid configuration: uar page size is larger than system page size\n");
c73c8b1e
EBE		 931 err = -ENODEV;
932 goto free_mem;
ab9c17a0
JM		 933 }
934
85743f1e 935 /* Set reserved_uars based on the uar_page_shift */
c73c8b1e 936 mlx4_set_num_reserved_uars(dev, dev_cap);
85743f1e
HN		 937
938 /* Although uar page size in FW differs from system page size,
939 * upper software layers (mlx4_ib, mlx4_en and part of mlx4_core)
940 * still works with assumption that uar page size == system page size
941 */
942 dev->caps.uar_page_size = PAGE_SIZE;
943
c73c8b1e 944 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
ab9c17a0 945 if (err) {
1a91de28
JP		 946 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
947 err);
c73c8b1e 948 goto free_mem;
ab9c17a0
JM		 949 }
950
c73c8b1e 951 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
ab9c17a0 952 PF_CONTEXT_BEHAVIOUR_MASK) {
7d077cd3 953 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
c73c8b1e
EBE		 954 func_cap->pf_context_behaviour,
955 PF_CONTEXT_BEHAVIOUR_MASK);
956 err = -EINVAL;
957 goto free_mem;
958 }
959
960 dev->caps.num_ports = func_cap->num_ports;
961 dev->quotas.qp = func_cap->qp_quota;
962 dev->quotas.srq = func_cap->srq_quota;
963 dev->quotas.cq = func_cap->cq_quota;
964 dev->quotas.mpt = func_cap->mpt_quota;
965 dev->quotas.mtt = func_cap->mtt_quota;
966 dev->caps.num_qps = 1 << hca_param->log_num_qps;
967 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
968 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
969 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
970 dev->caps.num_eqs = func_cap->max_eq;
971 dev->caps.reserved_eqs = func_cap->reserved_eq;
972 dev->caps.reserved_lkey = func_cap->reserved_lkey;
ab9c17a0
JM		 973 dev->caps.num_pds = MLX4_NUM_PDS;
974 dev->caps.num_mgms = 0;
975 dev->caps.num_amgms = 0;
976
ab9c17a0 977 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1a91de28
JP		 978 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
979 dev->caps.num_ports, MLX4_MAX_PORTS);
ab9c17a0
JM		 980 return -ENODEV;
981 }
982
2b3ddf27
JM		 983 mlx4_replace_zero_macs(dev);
984
c73c8b1e
EBE		 985 err = mlx4_slave_special_qp_cap(dev);
986 if (err) {
987 mlx4_err(dev, "Set special QP caps failed. aborting\n");
988 goto free_mem;
6634961c 989 }
6230bb23 990
ab9c17a0
JM		 991 if (dev->caps.uar_page_size * (dev->caps.num_uars -
992 dev->caps.reserved_uars) >
872bf2fb
YH		 993 pci_resource_len(dev->persist->pdev,
994 2)) {
1a91de28 995 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
ab9c17a0 996 dev->caps.uar_page_size * dev->caps.num_uars,
872bf2fb
YH		 997 (unsigned long long)
998 pci_resource_len(dev->persist->pdev, 2));
d49c2197 999 err = -ENOMEM;
47605df9 1000 goto err_mem;
ab9c17a0
JM		 1001 }
1002
c73c8b1e 1003 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
08ff3235
OG		 1004 dev->caps.eqe_size = 64;
1005 dev->caps.eqe_factor = 1;
1006 } else {
1007 dev->caps.eqe_size = 32;
1008 dev->caps.eqe_factor = 0;
1009 }
1010
c73c8b1e 1011 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
08ff3235 1012 dev->caps.cqe_size = 64;
77507aa2 1013 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1014 } else {
1015 dev->caps.cqe_size = 32;
1016 }
1017
c73c8b1e
EBE		 1018 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
1019 dev->caps.eqe_size = hca_param->eqe_size;
77507aa2
IS		 1020 dev->caps.eqe_factor = 0;
1021 }
1022
c73c8b1e
EBE		 1023 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
1024 dev->caps.cqe_size = hca_param->cqe_size;
77507aa2
IS		 1025 /* User still need to know when CQE > 32B */
1026 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1027 }
1028
f9bd2d7f 1029 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 1030 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
f9bd2d7f 1031
be599603
MS		 1032 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1033 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
1034
c73c8b1e 1035 slave_adjust_steering_mode(dev, dev_cap, hca_param);
802f42a8 1036 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
c73c8b1e 1037 hca_param->rss_ip_frags ? "on" : "off");
7b8157be 1038
c73c8b1e 1039 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
ddae0349
EE		 1040 dev->caps.bf_reg_size)
1041 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1042
c73c8b1e 1043 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
d57febe1
MB		 1044 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1045
47605df9 1046err_mem:
c73c8b1e
EBE		 1047 if (err)
1048 mlx4_slave_destroy_special_qp_cap(dev);
1049free_mem:
1050 kfree(hca_param);
1051 kfree(func_cap);
1052 kfree(dev_cap);
47605df9 1053 return err;
ab9c17a0 1054}
225c7b1f 1055
b046ffe5
EP		 1056static void mlx4_request_modules(struct mlx4_dev *dev)
1057{
1058 int port;
1059 int has_ib_port = false;
1060 int has_eth_port = false;
1061#define EN_DRV_NAME "mlx4_en"
1062#define IB_DRV_NAME "mlx4_ib"
1063
1064 for (port = 1; port <= dev->caps.num_ports; port++) {
1065 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1066 has_ib_port = true;
1067 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1068 has_eth_port = true;
1069 }
1070
b046ffe5
EP		 1071 if (has_eth_port)
1072 request_module_nowait(EN_DRV_NAME);
f24f790f
OG		 1073 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1074 request_module_nowait(IB_DRV_NAME);
b046ffe5
EP		 1075}
1076
7ff93f8b
YP		 1077/*
1078 * Change the port configuration of the device.
1079 * Every user of this function must hold the port mutex.
1080 */
27bf91d6
YP		 1081int mlx4_change_port_types(struct mlx4_dev *dev,
1082 enum mlx4_port_type *port_types)
7ff93f8b
YP		 1083{
1084 int err = 0;
1085 int change = 0;
1086 int port;
1087
1088 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 1089 /* Change the port type only if the new type is different
1090 * from the current, and not set to Auto */
3d8f9308 1091 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 1092 change = 1;
7ff93f8b
YP		 1093 }
1094 if (change) {
1095 mlx4_unregister_device(dev);
1096 for (port = 1; port <= dev->caps.num_ports; port++) {
1097 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 1098 dev->caps.port_type[port] = port_types[port - 1];
6634961c 1099 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b 1100 if (err) {
1a91de28
JP		 1101 mlx4_err(dev, "Failed to set port %d, aborting\n",
1102 port);
7ff93f8b
YP		 1103 goto out;
1104 }
1105 }
1106 mlx4_set_port_mask(dev);
1107 err = mlx4_register_device(dev);
b046ffe5
EP		 1108 if (err) {
1109 mlx4_err(dev, "Failed to register device\n");
1110 goto out;
1111 }
1112 mlx4_request_modules(dev);
7ff93f8b
YP		 1113 }
1114
1115out:
1116 return err;
1117}
1118
1119static ssize_t show_port_type(struct device *dev,
1120 struct device_attribute *attr,
1121 char *buf)
1122{
1123 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1124 port_attr);
1125 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 1126 char type[8];
1127
1128 sprintf(type, "%s",
1129 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1130 "ib" : "eth");
1131 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1132 sprintf(buf, "auto (%s)\n", type);
1133 else
1134 sprintf(buf, "%s\n", type);
7ff93f8b 1135
27bf91d6 1136 return strlen(buf);
7ff93f8b
YP		 1137}
1138
b2facd95
JP		 1139static int __set_port_type(struct mlx4_port_info *info,
1140 enum mlx4_port_type port_type)
7ff93f8b 1141{
7ff93f8b
YP		 1142 struct mlx4_dev *mdev = info->dev;
1143 struct mlx4_priv *priv = mlx4_priv(mdev);
1144 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 1145 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 1146 int i;
1147 int err = 0;
1148
33a1f8b1
MG		 1149 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1150 mlx4_err(mdev,
1151 "Requested port type for port %d is not supported on this HCA\n",
1152 info->port);
1153 err = -EINVAL;
1154 goto err_sup;
1155 }
1156
27bf91d6 1157 mlx4_stop_sense(mdev);
7ff93f8b 1158 mutex_lock(&priv->port_mutex);
b2facd95
JP		 1159 info->tmp_type = port_type;
1160
27bf91d6
YP		 1161 /* Possible type is always the one that was delivered */
1162 mdev->caps.possible_type[info->port] = info->tmp_type;
1163
1164 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 1165 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 1166 mdev->caps.possible_type[i+1];
1167 if (types[i] == MLX4_PORT_TYPE_AUTO)
1168 types[i] = mdev->caps.port_type[i+1];
1169 }
7ff93f8b 1170
58a60168
YP		 1171 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1172 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 1173 for (i = 1; i <= mdev->caps.num_ports; i++) {
1174 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1175 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1176 err = -EINVAL;
1177 }
1178 }
1179 }
1180 if (err) {
1a91de28 1181 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
27bf91d6
YP		 1182 goto out;
1183 }
1184
1185 mlx4_do_sense_ports(mdev, new_types, types);
1186
1187 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 1188 if (err)
1189 goto out;
1190
27bf91d6
YP		 1191 /* We are about to apply the changes after the configuration
1192 * was verified, no need to remember the temporary types
1193 * any more */
1194 for (i = 0; i < mdev->caps.num_ports; i++)
1195 priv->port[i + 1].tmp_type = 0;
7ff93f8b 1196
27bf91d6 1197 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 1198
1199out:
27bf91d6 1200 mlx4_start_sense(mdev);
7ff93f8b 1201 mutex_unlock(&priv->port_mutex);
33a1f8b1 1202err_sup:
b2facd95
JP		 1203 return err;
1204}
1205
1206static ssize_t set_port_type(struct device *dev,
1207 struct device_attribute *attr,
1208 const char *buf, size_t count)
1209{
1210 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1211 port_attr);
1212 struct mlx4_dev *mdev = info->dev;
1213 enum mlx4_port_type port_type;
1214 static DEFINE_MUTEX(set_port_type_mutex);
1215 int err;
1216
1217 mutex_lock(&set_port_type_mutex);
1218
1219 if (!strcmp(buf, "ib\n")) {
1220 port_type = MLX4_PORT_TYPE_IB;
1221 } else if (!strcmp(buf, "eth\n")) {
1222 port_type = MLX4_PORT_TYPE_ETH;
1223 } else if (!strcmp(buf, "auto\n")) {
1224 port_type = MLX4_PORT_TYPE_AUTO;
1225 } else {
1226 mlx4_err(mdev, "%s is not supported port type\n", buf);
1227 err = -EINVAL;
1228 goto err_out;
1229 }
1230
1231 err = __set_port_type(info, port_type);
1232
0a984556
AV		 1233err_out:
1234 mutex_unlock(&set_port_type_mutex);
1235
7ff93f8b
YP		 1236 return err ? err : count;
1237}
1238
096335b3
OG		 1239enum ibta_mtu {
1240 IB_MTU_256 = 1,
1241 IB_MTU_512 = 2,
1242 IB_MTU_1024 = 3,
1243 IB_MTU_2048 = 4,
1244 IB_MTU_4096 = 5
1245};
1246
1247static inline int int_to_ibta_mtu(int mtu)
1248{
1249 switch (mtu) {
1250 case 256: return IB_MTU_256;
1251 case 512: return IB_MTU_512;
1252 case 1024: return IB_MTU_1024;
1253 case 2048: return IB_MTU_2048;
1254 case 4096: return IB_MTU_4096;
1255 default: return -1;
1256 }
1257}
1258
1259static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1260{
1261 switch (mtu) {
1262 case IB_MTU_256: return 256;
1263 case IB_MTU_512: return 512;
1264 case IB_MTU_1024: return 1024;
1265 case IB_MTU_2048: return 2048;
1266 case IB_MTU_4096: return 4096;
1267 default: return -1;
1268 }
1269}
1270
1271static ssize_t show_port_ib_mtu(struct device *dev,
1272 struct device_attribute *attr,
1273 char *buf)
1274{
1275 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1276 port_mtu_attr);
1277 struct mlx4_dev *mdev = info->dev;
1278
1279 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1280 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1281
1282 sprintf(buf, "%d\n",
1283 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1284 return strlen(buf);
1285}
1286
1287static ssize_t set_port_ib_mtu(struct device *dev,
1288 struct device_attribute *attr,
1289 const char *buf, size_t count)
1290{
1291 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1292 port_mtu_attr);
1293 struct mlx4_dev *mdev = info->dev;
1294 struct mlx4_priv *priv = mlx4_priv(mdev);
1295 int err, port, mtu, ibta_mtu = -1;
1296
1297 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1298 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1299 return -EINVAL;
1300 }
1301
618fad95
DB		 1302 err = kstrtoint(buf, 0, &mtu);
1303 if (!err)
096335b3
OG		 1304 ibta_mtu = int_to_ibta_mtu(mtu);
1305
618fad95 1306 if (err || ibta_mtu < 0) {
096335b3
OG		 1307 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1308 return -EINVAL;
1309 }
1310
1311 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1312
1313 mlx4_stop_sense(mdev);
1314 mutex_lock(&priv->port_mutex);
1315 mlx4_unregister_device(mdev);
1316 for (port = 1; port <= mdev->caps.num_ports; port++) {
1317 mlx4_CLOSE_PORT(mdev, port);
6634961c 1318 err = mlx4_SET_PORT(mdev, port, -1);
096335b3 1319 if (err) {
1a91de28
JP		 1320 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1321 port);
096335b3
OG		 1322 goto err_set_port;
1323 }
1324 }
1325 err = mlx4_register_device(mdev);
1326err_set_port:
1327 mutex_unlock(&priv->port_mutex);
1328 mlx4_start_sense(mdev);
1329 return err ? err : count;
1330}
1331
e57968a1
MS		 1332/* bond for multi-function device */
1333#define MAX_MF_BOND_ALLOWED_SLAVES 63
1334static int mlx4_mf_bond(struct mlx4_dev *dev)
1335{
1336 int err = 0;
00ada910 1337 int nvfs;
e57968a1
MS		 1338 struct mlx4_slaves_pport slaves_port1;
1339 struct mlx4_slaves_pport slaves_port2;
1340 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1341
1342 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1343 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1344 bitmap_and(slaves_port_1_2,
1345 slaves_port1.slaves, slaves_port2.slaves,
1346 dev->persist->num_vfs + 1);
1347
1348 /* only single port vfs are allowed */
1349 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1350 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1351 return -EINVAL;
1352 }
1353
00ada910
MS		 1354 /* number of virtual functions is number of total functions minus one
1355 * physical function for each port.
1356 */
1357 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1358 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1359
e57968a1 1360 /* limit on maximum allowed VFs */
00ada910
MS		 1361 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1362 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1363 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
e57968a1 1364 return -EINVAL;
00ada910 1365 }
e57968a1
MS		 1366
1367 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1368 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1369 return -EINVAL;
1370 }
1371
1372 err = mlx4_bond_mac_table(dev);
1373 if (err)
1374 return err;
1375 err = mlx4_bond_vlan_table(dev);
1376 if (err)
1377 goto err1;
1378 err = mlx4_bond_fs_rules(dev);
1379 if (err)
1380 goto err2;
1381
1382 return 0;
1383err2:
1384 (void)mlx4_unbond_vlan_table(dev);
1385err1:
1386 (void)mlx4_unbond_mac_table(dev);
1387 return err;
1388}
1389
1390static int mlx4_mf_unbond(struct mlx4_dev *dev)
1391{
1392 int ret, ret1;
1393
1394 ret = mlx4_unbond_fs_rules(dev);
1395 if (ret)
1396 mlx4_warn(dev, "multifunction unbond for flow rules failedi (%d)\n", ret);
1397 ret1 = mlx4_unbond_mac_table(dev);
1398 if (ret1) {
1399 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1400 ret = ret1;
1401 }
1402 ret1 = mlx4_unbond_vlan_table(dev);
1403 if (ret1) {
1404 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1405 ret = ret1;
1406 }
1407 return ret;
1408}
1409
53f33ae2
MS		 1410int mlx4_bond(struct mlx4_dev *dev)
1411{
1412 int ret = 0;
1413 struct mlx4_priv *priv = mlx4_priv(dev);
1414
1415 mutex_lock(&priv->bond_mutex);
1416
e57968a1 1417 if (!mlx4_is_bonded(dev)) {
53f33ae2 1418 ret = mlx4_do_bond(dev, true);
e57968a1
MS		 1419 if (ret)
1420 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1421 if (!ret && mlx4_is_master(dev)) {
1422 ret = mlx4_mf_bond(dev);
1423 if (ret) {
1424 mlx4_err(dev, "bond for multifunction failed\n");
1425 mlx4_do_bond(dev, false);
1426 }
1427 }
1428 }
53f33ae2
MS		 1429
1430 mutex_unlock(&priv->bond_mutex);
e57968a1 1431 if (!ret)
53f33ae2 1432 mlx4_dbg(dev, "Device is bonded\n");
e57968a1 1433
53f33ae2
MS		 1434 return ret;
1435}
1436EXPORT_SYMBOL_GPL(mlx4_bond);
1437
1438int mlx4_unbond(struct mlx4_dev *dev)
1439{
1440 int ret = 0;
1441 struct mlx4_priv *priv = mlx4_priv(dev);
1442
1443 mutex_lock(&priv->bond_mutex);
1444
e57968a1
MS		 1445 if (mlx4_is_bonded(dev)) {
1446 int ret2 = 0;
1447
53f33ae2 1448 ret = mlx4_do_bond(dev, false);
e57968a1
MS		 1449 if (ret)
1450 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1451 if (mlx4_is_master(dev))
1452 ret2 = mlx4_mf_unbond(dev);
1453 if (ret2) {
1454 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1455 ret = ret2;
1456 }
1457 }
53f33ae2
MS		 1458
1459 mutex_unlock(&priv->bond_mutex);
e57968a1 1460 if (!ret)
53f33ae2 1461 mlx4_dbg(dev, "Device is unbonded\n");
e57968a1 1462
53f33ae2
MS		 1463 return ret;
1464}
1465EXPORT_SYMBOL_GPL(mlx4_unbond);
1466
1467
1468int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1469{
1470 u8 port1 = v2p->port1;
1471 u8 port2 = v2p->port2;
1472 struct mlx4_priv *priv = mlx4_priv(dev);
1473 int err;
1474
1475 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
423b3aec 1476 return -EOPNOTSUPP;
53f33ae2
MS		 1477
1478 mutex_lock(&priv->bond_mutex);
1479
1480 /* zero means keep current mapping for this port */
1481 if (port1 == 0)
1482 port1 = priv->v2p.port1;
1483 if (port2 == 0)
1484 port2 = priv->v2p.port2;
1485
1486 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1487 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1488 (port1 == 2 && port2 == 1)) {
1489 /* besides boundary checks cross mapping makes
1490 * no sense and therefore not allowed */
1491 err = -EINVAL;
1492 } else if ((port1 == priv->v2p.port1) &&
1493 (port2 == priv->v2p.port2)) {
1494 err = 0;
1495 } else {
1496 err = mlx4_virt2phy_port_map(dev, port1, port2);
1497 if (!err) {
1498 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1499 port1, port2);
1500 priv->v2p.port1 = port1;
1501 priv->v2p.port2 = port2;
1502 } else {
1503 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1504 }
1505 }
1506
1507 mutex_unlock(&priv->bond_mutex);
1508 return err;
1509}
1510EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1511
e8f9b2ed 1512static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 1513{
1514 struct mlx4_priv *priv = mlx4_priv(dev);
1515 int err;
1516
1517 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 1518 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1519 if (!priv->fw.fw_icm) {
1a91de28 1520 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
225c7b1f
RD		 1521 return -ENOMEM;
1522 }
1523
1524 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1525 if (err) {
1a91de28 1526 mlx4_err(dev, "MAP_FA command failed, aborting\n");
225c7b1f
RD		 1527 goto err_free;
1528 }
1529
1530 err = mlx4_RUN_FW(dev);
1531 if (err) {
1a91de28 1532 mlx4_err(dev, "RUN_FW command failed, aborting\n");
225c7b1f
RD		 1533 goto err_unmap_fa;
1534 }
1535
1536 return 0;
1537
1538err_unmap_fa:
1539 mlx4_UNMAP_FA(dev);
1540
1541err_free:
5b0bf5e2 1542 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1543 return err;
1544}
1545
e8f9b2ed
RD		 1546static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1547 int cmpt_entry_sz)
225c7b1f
RD		 1548{
1549 struct mlx4_priv *priv = mlx4_priv(dev);
1550 int err;
ab9c17a0 1551 int num_eqs;
225c7b1f
RD		 1552
1553 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1554 cmpt_base +
1555 ((u64) (MLX4_CMPT_TYPE_QP *
1556 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1557 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1558 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1559 0, 0);
225c7b1f
RD		 1560 if (err)
1561 goto err;
1562
1563 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1564 cmpt_base +
1565 ((u64) (MLX4_CMPT_TYPE_SRQ *
1566 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1567 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1568 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1569 if (err)
1570 goto err_qp;
1571
1572 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1573 cmpt_base +
1574 ((u64) (MLX4_CMPT_TYPE_CQ *
1575 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1576 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1577 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1578 if (err)
1579 goto err_srq;
1580
7ae0e400 1581 num_eqs = dev->phys_caps.num_phys_eqs;
225c7b1f
RD		 1582 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1583 cmpt_base +
1584 ((u64) (MLX4_CMPT_TYPE_EQ *
1585 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1586 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1587 if (err)
1588 goto err_cq;
1589
1590 return 0;
1591
1592err_cq:
1593 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1594
1595err_srq:
1596 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1597
1598err_qp:
1599 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1600
1601err:
1602 return err;
1603}
1604
3d73c288
RD		 1605static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1606 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1607{
1608 struct mlx4_priv *priv = mlx4_priv(dev);
1609 u64 aux_pages;
ab9c17a0 1610 int num_eqs;
225c7b1f
RD		 1611 int err;
1612
1613 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1614 if (err) {
1a91de28 1615 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
225c7b1f
RD		 1616 return err;
1617 }
1618
1a91de28 1619 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
225c7b1f
RD		 1620 (unsigned long long) icm_size >> 10,
1621 (unsigned long long) aux_pages << 2);
1622
1623 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1624 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f 1625 if (!priv->fw.aux_icm) {
1a91de28 1626 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
225c7b1f
RD		 1627 return -ENOMEM;
1628 }
1629
1630 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1631 if (err) {
1a91de28 1632 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
225c7b1f
RD		 1633 goto err_free_aux;
1634 }
1635
1636 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1637 if (err) {
1a91de28 1638 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
225c7b1f
RD		 1639 goto err_unmap_aux;
1640 }
1641
ab9c17a0 1642
7ae0e400 1643 num_eqs = dev->phys_caps.num_phys_eqs;
fa0681d2
RD		 1644 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1645 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1646 num_eqs, num_eqs, 0, 0);
225c7b1f 1647 if (err) {
1a91de28 1648 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
225c7b1f
RD		 1649 goto err_unmap_cmpt;
1650 }
1651
d7bb58fb
JM		 1652 /*
1653 * Reserved MTT entries must be aligned up to a cacheline
1654 * boundary, since the FW will write to them, while the driver
1655 * writes to all other MTT entries. (The variable
1656 * dev->caps.mtt_entry_sz below is really the MTT segment
1657 * size, not the raw entry size)
1658 */
1659 dev->caps.reserved_mtts =
1660 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1661 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1662
225c7b1f
RD		 1663 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1664 init_hca->mtt_base,
1665 dev->caps.mtt_entry_sz,
2b8fb286 1666 dev->caps.num_mtts,
5b0bf5e2 1667 dev->caps.reserved_mtts, 1, 0);
225c7b1f 1668 if (err) {
1a91de28 1669 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
225c7b1f
RD		 1670 goto err_unmap_eq;
1671 }
1672
1673 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1674 init_hca->dmpt_base,
1675 dev_cap->dmpt_entry_sz,
1676 dev->caps.num_mpts,
5b0bf5e2 1677 dev->caps.reserved_mrws, 1, 1);
225c7b1f 1678 if (err) {
1a91de28 1679 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
225c7b1f
RD		 1680 goto err_unmap_mtt;
1681 }
1682
1683 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1684 init_hca->qpc_base,
1685 dev_cap->qpc_entry_sz,
1686 dev->caps.num_qps,
93fc9e1b
YP		 1687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1688 0, 0);
225c7b1f 1689 if (err) {
1a91de28 1690 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
225c7b1f
RD		 1691 goto err_unmap_dmpt;
1692 }
1693
1694 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1695 init_hca->auxc_base,
1696 dev_cap->aux_entry_sz,
1697 dev->caps.num_qps,
93fc9e1b
YP		 1698 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1699 0, 0);
225c7b1f 1700 if (err) {
1a91de28 1701 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
225c7b1f
RD		 1702 goto err_unmap_qp;
1703 }
1704
1705 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1706 init_hca->altc_base,
1707 dev_cap->altc_entry_sz,
1708 dev->caps.num_qps,
93fc9e1b
YP		 1709 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1710 0, 0);
225c7b1f 1711 if (err) {
1a91de28 1712 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
225c7b1f
RD		 1713 goto err_unmap_auxc;
1714 }
1715
1716 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1717 init_hca->rdmarc_base,
1718 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1719 dev->caps.num_qps,
93fc9e1b
YP		 1720 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1721 0, 0);
225c7b1f
RD		 1722 if (err) {
1723 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1724 goto err_unmap_altc;
1725 }
1726
1727 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1728 init_hca->cqc_base,
1729 dev_cap->cqc_entry_sz,
1730 dev->caps.num_cqs,
5b0bf5e2 1731 dev->caps.reserved_cqs, 0, 0);
225c7b1f 1732 if (err) {
1a91de28 1733 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
225c7b1f
RD		 1734 goto err_unmap_rdmarc;
1735 }
1736
1737 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1738 init_hca->srqc_base,
1739 dev_cap->srq_entry_sz,
1740 dev->caps.num_srqs,
5b0bf5e2 1741 dev->caps.reserved_srqs, 0, 0);
225c7b1f 1742 if (err) {
1a91de28 1743 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
225c7b1f
RD		 1744 goto err_unmap_cq;
1745 }
1746
1747 /*
0ff1fb65
HHZ		 1748 * For flow steering device managed mode it is required to use
1749 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1750 * required, but for simplicity just map the whole multicast
1751 * group table now. The table isn't very big and it's a lot
1752 * easier than trying to track ref counts.
225c7b1f
RD		 1753 */
1754 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1755 init_hca->mc_base,
1756 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1757 dev->caps.num_mgms + dev->caps.num_amgms,
1758 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1759 0, 0);
225c7b1f 1760 if (err) {
1a91de28 1761 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
225c7b1f
RD		 1762 goto err_unmap_srq;
1763 }
1764
1765 return 0;
1766
1767err_unmap_srq:
1768 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1769
1770err_unmap_cq:
1771 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1772
1773err_unmap_rdmarc:
1774 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1775
1776err_unmap_altc:
1777 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1778
1779err_unmap_auxc:
1780 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1781
1782err_unmap_qp:
1783 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1784
1785err_unmap_dmpt:
1786 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1787
1788err_unmap_mtt:
1789 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1790
1791err_unmap_eq:
fa0681d2 1792 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1793
1794err_unmap_cmpt:
1795 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1796 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1797 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1798 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1799
1800err_unmap_aux:
1801 mlx4_UNMAP_ICM_AUX(dev);
1802
1803err_free_aux:
5b0bf5e2 1804 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1805
1806 return err;
1807}
1808
1809static void mlx4_free_icms(struct mlx4_dev *dev)
1810{
1811 struct mlx4_priv *priv = mlx4_priv(dev);
1812
1813 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1814 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1815 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1816 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1817 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1818 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1819 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1820 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1821 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1822 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1823 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1824 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1825 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1826 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1827
1828 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1829 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1830}
1831
ab9c17a0
JM		 1832static void mlx4_slave_exit(struct mlx4_dev *dev)
1833{
1834 struct mlx4_priv *priv = mlx4_priv(dev);
1835
f3d4c89e 1836 mutex_lock(&priv->cmd.slave_cmd_mutex);
0cd93027
YH		 1837 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1838 MLX4_COMM_TIME))
1a91de28 1839 mlx4_warn(dev, "Failed to close slave function\n");
f3d4c89e 1840 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1841}
1842
c1b43dca
EC		 1843static int map_bf_area(struct mlx4_dev *dev)
1844{
1845 struct mlx4_priv *priv = mlx4_priv(dev);
1846 resource_size_t bf_start;
1847 resource_size_t bf_len;
1848 int err = 0;
1849
3d747473
JM		 1850 if (!dev->caps.bf_reg_size)
1851 return -ENXIO;
1852
872bf2fb 1853 bf_start = pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0 1854 (dev->caps.num_uars << PAGE_SHIFT);
872bf2fb 1855 bf_len = pci_resource_len(dev->persist->pdev, 2) -
ab9c17a0 1856 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1857 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1858 if (!priv->bf_mapping)
1859 err = -ENOMEM;
1860
1861 return err;
1862}
1863
1864static void unmap_bf_area(struct mlx4_dev *dev)
1865{
1866 if (mlx4_priv(dev)->bf_mapping)
1867 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1868}
1869
a5a1d1c2 1870u64 mlx4_read_clock(struct mlx4_dev *dev)
ec693d47
AV		 1871{
1872 u32 clockhi, clocklo, clockhi1;
a5a1d1c2 1873 u64 cycles;
ec693d47
AV		 1874 int i;
1875 struct mlx4_priv *priv = mlx4_priv(dev);
1876
1877 for (i = 0; i < 10; i++) {
1878 clockhi = swab32(readl(priv->clock_mapping));
1879 clocklo = swab32(readl(priv->clock_mapping + 4));
1880 clockhi1 = swab32(readl(priv->clock_mapping));
1881 if (clockhi == clockhi1)
1882 break;
1883 }
1884
1885 cycles = (u64) clockhi << 32 | (u64) clocklo;
1886
1887 return cycles;
1888}
1889EXPORT_SYMBOL_GPL(mlx4_read_clock);
1890
1891
ddd8a6c1
EE		 1892static int map_internal_clock(struct mlx4_dev *dev)
1893{
1894 struct mlx4_priv *priv = mlx4_priv(dev);
1895
1896 priv->clock_mapping =
872bf2fb
YH		 1897 ioremap(pci_resource_start(dev->persist->pdev,
1898 priv->fw.clock_bar) +
ddd8a6c1
EE		 1899 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1900
1901 if (!priv->clock_mapping)
1902 return -ENOMEM;
1903
1904 return 0;
1905}
1906
52033cfb
MB		 1907int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1908 struct mlx4_clock_params *params)
1909{
1910 struct mlx4_priv *priv = mlx4_priv(dev);
1911
1912 if (mlx4_is_slave(dev))
423b3aec 1913 return -EOPNOTSUPP;
52033cfb
MB		 1914
1915 if (!params)
1916 return -EINVAL;
1917
1918 params->bar = priv->fw.clock_bar;
1919 params->offset = priv->fw.clock_offset;
1920 params->size = MLX4_CLOCK_SIZE;
1921
1922 return 0;
1923}
1924EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1925
ddd8a6c1
EE		 1926static void unmap_internal_clock(struct mlx4_dev *dev)
1927{
1928 struct mlx4_priv *priv = mlx4_priv(dev);
1929
1930 if (priv->clock_mapping)
1931 iounmap(priv->clock_mapping);
1932}
1933
225c7b1f
RD		 1934static void mlx4_close_hca(struct mlx4_dev *dev)
1935{
ddd8a6c1 1936 unmap_internal_clock(dev);
c1b43dca 1937 unmap_bf_area(dev);
ab9c17a0
JM		 1938 if (mlx4_is_slave(dev))
1939 mlx4_slave_exit(dev);
1940 else {
1941 mlx4_CLOSE_HCA(dev, 0);
1942 mlx4_free_icms(dev);
a0eacca9
MB		 1943 }
1944}
1945
1946static void mlx4_close_fw(struct mlx4_dev *dev)
1947{
1948 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 1949 mlx4_UNMAP_FA(dev);
1950 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1951 }
1952}
1953
55ad3592
YH		 1954static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1955{
1956#define COMM_CHAN_OFFLINE_OFFSET 0x09
1957
1958 u32 comm_flags;
1959 u32 offline_bit;
1960 unsigned long end;
1961 struct mlx4_priv *priv = mlx4_priv(dev);
1962
1963 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1964 while (time_before(jiffies, end)) {
1965 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1966 MLX4_COMM_CHAN_FLAGS));
1967 offline_bit = (comm_flags &
1968 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1969 if (!offline_bit)
1970 return 0;
4cbe4dac
JM		 1971
1972 /* If device removal has been requested,
1973 * do not continue retrying.
1974 */
1975 if (dev->persist->interface_state &
1976 MLX4_INTERFACE_STATE_NOWAIT)
1977 break;
1978
55ad3592
YH		 1979 /* There are cases as part of AER/Reset flow that PF needs
1980 * around 100 msec to load. We therefore sleep for 100 msec
1981 * to allow other tasks to make use of that CPU during this
1982 * time interval.
1983 */
1984 msleep(100);
1985 }
1986 mlx4_err(dev, "Communication channel is offline.\n");
1987 return -EIO;
1988}
1989
1990static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1991{
1992#define COMM_CHAN_RST_OFFSET 0x1e
1993
1994 struct mlx4_priv *priv = mlx4_priv(dev);
1995 u32 comm_rst;
1996 u32 comm_caps;
1997
1998 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1999 MLX4_COMM_CHAN_CAPS));
2000 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
2001
2002 if (comm_rst)
2003 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2004}
2005
ab9c17a0
JM		 2006static int mlx4_init_slave(struct mlx4_dev *dev)
2007{
2008 struct mlx4_priv *priv = mlx4_priv(dev);
2009 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 2010 int ret_from_reset = 0;
2011 u32 slave_read;
2012 u32 cmd_channel_ver;
2013
97989356 2014 if (atomic_read(&pf_loading)) {
1a91de28 2015 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
97989356
AV		 2016 return -EPROBE_DEFER;
2017 }
2018
f3d4c89e 2019 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2020 priv->cmd.max_cmds = 1;
55ad3592
YH		 2021 if (mlx4_comm_check_offline(dev)) {
2022 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
2023 goto err_offline;
2024 }
2025
2026 mlx4_reset_vf_support(dev);
ab9c17a0
JM		 2027 mlx4_warn(dev, "Sending reset\n");
2028 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
0cd93027 2029 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
ab9c17a0
JM		 2030 /* if we are in the middle of flr the slave will try
2031 * NUM_OF_RESET_RETRIES times before leaving.*/
2032 if (ret_from_reset) {
2033 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1a91de28 2034 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
5efe5355
JM		 2035 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2036 return -EPROBE_DEFER;
ab9c17a0
JM		 2037 } else
2038 goto err;
2039 }
2040
2041 /* check the driver version - the slave I/F revision
2042 * must match the master's */
2043 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
2044 cmd_channel_ver = mlx4_comm_get_version();
2045
2046 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
2047 MLX4_COMM_GET_IF_REV(slave_read)) {
1a91de28 2048 mlx4_err(dev, "slave driver version is not supported by the master\n");
ab9c17a0
JM		 2049 goto err;
2050 }
2051
2052 mlx4_warn(dev, "Sending vhcr0\n");
2053 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
0cd93027 2054 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2055 goto err;
2056 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
0cd93027 2057 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0
JM		 2058 goto err;
2059 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
0cd93027 2060 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2061 goto err;
0cd93027
YH		 2062 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
2063 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
ab9c17a0 2064 goto err;
f3d4c89e
RD		 2065
2066 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 2067 return 0;
2068
2069err:
0cd93027 2070 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
55ad3592 2071err_offline:
f3d4c89e 2072 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 2073 return -EIO;
225c7b1f
RD		 2074}
2075
6634961c
JM		 2076static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2077{
2078 int i;
2079
2080 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 2081 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2082 dev->caps.gid_table_len[i] =
449fc488 2083 mlx4_get_slave_num_gids(dev, 0, i);
b6ffaeff
JM		 2084 else
2085 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 2086 dev->caps.pkey_table_len[i] =
2087 dev->phys_caps.pkey_phys_table_len[i] - 1;
2088 }
2089}
2090
3c439b55
JM		 2091static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2092{
2093 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2094
2095 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2096 i++) {
2097 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2098 break;
2099 }
2100
2101 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2102}
2103
7d077cd3
MB		 2104static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2105{
2106 switch (dmfs_high_steer_mode) {
2107 case MLX4_STEERING_DMFS_A0_DEFAULT:
2108 return "default performance";
2109
2110 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2111 return "dynamic hybrid mode";
2112
2113 case MLX4_STEERING_DMFS_A0_STATIC:
2114 return "performance optimized for limited rule configuration (static)";
2115
2116 case MLX4_STEERING_DMFS_A0_DISABLE:
2117 return "disabled performance optimized steering";
2118
2119 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2120 return "performance optimized steering not supported";
2121
2122 default:
2123 return "Unrecognized mode";
2124 }
2125}
2126
2127#define MLX4_DMFS_A0_STEERING (1UL << 2)
2128
7b8157be
JM		 2129static void choose_steering_mode(struct mlx4_dev *dev,
2130 struct mlx4_dev_cap *dev_cap)
2131{
7d077cd3
MB		 2132 if (mlx4_log_num_mgm_entry_size <= 0) {
2133 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2134 if (dev->caps.dmfs_high_steer_mode ==
2135 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2136 mlx4_err(dev, "DMFS high rate mode not supported\n");
2137 else
2138 dev->caps.dmfs_high_steer_mode =
2139 MLX4_STEERING_DMFS_A0_STATIC;
2140 }
2141 }
2142
2143 if (mlx4_log_num_mgm_entry_size <= 0 &&
3c439b55 2144 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 2145 (!mlx4_is_mfunc(dev) ||
872bf2fb
YH		 2146 (dev_cap->fs_max_num_qp_per_entry >=
2147 (dev->persist->num_vfs + 1))) &&
3c439b55
JM		 2148 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2149 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2150 dev->oper_log_mgm_entry_size =
2151 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 2152 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2153 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2154 dev->caps.fs_log_max_ucast_qp_range_size =
2155 dev_cap->fs_log_max_ucast_qp_range_size;
2156 } else {
7d077cd3
MB		 2157 if (dev->caps.dmfs_high_steer_mode !=
2158 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2159 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
7b8157be
JM		 2160 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2161 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2162 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2163 else {
2164 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2165
2166 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2167 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1a91de28 2168 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
7b8157be 2169 }
3c439b55
JM		 2170 dev->oper_log_mgm_entry_size =
2171 mlx4_log_num_mgm_entry_size > 0 ?
2172 mlx4_log_num_mgm_entry_size :
2173 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 2174 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2175 }
1a91de28 2176 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
3c439b55
JM		 2177 mlx4_steering_mode_str(dev->caps.steering_mode),
2178 dev->oper_log_mgm_entry_size,
2179 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 2180}
2181
7ffdf726
OG		 2182static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2183 struct mlx4_dev_cap *dev_cap)
2184{
2185 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
5eff6dad 2186 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
7ffdf726
OG		 2187 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2188 else
2189 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2190
2191 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2192 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2193}
2194
7d077cd3
MB		 2195static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2196{
2197 int i;
2198 struct mlx4_port_cap port_cap;
2199
2200 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2201 return -EINVAL;
2202
2203 for (i = 1; i <= dev->caps.num_ports; i++) {
2204 if (mlx4_dev_port(dev, i, &port_cap)) {
2205 mlx4_err(dev,
2206 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2207 } else if ((dev->caps.dmfs_high_steer_mode !=
2208 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2209 (port_cap.dmfs_optimized_state ==
2210 !!(dev->caps.dmfs_high_steer_mode ==
2211 MLX4_STEERING_DMFS_A0_DISABLE))) {
2212 mlx4_err(dev,
2213 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2214 dmfs_high_rate_steering_mode_str(
2215 dev->caps.dmfs_high_steer_mode),
2216 (port_cap.dmfs_optimized_state ?
2217 "enabled" : "disabled"));
2218 }
2219 }
2220
2221 return 0;
2222}
2223
a0eacca9 2224static int mlx4_init_fw(struct mlx4_dev *dev)
225c7b1f 2225{
2d928651 2226 struct mlx4_mod_stat_cfg mlx4_cfg;
a0eacca9 2227 int err = 0;
225c7b1f 2228
ab9c17a0
JM		 2229 if (!mlx4_is_slave(dev)) {
2230 err = mlx4_QUERY_FW(dev);
2231 if (err) {
2232 if (err == -EACCES)
1a91de28 2233 mlx4_info(dev, "non-primary physical function, skipping\n");
ab9c17a0 2234 else
1a91de28 2235 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
bef772eb 2236 return err;
ab9c17a0 2237 }
225c7b1f 2238
ab9c17a0
JM		 2239 err = mlx4_load_fw(dev);
2240 if (err) {
1a91de28 2241 mlx4_err(dev, "Failed to start FW, aborting\n");
bef772eb 2242 return err;
ab9c17a0 2243 }
225c7b1f 2244
ab9c17a0
JM		 2245 mlx4_cfg.log_pg_sz_m = 1;
2246 mlx4_cfg.log_pg_sz = 0;
2247 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2248 if (err)
2249 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
a0eacca9 2250 }
2d928651 2251
a0eacca9
MB		 2252 return err;
2253}
2254
2255static int mlx4_init_hca(struct mlx4_dev *dev)
2256{
2257 struct mlx4_priv *priv = mlx4_priv(dev);
2258 struct mlx4_adapter adapter;
2259 struct mlx4_dev_cap dev_cap;
2260 struct mlx4_profile profile;
2261 struct mlx4_init_hca_param init_hca;
2262 u64 icm_size;
2263 struct mlx4_config_dev_params params;
2264 int err;
2265
2266 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2267 err = mlx4_dev_cap(dev, &dev_cap);
2268 if (err) {
1a91de28 2269 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
d0d01250 2270 return err;
ab9c17a0 2271 }
225c7b1f 2272
7b8157be 2273 choose_steering_mode(dev, &dev_cap);
7ffdf726 2274 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 2275
7d077cd3
MB		 2276 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2277 mlx4_is_master(dev))
2278 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2279
8e1a28e8
HHZ		 2280 err = mlx4_get_phys_port_id(dev);
2281 if (err)
2282 mlx4_err(dev, "Fail to get physical port id\n");
2283
6634961c
JM		 2284 if (mlx4_is_master(dev))
2285 mlx4_parav_master_pf_caps(dev);
2286
2599d858
AV		 2287 if (mlx4_low_memory_profile()) {
2288 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2289 profile = low_mem_profile;
2290 } else {
2291 profile = default_profile;
2292 }
0ff1fb65
HHZ		 2293 if (dev->caps.steering_mode ==
2294 MLX4_STEERING_MODE_DEVICE_MANAGED)
2295 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 2296
ab9c17a0
JM		 2297 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2298 &init_hca);
2299 if ((long long) icm_size < 0) {
2300 err = icm_size;
d0d01250 2301 return err;
ab9c17a0 2302 }
225c7b1f 2303
a5bbe892
EC		 2304 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2305
ca3d89a3 2306 if (enable_4k_uar || !dev->persist->num_vfs) {
76e39ccf
EC		 2307 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2308 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2309 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2310 } else {
2311 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2312 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2313 }
85743f1e 2314
e448834e
SM		 2315 init_hca.mw_enabled = 0;
2316 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2317 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2318 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 2319
ab9c17a0
JM		 2320 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2321 if (err)
d0d01250 2322 return err;
225c7b1f 2323
ab9c17a0
JM		 2324 err = mlx4_INIT_HCA(dev, &init_hca);
2325 if (err) {
1a91de28 2326 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
ab9c17a0
JM		 2327 goto err_free_icm;
2328 }
7ae0e400
MB		 2329
2330 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2331 err = mlx4_query_func(dev, &dev_cap);
2332 if (err < 0) {
2333 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
d0d01250 2334 goto err_close;
7ae0e400
MB		 2335 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2336 dev->caps.num_eqs = dev_cap.max_eqs;
2337 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2338 dev->caps.reserved_uars = dev_cap.reserved_uars;
2339 }
2340 }
2341
ddd8a6c1
EE		 2342 /*
2343 * If TS is supported by FW
2344 * read HCA frequency by QUERY_HCA command
2345 */
2346 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2347 memset(&init_hca, 0, sizeof(init_hca));
2348 err = mlx4_QUERY_HCA(dev, &init_hca);
2349 if (err) {
1a91de28 2350 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
ddd8a6c1
EE		 2351 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2352 } else {
2353 dev->caps.hca_core_clock =
2354 init_hca.hca_core_clock;
2355 }
2356
2357 /* In case we got HCA frequency 0 - disable timestamping
2358 * to avoid dividing by zero
2359 */
2360 if (!dev->caps.hca_core_clock) {
2361 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2362 mlx4_err(dev,
1a91de28 2363 "HCA frequency is 0 - timestamping is not supported\n");
ddd8a6c1
EE		 2364 } else if (map_internal_clock(dev)) {
2365 /*
2366 * Map internal clock,
2367 * in case of failure disable timestamping
2368 */
2369 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1a91de28 2370 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
ddd8a6c1
EE		 2371 }
2372 }
7d077cd3
MB		 2373
2374 if (dev->caps.dmfs_high_steer_mode !=
2375 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2376 if (mlx4_validate_optimized_steering(dev))
2377 mlx4_warn(dev, "Optimized steering validation failed\n");
2378
2379 if (dev->caps.dmfs_high_steer_mode ==
2380 MLX4_STEERING_DMFS_A0_DISABLE) {
2381 dev->caps.dmfs_high_rate_qpn_base =
2382 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2383 dev->caps.dmfs_high_rate_qpn_range =
2384 MLX4_A0_STEERING_TABLE_SIZE;
2385 }
2386
4931c6ef
SM		 2387 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2388 dmfs_high_rate_steering_mode_str(
7d077cd3
MB		 2389 dev->caps.dmfs_high_steer_mode));
2390 }
ab9c17a0
JM		 2391 } else {
2392 err = mlx4_init_slave(dev);
2393 if (err) {
5efe5355
JM		 2394 if (err != -EPROBE_DEFER)
2395 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 2396 return err;
ab9c17a0 2397 }
225c7b1f 2398
ab9c17a0
JM		 2399 err = mlx4_slave_cap(dev);
2400 if (err) {
2401 mlx4_err(dev, "Failed to obtain slave caps\n");
2402 goto err_close;
2403 }
225c7b1f
RD		 2404 }
2405
ab9c17a0
JM		 2406 if (map_bf_area(dev))
2407 mlx4_dbg(dev, "Failed to map blue flame area\n");
2408
2409 /*Only the master set the ports, all the rest got it from it.*/
2410 if (!mlx4_is_slave(dev))
2411 mlx4_set_port_mask(dev);
2412
225c7b1f
RD		 2413 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2414 if (err) {
1a91de28 2415 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
bef772eb 2416 goto unmap_bf;
225c7b1f
RD		 2417 }
2418
f8c6455b
SM		 2419 /* Query CONFIG_DEV parameters */
2420 err = mlx4_config_dev_retrieval(dev, &params);
423b3aec 2421 if (err && err != -EOPNOTSUPP) {
f8c6455b
SM		 2422 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2423 } else if (!err) {
2424 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2425 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2426 }
225c7b1f 2427 priv->eq_table.inta_pin = adapter.inta_pin;
31975e27 2428 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
225c7b1f
RD		 2429
2430 return 0;
2431
bef772eb 2432unmap_bf:
ddd8a6c1 2433 unmap_internal_clock(dev);
bef772eb
AY		 2434 unmap_bf_area(dev);
2435
c73c8b1e
EBE		 2436 if (mlx4_is_slave(dev))
2437 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 2438
225c7b1f 2439err_close:
41929ed2
DB		 2440 if (mlx4_is_slave(dev))
2441 mlx4_slave_exit(dev);
2442 else
2443 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 2444
2445err_free_icm:
ab9c17a0
JM		 2446 if (!mlx4_is_slave(dev))
2447 mlx4_free_icms(dev);
225c7b1f 2448
225c7b1f
RD		 2449 return err;
2450}
2451
f2a3f6a3
OG		 2452static int mlx4_init_counters_table(struct mlx4_dev *dev)
2453{
2454 struct mlx4_priv *priv = mlx4_priv(dev);
47d8417f 2455 int nent_pow2;
f2a3f6a3
OG		 2456
2457 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2458 return -ENOENT;
2459
2632d18d
EBE		 2460 if (!dev->caps.max_counters)
2461 return -ENOSPC;
2462
47d8417f
EBE		 2463 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2464 /* reserve last counter index for sink counter */
2465 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2466 nent_pow2 - 1, 0,
2467 nent_pow2 - dev->caps.max_counters + 1);
f2a3f6a3
OG		 2468}
2469
2470static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2471{
efa6bc91
EBE		 2472 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2473 return;
2474
2632d18d
EBE		 2475 if (!dev->caps.max_counters)
2476 return;
2477
f2a3f6a3
OG		 2478 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2479}
2480
6de5f7f6
EBE		 2481static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2482{
2483 struct mlx4_priv *priv = mlx4_priv(dev);
2484 int port;
2485
2486 for (port = 0; port < dev->caps.num_ports; port++)
2487 if (priv->def_counter[port] != -1)
2488 mlx4_counter_free(dev, priv->def_counter[port]);
2489}
2490
2491static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2492{
2493 struct mlx4_priv *priv = mlx4_priv(dev);
2494 int port, err = 0;
2495 u32 idx;
2496
2497 for (port = 0; port < dev->caps.num_ports; port++)
2498 priv->def_counter[port] = -1;
2499
2500 for (port = 0; port < dev->caps.num_ports; port++) {
2501 err = mlx4_counter_alloc(dev, &idx);
2502
2503 if (!err || err == -ENOSPC) {
2504 priv->def_counter[port] = idx;
2505 } else if (err == -ENOENT) {
2506 err = 0;
2507 continue;
178d23e3
OG		 2508 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2509 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2510 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2511 MLX4_SINK_COUNTER_INDEX(dev));
2512 err = 0;
6de5f7f6
EBE		 2513 } else {
2514 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2515 __func__, port + 1, err);
2516 mlx4_cleanup_default_counters(dev);
2517 return err;
2518 }
2519
2520 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2521 __func__, priv->def_counter[port], port + 1);
2522 }
2523
2524 return err;
2525}
2526
ba062d52 2527int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 2528{
2529 struct mlx4_priv *priv = mlx4_priv(dev);
2530
2531 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2532 return -ENOENT;
2533
2534 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
6de5f7f6
EBE		 2535 if (*idx == -1) {
2536 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2537 return -ENOSPC;
2538 }
f2a3f6a3
OG		 2539
2540 return 0;
2541}
ba062d52
JM		 2542
2543int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2544{
2545 u64 out_param;
2546 int err;
2547
2548 if (mlx4_is_mfunc(dev)) {
2549 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
2550 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2551 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2552 if (!err)
2553 *idx = get_param_l(&out_param);
2554
2555 return err;
2556 }
2557 return __mlx4_counter_alloc(dev, idx);
2558}
f2a3f6a3
OG		 2559EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2560
b72ca7e9
EBE		 2561static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2562 u8 counter_index)
2563{
2564 struct mlx4_cmd_mailbox *if_stat_mailbox;
2565 int err;
2566 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2567
2568 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2569 if (IS_ERR(if_stat_mailbox))
2570 return PTR_ERR(if_stat_mailbox);
2571
2572 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2573 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2574 MLX4_CMD_NATIVE);
2575
2576 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2577 return err;
2578}
2579
ba062d52 2580void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 2581{
efa6bc91
EBE		 2582 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2583 return;
2584
6de5f7f6
EBE		 2585 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2586 return;
2587
b72ca7e9
EBE		 2588 __mlx4_clear_if_stat(dev, idx);
2589
7c6d74d2 2590 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 2591 return;
2592}
ba062d52
JM		 2593
2594void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2595{
e7dbeba8 2596 u64 in_param = 0;
ba062d52
JM		 2597
2598 if (mlx4_is_mfunc(dev)) {
2599 set_param_l(&in_param, idx);
2600 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2601 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2602 MLX4_CMD_WRAPPED);
2603 return;
2604 }
2605 __mlx4_counter_free(dev, idx);
2606}
f2a3f6a3
OG		 2607EXPORT_SYMBOL_GPL(mlx4_counter_free);
2608
6de5f7f6
EBE		 2609int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2610{
2611 struct mlx4_priv *priv = mlx4_priv(dev);
2612
2613 return priv->def_counter[port - 1];
2614}
2615EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2616
773af94e
YH		 2617void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2618{
2619 struct mlx4_priv *priv = mlx4_priv(dev);
2620
2621 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2622}
2623EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2624
2625__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2626{
2627 struct mlx4_priv *priv = mlx4_priv(dev);
2628
2629 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2630}
2631EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2632
fb517a4f
YH		 2633void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2634{
2635 struct mlx4_priv *priv = mlx4_priv(dev);
2636 __be64 guid;
2637
2638 /* hw GUID */
2639 if (entry == 0)
2640 return;
2641
2642 get_random_bytes((char *)&guid, sizeof(guid));
2643 guid &= ~(cpu_to_be64(1ULL << 56));
2644 guid |= cpu_to_be64(1ULL << 57);
2645 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2646}
2647
3d73c288 2648static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 2649{
2650 struct mlx4_priv *priv = mlx4_priv(dev);
2651 int err;
7ff93f8b 2652 int port;
9a5aa622 2653 __be32 ib_port_default_caps;
225c7b1f 2654
225c7b1f
RD		 2655 err = mlx4_init_uar_table(dev);
2656 if (err) {
1a91de28 2657 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
5d4de16c 2658 return err;
225c7b1f
RD		 2659 }
2660
2661 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2662 if (err) {
1a91de28 2663 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
225c7b1f
RD		 2664 goto err_uar_table_free;
2665 }
2666
4979d18f 2667 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f 2668 if (!priv->kar) {
1a91de28 2669 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
225c7b1f
RD		 2670 err = -ENOMEM;
2671 goto err_uar_free;
2672 }
2673
2674 err = mlx4_init_pd_table(dev);
2675 if (err) {
1a91de28 2676 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
225c7b1f
RD		 2677 goto err_kar_unmap;
2678 }
2679
012a8ff5
SH		 2680 err = mlx4_init_xrcd_table(dev);
2681 if (err) {
1a91de28 2682 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
012a8ff5
SH		 2683 goto err_pd_table_free;
2684 }
2685
225c7b1f
RD		 2686 err = mlx4_init_mr_table(dev);
2687 if (err) {
1a91de28 2688 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
012a8ff5 2689 goto err_xrcd_table_free;
225c7b1f
RD		 2690 }
2691
fe6f700d
YP		 2692 if (!mlx4_is_slave(dev)) {
2693 err = mlx4_init_mcg_table(dev);
2694 if (err) {
1a91de28 2695 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
fe6f700d
YP		 2696 goto err_mr_table_free;
2697 }
114840c3
JM		 2698 err = mlx4_config_mad_demux(dev);
2699 if (err) {
2700 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2701 goto err_mcg_table_free;
2702 }
fe6f700d
YP		 2703 }
2704
225c7b1f
RD		 2705 err = mlx4_init_eq_table(dev);
2706 if (err) {
1a91de28 2707 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
fe6f700d 2708 goto err_mcg_table_free;
225c7b1f
RD		 2709 }
2710
2711 err = mlx4_cmd_use_events(dev);
2712 if (err) {
1a91de28 2713 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
225c7b1f
RD		 2714 goto err_eq_table_free;
2715 }
2716
2717 err = mlx4_NOP(dev);
2718 if (err) {
08fb1055 2719 if (dev->flags & MLX4_FLAG_MSI_X) {
1a91de28 2720 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
c66fa19c 2721 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
1a91de28 2722 mlx4_warn(dev, "Trying again without MSI-X\n");
08fb1055 2723 } else {
1a91de28 2724 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
c66fa19c 2725 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
225c7b1f 2726 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 2727 }
225c7b1f
RD		 2728
2729 goto err_cmd_poll;
2730 }
2731
2732 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2733
2734 err = mlx4_init_cq_table(dev);
2735 if (err) {
1a91de28 2736 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
225c7b1f
RD		 2737 goto err_cmd_poll;
2738 }
2739
2740 err = mlx4_init_srq_table(dev);
2741 if (err) {
1a91de28 2742 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
225c7b1f
RD		 2743 goto err_cq_table_free;
2744 }
2745
2746 err = mlx4_init_qp_table(dev);
2747 if (err) {
1a91de28 2748 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
225c7b1f
RD		 2749 goto err_srq_table_free;
2750 }
2751
2632d18d
EBE		 2752 if (!mlx4_is_slave(dev)) {
2753 err = mlx4_init_counters_table(dev);
2754 if (err && err != -ENOENT) {
2755 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2756 goto err_qp_table_free;
2757 }
f2a3f6a3
OG		 2758 }
2759
6de5f7f6
EBE		 2760 err = mlx4_allocate_default_counters(dev);
2761 if (err) {
2762 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2763 goto err_counters_table_free;
f2a3f6a3
OG		 2764 }
2765
ab9c17a0
JM		 2766 if (!mlx4_is_slave(dev)) {
2767 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 2768 ib_port_default_caps = 0;
2769 err = mlx4_get_port_ib_caps(dev, port,
2770 &ib_port_default_caps);
2771 if (err)
1a91de28
JP		 2772 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2773 port, err);
ab9c17a0
JM		 2774 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2775
2aca1172
JM		 2776 /* initialize per-slave default ib port capabilities */
2777 if (mlx4_is_master(dev)) {
2778 int i;
2779 for (i = 0; i < dev->num_slaves; i++) {
2780 if (i == mlx4_master_func_num(dev))
2781 continue;
2782 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1a91de28 2783 ib_port_default_caps;
2aca1172
JM		 2784 }
2785 }
2786
096335b3
OG		 2787 if (mlx4_is_mfunc(dev))
2788 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2789 else
2790 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 2791
6634961c
JM		 2792 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2793 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 2794 if (err) {
2795 mlx4_err(dev, "Failed to set port %d, aborting\n",
1a91de28 2796 port);
6de5f7f6 2797 goto err_default_countes_free;
ab9c17a0 2798 }
7ff93f8b
YP		 2799 }
2800 }
2801
225c7b1f
RD		 2802 return 0;
2803
6de5f7f6
EBE		 2804err_default_countes_free:
2805 mlx4_cleanup_default_counters(dev);
2806
f2a3f6a3 2807err_counters_table_free:
2632d18d
EBE		 2808 if (!mlx4_is_slave(dev))
2809 mlx4_cleanup_counters_table(dev);
f2a3f6a3 2810
225c7b1f
RD		 2811err_qp_table_free:
2812 mlx4_cleanup_qp_table(dev);
2813
2814err_srq_table_free:
2815 mlx4_cleanup_srq_table(dev);
2816
2817err_cq_table_free:
2818 mlx4_cleanup_cq_table(dev);
2819
2820err_cmd_poll:
2821 mlx4_cmd_use_polling(dev);
2822
2823err_eq_table_free:
2824 mlx4_cleanup_eq_table(dev);
2825
fe6f700d
YP		 2826err_mcg_table_free:
2827 if (!mlx4_is_slave(dev))
2828 mlx4_cleanup_mcg_table(dev);
2829
ee49bd93 2830err_mr_table_free:
225c7b1f
RD		 2831 mlx4_cleanup_mr_table(dev);
2832
012a8ff5
SH		 2833err_xrcd_table_free:
2834 mlx4_cleanup_xrcd_table(dev);
2835
225c7b1f
RD		 2836err_pd_table_free:
2837 mlx4_cleanup_pd_table(dev);
2838
2839err_kar_unmap:
2840 iounmap(priv->kar);
2841
2842err_uar_free:
2843 mlx4_uar_free(dev, &priv->driver_uar);
2844
2845err_uar_table_free:
2846 mlx4_cleanup_uar_table(dev);
2847 return err;
2848}
2849
de161803
IS		 2850static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2851{
2852 int requested_cpu = 0;
2853 struct mlx4_priv *priv = mlx4_priv(dev);
2854 struct mlx4_eq *eq;
2855 int off = 0;
2856 int i;
2857
2858 if (eqn > dev->caps.num_comp_vectors)
2859 return -EINVAL;
2860
2861 for (i = 1; i < port; i++)
2862 off += mlx4_get_eqs_per_port(dev, i);
2863
2864 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2865
2866 /* Meaning EQs are shared, and this call comes from the second port */
2867 if (requested_cpu < 0)
2868 return 0;
2869
2870 eq = &priv->eq_table.eq[eqn];
2871
2872 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2873 return -ENOMEM;
2874
2875 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2876
2877 return 0;
2878}
2879
e8f9b2ed 2880static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 2881{
2882 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 2883 struct msix_entry *entries;
225c7b1f 2884 int i;
c66fa19c 2885 int port = 0;
225c7b1f
RD		 2886
2887 if (msi_x) {
4762010f 2888 int nreq = min3(dev->caps.num_ports *
2889 (int)num_online_cpus() + 1,
2890 dev->caps.num_eqs - dev->caps.reserved_eqs,
2891 MAX_MSIX);
ab9c17a0 2892
31975e27 2893 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
b8dd786f
YP		 2894 if (!entries)
2895 goto no_msi;
2896
2897 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2898 entries[i].entry = i;
2899
872bf2fb
YH		 2900 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2901 nreq);
66e2f9c1 2902
c66fa19c 2903 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
5bf0da7d 2904 kfree(entries);
225c7b1f 2905 goto no_msi;
0b7ca5a9 2906 }
c66fa19c
MB		 2907 /* 1 is reserved for events (asyncrounous EQ) */
2908 dev->caps.num_comp_vectors = nreq - 1;
2909
2910 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2911 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2912 dev->caps.num_ports);
2913
2914 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2915 if (i == MLX4_EQ_ASYNC)
2916 continue;
2917
2918 priv->eq_table.eq[i].irq =
2919 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2920
85121d6e 2921 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
c66fa19c
MB		 2922 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2923 dev->caps.num_ports);
de161803
IS		 2924 /* We don't set affinity hint when there
2925 * aren't enough EQs
2926 */
c66fa19c
MB		 2927 } else {
2928 set_bit(port,
2929 priv->eq_table.eq[i].actv_ports.ports);
de161803
IS		 2930 if (mlx4_init_affinity_hint(dev, port + 1, i))
2931 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2932 i);
c66fa19c
MB		 2933 }
2934 /* We divide the Eqs evenly between the two ports.
2935 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
2936 * refers to the number of Eqs per port
2937 * (i.e eqs_per_port). Theoretically, we would like to
2938 * write something like (i + 1) % eqs_per_port == 0.
2939 * However, since there's an asynchronous Eq, we have
2940 * to skip over it by comparing this condition to
2941 * !!((i + 1) > MLX4_EQ_ASYNC).
2942 */
2943 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2944 ((i + 1) %
2945 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2946 !!((i + 1) > MLX4_EQ_ASYNC))
2947 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
2948 * everything is shared anyway.
2949 */
2950 port++;
2951 }
225c7b1f
RD		 2952
2953 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2954
2955 kfree(entries);
225c7b1f
RD		 2956 return;
2957 }
2958
2959no_msi:
b8dd786f
YP		 2960 dev->caps.num_comp_vectors = 1;
2961
c66fa19c
MB		 2962 BUG_ON(MLX4_EQ_ASYNC >= 2);
2963 for (i = 0; i < 2; ++i) {
872bf2fb 2964 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
c66fa19c
MB		 2965 if (i != MLX4_EQ_ASYNC) {
2966 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2967 dev->caps.num_ports);
2968 }
2969 }
225c7b1f
RD		 2970}
2971
7ff93f8b 2972static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8 2973{
09d4d087 2974 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2a2336f8 2975 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
09d4d087
JP		 2976 int err;
2977
2978 err = devlink_port_register(devlink, &info->devlink_port, port);
2979 if (err)
2980 return err;
2a2336f8
YP		 2981
2982 info->dev = dev;
2983 info->port = port;
ab9c17a0 2984 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2985 mlx4_init_mac_table(dev, &info->mac_table);
2986 mlx4_init_vlan_table(dev, &info->vlan_table);
111c6094 2987 mlx4_init_roce_gid_table(dev, &info->gid_table);
16a10ffd 2988 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2989 }
7ff93f8b
YP		 2990
2991 sprintf(info->dev_name, "mlx4_port%d", port);
2992 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2993 if (mlx4_is_mfunc(dev))
2994 info->port_attr.attr.mode = S_IRUGO;
2995 else {
2996 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2997 info->port_attr.store = set_port_type;
2998 }
7ff93f8b 2999 info->port_attr.show = show_port_type;
3691c964 3000 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b 3001
872bf2fb 3002 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
7ff93f8b
YP		 3003 if (err) {
3004 mlx4_err(dev, "Failed to create file for port %d\n", port);
09d4d087 3005 devlink_port_unregister(&info->devlink_port);
7ff93f8b
YP		 3006 info->port = -1;
3007 }
3008
096335b3
OG		 3009 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
3010 info->port_mtu_attr.attr.name = info->dev_mtu_name;
3011 if (mlx4_is_mfunc(dev))
3012 info->port_mtu_attr.attr.mode = S_IRUGO;
3013 else {
3014 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
3015 info->port_mtu_attr.store = set_port_ib_mtu;
3016 }
3017 info->port_mtu_attr.show = show_port_ib_mtu;
3018 sysfs_attr_init(&info->port_mtu_attr.attr);
3019
872bf2fb
YH		 3020 err = device_create_file(&dev->persist->pdev->dev,
3021 &info->port_mtu_attr);
096335b3
OG		 3022 if (err) {
3023 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
872bf2fb
YH		 3024 device_remove_file(&info->dev->persist->pdev->dev,
3025 &info->port_attr);
fba12966 3026 devlink_port_unregister(&info->devlink_port);
096335b3
OG		 3027 info->port = -1;
3028 }
3029
7ff93f8b
YP		 3030 return err;
3031}
3032
3033static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
3034{
3035 if (info->port < 0)
3036 return;
3037
872bf2fb
YH		 3038 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
3039 device_remove_file(&info->dev->persist->pdev->dev,
3040 &info->port_mtu_attr);
fba12966
KH		 3041 devlink_port_unregister(&info->devlink_port);
3042
c66fa19c
MB		 3043#ifdef CONFIG_RFS_ACCEL
3044 free_irq_cpu_rmap(info->rmap);
3045 info->rmap = NULL;
3046#endif
2a2336f8
YP		 3047}
3048
b12d93d6
YP		 3049static int mlx4_init_steering(struct mlx4_dev *dev)
3050{
3051 struct mlx4_priv *priv = mlx4_priv(dev);
3052 int num_entries = dev->caps.num_ports;
3053 int i, j;
3054
3055 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
3056 if (!priv->steer)
3057 return -ENOMEM;
3058
45b51365 3059 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 3060 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3061 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
3062 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
3063 }
b12d93d6
YP		 3064 return 0;
3065}
3066
3067static void mlx4_clear_steering(struct mlx4_dev *dev)
3068{
3069 struct mlx4_priv *priv = mlx4_priv(dev);
3070 struct mlx4_steer_index *entry, *tmp_entry;
3071 struct mlx4_promisc_qp *pqp, *tmp_pqp;
3072 int num_entries = dev->caps.num_ports;
3073 int i, j;
3074
3075 for (i = 0; i < num_entries; i++) {
3076 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3077 list_for_each_entry_safe(pqp, tmp_pqp,
3078 &priv->steer[i].promisc_qps[j],
3079 list) {
3080 list_del(&pqp->list);
3081 kfree(pqp);
3082 }
3083 list_for_each_entry_safe(entry, tmp_entry,
3084 &priv->steer[i].steer_entries[j],
3085 list) {
3086 list_del(&entry->list);
3087 list_for_each_entry_safe(pqp, tmp_pqp,
3088 &entry->duplicates,
3089 list) {
3090 list_del(&pqp->list);
3091 kfree(pqp);
3092 }
3093 kfree(entry);
3094 }
3095 }
3096 }
3097 kfree(priv->steer);
3098}
3099
ab9c17a0
JM		 3100static int extended_func_num(struct pci_dev *pdev)
3101{
3102 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3103}
3104
3105#define MLX4_OWNER_BASE 0x8069c
3106#define MLX4_OWNER_SIZE 4
3107
3108static int mlx4_get_ownership(struct mlx4_dev *dev)
3109{
3110 void __iomem *owner;
3111 u32 ret;
3112
872bf2fb 3113 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3114 return -EIO;
3115
872bf2fb
YH		 3116 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3117 MLX4_OWNER_BASE,
ab9c17a0
JM		 3118 MLX4_OWNER_SIZE);
3119 if (!owner) {
3120 mlx4_err(dev, "Failed to obtain ownership bit\n");
3121 return -ENOMEM;
3122 }
3123
3124 ret = readl(owner);
3125 iounmap(owner);
3126 return (int) !!ret;
3127}
3128
3129static void mlx4_free_ownership(struct mlx4_dev *dev)
3130{
3131 void __iomem *owner;
3132
872bf2fb 3133 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 3134 return;
3135
872bf2fb
YH		 3136 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3137 MLX4_OWNER_BASE,
ab9c17a0
JM		 3138 MLX4_OWNER_SIZE);
3139 if (!owner) {
3140 mlx4_err(dev, "Failed to obtain ownership bit\n");
3141 return;
3142 }
3143 writel(0, owner);
3144 msleep(1000);
3145 iounmap(owner);
3146}
3147
a0eacca9
MB		 3148#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3149 !!((flags) & MLX4_FLAG_MASTER))
3150
3151static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
55ad3592 3152 u8 total_vfs, int existing_vfs, int reset_flow)
a0eacca9
MB		 3153{
3154 u64 dev_flags = dev->flags;
da315679 3155 int err = 0;
0beb44b0
CS		 3156 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3157 MLX4_MAX_NUM_VF);
a0eacca9 3158
55ad3592
YH		 3159 if (reset_flow) {
3160 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3161 GFP_KERNEL);
3162 if (!dev->dev_vfs)
3163 goto free_mem;
3164 return dev_flags;
3165 }
3166
da315679
MB		 3167 atomic_inc(&pf_loading);
3168 if (dev->flags & MLX4_FLAG_SRIOV) {
3169 if (existing_vfs != total_vfs) {
3170 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3171 existing_vfs, total_vfs);
3172 total_vfs = existing_vfs;
3173 }
3174 }
3175
3176 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
a0eacca9
MB		 3177 if (NULL == dev->dev_vfs) {
3178 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3179 goto disable_sriov;
da315679
MB		 3180 }
3181
3182 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
0beb44b0
CS		 3183 if (total_vfs > fw_enabled_sriov_vfs) {
3184 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3185 total_vfs, fw_enabled_sriov_vfs);
3186 err = -ENOMEM;
3187 goto disable_sriov;
3188 }
da315679
MB		 3189 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3190 err = pci_enable_sriov(pdev, total_vfs);
3191 }
3192 if (err) {
3193 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3194 err);
3195 goto disable_sriov;
3196 } else {
3197 mlx4_warn(dev, "Running in master mode\n");
3198 dev_flags |= MLX4_FLAG_SRIOV |
3199 MLX4_FLAG_MASTER;
3200 dev_flags &= ~MLX4_FLAG_SLAVE;
872bf2fb 3201 dev->persist->num_vfs = total_vfs;
a0eacca9
MB		 3202 }
3203 return dev_flags;
3204
3205disable_sriov:
da315679 3206 atomic_dec(&pf_loading);
55ad3592 3207free_mem:
872bf2fb 3208 dev->persist->num_vfs = 0;
a0eacca9 3209 kfree(dev->dev_vfs);
5114a04e 3210 dev->dev_vfs = NULL;
a0eacca9
MB		 3211 return dev_flags & ~MLX4_FLAG_MASTER;
3212}
3213
de966c59
MB		 3214enum {
3215 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3216};
3217
3218static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3219 int *nvfs)
3220{
3221 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3222 /* Checking for 64 VFs as a limitation of CX2 */
3223 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3224 requested_vfs >= 64) {
3225 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3226 requested_vfs);
3227 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3228 }
3229 return 0;
3230}
3231
4bfd2e6e
DJ		 3232static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3233{
3234 struct pci_dev *pdev = dev->persist->pdev;
3235 int err = 0;
3236
3237 mutex_lock(&dev->persist->pci_status_mutex);
3238 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3239 err = pci_enable_device(pdev);
3240 if (!err)
3241 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3242 }
3243 mutex_unlock(&dev->persist->pci_status_mutex);
3244
3245 return err;
3246}
3247
3248static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3249{
3250 struct pci_dev *pdev = dev->persist->pdev;
3251
3252 mutex_lock(&dev->persist->pci_status_mutex);
3253 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3254 pci_disable_device(pdev);
3255 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3256 }
3257 mutex_unlock(&dev->persist->pci_status_mutex);
3258}
3259
e1c00e10 3260static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
55ad3592
YH		 3261 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3262 int reset_flow)
225c7b1f 3263{
225c7b1f 3264 struct mlx4_dev *dev;
e1c00e10 3265 unsigned sum = 0;
225c7b1f 3266 int err;
2a2336f8 3267 int port;
e1c00e10 3268 int i;
7ae0e400 3269 struct mlx4_dev_cap *dev_cap = NULL;
bbb07af4 3270 int existing_vfs = 0;
225c7b1f 3271
e1c00e10 3272 dev = &priv->dev;
225c7b1f 3273
b581401e
RD		 3274 INIT_LIST_HEAD(&priv->ctx_list);
3275 spin_lock_init(&priv->ctx_lock);
225c7b1f 3276
7ff93f8b 3277 mutex_init(&priv->port_mutex);
53f33ae2 3278 mutex_init(&priv->bond_mutex);
7ff93f8b 3279
6296883c
YP		 3280 INIT_LIST_HEAD(&priv->pgdir_list);
3281 mutex_init(&priv->pgdir_mutex);
0c5ddb51 3282 spin_lock_init(&priv->cmd.context_lock);
6296883c 3283
c1b43dca
EC		 3284 INIT_LIST_HEAD(&priv->bf_list);
3285 mutex_init(&priv->bf_mutex);
3286
aca7a3ac 3287 dev->rev_id = pdev->revision;
6e7136ed 3288 dev->numa_node = dev_to_node(&pdev->dev);
e1c00e10 3289
ab9c17a0 3290 /* Detect if this device is a virtual function */
839f1243 3291 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 3292 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3293 dev->flags |= MLX4_FLAG_SLAVE;
3294 } else {
3295 /* We reset the device and enable SRIOV only for physical
3296 * devices. Try to claim ownership on the device;
3297 * if already taken, skip -- do not allow multiple PFs */
3298 err = mlx4_get_ownership(dev);
3299 if (err) {
3300 if (err < 0)
e1c00e10 3301 return err;
ab9c17a0 3302 else {
1a91de28 3303 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
e1c00e10 3304 return -EINVAL;
ab9c17a0
JM		 3305 }
3306 }
aca7a3ac 3307
fe6f700d
YP		 3308 atomic_set(&priv->opreq_count, 0);
3309 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3310
ab9c17a0
JM		 3311 /*
3312 * Now reset the HCA before we touch the PCI capabilities or
3313 * attempt a firmware command, since a boot ROM may have left
3314 * the HCA in an undefined state.
3315 */
3316 err = mlx4_reset(dev);
3317 if (err) {
1a91de28 3318 mlx4_err(dev, "Failed to reset HCA, aborting\n");
e1c00e10 3319 goto err_sriov;
ab9c17a0 3320 }
7ae0e400
MB		 3321
3322 if (total_vfs) {
7ae0e400 3323 dev->flags = MLX4_FLAG_MASTER;
da315679
MB		 3324 existing_vfs = pci_num_vf(pdev);
3325 if (existing_vfs)
3326 dev->flags |= MLX4_FLAG_SRIOV;
872bf2fb 3327 dev->persist->num_vfs = total_vfs;
7ae0e400 3328 }
225c7b1f
RD		 3329 }
3330
f6bc11e4
YH		 3331 /* on load remove any previous indication of internal error,
3332 * device is up.
3333 */
3334 dev->persist->state = MLX4_DEVICE_STATE_UP;
3335
ab9c17a0 3336slave_start:
521130d1
EE		 3337 err = mlx4_cmd_init(dev);
3338 if (err) {
1a91de28 3339 mlx4_err(dev, "Failed to init command interface, aborting\n");
ab9c17a0
JM		 3340 goto err_sriov;
3341 }
3342
3343 /* In slave functions, the communication channel must be initialized
3344 * before posting commands. Also, init num_slaves before calling
3345 * mlx4_init_hca */
3346 if (mlx4_is_mfunc(dev)) {
7ae0e400 3347 if (mlx4_is_master(dev)) {
ab9c17a0 3348 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
7ae0e400
MB		 3349
3350 } else {
ab9c17a0 3351 dev->num_slaves = 0;
f356fcbe
JM		 3352 err = mlx4_multi_func_init(dev);
3353 if (err) {
1a91de28 3354 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
ab9c17a0
JM		 3355 goto err_cmd;
3356 }
3357 }
225c7b1f
RD		 3358 }
3359
a0eacca9
MB		 3360 err = mlx4_init_fw(dev);
3361 if (err) {
3362 mlx4_err(dev, "Failed to init fw, aborting.\n");
3363 goto err_mfunc;
3364 }
3365
7ae0e400 3366 if (mlx4_is_master(dev)) {
da315679 3367 /* when we hit the goto slave_start below, dev_cap already initialized */
7ae0e400
MB		 3368 if (!dev_cap) {
3369 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3370
3371 if (!dev_cap) {
3372 err = -ENOMEM;
3373 goto err_fw;
3374 }
3375
3376 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3377 if (err) {
3378 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3379 goto err_fw;
3380 }
3381
de966c59
MB		 3382 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3383 goto err_fw;
3384
7ae0e400 3385 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3386 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3387 total_vfs,
3388 existing_vfs,
3389 reset_flow);
7ae0e400 3390
ed3d2276 3391 mlx4_close_fw(dev);
7ae0e400
MB		 3392 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3393 dev->flags = dev_flags;
3394 if (!SRIOV_VALID_STATE(dev->flags)) {
3395 mlx4_err(dev, "Invalid SRIOV state\n");
3396 goto err_sriov;
3397 }
3398 err = mlx4_reset(dev);
3399 if (err) {
3400 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3401 goto err_sriov;
3402 }
3403 goto slave_start;
3404 }
3405 } else {
3406 /* Legacy mode FW requires SRIOV to be enabled before
3407 * doing QUERY_DEV_CAP, since max_eq's value is different if
3408 * SRIOV is enabled.
3409 */
3410 memset(dev_cap, 0, sizeof(*dev_cap));
3411 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3412 if (err) {
3413 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3414 goto err_fw;
3415 }
de966c59
MB		 3416
3417 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3418 goto err_fw;
7ae0e400
MB		 3419 }
3420 }
3421
225c7b1f 3422 err = mlx4_init_hca(dev);
ab9c17a0
JM		 3423 if (err) {
3424 if (err == -EACCES) {
3425 /* Not primary Physical function
3426 * Running in slave mode */
ffc39f6d 3427 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
a0eacca9
MB		 3428 /* We're not a PF */
3429 if (dev->flags & MLX4_FLAG_SRIOV) {
3430 if (!existing_vfs)
3431 pci_disable_sriov(pdev);
55ad3592 3432 if (mlx4_is_master(dev) && !reset_flow)
a0eacca9
MB		 3433 atomic_dec(&pf_loading);
3434 dev->flags &= ~MLX4_FLAG_SRIOV;
3435 }
3436 if (!mlx4_is_slave(dev))
3437 mlx4_free_ownership(dev);
ab9c17a0
JM		 3438 dev->flags |= MLX4_FLAG_SLAVE;
3439 dev->flags &= ~MLX4_FLAG_MASTER;
3440 goto slave_start;
3441 } else
a0eacca9 3442 goto err_fw;
ab9c17a0
JM		 3443 }
3444
7ae0e400 3445 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
55ad3592
YH		 3446 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3447 existing_vfs, reset_flow);
7ae0e400
MB		 3448
3449 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3450 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3451 dev->flags = dev_flags;
3452 err = mlx4_cmd_init(dev);
3453 if (err) {
3454 /* Only VHCR is cleaned up, so could still
3455 * send FW commands
3456 */
3457 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3458 goto err_close;
3459 }
3460 } else {
3461 dev->flags = dev_flags;
3462 }
3463
3464 if (!SRIOV_VALID_STATE(dev->flags)) {
3465 mlx4_err(dev, "Invalid SRIOV state\n");
3466 goto err_close;
3467 }
3468 }
3469
b912b2f8
EP		 3470 /* check if the device is functioning at its maximum possible speed.
3471 * No return code for this call, just warn the user in case of PCI
3472 * express device capabilities are under-satisfied by the bus.
3473 */
83d3459a
EP		 3474 if (!mlx4_is_slave(dev))
3475 mlx4_check_pcie_caps(dev);
b912b2f8 3476
ab9c17a0
JM		 3477 /* In master functions, the communication channel must be initialized
3478 * after obtaining its address from fw */
3479 if (mlx4_is_master(dev)) {
e1c00e10
MD		 3480 if (dev->caps.num_ports < 2 &&
3481 num_vfs_argc > 1) {
3482 err = -EINVAL;
3483 mlx4_err(dev,
3484 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3485 dev->caps.num_ports);
ab9c17a0
JM		 3486 goto err_close;
3487 }
872bf2fb 3488 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
dd41cc3b 3489
872bf2fb
YH		 3490 for (i = 0;
3491 i < sizeof(dev->persist->nvfs)/
3492 sizeof(dev->persist->nvfs[0]); i++) {
e1c00e10
MD		 3493 unsigned j;
3494
872bf2fb 3495 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
e1c00e10
MD		 3496 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3497 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3498 dev->caps.num_ports;
1ab95d37
MB		 3499 }
3500 }
e1c00e10
MD		 3501
3502 /* In master functions, the communication channel
3503 * must be initialized after obtaining its address from fw
3504 */
3505 err = mlx4_multi_func_init(dev);
3506 if (err) {
3507 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3508 goto err_close;
3509 }
ab9c17a0 3510 }
225c7b1f 3511
b8dd786f
YP		 3512 err = mlx4_alloc_eq_table(dev);
3513 if (err)
ab9c17a0 3514 goto err_master_mfunc;
b8dd786f 3515
c66fa19c 3516 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
730c41d5 3517 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 3518
08fb1055 3519 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 3520 if ((mlx4_is_mfunc(dev)) &&
3521 !(dev->flags & MLX4_FLAG_MSI_X)) {
72b8eaab 3522 err = -EOPNOTSUPP;
1a91de28 3523 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
b12d93d6 3524 goto err_free_eq;
ab9c17a0
JM		 3525 }
3526
3527 if (!mlx4_is_slave(dev)) {
3528 err = mlx4_init_steering(dev);
3529 if (err)
e1c00e10 3530 goto err_disable_msix;
ab9c17a0 3531 }
b12d93d6 3532
6ed63d84
JM		 3533 mlx4_init_quotas(dev);
3534
225c7b1f 3535 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 3536 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3537 !mlx4_is_mfunc(dev)) {
08fb1055 3538 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1 3539 dev->caps.num_comp_vectors = 1;
08fb1055
MT		 3540 pci_disable_msix(pdev);
3541 err = mlx4_setup_hca(dev);
3542 }
3543
225c7b1f 3544 if (err)
b12d93d6 3545 goto err_steer;
225c7b1f 3546
55ad3592
YH		 3547 /* When PF resources are ready arm its comm channel to enable
3548 * getting commands
3549 */
3550 if (mlx4_is_master(dev)) {
3551 err = mlx4_ARM_COMM_CHANNEL(dev);
3552 if (err) {
3553 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3554 err);
3555 goto err_steer;
3556 }
3557 }
5a0d0a61 3558
7ff93f8b
YP		 3559 for (port = 1; port <= dev->caps.num_ports; port++) {
3560 err = mlx4_init_port_info(dev, port);
3561 if (err)
3562 goto err_port;
3563 }
2a2336f8 3564
53f33ae2
MS		 3565 priv->v2p.port1 = 1;
3566 priv->v2p.port2 = 2;
3567
225c7b1f
RD		 3568 err = mlx4_register_device(dev);
3569 if (err)
7ff93f8b 3570 goto err_port;
225c7b1f 3571
b046ffe5
EP		 3572 mlx4_request_modules(dev);
3573
27bf91d6
YP		 3574 mlx4_sense_init(dev);
3575 mlx4_start_sense(dev);
3576
befdf897 3577 priv->removed = 0;
225c7b1f 3578
55ad3592 3579 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3580 atomic_dec(&pf_loading);
3581
da315679 3582 kfree(dev_cap);
225c7b1f
RD		 3583 return 0;
3584
7ff93f8b 3585err_port:
b4f77264 3586 for (--port; port >= 1; --port)
7ff93f8b
YP		 3587 mlx4_cleanup_port_info(&priv->port[port]);
3588
6de5f7f6 3589 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3590 if (!mlx4_is_slave(dev))
3591 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 3592 mlx4_cleanup_qp_table(dev);
3593 mlx4_cleanup_srq_table(dev);
3594 mlx4_cleanup_cq_table(dev);
3595 mlx4_cmd_use_polling(dev);
3596 mlx4_cleanup_eq_table(dev);
fe6f700d 3597 mlx4_cleanup_mcg_table(dev);
225c7b1f 3598 mlx4_cleanup_mr_table(dev);
012a8ff5 3599 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 3600 mlx4_cleanup_pd_table(dev);
3601 mlx4_cleanup_uar_table(dev);
3602
b12d93d6 3603err_steer:
ab9c17a0
JM		 3604 if (!mlx4_is_slave(dev))
3605 mlx4_clear_steering(dev);
b12d93d6 3606
e1c00e10
MD		 3607err_disable_msix:
3608 if (dev->flags & MLX4_FLAG_MSI_X)
3609 pci_disable_msix(pdev);
3610
b8dd786f
YP		 3611err_free_eq:
3612 mlx4_free_eq_table(dev);
3613
ab9c17a0 3614err_master_mfunc:
772103e6
JM		 3615 if (mlx4_is_master(dev)) {
3616 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 3617 mlx4_multi_func_cleanup(dev);
772103e6 3618 }
ab9c17a0 3619
c73c8b1e
EBE		 3620 if (mlx4_is_slave(dev))
3621 mlx4_slave_destroy_special_qp_cap(dev);
b38f2879 3622
225c7b1f
RD		 3623err_close:
3624 mlx4_close_hca(dev);
3625
a0eacca9
MB		 3626err_fw:
3627 mlx4_close_fw(dev);
3628
ab9c17a0
JM		 3629err_mfunc:
3630 if (mlx4_is_slave(dev))
3631 mlx4_multi_func_cleanup(dev);
3632
225c7b1f 3633err_cmd:
ffc39f6d 3634 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
225c7b1f 3635
ab9c17a0 3636err_sriov:
55ad3592 3637 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
ab9c17a0 3638 pci_disable_sriov(pdev);
55ad3592
YH		 3639 dev->flags &= ~MLX4_FLAG_SRIOV;
3640 }
ab9c17a0 3641
55ad3592 3642 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
e1a5ddc5
AV		 3643 atomic_dec(&pf_loading);
3644
1ab95d37
MB		 3645 kfree(priv->dev.dev_vfs);
3646
e1c00e10
MD		 3647 if (!mlx4_is_slave(dev))
3648 mlx4_free_ownership(dev);
3649
7ae0e400 3650 kfree(dev_cap);
e1c00e10
MD		 3651 return err;
3652}
3653
3654static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3655 struct mlx4_priv *priv)
3656{
3657 int err;
3658 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3659 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3660 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3661 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3662 unsigned total_vfs = 0;
3663 unsigned int i;
3664
3665 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3666
4bfd2e6e 3667 err = mlx4_pci_enable_device(&priv->dev);
e1c00e10
MD		 3668 if (err) {
3669 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3670 return err;
3671 }
3672
3673 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
3674 * per port, we must limit the number of VFs to 63 (since their are
3675 * 128 MACs)
3676 */
3677 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc;
3678 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3679 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3680 if (nvfs[i] < 0) {
3681 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3682 err = -EINVAL;
3683 goto err_disable_pdev;
3684 }
3685 }
3686 for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc;
3687 i++) {
3688 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3689 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3690 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3691 err = -EINVAL;
3692 goto err_disable_pdev;
3693 }
3694 }
0beb44b0 3695 if (total_vfs > MLX4_MAX_NUM_VF) {
e1c00e10 3696 dev_err(&pdev->dev,
0beb44b0
CS		 3697 "Requested more VF's (%d) than allowed by hw (%d)\n",
3698 total_vfs, MLX4_MAX_NUM_VF);
e1c00e10
MD		 3699 err = -EINVAL;
3700 goto err_disable_pdev;
3701 }
3702
3703 for (i = 0; i < MLX4_MAX_PORTS; i++) {
0beb44b0 3704 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
e1c00e10 3705 dev_err(&pdev->dev,
0beb44b0 3706 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
e1c00e10 3707 nvfs[i] + nvfs[2], i + 1,
0beb44b0 3708 MLX4_MAX_NUM_VF_P_PORT);
e1c00e10
MD		 3709 err = -EINVAL;
3710 goto err_disable_pdev;
3711 }
3712 }
3713
3714 /* Check for BARs. */
3715 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3716 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3717 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3718 pci_dev_data, pci_resource_flags(pdev, 0));
3719 err = -ENODEV;
3720 goto err_disable_pdev;
3721 }
3722 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3723 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3724 err = -ENODEV;
3725 goto err_disable_pdev;
3726 }
3727
3728 err = pci_request_regions(pdev, DRV_NAME);
3729 if (err) {
3730 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3731 goto err_disable_pdev;
3732 }
3733
3734 pci_set_master(pdev);
3735
3736 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3737 if (err) {
3738 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3739 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3740 if (err) {
3741 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3742 goto err_release_regions;
3743 }
3744 }
3745 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3746 if (err) {
3747 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3748 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3749 if (err) {
3750 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3751 goto err_release_regions;
3752 }
3753 }
3754
3755 /* Allow large DMA segments, up to the firmware limit of 1 GB */
3756 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3757 /* Detect if this device is a virtual function */
3758 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3759 /* When acting as pf, we normally skip vfs unless explicitly
3760 * requested to probe them.
3761 */
3762 if (total_vfs) {
3763 unsigned vfs_offset = 0;
3764
3765 for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) &&
3766 vfs_offset + nvfs[i] < extended_func_num(pdev);
3767 vfs_offset += nvfs[i], i++)
3768 ;
3769 if (i == sizeof(nvfs)/sizeof(nvfs[0])) {
3770 err = -ENODEV;
3771 goto err_release_regions;
3772 }
3773 if ((extended_func_num(pdev) - vfs_offset)
3774 > prb_vf[i]) {
3775 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3776 extended_func_num(pdev));
3777 err = -ENODEV;
3778 goto err_release_regions;
3779 }
3780 }
3781 }
3782
ad9a0bf0 3783 err = mlx4_catas_init(&priv->dev);
e1c00e10
MD		 3784 if (err)
3785 goto err_release_regions;
ad9a0bf0 3786
55ad3592 3787 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
ad9a0bf0
YH		 3788 if (err)
3789 goto err_catas;
3790
e1c00e10 3791 return 0;
225c7b1f 3792
ad9a0bf0
YH		 3793err_catas:
3794 mlx4_catas_end(&priv->dev);
3795
a01df0fe
RD		 3796err_release_regions:
3797 pci_release_regions(pdev);
225c7b1f
RD		 3798
3799err_disable_pdev:
4bfd2e6e 3800 mlx4_pci_disable_device(&priv->dev);
225c7b1f
RD		 3801 return err;
3802}
3803
b2facd95
JP		 3804static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3805 enum devlink_port_type port_type)
3806{
3807 struct mlx4_port_info *info = container_of(devlink_port,
3808 struct mlx4_port_info,
3809 devlink_port);
3810 enum mlx4_port_type mlx4_port_type;
3811
3812 switch (port_type) {
3813 case DEVLINK_PORT_TYPE_AUTO:
3814 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3815 break;
3816 case DEVLINK_PORT_TYPE_ETH:
3817 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3818 break;
3819 case DEVLINK_PORT_TYPE_IB:
3820 mlx4_port_type = MLX4_PORT_TYPE_IB;
3821 break;
3822 default:
3823 return -EOPNOTSUPP;
3824 }
3825
3826 return __set_port_type(info, mlx4_port_type);
3827}
3828
3829static const struct devlink_ops mlx4_devlink_ops = {
3830 .port_type_set = mlx4_devlink_port_type_set,
3831};
3832
1dd06ae8 3833static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 3834{
09d4d087 3835 struct devlink *devlink;
befdf897
WY		 3836 struct mlx4_priv *priv;
3837 struct mlx4_dev *dev;
e1c00e10 3838 int ret;
befdf897 3839
0a645e80 3840 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 3841
b2facd95 3842 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
09d4d087 3843 if (!devlink)
befdf897 3844 return -ENOMEM;
09d4d087 3845 priv = devlink_priv(devlink);
befdf897
WY		 3846
3847 dev = &priv->dev;
872bf2fb
YH		 3848 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3849 if (!dev->persist) {
09d4d087
JP		 3850 ret = -ENOMEM;
3851 goto err_devlink_free;
872bf2fb
YH		 3852 }
3853 dev->persist->pdev = pdev;
3854 dev->persist->dev = dev;
3855 pci_set_drvdata(pdev, dev->persist);
befdf897 3856 priv->pci_dev_data = id->driver_data;
f6bc11e4 3857 mutex_init(&dev->persist->device_state_mutex);
c69453e2 3858 mutex_init(&dev->persist->interface_state_mutex);
4bfd2e6e 3859 mutex_init(&dev->persist->pci_status_mutex);
befdf897 3860
09d4d087
JP		 3861 ret = devlink_register(devlink, &pdev->dev);
3862 if (ret)
3863 goto err_persist_free;
3864
e1c00e10 3865 ret = __mlx4_init_one(pdev, id->driver_data, priv);
09d4d087
JP		 3866 if (ret)
3867 goto err_devlink_unregister;
2ba5fbd6 3868
09d4d087
JP		 3869 pci_save_state(pdev);
3870 return 0;
3871
3872err_devlink_unregister:
3873 devlink_unregister(devlink);
3874err_persist_free:
3875 kfree(dev->persist);
3876err_devlink_free:
3877 devlink_free(devlink);
e1c00e10 3878 return ret;
3d73c288
RD		 3879}
3880
dd0eefe3
YH		 3881static void mlx4_clean_dev(struct mlx4_dev *dev)
3882{
3883 struct mlx4_dev_persistent *persist = dev->persist;
3884 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592 3885 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
dd0eefe3
YH		 3886
3887 memset(priv, 0, sizeof(*priv));
3888 priv->dev.persist = persist;
55ad3592 3889 priv->dev.flags = flags;
dd0eefe3
YH		 3890}
3891
e1c00e10 3892static void mlx4_unload_one(struct pci_dev *pdev)
225c7b1f 3893{
872bf2fb
YH		 3894 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3895 struct mlx4_dev *dev = persist->dev;
225c7b1f 3896 struct mlx4_priv *priv = mlx4_priv(dev);
befdf897 3897 int pci_dev_data;
dd0eefe3 3898 int p, i;
225c7b1f 3899
befdf897
WY		 3900 if (priv->removed)
3901 return;
225c7b1f 3902
dd0eefe3
YH		 3903 /* saving current ports type for further use */
3904 for (i = 0; i < dev->caps.num_ports; i++) {
3905 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3906 dev->persist->curr_port_poss_type[i] = dev->caps.
3907 possible_type[i + 1];
3908 }
3909
befdf897 3910 pci_dev_data = priv->pci_dev_data;
225c7b1f 3911
befdf897
WY		 3912 mlx4_stop_sense(dev);
3913 mlx4_unregister_device(dev);
225c7b1f 3914
befdf897
WY		 3915 for (p = 1; p <= dev->caps.num_ports; p++) {
3916 mlx4_cleanup_port_info(&priv->port[p]);
3917 mlx4_CLOSE_PORT(dev, p);
3918 }
3919
3920 if (mlx4_is_master(dev))
3921 mlx4_free_resource_tracker(dev,
3922 RES_TR_FREE_SLAVES_ONLY);
3923
6de5f7f6 3924 mlx4_cleanup_default_counters(dev);
2632d18d
EBE		 3925 if (!mlx4_is_slave(dev))
3926 mlx4_cleanup_counters_table(dev);
befdf897
WY		 3927 mlx4_cleanup_qp_table(dev);
3928 mlx4_cleanup_srq_table(dev);
3929 mlx4_cleanup_cq_table(dev);
3930 mlx4_cmd_use_polling(dev);
3931 mlx4_cleanup_eq_table(dev);
3932 mlx4_cleanup_mcg_table(dev);
3933 mlx4_cleanup_mr_table(dev);
3934 mlx4_cleanup_xrcd_table(dev);
3935 mlx4_cleanup_pd_table(dev);
225c7b1f 3936
befdf897
WY		 3937 if (mlx4_is_master(dev))
3938 mlx4_free_resource_tracker(dev,
3939 RES_TR_FREE_STRUCTS_ONLY);
47605df9 3940
befdf897
WY		 3941 iounmap(priv->kar);
3942 mlx4_uar_free(dev, &priv->driver_uar);
3943 mlx4_cleanup_uar_table(dev);
3944 if (!mlx4_is_slave(dev))
3945 mlx4_clear_steering(dev);
3946 mlx4_free_eq_table(dev);
3947 if (mlx4_is_master(dev))
3948 mlx4_multi_func_cleanup(dev);
3949 mlx4_close_hca(dev);
a0eacca9 3950 mlx4_close_fw(dev);
befdf897
WY		 3951 if (mlx4_is_slave(dev))
3952 mlx4_multi_func_cleanup(dev);
ffc39f6d 3953 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
47605df9 3954
befdf897
WY		 3955 if (dev->flags & MLX4_FLAG_MSI_X)
3956 pci_disable_msix(pdev);
befdf897
WY		 3957
3958 if (!mlx4_is_slave(dev))
3959 mlx4_free_ownership(dev);
3960
c73c8b1e 3961 mlx4_slave_destroy_special_qp_cap(dev);
befdf897
WY		 3962 kfree(dev->dev_vfs);
3963
dd0eefe3 3964 mlx4_clean_dev(dev);
befdf897
WY		 3965 priv->pci_dev_data = pci_dev_data;
3966 priv->removed = 1;
3967}
3968
3969static void mlx4_remove_one(struct pci_dev *pdev)
3970{
872bf2fb
YH		 3971 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3972 struct mlx4_dev *dev = persist->dev;
befdf897 3973 struct mlx4_priv *priv = mlx4_priv(dev);
09d4d087 3974 struct devlink *devlink = priv_to_devlink(priv);
55ad3592 3975 int active_vfs = 0;
befdf897 3976
4cbe4dac
JM		 3977 if (mlx4_is_slave(dev))
3978 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3979
c69453e2
YH		 3980 mutex_lock(&persist->interface_state_mutex);
3981 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3982 mutex_unlock(&persist->interface_state_mutex);
3983
55ad3592
YH		 3984 /* Disabling SR-IOV is not allowed while there are active vf's */
3985 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3986 active_vfs = mlx4_how_many_lives_vf(dev);
3987 if (active_vfs) {
3988 pr_warn("Removing PF when there are active VF's !!\n");
3989 pr_warn("Will not disable SR-IOV.\n");
3990 }
3991 }
3992
c69453e2
YH		 3993 /* device marked to be under deletion running now without the lock
3994 * letting other tasks to be terminated
3995 */
3996 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3997 mlx4_unload_one(pdev);
3998 else
3999 mlx4_info(dev, "%s: interface is down\n", __func__);
ad9a0bf0 4000 mlx4_catas_end(dev);
55ad3592
YH		 4001 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
4002 mlx4_warn(dev, "Disabling SR-IOV\n");
4003 pci_disable_sriov(pdev);
4004 }
4005
e1c00e10 4006 pci_release_regions(pdev);
4bfd2e6e 4007 mlx4_pci_disable_device(dev);
09d4d087 4008 devlink_unregister(devlink);
872bf2fb 4009 kfree(dev->persist);
09d4d087 4010 devlink_free(devlink);
225c7b1f
RD		 4011}
4012
dd0eefe3
YH		 4013static int restore_current_port_types(struct mlx4_dev *dev,
4014 enum mlx4_port_type *types,
4015 enum mlx4_port_type *poss_types)
4016{
4017 struct mlx4_priv *priv = mlx4_priv(dev);
4018 int err, i;
4019
4020 mlx4_stop_sense(dev);
4021
4022 mutex_lock(&priv->port_mutex);
4023 for (i = 0; i < dev->caps.num_ports; i++)
4024 dev->caps.possible_type[i + 1] = poss_types[i];
4025 err = mlx4_change_port_types(dev, types);
4026 mlx4_start_sense(dev);
4027 mutex_unlock(&priv->port_mutex);
4028
4029 return err;
4030}
4031
ee49bd93
JM		 4032int mlx4_restart_one(struct pci_dev *pdev)
4033{
872bf2fb
YH		 4034 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4035 struct mlx4_dev *dev = persist->dev;
839f1243 4036 struct mlx4_priv *priv = mlx4_priv(dev);
e1c00e10
MD		 4037 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4038 int pci_dev_data, err, total_vfs;
839f1243
RD		 4039
4040 pci_dev_data = priv->pci_dev_data;
872bf2fb
YH		 4041 total_vfs = dev->persist->num_vfs;
4042 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
e1c00e10
MD		 4043
4044 mlx4_unload_one(pdev);
55ad3592 4045 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
e1c00e10
MD		 4046 if (err) {
4047 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
4048 __func__, pci_name(pdev), err);
4049 return err;
4050 }
4051
dd0eefe3
YH		 4052 err = restore_current_port_types(dev, dev->persist->curr_port_type,
4053 dev->persist->curr_port_poss_type);
4054 if (err)
4055 mlx4_err(dev, "could not restore original port types (%d)\n",
4056 err);
4057
e1c00e10 4058 return err;
ee49bd93
JM		 4059}
4060
c19e4b90
BH		 4061#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
4062#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
4063#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
4064
9baa3c34 4065static const struct pci_device_id mlx4_pci_table[] = {
c19e4b90
BH		 4066 /* MT25408 "Hermon" */
4067 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR), /* SDR */
4068 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR), /* DDR */
4069 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR), /* QDR */
4070 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2), /* DDR Gen2 */
4071 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2), /* QDR Gen2 */
4072 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN), /* EN 10GigE */
4073 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2), /* EN 10GigE Gen2 */
4074 /* MT25458 ConnectX EN 10GBASE-T */
4075 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4076 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2), /* Gen2 */
4077 /* MT26468 ConnectX EN 10GigE PCIe Gen2*/
4078 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4079 /* MT26438 ConnectX EN 40GigE PCIe Gen2 5GT/s */
4080 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4081 /* MT26478 ConnectX2 40GigE PCIe Gen2 */
4082 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4083 /* MT25400 Family [ConnectX-2] */
4084 MLX_VF(0x1002), /* Virtual Function */
ab9c17a0 4085 /* MT27500 Family [ConnectX-3] */
c19e4b90
BH		 4086 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4087 MLX_VF(0x1004), /* Virtual Function */
4088 MLX_GN(0x1005), /* MT27510 Family */
4089 MLX_GN(0x1006), /* MT27511 Family */
4090 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO), /* MT27520 Family */
4091 MLX_GN(0x1008), /* MT27521 Family */
4092 MLX_GN(0x1009), /* MT27530 Family */
4093 MLX_GN(0x100a), /* MT27531 Family */
4094 MLX_GN(0x100b), /* MT27540 Family */
4095 MLX_GN(0x100c), /* MT27541 Family */
4096 MLX_GN(0x100d), /* MT27550 Family */
4097 MLX_GN(0x100e), /* MT27551 Family */
4098 MLX_GN(0x100f), /* MT27560 Family */
4099 MLX_GN(0x1010), /* MT27561 Family */
4100
4101 /*
4102 * See the mellanox_check_broken_intx_masking() quirk when
4103 * adding devices
4104 */
4105
225c7b1f
RD		 4106 { 0, }
4107};
4108
4109MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4110
57dbf29a
KSS		 4111static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4112 pci_channel_state_t state)
4113{
2ba5fbd6
YH		 4114 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4115
4116 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4117 mlx4_enter_error_state(persist);
57dbf29a 4118
2ba5fbd6
YH		 4119 mutex_lock(&persist->interface_state_mutex);
4120 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4121 mlx4_unload_one(pdev);
4122
4123 mutex_unlock(&persist->interface_state_mutex);
4124 if (state == pci_channel_io_perm_failure)
4125 return PCI_ERS_RESULT_DISCONNECT;
4126
4bfd2e6e 4127 mlx4_pci_disable_device(persist->dev);
2ba5fbd6 4128 return PCI_ERS_RESULT_NEED_RESET;
57dbf29a
KSS		 4129}
4130
4131static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4132{
2ba5fbd6
YH		 4133 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4134 struct mlx4_dev *dev = persist->dev;
c12833ac 4135 int err;
97a5221f 4136
2ba5fbd6 4137 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4bfd2e6e 4138 err = mlx4_pci_enable_device(dev);
c12833ac
DJ		 4139 if (err) {
4140 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
2ba5fbd6
YH		 4141 return PCI_ERS_RESULT_DISCONNECT;
4142 }
4143
4144 pci_set_master(pdev);
4145 pci_restore_state(pdev);
4146 pci_save_state(pdev);
c12833ac
DJ		 4147 return PCI_ERS_RESULT_RECOVERED;
4148}
4149
4150static void mlx4_pci_resume(struct pci_dev *pdev)
4151{
4152 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4153 struct mlx4_dev *dev = persist->dev;
4154 struct mlx4_priv *priv = mlx4_priv(dev);
4155 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4156 int total_vfs;
4157 int err;
2ba5fbd6 4158
c12833ac 4159 mlx4_err(dev, "%s was called\n", __func__);
2ba5fbd6
YH		 4160 total_vfs = dev->persist->num_vfs;
4161 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4162
4163 mutex_lock(&persist->interface_state_mutex);
4164 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
c12833ac 4165 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
55ad3592 4166 priv, 1);
c12833ac
DJ		 4167 if (err) {
4168 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4169 __func__, err);
2ba5fbd6
YH		 4170 goto end;
4171 }
4172
c12833ac 4173 err = restore_current_port_types(dev, dev->persist->
2ba5fbd6
YH		 4174 curr_port_type, dev->persist->
4175 curr_port_poss_type);
c12833ac
DJ		 4176 if (err)
4177 mlx4_err(dev, "could not restore original port types (%d)\n", err);
2ba5fbd6
YH		 4178 }
4179end:
4180 mutex_unlock(&persist->interface_state_mutex);
57dbf29a 4181
57dbf29a
KSS		 4182}
4183
2ba5fbd6
YH		 4184static void mlx4_shutdown(struct pci_dev *pdev)
4185{
4186 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4187
4188 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4189 mutex_lock(&persist->interface_state_mutex);
b4353708 4190 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
2ba5fbd6
YH		 4191 mlx4_unload_one(pdev);
4192 mutex_unlock(&persist->interface_state_mutex);
4193}
4194
3646f0e5 4195static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 4196 .error_detected = mlx4_pci_err_detected,
4197 .slot_reset = mlx4_pci_slot_reset,
c12833ac 4198 .resume = mlx4_pci_resume,
57dbf29a
KSS		 4199};
4200
225c7b1f
RD		 4201static struct pci_driver mlx4_driver = {
4202 .name = DRV_NAME,
4203 .id_table = mlx4_pci_table,
4204 .probe = mlx4_init_one,
2ba5fbd6 4205 .shutdown = mlx4_shutdown,
f57e6848 4206 .remove = mlx4_remove_one,
57dbf29a 4207 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 4208};
4209
7ff93f8b
YP		 4210static int __init mlx4_verify_params(void)
4211{
4212 if ((log_num_mac < 0) || (log_num_mac > 7)) {
c20862c8 4213 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 4214 return -1;
4215 }
4216
cb29688a 4217 if (log_num_vlan != 0)
c20862c8
AV		 4218 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4219 MLX4_LOG_NUM_VLANS);
7ff93f8b 4220
ecc8fb11
AV		 4221 if (use_prio != 0)
4222 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
7ff93f8b 4223
0498628f 4224 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
c20862c8
AV		 4225 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4226 log_mtts_per_seg);
ab6bf42e
EC		 4227 return -1;
4228 }
4229
ab9c17a0
JM		 4230 /* Check if module param for ports type has legal combination */
4231 if (port_type_array[0] == false && port_type_array[1] == true) {
c20862c8 4232 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
ab9c17a0
JM		 4233 port_type_array[0] = true;
4234 }
4235
7d077cd3
MB		 4236 if (mlx4_log_num_mgm_entry_size < -7 ||
4237 (mlx4_log_num_mgm_entry_size > 0 &&
4238 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4239 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4240 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
1a91de28
JP		 4241 mlx4_log_num_mgm_entry_size,
4242 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4243 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
3c439b55
JM		 4244 return -1;
4245 }
4246
7ff93f8b
YP		 4247 return 0;
4248}
4249
225c7b1f
RD		 4250static int __init mlx4_init(void)
4251{
4252 int ret;
4253
7ff93f8b
YP		 4254 if (mlx4_verify_params())
4255 return -EINVAL;
4256
27bf91d6
YP		 4257
4258 mlx4_wq = create_singlethread_workqueue("mlx4");
4259 if (!mlx4_wq)
4260 return -ENOMEM;
ee49bd93 4261
225c7b1f 4262 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 4263 if (ret < 0)
4264 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4265 return ret < 0 ? ret : 0;
4266}
4267
4268static void __exit mlx4_cleanup(void)
4269{
4270 pci_unregister_driver(&mlx4_driver);
27bf91d6 4271 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 4272}
4273
4274module_init(mlx4_init);
4275module_exit(mlx4_cleanup);
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