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mlx4: In RoCE allow guests to have multiple GIDS
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / main.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
51a379d0 4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36#include <linux/module.h>
37#include <linux/init.h>
38#include <linux/errno.h>
39#include <linux/pci.h>
40#include <linux/dma-mapping.h>
5a0e3ad6 41#include <linux/slab.h>
c1b43dca 42#include <linux/io-mapping.h>
ab9c17a0 43#include <linux/delay.h>
b046ffe5 44#include <linux/kmod.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
47#include <linux/mlx4/doorbell.h>
48
49#include "mlx4.h"
50#include "fw.h"
51#include "icm.h"
52
53MODULE_AUTHOR("Roland Dreier");
54MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
55MODULE_LICENSE("Dual BSD/GPL");
56MODULE_VERSION(DRV_VERSION);
57
27bf91d6
YP		 58struct workqueue_struct *mlx4_wq;
59
225c7b1f
RD		 60#ifdef CONFIG_MLX4_DEBUG
61
62int mlx4_debug_level = 0;
63module_param_named(debug_level, mlx4_debug_level, int, 0644);
64MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
65
66#endif /* CONFIG_MLX4_DEBUG */
67
68#ifdef CONFIG_PCI_MSI
69
08fb1055 70static int msi_x = 1;
225c7b1f
RD		 71module_param(msi_x, int, 0444);
72MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
73
74#else /* CONFIG_PCI_MSI */
75
76#define msi_x (0)
77
78#endif /* CONFIG_PCI_MSI */
79
ab9c17a0
JM		 80static int num_vfs;
81module_param(num_vfs, int, 0444);
82MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0");
83
84static int probe_vf;
85module_param(probe_vf, int, 0644);
86MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)");
87
3c439b55 88int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
0ec2c0f8
EE		 89module_param_named(log_num_mgm_entry_size,
90 mlx4_log_num_mgm_entry_size, int, 0444);
91MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
92 " of qp per mcg, for example:"
3c439b55 93 " 10 gives 248.range: 7 <="
0ff1fb65 94 " log_num_mgm_entry_size <= 12."
3c439b55
JM		 95 " To activate device managed"
96 " flow steering when available, set to -1");
0ec2c0f8 97
be902ab1 98static bool enable_64b_cqe_eqe = true;
08ff3235
OG		 99module_param(enable_64b_cqe_eqe, bool, 0444);
100MODULE_PARM_DESC(enable_64b_cqe_eqe,
be902ab1 101 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
08ff3235 102
ab9c17a0 103#define HCA_GLOBAL_CAP_MASK 0
08ff3235
OG		 104
105#define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE
ab9c17a0 106
f57e6848 107static char mlx4_version[] =
225c7b1f
RD		 108 DRV_NAME ": Mellanox ConnectX core driver v"
109 DRV_VERSION " (" DRV_RELDATE ")\n";
110
111static struct mlx4_profile default_profile = {
ab9c17a0 112 .num_qp = 1 << 18,
225c7b1f 113 .num_srq = 1 << 16,
c9f2ba5e 114 .rdmarc_per_qp = 1 << 4,
225c7b1f
RD		 115 .num_cq = 1 << 16,
116 .num_mcg = 1 << 13,
ab9c17a0 117 .num_mpt = 1 << 19,
9fd7a1e1 118 .num_mtt = 1 << 20, /* It is really num mtt segements */
225c7b1f
RD		 119};
120
ab9c17a0 121static int log_num_mac = 7;
93fc9e1b
YP		 122module_param_named(log_num_mac, log_num_mac, int, 0444);
123MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
124
125static int log_num_vlan;
126module_param_named(log_num_vlan, log_num_vlan, int, 0444);
127MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
cb29688a
OG		 128/* Log2 max number of VLANs per ETH port (0-7) */
129#define MLX4_LOG_NUM_VLANS 7
93fc9e1b 130
eb939922 131static bool use_prio;
93fc9e1b
YP		 132module_param_named(use_prio, use_prio, bool, 0444);
133MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
134 "(0/1, default 0)");
135
2b8fb286 136int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
ab6bf42e 137module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
0498628f 138MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
ab6bf42e 139
8d0fc7b6 140static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
ab9c17a0
JM		 141static int arr_argc = 2;
142module_param_array(port_type_array, int, &arr_argc, 0444);
8d0fc7b6
YP		 143MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
144 "1 for IB, 2 for Ethernet");
ab9c17a0
JM		 145
146struct mlx4_port_config {
147 struct list_head list;
148 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
149 struct pci_dev *pdev;
150};
151
27bf91d6
YP		 152int mlx4_check_port_params(struct mlx4_dev *dev,
153 enum mlx4_port_type *port_type)
7ff93f8b
YP		 154{
155 int i;
156
157 for (i = 0; i < dev->caps.num_ports - 1; i++) {
27bf91d6
YP		 158 if (port_type[i] != port_type[i + 1]) {
159 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
160 mlx4_err(dev, "Only same port types supported "
161 "on this HCA, aborting.\n");
162 return -EINVAL;
163 }
7ff93f8b
YP		 164 }
165 }
7ff93f8b
YP		 166
167 for (i = 0; i < dev->caps.num_ports; i++) {
168 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
169 mlx4_err(dev, "Requested port type for port %d is not "
170 "supported on this HCA\n", i + 1);
171 return -EINVAL;
172 }
173 }
174 return 0;
175}
176
177static void mlx4_set_port_mask(struct mlx4_dev *dev)
178{
179 int i;
180
7ff93f8b 181 for (i = 1; i <= dev->caps.num_ports; ++i)
65dab25d 182 dev->caps.port_mask[i] = dev->caps.port_type[i];
7ff93f8b 183}
f2a3f6a3 184
3d73c288 185static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
225c7b1f
RD		 186{
187 int err;
5ae2a7a8 188 int i;
225c7b1f
RD		 189
190 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
191 if (err) {
192 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
193 return err;
194 }
195
196 if (dev_cap->min_page_sz > PAGE_SIZE) {
197 mlx4_err(dev, "HCA minimum page size of %d bigger than "
198 "kernel PAGE_SIZE of %ld, aborting.\n",
199 dev_cap->min_page_sz, PAGE_SIZE);
200 return -ENODEV;
201 }
202 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
203 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
204 "aborting.\n",
205 dev_cap->num_ports, MLX4_MAX_PORTS);
206 return -ENODEV;
207 }
208
209 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
210 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
211 "PCI resource 2 size of 0x%llx, aborting.\n",
212 dev_cap->uar_size,
213 (unsigned long long) pci_resource_len(dev->pdev, 2));
214 return -ENODEV;
215 }
216
217 dev->caps.num_ports = dev_cap->num_ports;
3fc929e2 218 dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM;
5ae2a7a8
RD		 219 for (i = 1; i <= dev->caps.num_ports; ++i) {
220 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
b79acb49 221 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
6634961c
JM		 222 dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i];
223 dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i];
224 /* set gid and pkey table operating lengths by default
225 * to non-sriov values */
5ae2a7a8
RD		 226 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
227 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
228 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
b79acb49
YP		 229 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
230 dev->caps.def_mac[i] = dev_cap->def_mac[i];
7ff93f8b 231 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
8d0fc7b6
YP		 232 dev->caps.suggested_type[i] = dev_cap->suggested_type[i];
233 dev->caps.default_sense[i] = dev_cap->default_sense[i];
7699517d
YP		 234 dev->caps.trans_type[i] = dev_cap->trans_type[i];
235 dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i];
236 dev->caps.wavelength[i] = dev_cap->wavelength[i];
237 dev->caps.trans_code[i] = dev_cap->trans_code[i];
5ae2a7a8
RD		 238 }
239
ab9c17a0 240 dev->caps.uar_page_size = PAGE_SIZE;
225c7b1f 241 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
225c7b1f
RD		 242 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
243 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
244 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
245 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
246 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
247 dev->caps.max_wqes = dev_cap->max_qp_sz;
248 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
225c7b1f
RD		 249 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
250 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
251 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
252 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
253 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
225c7b1f
RD		 254 /*
255 * Subtract 1 from the limit because we need to allocate a
256 * spare CQE so the HCA HW can tell the difference between an
257 * empty CQ and a full CQ.
258 */
259 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
260 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
261 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2b8fb286 262 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
225c7b1f 263 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
ab9c17a0
JM		 264
265 /* The first 128 UARs are used for EQ doorbells */
266 dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars);
225c7b1f 267 dev->caps.reserved_pds = dev_cap->reserved_pds;
012a8ff5
SH		 268 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
269 dev_cap->reserved_xrcds : 0;
270 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
271 dev_cap->max_xrcds : 0;
2b8fb286
MA		 272 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
273
149983af 274 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
225c7b1f
RD		 275 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
276 dev->caps.flags = dev_cap->flags;
b3416f44 277 dev->caps.flags2 = dev_cap->flags2;
95d04f07
RD		 278 dev->caps.bmme_flags = dev_cap->bmme_flags;
279 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
225c7b1f 280 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
b832be1e 281 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
b3416f44 282 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
225c7b1f 283
ca3e57a5
RD		 284 /* Sense port always allowed on supported devices for ConnectX-1 and -2 */
285 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
58a60168 286 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
aadf4f3f
RD		 287 /* Don't do sense port on multifunction devices (for now at least) */
288 if (mlx4_is_mfunc(dev))
289 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
58a60168 290
93fc9e1b 291 dev->caps.log_num_macs = log_num_mac;
cb29688a 292 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
93fc9e1b
YP		 293 dev->caps.log_num_prios = use_prio ? 3 : 0;
294
295 for (i = 1; i <= dev->caps.num_ports; ++i) {
ab9c17a0
JM		 296 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
297 if (dev->caps.supported_type[i]) {
298 /* if only ETH is supported - assign ETH */
299 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
300 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
105c320f 301 /* if only IB is supported, assign IB */
ab9c17a0 302 else if (dev->caps.supported_type[i] ==
105c320f
JM		 303 MLX4_PORT_TYPE_IB)
304 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
ab9c17a0 305 else {
105c320f
JM		 306 /* if IB and ETH are supported, we set the port
307 * type according to user selection of port type;
308 * if user selected none, take the FW hint */
309 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
8d0fc7b6
YP		 310 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
311 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
ab9c17a0 312 else
105c320f 313 dev->caps.port_type[i] = port_type_array[i - 1];
ab9c17a0
JM		 314 }
315 }
8d0fc7b6
YP		 316 /*
317 * Link sensing is allowed on the port if 3 conditions are true:
318 * 1. Both protocols are supported on the port.
319 * 2. Different types are supported on the port
320 * 3. FW declared that it supports link sensing
321 */
27bf91d6 322 mlx4_priv(dev)->sense.sense_allowed[i] =
58a60168 323 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
8d0fc7b6 324 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
58a60168 325 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
7ff93f8b 326
8d0fc7b6
YP		 327 /*
328 * If "default_sense" bit is set, we move the port to "AUTO" mode
329 * and perform sense_port FW command to try and set the correct
330 * port type from beginning
331 */
46c46747 332 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
8d0fc7b6
YP		 333 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
334 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
335 mlx4_SENSE_PORT(dev, i, &sensed_port);
336 if (sensed_port != MLX4_PORT_TYPE_NONE)
337 dev->caps.port_type[i] = sensed_port;
338 } else {
339 dev->caps.possible_type[i] = dev->caps.port_type[i];
340 }
341
93fc9e1b
YP		 342 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
343 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
344 mlx4_warn(dev, "Requested number of MACs is too much "
345 "for port %d, reducing to %d.\n",
346 i, 1 << dev->caps.log_num_macs);
347 }
348 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
349 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
350 mlx4_warn(dev, "Requested number of VLANs is too much "
351 "for port %d, reducing to %d.\n",
352 i, 1 << dev->caps.log_num_vlans);
353 }
354 }
355
f2a3f6a3
OG		 356 dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
357
93fc9e1b
YP		 358 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
359 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
360 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
361 (1 << dev->caps.log_num_macs) *
362 (1 << dev->caps.log_num_vlans) *
363 (1 << dev->caps.log_num_prios) *
364 dev->caps.num_ports;
365 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
366
367 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
368 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
369 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
370 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
371
e2c76824 372 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
08ff3235 373
b3051320 374 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
08ff3235
OG		 375 if (dev_cap->flags &
376 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
377 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
378 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
379 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
380 }
381 }
382
f97b4b5d 383 if ((dev->caps.flags &
08ff3235
OG		 384 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
385 mlx4_is_master(dev))
386 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
387
225c7b1f
RD		 388 return 0;
389}
b912b2f8
EP		 390
391static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev,
392 enum pci_bus_speed *speed,
393 enum pcie_link_width *width)
394{
395 u32 lnkcap1, lnkcap2;
396 int err1, err2;
397
398#define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
399
400 *speed = PCI_SPEED_UNKNOWN;
401 *width = PCIE_LNK_WIDTH_UNKNOWN;
402
403 err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1);
404 err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2);
405 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
406 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
407 *speed = PCIE_SPEED_8_0GT;
408 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
409 *speed = PCIE_SPEED_5_0GT;
410 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
411 *speed = PCIE_SPEED_2_5GT;
412 }
413 if (!err1) {
414 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
415 if (!lnkcap2) { /* pre-r3.0 */
416 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
417 *speed = PCIE_SPEED_5_0GT;
418 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
419 *speed = PCIE_SPEED_2_5GT;
420 }
421 }
422
423 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) {
424 return err1 ? err1 :
425 err2 ? err2 : -EINVAL;
426 }
427 return 0;
428}
429
430static void mlx4_check_pcie_caps(struct mlx4_dev *dev)
431{
432 enum pcie_link_width width, width_cap;
433 enum pci_bus_speed speed, speed_cap;
434 int err;
435
436#define PCIE_SPEED_STR(speed) \
437 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
438 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
439 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
440 "Unknown")
441
442 err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap);
443 if (err) {
444 mlx4_warn(dev,
445 "Unable to determine PCIe device BW capabilities\n");
446 return;
447 }
448
449 err = pcie_get_minimum_link(dev->pdev, &speed, &width);
450 if (err || speed == PCI_SPEED_UNKNOWN ||
451 width == PCIE_LNK_WIDTH_UNKNOWN) {
452 mlx4_warn(dev,
453 "Unable to determine PCI device chain minimum BW\n");
454 return;
455 }
456
457 if (width != width_cap || speed != speed_cap)
458 mlx4_warn(dev,
459 "PCIe BW is different than device's capability\n");
460
461 mlx4_info(dev, "PCIe link speed is %s, device supports %s\n",
462 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
463 mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n",
464 width, width_cap);
465 return;
466}
467
ab9c17a0
JM		 468/*The function checks if there are live vf, return the num of them*/
469static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
470{
471 struct mlx4_priv *priv = mlx4_priv(dev);
472 struct mlx4_slave_state *s_state;
473 int i;
474 int ret = 0;
475
476 for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) {
477 s_state = &priv->mfunc.master.slave_state[i];
478 if (s_state->active && s_state->last_cmd !=
479 MLX4_COMM_CMD_RESET) {
480 mlx4_warn(dev, "%s: slave: %d is still active\n",
481 __func__, i);
482 ret++;
483 }
484 }
485 return ret;
486}
487
396f2feb
JM		 488int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
489{
490 u32 qk = MLX4_RESERVED_QKEY_BASE;
47605df9
JM		 491
492 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
493 qpn < dev->phys_caps.base_proxy_sqpn)
396f2feb
JM		 494 return -EINVAL;
495
47605df9 496 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
396f2feb 497 /* tunnel qp */
47605df9 498 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
396f2feb 499 else
47605df9 500 qk += qpn - dev->phys_caps.base_proxy_sqpn;
396f2feb
JM		 501 *qkey = qk;
502 return 0;
503}
504EXPORT_SYMBOL(mlx4_get_parav_qkey);
505
54679e14
JM		 506void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
507{
508 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
509
510 if (!mlx4_is_master(dev))
511 return;
512
513 priv->virt2phys_pkey[slave][port - 1][i] = val;
514}
515EXPORT_SYMBOL(mlx4_sync_pkey_table);
516
afa8fd1d
JM		 517void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
518{
519 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
520
521 if (!mlx4_is_master(dev))
522 return;
523
524 priv->slave_node_guids[slave] = guid;
525}
526EXPORT_SYMBOL(mlx4_put_slave_node_guid);
527
528__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
529{
530 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
531
532 if (!mlx4_is_master(dev))
533 return 0;
534
535 return priv->slave_node_guids[slave];
536}
537EXPORT_SYMBOL(mlx4_get_slave_node_guid);
538
e10903b0 539int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
ab9c17a0
JM		 540{
541 struct mlx4_priv *priv = mlx4_priv(dev);
542 struct mlx4_slave_state *s_slave;
543
544 if (!mlx4_is_master(dev))
545 return 0;
546
547 s_slave = &priv->mfunc.master.slave_state[slave];
548 return !!s_slave->active;
549}
550EXPORT_SYMBOL(mlx4_is_slave_active);
551
7b8157be
JM		 552static void slave_adjust_steering_mode(struct mlx4_dev *dev,
553 struct mlx4_dev_cap *dev_cap,
554 struct mlx4_init_hca_param *hca_param)
555{
556 dev->caps.steering_mode = hca_param->steering_mode;
557 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
558 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
559 dev->caps.fs_log_max_ucast_qp_range_size =
560 dev_cap->fs_log_max_ucast_qp_range_size;
561 } else
562 dev->caps.num_qp_per_mgm =
563 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
564
565 mlx4_dbg(dev, "Steering mode is: %s\n",
566 mlx4_steering_mode_str(dev->caps.steering_mode));
567}
568
ab9c17a0
JM		 569static int mlx4_slave_cap(struct mlx4_dev *dev)
570{
571 int err;
572 u32 page_size;
573 struct mlx4_dev_cap dev_cap;
574 struct mlx4_func_cap func_cap;
575 struct mlx4_init_hca_param hca_param;
576 int i;
577
578 memset(&hca_param, 0, sizeof(hca_param));
579 err = mlx4_QUERY_HCA(dev, &hca_param);
580 if (err) {
581 mlx4_err(dev, "QUERY_HCA command failed, aborting.\n");
582 return err;
583 }
584
585 /*fail if the hca has an unknown capability */
586 if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) !=
587 HCA_GLOBAL_CAP_MASK) {
588 mlx4_err(dev, "Unknown hca global capabilities\n");
589 return -ENOSYS;
590 }
591
592 mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz;
593
ddd8a6c1
EE		 594 dev->caps.hca_core_clock = hca_param.hca_core_clock;
595
ab9c17a0 596 memset(&dev_cap, 0, sizeof(dev_cap));
b91cb3eb 597 dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp;
ab9c17a0
JM		 598 err = mlx4_dev_cap(dev, &dev_cap);
599 if (err) {
600 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
601 return err;
602 }
603
b91cb3eb
JM		 604 err = mlx4_QUERY_FW(dev);
605 if (err)
606 mlx4_err(dev, "QUERY_FW command failed: could not get FW version.\n");
607
ab9c17a0
JM		 608 page_size = ~dev->caps.page_size_cap + 1;
609 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
610 if (page_size > PAGE_SIZE) {
611 mlx4_err(dev, "HCA minimum page size of %d bigger than "
612 "kernel PAGE_SIZE of %ld, aborting.\n",
613 page_size, PAGE_SIZE);
614 return -ENODEV;
615 }
616
617 /* slave gets uar page size from QUERY_HCA fw command */
618 dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12);
619
620 /* TODO: relax this assumption */
621 if (dev->caps.uar_page_size != PAGE_SIZE) {
622 mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n",
623 dev->caps.uar_page_size, PAGE_SIZE);
624 return -ENODEV;
625 }
626
627 memset(&func_cap, 0, sizeof(func_cap));
47605df9 628 err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap);
ab9c17a0 629 if (err) {
47605df9
JM		 630 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d).\n",
631 err);
ab9c17a0
JM		 632 return err;
633 }
634
635 if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
636 PF_CONTEXT_BEHAVIOUR_MASK) {
637 mlx4_err(dev, "Unknown pf context behaviour\n");
638 return -ENOSYS;
639 }
640
ab9c17a0 641 dev->caps.num_ports = func_cap.num_ports;
5a0d0a61
JM		 642 dev->quotas.qp = func_cap.qp_quota;
643 dev->quotas.srq = func_cap.srq_quota;
644 dev->quotas.cq = func_cap.cq_quota;
645 dev->quotas.mpt = func_cap.mpt_quota;
646 dev->quotas.mtt = func_cap.mtt_quota;
647 dev->caps.num_qps = 1 << hca_param.log_num_qps;
648 dev->caps.num_srqs = 1 << hca_param.log_num_srqs;
649 dev->caps.num_cqs = 1 << hca_param.log_num_cqs;
650 dev->caps.num_mpts = 1 << hca_param.log_mpt_sz;
651 dev->caps.num_eqs = func_cap.max_eq;
652 dev->caps.reserved_eqs = func_cap.reserved_eq;
ab9c17a0
JM		 653 dev->caps.num_pds = MLX4_NUM_PDS;
654 dev->caps.num_mgms = 0;
655 dev->caps.num_amgms = 0;
656
ab9c17a0
JM		 657 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
658 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
659 "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS);
660 return -ENODEV;
661 }
662
47605df9
JM		 663 dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
664 dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
665 dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
666 dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL);
667
668 if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy ||
669 !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) {
670 err = -ENOMEM;
671 goto err_mem;
672 }
673
6634961c 674 for (i = 1; i <= dev->caps.num_ports; ++i) {
47605df9
JM		 675 err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap);
676 if (err) {
677 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for"
678 " port %d, aborting (%d).\n", i, err);
679 goto err_mem;
680 }
681 dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn;
682 dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn;
683 dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn;
684 dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn;
6230bb23 685 dev->caps.port_mask[i] = dev->caps.port_type[i];
8e1a28e8 686 dev->caps.phys_port_id[i] = func_cap.phys_port_id;
6634961c
JM		 687 if (mlx4_get_slave_pkey_gid_tbl_len(dev, i,
688 &dev->caps.gid_table_len[i],
689 &dev->caps.pkey_table_len[i]))
47605df9 690 goto err_mem;
6634961c 691 }
6230bb23 692
ab9c17a0
JM		 693 if (dev->caps.uar_page_size * (dev->caps.num_uars -
694 dev->caps.reserved_uars) >
695 pci_resource_len(dev->pdev, 2)) {
696 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than "
697 "PCI resource 2 size of 0x%llx, aborting.\n",
698 dev->caps.uar_page_size * dev->caps.num_uars,
699 (unsigned long long) pci_resource_len(dev->pdev, 2));
47605df9 700 goto err_mem;
ab9c17a0
JM		 701 }
702
08ff3235
OG		 703 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
704 dev->caps.eqe_size = 64;
705 dev->caps.eqe_factor = 1;
706 } else {
707 dev->caps.eqe_size = 32;
708 dev->caps.eqe_factor = 0;
709 }
710
711 if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
712 dev->caps.cqe_size = 64;
713 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
714 } else {
715 dev->caps.cqe_size = 32;
716 }
717
f9bd2d7f
AV		 718 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
719 mlx4_warn(dev, "Timestamping is not supported in slave mode.\n");
720
7b8157be
JM		 721 slave_adjust_steering_mode(dev, &dev_cap, &hca_param);
722
ab9c17a0 723 return 0;
47605df9
JM		 724
725err_mem:
726 kfree(dev->caps.qp0_tunnel);
727 kfree(dev->caps.qp0_proxy);
728 kfree(dev->caps.qp1_tunnel);
729 kfree(dev->caps.qp1_proxy);
730 dev->caps.qp0_tunnel = dev->caps.qp0_proxy =
731 dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL;
732
733 return err;
ab9c17a0 734}
225c7b1f 735
b046ffe5
EP		 736static void mlx4_request_modules(struct mlx4_dev *dev)
737{
738 int port;
739 int has_ib_port = false;
740 int has_eth_port = false;
741#define EN_DRV_NAME "mlx4_en"
742#define IB_DRV_NAME "mlx4_ib"
743
744 for (port = 1; port <= dev->caps.num_ports; port++) {
745 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
746 has_ib_port = true;
747 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
748 has_eth_port = true;
749 }
750
751 if (has_ib_port)
752 request_module_nowait(IB_DRV_NAME);
753 if (has_eth_port)
754 request_module_nowait(EN_DRV_NAME);
755}
756
7ff93f8b
YP		 757/*
758 * Change the port configuration of the device.
759 * Every user of this function must hold the port mutex.
760 */
27bf91d6
YP		 761int mlx4_change_port_types(struct mlx4_dev *dev,
762 enum mlx4_port_type *port_types)
7ff93f8b
YP		 763{
764 int err = 0;
765 int change = 0;
766 int port;
767
768 for (port = 0; port < dev->caps.num_ports; port++) {
27bf91d6
YP		 769 /* Change the port type only if the new type is different
770 * from the current, and not set to Auto */
3d8f9308 771 if (port_types[port] != dev->caps.port_type[port + 1])
7ff93f8b 772 change = 1;
7ff93f8b
YP		 773 }
774 if (change) {
775 mlx4_unregister_device(dev);
776 for (port = 1; port <= dev->caps.num_ports; port++) {
777 mlx4_CLOSE_PORT(dev, port);
1e0f03d5 778 dev->caps.port_type[port] = port_types[port - 1];
6634961c 779 err = mlx4_SET_PORT(dev, port, -1);
7ff93f8b
YP		 780 if (err) {
781 mlx4_err(dev, "Failed to set port %d, "
782 "aborting\n", port);
783 goto out;
784 }
785 }
786 mlx4_set_port_mask(dev);
787 err = mlx4_register_device(dev);
b046ffe5
EP		 788 if (err) {
789 mlx4_err(dev, "Failed to register device\n");
790 goto out;
791 }
792 mlx4_request_modules(dev);
7ff93f8b
YP		 793 }
794
795out:
796 return err;
797}
798
799static ssize_t show_port_type(struct device *dev,
800 struct device_attribute *attr,
801 char *buf)
802{
803 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
804 port_attr);
805 struct mlx4_dev *mdev = info->dev;
27bf91d6
YP		 806 char type[8];
807
808 sprintf(type, "%s",
809 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
810 "ib" : "eth");
811 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
812 sprintf(buf, "auto (%s)\n", type);
813 else
814 sprintf(buf, "%s\n", type);
7ff93f8b 815
27bf91d6 816 return strlen(buf);
7ff93f8b
YP		 817}
818
819static ssize_t set_port_type(struct device *dev,
820 struct device_attribute *attr,
821 const char *buf, size_t count)
822{
823 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
824 port_attr);
825 struct mlx4_dev *mdev = info->dev;
826 struct mlx4_priv *priv = mlx4_priv(mdev);
827 enum mlx4_port_type types[MLX4_MAX_PORTS];
27bf91d6 828 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
7ff93f8b
YP		 829 int i;
830 int err = 0;
831
832 if (!strcmp(buf, "ib\n"))
833 info->tmp_type = MLX4_PORT_TYPE_IB;
834 else if (!strcmp(buf, "eth\n"))
835 info->tmp_type = MLX4_PORT_TYPE_ETH;
27bf91d6
YP		 836 else if (!strcmp(buf, "auto\n"))
837 info->tmp_type = MLX4_PORT_TYPE_AUTO;
7ff93f8b
YP		 838 else {
839 mlx4_err(mdev, "%s is not supported port type\n", buf);
840 return -EINVAL;
841 }
842
27bf91d6 843 mlx4_stop_sense(mdev);
7ff93f8b 844 mutex_lock(&priv->port_mutex);
27bf91d6
YP		 845 /* Possible type is always the one that was delivered */
846 mdev->caps.possible_type[info->port] = info->tmp_type;
847
848 for (i = 0; i < mdev->caps.num_ports; i++) {
7ff93f8b 849 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
27bf91d6
YP		 850 mdev->caps.possible_type[i+1];
851 if (types[i] == MLX4_PORT_TYPE_AUTO)
852 types[i] = mdev->caps.port_type[i+1];
853 }
7ff93f8b 854
58a60168
YP		 855 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
856 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
27bf91d6
YP		 857 for (i = 1; i <= mdev->caps.num_ports; i++) {
858 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
859 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
860 err = -EINVAL;
861 }
862 }
863 }
864 if (err) {
865 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
866 "Set only 'eth' or 'ib' for both ports "
867 "(should be the same)\n");
868 goto out;
869 }
870
871 mlx4_do_sense_ports(mdev, new_types, types);
872
873 err = mlx4_check_port_params(mdev, new_types);
7ff93f8b
YP		 874 if (err)
875 goto out;
876
27bf91d6
YP		 877 /* We are about to apply the changes after the configuration
878 * was verified, no need to remember the temporary types
879 * any more */
880 for (i = 0; i < mdev->caps.num_ports; i++)
881 priv->port[i + 1].tmp_type = 0;
7ff93f8b 882
27bf91d6 883 err = mlx4_change_port_types(mdev, new_types);
7ff93f8b
YP		 884
885out:
27bf91d6 886 mlx4_start_sense(mdev);
7ff93f8b
YP		 887 mutex_unlock(&priv->port_mutex);
888 return err ? err : count;
889}
890
096335b3
OG		 891enum ibta_mtu {
892 IB_MTU_256 = 1,
893 IB_MTU_512 = 2,
894 IB_MTU_1024 = 3,
895 IB_MTU_2048 = 4,
896 IB_MTU_4096 = 5
897};
898
899static inline int int_to_ibta_mtu(int mtu)
900{
901 switch (mtu) {
902 case 256: return IB_MTU_256;
903 case 512: return IB_MTU_512;
904 case 1024: return IB_MTU_1024;
905 case 2048: return IB_MTU_2048;
906 case 4096: return IB_MTU_4096;
907 default: return -1;
908 }
909}
910
911static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
912{
913 switch (mtu) {
914 case IB_MTU_256: return 256;
915 case IB_MTU_512: return 512;
916 case IB_MTU_1024: return 1024;
917 case IB_MTU_2048: return 2048;
918 case IB_MTU_4096: return 4096;
919 default: return -1;
920 }
921}
922
923static ssize_t show_port_ib_mtu(struct device *dev,
924 struct device_attribute *attr,
925 char *buf)
926{
927 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
928 port_mtu_attr);
929 struct mlx4_dev *mdev = info->dev;
930
931 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
932 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
933
934 sprintf(buf, "%d\n",
935 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
936 return strlen(buf);
937}
938
939static ssize_t set_port_ib_mtu(struct device *dev,
940 struct device_attribute *attr,
941 const char *buf, size_t count)
942{
943 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
944 port_mtu_attr);
945 struct mlx4_dev *mdev = info->dev;
946 struct mlx4_priv *priv = mlx4_priv(mdev);
947 int err, port, mtu, ibta_mtu = -1;
948
949 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
950 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
951 return -EINVAL;
952 }
953
618fad95
DB		 954 err = kstrtoint(buf, 0, &mtu);
955 if (!err)
096335b3
OG		 956 ibta_mtu = int_to_ibta_mtu(mtu);
957
618fad95 958 if (err || ibta_mtu < 0) {
096335b3
OG		 959 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
960 return -EINVAL;
961 }
962
963 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
964
965 mlx4_stop_sense(mdev);
966 mutex_lock(&priv->port_mutex);
967 mlx4_unregister_device(mdev);
968 for (port = 1; port <= mdev->caps.num_ports; port++) {
969 mlx4_CLOSE_PORT(mdev, port);
6634961c 970 err = mlx4_SET_PORT(mdev, port, -1);
096335b3
OG		 971 if (err) {
972 mlx4_err(mdev, "Failed to set port %d, "
973 "aborting\n", port);
974 goto err_set_port;
975 }
976 }
977 err = mlx4_register_device(mdev);
978err_set_port:
979 mutex_unlock(&priv->port_mutex);
980 mlx4_start_sense(mdev);
981 return err ? err : count;
982}
983
e8f9b2ed 984static int mlx4_load_fw(struct mlx4_dev *dev)
225c7b1f
RD		 985{
986 struct mlx4_priv *priv = mlx4_priv(dev);
987 int err;
988
989 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
5b0bf5e2 990 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 991 if (!priv->fw.fw_icm) {
992 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
993 return -ENOMEM;
994 }
995
996 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
997 if (err) {
998 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
999 goto err_free;
1000 }
1001
1002 err = mlx4_RUN_FW(dev);
1003 if (err) {
1004 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
1005 goto err_unmap_fa;
1006 }
1007
1008 return 0;
1009
1010err_unmap_fa:
1011 mlx4_UNMAP_FA(dev);
1012
1013err_free:
5b0bf5e2 1014 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
225c7b1f
RD		 1015 return err;
1016}
1017
e8f9b2ed
RD		 1018static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1019 int cmpt_entry_sz)
225c7b1f
RD		 1020{
1021 struct mlx4_priv *priv = mlx4_priv(dev);
1022 int err;
ab9c17a0 1023 int num_eqs;
225c7b1f
RD		 1024
1025 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1026 cmpt_base +
1027 ((u64) (MLX4_CMPT_TYPE_QP *
1028 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1029 cmpt_entry_sz, dev->caps.num_qps,
93fc9e1b
YP		 1030 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1031 0, 0);
225c7b1f
RD		 1032 if (err)
1033 goto err;
1034
1035 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1036 cmpt_base +
1037 ((u64) (MLX4_CMPT_TYPE_SRQ *
1038 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1039 cmpt_entry_sz, dev->caps.num_srqs,
5b0bf5e2 1040 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1041 if (err)
1042 goto err_qp;
1043
1044 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1045 cmpt_base +
1046 ((u64) (MLX4_CMPT_TYPE_CQ *
1047 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1048 cmpt_entry_sz, dev->caps.num_cqs,
5b0bf5e2 1049 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1050 if (err)
1051 goto err_srq;
1052
3fc929e2
MA		 1053 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1054 dev->caps.num_eqs;
225c7b1f
RD		 1055 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1056 cmpt_base +
1057 ((u64) (MLX4_CMPT_TYPE_EQ *
1058 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
ab9c17a0 1059 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1060 if (err)
1061 goto err_cq;
1062
1063 return 0;
1064
1065err_cq:
1066 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1067
1068err_srq:
1069 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1070
1071err_qp:
1072 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1073
1074err:
1075 return err;
1076}
1077
3d73c288
RD		 1078static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1079 struct mlx4_init_hca_param *init_hca, u64 icm_size)
225c7b1f
RD		 1080{
1081 struct mlx4_priv *priv = mlx4_priv(dev);
1082 u64 aux_pages;
ab9c17a0 1083 int num_eqs;
225c7b1f
RD		 1084 int err;
1085
1086 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1087 if (err) {
1088 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
1089 return err;
1090 }
1091
1092 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
1093 (unsigned long long) icm_size >> 10,
1094 (unsigned long long) aux_pages << 2);
1095
1096 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
5b0bf5e2 1097 GFP_HIGHUSER | __GFP_NOWARN, 0);
225c7b1f
RD		 1098 if (!priv->fw.aux_icm) {
1099 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
1100 return -ENOMEM;
1101 }
1102
1103 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1104 if (err) {
1105 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
1106 goto err_free_aux;
1107 }
1108
1109 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1110 if (err) {
1111 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
1112 goto err_unmap_aux;
1113 }
1114
ab9c17a0 1115
3fc929e2
MA		 1116 num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs :
1117 dev->caps.num_eqs;
fa0681d2
RD		 1118 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1119 init_hca->eqc_base, dev_cap->eqc_entry_sz,
ab9c17a0 1120 num_eqs, num_eqs, 0, 0);
225c7b1f
RD		 1121 if (err) {
1122 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
1123 goto err_unmap_cmpt;
1124 }
1125
d7bb58fb
JM		 1126 /*
1127 * Reserved MTT entries must be aligned up to a cacheline
1128 * boundary, since the FW will write to them, while the driver
1129 * writes to all other MTT entries. (The variable
1130 * dev->caps.mtt_entry_sz below is really the MTT segment
1131 * size, not the raw entry size)
1132 */
1133 dev->caps.reserved_mtts =
1134 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1135 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1136
225c7b1f
RD		 1137 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1138 init_hca->mtt_base,
1139 dev->caps.mtt_entry_sz,
2b8fb286 1140 dev->caps.num_mtts,
5b0bf5e2 1141 dev->caps.reserved_mtts, 1, 0);
225c7b1f
RD		 1142 if (err) {
1143 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
1144 goto err_unmap_eq;
1145 }
1146
1147 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1148 init_hca->dmpt_base,
1149 dev_cap->dmpt_entry_sz,
1150 dev->caps.num_mpts,
5b0bf5e2 1151 dev->caps.reserved_mrws, 1, 1);
225c7b1f
RD		 1152 if (err) {
1153 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
1154 goto err_unmap_mtt;
1155 }
1156
1157 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1158 init_hca->qpc_base,
1159 dev_cap->qpc_entry_sz,
1160 dev->caps.num_qps,
93fc9e1b
YP		 1161 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1162 0, 0);
225c7b1f
RD		 1163 if (err) {
1164 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
1165 goto err_unmap_dmpt;
1166 }
1167
1168 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1169 init_hca->auxc_base,
1170 dev_cap->aux_entry_sz,
1171 dev->caps.num_qps,
93fc9e1b
YP		 1172 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1173 0, 0);
225c7b1f
RD		 1174 if (err) {
1175 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
1176 goto err_unmap_qp;
1177 }
1178
1179 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1180 init_hca->altc_base,
1181 dev_cap->altc_entry_sz,
1182 dev->caps.num_qps,
93fc9e1b
YP		 1183 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1184 0, 0);
225c7b1f
RD		 1185 if (err) {
1186 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
1187 goto err_unmap_auxc;
1188 }
1189
1190 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1191 init_hca->rdmarc_base,
1192 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1193 dev->caps.num_qps,
93fc9e1b
YP		 1194 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1195 0, 0);
225c7b1f
RD		 1196 if (err) {
1197 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1198 goto err_unmap_altc;
1199 }
1200
1201 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1202 init_hca->cqc_base,
1203 dev_cap->cqc_entry_sz,
1204 dev->caps.num_cqs,
5b0bf5e2 1205 dev->caps.reserved_cqs, 0, 0);
225c7b1f
RD		 1206 if (err) {
1207 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
1208 goto err_unmap_rdmarc;
1209 }
1210
1211 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1212 init_hca->srqc_base,
1213 dev_cap->srq_entry_sz,
1214 dev->caps.num_srqs,
5b0bf5e2 1215 dev->caps.reserved_srqs, 0, 0);
225c7b1f
RD		 1216 if (err) {
1217 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
1218 goto err_unmap_cq;
1219 }
1220
1221 /*
0ff1fb65
HHZ		 1222 * For flow steering device managed mode it is required to use
1223 * mlx4_init_icm_table. For B0 steering mode it's not strictly
1224 * required, but for simplicity just map the whole multicast
1225 * group table now. The table isn't very big and it's a lot
1226 * easier than trying to track ref counts.
225c7b1f
RD		 1227 */
1228 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
0ec2c0f8
EE		 1229 init_hca->mc_base,
1230 mlx4_get_mgm_entry_size(dev),
225c7b1f
RD		 1231 dev->caps.num_mgms + dev->caps.num_amgms,
1232 dev->caps.num_mgms + dev->caps.num_amgms,
5b0bf5e2 1233 0, 0);
225c7b1f
RD		 1234 if (err) {
1235 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
1236 goto err_unmap_srq;
1237 }
1238
1239 return 0;
1240
1241err_unmap_srq:
1242 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1243
1244err_unmap_cq:
1245 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1246
1247err_unmap_rdmarc:
1248 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1249
1250err_unmap_altc:
1251 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1252
1253err_unmap_auxc:
1254 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1255
1256err_unmap_qp:
1257 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1258
1259err_unmap_dmpt:
1260 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1261
1262err_unmap_mtt:
1263 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1264
1265err_unmap_eq:
fa0681d2 1266 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1267
1268err_unmap_cmpt:
1269 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1270 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1271 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1272 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1273
1274err_unmap_aux:
1275 mlx4_UNMAP_ICM_AUX(dev);
1276
1277err_free_aux:
5b0bf5e2 1278 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1279
1280 return err;
1281}
1282
1283static void mlx4_free_icms(struct mlx4_dev *dev)
1284{
1285 struct mlx4_priv *priv = mlx4_priv(dev);
1286
1287 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1288 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1289 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1290 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1291 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1292 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1293 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1294 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1295 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
fa0681d2 1296 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
225c7b1f
RD		 1297 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1298 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1299 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1300 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
225c7b1f
RD		 1301
1302 mlx4_UNMAP_ICM_AUX(dev);
5b0bf5e2 1303 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
225c7b1f
RD		 1304}
1305
ab9c17a0
JM		 1306static void mlx4_slave_exit(struct mlx4_dev *dev)
1307{
1308 struct mlx4_priv *priv = mlx4_priv(dev);
1309
f3d4c89e 1310 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1311 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME))
1312 mlx4_warn(dev, "Failed to close slave function.\n");
f3d4c89e 1313 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1314}
1315
c1b43dca
EC		 1316static int map_bf_area(struct mlx4_dev *dev)
1317{
1318 struct mlx4_priv *priv = mlx4_priv(dev);
1319 resource_size_t bf_start;
1320 resource_size_t bf_len;
1321 int err = 0;
1322
3d747473
JM		 1323 if (!dev->caps.bf_reg_size)
1324 return -ENXIO;
1325
ab9c17a0
JM		 1326 bf_start = pci_resource_start(dev->pdev, 2) +
1327 (dev->caps.num_uars << PAGE_SHIFT);
1328 bf_len = pci_resource_len(dev->pdev, 2) -
1329 (dev->caps.num_uars << PAGE_SHIFT);
c1b43dca
EC		 1330 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1331 if (!priv->bf_mapping)
1332 err = -ENOMEM;
1333
1334 return err;
1335}
1336
1337static void unmap_bf_area(struct mlx4_dev *dev)
1338{
1339 if (mlx4_priv(dev)->bf_mapping)
1340 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1341}
1342
ec693d47
AV		 1343cycle_t mlx4_read_clock(struct mlx4_dev *dev)
1344{
1345 u32 clockhi, clocklo, clockhi1;
1346 cycle_t cycles;
1347 int i;
1348 struct mlx4_priv *priv = mlx4_priv(dev);
1349
1350 for (i = 0; i < 10; i++) {
1351 clockhi = swab32(readl(priv->clock_mapping));
1352 clocklo = swab32(readl(priv->clock_mapping + 4));
1353 clockhi1 = swab32(readl(priv->clock_mapping));
1354 if (clockhi == clockhi1)
1355 break;
1356 }
1357
1358 cycles = (u64) clockhi << 32 | (u64) clocklo;
1359
1360 return cycles;
1361}
1362EXPORT_SYMBOL_GPL(mlx4_read_clock);
1363
1364
ddd8a6c1
EE		 1365static int map_internal_clock(struct mlx4_dev *dev)
1366{
1367 struct mlx4_priv *priv = mlx4_priv(dev);
1368
1369 priv->clock_mapping =
1370 ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) +
1371 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1372
1373 if (!priv->clock_mapping)
1374 return -ENOMEM;
1375
1376 return 0;
1377}
1378
1379static void unmap_internal_clock(struct mlx4_dev *dev)
1380{
1381 struct mlx4_priv *priv = mlx4_priv(dev);
1382
1383 if (priv->clock_mapping)
1384 iounmap(priv->clock_mapping);
1385}
1386
225c7b1f
RD		 1387static void mlx4_close_hca(struct mlx4_dev *dev)
1388{
ddd8a6c1 1389 unmap_internal_clock(dev);
c1b43dca 1390 unmap_bf_area(dev);
ab9c17a0
JM		 1391 if (mlx4_is_slave(dev))
1392 mlx4_slave_exit(dev);
1393 else {
1394 mlx4_CLOSE_HCA(dev, 0);
1395 mlx4_free_icms(dev);
1396 mlx4_UNMAP_FA(dev);
1397 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1398 }
1399}
1400
1401static int mlx4_init_slave(struct mlx4_dev *dev)
1402{
1403 struct mlx4_priv *priv = mlx4_priv(dev);
1404 u64 dma = (u64) priv->mfunc.vhcr_dma;
ab9c17a0
JM		 1405 int ret_from_reset = 0;
1406 u32 slave_read;
1407 u32 cmd_channel_ver;
1408
f3d4c89e 1409 mutex_lock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1410 priv->cmd.max_cmds = 1;
1411 mlx4_warn(dev, "Sending reset\n");
1412 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1413 MLX4_COMM_TIME);
1414 /* if we are in the middle of flr the slave will try
1415 * NUM_OF_RESET_RETRIES times before leaving.*/
1416 if (ret_from_reset) {
1417 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
5efe5355
JM		 1418 mlx4_warn(dev, "slave is currently in the "
1419 "middle of FLR. Deferring probe.\n");
1420 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1421 return -EPROBE_DEFER;
ab9c17a0
JM		 1422 } else
1423 goto err;
1424 }
1425
1426 /* check the driver version - the slave I/F revision
1427 * must match the master's */
1428 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1429 cmd_channel_ver = mlx4_comm_get_version();
1430
1431 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1432 MLX4_COMM_GET_IF_REV(slave_read)) {
1433 mlx4_err(dev, "slave driver version is not supported"
1434 " by the master\n");
1435 goto err;
1436 }
1437
1438 mlx4_warn(dev, "Sending vhcr0\n");
1439 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1440 MLX4_COMM_TIME))
1441 goto err;
1442 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1443 MLX4_COMM_TIME))
1444 goto err;
1445 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1446 MLX4_COMM_TIME))
1447 goto err;
1448 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME))
1449 goto err;
f3d4c89e
RD		 1450
1451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0
JM		 1452 return 0;
1453
1454err:
1455 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0);
f3d4c89e 1456 mutex_unlock(&priv->cmd.slave_cmd_mutex);
ab9c17a0 1457 return -EIO;
225c7b1f
RD		 1458}
1459
6634961c
JM		 1460static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
1461{
1462 int i;
1463
1464 for (i = 1; i <= dev->caps.num_ports; i++) {
b6ffaeff
JM		 1465 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
1466 dev->caps.gid_table_len[i] =
1467 mlx4_get_slave_num_gids(dev, 0);
1468 else
1469 dev->caps.gid_table_len[i] = 1;
6634961c
JM		 1470 dev->caps.pkey_table_len[i] =
1471 dev->phys_caps.pkey_phys_table_len[i] - 1;
1472 }
1473}
1474
3c439b55
JM		 1475static int choose_log_fs_mgm_entry_size(int qp_per_entry)
1476{
1477 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
1478
1479 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
1480 i++) {
1481 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
1482 break;
1483 }
1484
1485 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
1486}
1487
7b8157be
JM		 1488static void choose_steering_mode(struct mlx4_dev *dev,
1489 struct mlx4_dev_cap *dev_cap)
1490{
3c439b55
JM		 1491 if (mlx4_log_num_mgm_entry_size == -1 &&
1492 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
7b8157be 1493 (!mlx4_is_mfunc(dev) ||
3c439b55
JM		 1494 (dev_cap->fs_max_num_qp_per_entry >= (num_vfs + 1))) &&
1495 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
1496 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
1497 dev->oper_log_mgm_entry_size =
1498 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
7b8157be
JM		 1499 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1500 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
1501 dev->caps.fs_log_max_ucast_qp_range_size =
1502 dev_cap->fs_log_max_ucast_qp_range_size;
1503 } else {
1504 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
1505 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1506 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
1507 else {
1508 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
1509
1510 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
1511 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1512 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags "
1513 "set to use B0 steering. Falling back to A0 steering mode.\n");
1514 }
3c439b55
JM		 1515 dev->oper_log_mgm_entry_size =
1516 mlx4_log_num_mgm_entry_size > 0 ?
1517 mlx4_log_num_mgm_entry_size :
1518 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
7b8157be
JM		 1519 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
1520 }
3c439b55
JM		 1521 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, "
1522 "modparam log_num_mgm_entry_size = %d\n",
1523 mlx4_steering_mode_str(dev->caps.steering_mode),
1524 dev->oper_log_mgm_entry_size,
1525 mlx4_log_num_mgm_entry_size);
7b8157be
JM		 1526}
1527
7ffdf726
OG		 1528static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
1529 struct mlx4_dev_cap *dev_cap)
1530{
1531 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
1532 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
1533 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
1534 else
1535 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
1536
1537 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
1538 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
1539}
1540
3d73c288 1541static int mlx4_init_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1542{
1543 struct mlx4_priv *priv = mlx4_priv(dev);
1544 struct mlx4_adapter adapter;
1545 struct mlx4_dev_cap dev_cap;
2d928651 1546 struct mlx4_mod_stat_cfg mlx4_cfg;
225c7b1f
RD		 1547 struct mlx4_profile profile;
1548 struct mlx4_init_hca_param init_hca;
1549 u64 icm_size;
1550 int err;
1551
ab9c17a0
JM		 1552 if (!mlx4_is_slave(dev)) {
1553 err = mlx4_QUERY_FW(dev);
1554 if (err) {
1555 if (err == -EACCES)
1556 mlx4_info(dev, "non-primary physical function, skipping.\n");
1557 else
1558 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
bef772eb 1559 return err;
ab9c17a0 1560 }
225c7b1f 1561
ab9c17a0
JM		 1562 err = mlx4_load_fw(dev);
1563 if (err) {
1564 mlx4_err(dev, "Failed to start FW, aborting.\n");
bef772eb 1565 return err;
ab9c17a0 1566 }
225c7b1f 1567
ab9c17a0
JM		 1568 mlx4_cfg.log_pg_sz_m = 1;
1569 mlx4_cfg.log_pg_sz = 0;
1570 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
1571 if (err)
1572 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2d928651 1573
ab9c17a0
JM		 1574 err = mlx4_dev_cap(dev, &dev_cap);
1575 if (err) {
1576 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
1577 goto err_stop_fw;
1578 }
225c7b1f 1579
7b8157be 1580 choose_steering_mode(dev, &dev_cap);
7ffdf726 1581 choose_tunnel_offload_mode(dev, &dev_cap);
7b8157be 1582
8e1a28e8
HHZ		 1583 err = mlx4_get_phys_port_id(dev);
1584 if (err)
1585 mlx4_err(dev, "Fail to get physical port id\n");
1586
6634961c
JM		 1587 if (mlx4_is_master(dev))
1588 mlx4_parav_master_pf_caps(dev);
1589
ab9c17a0 1590 profile = default_profile;
0ff1fb65
HHZ		 1591 if (dev->caps.steering_mode ==
1592 MLX4_STEERING_MODE_DEVICE_MANAGED)
1593 profile.num_mcg = MLX4_FS_NUM_MCG;
225c7b1f 1594
ab9c17a0
JM		 1595 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
1596 &init_hca);
1597 if ((long long) icm_size < 0) {
1598 err = icm_size;
1599 goto err_stop_fw;
1600 }
225c7b1f 1601
a5bbe892
EC		 1602 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
1603
ab9c17a0
JM		 1604 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
1605 init_hca.uar_page_sz = PAGE_SHIFT - 12;
e448834e
SM		 1606 init_hca.mw_enabled = 0;
1607 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
1608 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
1609 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
c1b43dca 1610
ab9c17a0
JM		 1611 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
1612 if (err)
1613 goto err_stop_fw;
225c7b1f 1614
ab9c17a0
JM		 1615 err = mlx4_INIT_HCA(dev, &init_hca);
1616 if (err) {
1617 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
1618 goto err_free_icm;
1619 }
ddd8a6c1
EE		 1620 /*
1621 * If TS is supported by FW
1622 * read HCA frequency by QUERY_HCA command
1623 */
1624 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1625 memset(&init_hca, 0, sizeof(init_hca));
1626 err = mlx4_QUERY_HCA(dev, &init_hca);
1627 if (err) {
1628 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp.\n");
1629 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1630 } else {
1631 dev->caps.hca_core_clock =
1632 init_hca.hca_core_clock;
1633 }
1634
1635 /* In case we got HCA frequency 0 - disable timestamping
1636 * to avoid dividing by zero
1637 */
1638 if (!dev->caps.hca_core_clock) {
1639 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1640 mlx4_err(dev,
1641 "HCA frequency is 0. Timestamping is not supported.");
1642 } else if (map_internal_clock(dev)) {
1643 /*
1644 * Map internal clock,
1645 * in case of failure disable timestamping
1646 */
1647 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1648 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported.\n");
1649 }
1650 }
ab9c17a0
JM		 1651 } else {
1652 err = mlx4_init_slave(dev);
1653 if (err) {
5efe5355
JM		 1654 if (err != -EPROBE_DEFER)
1655 mlx4_err(dev, "Failed to initialize slave\n");
bef772eb 1656 return err;
ab9c17a0 1657 }
225c7b1f 1658
ab9c17a0
JM		 1659 err = mlx4_slave_cap(dev);
1660 if (err) {
1661 mlx4_err(dev, "Failed to obtain slave caps\n");
1662 goto err_close;
1663 }
225c7b1f
RD		 1664 }
1665
ab9c17a0
JM		 1666 if (map_bf_area(dev))
1667 mlx4_dbg(dev, "Failed to map blue flame area\n");
1668
1669 /*Only the master set the ports, all the rest got it from it.*/
1670 if (!mlx4_is_slave(dev))
1671 mlx4_set_port_mask(dev);
1672
225c7b1f
RD		 1673 err = mlx4_QUERY_ADAPTER(dev, &adapter);
1674 if (err) {
1675 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
bef772eb 1676 goto unmap_bf;
225c7b1f
RD		 1677 }
1678
1679 priv->eq_table.inta_pin = adapter.inta_pin;
cd9281d8 1680 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
225c7b1f
RD		 1681
1682 return 0;
1683
bef772eb 1684unmap_bf:
ddd8a6c1 1685 unmap_internal_clock(dev);
bef772eb
AY		 1686 unmap_bf_area(dev);
1687
225c7b1f 1688err_close:
41929ed2
DB		 1689 if (mlx4_is_slave(dev))
1690 mlx4_slave_exit(dev);
1691 else
1692 mlx4_CLOSE_HCA(dev, 0);
225c7b1f
RD		 1693
1694err_free_icm:
ab9c17a0
JM		 1695 if (!mlx4_is_slave(dev))
1696 mlx4_free_icms(dev);
225c7b1f
RD		 1697
1698err_stop_fw:
ab9c17a0
JM		 1699 if (!mlx4_is_slave(dev)) {
1700 mlx4_UNMAP_FA(dev);
1701 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1702 }
225c7b1f
RD		 1703 return err;
1704}
1705
f2a3f6a3
OG		 1706static int mlx4_init_counters_table(struct mlx4_dev *dev)
1707{
1708 struct mlx4_priv *priv = mlx4_priv(dev);
1709 int nent;
1710
1711 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1712 return -ENOENT;
1713
1714 nent = dev->caps.max_counters;
1715 return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
1716}
1717
1718static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
1719{
1720 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
1721}
1722
ba062d52 1723int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
f2a3f6a3
OG		 1724{
1725 struct mlx4_priv *priv = mlx4_priv(dev);
1726
1727 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
1728 return -ENOENT;
1729
1730 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
1731 if (*idx == -1)
1732 return -ENOMEM;
1733
1734 return 0;
1735}
ba062d52
JM		 1736
1737int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
1738{
1739 u64 out_param;
1740 int err;
1741
1742 if (mlx4_is_mfunc(dev)) {
1743 err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER,
1744 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
1745 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
1746 if (!err)
1747 *idx = get_param_l(&out_param);
1748
1749 return err;
1750 }
1751 return __mlx4_counter_alloc(dev, idx);
1752}
f2a3f6a3
OG		 1753EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
1754
ba062d52 1755void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
f2a3f6a3 1756{
7c6d74d2 1757 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
f2a3f6a3
OG		 1758 return;
1759}
ba062d52
JM		 1760
1761void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
1762{
e7dbeba8 1763 u64 in_param = 0;
ba062d52
JM		 1764
1765 if (mlx4_is_mfunc(dev)) {
1766 set_param_l(&in_param, idx);
1767 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
1768 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
1769 MLX4_CMD_WRAPPED);
1770 return;
1771 }
1772 __mlx4_counter_free(dev, idx);
1773}
f2a3f6a3
OG		 1774EXPORT_SYMBOL_GPL(mlx4_counter_free);
1775
3d73c288 1776static int mlx4_setup_hca(struct mlx4_dev *dev)
225c7b1f
RD		 1777{
1778 struct mlx4_priv *priv = mlx4_priv(dev);
1779 int err;
7ff93f8b 1780 int port;
9a5aa622 1781 __be32 ib_port_default_caps;
225c7b1f 1782
225c7b1f
RD		 1783 err = mlx4_init_uar_table(dev);
1784 if (err) {
1785 mlx4_err(dev, "Failed to initialize "
1786 "user access region table, aborting.\n");
1787 return err;
1788 }
1789
1790 err = mlx4_uar_alloc(dev, &priv->driver_uar);
1791 if (err) {
1792 mlx4_err(dev, "Failed to allocate driver access region, "
1793 "aborting.\n");
1794 goto err_uar_table_free;
1795 }
1796
4979d18f 1797 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
225c7b1f
RD		 1798 if (!priv->kar) {
1799 mlx4_err(dev, "Couldn't map kernel access region, "
1800 "aborting.\n");
1801 err = -ENOMEM;
1802 goto err_uar_free;
1803 }
1804
1805 err = mlx4_init_pd_table(dev);
1806 if (err) {
1807 mlx4_err(dev, "Failed to initialize "
1808 "protection domain table, aborting.\n");
1809 goto err_kar_unmap;
1810 }
1811
012a8ff5
SH		 1812 err = mlx4_init_xrcd_table(dev);
1813 if (err) {
1814 mlx4_err(dev, "Failed to initialize "
1815 "reliable connection domain table, aborting.\n");
1816 goto err_pd_table_free;
1817 }
1818
225c7b1f
RD		 1819 err = mlx4_init_mr_table(dev);
1820 if (err) {
1821 mlx4_err(dev, "Failed to initialize "
1822 "memory region table, aborting.\n");
012a8ff5 1823 goto err_xrcd_table_free;
225c7b1f
RD		 1824 }
1825
fe6f700d
YP		 1826 if (!mlx4_is_slave(dev)) {
1827 err = mlx4_init_mcg_table(dev);
1828 if (err) {
1829 mlx4_err(dev, "Failed to initialize multicast group table, aborting.\n");
1830 goto err_mr_table_free;
1831 }
1832 }
1833
225c7b1f
RD		 1834 err = mlx4_init_eq_table(dev);
1835 if (err) {
1836 mlx4_err(dev, "Failed to initialize "
1837 "event queue table, aborting.\n");
fe6f700d 1838 goto err_mcg_table_free;
225c7b1f
RD		 1839 }
1840
1841 err = mlx4_cmd_use_events(dev);
1842 if (err) {
1843 mlx4_err(dev, "Failed to switch to event-driven "
1844 "firmware commands, aborting.\n");
1845 goto err_eq_table_free;
1846 }
1847
1848 err = mlx4_NOP(dev);
1849 if (err) {
08fb1055
MT		 1850 if (dev->flags & MLX4_FLAG_MSI_X) {
1851 mlx4_warn(dev, "NOP command failed to generate MSI-X "
1852 "interrupt IRQ %d).\n",
b8dd786f 1853 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
08fb1055
MT		 1854 mlx4_warn(dev, "Trying again without MSI-X.\n");
1855 } else {
1856 mlx4_err(dev, "NOP command failed to generate interrupt "
1857 "(IRQ %d), aborting.\n",
b8dd786f 1858 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
225c7b1f 1859 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
08fb1055 1860 }
225c7b1f
RD		 1861
1862 goto err_cmd_poll;
1863 }
1864
1865 mlx4_dbg(dev, "NOP command IRQ test passed\n");
1866
1867 err = mlx4_init_cq_table(dev);
1868 if (err) {
1869 mlx4_err(dev, "Failed to initialize "
1870 "completion queue table, aborting.\n");
1871 goto err_cmd_poll;
1872 }
1873
1874 err = mlx4_init_srq_table(dev);
1875 if (err) {
1876 mlx4_err(dev, "Failed to initialize "
1877 "shared receive queue table, aborting.\n");
1878 goto err_cq_table_free;
1879 }
1880
1881 err = mlx4_init_qp_table(dev);
1882 if (err) {
1883 mlx4_err(dev, "Failed to initialize "
1884 "queue pair table, aborting.\n");
1885 goto err_srq_table_free;
1886 }
1887
f2a3f6a3
OG		 1888 err = mlx4_init_counters_table(dev);
1889 if (err && err != -ENOENT) {
1890 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
fe6f700d 1891 goto err_qp_table_free;
f2a3f6a3
OG		 1892 }
1893
ab9c17a0
JM		 1894 if (!mlx4_is_slave(dev)) {
1895 for (port = 1; port <= dev->caps.num_ports; port++) {
ab9c17a0
JM		 1896 ib_port_default_caps = 0;
1897 err = mlx4_get_port_ib_caps(dev, port,
1898 &ib_port_default_caps);
1899 if (err)
1900 mlx4_warn(dev, "failed to get port %d default "
1901 "ib capabilities (%d). Continuing "
1902 "with caps = 0\n", port, err);
1903 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1904
2aca1172
JM		 1905 /* initialize per-slave default ib port capabilities */
1906 if (mlx4_is_master(dev)) {
1907 int i;
1908 for (i = 0; i < dev->num_slaves; i++) {
1909 if (i == mlx4_master_func_num(dev))
1910 continue;
1911 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
1912 ib_port_default_caps;
1913 }
1914 }
1915
096335b3
OG		 1916 if (mlx4_is_mfunc(dev))
1917 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
1918 else
1919 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
97285b78 1920
6634961c
JM		 1921 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
1922 dev->caps.pkey_table_len[port] : -1);
ab9c17a0
JM		 1923 if (err) {
1924 mlx4_err(dev, "Failed to set port %d, aborting\n",
1925 port);
1926 goto err_counters_table_free;
1927 }
7ff93f8b
YP		 1928 }
1929 }
1930
225c7b1f
RD		 1931 return 0;
1932
f2a3f6a3
OG		 1933err_counters_table_free:
1934 mlx4_cleanup_counters_table(dev);
1935
225c7b1f
RD		 1936err_qp_table_free:
1937 mlx4_cleanup_qp_table(dev);
1938
1939err_srq_table_free:
1940 mlx4_cleanup_srq_table(dev);
1941
1942err_cq_table_free:
1943 mlx4_cleanup_cq_table(dev);
1944
1945err_cmd_poll:
1946 mlx4_cmd_use_polling(dev);
1947
1948err_eq_table_free:
1949 mlx4_cleanup_eq_table(dev);
1950
fe6f700d
YP		 1951err_mcg_table_free:
1952 if (!mlx4_is_slave(dev))
1953 mlx4_cleanup_mcg_table(dev);
1954
ee49bd93 1955err_mr_table_free:
225c7b1f
RD		 1956 mlx4_cleanup_mr_table(dev);
1957
012a8ff5
SH		 1958err_xrcd_table_free:
1959 mlx4_cleanup_xrcd_table(dev);
1960
225c7b1f
RD		 1961err_pd_table_free:
1962 mlx4_cleanup_pd_table(dev);
1963
1964err_kar_unmap:
1965 iounmap(priv->kar);
1966
1967err_uar_free:
1968 mlx4_uar_free(dev, &priv->driver_uar);
1969
1970err_uar_table_free:
1971 mlx4_cleanup_uar_table(dev);
1972 return err;
1973}
1974
e8f9b2ed 1975static void mlx4_enable_msi_x(struct mlx4_dev *dev)
225c7b1f
RD		 1976{
1977 struct mlx4_priv *priv = mlx4_priv(dev);
b8dd786f 1978 struct msix_entry *entries;
0b7ca5a9 1979 int nreq = min_t(int, dev->caps.num_ports *
bb2146bc 1980 min_t(int, num_online_cpus() + 1,
90b1ebe7 1981 MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX);
225c7b1f
RD		 1982 int i;
1983
1984 if (msi_x) {
ca4c7b35
OG		 1985 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1986 nreq);
ab9c17a0 1987
b8dd786f
YP		 1988 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1989 if (!entries)
1990 goto no_msi;
1991
1992 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 1993 entries[i].entry = i;
1994
66e2f9c1
AG		 1995 nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq);
1996
1997 if (nreq < 0) {
5bf0da7d 1998 kfree(entries);
225c7b1f 1999 goto no_msi;
66e2f9c1
AG		 2000 } else if (nreq < MSIX_LEGACY_SZ +
2001 dev->caps.num_ports * MIN_MSIX_P_PORT) {
0b7ca5a9
YP		 2002 /*Working in legacy mode , all EQ's shared*/
2003 dev->caps.comp_pool = 0;
2004 dev->caps.num_comp_vectors = nreq - 1;
2005 } else {
2006 dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ;
2007 dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
2008 }
b8dd786f 2009 for (i = 0; i < nreq; ++i)
225c7b1f
RD		 2010 priv->eq_table.eq[i].irq = entries[i].vector;
2011
2012 dev->flags |= MLX4_FLAG_MSI_X;
b8dd786f
YP		 2013
2014 kfree(entries);
225c7b1f
RD		 2015 return;
2016 }
2017
2018no_msi:
b8dd786f 2019 dev->caps.num_comp_vectors = 1;
0b7ca5a9 2020 dev->caps.comp_pool = 0;
b8dd786f
YP		 2021
2022 for (i = 0; i < 2; ++i)
225c7b1f
RD		 2023 priv->eq_table.eq[i].irq = dev->pdev->irq;
2024}
2025
7ff93f8b 2026static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2a2336f8
YP		 2027{
2028 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
7ff93f8b 2029 int err = 0;
2a2336f8
YP		 2030
2031 info->dev = dev;
2032 info->port = port;
ab9c17a0 2033 if (!mlx4_is_slave(dev)) {
ab9c17a0
JM		 2034 mlx4_init_mac_table(dev, &info->mac_table);
2035 mlx4_init_vlan_table(dev, &info->vlan_table);
16a10ffd 2036 info->base_qpn = mlx4_get_base_qpn(dev, port);
ab9c17a0 2037 }
7ff93f8b
YP		 2038
2039 sprintf(info->dev_name, "mlx4_port%d", port);
2040 info->port_attr.attr.name = info->dev_name;
ab9c17a0
JM		 2041 if (mlx4_is_mfunc(dev))
2042 info->port_attr.attr.mode = S_IRUGO;
2043 else {
2044 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
2045 info->port_attr.store = set_port_type;
2046 }
7ff93f8b 2047 info->port_attr.show = show_port_type;
3691c964 2048 sysfs_attr_init(&info->port_attr.attr);
7ff93f8b
YP		 2049
2050 err = device_create_file(&dev->pdev->dev, &info->port_attr);
2051 if (err) {
2052 mlx4_err(dev, "Failed to create file for port %d\n", port);
2053 info->port = -1;
2054 }
2055
096335b3
OG		 2056 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2057 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2058 if (mlx4_is_mfunc(dev))
2059 info->port_mtu_attr.attr.mode = S_IRUGO;
2060 else {
2061 info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR;
2062 info->port_mtu_attr.store = set_port_ib_mtu;
2063 }
2064 info->port_mtu_attr.show = show_port_ib_mtu;
2065 sysfs_attr_init(&info->port_mtu_attr.attr);
2066
2067 err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr);
2068 if (err) {
2069 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2070 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
2071 info->port = -1;
2072 }
2073
7ff93f8b
YP		 2074 return err;
2075}
2076
2077static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2078{
2079 if (info->port < 0)
2080 return;
2081
2082 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
096335b3 2083 device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr);
2a2336f8
YP		 2084}
2085
b12d93d6
YP		 2086static int mlx4_init_steering(struct mlx4_dev *dev)
2087{
2088 struct mlx4_priv *priv = mlx4_priv(dev);
2089 int num_entries = dev->caps.num_ports;
2090 int i, j;
2091
2092 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2093 if (!priv->steer)
2094 return -ENOMEM;
2095
45b51365 2096 for (i = 0; i < num_entries; i++)
b12d93d6
YP		 2097 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2098 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2099 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2100 }
b12d93d6
YP		 2101 return 0;
2102}
2103
2104static void mlx4_clear_steering(struct mlx4_dev *dev)
2105{
2106 struct mlx4_priv *priv = mlx4_priv(dev);
2107 struct mlx4_steer_index *entry, *tmp_entry;
2108 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2109 int num_entries = dev->caps.num_ports;
2110 int i, j;
2111
2112 for (i = 0; i < num_entries; i++) {
2113 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2114 list_for_each_entry_safe(pqp, tmp_pqp,
2115 &priv->steer[i].promisc_qps[j],
2116 list) {
2117 list_del(&pqp->list);
2118 kfree(pqp);
2119 }
2120 list_for_each_entry_safe(entry, tmp_entry,
2121 &priv->steer[i].steer_entries[j],
2122 list) {
2123 list_del(&entry->list);
2124 list_for_each_entry_safe(pqp, tmp_pqp,
2125 &entry->duplicates,
2126 list) {
2127 list_del(&pqp->list);
2128 kfree(pqp);
2129 }
2130 kfree(entry);
2131 }
2132 }
2133 }
2134 kfree(priv->steer);
2135}
2136
ab9c17a0
JM		 2137static int extended_func_num(struct pci_dev *pdev)
2138{
2139 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
2140}
2141
2142#define MLX4_OWNER_BASE 0x8069c
2143#define MLX4_OWNER_SIZE 4
2144
2145static int mlx4_get_ownership(struct mlx4_dev *dev)
2146{
2147 void __iomem *owner;
2148 u32 ret;
2149
57dbf29a
KSS		 2150 if (pci_channel_offline(dev->pdev))
2151 return -EIO;
2152
ab9c17a0
JM		 2153 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2154 MLX4_OWNER_SIZE);
2155 if (!owner) {
2156 mlx4_err(dev, "Failed to obtain ownership bit\n");
2157 return -ENOMEM;
2158 }
2159
2160 ret = readl(owner);
2161 iounmap(owner);
2162 return (int) !!ret;
2163}
2164
2165static void mlx4_free_ownership(struct mlx4_dev *dev)
2166{
2167 void __iomem *owner;
2168
57dbf29a
KSS		 2169 if (pci_channel_offline(dev->pdev))
2170 return;
2171
ab9c17a0
JM		 2172 owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE,
2173 MLX4_OWNER_SIZE);
2174 if (!owner) {
2175 mlx4_err(dev, "Failed to obtain ownership bit\n");
2176 return;
2177 }
2178 writel(0, owner);
2179 msleep(1000);
2180 iounmap(owner);
2181}
2182
839f1243 2183static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data)
225c7b1f 2184{
225c7b1f
RD		 2185 struct mlx4_priv *priv;
2186 struct mlx4_dev *dev;
2187 int err;
2a2336f8 2188 int port;
225c7b1f 2189
0a645e80 2190 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
225c7b1f
RD		 2191
2192 err = pci_enable_device(pdev);
2193 if (err) {
2194 dev_err(&pdev->dev, "Cannot enable PCI device, "
2195 "aborting.\n");
2196 return err;
2197 }
5a0d0a61
JM		 2198
2199 /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS
2200 * per port, we must limit the number of VFs to 63 (since their are
2201 * 128 MACs)
2202 */
2203 if (num_vfs >= MLX4_MAX_NUM_VF) {
2204 dev_err(&pdev->dev,
2205 "Requested more VF's (%d) than allowed (%d)\n",
2206 num_vfs, MLX4_MAX_NUM_VF - 1);
ab9c17a0
JM		 2207 return -EINVAL;
2208 }
30e514a7
JM		 2209
2210 if (num_vfs < 0) {
2211 pr_err("num_vfs module parameter cannot be negative\n");
2212 return -EINVAL;
2213 }
225c7b1f 2214 /*
ab9c17a0 2215 * Check for BARs.
225c7b1f 2216 */
839f1243 2217 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
ab9c17a0
JM		 2218 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2219 dev_err(&pdev->dev, "Missing DCS, aborting."
839f1243
RD		 2220 "(driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
2221 pci_dev_data, pci_resource_flags(pdev, 0));
225c7b1f
RD		 2222 err = -ENODEV;
2223 goto err_disable_pdev;
2224 }
2225 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
2226 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
2227 err = -ENODEV;
2228 goto err_disable_pdev;
2229 }
2230
a01df0fe 2231 err = pci_request_regions(pdev, DRV_NAME);
225c7b1f 2232 if (err) {
a01df0fe 2233 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
225c7b1f
RD		 2234 goto err_disable_pdev;
2235 }
2236
225c7b1f
RD		 2237 pci_set_master(pdev);
2238
6a35528a 2239 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2240 if (err) {
2241 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
284901a9 2242 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2243 if (err) {
2244 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
a01df0fe 2245 goto err_release_regions;
225c7b1f
RD		 2246 }
2247 }
6a35528a 2248 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
225c7b1f
RD		 2249 if (err) {
2250 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
2251 "consistent PCI DMA mask.\n");
284901a9 2252 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
225c7b1f
RD		 2253 if (err) {
2254 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
2255 "aborting.\n");
a01df0fe 2256 goto err_release_regions;
225c7b1f
RD		 2257 }
2258 }
2259
7f9e5c48
DD		 2260 /* Allow large DMA segments, up to the firmware limit of 1 GB */
2261 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
2262
b2adaca9 2263 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
225c7b1f 2264 if (!priv) {
225c7b1f 2265 err = -ENOMEM;
a01df0fe 2266 goto err_release_regions;
225c7b1f
RD		 2267 }
2268
2269 dev = &priv->dev;
2270 dev->pdev = pdev;
b581401e
RD		 2271 INIT_LIST_HEAD(&priv->ctx_list);
2272 spin_lock_init(&priv->ctx_lock);
225c7b1f 2273
7ff93f8b
YP		 2274 mutex_init(&priv->port_mutex);
2275
6296883c
YP		 2276 INIT_LIST_HEAD(&priv->pgdir_list);
2277 mutex_init(&priv->pgdir_mutex);
2278
c1b43dca
EC		 2279 INIT_LIST_HEAD(&priv->bf_list);
2280 mutex_init(&priv->bf_mutex);
2281
aca7a3ac 2282 dev->rev_id = pdev->revision;
6e7136ed 2283 dev->numa_node = dev_to_node(&pdev->dev);
ab9c17a0 2284 /* Detect if this device is a virtual function */
839f1243 2285 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
ab9c17a0
JM		 2286 /* When acting as pf, we normally skip vfs unless explicitly
2287 * requested to probe them. */
2288 if (num_vfs && extended_func_num(pdev) > probe_vf) {
2289 mlx4_warn(dev, "Skipping virtual function:%d\n",
2290 extended_func_num(pdev));
2291 err = -ENODEV;
2292 goto err_free_dev;
2293 }
2294 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
2295 dev->flags |= MLX4_FLAG_SLAVE;
2296 } else {
2297 /* We reset the device and enable SRIOV only for physical
2298 * devices. Try to claim ownership on the device;
2299 * if already taken, skip -- do not allow multiple PFs */
2300 err = mlx4_get_ownership(dev);
2301 if (err) {
2302 if (err < 0)
2303 goto err_free_dev;
2304 else {
2305 mlx4_warn(dev, "Multiple PFs not yet supported."
2306 " Skipping PF.\n");
2307 err = -EINVAL;
2308 goto err_free_dev;
2309 }
2310 }
aca7a3ac 2311
ab9c17a0 2312 if (num_vfs) {
84b1f153 2313 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", num_vfs);
ab9c17a0
JM		 2314 err = pci_enable_sriov(pdev, num_vfs);
2315 if (err) {
84b1f153
RD		 2316 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d).\n",
2317 err);
ab9c17a0
JM		 2318 err = 0;
2319 } else {
2320 mlx4_warn(dev, "Running in master mode\n");
2321 dev->flags |= MLX4_FLAG_SRIOV |
2322 MLX4_FLAG_MASTER;
2323 dev->num_vfs = num_vfs;
2324 }
2325 }
2326
fe6f700d
YP		 2327 atomic_set(&priv->opreq_count, 0);
2328 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
2329
ab9c17a0
JM		 2330 /*
2331 * Now reset the HCA before we touch the PCI capabilities or
2332 * attempt a firmware command, since a boot ROM may have left
2333 * the HCA in an undefined state.
2334 */
2335 err = mlx4_reset(dev);
2336 if (err) {
2337 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
2338 goto err_rel_own;
2339 }
225c7b1f
RD		 2340 }
2341
ab9c17a0 2342slave_start:
521130d1
EE		 2343 err = mlx4_cmd_init(dev);
2344 if (err) {
225c7b1f 2345 mlx4_err(dev, "Failed to init command interface, aborting.\n");
ab9c17a0
JM		 2346 goto err_sriov;
2347 }
2348
2349 /* In slave functions, the communication channel must be initialized
2350 * before posting commands. Also, init num_slaves before calling
2351 * mlx4_init_hca */
2352 if (mlx4_is_mfunc(dev)) {
2353 if (mlx4_is_master(dev))
2354 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
2355 else {
2356 dev->num_slaves = 0;
f356fcbe
JM		 2357 err = mlx4_multi_func_init(dev);
2358 if (err) {
ab9c17a0
JM		 2359 mlx4_err(dev, "Failed to init slave mfunc"
2360 " interface, aborting.\n");
2361 goto err_cmd;
2362 }
2363 }
225c7b1f
RD		 2364 }
2365
2366 err = mlx4_init_hca(dev);
ab9c17a0
JM		 2367 if (err) {
2368 if (err == -EACCES) {
2369 /* Not primary Physical function
2370 * Running in slave mode */
2371 mlx4_cmd_cleanup(dev);
2372 dev->flags |= MLX4_FLAG_SLAVE;
2373 dev->flags &= ~MLX4_FLAG_MASTER;
2374 goto slave_start;
2375 } else
2376 goto err_mfunc;
2377 }
2378
b912b2f8
EP		 2379 /* check if the device is functioning at its maximum possible speed.
2380 * No return code for this call, just warn the user in case of PCI
2381 * express device capabilities are under-satisfied by the bus.
2382 */
2383 mlx4_check_pcie_caps(dev);
2384
ab9c17a0
JM		 2385 /* In master functions, the communication channel must be initialized
2386 * after obtaining its address from fw */
2387 if (mlx4_is_master(dev)) {
f356fcbe
JM		 2388 err = mlx4_multi_func_init(dev);
2389 if (err) {
ab9c17a0
JM		 2390 mlx4_err(dev, "Failed to init master mfunc"
2391 "interface, aborting.\n");
2392 goto err_close;
2393 }
2394 }
225c7b1f 2395
b8dd786f
YP		 2396 err = mlx4_alloc_eq_table(dev);
2397 if (err)
ab9c17a0 2398 goto err_master_mfunc;
b8dd786f 2399
0b7ca5a9 2400 priv->msix_ctl.pool_bm = 0;
730c41d5 2401 mutex_init(&priv->msix_ctl.pool_lock);
0b7ca5a9 2402
08fb1055 2403 mlx4_enable_msi_x(dev);
ab9c17a0
JM		 2404 if ((mlx4_is_mfunc(dev)) &&
2405 !(dev->flags & MLX4_FLAG_MSI_X)) {
f356fcbe 2406 err = -ENOSYS;
ab9c17a0
JM		 2407 mlx4_err(dev, "INTx is not supported in multi-function mode."
2408 " aborting.\n");
b12d93d6 2409 goto err_free_eq;
ab9c17a0
JM		 2410 }
2411
2412 if (!mlx4_is_slave(dev)) {
2413 err = mlx4_init_steering(dev);
2414 if (err)
2415 goto err_free_eq;
2416 }
b12d93d6 2417
225c7b1f 2418 err = mlx4_setup_hca(dev);
ab9c17a0
JM		 2419 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
2420 !mlx4_is_mfunc(dev)) {
08fb1055 2421 dev->flags &= ~MLX4_FLAG_MSI_X;
9858d2d1
YP		 2422 dev->caps.num_comp_vectors = 1;
2423 dev->caps.comp_pool = 0;
08fb1055
MT		 2424 pci_disable_msix(pdev);
2425 err = mlx4_setup_hca(dev);
2426 }
2427
225c7b1f 2428 if (err)
b12d93d6 2429 goto err_steer;
225c7b1f 2430
5a0d0a61
JM		 2431 mlx4_init_quotas(dev);
2432
7ff93f8b
YP		 2433 for (port = 1; port <= dev->caps.num_ports; port++) {
2434 err = mlx4_init_port_info(dev, port);
2435 if (err)
2436 goto err_port;
2437 }
2a2336f8 2438
225c7b1f
RD		 2439 err = mlx4_register_device(dev);
2440 if (err)
7ff93f8b 2441 goto err_port;
225c7b1f 2442
b046ffe5
EP		 2443 mlx4_request_modules(dev);
2444
27bf91d6
YP		 2445 mlx4_sense_init(dev);
2446 mlx4_start_sense(dev);
2447
839f1243 2448 priv->pci_dev_data = pci_dev_data;
225c7b1f
RD		 2449 pci_set_drvdata(pdev, dev);
2450
2451 return 0;
2452
7ff93f8b 2453err_port:
b4f77264 2454 for (--port; port >= 1; --port)
7ff93f8b
YP		 2455 mlx4_cleanup_port_info(&priv->port[port]);
2456
f2a3f6a3 2457 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2458 mlx4_cleanup_qp_table(dev);
2459 mlx4_cleanup_srq_table(dev);
2460 mlx4_cleanup_cq_table(dev);
2461 mlx4_cmd_use_polling(dev);
2462 mlx4_cleanup_eq_table(dev);
fe6f700d 2463 mlx4_cleanup_mcg_table(dev);
225c7b1f 2464 mlx4_cleanup_mr_table(dev);
012a8ff5 2465 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2466 mlx4_cleanup_pd_table(dev);
2467 mlx4_cleanup_uar_table(dev);
2468
b12d93d6 2469err_steer:
ab9c17a0
JM		 2470 if (!mlx4_is_slave(dev))
2471 mlx4_clear_steering(dev);
b12d93d6 2472
b8dd786f
YP		 2473err_free_eq:
2474 mlx4_free_eq_table(dev);
2475
ab9c17a0
JM		 2476err_master_mfunc:
2477 if (mlx4_is_master(dev))
2478 mlx4_multi_func_cleanup(dev);
2479
225c7b1f 2480err_close:
08fb1055
MT		 2481 if (dev->flags & MLX4_FLAG_MSI_X)
2482 pci_disable_msix(pdev);
2483
225c7b1f
RD		 2484 mlx4_close_hca(dev);
2485
ab9c17a0
JM		 2486err_mfunc:
2487 if (mlx4_is_slave(dev))
2488 mlx4_multi_func_cleanup(dev);
2489
225c7b1f
RD		 2490err_cmd:
2491 mlx4_cmd_cleanup(dev);
2492
ab9c17a0 2493err_sriov:
681372a7 2494 if (dev->flags & MLX4_FLAG_SRIOV)
ab9c17a0
JM		 2495 pci_disable_sriov(pdev);
2496
2497err_rel_own:
2498 if (!mlx4_is_slave(dev))
2499 mlx4_free_ownership(dev);
2500
225c7b1f 2501err_free_dev:
225c7b1f
RD		 2502 kfree(priv);
2503
a01df0fe
RD		 2504err_release_regions:
2505 pci_release_regions(pdev);
225c7b1f
RD		 2506
2507err_disable_pdev:
2508 pci_disable_device(pdev);
2509 pci_set_drvdata(pdev, NULL);
2510 return err;
2511}
2512
1dd06ae8 2513static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3d73c288 2514{
0a645e80 2515 printk_once(KERN_INFO "%s", mlx4_version);
3d73c288 2516
839f1243 2517 return __mlx4_init_one(pdev, id->driver_data);
3d73c288
RD		 2518}
2519
2520static void mlx4_remove_one(struct pci_dev *pdev)
225c7b1f
RD		 2521{
2522 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2523 struct mlx4_priv *priv = mlx4_priv(dev);
2524 int p;
2525
2526 if (dev) {
ab9c17a0
JM		 2527 /* in SRIOV it is not allowed to unload the pf's
2528 * driver while there are alive vf's */
2529 if (mlx4_is_master(dev)) {
2530 if (mlx4_how_many_lives_vf(dev))
2531 printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n");
2532 }
27bf91d6 2533 mlx4_stop_sense(dev);
225c7b1f
RD		 2534 mlx4_unregister_device(dev);
2535
7ff93f8b
YP		 2536 for (p = 1; p <= dev->caps.num_ports; p++) {
2537 mlx4_cleanup_port_info(&priv->port[p]);
225c7b1f 2538 mlx4_CLOSE_PORT(dev, p);
7ff93f8b 2539 }
225c7b1f 2540
b8924951
JM		 2541 if (mlx4_is_master(dev))
2542 mlx4_free_resource_tracker(dev,
2543 RES_TR_FREE_SLAVES_ONLY);
2544
f2a3f6a3 2545 mlx4_cleanup_counters_table(dev);
225c7b1f
RD		 2546 mlx4_cleanup_qp_table(dev);
2547 mlx4_cleanup_srq_table(dev);
2548 mlx4_cleanup_cq_table(dev);
2549 mlx4_cmd_use_polling(dev);
2550 mlx4_cleanup_eq_table(dev);
fe6f700d 2551 mlx4_cleanup_mcg_table(dev);
225c7b1f 2552 mlx4_cleanup_mr_table(dev);
012a8ff5 2553 mlx4_cleanup_xrcd_table(dev);
225c7b1f
RD		 2554 mlx4_cleanup_pd_table(dev);
2555
ab9c17a0 2556 if (mlx4_is_master(dev))
b8924951
JM		 2557 mlx4_free_resource_tracker(dev,
2558 RES_TR_FREE_STRUCTS_ONLY);
ab9c17a0 2559
225c7b1f
RD		 2560 iounmap(priv->kar);
2561 mlx4_uar_free(dev, &priv->driver_uar);
2562 mlx4_cleanup_uar_table(dev);
ab9c17a0
JM		 2563 if (!mlx4_is_slave(dev))
2564 mlx4_clear_steering(dev);
b8dd786f 2565 mlx4_free_eq_table(dev);
ab9c17a0
JM		 2566 if (mlx4_is_master(dev))
2567 mlx4_multi_func_cleanup(dev);
225c7b1f 2568 mlx4_close_hca(dev);
ab9c17a0
JM		 2569 if (mlx4_is_slave(dev))
2570 mlx4_multi_func_cleanup(dev);
225c7b1f
RD		 2571 mlx4_cmd_cleanup(dev);
2572
2573 if (dev->flags & MLX4_FLAG_MSI_X)
2574 pci_disable_msix(pdev);
681372a7 2575 if (dev->flags & MLX4_FLAG_SRIOV) {
84b1f153 2576 mlx4_warn(dev, "Disabling SR-IOV\n");
ab9c17a0
JM		 2577 pci_disable_sriov(pdev);
2578 }
225c7b1f 2579
ab9c17a0
JM		 2580 if (!mlx4_is_slave(dev))
2581 mlx4_free_ownership(dev);
47605df9
JM		 2582
2583 kfree(dev->caps.qp0_tunnel);
2584 kfree(dev->caps.qp0_proxy);
2585 kfree(dev->caps.qp1_tunnel);
2586 kfree(dev->caps.qp1_proxy);
2587
225c7b1f 2588 kfree(priv);
a01df0fe 2589 pci_release_regions(pdev);
225c7b1f
RD		 2590 pci_disable_device(pdev);
2591 pci_set_drvdata(pdev, NULL);
2592 }
2593}
2594
ee49bd93
JM		 2595int mlx4_restart_one(struct pci_dev *pdev)
2596{
839f1243
RD		 2597 struct mlx4_dev *dev = pci_get_drvdata(pdev);
2598 struct mlx4_priv *priv = mlx4_priv(dev);
2599 int pci_dev_data;
2600
2601 pci_dev_data = priv->pci_dev_data;
ee49bd93 2602 mlx4_remove_one(pdev);
839f1243 2603 return __mlx4_init_one(pdev, pci_dev_data);
ee49bd93
JM		 2604}
2605
a3aa1884 2606static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
ab9c17a0 2607 /* MT25408 "Hermon" SDR */
ca3e57a5 2608 { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2609 /* MT25408 "Hermon" DDR */
ca3e57a5 2610 { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2611 /* MT25408 "Hermon" QDR */
ca3e57a5 2612 { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2613 /* MT25408 "Hermon" DDR PCIe gen2 */
ca3e57a5 2614 { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2615 /* MT25408 "Hermon" QDR PCIe gen2 */
ca3e57a5 2616 { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2617 /* MT25408 "Hermon" EN 10GigE */
ca3e57a5 2618 { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2619 /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
ca3e57a5 2620 { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2621 /* MT25458 ConnectX EN 10GBASE-T 10GigE */
ca3e57a5 2622 { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2623 /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
ca3e57a5 2624 { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2625 /* MT26468 ConnectX EN 10GigE PCIe gen2*/
ca3e57a5 2626 { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2627 /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
ca3e57a5 2628 { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2629 /* MT26478 ConnectX2 40GigE PCIe gen2 */
ca3e57a5 2630 { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT },
ab9c17a0 2631 /* MT25400 Family [ConnectX-2 Virtual Function] */
839f1243 2632 { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2633 /* MT27500 Family [ConnectX-3] */
2634 { PCI_VDEVICE(MELLANOX, 0x1003), 0 },
2635 /* MT27500 Family [ConnectX-3 Virtual Function] */
839f1243 2636 { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF },
ab9c17a0
JM		 2637 { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */
2638 { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */
2639 { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */
2640 { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */
2641 { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */
2642 { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */
2643 { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */
2644 { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */
2645 { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */
2646 { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */
2647 { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */
2648 { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */
225c7b1f
RD		 2649 { 0, }
2650};
2651
2652MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
2653
57dbf29a
KSS		 2654static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
2655 pci_channel_state_t state)
2656{
2657 mlx4_remove_one(pdev);
2658
2659 return state == pci_channel_io_perm_failure ?
2660 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
2661}
2662
2663static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
2664{
839f1243 2665 int ret = __mlx4_init_one(pdev, 0);
57dbf29a
KSS		 2666
2667 return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
2668}
2669
3646f0e5 2670static const struct pci_error_handlers mlx4_err_handler = {
57dbf29a
KSS		 2671 .error_detected = mlx4_pci_err_detected,
2672 .slot_reset = mlx4_pci_slot_reset,
2673};
2674
225c7b1f
RD		 2675static struct pci_driver mlx4_driver = {
2676 .name = DRV_NAME,
2677 .id_table = mlx4_pci_table,
2678 .probe = mlx4_init_one,
f57e6848 2679 .remove = mlx4_remove_one,
57dbf29a 2680 .err_handler = &mlx4_err_handler,
225c7b1f
RD		 2681};
2682
7ff93f8b
YP		 2683static int __init mlx4_verify_params(void)
2684{
2685 if ((log_num_mac < 0) || (log_num_mac > 7)) {
0a645e80 2686 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
7ff93f8b
YP		 2687 return -1;
2688 }
2689
cb29688a
OG		 2690 if (log_num_vlan != 0)
2691 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
2692 MLX4_LOG_NUM_VLANS);
7ff93f8b 2693
0498628f 2694 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
0a645e80 2695 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
ab6bf42e
EC		 2696 return -1;
2697 }
2698
ab9c17a0
JM		 2699 /* Check if module param for ports type has legal combination */
2700 if (port_type_array[0] == false && port_type_array[1] == true) {
2701 printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
2702 port_type_array[0] = true;
2703 }
2704
3c439b55
JM		 2705 if (mlx4_log_num_mgm_entry_size != -1 &&
2706 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
2707 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) {
2708 pr_warning("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not "
2709 "in legal range (-1 or %d..%d)\n",
2710 mlx4_log_num_mgm_entry_size,
2711 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
2712 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
2713 return -1;
2714 }
2715
7ff93f8b
YP		 2716 return 0;
2717}
2718
225c7b1f
RD		 2719static int __init mlx4_init(void)
2720{
2721 int ret;
2722
7ff93f8b
YP		 2723 if (mlx4_verify_params())
2724 return -EINVAL;
2725
27bf91d6
YP		 2726 mlx4_catas_init();
2727
2728 mlx4_wq = create_singlethread_workqueue("mlx4");
2729 if (!mlx4_wq)
2730 return -ENOMEM;
ee49bd93 2731
225c7b1f 2732 ret = pci_register_driver(&mlx4_driver);
1b85ee09
WY		 2733 if (ret < 0)
2734 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2735 return ret < 0 ? ret : 0;
2736}
2737
2738static void __exit mlx4_cleanup(void)
2739{
2740 pci_unregister_driver(&mlx4_driver);
27bf91d6 2741 destroy_workqueue(mlx4_wq);
225c7b1f
RD		 2742}
2743
2744module_init(mlx4_init);
2745module_exit(mlx4_cleanup);
Linux 6.x block layer and io_uring tree(s)