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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2006, 2007 Cisco Systems. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #ifndef MLX4_FW_H | |
36 | #define MLX4_FW_H | |
37 | ||
38 | #include "mlx4.h" | |
39 | #include "icm.h" | |
40 | ||
2d928651 VS |
41 | struct mlx4_mod_stat_cfg { |
42 | u8 log_pg_sz; | |
43 | u8 log_pg_sz_m; | |
44 | }; | |
45 | ||
225c7b1f RD |
46 | struct mlx4_dev_cap { |
47 | int max_srq_sz; | |
48 | int max_qp_sz; | |
49 | int reserved_qps; | |
50 | int max_qps; | |
51 | int reserved_srqs; | |
52 | int max_srqs; | |
53 | int max_cq_sz; | |
54 | int reserved_cqs; | |
55 | int max_cqs; | |
56 | int max_mpts; | |
57 | int reserved_eqs; | |
58 | int max_eqs; | |
59 | int reserved_mtts; | |
60 | int max_mrw_sz; | |
61 | int reserved_mrws; | |
62 | int max_mtt_seg; | |
63 | int max_requester_per_qp; | |
64 | int max_responder_per_qp; | |
65 | int max_rdma_global; | |
66 | int local_ca_ack_delay; | |
225c7b1f | 67 | int num_ports; |
149983af | 68 | u32 max_msg_sz; |
b79acb49 | 69 | int ib_mtu[MLX4_MAX_PORTS + 1]; |
5ae2a7a8 RD |
70 | int max_port_width[MLX4_MAX_PORTS + 1]; |
71 | int max_vl[MLX4_MAX_PORTS + 1]; | |
72 | int max_gids[MLX4_MAX_PORTS + 1]; | |
73 | int max_pkeys[MLX4_MAX_PORTS + 1]; | |
b79acb49 YP |
74 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
75 | u16 eth_mtu[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
76 | int trans_type[MLX4_MAX_PORTS + 1]; |
77 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
78 | u16 wavelength[MLX4_MAX_PORTS + 1]; | |
79 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f | 80 | u16 stat_rate_support; |
0ff1fb65 HHZ |
81 | int fs_log_max_ucast_qp_range_size; |
82 | int fs_max_num_qp_per_entry; | |
52eafc68 | 83 | u64 flags; |
b3416f44 | 84 | u64 flags2; |
225c7b1f RD |
85 | int reserved_uars; |
86 | int uar_size; | |
87 | int min_page_sz; | |
88 | int bf_reg_size; | |
89 | int bf_regs_per_page; | |
90 | int max_sq_sg; | |
91 | int max_sq_desc_sz; | |
92 | int max_rq_sg; | |
93 | int max_rq_desc_sz; | |
94 | int max_qp_per_mcg; | |
95 | int reserved_mgms; | |
96 | int max_mcgs; | |
97 | int reserved_pds; | |
98 | int max_pds; | |
012a8ff5 SH |
99 | int reserved_xrcds; |
100 | int max_xrcds; | |
225c7b1f RD |
101 | int qpc_entry_sz; |
102 | int rdmarc_entry_sz; | |
103 | int altc_entry_sz; | |
104 | int aux_entry_sz; | |
105 | int srq_entry_sz; | |
106 | int cqc_entry_sz; | |
107 | int eqc_entry_sz; | |
108 | int dmpt_entry_sz; | |
109 | int cmpt_entry_sz; | |
110 | int mtt_entry_sz; | |
111 | int resize_srq; | |
95d04f07 | 112 | u32 bmme_flags; |
225c7b1f RD |
113 | u32 reserved_lkey; |
114 | u64 max_icm_sz; | |
b832be1e | 115 | int max_gso_sz; |
b3416f44 | 116 | int max_rss_tbl_sz; |
7ff93f8b | 117 | u8 supported_port_types[MLX4_MAX_PORTS + 1]; |
8d0fc7b6 YP |
118 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
119 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
93fc9e1b YP |
120 | u8 log_max_macs[MLX4_MAX_PORTS + 1]; |
121 | u8 log_max_vlans[MLX4_MAX_PORTS + 1]; | |
f2a3f6a3 | 122 | u32 max_counters; |
225c7b1f RD |
123 | }; |
124 | ||
5cc914f1 | 125 | struct mlx4_func_cap { |
5cc914f1 MA |
126 | u8 num_ports; |
127 | u8 flags; | |
128 | u32 pf_context_behaviour; | |
129 | int qp_quota; | |
130 | int cq_quota; | |
131 | int srq_quota; | |
132 | int mpt_quota; | |
133 | int mtt_quota; | |
134 | int max_eq; | |
135 | int reserved_eq; | |
136 | int mcg_quota; | |
137 | u8 physical_port[MLX4_MAX_PORTS + 1]; | |
138 | u8 port_flags[MLX4_MAX_PORTS + 1]; | |
139 | }; | |
140 | ||
225c7b1f | 141 | struct mlx4_adapter { |
225c7b1f RD |
142 | char board_id[MLX4_BOARD_ID_LEN]; |
143 | u8 inta_pin; | |
144 | }; | |
145 | ||
146 | struct mlx4_init_hca_param { | |
147 | u64 qpc_base; | |
148 | u64 rdmarc_base; | |
149 | u64 auxc_base; | |
150 | u64 altc_base; | |
151 | u64 srqc_base; | |
152 | u64 cqc_base; | |
153 | u64 eqc_base; | |
154 | u64 mc_base; | |
155 | u64 dmpt_base; | |
156 | u64 cmpt_base; | |
157 | u64 mtt_base; | |
5cc914f1 | 158 | u64 global_caps; |
225c7b1f RD |
159 | u16 log_mc_entry_sz; |
160 | u16 log_mc_hash_sz; | |
161 | u8 log_num_qps; | |
162 | u8 log_num_srqs; | |
163 | u8 log_num_cqs; | |
164 | u8 log_num_eqs; | |
165 | u8 log_rd_per_qp; | |
166 | u8 log_mc_table_sz; | |
167 | u8 log_mpt_sz; | |
168 | u8 log_uar_sz; | |
ab9c17a0 | 169 | u8 uar_page_sz; /* log pg sz in 4k chunks */ |
0ff1fb65 | 170 | u8 fs_hash_enable_bits; |
225c7b1f RD |
171 | }; |
172 | ||
173 | struct mlx4_init_ib_param { | |
174 | int port_width; | |
175 | int vl_cap; | |
176 | int mtu_cap; | |
177 | u16 gid_cap; | |
178 | u16 pkey_cap; | |
179 | int set_guid0; | |
180 | u64 guid0; | |
181 | int set_node_guid; | |
182 | u64 node_guid; | |
183 | int set_si_guid; | |
184 | u64 si_guid; | |
185 | }; | |
186 | ||
187 | struct mlx4_set_ib_param { | |
188 | int set_si_guid; | |
189 | int reset_qkey_viol; | |
190 | u64 si_guid; | |
191 | u32 cap_mask; | |
192 | }; | |
193 | ||
194 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap); | |
5cc914f1 MA |
195 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap); |
196 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, | |
197 | struct mlx4_vhcr *vhcr, | |
198 | struct mlx4_cmd_mailbox *inbox, | |
199 | struct mlx4_cmd_mailbox *outbox, | |
200 | struct mlx4_cmd_info *cmd); | |
225c7b1f RD |
201 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm); |
202 | int mlx4_UNMAP_FA(struct mlx4_dev *dev); | |
203 | int mlx4_RUN_FW(struct mlx4_dev *dev); | |
204 | int mlx4_QUERY_FW(struct mlx4_dev *dev); | |
205 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter); | |
206 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); | |
ab9c17a0 | 207 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param); |
225c7b1f RD |
208 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic); |
209 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt); | |
210 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages); | |
211 | int mlx4_MAP_ICM_AUX(struct mlx4_dev *dev, struct mlx4_icm *icm); | |
212 | int mlx4_UNMAP_ICM_AUX(struct mlx4_dev *dev); | |
213 | int mlx4_NOP(struct mlx4_dev *dev); | |
2d928651 | 214 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg); |
225c7b1f RD |
215 | |
216 | #endif /* MLX4_FW_H */ |