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net/mlx4: remove unneeded semicolon
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / eq.c
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225c7b1f 1/*
51a379d0 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
225c7b1f 34#include <linux/interrupt.h>
5a0e3ad6 35#include <linux/slab.h>
ee40fa06 36#include <linux/export.h>
27ac792c 37#include <linux/mm.h>
9cbe05c7 38#include <linux/dma-mapping.h>
225c7b1f
RD		 39
40#include <linux/mlx4/cmd.h>
d9236c3f 41#include <linux/cpu_rmap.h>
225c7b1f
RD		 42
43#include "mlx4.h"
44#include "fw.h"
45
f5f5951c 46enum {
0b7ca5a9 47 MLX4_IRQNAME_SIZE = 32
f5f5951c
AB		 48};
49
225c7b1f
RD		 50enum {
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
54};
55
225c7b1f
RD		 56#define MLX4_EQ_STATUS_OK ( 0 << 28)
57#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58#define MLX4_EQ_OWNER_SW ( 0 << 24)
59#define MLX4_EQ_OWNER_HW ( 1 << 24)
60#define MLX4_EQ_FLAG_EC ( 1 << 18)
61#define MLX4_EQ_FLAG_OI ( 1 << 17)
62#define MLX4_EQ_STATE_ARMED ( 9 << 8)
63#define MLX4_EQ_STATE_FIRED (10 << 8)
64#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
65
66#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
225c7b1f
RD		 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
acba2420 80 (1ull << MLX4_EVENT_TYPE_CMD) | \
fe6f700d 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
acba2420 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
5984be90
JM		 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
225c7b1f 85
00f5ce99
JM		 86static u64 get_async_ev_mask(struct mlx4_dev *dev)
87{
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
be6a6b43
JM		 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT);
00f5ce99
JM		 93
94 return async_ev_mask;
95}
96
225c7b1f
RD		 97static void eq_set_ci(struct mlx4_eq *eq, int req_not)
98{
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 req_not << 31),
101 eq->doorbell);
102 /* We still want ordering, just not swabbing, so add a barrier */
103 mb();
104}
105
43c816c6
IS		 106static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
107 u8 eqe_size)
225c7b1f 108{
08ff3235 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */
43c816c6
IS		 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with
112 * strides of 64B,128B and 256B.
113 * When 64B EQE is used, the first (in the lower addresses)
08ff3235
OG		 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
115 * contain the legacy EQE information.
43c816c6 116 * In all other cases, the first 32B contains the legacy EQE info.
08ff3235
OG		 117 */
118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
225c7b1f
RD		 119}
120
43c816c6 121static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
225c7b1f 122{
43c816c6 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
225c7b1f
RD		 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
125}
126
acba2420
JM		 127static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
128{
129 struct mlx4_eqe *eqe =
130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
131 return (!!(eqe->owner & 0x80) ^
132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
133 eqe : NULL;
134}
135
acba2420
JM		 136void mlx4_gen_slave_eqe(struct work_struct *work)
137{
138 struct mlx4_mfunc_master_ctx *master =
139 container_of(work, struct mlx4_mfunc_master_ctx,
140 slave_event_work);
141 struct mlx4_mfunc *mfunc =
142 container_of(master, struct mlx4_mfunc, master);
143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
144 struct mlx4_dev *dev = &priv->dev;
145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
146 struct mlx4_eqe *eqe;
147 u8 slave;
74d4943f 148 int i, phys_port, slave_port;
acba2420
JM		 149
150 for (eqe = next_slave_event_eqe(slave_eq); eqe;
151 eqe = next_slave_event_eqe(slave_eq)) {
152 slave = eqe->slave_id;
153
8d80d04a
MS		 154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE &&
155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN &&
156 mlx4_is_bonded(dev)) {
157 struct mlx4_port_cap port_cap;
158
159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state)
160 goto consume;
161
162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state)
163 goto consume;
164 }
acba2420
JM		 165 /* All active slaves need to receive the event */
166 if (slave == ALL_SLAVES) {
bffb023a 167 for (i = 0; i <= dev->persist->num_vfs; i++) {
74d4943f
OG		 168 phys_port = 0;
169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT &&
170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) {
171 phys_port = eqe->event.port_mgmt_change.port;
172 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port);
173 if (slave_port < 0) /* VF doesn't have this port */
174 continue;
175 eqe->event.port_mgmt_change.port = slave_port;
176 }
bffb023a
JM		 177 if (mlx4_GEN_EQE(dev, i, eqe))
178 mlx4_warn(dev, "Failed to generate event for slave %d\n",
179 i);
74d4943f
OG		 180 if (phys_port)
181 eqe->event.port_mgmt_change.port = phys_port;
acba2420
JM		 182 }
183 } else {
184 if (mlx4_GEN_EQE(dev, slave, eqe))
1a91de28
JP		 185 mlx4_warn(dev, "Failed to generate event for slave %d\n",
186 slave);
acba2420 187 }
8d80d04a 188consume:
acba2420
JM		 189 ++slave_eq->cons;
190 }
191}
192
193
194static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
195{
196 struct mlx4_priv *priv = mlx4_priv(dev);
197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
992e8e6e
JM		 198 struct mlx4_eqe *s_eqe;
199 unsigned long flags;
acba2420 200
992e8e6e
JM		 201 spin_lock_irqsave(&slave_eq->event_lock, flags);
202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
acba2420
JM		 203 if ((!!(s_eqe->owner & 0x80)) ^
204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
1a91de28
JP		 205 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
206 slave);
992e8e6e 207 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
acba2420
JM		 208 return;
209 }
210
c02b0501 211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
acba2420
JM		 212 s_eqe->slave_id = slave;
213 /* ensure all information is written before setting the ownersip bit */
12b3375f 214 dma_wmb();
acba2420
JM		 215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
216 ++slave_eq->prod;
217
218 queue_work(priv->mfunc.master.comm_wq,
219 &priv->mfunc.master.slave_event_work);
992e8e6e 220 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
acba2420
JM		 221}
222
223static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
224 struct mlx4_eqe *eqe)
225{
226 struct mlx4_priv *priv = mlx4_priv(dev);
acba2420 227
bffb023a
JM		 228 if (slave < 0 || slave > dev->persist->num_vfs ||
229 slave == dev->caps.function ||
230 !priv->mfunc.master.slave_state[slave].active)
acba2420 231 return;
acba2420
JM		 232
233 slave_event(dev, slave, eqe);
234}
235
db9777e3 236#if defined(CONFIG_SMP)
de161803
IS		 237static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec)
238{
239 int hint_err;
240 struct mlx4_dev *dev = &priv->dev;
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec];
242
8ac1ee6f
NC		 243 if (!cpumask_available(eq->affinity_mask) ||
244 cpumask_empty(eq->affinity_mask))
de161803
IS		 245 return;
246
247 hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask);
248 if (hint_err)
249 mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err);
250}
db9777e3 251#endif
de161803 252
993c401e
JM		 253int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
254{
255 struct mlx4_eqe eqe;
256
257 struct mlx4_priv *priv = mlx4_priv(dev);
258 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
259
260 if (!s_slave->active)
261 return 0;
262
31975e27 263 memset(&eqe, 0, sizeof(eqe));
993c401e
JM		 264
265 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
266 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
74d4943f 267 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 268
269 return mlx4_GEN_EQE(dev, slave, &eqe);
270}
271EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
272
273int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
274{
275 struct mlx4_eqe eqe;
276
277 /*don't send if we don't have the that slave */
872bf2fb 278 if (dev->persist->num_vfs < slave)
993c401e 279 return 0;
31975e27 280 memset(&eqe, 0, sizeof(eqe));
993c401e
JM		 281
282 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
283 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
74d4943f 284 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 285
286 return mlx4_GEN_EQE(dev, slave, &eqe);
287}
288EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
289
290int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
291 u8 port_subtype_change)
292{
293 struct mlx4_eqe eqe;
74d4943f 294 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 295
296 /*don't send if we don't have the that slave */
872bf2fb 297 if (dev->persist->num_vfs < slave)
993c401e 298 return 0;
31975e27 299 memset(&eqe, 0, sizeof(eqe));
993c401e
JM		 300
301 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
302 eqe.subtype = port_subtype_change;
74d4943f 303 eqe.event.port_change.port = cpu_to_be32(slave_port << 28);
993c401e
JM		 304
305 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
306 port_subtype_change, slave, port);
307 return mlx4_GEN_EQE(dev, slave, &eqe);
308}
309EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
310
311enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
312{
313 struct mlx4_priv *priv = mlx4_priv(dev);
314 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
449fc488
MB		 315 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
316
317 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
318 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 319 pr_err("%s: Error: asking for slave:%d, port:%d\n",
320 __func__, slave, port);
321 return SLAVE_PORT_DOWN;
322 }
323 return s_state[slave].port_state[port];
324}
325EXPORT_SYMBOL(mlx4_get_slave_port_state);
326
327static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
328 enum slave_port_state state)
329{
330 struct mlx4_priv *priv = mlx4_priv(dev);
331 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
449fc488 332 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
993c401e 333
449fc488
MB		 334 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
335 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 336 pr_err("%s: Error: asking for slave:%d, port:%d\n",
337 __func__, slave, port);
338 return -1;
339 }
340 s_state[slave].port_state[port] = state;
341
342 return 0;
343}
344
345static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
346{
347 int i;
348 enum slave_port_gen_event gen_event;
449fc488
MB		 349 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
350 port);
993c401e 351
872bf2fb 352 for (i = 0; i < dev->persist->num_vfs + 1; i++)
449fc488
MB		 353 if (test_bit(i, slaves_pport.slaves))
354 set_and_calc_slave_port_state(dev, i, port,
355 event, &gen_event);
993c401e
JM		 356}
357/**************************************************************************
358 The function get as input the new event to that port,
359 and according to the prev state change the slave's port state.
360 The events are:
361 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
362 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
363 MLX4_PORT_STATE_IB_EVENT_GID_VALID
364 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
365***************************************************************************/
366int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
367 u8 port, int event,
368 enum slave_port_gen_event *gen_event)
369{
370 struct mlx4_priv *priv = mlx4_priv(dev);
371 struct mlx4_slave_state *ctx = NULL;
372 unsigned long flags;
373 int ret = -1;
449fc488 374 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
993c401e
JM		 375 enum slave_port_state cur_state =
376 mlx4_get_slave_port_state(dev, slave, port);
377
378 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
379
449fc488
MB		 380 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
381 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 382 pr_err("%s: Error: asking for slave:%d, port:%d\n",
383 __func__, slave, port);
384 return ret;
385 }
386
387 ctx = &priv->mfunc.master.slave_state[slave];
388 spin_lock_irqsave(&ctx->lock, flags);
389
993c401e
JM		 390 switch (cur_state) {
391 case SLAVE_PORT_DOWN:
392 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
393 mlx4_set_slave_port_state(dev, slave, port,
394 SLAVE_PENDING_UP);
395 break;
396 case SLAVE_PENDING_UP:
397 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
398 mlx4_set_slave_port_state(dev, slave, port,
399 SLAVE_PORT_DOWN);
400 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
401 mlx4_set_slave_port_state(dev, slave, port,
402 SLAVE_PORT_UP);
403 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
404 }
405 break;
406 case SLAVE_PORT_UP:
407 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
408 mlx4_set_slave_port_state(dev, slave, port,
409 SLAVE_PORT_DOWN);
410 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
411 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
412 event) {
413 mlx4_set_slave_port_state(dev, slave, port,
414 SLAVE_PENDING_UP);
415 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
416 }
417 break;
418 default:
1a91de28
JP		 419 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
420 __func__, slave, port);
421 goto out;
993c401e
JM		 422 }
423 ret = mlx4_get_slave_port_state(dev, slave, port);
993c401e
JM		 424
425out:
426 spin_unlock_irqrestore(&ctx->lock, flags);
427 return ret;
428}
429
430EXPORT_SYMBOL(set_and_calc_slave_port_state);
431
432int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
433{
434 struct mlx4_eqe eqe;
435
31975e27 436 memset(&eqe, 0, sizeof(eqe));
993c401e
JM		 437
438 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
439 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
440 eqe.event.port_mgmt_change.port = port;
441 eqe.event.port_mgmt_change.params.port_info.changed_attr =
442 cpu_to_be32((u32) attr);
443
444 slave_event(dev, ALL_SLAVES, &eqe);
445 return 0;
446}
447EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
448
acba2420
JM		 449void mlx4_master_handle_slave_flr(struct work_struct *work)
450{
451 struct mlx4_mfunc_master_ctx *master =
452 container_of(work, struct mlx4_mfunc_master_ctx,
453 slave_flr_event_work);
454 struct mlx4_mfunc *mfunc =
455 container_of(master, struct mlx4_mfunc, master);
456 struct mlx4_priv *priv =
457 container_of(mfunc, struct mlx4_priv, mfunc);
458 struct mlx4_dev *dev = &priv->dev;
459 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
460 int i;
461 int err;
311f813a 462 unsigned long flags;
acba2420
JM		 463
464 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
465
466 for (i = 0 ; i < dev->num_slaves; i++) {
467
468 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
1a91de28
JP		 469 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
470 i);
55ad3592
YH		 471 /* In case of 'Reset flow' FLR can be generated for
472 * a slave before mlx4_load_one is done.
473 * make sure interface is up before trying to delete
474 * slave resources which weren't allocated yet.
475 */
476 if (dev->persist->interface_state &
477 MLX4_INTERFACE_STATE_UP)
478 mlx4_delete_all_resources_for_slave(dev, i);
acba2420 479 /*return the slave to running mode*/
311f813a 480 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 481 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
482 slave_state[i].is_slave_going_down = 0;
311f813a 483 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 484 /*notify the FW:*/
485 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
486 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
487 if (err)
1a91de28
JP		 488 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
489 i);
acba2420
JM		 490 }
491 }
492}
493
225c7b1f
RD		 494static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
495{
acba2420 496 struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f 497 struct mlx4_eqe *eqe;
01f0f425 498 int cqn;
225c7b1f
RD		 499 int eqes_found = 0;
500 int set_ci = 0;
27bf91d6 501 int port;
acba2420
JM		 502 int slave = 0;
503 int ret;
504 u32 flr_slave;
505 u8 update_slave_state;
506 int i;
993c401e 507 enum slave_port_gen_event gen_event;
311f813a 508 unsigned long flags;
948e306d 509 struct mlx4_vport_state *s_info;
43c816c6 510 int eqe_size = dev->caps.eqe_size;
225c7b1f 511
43c816c6 512 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
225c7b1f
RD		 513 /*
514 * Make sure we read EQ entry contents after we've
515 * checked the ownership bit.
516 */
12b3375f 517 dma_rmb();
225c7b1f
RD		 518
519 switch (eqe->type) {
520 case MLX4_EVENT_TYPE_COMP:
521 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
522 mlx4_cq_completion(dev, cqn);
523 break;
524
525 case MLX4_EVENT_TYPE_PATH_MIG:
526 case MLX4_EVENT_TYPE_COMM_EST:
527 case MLX4_EVENT_TYPE_SQ_DRAINED:
528 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
529 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
530 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
531 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
532 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
acba2420
JM		 533 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
534 if (mlx4_is_master(dev)) {
535 /* forward only to slave owning the QP */
536 ret = mlx4_get_slave_from_resource_id(dev,
537 RES_QP,
538 be32_to_cpu(eqe->event.qp.qpn)
539 & 0xffffff, &slave);
540 if (ret && ret != -ENOENT) {
1a91de28 541 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
acba2420
JM		 542 eqe->type, eqe->subtype,
543 eq->eqn, eq->cons_index, ret);
544 break;
545 }
546
547 if (!ret && slave != dev->caps.function) {
548 mlx4_slave_event(dev, slave, eqe);
549 break;
550 }
551
552 }
553 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
554 0xffffff, eqe->type);
225c7b1f
RD		 555 break;
556
557 case MLX4_EVENT_TYPE_SRQ_LIMIT:
9577b174
JM		 558 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
559 __func__, be32_to_cpu(eqe->event.srq.srqn),
560 eq->eqn);
225c7b1f 561 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
acba2420
JM		 562 if (mlx4_is_master(dev)) {
563 /* forward only to slave owning the SRQ */
564 ret = mlx4_get_slave_from_resource_id(dev,
565 RES_SRQ,
566 be32_to_cpu(eqe->event.srq.srqn)
567 & 0xffffff,
568 &slave);
569 if (ret && ret != -ENOENT) {
1a91de28 570 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
acba2420
JM		 571 eqe->type, eqe->subtype,
572 eq->eqn, eq->cons_index, ret);
573 break;
574 }
9577b174
JM		 575 if (eqe->type ==
576 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
577 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
578 __func__, slave,
579 be32_to_cpu(eqe->event.srq.srqn),
580 eqe->type, eqe->subtype);
acba2420
JM		 581
582 if (!ret && slave != dev->caps.function) {
9577b174
JM		 583 if (eqe->type ==
584 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
585 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
586 __func__, eqe->type,
587 eqe->subtype, slave);
acba2420
JM		 588 mlx4_slave_event(dev, slave, eqe);
589 break;
590 }
591 }
592 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
593 0xffffff, eqe->type);
225c7b1f
RD		 594 break;
595
596 case MLX4_EVENT_TYPE_CMD:
597 mlx4_cmd_event(dev,
598 be16_to_cpu(eqe->event.cmd.token),
599 eqe->event.cmd.status,
600 be64_to_cpu(eqe->event.cmd.out_param));
601 break;
602
449fc488
MB		 603 case MLX4_EVENT_TYPE_PORT_CHANGE: {
604 struct mlx4_slaves_pport slaves_port;
27bf91d6 605 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
449fc488 606 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
27bf91d6 607 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
993c401e 608 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
27bf91d6
YP		 609 port);
610 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
993c401e
JM		 611 if (!mlx4_is_master(dev))
612 break;
872bf2fb
YH		 613 for (i = 0; i < dev->persist->num_vfs + 1;
614 i++) {
8d80d04a
MS		 615 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
616
617 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
449fc488 618 continue;
993c401e
JM		 619 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
620 if (i == mlx4_master_func_num(dev))
621 continue;
1a91de28 622 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
acba2420 623 __func__, i, port);
1c1bf349 624 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
449fc488
MB		 625 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
626 eqe->event.port_change.port =
627 cpu_to_be32(
628 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
8d80d04a 629 | (reported_port << 28));
948e306d 630 mlx4_slave_event(dev, i, eqe);
449fc488 631 }
993c401e
JM		 632 } else { /* IB port */
633 set_and_calc_slave_port_state(dev, i, port,
634 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
635 &gen_event);
636 /*we can be in pending state, then do not send port_down event*/
637 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
638 if (i == mlx4_master_func_num(dev))
639 continue;
74d4943f
OG		 640 eqe->event.port_change.port =
641 cpu_to_be32(
642 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
643 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
993c401e
JM		 644 mlx4_slave_event(dev, i, eqe);
645 }
acba2420 646 }
993c401e 647 }
27bf91d6 648 } else {
993c401e
JM		 649 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
650
27bf91d6 651 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
acba2420 652
993c401e
JM		 653 if (!mlx4_is_master(dev))
654 break;
655 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
872bf2fb
YH		 656 for (i = 0;
657 i < dev->persist->num_vfs + 1;
658 i++) {
8d80d04a
MS		 659 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
660
661 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
449fc488 662 continue;
993c401e 663 if (i == mlx4_master_func_num(dev))
acba2420 664 continue;
1c1bf349 665 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
449fc488
MB		 666 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
667 eqe->event.port_change.port =
668 cpu_to_be32(
669 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
8d80d04a 670 | (reported_port << 28));
948e306d 671 mlx4_slave_event(dev, i, eqe);
449fc488 672 }
acba2420 673 }
993c401e
JM		 674 else /* IB port */
675 /* port-up event will be sent to a slave when the
676 * slave's alias-guid is set. This is done in alias_GUID.c
677 */
678 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
27bf91d6 679 }
225c7b1f 680 break;
449fc488 681 }
225c7b1f
RD		 682
683 case MLX4_EVENT_TYPE_CQ_ERROR:
684 mlx4_warn(dev, "CQ %s on CQN %06x\n",
685 eqe->event.cq_err.syndrome == 1 ?
686 "overrun" : "access violation",
687 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
acba2420
JM		 688 if (mlx4_is_master(dev)) {
689 ret = mlx4_get_slave_from_resource_id(dev,
690 RES_CQ,
691 be32_to_cpu(eqe->event.cq_err.cqn)
692 & 0xffffff, &slave);
693 if (ret && ret != -ENOENT) {
1a91de28
JP		 694 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
695 eqe->type, eqe->subtype,
696 eq->eqn, eq->cons_index, ret);
acba2420
JM		 697 break;
698 }
699
700 if (!ret && slave != dev->caps.function) {
701 mlx4_slave_event(dev, slave, eqe);
702 break;
703 }
704 }
705 mlx4_cq_event(dev,
706 be32_to_cpu(eqe->event.cq_err.cqn)
707 & 0xffffff,
225c7b1f
RD		 708 eqe->type);
709 break;
710
711 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
712 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
713 break;
714
fe6f700d
YP		 715 case MLX4_EVENT_TYPE_OP_REQUIRED:
716 atomic_inc(&priv->opreq_count);
717 /* FW commands can't be executed from interrupt context
718 * working in deferred task
719 */
720 queue_work(mlx4_wq, &priv->opreq_task);
721 break;
722
acba2420
JM		 723 case MLX4_EVENT_TYPE_COMM_CHANNEL:
724 if (!mlx4_is_master(dev)) {
1a91de28 725 mlx4_warn(dev, "Received comm channel event for non master device\n");
acba2420
JM		 726 break;
727 }
728 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
729 eqe->event.comm_channel_arm.bit_vec,
a434f1fd 730 sizeof(eqe->event.comm_channel_arm.bit_vec));
acba2420
JM		 731 queue_work(priv->mfunc.master.comm_wq,
732 &priv->mfunc.master.comm_work);
733 break;
734
735 case MLX4_EVENT_TYPE_FLR_EVENT:
736 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
737 if (!mlx4_is_master(dev)) {
1a91de28 738 mlx4_warn(dev, "Non-master function received FLR event\n");
acba2420
JM		 739 break;
740 }
741
742 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
743
30f7c73b 744 if (flr_slave >= dev->num_slaves) {
acba2420
JM		 745 mlx4_warn(dev,
746 "Got FLR for unknown function: %d\n",
747 flr_slave);
748 update_slave_state = 0;
749 } else
750 update_slave_state = 1;
751
311f813a 752 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 753 if (update_slave_state) {
754 priv->mfunc.master.slave_state[flr_slave].active = false;
755 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
756 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
757 }
311f813a 758 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
a0667a83
YH		 759 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN,
760 flr_slave);
acba2420
JM		 761 queue_work(priv->mfunc.master.comm_wq,
762 &priv->mfunc.master.slave_flr_event_work);
763 break;
5984be90
JM		 764
765 case MLX4_EVENT_TYPE_FATAL_WARNING:
766 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
767 if (mlx4_is_master(dev))
768 for (i = 0; i < dev->num_slaves; i++) {
1a91de28
JP		 769 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
770 __func__, i);
5984be90
JM		 771 if (i == dev->caps.function)
772 continue;
773 mlx4_slave_event(dev, i, eqe);
774 }
1a91de28
JP		 775 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
776 be16_to_cpu(eqe->event.warming.warning_threshold),
777 be16_to_cpu(eqe->event.warming.current_temperature));
5984be90 778 } else
1a91de28 779 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
5984be90
JM		 780 eqe->type, eqe->subtype, eq->eqn,
781 eq->cons_index, eqe->owner, eq->nent,
782 eqe->slave_id,
783 !!(eqe->owner & 0x80) ^
784 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
785
786 break;
787
00f5ce99
JM		 788 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
789 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
790 (unsigned long) eqe);
791 break;
792
be6a6b43
JM		 793 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT:
794 switch (eqe->subtype) {
795 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE:
796 mlx4_warn(dev, "Bad cable detected on port %u\n",
797 eqe->event.bad_cable.port);
798 break;
799 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE:
800 mlx4_warn(dev, "Unsupported cable detected\n");
801 break;
802 default:
803 mlx4_dbg(dev,
804 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n",
805 eqe->type, eqe->subtype, eq->eqn,
806 eq->cons_index, eqe->owner, eq->nent,
807 !!(eqe->owner & 0x80) ^
808 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
809 break;
810 }
811 break;
812
225c7b1f
RD		 813 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
814 case MLX4_EVENT_TYPE_ECC_DETECT:
815 default:
1a91de28 816 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
acba2420
JM		 817 eqe->type, eqe->subtype, eq->eqn,
818 eq->cons_index, eqe->owner, eq->nent,
819 eqe->slave_id,
820 !!(eqe->owner & 0x80) ^
821 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
225c7b1f 822 break;
bec03deb 823 }
225c7b1f
RD		 824
825 ++eq->cons_index;
826 eqes_found = 1;
827 ++set_ci;
828
829 /*
830 * The HCA will think the queue has overflowed if we
831 * don't tell it we've been processing events. We
832 * create our EQs with MLX4_NUM_SPARE_EQE extra
833 * entries, so we must update our consumer index at
834 * least that often.
835 */
836 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
225c7b1f
RD		 837 eq_set_ci(eq, 0);
838 set_ci = 0;
839 }
840 }
841
842 eq_set_ci(eq, 1);
843
844 return eqes_found;
845}
846
847static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
848{
849 struct mlx4_dev *dev = dev_ptr;
850 struct mlx4_priv *priv = mlx4_priv(dev);
851 int work = 0;
852 int i;
853
854 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
855
b8dd786f 856 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f
RD		 857 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
858
859 return IRQ_RETVAL(work);
860}
861
862static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
863{
864 struct mlx4_eq *eq = eq_ptr;
865 struct mlx4_dev *dev = eq->dev;
866
867 mlx4_eq_int(dev, eq);
868
869 /* MSI-X vectors always belong to us */
870 return IRQ_HANDLED;
871}
872
acba2420
JM		 873int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
874 struct mlx4_vhcr *vhcr,
875 struct mlx4_cmd_mailbox *inbox,
876 struct mlx4_cmd_mailbox *outbox,
877 struct mlx4_cmd_info *cmd)
878{
879 struct mlx4_priv *priv = mlx4_priv(dev);
880 struct mlx4_slave_event_eq_info *event_eq =
803143fb 881 priv->mfunc.master.slave_state[slave].event_eq;
acba2420 882 u32 in_modifier = vhcr->in_modifier;
c101c81b 883 u32 eqn = in_modifier & 0x3FF;
acba2420
JM		 884 u64 in_param = vhcr->in_param;
885 int err = 0;
803143fb 886 int i;
acba2420
JM		 887
888 if (slave == dev->caps.function)
889 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
890 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
891 MLX4_CMD_NATIVE);
803143fb
MA		 892 if (!err)
893 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
894 if (in_param & (1LL << i))
895 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
896
acba2420
JM		 897 return err;
898}
899
225c7b1f
RD		 900static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
901 int eq_num)
902{
903 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
f9baff50
JM		 904 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
905 MLX4_CMD_WRAPPED);
225c7b1f
RD		 906}
907
908static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
909 int eq_num)
910{
eb41049f 911 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
acba2420 912 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
f9baff50 913 MLX4_CMD_WRAPPED);
225c7b1f
RD		 914}
915
30a5da5b 916static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num)
225c7b1f 917{
30a5da5b
JM		 918 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
919 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 920}
921
b8dd786f
YP		 922static int mlx4_num_eq_uar(struct mlx4_dev *dev)
923{
924 /*
925 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
926 * we need to map, take the difference of highest index and
927 * the lowest index we'll use and add 1.
928 */
c66fa19c
MB		 929 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
930 dev->caps.reserved_eqs / 4 + 1;
b8dd786f
YP		 931}
932
3d73c288 933static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
225c7b1f
RD		 934{
935 struct mlx4_priv *priv = mlx4_priv(dev);
936 int index;
937
938 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
939
940 if (!priv->eq_table.uar_map[index]) {
941 priv->eq_table.uar_map[index] =
85743f1e
HN		 942 ioremap(
943 pci_resource_start(dev->persist->pdev, 2) +
944 ((eq->eqn / 4) << (dev->uar_page_shift)),
945 (1 << (dev->uar_page_shift)));
225c7b1f
RD		 946 if (!priv->eq_table.uar_map[index]) {
947 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
948 eq->eqn);
949 return NULL;
950 }
951 }
952
953 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
954}
955
bfc0d8c3
DB		 956static void mlx4_unmap_uar(struct mlx4_dev *dev)
957{
958 struct mlx4_priv *priv = mlx4_priv(dev);
959 int i;
960
961 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
962 if (priv->eq_table.uar_map[i]) {
963 iounmap(priv->eq_table.uar_map[i]);
964 priv->eq_table.uar_map[i] = NULL;
965 }
966}
967
3d73c288
RD		 968static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
969 u8 intr, struct mlx4_eq *eq)
225c7b1f
RD		 970{
971 struct mlx4_priv *priv = mlx4_priv(dev);
972 struct mlx4_cmd_mailbox *mailbox;
973 struct mlx4_eq_context *eq_context;
974 int npages;
975 u64 *dma_list = NULL;
976 dma_addr_t t;
977 u64 mtt_addr;
978 int err = -ENOMEM;
979 int i;
980
981 eq->dev = dev;
982 eq->nent = roundup_pow_of_two(max(nent, 2));
43c816c6
IS		 983 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
984 * strides of 64B,128B and 256B.
985 */
986 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
225c7b1f 987
31975e27 988 eq->page_list = kmalloc_array(npages, sizeof(*eq->page_list),
989 GFP_KERNEL);
225c7b1f
RD		 990 if (!eq->page_list)
991 goto err_out;
992
993 for (i = 0; i < npages; ++i)
994 eq->page_list[i].buf = NULL;
995
31975e27 996 dma_list = kmalloc_array(npages, sizeof(*dma_list), GFP_KERNEL);
225c7b1f
RD		 997 if (!dma_list)
998 goto err_out_free;
999
1000 mailbox = mlx4_alloc_cmd_mailbox(dev);
1001 if (IS_ERR(mailbox))
1002 goto err_out_free;
1003 eq_context = mailbox->buf;
1004
1005 for (i = 0; i < npages; ++i) {
872bf2fb
YH		 1006 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
1007 pdev->dev,
1008 PAGE_SIZE, &t,
1009 GFP_KERNEL);
225c7b1f
RD		 1010 if (!eq->page_list[i].buf)
1011 goto err_out_free_pages;
1012
1013 dma_list[i] = t;
1014 eq->page_list[i].map = t;
1015
1016 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
1017 }
1018
1019 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
1020 if (eq->eqn == -1)
1021 goto err_out_free_pages;
1022
1023 eq->doorbell = mlx4_get_eq_uar(dev, eq);
1024 if (!eq->doorbell) {
1025 err = -ENOMEM;
1026 goto err_out_free_eq;
1027 }
1028
1029 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
1030 if (err)
1031 goto err_out_free_eq;
1032
1033 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
1034 if (err)
1035 goto err_out_free_mtt;
1036
225c7b1f
RD		 1037 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
1038 MLX4_EQ_STATE_ARMED);
1039 eq_context->log_eq_size = ilog2(eq->nent);
1040 eq_context->intr = intr;
1041 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
1042
1043 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
1044 eq_context->mtt_base_addr_h = mtt_addr >> 32;
1045 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
1046
1047 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
1048 if (err) {
1049 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
1050 goto err_out_free_mtt;
1051 }
1052
1053 kfree(dma_list);
1054 mlx4_free_cmd_mailbox(dev, mailbox);
1055
1056 eq->cons_index = 0;
1057
3dca0f42
MB		 1058 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1059 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1060 spin_lock_init(&eq->tasklet_ctx.lock);
1061 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
1062 (unsigned long)&eq->tasklet_ctx);
1063
225c7b1f
RD		 1064 return err;
1065
1066err_out_free_mtt:
1067 mlx4_mtt_cleanup(dev, &eq->mtt);
1068
1069err_out_free_eq:
7c6d74d2 1070 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
225c7b1f
RD		 1071
1072err_out_free_pages:
1073 for (i = 0; i < npages; ++i)
1074 if (eq->page_list[i].buf)
872bf2fb 1075 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
225c7b1f
RD		 1076 eq->page_list[i].buf,
1077 eq->page_list[i].map);
1078
1079 mlx4_free_cmd_mailbox(dev, mailbox);
1080
1081err_out_free:
1082 kfree(eq->page_list);
1083 kfree(dma_list);
1084
1085err_out:
1086 return err;
1087}
1088
1089static void mlx4_free_eq(struct mlx4_dev *dev,
1090 struct mlx4_eq *eq)
1091{
1092 struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f 1093 int err;
225c7b1f 1094 int i;
43c816c6
IS		 1095 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1096 * strides of 64B,128B and 256B
1097 */
1098 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
225c7b1f 1099
30a5da5b 1100 err = mlx4_HW2SW_EQ(dev, eq->eqn);
225c7b1f
RD		 1101 if (err)
1102 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1103
bf1bac5b 1104 synchronize_irq(eq->irq);
3dca0f42 1105 tasklet_disable(&eq->tasklet_ctx.task);
225c7b1f
RD		 1106
1107 mlx4_mtt_cleanup(dev, &eq->mtt);
1108 for (i = 0; i < npages; ++i)
872bf2fb
YH		 1109 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1110 eq->page_list[i].buf,
1111 eq->page_list[i].map);
225c7b1f
RD		 1112
1113 kfree(eq->page_list);
7c6d74d2 1114 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
225c7b1f
RD		 1115}
1116
1117static void mlx4_free_irqs(struct mlx4_dev *dev)
1118{
1119 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
c66fa19c 1120 int i;
225c7b1f
RD		 1121
1122 if (eq_table->have_irq)
872bf2fb 1123 free_irq(dev->persist->pdev->irq, dev);
0b7ca5a9 1124
b8dd786f 1125 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
d1fdf24b 1126 if (eq_table->eq[i].have_irq) {
de161803
IS		 1127 free_cpumask_var(eq_table->eq[i].affinity_mask);
1128#if defined(CONFIG_SMP)
1129 irq_set_affinity_hint(eq_table->eq[i].irq, NULL);
1130#endif
225c7b1f 1131 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
d1fdf24b
RD		 1132 eq_table->eq[i].have_irq = 0;
1133 }
b8dd786f
YP		 1134
1135 kfree(eq_table->irq_names);
225c7b1f
RD		 1136}
1137
3d73c288 1138static int mlx4_map_clr_int(struct mlx4_dev *dev)
225c7b1f
RD		 1139{
1140 struct mlx4_priv *priv = mlx4_priv(dev);
1141
872bf2fb
YH		 1142 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1143 priv->fw.clr_int_bar) +
225c7b1f
RD		 1144 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1145 if (!priv->clr_base) {
1a91de28 1146 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
225c7b1f
RD		 1147 return -ENOMEM;
1148 }
1149
1150 return 0;
1151}
1152
1153static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1154{
1155 struct mlx4_priv *priv = mlx4_priv(dev);
1156
1157 iounmap(priv->clr_base);
1158}
1159
b8dd786f
YP		 1160int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1161{
1162 struct mlx4_priv *priv = mlx4_priv(dev);
1163
1164 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
31975e27 1165 sizeof(*priv->eq_table.eq), GFP_KERNEL);
b8dd786f
YP		 1166 if (!priv->eq_table.eq)
1167 return -ENOMEM;
1168
1169 return 0;
1170}
1171
1172void mlx4_free_eq_table(struct mlx4_dev *dev)
1173{
1174 kfree(mlx4_priv(dev)->eq_table.eq);
1175}
1176
3d73c288 1177int mlx4_init_eq_table(struct mlx4_dev *dev)
225c7b1f
RD		 1178{
1179 struct mlx4_priv *priv = mlx4_priv(dev);
1180 int err;
1181 int i;
1182
758ff235 1183 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
31975e27 1184 sizeof(*priv->eq_table.uar_map),
758ff235 1185 GFP_KERNEL);
b8dd786f
YP		 1186 if (!priv->eq_table.uar_map) {
1187 err = -ENOMEM;
1188 goto err_out_free;
1189 }
1190
7ae0e400
MB		 1191 err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1192 roundup_pow_of_two(dev->caps.num_eqs),
1193 dev->caps.num_eqs - 1,
1194 dev->caps.reserved_eqs,
1195 roundup_pow_of_two(dev->caps.num_eqs) -
1196 dev->caps.num_eqs);
225c7b1f 1197 if (err)
b8dd786f 1198 goto err_out_free;
225c7b1f 1199
b8dd786f 1200 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f
RD		 1201 priv->eq_table.uar_map[i] = NULL;
1202
acba2420
JM		 1203 if (!mlx4_is_slave(dev)) {
1204 err = mlx4_map_clr_int(dev);
1205 if (err)
1206 goto err_out_bitmap;
225c7b1f 1207
acba2420
JM		 1208 priv->eq_table.clr_mask =
1209 swab32(1 << (priv->eq_table.inta_pin & 31));
1210 priv->eq_table.clr_int = priv->clr_base +
1211 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1212 }
225c7b1f 1213
f5f5951c 1214 priv->eq_table.irq_names =
6da2ec56
KC		 1215 kmalloc_array(MLX4_IRQNAME_SIZE,
1216 (dev->caps.num_comp_vectors + 1),
1217 GFP_KERNEL);
b8dd786f
YP		 1218 if (!priv->eq_table.irq_names) {
1219 err = -ENOMEM;
c66fa19c 1220 goto err_out_clr_int;
b8dd786f
YP		 1221 }
1222
c66fa19c
MB		 1223 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1224 if (i == MLX4_EQ_ASYNC) {
1225 err = mlx4_create_eq(dev,
1226 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1227 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
1228 } else {
c66fa19c 1229 struct mlx4_eq *eq = &priv->eq_table.eq[i];
db9777e3 1230#ifdef CONFIG_RFS_ACCEL
c66fa19c
MB		 1231 int port = find_first_bit(eq->actv_ports.ports,
1232 dev->caps.num_ports) + 1;
1233
1234 if (port <= dev->caps.num_ports) {
1235 struct mlx4_port_info *info =
1236 &mlx4_priv(dev)->port[port];
1237
1238 if (!info->rmap) {
1239 info->rmap = alloc_irq_cpu_rmap(
1240 mlx4_get_eqs_per_port(dev, port));
1241 if (!info->rmap) {
1242 mlx4_warn(dev, "Failed to allocate cpu rmap\n");
1243 err = -ENOMEM;
1244 goto err_out_unmap;
1245 }
1246 }
0b7ca5a9 1247
c66fa19c
MB		 1248 err = irq_cpu_rmap_add(
1249 info->rmap, eq->irq);
1250 if (err)
1251 mlx4_warn(dev, "Failed adding irq rmap\n");
1252 }
1253#endif
6ed63d84
JM		 1254 err = mlx4_create_eq(dev, dev->quotas.cq +
1255 MLX4_NUM_SPARE_EQE,
c66fa19c
MB		 1256 (dev->flags & MLX4_FLAG_MSI_X) ?
1257 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0,
1258 eq);
0b7ca5a9 1259 }
c66fa19c
MB		 1260 if (err)
1261 goto err_out_unmap;
0b7ca5a9
YP		 1262 }
1263
225c7b1f 1264 if (dev->flags & MLX4_FLAG_MSI_X) {
b8dd786f
YP		 1265 const char *eq_name;
1266
c66fa19c
MB		 1267 snprintf(priv->eq_table.irq_names +
1268 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE,
1269 MLX4_IRQNAME_SIZE,
1270 "mlx4-async@pci:%s",
1271 pci_name(dev->persist->pdev));
1272 eq_name = priv->eq_table.irq_names +
1273 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE;
225c7b1f 1274
c66fa19c
MB		 1275 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq,
1276 mlx4_msi_x_interrupt, 0, eq_name,
1277 priv->eq_table.eq + MLX4_EQ_ASYNC);
1278 if (err)
1279 goto err_out_unmap;
225c7b1f 1280
c66fa19c 1281 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1;
225c7b1f 1282 } else {
f5f5951c
AB		 1283 snprintf(priv->eq_table.irq_names,
1284 MLX4_IRQNAME_SIZE,
1285 DRV_NAME "@pci:%s",
872bf2fb
YH		 1286 pci_name(dev->persist->pdev));
1287 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
f5f5951c 1288 IRQF_SHARED, priv->eq_table.irq_names, dev);
225c7b1f 1289 if (err)
c66fa19c 1290 goto err_out_unmap;
225c7b1f
RD		 1291
1292 priv->eq_table.have_irq = 1;
1293 }
1294
00f5ce99 1295 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
c66fa19c 1296 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
225c7b1f
RD		 1297 if (err)
1298 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
c66fa19c 1299 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
225c7b1f 1300
c66fa19c
MB		 1301 /* arm ASYNC eq */
1302 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1);
225c7b1f 1303
225c7b1f
RD		 1304 return 0;
1305
225c7b1f 1306err_out_unmap:
2a292822
SO		 1307 while (i > 0)
1308 mlx4_free_eq(dev, &priv->eq_table.eq[--i]);
c66fa19c
MB		 1309#ifdef CONFIG_RFS_ACCEL
1310 for (i = 1; i <= dev->caps.num_ports; i++) {
1311 if (mlx4_priv(dev)->port[i].rmap) {
1312 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1313 mlx4_priv(dev)->port[i].rmap = NULL;
1314 }
b8dd786f 1315 }
c66fa19c
MB		 1316#endif
1317 mlx4_free_irqs(dev);
1318
1319err_out_clr_int:
acba2420
JM		 1320 if (!mlx4_is_slave(dev))
1321 mlx4_unmap_clr_int(dev);
225c7b1f 1322
b8dd786f 1323err_out_bitmap:
bfc0d8c3 1324 mlx4_unmap_uar(dev);
225c7b1f 1325 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f
YP		 1326
1327err_out_free:
1328 kfree(priv->eq_table.uar_map);
1329
225c7b1f
RD		 1330 return err;
1331}
1332
1333void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1334{
1335 struct mlx4_priv *priv = mlx4_priv(dev);
1336 int i;
1337
00f5ce99 1338 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
c66fa19c 1339 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
225c7b1f 1340
c66fa19c
MB		 1341#ifdef CONFIG_RFS_ACCEL
1342 for (i = 1; i <= dev->caps.num_ports; i++) {
1343 if (mlx4_priv(dev)->port[i].rmap) {
1344 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1345 mlx4_priv(dev)->port[i].rmap = NULL;
1346 }
1347 }
1348#endif
225c7b1f
RD		 1349 mlx4_free_irqs(dev);
1350
c66fa19c 1351 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f 1352 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
225c7b1f 1353
acba2420
JM		 1354 if (!mlx4_is_slave(dev))
1355 mlx4_unmap_clr_int(dev);
225c7b1f 1356
bfc0d8c3 1357 mlx4_unmap_uar(dev);
225c7b1f 1358 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f
YP		 1359
1360 kfree(priv->eq_table.uar_map);
225c7b1f 1361}
e7c1c2c4 1362
6f2e0d2c
EE		 1363/* A test that verifies that we can accept interrupts
1364 * on the vector allocated for asynchronous events
1365 */
1366int mlx4_test_async(struct mlx4_dev *dev)
1367{
1368 return mlx4_NOP(dev);
1369}
1370EXPORT_SYMBOL(mlx4_test_async);
1371
1372/* A test that verifies that we can accept interrupts
1373 * on the given irq vector of the tested port.
e7c1c2c4
YP		 1374 * Interrupts are checked using the NOP command.
1375 */
6f2e0d2c 1376int mlx4_test_interrupt(struct mlx4_dev *dev, int vector)
e7c1c2c4
YP		 1377{
1378 struct mlx4_priv *priv = mlx4_priv(dev);
e7c1c2c4
YP		 1379 int err;
1380
6f2e0d2c
EE		 1381 /* Temporary use polling for command completions */
1382 mlx4_cmd_use_polling(dev);
e7c1c2c4 1383
6f2e0d2c
EE		 1384 /* Map the new eq to handle all asynchronous events */
1385 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1386 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn);
1387 if (err) {
1388 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1389 goto out;
e7c1c2c4
YP		 1390 }
1391
6f2e0d2c
EE		 1392 /* Go back to using events */
1393 mlx4_cmd_use_events(dev);
1394 err = mlx4_NOP(dev);
1395
e7c1c2c4 1396 /* Return to default */
6f2e0d2c
EE		 1397 mlx4_cmd_use_polling(dev);
1398out:
00f5ce99 1399 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
c66fa19c 1400 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
6f2e0d2c
EE		 1401 mlx4_cmd_use_events(dev);
1402
e7c1c2c4
YP		 1403 return err;
1404}
6f2e0d2c 1405EXPORT_SYMBOL(mlx4_test_interrupt);
0b7ca5a9 1406
c66fa19c 1407bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector)
0b7ca5a9 1408{
c66fa19c 1409 struct mlx4_priv *priv = mlx4_priv(dev);
0b7ca5a9 1410
c66fa19c
MB		 1411 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1412 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) ||
1413 (vector == MLX4_EQ_ASYNC))
1414 return false;
1415
1416 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports);
1417}
1418EXPORT_SYMBOL(mlx4_is_eq_vector_valid);
1419
1420u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port)
1421{
1422 struct mlx4_priv *priv = mlx4_priv(dev);
1423 unsigned int i;
1424 unsigned int sum = 0;
1425
1426 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++)
1427 sum += !!test_bit(port - 1,
1428 priv->eq_table.eq[i].actv_ports.ports);
1429
1430 return sum;
1431}
1432EXPORT_SYMBOL(mlx4_get_eqs_per_port);
1433
1434int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector)
1435{
1436 struct mlx4_priv *priv = mlx4_priv(dev);
1437
1438 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1439 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1))
1440 return -EINVAL;
1441
1442 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports,
1443 dev->caps.num_ports) > 1);
1444}
1445EXPORT_SYMBOL(mlx4_is_eq_shared);
1446
1447struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port)
1448{
1449 return mlx4_priv(dev)->port[port].rmap;
1450}
1451EXPORT_SYMBOL(mlx4_get_cpu_rmap);
1452
1453int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector)
1454{
0b7ca5a9 1455 struct mlx4_priv *priv = mlx4_priv(dev);
c66fa19c
MB		 1456 int err = 0, i = 0;
1457 u32 min_ref_count_val = (u32)-1;
1458 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector);
1459 int *prequested_vector = NULL;
1460
0b7ca5a9 1461
730c41d5 1462 mutex_lock(&priv->msix_ctl.pool_lock);
c66fa19c
MB		 1463 if (requested_vector < (dev->caps.num_comp_vectors + 1) &&
1464 (requested_vector >= 0) &&
1465 (requested_vector != MLX4_EQ_ASYNC)) {
1466 if (test_bit(port - 1,
1467 priv->eq_table.eq[requested_vector].actv_ports.ports)) {
1468 prequested_vector = &requested_vector;
1469 } else {
1470 struct mlx4_eq *eq;
1471
1472 for (i = 1; i < port;
1473 requested_vector += mlx4_get_eqs_per_port(dev, i++))
1474 ;
1475
1476 eq = &priv->eq_table.eq[requested_vector];
1477 if (requested_vector < dev->caps.num_comp_vectors + 1 &&
1478 test_bit(port - 1, eq->actv_ports.ports)) {
1479 prequested_vector = &requested_vector;
d9236c3f 1480 }
c66fa19c
MB		 1481 }
1482 }
1483
1484 if (!prequested_vector) {
1485 requested_vector = -1;
1486 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1;
1487 i++) {
1488 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1489
1490 if (min_ref_count_val > eq->ref_count &&
1491 test_bit(port - 1, eq->actv_ports.ports)) {
1492 min_ref_count_val = eq->ref_count;
1493 requested_vector = i;
0b7ca5a9 1494 }
c66fa19c 1495 }
2eacc23c 1496
c66fa19c
MB		 1497 if (requested_vector < 0) {
1498 err = -ENOSPC;
1499 goto err_unlock;
0b7ca5a9 1500 }
c66fa19c
MB		 1501
1502 prequested_vector = &requested_vector;
0b7ca5a9 1503 }
c66fa19c
MB		 1504
1505 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) &&
1506 dev->flags & MLX4_FLAG_MSI_X) {
1507 set_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1508 snprintf(priv->eq_table.irq_names +
1509 *prequested_vector * MLX4_IRQNAME_SIZE,
1510 MLX4_IRQNAME_SIZE, "mlx4-%d@%s",
1511 *prequested_vector, dev_name(&dev->persist->pdev->dev));
1512
1513 err = request_irq(priv->eq_table.eq[*prequested_vector].irq,
1514 mlx4_msi_x_interrupt, 0,
1515 &priv->eq_table.irq_names[*prequested_vector << 5],
1516 priv->eq_table.eq + *prequested_vector);
1517
1518 if (err) {
1519 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1520 *prequested_vector = -1;
1521 } else {
de161803
IS		 1522#if defined(CONFIG_SMP)
1523 mlx4_set_eq_affinity_hint(priv, *prequested_vector);
1524#endif
c66fa19c
MB		 1525 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1);
1526 priv->eq_table.eq[*prequested_vector].have_irq = 1;
1527 }
1528 }
1529
1530 if (!err && *prequested_vector >= 0)
1531 priv->eq_table.eq[*prequested_vector].ref_count++;
1532
1533err_unlock:
730c41d5 1534 mutex_unlock(&priv->msix_ctl.pool_lock);
0b7ca5a9 1535
c66fa19c
MB		 1536 if (!err && *prequested_vector >= 0)
1537 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector);
1538 else
0b7ca5a9 1539 *vector = 0;
c66fa19c 1540
0b7ca5a9
YP		 1541 return err;
1542}
1543EXPORT_SYMBOL(mlx4_assign_eq);
1544
c66fa19c 1545int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec)
35f6f453
AV		 1546{
1547 struct mlx4_priv *priv = mlx4_priv(dev);
1548
c66fa19c 1549 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq;
35f6f453
AV		 1550}
1551EXPORT_SYMBOL(mlx4_eq_get_irq);
1552
0b7ca5a9
YP		 1553void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1554{
1555 struct mlx4_priv *priv = mlx4_priv(dev);
c66fa19c
MB		 1556 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec);
1557
1558 mutex_lock(&priv->msix_ctl.pool_lock);
1559 priv->eq_table.eq[eq_vec].ref_count--;
0b7ca5a9 1560
c66fa19c
MB		 1561 /* once we allocated EQ, we don't release it because it might be binded
1562 * to cpu_rmap.
1563 */
1564 mutex_unlock(&priv->msix_ctl.pool_lock);
0b7ca5a9
YP		 1565}
1566EXPORT_SYMBOL(mlx4_release_eq);
1567
Linux 6.x block layer and io_uring tree(s)