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225c7b1f | 1 | /* |
51a379d0 | 2 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
3 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
4 | * | |
5 | * This software is available to you under a choice of one of two | |
6 | * licenses. You may choose to be licensed under the terms of the GNU | |
7 | * General Public License (GPL) Version 2, available from the file | |
8 | * COPYING in the main directory of this source tree, or the | |
9 | * OpenIB.org BSD license below: | |
10 | * | |
11 | * Redistribution and use in source and binary forms, with or | |
12 | * without modification, are permitted provided that the following | |
13 | * conditions are met: | |
14 | * | |
15 | * - Redistributions of source code must retain the above | |
16 | * copyright notice, this list of conditions and the following | |
17 | * disclaimer. | |
18 | * | |
19 | * - Redistributions in binary form must reproduce the above | |
20 | * copyright notice, this list of conditions and the following | |
21 | * disclaimer in the documentation and/or other materials | |
22 | * provided with the distribution. | |
23 | * | |
24 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
25 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
26 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
27 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
28 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
29 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
30 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
31 | * SOFTWARE. | |
32 | */ | |
33 | ||
225c7b1f | 34 | #include <linux/interrupt.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
ee40fa06 | 36 | #include <linux/export.h> |
27ac792c | 37 | #include <linux/mm.h> |
9cbe05c7 | 38 | #include <linux/dma-mapping.h> |
225c7b1f RD |
39 | |
40 | #include <linux/mlx4/cmd.h> | |
d9236c3f | 41 | #include <linux/cpu_rmap.h> |
225c7b1f RD |
42 | |
43 | #include "mlx4.h" | |
44 | #include "fw.h" | |
45 | ||
f5f5951c | 46 | enum { |
0b7ca5a9 | 47 | MLX4_IRQNAME_SIZE = 32 |
f5f5951c AB |
48 | }; |
49 | ||
225c7b1f RD |
50 | enum { |
51 | MLX4_NUM_ASYNC_EQE = 0x100, | |
52 | MLX4_NUM_SPARE_EQE = 0x80, | |
53 | MLX4_EQ_ENTRY_SIZE = 0x20 | |
54 | }; | |
55 | ||
225c7b1f RD |
56 | #define MLX4_EQ_STATUS_OK ( 0 << 28) |
57 | #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) | |
58 | #define MLX4_EQ_OWNER_SW ( 0 << 24) | |
59 | #define MLX4_EQ_OWNER_HW ( 1 << 24) | |
60 | #define MLX4_EQ_FLAG_EC ( 1 << 18) | |
61 | #define MLX4_EQ_FLAG_OI ( 1 << 17) | |
62 | #define MLX4_EQ_STATE_ARMED ( 9 << 8) | |
63 | #define MLX4_EQ_STATE_FIRED (10 << 8) | |
64 | #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) | |
65 | ||
66 | #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ | |
67 | (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ | |
68 | (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ | |
69 | (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ | |
70 | (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ | |
71 | (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ | |
72 | (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ | |
73 | (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ | |
74 | (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ | |
225c7b1f RD |
75 | (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ |
76 | (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ | |
77 | (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ | |
78 | (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ | |
79 | (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ | |
acba2420 | 80 | (1ull << MLX4_EVENT_TYPE_CMD) | \ |
fe6f700d | 81 | (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ |
acba2420 | 82 | (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ |
5984be90 JM |
83 | (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ |
84 | (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) | |
225c7b1f | 85 | |
00f5ce99 JM |
86 | static u64 get_async_ev_mask(struct mlx4_dev *dev) |
87 | { | |
88 | u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; | |
89 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) | |
90 | async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); | |
be6a6b43 JM |
91 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) |
92 | async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT); | |
00f5ce99 JM |
93 | |
94 | return async_ev_mask; | |
95 | } | |
96 | ||
225c7b1f RD |
97 | static void eq_set_ci(struct mlx4_eq *eq, int req_not) |
98 | { | |
99 | __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | | |
100 | req_not << 31), | |
101 | eq->doorbell); | |
102 | /* We still want ordering, just not swabbing, so add a barrier */ | |
103 | mb(); | |
104 | } | |
105 | ||
43c816c6 IS |
106 | static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, |
107 | u8 eqe_size) | |
225c7b1f | 108 | { |
08ff3235 | 109 | /* (entry & (eq->nent - 1)) gives us a cyclic array */ |
43c816c6 IS |
110 | unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; |
111 | /* CX3 is capable of extending the EQE from 32 to 64 bytes with | |
112 | * strides of 64B,128B and 256B. | |
113 | * When 64B EQE is used, the first (in the lower addresses) | |
08ff3235 OG |
114 | * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes |
115 | * contain the legacy EQE information. | |
43c816c6 | 116 | * In all other cases, the first 32B contains the legacy EQE info. |
08ff3235 OG |
117 | */ |
118 | return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; | |
225c7b1f RD |
119 | } |
120 | ||
43c816c6 | 121 | static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) |
225c7b1f | 122 | { |
43c816c6 | 123 | struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); |
225c7b1f RD |
124 | return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; |
125 | } | |
126 | ||
acba2420 JM |
127 | static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) |
128 | { | |
129 | struct mlx4_eqe *eqe = | |
130 | &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; | |
131 | return (!!(eqe->owner & 0x80) ^ | |
132 | !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? | |
133 | eqe : NULL; | |
134 | } | |
135 | ||
acba2420 JM |
136 | void mlx4_gen_slave_eqe(struct work_struct *work) |
137 | { | |
138 | struct mlx4_mfunc_master_ctx *master = | |
139 | container_of(work, struct mlx4_mfunc_master_ctx, | |
140 | slave_event_work); | |
141 | struct mlx4_mfunc *mfunc = | |
142 | container_of(master, struct mlx4_mfunc, master); | |
143 | struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); | |
144 | struct mlx4_dev *dev = &priv->dev; | |
145 | struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; | |
146 | struct mlx4_eqe *eqe; | |
147 | u8 slave; | |
74d4943f | 148 | int i, phys_port, slave_port; |
acba2420 JM |
149 | |
150 | for (eqe = next_slave_event_eqe(slave_eq); eqe; | |
151 | eqe = next_slave_event_eqe(slave_eq)) { | |
152 | slave = eqe->slave_id; | |
153 | ||
154 | /* All active slaves need to receive the event */ | |
155 | if (slave == ALL_SLAVES) { | |
bffb023a | 156 | for (i = 0; i <= dev->persist->num_vfs; i++) { |
74d4943f OG |
157 | phys_port = 0; |
158 | if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT && | |
159 | eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) { | |
160 | phys_port = eqe->event.port_mgmt_change.port; | |
161 | slave_port = mlx4_phys_to_slave_port(dev, i, phys_port); | |
162 | if (slave_port < 0) /* VF doesn't have this port */ | |
163 | continue; | |
164 | eqe->event.port_mgmt_change.port = slave_port; | |
165 | } | |
bffb023a JM |
166 | if (mlx4_GEN_EQE(dev, i, eqe)) |
167 | mlx4_warn(dev, "Failed to generate event for slave %d\n", | |
168 | i); | |
74d4943f OG |
169 | if (phys_port) |
170 | eqe->event.port_mgmt_change.port = phys_port; | |
acba2420 JM |
171 | } |
172 | } else { | |
173 | if (mlx4_GEN_EQE(dev, slave, eqe)) | |
1a91de28 JP |
174 | mlx4_warn(dev, "Failed to generate event for slave %d\n", |
175 | slave); | |
acba2420 JM |
176 | } |
177 | ++slave_eq->cons; | |
178 | } | |
179 | } | |
180 | ||
181 | ||
182 | static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) | |
183 | { | |
184 | struct mlx4_priv *priv = mlx4_priv(dev); | |
185 | struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; | |
992e8e6e JM |
186 | struct mlx4_eqe *s_eqe; |
187 | unsigned long flags; | |
acba2420 | 188 | |
992e8e6e JM |
189 | spin_lock_irqsave(&slave_eq->event_lock, flags); |
190 | s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; | |
acba2420 JM |
191 | if ((!!(s_eqe->owner & 0x80)) ^ |
192 | (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { | |
1a91de28 JP |
193 | mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", |
194 | slave); | |
992e8e6e | 195 | spin_unlock_irqrestore(&slave_eq->event_lock, flags); |
acba2420 JM |
196 | return; |
197 | } | |
198 | ||
08ff3235 | 199 | memcpy(s_eqe, eqe, dev->caps.eqe_size - 1); |
acba2420 JM |
200 | s_eqe->slave_id = slave; |
201 | /* ensure all information is written before setting the ownersip bit */ | |
12b3375f | 202 | dma_wmb(); |
acba2420 JM |
203 | s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; |
204 | ++slave_eq->prod; | |
205 | ||
206 | queue_work(priv->mfunc.master.comm_wq, | |
207 | &priv->mfunc.master.slave_event_work); | |
992e8e6e | 208 | spin_unlock_irqrestore(&slave_eq->event_lock, flags); |
acba2420 JM |
209 | } |
210 | ||
211 | static void mlx4_slave_event(struct mlx4_dev *dev, int slave, | |
212 | struct mlx4_eqe *eqe) | |
213 | { | |
214 | struct mlx4_priv *priv = mlx4_priv(dev); | |
acba2420 | 215 | |
bffb023a JM |
216 | if (slave < 0 || slave > dev->persist->num_vfs || |
217 | slave == dev->caps.function || | |
218 | !priv->mfunc.master.slave_state[slave].active) | |
acba2420 | 219 | return; |
acba2420 JM |
220 | |
221 | slave_event(dev, slave, eqe); | |
222 | } | |
223 | ||
db9777e3 | 224 | #if defined(CONFIG_SMP) |
de161803 IS |
225 | static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec) |
226 | { | |
227 | int hint_err; | |
228 | struct mlx4_dev *dev = &priv->dev; | |
229 | struct mlx4_eq *eq = &priv->eq_table.eq[vec]; | |
230 | ||
231 | if (!eq->affinity_mask || cpumask_empty(eq->affinity_mask)) | |
232 | return; | |
233 | ||
234 | hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask); | |
235 | if (hint_err) | |
236 | mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err); | |
237 | } | |
db9777e3 | 238 | #endif |
de161803 | 239 | |
993c401e JM |
240 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) |
241 | { | |
242 | struct mlx4_eqe eqe; | |
243 | ||
244 | struct mlx4_priv *priv = mlx4_priv(dev); | |
245 | struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; | |
246 | ||
247 | if (!s_slave->active) | |
248 | return 0; | |
249 | ||
250 | memset(&eqe, 0, sizeof eqe); | |
251 | ||
252 | eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; | |
253 | eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; | |
74d4943f | 254 | eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); |
993c401e JM |
255 | |
256 | return mlx4_GEN_EQE(dev, slave, &eqe); | |
257 | } | |
258 | EXPORT_SYMBOL(mlx4_gen_pkey_eqe); | |
259 | ||
260 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) | |
261 | { | |
262 | struct mlx4_eqe eqe; | |
263 | ||
264 | /*don't send if we don't have the that slave */ | |
872bf2fb | 265 | if (dev->persist->num_vfs < slave) |
993c401e JM |
266 | return 0; |
267 | memset(&eqe, 0, sizeof eqe); | |
268 | ||
269 | eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; | |
270 | eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; | |
74d4943f | 271 | eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); |
993c401e JM |
272 | |
273 | return mlx4_GEN_EQE(dev, slave, &eqe); | |
274 | } | |
275 | EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); | |
276 | ||
277 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, | |
278 | u8 port_subtype_change) | |
279 | { | |
280 | struct mlx4_eqe eqe; | |
74d4943f | 281 | u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port); |
993c401e JM |
282 | |
283 | /*don't send if we don't have the that slave */ | |
872bf2fb | 284 | if (dev->persist->num_vfs < slave) |
993c401e JM |
285 | return 0; |
286 | memset(&eqe, 0, sizeof eqe); | |
287 | ||
288 | eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; | |
289 | eqe.subtype = port_subtype_change; | |
74d4943f | 290 | eqe.event.port_change.port = cpu_to_be32(slave_port << 28); |
993c401e JM |
291 | |
292 | mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, | |
293 | port_subtype_change, slave, port); | |
294 | return mlx4_GEN_EQE(dev, slave, &eqe); | |
295 | } | |
296 | EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); | |
297 | ||
298 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) | |
299 | { | |
300 | struct mlx4_priv *priv = mlx4_priv(dev); | |
301 | struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; | |
449fc488 MB |
302 | struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); |
303 | ||
304 | if (slave >= dev->num_slaves || port > dev->caps.num_ports || | |
305 | port <= 0 || !test_bit(port - 1, actv_ports.ports)) { | |
993c401e JM |
306 | pr_err("%s: Error: asking for slave:%d, port:%d\n", |
307 | __func__, slave, port); | |
308 | return SLAVE_PORT_DOWN; | |
309 | } | |
310 | return s_state[slave].port_state[port]; | |
311 | } | |
312 | EXPORT_SYMBOL(mlx4_get_slave_port_state); | |
313 | ||
314 | static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, | |
315 | enum slave_port_state state) | |
316 | { | |
317 | struct mlx4_priv *priv = mlx4_priv(dev); | |
318 | struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; | |
449fc488 | 319 | struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); |
993c401e | 320 | |
449fc488 MB |
321 | if (slave >= dev->num_slaves || port > dev->caps.num_ports || |
322 | port <= 0 || !test_bit(port - 1, actv_ports.ports)) { | |
993c401e JM |
323 | pr_err("%s: Error: asking for slave:%d, port:%d\n", |
324 | __func__, slave, port); | |
325 | return -1; | |
326 | } | |
327 | s_state[slave].port_state[port] = state; | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) | |
333 | { | |
334 | int i; | |
335 | enum slave_port_gen_event gen_event; | |
449fc488 MB |
336 | struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, |
337 | port); | |
993c401e | 338 | |
872bf2fb | 339 | for (i = 0; i < dev->persist->num_vfs + 1; i++) |
449fc488 MB |
340 | if (test_bit(i, slaves_pport.slaves)) |
341 | set_and_calc_slave_port_state(dev, i, port, | |
342 | event, &gen_event); | |
993c401e JM |
343 | } |
344 | /************************************************************************** | |
345 | The function get as input the new event to that port, | |
346 | and according to the prev state change the slave's port state. | |
347 | The events are: | |
348 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
349 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP | |
350 | MLX4_PORT_STATE_IB_EVENT_GID_VALID | |
351 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID | |
352 | ***************************************************************************/ | |
353 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, | |
354 | u8 port, int event, | |
355 | enum slave_port_gen_event *gen_event) | |
356 | { | |
357 | struct mlx4_priv *priv = mlx4_priv(dev); | |
358 | struct mlx4_slave_state *ctx = NULL; | |
359 | unsigned long flags; | |
360 | int ret = -1; | |
449fc488 | 361 | struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); |
993c401e JM |
362 | enum slave_port_state cur_state = |
363 | mlx4_get_slave_port_state(dev, slave, port); | |
364 | ||
365 | *gen_event = SLAVE_PORT_GEN_EVENT_NONE; | |
366 | ||
449fc488 MB |
367 | if (slave >= dev->num_slaves || port > dev->caps.num_ports || |
368 | port <= 0 || !test_bit(port - 1, actv_ports.ports)) { | |
993c401e JM |
369 | pr_err("%s: Error: asking for slave:%d, port:%d\n", |
370 | __func__, slave, port); | |
371 | return ret; | |
372 | } | |
373 | ||
374 | ctx = &priv->mfunc.master.slave_state[slave]; | |
375 | spin_lock_irqsave(&ctx->lock, flags); | |
376 | ||
993c401e JM |
377 | switch (cur_state) { |
378 | case SLAVE_PORT_DOWN: | |
379 | if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) | |
380 | mlx4_set_slave_port_state(dev, slave, port, | |
381 | SLAVE_PENDING_UP); | |
382 | break; | |
383 | case SLAVE_PENDING_UP: | |
384 | if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) | |
385 | mlx4_set_slave_port_state(dev, slave, port, | |
386 | SLAVE_PORT_DOWN); | |
387 | else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { | |
388 | mlx4_set_slave_port_state(dev, slave, port, | |
389 | SLAVE_PORT_UP); | |
390 | *gen_event = SLAVE_PORT_GEN_EVENT_UP; | |
391 | } | |
392 | break; | |
393 | case SLAVE_PORT_UP: | |
394 | if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { | |
395 | mlx4_set_slave_port_state(dev, slave, port, | |
396 | SLAVE_PORT_DOWN); | |
397 | *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; | |
398 | } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == | |
399 | event) { | |
400 | mlx4_set_slave_port_state(dev, slave, port, | |
401 | SLAVE_PENDING_UP); | |
402 | *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; | |
403 | } | |
404 | break; | |
405 | default: | |
1a91de28 JP |
406 | pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", |
407 | __func__, slave, port); | |
408 | goto out; | |
993c401e JM |
409 | } |
410 | ret = mlx4_get_slave_port_state(dev, slave, port); | |
993c401e JM |
411 | |
412 | out: | |
413 | spin_unlock_irqrestore(&ctx->lock, flags); | |
414 | return ret; | |
415 | } | |
416 | ||
417 | EXPORT_SYMBOL(set_and_calc_slave_port_state); | |
418 | ||
419 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) | |
420 | { | |
421 | struct mlx4_eqe eqe; | |
422 | ||
423 | memset(&eqe, 0, sizeof eqe); | |
424 | ||
425 | eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; | |
426 | eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; | |
427 | eqe.event.port_mgmt_change.port = port; | |
428 | eqe.event.port_mgmt_change.params.port_info.changed_attr = | |
429 | cpu_to_be32((u32) attr); | |
430 | ||
431 | slave_event(dev, ALL_SLAVES, &eqe); | |
432 | return 0; | |
433 | } | |
434 | EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); | |
435 | ||
acba2420 JM |
436 | void mlx4_master_handle_slave_flr(struct work_struct *work) |
437 | { | |
438 | struct mlx4_mfunc_master_ctx *master = | |
439 | container_of(work, struct mlx4_mfunc_master_ctx, | |
440 | slave_flr_event_work); | |
441 | struct mlx4_mfunc *mfunc = | |
442 | container_of(master, struct mlx4_mfunc, master); | |
443 | struct mlx4_priv *priv = | |
444 | container_of(mfunc, struct mlx4_priv, mfunc); | |
445 | struct mlx4_dev *dev = &priv->dev; | |
446 | struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; | |
447 | int i; | |
448 | int err; | |
311f813a | 449 | unsigned long flags; |
acba2420 JM |
450 | |
451 | mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); | |
452 | ||
453 | for (i = 0 ; i < dev->num_slaves; i++) { | |
454 | ||
455 | if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { | |
1a91de28 JP |
456 | mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", |
457 | i); | |
55ad3592 YH |
458 | /* In case of 'Reset flow' FLR can be generated for |
459 | * a slave before mlx4_load_one is done. | |
460 | * make sure interface is up before trying to delete | |
461 | * slave resources which weren't allocated yet. | |
462 | */ | |
463 | if (dev->persist->interface_state & | |
464 | MLX4_INTERFACE_STATE_UP) | |
465 | mlx4_delete_all_resources_for_slave(dev, i); | |
acba2420 | 466 | /*return the slave to running mode*/ |
311f813a | 467 | spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); |
acba2420 JM |
468 | slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; |
469 | slave_state[i].is_slave_going_down = 0; | |
311f813a | 470 | spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); |
acba2420 JM |
471 | /*notify the FW:*/ |
472 | err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, | |
473 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
474 | if (err) | |
1a91de28 JP |
475 | mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", |
476 | i); | |
acba2420 JM |
477 | } |
478 | } | |
479 | } | |
480 | ||
225c7b1f RD |
481 | static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) |
482 | { | |
acba2420 | 483 | struct mlx4_priv *priv = mlx4_priv(dev); |
225c7b1f | 484 | struct mlx4_eqe *eqe; |
3dca0f42 | 485 | int cqn = -1; |
225c7b1f RD |
486 | int eqes_found = 0; |
487 | int set_ci = 0; | |
27bf91d6 | 488 | int port; |
acba2420 JM |
489 | int slave = 0; |
490 | int ret; | |
491 | u32 flr_slave; | |
492 | u8 update_slave_state; | |
493 | int i; | |
993c401e | 494 | enum slave_port_gen_event gen_event; |
311f813a | 495 | unsigned long flags; |
948e306d | 496 | struct mlx4_vport_state *s_info; |
43c816c6 | 497 | int eqe_size = dev->caps.eqe_size; |
225c7b1f | 498 | |
43c816c6 | 499 | while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { |
225c7b1f RD |
500 | /* |
501 | * Make sure we read EQ entry contents after we've | |
502 | * checked the ownership bit. | |
503 | */ | |
12b3375f | 504 | dma_rmb(); |
225c7b1f RD |
505 | |
506 | switch (eqe->type) { | |
507 | case MLX4_EVENT_TYPE_COMP: | |
508 | cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; | |
509 | mlx4_cq_completion(dev, cqn); | |
510 | break; | |
511 | ||
512 | case MLX4_EVENT_TYPE_PATH_MIG: | |
513 | case MLX4_EVENT_TYPE_COMM_EST: | |
514 | case MLX4_EVENT_TYPE_SQ_DRAINED: | |
515 | case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: | |
516 | case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: | |
517 | case MLX4_EVENT_TYPE_PATH_MIG_FAILED: | |
518 | case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: | |
519 | case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: | |
acba2420 JM |
520 | mlx4_dbg(dev, "event %d arrived\n", eqe->type); |
521 | if (mlx4_is_master(dev)) { | |
522 | /* forward only to slave owning the QP */ | |
523 | ret = mlx4_get_slave_from_resource_id(dev, | |
524 | RES_QP, | |
525 | be32_to_cpu(eqe->event.qp.qpn) | |
526 | & 0xffffff, &slave); | |
527 | if (ret && ret != -ENOENT) { | |
1a91de28 | 528 | mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", |
acba2420 JM |
529 | eqe->type, eqe->subtype, |
530 | eq->eqn, eq->cons_index, ret); | |
531 | break; | |
532 | } | |
533 | ||
534 | if (!ret && slave != dev->caps.function) { | |
535 | mlx4_slave_event(dev, slave, eqe); | |
536 | break; | |
537 | } | |
538 | ||
539 | } | |
540 | mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & | |
541 | 0xffffff, eqe->type); | |
225c7b1f RD |
542 | break; |
543 | ||
544 | case MLX4_EVENT_TYPE_SRQ_LIMIT: | |
e0debf9c JM |
545 | mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", |
546 | __func__); | |
225c7b1f | 547 | case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: |
acba2420 JM |
548 | if (mlx4_is_master(dev)) { |
549 | /* forward only to slave owning the SRQ */ | |
550 | ret = mlx4_get_slave_from_resource_id(dev, | |
551 | RES_SRQ, | |
552 | be32_to_cpu(eqe->event.srq.srqn) | |
553 | & 0xffffff, | |
554 | &slave); | |
555 | if (ret && ret != -ENOENT) { | |
1a91de28 | 556 | mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", |
acba2420 JM |
557 | eqe->type, eqe->subtype, |
558 | eq->eqn, eq->cons_index, ret); | |
559 | break; | |
560 | } | |
1a91de28 JP |
561 | mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", |
562 | __func__, slave, | |
acba2420 JM |
563 | be32_to_cpu(eqe->event.srq.srqn), |
564 | eqe->type, eqe->subtype); | |
565 | ||
566 | if (!ret && slave != dev->caps.function) { | |
1a91de28 JP |
567 | mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", |
568 | __func__, eqe->type, | |
acba2420 JM |
569 | eqe->subtype, slave); |
570 | mlx4_slave_event(dev, slave, eqe); | |
571 | break; | |
572 | } | |
573 | } | |
574 | mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & | |
575 | 0xffffff, eqe->type); | |
225c7b1f RD |
576 | break; |
577 | ||
578 | case MLX4_EVENT_TYPE_CMD: | |
579 | mlx4_cmd_event(dev, | |
580 | be16_to_cpu(eqe->event.cmd.token), | |
581 | eqe->event.cmd.status, | |
582 | be64_to_cpu(eqe->event.cmd.out_param)); | |
583 | break; | |
584 | ||
449fc488 MB |
585 | case MLX4_EVENT_TYPE_PORT_CHANGE: { |
586 | struct mlx4_slaves_pport slaves_port; | |
27bf91d6 | 587 | port = be32_to_cpu(eqe->event.port_change.port) >> 28; |
449fc488 | 588 | slaves_port = mlx4_phys_to_slaves_pport(dev, port); |
27bf91d6 | 589 | if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { |
993c401e | 590 | mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, |
27bf91d6 YP |
591 | port); |
592 | mlx4_priv(dev)->sense.do_sense_port[port] = 1; | |
993c401e JM |
593 | if (!mlx4_is_master(dev)) |
594 | break; | |
872bf2fb YH |
595 | for (i = 0; i < dev->persist->num_vfs + 1; |
596 | i++) { | |
449fc488 MB |
597 | if (!test_bit(i, slaves_port.slaves)) |
598 | continue; | |
993c401e JM |
599 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { |
600 | if (i == mlx4_master_func_num(dev)) | |
601 | continue; | |
1a91de28 | 602 | mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", |
acba2420 | 603 | __func__, i, port); |
948e306d | 604 | s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; |
449fc488 MB |
605 | if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { |
606 | eqe->event.port_change.port = | |
607 | cpu_to_be32( | |
608 | (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) | |
609 | | (mlx4_phys_to_slave_port(dev, i, port) << 28)); | |
948e306d | 610 | mlx4_slave_event(dev, i, eqe); |
449fc488 | 611 | } |
993c401e JM |
612 | } else { /* IB port */ |
613 | set_and_calc_slave_port_state(dev, i, port, | |
614 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
615 | &gen_event); | |
616 | /*we can be in pending state, then do not send port_down event*/ | |
617 | if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { | |
618 | if (i == mlx4_master_func_num(dev)) | |
619 | continue; | |
74d4943f OG |
620 | eqe->event.port_change.port = |
621 | cpu_to_be32( | |
622 | (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) | |
623 | | (mlx4_phys_to_slave_port(dev, i, port) << 28)); | |
993c401e JM |
624 | mlx4_slave_event(dev, i, eqe); |
625 | } | |
acba2420 | 626 | } |
993c401e | 627 | } |
27bf91d6 | 628 | } else { |
993c401e JM |
629 | mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); |
630 | ||
27bf91d6 | 631 | mlx4_priv(dev)->sense.do_sense_port[port] = 0; |
acba2420 | 632 | |
993c401e JM |
633 | if (!mlx4_is_master(dev)) |
634 | break; | |
635 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) | |
872bf2fb YH |
636 | for (i = 0; |
637 | i < dev->persist->num_vfs + 1; | |
638 | i++) { | |
449fc488 MB |
639 | if (!test_bit(i, slaves_port.slaves)) |
640 | continue; | |
993c401e | 641 | if (i == mlx4_master_func_num(dev)) |
acba2420 | 642 | continue; |
948e306d | 643 | s_info = &priv->mfunc.master.vf_oper[slave].vport[port].state; |
449fc488 MB |
644 | if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) { |
645 | eqe->event.port_change.port = | |
646 | cpu_to_be32( | |
647 | (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) | |
648 | | (mlx4_phys_to_slave_port(dev, i, port) << 28)); | |
948e306d | 649 | mlx4_slave_event(dev, i, eqe); |
449fc488 | 650 | } |
acba2420 | 651 | } |
993c401e JM |
652 | else /* IB port */ |
653 | /* port-up event will be sent to a slave when the | |
654 | * slave's alias-guid is set. This is done in alias_GUID.c | |
655 | */ | |
656 | set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); | |
27bf91d6 | 657 | } |
225c7b1f | 658 | break; |
449fc488 | 659 | } |
225c7b1f RD |
660 | |
661 | case MLX4_EVENT_TYPE_CQ_ERROR: | |
662 | mlx4_warn(dev, "CQ %s on CQN %06x\n", | |
663 | eqe->event.cq_err.syndrome == 1 ? | |
664 | "overrun" : "access violation", | |
665 | be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); | |
acba2420 JM |
666 | if (mlx4_is_master(dev)) { |
667 | ret = mlx4_get_slave_from_resource_id(dev, | |
668 | RES_CQ, | |
669 | be32_to_cpu(eqe->event.cq_err.cqn) | |
670 | & 0xffffff, &slave); | |
671 | if (ret && ret != -ENOENT) { | |
1a91de28 JP |
672 | mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", |
673 | eqe->type, eqe->subtype, | |
674 | eq->eqn, eq->cons_index, ret); | |
acba2420 JM |
675 | break; |
676 | } | |
677 | ||
678 | if (!ret && slave != dev->caps.function) { | |
679 | mlx4_slave_event(dev, slave, eqe); | |
680 | break; | |
681 | } | |
682 | } | |
683 | mlx4_cq_event(dev, | |
684 | be32_to_cpu(eqe->event.cq_err.cqn) | |
685 | & 0xffffff, | |
225c7b1f RD |
686 | eqe->type); |
687 | break; | |
688 | ||
689 | case MLX4_EVENT_TYPE_EQ_OVERFLOW: | |
690 | mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); | |
691 | break; | |
692 | ||
fe6f700d YP |
693 | case MLX4_EVENT_TYPE_OP_REQUIRED: |
694 | atomic_inc(&priv->opreq_count); | |
695 | /* FW commands can't be executed from interrupt context | |
696 | * working in deferred task | |
697 | */ | |
698 | queue_work(mlx4_wq, &priv->opreq_task); | |
699 | break; | |
700 | ||
acba2420 JM |
701 | case MLX4_EVENT_TYPE_COMM_CHANNEL: |
702 | if (!mlx4_is_master(dev)) { | |
1a91de28 | 703 | mlx4_warn(dev, "Received comm channel event for non master device\n"); |
acba2420 JM |
704 | break; |
705 | } | |
706 | memcpy(&priv->mfunc.master.comm_arm_bit_vector, | |
707 | eqe->event.comm_channel_arm.bit_vec, | |
708 | sizeof eqe->event.comm_channel_arm.bit_vec); | |
709 | queue_work(priv->mfunc.master.comm_wq, | |
710 | &priv->mfunc.master.comm_work); | |
711 | break; | |
712 | ||
713 | case MLX4_EVENT_TYPE_FLR_EVENT: | |
714 | flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); | |
715 | if (!mlx4_is_master(dev)) { | |
1a91de28 | 716 | mlx4_warn(dev, "Non-master function received FLR event\n"); |
acba2420 JM |
717 | break; |
718 | } | |
719 | ||
720 | mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); | |
721 | ||
30f7c73b | 722 | if (flr_slave >= dev->num_slaves) { |
acba2420 JM |
723 | mlx4_warn(dev, |
724 | "Got FLR for unknown function: %d\n", | |
725 | flr_slave); | |
726 | update_slave_state = 0; | |
727 | } else | |
728 | update_slave_state = 1; | |
729 | ||
311f813a | 730 | spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); |
acba2420 JM |
731 | if (update_slave_state) { |
732 | priv->mfunc.master.slave_state[flr_slave].active = false; | |
733 | priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; | |
734 | priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; | |
735 | } | |
311f813a | 736 | spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); |
a0667a83 YH |
737 | mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, |
738 | flr_slave); | |
acba2420 JM |
739 | queue_work(priv->mfunc.master.comm_wq, |
740 | &priv->mfunc.master.slave_flr_event_work); | |
741 | break; | |
5984be90 JM |
742 | |
743 | case MLX4_EVENT_TYPE_FATAL_WARNING: | |
744 | if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { | |
745 | if (mlx4_is_master(dev)) | |
746 | for (i = 0; i < dev->num_slaves; i++) { | |
1a91de28 JP |
747 | mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", |
748 | __func__, i); | |
5984be90 JM |
749 | if (i == dev->caps.function) |
750 | continue; | |
751 | mlx4_slave_event(dev, i, eqe); | |
752 | } | |
1a91de28 JP |
753 | mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", |
754 | be16_to_cpu(eqe->event.warming.warning_threshold), | |
755 | be16_to_cpu(eqe->event.warming.current_temperature)); | |
5984be90 | 756 | } else |
1a91de28 | 757 | mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", |
5984be90 JM |
758 | eqe->type, eqe->subtype, eq->eqn, |
759 | eq->cons_index, eqe->owner, eq->nent, | |
760 | eqe->slave_id, | |
761 | !!(eqe->owner & 0x80) ^ | |
762 | !!(eq->cons_index & eq->nent) ? "HW" : "SW"); | |
763 | ||
764 | break; | |
765 | ||
00f5ce99 JM |
766 | case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: |
767 | mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, | |
768 | (unsigned long) eqe); | |
769 | break; | |
770 | ||
be6a6b43 JM |
771 | case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT: |
772 | switch (eqe->subtype) { | |
773 | case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE: | |
774 | mlx4_warn(dev, "Bad cable detected on port %u\n", | |
775 | eqe->event.bad_cable.port); | |
776 | break; | |
777 | case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE: | |
778 | mlx4_warn(dev, "Unsupported cable detected\n"); | |
779 | break; | |
780 | default: | |
781 | mlx4_dbg(dev, | |
782 | "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n", | |
783 | eqe->type, eqe->subtype, eq->eqn, | |
784 | eq->cons_index, eqe->owner, eq->nent, | |
785 | !!(eqe->owner & 0x80) ^ | |
786 | !!(eq->cons_index & eq->nent) ? "HW" : "SW"); | |
787 | break; | |
788 | } | |
789 | break; | |
790 | ||
225c7b1f RD |
791 | case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: |
792 | case MLX4_EVENT_TYPE_ECC_DETECT: | |
793 | default: | |
1a91de28 | 794 | mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", |
acba2420 JM |
795 | eqe->type, eqe->subtype, eq->eqn, |
796 | eq->cons_index, eqe->owner, eq->nent, | |
797 | eqe->slave_id, | |
798 | !!(eqe->owner & 0x80) ^ | |
799 | !!(eq->cons_index & eq->nent) ? "HW" : "SW"); | |
225c7b1f | 800 | break; |
acba2420 | 801 | }; |
225c7b1f RD |
802 | |
803 | ++eq->cons_index; | |
804 | eqes_found = 1; | |
805 | ++set_ci; | |
806 | ||
807 | /* | |
808 | * The HCA will think the queue has overflowed if we | |
809 | * don't tell it we've been processing events. We | |
810 | * create our EQs with MLX4_NUM_SPARE_EQE extra | |
811 | * entries, so we must update our consumer index at | |
812 | * least that often. | |
813 | */ | |
814 | if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { | |
225c7b1f RD |
815 | eq_set_ci(eq, 0); |
816 | set_ci = 0; | |
817 | } | |
818 | } | |
819 | ||
820 | eq_set_ci(eq, 1); | |
821 | ||
3dca0f42 MB |
822 | /* cqn is 24bit wide but is initialized such that its higher bits |
823 | * are ones too. Thus, if we got any event, cqn's high bits should be off | |
824 | * and we need to schedule the tasklet. | |
825 | */ | |
826 | if (!(cqn & ~0xffffff)) | |
827 | tasklet_schedule(&eq->tasklet_ctx.task); | |
828 | ||
225c7b1f RD |
829 | return eqes_found; |
830 | } | |
831 | ||
832 | static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) | |
833 | { | |
834 | struct mlx4_dev *dev = dev_ptr; | |
835 | struct mlx4_priv *priv = mlx4_priv(dev); | |
836 | int work = 0; | |
837 | int i; | |
838 | ||
839 | writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); | |
840 | ||
b8dd786f | 841 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) |
225c7b1f RD |
842 | work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); |
843 | ||
844 | return IRQ_RETVAL(work); | |
845 | } | |
846 | ||
847 | static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) | |
848 | { | |
849 | struct mlx4_eq *eq = eq_ptr; | |
850 | struct mlx4_dev *dev = eq->dev; | |
851 | ||
852 | mlx4_eq_int(dev, eq); | |
853 | ||
854 | /* MSI-X vectors always belong to us */ | |
855 | return IRQ_HANDLED; | |
856 | } | |
857 | ||
acba2420 JM |
858 | int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, |
859 | struct mlx4_vhcr *vhcr, | |
860 | struct mlx4_cmd_mailbox *inbox, | |
861 | struct mlx4_cmd_mailbox *outbox, | |
862 | struct mlx4_cmd_info *cmd) | |
863 | { | |
864 | struct mlx4_priv *priv = mlx4_priv(dev); | |
865 | struct mlx4_slave_event_eq_info *event_eq = | |
803143fb | 866 | priv->mfunc.master.slave_state[slave].event_eq; |
acba2420 | 867 | u32 in_modifier = vhcr->in_modifier; |
c101c81b | 868 | u32 eqn = in_modifier & 0x3FF; |
acba2420 JM |
869 | u64 in_param = vhcr->in_param; |
870 | int err = 0; | |
803143fb | 871 | int i; |
acba2420 JM |
872 | |
873 | if (slave == dev->caps.function) | |
874 | err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, | |
875 | 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, | |
876 | MLX4_CMD_NATIVE); | |
803143fb MA |
877 | if (!err) |
878 | for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) | |
879 | if (in_param & (1LL << i)) | |
880 | event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; | |
881 | ||
acba2420 JM |
882 | return err; |
883 | } | |
884 | ||
225c7b1f RD |
885 | static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, |
886 | int eq_num) | |
887 | { | |
888 | return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, | |
f9baff50 JM |
889 | 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, |
890 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
891 | } |
892 | ||
893 | static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, | |
894 | int eq_num) | |
895 | { | |
eb41049f | 896 | return mlx4_cmd(dev, mailbox->dma, eq_num, 0, |
acba2420 | 897 | MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, |
f9baff50 | 898 | MLX4_CMD_WRAPPED); |
225c7b1f RD |
899 | } |
900 | ||
30a5da5b | 901 | static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num) |
225c7b1f | 902 | { |
30a5da5b JM |
903 | return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ, |
904 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
225c7b1f RD |
905 | } |
906 | ||
b8dd786f YP |
907 | static int mlx4_num_eq_uar(struct mlx4_dev *dev) |
908 | { | |
909 | /* | |
910 | * Each UAR holds 4 EQ doorbells. To figure out how many UARs | |
911 | * we need to map, take the difference of highest index and | |
912 | * the lowest index we'll use and add 1. | |
913 | */ | |
c66fa19c MB |
914 | return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 - |
915 | dev->caps.reserved_eqs / 4 + 1; | |
b8dd786f YP |
916 | } |
917 | ||
3d73c288 | 918 | static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) |
225c7b1f RD |
919 | { |
920 | struct mlx4_priv *priv = mlx4_priv(dev); | |
921 | int index; | |
922 | ||
923 | index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; | |
924 | ||
925 | if (!priv->eq_table.uar_map[index]) { | |
926 | priv->eq_table.uar_map[index] = | |
872bf2fb | 927 | ioremap(pci_resource_start(dev->persist->pdev, 2) + |
225c7b1f RD |
928 | ((eq->eqn / 4) << PAGE_SHIFT), |
929 | PAGE_SIZE); | |
930 | if (!priv->eq_table.uar_map[index]) { | |
931 | mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", | |
932 | eq->eqn); | |
933 | return NULL; | |
934 | } | |
935 | } | |
936 | ||
937 | return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); | |
938 | } | |
939 | ||
bfc0d8c3 DB |
940 | static void mlx4_unmap_uar(struct mlx4_dev *dev) |
941 | { | |
942 | struct mlx4_priv *priv = mlx4_priv(dev); | |
943 | int i; | |
944 | ||
945 | for (i = 0; i < mlx4_num_eq_uar(dev); ++i) | |
946 | if (priv->eq_table.uar_map[i]) { | |
947 | iounmap(priv->eq_table.uar_map[i]); | |
948 | priv->eq_table.uar_map[i] = NULL; | |
949 | } | |
950 | } | |
951 | ||
3d73c288 RD |
952 | static int mlx4_create_eq(struct mlx4_dev *dev, int nent, |
953 | u8 intr, struct mlx4_eq *eq) | |
225c7b1f RD |
954 | { |
955 | struct mlx4_priv *priv = mlx4_priv(dev); | |
956 | struct mlx4_cmd_mailbox *mailbox; | |
957 | struct mlx4_eq_context *eq_context; | |
958 | int npages; | |
959 | u64 *dma_list = NULL; | |
960 | dma_addr_t t; | |
961 | u64 mtt_addr; | |
962 | int err = -ENOMEM; | |
963 | int i; | |
964 | ||
965 | eq->dev = dev; | |
966 | eq->nent = roundup_pow_of_two(max(nent, 2)); | |
43c816c6 IS |
967 | /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with |
968 | * strides of 64B,128B and 256B. | |
969 | */ | |
970 | npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; | |
225c7b1f RD |
971 | |
972 | eq->page_list = kmalloc(npages * sizeof *eq->page_list, | |
973 | GFP_KERNEL); | |
974 | if (!eq->page_list) | |
975 | goto err_out; | |
976 | ||
977 | for (i = 0; i < npages; ++i) | |
978 | eq->page_list[i].buf = NULL; | |
979 | ||
980 | dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); | |
981 | if (!dma_list) | |
982 | goto err_out_free; | |
983 | ||
984 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
985 | if (IS_ERR(mailbox)) | |
986 | goto err_out_free; | |
987 | eq_context = mailbox->buf; | |
988 | ||
989 | for (i = 0; i < npages; ++i) { | |
872bf2fb YH |
990 | eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> |
991 | pdev->dev, | |
992 | PAGE_SIZE, &t, | |
993 | GFP_KERNEL); | |
225c7b1f RD |
994 | if (!eq->page_list[i].buf) |
995 | goto err_out_free_pages; | |
996 | ||
997 | dma_list[i] = t; | |
998 | eq->page_list[i].map = t; | |
999 | ||
1000 | memset(eq->page_list[i].buf, 0, PAGE_SIZE); | |
1001 | } | |
1002 | ||
1003 | eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); | |
1004 | if (eq->eqn == -1) | |
1005 | goto err_out_free_pages; | |
1006 | ||
1007 | eq->doorbell = mlx4_get_eq_uar(dev, eq); | |
1008 | if (!eq->doorbell) { | |
1009 | err = -ENOMEM; | |
1010 | goto err_out_free_eq; | |
1011 | } | |
1012 | ||
1013 | err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); | |
1014 | if (err) | |
1015 | goto err_out_free_eq; | |
1016 | ||
1017 | err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); | |
1018 | if (err) | |
1019 | goto err_out_free_mtt; | |
1020 | ||
225c7b1f RD |
1021 | eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | |
1022 | MLX4_EQ_STATE_ARMED); | |
1023 | eq_context->log_eq_size = ilog2(eq->nent); | |
1024 | eq_context->intr = intr; | |
1025 | eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; | |
1026 | ||
1027 | mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); | |
1028 | eq_context->mtt_base_addr_h = mtt_addr >> 32; | |
1029 | eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); | |
1030 | ||
1031 | err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); | |
1032 | if (err) { | |
1033 | mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); | |
1034 | goto err_out_free_mtt; | |
1035 | } | |
1036 | ||
1037 | kfree(dma_list); | |
1038 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1039 | ||
1040 | eq->cons_index = 0; | |
1041 | ||
3dca0f42 MB |
1042 | INIT_LIST_HEAD(&eq->tasklet_ctx.list); |
1043 | INIT_LIST_HEAD(&eq->tasklet_ctx.process_list); | |
1044 | spin_lock_init(&eq->tasklet_ctx.lock); | |
1045 | tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb, | |
1046 | (unsigned long)&eq->tasklet_ctx); | |
1047 | ||
225c7b1f RD |
1048 | return err; |
1049 | ||
1050 | err_out_free_mtt: | |
1051 | mlx4_mtt_cleanup(dev, &eq->mtt); | |
1052 | ||
1053 | err_out_free_eq: | |
7c6d74d2 | 1054 | mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); |
225c7b1f RD |
1055 | |
1056 | err_out_free_pages: | |
1057 | for (i = 0; i < npages; ++i) | |
1058 | if (eq->page_list[i].buf) | |
872bf2fb | 1059 | dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, |
225c7b1f RD |
1060 | eq->page_list[i].buf, |
1061 | eq->page_list[i].map); | |
1062 | ||
1063 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1064 | ||
1065 | err_out_free: | |
1066 | kfree(eq->page_list); | |
1067 | kfree(dma_list); | |
1068 | ||
1069 | err_out: | |
1070 | return err; | |
1071 | } | |
1072 | ||
1073 | static void mlx4_free_eq(struct mlx4_dev *dev, | |
1074 | struct mlx4_eq *eq) | |
1075 | { | |
1076 | struct mlx4_priv *priv = mlx4_priv(dev); | |
225c7b1f | 1077 | int err; |
225c7b1f | 1078 | int i; |
43c816c6 IS |
1079 | /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with |
1080 | * strides of 64B,128B and 256B | |
1081 | */ | |
1082 | int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; | |
225c7b1f | 1083 | |
30a5da5b | 1084 | err = mlx4_HW2SW_EQ(dev, eq->eqn); |
225c7b1f RD |
1085 | if (err) |
1086 | mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); | |
1087 | ||
bf1bac5b | 1088 | synchronize_irq(eq->irq); |
3dca0f42 | 1089 | tasklet_disable(&eq->tasklet_ctx.task); |
225c7b1f RD |
1090 | |
1091 | mlx4_mtt_cleanup(dev, &eq->mtt); | |
1092 | for (i = 0; i < npages; ++i) | |
872bf2fb YH |
1093 | dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, |
1094 | eq->page_list[i].buf, | |
1095 | eq->page_list[i].map); | |
225c7b1f RD |
1096 | |
1097 | kfree(eq->page_list); | |
7c6d74d2 | 1098 | mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); |
225c7b1f RD |
1099 | } |
1100 | ||
1101 | static void mlx4_free_irqs(struct mlx4_dev *dev) | |
1102 | { | |
1103 | struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; | |
c66fa19c | 1104 | int i; |
225c7b1f RD |
1105 | |
1106 | if (eq_table->have_irq) | |
872bf2fb | 1107 | free_irq(dev->persist->pdev->irq, dev); |
0b7ca5a9 | 1108 | |
b8dd786f | 1109 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) |
d1fdf24b | 1110 | if (eq_table->eq[i].have_irq) { |
de161803 IS |
1111 | free_cpumask_var(eq_table->eq[i].affinity_mask); |
1112 | #if defined(CONFIG_SMP) | |
1113 | irq_set_affinity_hint(eq_table->eq[i].irq, NULL); | |
1114 | #endif | |
225c7b1f | 1115 | free_irq(eq_table->eq[i].irq, eq_table->eq + i); |
d1fdf24b RD |
1116 | eq_table->eq[i].have_irq = 0; |
1117 | } | |
b8dd786f YP |
1118 | |
1119 | kfree(eq_table->irq_names); | |
225c7b1f RD |
1120 | } |
1121 | ||
3d73c288 | 1122 | static int mlx4_map_clr_int(struct mlx4_dev *dev) |
225c7b1f RD |
1123 | { |
1124 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1125 | ||
872bf2fb YH |
1126 | priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, |
1127 | priv->fw.clr_int_bar) + | |
225c7b1f RD |
1128 | priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); |
1129 | if (!priv->clr_base) { | |
1a91de28 | 1130 | mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); |
225c7b1f RD |
1131 | return -ENOMEM; |
1132 | } | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static void mlx4_unmap_clr_int(struct mlx4_dev *dev) | |
1138 | { | |
1139 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1140 | ||
1141 | iounmap(priv->clr_base); | |
1142 | } | |
1143 | ||
b8dd786f YP |
1144 | int mlx4_alloc_eq_table(struct mlx4_dev *dev) |
1145 | { | |
1146 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1147 | ||
1148 | priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, | |
1149 | sizeof *priv->eq_table.eq, GFP_KERNEL); | |
1150 | if (!priv->eq_table.eq) | |
1151 | return -ENOMEM; | |
1152 | ||
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | void mlx4_free_eq_table(struct mlx4_dev *dev) | |
1157 | { | |
1158 | kfree(mlx4_priv(dev)->eq_table.eq); | |
1159 | } | |
1160 | ||
3d73c288 | 1161 | int mlx4_init_eq_table(struct mlx4_dev *dev) |
225c7b1f RD |
1162 | { |
1163 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1164 | int err; | |
1165 | int i; | |
1166 | ||
758ff235 AL |
1167 | priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), |
1168 | sizeof *priv->eq_table.uar_map, | |
1169 | GFP_KERNEL); | |
b8dd786f YP |
1170 | if (!priv->eq_table.uar_map) { |
1171 | err = -ENOMEM; | |
1172 | goto err_out_free; | |
1173 | } | |
1174 | ||
7ae0e400 MB |
1175 | err = mlx4_bitmap_init(&priv->eq_table.bitmap, |
1176 | roundup_pow_of_two(dev->caps.num_eqs), | |
1177 | dev->caps.num_eqs - 1, | |
1178 | dev->caps.reserved_eqs, | |
1179 | roundup_pow_of_two(dev->caps.num_eqs) - | |
1180 | dev->caps.num_eqs); | |
225c7b1f | 1181 | if (err) |
b8dd786f | 1182 | goto err_out_free; |
225c7b1f | 1183 | |
b8dd786f | 1184 | for (i = 0; i < mlx4_num_eq_uar(dev); ++i) |
225c7b1f RD |
1185 | priv->eq_table.uar_map[i] = NULL; |
1186 | ||
acba2420 JM |
1187 | if (!mlx4_is_slave(dev)) { |
1188 | err = mlx4_map_clr_int(dev); | |
1189 | if (err) | |
1190 | goto err_out_bitmap; | |
225c7b1f | 1191 | |
acba2420 JM |
1192 | priv->eq_table.clr_mask = |
1193 | swab32(1 << (priv->eq_table.inta_pin & 31)); | |
1194 | priv->eq_table.clr_int = priv->clr_base + | |
1195 | (priv->eq_table.inta_pin < 32 ? 4 : 0); | |
1196 | } | |
225c7b1f | 1197 | |
f5f5951c | 1198 | priv->eq_table.irq_names = |
c66fa19c | 1199 | kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1), |
f5f5951c | 1200 | GFP_KERNEL); |
b8dd786f YP |
1201 | if (!priv->eq_table.irq_names) { |
1202 | err = -ENOMEM; | |
c66fa19c | 1203 | goto err_out_clr_int; |
b8dd786f YP |
1204 | } |
1205 | ||
c66fa19c MB |
1206 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { |
1207 | if (i == MLX4_EQ_ASYNC) { | |
1208 | err = mlx4_create_eq(dev, | |
1209 | MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, | |
1210 | 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]); | |
1211 | } else { | |
c66fa19c | 1212 | struct mlx4_eq *eq = &priv->eq_table.eq[i]; |
db9777e3 | 1213 | #ifdef CONFIG_RFS_ACCEL |
c66fa19c MB |
1214 | int port = find_first_bit(eq->actv_ports.ports, |
1215 | dev->caps.num_ports) + 1; | |
1216 | ||
1217 | if (port <= dev->caps.num_ports) { | |
1218 | struct mlx4_port_info *info = | |
1219 | &mlx4_priv(dev)->port[port]; | |
1220 | ||
1221 | if (!info->rmap) { | |
1222 | info->rmap = alloc_irq_cpu_rmap( | |
1223 | mlx4_get_eqs_per_port(dev, port)); | |
1224 | if (!info->rmap) { | |
1225 | mlx4_warn(dev, "Failed to allocate cpu rmap\n"); | |
1226 | err = -ENOMEM; | |
1227 | goto err_out_unmap; | |
1228 | } | |
1229 | } | |
0b7ca5a9 | 1230 | |
c66fa19c MB |
1231 | err = irq_cpu_rmap_add( |
1232 | info->rmap, eq->irq); | |
1233 | if (err) | |
1234 | mlx4_warn(dev, "Failed adding irq rmap\n"); | |
1235 | } | |
1236 | #endif | |
1237 | err = mlx4_create_eq(dev, dev->caps.num_cqs - | |
1238 | dev->caps.reserved_cqs + | |
1239 | MLX4_NUM_SPARE_EQE, | |
1240 | (dev->flags & MLX4_FLAG_MSI_X) ? | |
1241 | i + 1 - !!(i > MLX4_EQ_ASYNC) : 0, | |
1242 | eq); | |
0b7ca5a9 | 1243 | } |
c66fa19c MB |
1244 | if (err) |
1245 | goto err_out_unmap; | |
0b7ca5a9 YP |
1246 | } |
1247 | ||
225c7b1f | 1248 | if (dev->flags & MLX4_FLAG_MSI_X) { |
b8dd786f YP |
1249 | const char *eq_name; |
1250 | ||
c66fa19c MB |
1251 | snprintf(priv->eq_table.irq_names + |
1252 | MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, | |
1253 | MLX4_IRQNAME_SIZE, | |
1254 | "mlx4-async@pci:%s", | |
1255 | pci_name(dev->persist->pdev)); | |
1256 | eq_name = priv->eq_table.irq_names + | |
1257 | MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; | |
225c7b1f | 1258 | |
c66fa19c MB |
1259 | err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, |
1260 | mlx4_msi_x_interrupt, 0, eq_name, | |
1261 | priv->eq_table.eq + MLX4_EQ_ASYNC); | |
1262 | if (err) | |
1263 | goto err_out_unmap; | |
225c7b1f | 1264 | |
c66fa19c | 1265 | priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; |
225c7b1f | 1266 | } else { |
f5f5951c AB |
1267 | snprintf(priv->eq_table.irq_names, |
1268 | MLX4_IRQNAME_SIZE, | |
1269 | DRV_NAME "@pci:%s", | |
872bf2fb YH |
1270 | pci_name(dev->persist->pdev)); |
1271 | err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, | |
f5f5951c | 1272 | IRQF_SHARED, priv->eq_table.irq_names, dev); |
225c7b1f | 1273 | if (err) |
c66fa19c | 1274 | goto err_out_unmap; |
225c7b1f RD |
1275 | |
1276 | priv->eq_table.have_irq = 1; | |
1277 | } | |
1278 | ||
00f5ce99 | 1279 | err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, |
c66fa19c | 1280 | priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); |
225c7b1f RD |
1281 | if (err) |
1282 | mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", | |
c66fa19c | 1283 | priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); |
225c7b1f | 1284 | |
c66fa19c MB |
1285 | /* arm ASYNC eq */ |
1286 | eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1); | |
225c7b1f | 1287 | |
225c7b1f RD |
1288 | return 0; |
1289 | ||
225c7b1f | 1290 | err_out_unmap: |
c66fa19c MB |
1291 | while (i >= 0) |
1292 | mlx4_free_eq(dev, &priv->eq_table.eq[i--]); | |
1293 | #ifdef CONFIG_RFS_ACCEL | |
1294 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
1295 | if (mlx4_priv(dev)->port[i].rmap) { | |
1296 | free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); | |
1297 | mlx4_priv(dev)->port[i].rmap = NULL; | |
1298 | } | |
b8dd786f | 1299 | } |
c66fa19c MB |
1300 | #endif |
1301 | mlx4_free_irqs(dev); | |
1302 | ||
1303 | err_out_clr_int: | |
acba2420 JM |
1304 | if (!mlx4_is_slave(dev)) |
1305 | mlx4_unmap_clr_int(dev); | |
225c7b1f | 1306 | |
b8dd786f | 1307 | err_out_bitmap: |
bfc0d8c3 | 1308 | mlx4_unmap_uar(dev); |
225c7b1f | 1309 | mlx4_bitmap_cleanup(&priv->eq_table.bitmap); |
b8dd786f YP |
1310 | |
1311 | err_out_free: | |
1312 | kfree(priv->eq_table.uar_map); | |
1313 | ||
225c7b1f RD |
1314 | return err; |
1315 | } | |
1316 | ||
1317 | void mlx4_cleanup_eq_table(struct mlx4_dev *dev) | |
1318 | { | |
1319 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1320 | int i; | |
1321 | ||
00f5ce99 | 1322 | mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, |
c66fa19c | 1323 | priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); |
225c7b1f | 1324 | |
c66fa19c MB |
1325 | #ifdef CONFIG_RFS_ACCEL |
1326 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
1327 | if (mlx4_priv(dev)->port[i].rmap) { | |
1328 | free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); | |
1329 | mlx4_priv(dev)->port[i].rmap = NULL; | |
1330 | } | |
1331 | } | |
1332 | #endif | |
225c7b1f RD |
1333 | mlx4_free_irqs(dev); |
1334 | ||
c66fa19c | 1335 | for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) |
225c7b1f | 1336 | mlx4_free_eq(dev, &priv->eq_table.eq[i]); |
225c7b1f | 1337 | |
acba2420 JM |
1338 | if (!mlx4_is_slave(dev)) |
1339 | mlx4_unmap_clr_int(dev); | |
225c7b1f | 1340 | |
bfc0d8c3 | 1341 | mlx4_unmap_uar(dev); |
225c7b1f | 1342 | mlx4_bitmap_cleanup(&priv->eq_table.bitmap); |
b8dd786f YP |
1343 | |
1344 | kfree(priv->eq_table.uar_map); | |
225c7b1f | 1345 | } |
e7c1c2c4 YP |
1346 | |
1347 | /* A test that verifies that we can accept interrupts on all | |
1348 | * the irq vectors of the device. | |
1349 | * Interrupts are checked using the NOP command. | |
1350 | */ | |
1351 | int mlx4_test_interrupts(struct mlx4_dev *dev) | |
1352 | { | |
1353 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1354 | int i; | |
1355 | int err; | |
1356 | ||
1357 | err = mlx4_NOP(dev); | |
1358 | /* When not in MSI_X, there is only one irq to check */ | |
acba2420 | 1359 | if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev)) |
e7c1c2c4 YP |
1360 | return err; |
1361 | ||
1362 | /* A loop over all completion vectors, for each vector we will check | |
1363 | * whether it works by mapping command completions to that vector | |
1364 | * and performing a NOP command | |
1365 | */ | |
1366 | for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) { | |
1367 | /* Temporary use polling for command completions */ | |
1368 | mlx4_cmd_use_polling(dev); | |
1369 | ||
b3834be5 | 1370 | /* Map the new eq to handle all asynchronous events */ |
00f5ce99 | 1371 | err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, |
e7c1c2c4 YP |
1372 | priv->eq_table.eq[i].eqn); |
1373 | if (err) { | |
1374 | mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); | |
1375 | mlx4_cmd_use_events(dev); | |
1376 | break; | |
1377 | } | |
1378 | ||
1379 | /* Go back to using events */ | |
1380 | mlx4_cmd_use_events(dev); | |
1381 | err = mlx4_NOP(dev); | |
1382 | } | |
1383 | ||
1384 | /* Return to default */ | |
00f5ce99 | 1385 | mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, |
c66fa19c | 1386 | priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); |
e7c1c2c4 YP |
1387 | return err; |
1388 | } | |
1389 | EXPORT_SYMBOL(mlx4_test_interrupts); | |
0b7ca5a9 | 1390 | |
c66fa19c | 1391 | bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector) |
0b7ca5a9 | 1392 | { |
c66fa19c | 1393 | struct mlx4_priv *priv = mlx4_priv(dev); |
0b7ca5a9 | 1394 | |
c66fa19c MB |
1395 | vector = MLX4_CQ_TO_EQ_VECTOR(vector); |
1396 | if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) || | |
1397 | (vector == MLX4_EQ_ASYNC)) | |
1398 | return false; | |
1399 | ||
1400 | return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports); | |
1401 | } | |
1402 | EXPORT_SYMBOL(mlx4_is_eq_vector_valid); | |
1403 | ||
1404 | u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port) | |
1405 | { | |
1406 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1407 | unsigned int i; | |
1408 | unsigned int sum = 0; | |
1409 | ||
1410 | for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) | |
1411 | sum += !!test_bit(port - 1, | |
1412 | priv->eq_table.eq[i].actv_ports.ports); | |
1413 | ||
1414 | return sum; | |
1415 | } | |
1416 | EXPORT_SYMBOL(mlx4_get_eqs_per_port); | |
1417 | ||
1418 | int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector) | |
1419 | { | |
1420 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1421 | ||
1422 | vector = MLX4_CQ_TO_EQ_VECTOR(vector); | |
1423 | if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1)) | |
1424 | return -EINVAL; | |
1425 | ||
1426 | return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports, | |
1427 | dev->caps.num_ports) > 1); | |
1428 | } | |
1429 | EXPORT_SYMBOL(mlx4_is_eq_shared); | |
1430 | ||
1431 | struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port) | |
1432 | { | |
1433 | return mlx4_priv(dev)->port[port].rmap; | |
1434 | } | |
1435 | EXPORT_SYMBOL(mlx4_get_cpu_rmap); | |
1436 | ||
1437 | int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector) | |
1438 | { | |
0b7ca5a9 | 1439 | struct mlx4_priv *priv = mlx4_priv(dev); |
c66fa19c MB |
1440 | int err = 0, i = 0; |
1441 | u32 min_ref_count_val = (u32)-1; | |
1442 | int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector); | |
1443 | int *prequested_vector = NULL; | |
1444 | ||
0b7ca5a9 | 1445 | |
730c41d5 | 1446 | mutex_lock(&priv->msix_ctl.pool_lock); |
c66fa19c MB |
1447 | if (requested_vector < (dev->caps.num_comp_vectors + 1) && |
1448 | (requested_vector >= 0) && | |
1449 | (requested_vector != MLX4_EQ_ASYNC)) { | |
1450 | if (test_bit(port - 1, | |
1451 | priv->eq_table.eq[requested_vector].actv_ports.ports)) { | |
1452 | prequested_vector = &requested_vector; | |
1453 | } else { | |
1454 | struct mlx4_eq *eq; | |
1455 | ||
1456 | for (i = 1; i < port; | |
1457 | requested_vector += mlx4_get_eqs_per_port(dev, i++)) | |
1458 | ; | |
1459 | ||
1460 | eq = &priv->eq_table.eq[requested_vector]; | |
1461 | if (requested_vector < dev->caps.num_comp_vectors + 1 && | |
1462 | test_bit(port - 1, eq->actv_ports.ports)) { | |
1463 | prequested_vector = &requested_vector; | |
d9236c3f | 1464 | } |
c66fa19c MB |
1465 | } |
1466 | } | |
1467 | ||
1468 | if (!prequested_vector) { | |
1469 | requested_vector = -1; | |
1470 | for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1; | |
1471 | i++) { | |
1472 | struct mlx4_eq *eq = &priv->eq_table.eq[i]; | |
1473 | ||
1474 | if (min_ref_count_val > eq->ref_count && | |
1475 | test_bit(port - 1, eq->actv_ports.ports)) { | |
1476 | min_ref_count_val = eq->ref_count; | |
1477 | requested_vector = i; | |
0b7ca5a9 | 1478 | } |
c66fa19c | 1479 | } |
2eacc23c | 1480 | |
c66fa19c MB |
1481 | if (requested_vector < 0) { |
1482 | err = -ENOSPC; | |
1483 | goto err_unlock; | |
0b7ca5a9 | 1484 | } |
c66fa19c MB |
1485 | |
1486 | prequested_vector = &requested_vector; | |
0b7ca5a9 | 1487 | } |
c66fa19c MB |
1488 | |
1489 | if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && | |
1490 | dev->flags & MLX4_FLAG_MSI_X) { | |
1491 | set_bit(*prequested_vector, priv->msix_ctl.pool_bm); | |
1492 | snprintf(priv->eq_table.irq_names + | |
1493 | *prequested_vector * MLX4_IRQNAME_SIZE, | |
1494 | MLX4_IRQNAME_SIZE, "mlx4-%d@%s", | |
1495 | *prequested_vector, dev_name(&dev->persist->pdev->dev)); | |
1496 | ||
1497 | err = request_irq(priv->eq_table.eq[*prequested_vector].irq, | |
1498 | mlx4_msi_x_interrupt, 0, | |
1499 | &priv->eq_table.irq_names[*prequested_vector << 5], | |
1500 | priv->eq_table.eq + *prequested_vector); | |
1501 | ||
1502 | if (err) { | |
1503 | clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); | |
1504 | *prequested_vector = -1; | |
1505 | } else { | |
de161803 IS |
1506 | #if defined(CONFIG_SMP) |
1507 | mlx4_set_eq_affinity_hint(priv, *prequested_vector); | |
1508 | #endif | |
c66fa19c MB |
1509 | eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); |
1510 | priv->eq_table.eq[*prequested_vector].have_irq = 1; | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | if (!err && *prequested_vector >= 0) | |
1515 | priv->eq_table.eq[*prequested_vector].ref_count++; | |
1516 | ||
1517 | err_unlock: | |
730c41d5 | 1518 | mutex_unlock(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 1519 | |
c66fa19c MB |
1520 | if (!err && *prequested_vector >= 0) |
1521 | *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector); | |
1522 | else | |
0b7ca5a9 | 1523 | *vector = 0; |
c66fa19c | 1524 | |
0b7ca5a9 YP |
1525 | return err; |
1526 | } | |
1527 | EXPORT_SYMBOL(mlx4_assign_eq); | |
1528 | ||
c66fa19c | 1529 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec) |
35f6f453 AV |
1530 | { |
1531 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1532 | ||
c66fa19c | 1533 | return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq; |
35f6f453 AV |
1534 | } |
1535 | EXPORT_SYMBOL(mlx4_eq_get_irq); | |
1536 | ||
0b7ca5a9 YP |
1537 | void mlx4_release_eq(struct mlx4_dev *dev, int vec) |
1538 | { | |
1539 | struct mlx4_priv *priv = mlx4_priv(dev); | |
c66fa19c MB |
1540 | int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec); |
1541 | ||
1542 | mutex_lock(&priv->msix_ctl.pool_lock); | |
1543 | priv->eq_table.eq[eq_vec].ref_count--; | |
0b7ca5a9 | 1544 | |
c66fa19c MB |
1545 | /* once we allocated EQ, we don't release it because it might be binded |
1546 | * to cpu_rmap. | |
1547 | */ | |
1548 | mutex_unlock(&priv->msix_ctl.pool_lock); | |
0b7ca5a9 YP |
1549 | } |
1550 | EXPORT_SYMBOL(mlx4_release_eq); | |
1551 |