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Merge tag 'drm-misc-next-2017-01-30' of git://anongit.freedesktop.org/git/drm-misc...
[linux-block.git] / drivers / net / ethernet / mellanox / mlx4 / eq.c
CommitLineData
225c7b1f 1/*
51a379d0 2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
225c7b1f 34#include <linux/interrupt.h>
5a0e3ad6 35#include <linux/slab.h>
ee40fa06 36#include <linux/export.h>
27ac792c 37#include <linux/mm.h>
9cbe05c7 38#include <linux/dma-mapping.h>
225c7b1f
RD		 39
40#include <linux/mlx4/cmd.h>
d9236c3f 41#include <linux/cpu_rmap.h>
225c7b1f
RD		 42
43#include "mlx4.h"
44#include "fw.h"
45
f5f5951c 46enum {
0b7ca5a9 47 MLX4_IRQNAME_SIZE = 32
f5f5951c
AB		 48};
49
225c7b1f
RD		 50enum {
51 MLX4_NUM_ASYNC_EQE = 0x100,
52 MLX4_NUM_SPARE_EQE = 0x80,
53 MLX4_EQ_ENTRY_SIZE = 0x20
54};
55
225c7b1f
RD		 56#define MLX4_EQ_STATUS_OK ( 0 << 28)
57#define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
58#define MLX4_EQ_OWNER_SW ( 0 << 24)
59#define MLX4_EQ_OWNER_HW ( 1 << 24)
60#define MLX4_EQ_FLAG_EC ( 1 << 18)
61#define MLX4_EQ_FLAG_OI ( 1 << 17)
62#define MLX4_EQ_STATE_ARMED ( 9 << 8)
63#define MLX4_EQ_STATE_FIRED (10 << 8)
64#define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
65
66#define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
225c7b1f
RD		 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
acba2420 80 (1ull << MLX4_EVENT_TYPE_CMD) | \
fe6f700d 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \
acba2420 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
5984be90
JM		 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
225c7b1f 85
00f5ce99
JM		 86static u64 get_async_ev_mask(struct mlx4_dev *dev)
87{
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
be6a6b43
JM		 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT);
00f5ce99
JM		 93
94 return async_ev_mask;
95}
96
225c7b1f
RD		 97static void eq_set_ci(struct mlx4_eq *eq, int req_not)
98{
99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 req_not << 31),
101 eq->doorbell);
102 /* We still want ordering, just not swabbing, so add a barrier */
103 mb();
104}
105
43c816c6
IS		 106static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,
107 u8 eqe_size)
225c7b1f 108{
08ff3235 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */
43c816c6
IS		 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size;
111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with
112 * strides of 64B,128B and 256B.
113 * When 64B EQE is used, the first (in the lower addresses)
08ff3235
OG		 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
115 * contain the legacy EQE information.
43c816c6 116 * In all other cases, the first 32B contains the legacy EQE info.
08ff3235
OG		 117 */
118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
225c7b1f
RD		 119}
120
43c816c6 121static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size)
225c7b1f 122{
43c816c6 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size);
225c7b1f
RD		 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
125}
126
acba2420
JM		 127static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
128{
129 struct mlx4_eqe *eqe =
130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
131 return (!!(eqe->owner & 0x80) ^
132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
133 eqe : NULL;
134}
135
acba2420
JM		 136void mlx4_gen_slave_eqe(struct work_struct *work)
137{
138 struct mlx4_mfunc_master_ctx *master =
139 container_of(work, struct mlx4_mfunc_master_ctx,
140 slave_event_work);
141 struct mlx4_mfunc *mfunc =
142 container_of(master, struct mlx4_mfunc, master);
143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
144 struct mlx4_dev *dev = &priv->dev;
145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
146 struct mlx4_eqe *eqe;
147 u8 slave;
74d4943f 148 int i, phys_port, slave_port;
acba2420
JM		 149
150 for (eqe = next_slave_event_eqe(slave_eq); eqe;
151 eqe = next_slave_event_eqe(slave_eq)) {
152 slave = eqe->slave_id;
153
8d80d04a
MS		 154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE &&
155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN &&
156 mlx4_is_bonded(dev)) {
157 struct mlx4_port_cap port_cap;
158
159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state)
160 goto consume;
161
162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state)
163 goto consume;
164 }
acba2420
JM		 165 /* All active slaves need to receive the event */
166 if (slave == ALL_SLAVES) {
bffb023a 167 for (i = 0; i <= dev->persist->num_vfs; i++) {
74d4943f
OG		 168 phys_port = 0;
169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT &&
170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) {
171 phys_port = eqe->event.port_mgmt_change.port;
172 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port);
173 if (slave_port < 0) /* VF doesn't have this port */
174 continue;
175 eqe->event.port_mgmt_change.port = slave_port;
176 }
bffb023a
JM		 177 if (mlx4_GEN_EQE(dev, i, eqe))
178 mlx4_warn(dev, "Failed to generate event for slave %d\n",
179 i);
74d4943f
OG		 180 if (phys_port)
181 eqe->event.port_mgmt_change.port = phys_port;
acba2420
JM		 182 }
183 } else {
184 if (mlx4_GEN_EQE(dev, slave, eqe))
1a91de28
JP		 185 mlx4_warn(dev, "Failed to generate event for slave %d\n",
186 slave);
acba2420 187 }
8d80d04a 188consume:
acba2420
JM		 189 ++slave_eq->cons;
190 }
191}
192
193
194static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
195{
196 struct mlx4_priv *priv = mlx4_priv(dev);
197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
992e8e6e
JM		 198 struct mlx4_eqe *s_eqe;
199 unsigned long flags;
acba2420 200
992e8e6e
JM		 201 spin_lock_irqsave(&slave_eq->event_lock, flags);
202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
acba2420
JM		 203 if ((!!(s_eqe->owner & 0x80)) ^
204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
1a91de28
JP		 205 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n",
206 slave);
992e8e6e 207 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
acba2420
JM		 208 return;
209 }
210
c02b0501 211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1);
acba2420
JM		 212 s_eqe->slave_id = slave;
213 /* ensure all information is written before setting the ownersip bit */
12b3375f 214 dma_wmb();
acba2420
JM		 215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
216 ++slave_eq->prod;
217
218 queue_work(priv->mfunc.master.comm_wq,
219 &priv->mfunc.master.slave_event_work);
992e8e6e 220 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
acba2420
JM		 221}
222
223static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
224 struct mlx4_eqe *eqe)
225{
226 struct mlx4_priv *priv = mlx4_priv(dev);
acba2420 227
bffb023a
JM		 228 if (slave < 0 || slave > dev->persist->num_vfs ||
229 slave == dev->caps.function ||
230 !priv->mfunc.master.slave_state[slave].active)
acba2420 231 return;
acba2420
JM		 232
233 slave_event(dev, slave, eqe);
234}
235
db9777e3 236#if defined(CONFIG_SMP)
de161803
IS		 237static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec)
238{
239 int hint_err;
240 struct mlx4_dev *dev = &priv->dev;
241 struct mlx4_eq *eq = &priv->eq_table.eq[vec];
242
243 if (!eq->affinity_mask || cpumask_empty(eq->affinity_mask))
244 return;
245
246 hint_err = irq_set_affinity_hint(eq->irq, eq->affinity_mask);
247 if (hint_err)
248 mlx4_warn(dev, "irq_set_affinity_hint failed, err %d\n", hint_err);
249}
db9777e3 250#endif
de161803 251
993c401e
JM		 252int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
253{
254 struct mlx4_eqe eqe;
255
256 struct mlx4_priv *priv = mlx4_priv(dev);
257 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
258
259 if (!s_slave->active)
260 return 0;
261
262 memset(&eqe, 0, sizeof eqe);
263
264 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
265 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
74d4943f 266 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 267
268 return mlx4_GEN_EQE(dev, slave, &eqe);
269}
270EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
271
272int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
273{
274 struct mlx4_eqe eqe;
275
276 /*don't send if we don't have the that slave */
872bf2fb 277 if (dev->persist->num_vfs < slave)
993c401e
JM		 278 return 0;
279 memset(&eqe, 0, sizeof eqe);
280
281 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
282 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
74d4943f 283 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 284
285 return mlx4_GEN_EQE(dev, slave, &eqe);
286}
287EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
288
289int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
290 u8 port_subtype_change)
291{
292 struct mlx4_eqe eqe;
74d4943f 293 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port);
993c401e
JM		 294
295 /*don't send if we don't have the that slave */
872bf2fb 296 if (dev->persist->num_vfs < slave)
993c401e
JM		 297 return 0;
298 memset(&eqe, 0, sizeof eqe);
299
300 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
301 eqe.subtype = port_subtype_change;
74d4943f 302 eqe.event.port_change.port = cpu_to_be32(slave_port << 28);
993c401e
JM		 303
304 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
305 port_subtype_change, slave, port);
306 return mlx4_GEN_EQE(dev, slave, &eqe);
307}
308EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
309
310enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
311{
312 struct mlx4_priv *priv = mlx4_priv(dev);
313 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
449fc488
MB		 314 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
315
316 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
317 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 318 pr_err("%s: Error: asking for slave:%d, port:%d\n",
319 __func__, slave, port);
320 return SLAVE_PORT_DOWN;
321 }
322 return s_state[slave].port_state[port];
323}
324EXPORT_SYMBOL(mlx4_get_slave_port_state);
325
326static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
327 enum slave_port_state state)
328{
329 struct mlx4_priv *priv = mlx4_priv(dev);
330 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
449fc488 331 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
993c401e 332
449fc488
MB		 333 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
334 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 335 pr_err("%s: Error: asking for slave:%d, port:%d\n",
336 __func__, slave, port);
337 return -1;
338 }
339 s_state[slave].port_state[port] = state;
340
341 return 0;
342}
343
344static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
345{
346 int i;
347 enum slave_port_gen_event gen_event;
449fc488
MB		 348 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev,
349 port);
993c401e 350
872bf2fb 351 for (i = 0; i < dev->persist->num_vfs + 1; i++)
449fc488
MB		 352 if (test_bit(i, slaves_pport.slaves))
353 set_and_calc_slave_port_state(dev, i, port,
354 event, &gen_event);
993c401e
JM		 355}
356/**************************************************************************
357 The function get as input the new event to that port,
358 and according to the prev state change the slave's port state.
359 The events are:
360 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
361 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
362 MLX4_PORT_STATE_IB_EVENT_GID_VALID
363 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
364***************************************************************************/
365int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
366 u8 port, int event,
367 enum slave_port_gen_event *gen_event)
368{
369 struct mlx4_priv *priv = mlx4_priv(dev);
370 struct mlx4_slave_state *ctx = NULL;
371 unsigned long flags;
372 int ret = -1;
449fc488 373 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
993c401e
JM		 374 enum slave_port_state cur_state =
375 mlx4_get_slave_port_state(dev, slave, port);
376
377 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
378
449fc488
MB		 379 if (slave >= dev->num_slaves || port > dev->caps.num_ports ||
380 port <= 0 || !test_bit(port - 1, actv_ports.ports)) {
993c401e
JM		 381 pr_err("%s: Error: asking for slave:%d, port:%d\n",
382 __func__, slave, port);
383 return ret;
384 }
385
386 ctx = &priv->mfunc.master.slave_state[slave];
387 spin_lock_irqsave(&ctx->lock, flags);
388
993c401e
JM		 389 switch (cur_state) {
390 case SLAVE_PORT_DOWN:
391 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
392 mlx4_set_slave_port_state(dev, slave, port,
393 SLAVE_PENDING_UP);
394 break;
395 case SLAVE_PENDING_UP:
396 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
397 mlx4_set_slave_port_state(dev, slave, port,
398 SLAVE_PORT_DOWN);
399 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
400 mlx4_set_slave_port_state(dev, slave, port,
401 SLAVE_PORT_UP);
402 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
403 }
404 break;
405 case SLAVE_PORT_UP:
406 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
407 mlx4_set_slave_port_state(dev, slave, port,
408 SLAVE_PORT_DOWN);
409 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
410 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
411 event) {
412 mlx4_set_slave_port_state(dev, slave, port,
413 SLAVE_PENDING_UP);
414 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
415 }
416 break;
417 default:
1a91de28
JP		 418 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n",
419 __func__, slave, port);
420 goto out;
993c401e
JM		 421 }
422 ret = mlx4_get_slave_port_state(dev, slave, port);
993c401e
JM		 423
424out:
425 spin_unlock_irqrestore(&ctx->lock, flags);
426 return ret;
427}
428
429EXPORT_SYMBOL(set_and_calc_slave_port_state);
430
431int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
432{
433 struct mlx4_eqe eqe;
434
435 memset(&eqe, 0, sizeof eqe);
436
437 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
438 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
439 eqe.event.port_mgmt_change.port = port;
440 eqe.event.port_mgmt_change.params.port_info.changed_attr =
441 cpu_to_be32((u32) attr);
442
443 slave_event(dev, ALL_SLAVES, &eqe);
444 return 0;
445}
446EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
447
acba2420
JM		 448void mlx4_master_handle_slave_flr(struct work_struct *work)
449{
450 struct mlx4_mfunc_master_ctx *master =
451 container_of(work, struct mlx4_mfunc_master_ctx,
452 slave_flr_event_work);
453 struct mlx4_mfunc *mfunc =
454 container_of(master, struct mlx4_mfunc, master);
455 struct mlx4_priv *priv =
456 container_of(mfunc, struct mlx4_priv, mfunc);
457 struct mlx4_dev *dev = &priv->dev;
458 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
459 int i;
460 int err;
311f813a 461 unsigned long flags;
acba2420
JM		 462
463 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
464
465 for (i = 0 ; i < dev->num_slaves; i++) {
466
467 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
1a91de28
JP		 468 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n",
469 i);
55ad3592
YH		 470 /* In case of 'Reset flow' FLR can be generated for
471 * a slave before mlx4_load_one is done.
472 * make sure interface is up before trying to delete
473 * slave resources which weren't allocated yet.
474 */
475 if (dev->persist->interface_state &
476 MLX4_INTERFACE_STATE_UP)
477 mlx4_delete_all_resources_for_slave(dev, i);
acba2420 478 /*return the slave to running mode*/
311f813a 479 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 480 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
481 slave_state[i].is_slave_going_down = 0;
311f813a 482 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 483 /*notify the FW:*/
484 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
485 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
486 if (err)
1a91de28
JP		 487 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n",
488 i);
acba2420
JM		 489 }
490 }
491}
492
225c7b1f
RD		 493static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
494{
acba2420 495 struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f 496 struct mlx4_eqe *eqe;
3dca0f42 497 int cqn = -1;
225c7b1f
RD		 498 int eqes_found = 0;
499 int set_ci = 0;
27bf91d6 500 int port;
acba2420
JM		 501 int slave = 0;
502 int ret;
503 u32 flr_slave;
504 u8 update_slave_state;
505 int i;
993c401e 506 enum slave_port_gen_event gen_event;
311f813a 507 unsigned long flags;
948e306d 508 struct mlx4_vport_state *s_info;
43c816c6 509 int eqe_size = dev->caps.eqe_size;
225c7b1f 510
43c816c6 511 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) {
225c7b1f
RD		 512 /*
513 * Make sure we read EQ entry contents after we've
514 * checked the ownership bit.
515 */
12b3375f 516 dma_rmb();
225c7b1f
RD		 517
518 switch (eqe->type) {
519 case MLX4_EVENT_TYPE_COMP:
520 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
521 mlx4_cq_completion(dev, cqn);
522 break;
523
524 case MLX4_EVENT_TYPE_PATH_MIG:
525 case MLX4_EVENT_TYPE_COMM_EST:
526 case MLX4_EVENT_TYPE_SQ_DRAINED:
527 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
528 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
529 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
530 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
531 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
acba2420
JM		 532 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
533 if (mlx4_is_master(dev)) {
534 /* forward only to slave owning the QP */
535 ret = mlx4_get_slave_from_resource_id(dev,
536 RES_QP,
537 be32_to_cpu(eqe->event.qp.qpn)
538 & 0xffffff, &slave);
539 if (ret && ret != -ENOENT) {
1a91de28 540 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
acba2420
JM		 541 eqe->type, eqe->subtype,
542 eq->eqn, eq->cons_index, ret);
543 break;
544 }
545
546 if (!ret && slave != dev->caps.function) {
547 mlx4_slave_event(dev, slave, eqe);
548 break;
549 }
550
551 }
552 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
553 0xffffff, eqe->type);
225c7b1f
RD		 554 break;
555
556 case MLX4_EVENT_TYPE_SRQ_LIMIT:
9577b174
JM		 557 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT. srq_no=0x%x, eq 0x%x\n",
558 __func__, be32_to_cpu(eqe->event.srq.srqn),
559 eq->eqn);
225c7b1f 560 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
acba2420
JM		 561 if (mlx4_is_master(dev)) {
562 /* forward only to slave owning the SRQ */
563 ret = mlx4_get_slave_from_resource_id(dev,
564 RES_SRQ,
565 be32_to_cpu(eqe->event.srq.srqn)
566 & 0xffffff,
567 &slave);
568 if (ret && ret != -ENOENT) {
1a91de28 569 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
acba2420
JM		 570 eqe->type, eqe->subtype,
571 eq->eqn, eq->cons_index, ret);
572 break;
573 }
9577b174
JM		 574 if (eqe->type ==
575 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
576 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n",
577 __func__, slave,
578 be32_to_cpu(eqe->event.srq.srqn),
579 eqe->type, eqe->subtype);
acba2420
JM		 580
581 if (!ret && slave != dev->caps.function) {
9577b174
JM		 582 if (eqe->type ==
583 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR)
584 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n",
585 __func__, eqe->type,
586 eqe->subtype, slave);
acba2420
JM		 587 mlx4_slave_event(dev, slave, eqe);
588 break;
589 }
590 }
591 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
592 0xffffff, eqe->type);
225c7b1f
RD		 593 break;
594
595 case MLX4_EVENT_TYPE_CMD:
596 mlx4_cmd_event(dev,
597 be16_to_cpu(eqe->event.cmd.token),
598 eqe->event.cmd.status,
599 be64_to_cpu(eqe->event.cmd.out_param));
600 break;
601
449fc488
MB		 602 case MLX4_EVENT_TYPE_PORT_CHANGE: {
603 struct mlx4_slaves_pport slaves_port;
27bf91d6 604 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
449fc488 605 slaves_port = mlx4_phys_to_slaves_pport(dev, port);
27bf91d6 606 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
993c401e 607 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
27bf91d6
YP		 608 port);
609 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
993c401e
JM		 610 if (!mlx4_is_master(dev))
611 break;
872bf2fb
YH		 612 for (i = 0; i < dev->persist->num_vfs + 1;
613 i++) {
8d80d04a
MS		 614 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
615
616 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
449fc488 617 continue;
993c401e
JM		 618 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
619 if (i == mlx4_master_func_num(dev))
620 continue;
1a91de28 621 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n",
acba2420 622 __func__, i, port);
1c1bf349 623 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
449fc488
MB		 624 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
625 eqe->event.port_change.port =
626 cpu_to_be32(
627 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
8d80d04a 628 | (reported_port << 28));
948e306d 629 mlx4_slave_event(dev, i, eqe);
449fc488 630 }
993c401e
JM		 631 } else { /* IB port */
632 set_and_calc_slave_port_state(dev, i, port,
633 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
634 &gen_event);
635 /*we can be in pending state, then do not send port_down event*/
636 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
637 if (i == mlx4_master_func_num(dev))
638 continue;
74d4943f
OG		 639 eqe->event.port_change.port =
640 cpu_to_be32(
641 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
642 | (mlx4_phys_to_slave_port(dev, i, port) << 28));
993c401e
JM		 643 mlx4_slave_event(dev, i, eqe);
644 }
acba2420 645 }
993c401e 646 }
27bf91d6 647 } else {
993c401e
JM		 648 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
649
27bf91d6 650 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
acba2420 651
993c401e
JM		 652 if (!mlx4_is_master(dev))
653 break;
654 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
872bf2fb
YH		 655 for (i = 0;
656 i < dev->persist->num_vfs + 1;
657 i++) {
8d80d04a
MS		 658 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port);
659
660 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev))
449fc488 661 continue;
993c401e 662 if (i == mlx4_master_func_num(dev))
acba2420 663 continue;
1c1bf349 664 s_info = &priv->mfunc.master.vf_oper[i].vport[port].state;
449fc488
MB		 665 if (IFLA_VF_LINK_STATE_AUTO == s_info->link_state) {
666 eqe->event.port_change.port =
667 cpu_to_be32(
668 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF)
8d80d04a 669 | (reported_port << 28));
948e306d 670 mlx4_slave_event(dev, i, eqe);
449fc488 671 }
acba2420 672 }
993c401e
JM		 673 else /* IB port */
674 /* port-up event will be sent to a slave when the
675 * slave's alias-guid is set. This is done in alias_GUID.c
676 */
677 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
27bf91d6 678 }
225c7b1f 679 break;
449fc488 680 }
225c7b1f
RD		 681
682 case MLX4_EVENT_TYPE_CQ_ERROR:
683 mlx4_warn(dev, "CQ %s on CQN %06x\n",
684 eqe->event.cq_err.syndrome == 1 ?
685 "overrun" : "access violation",
686 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
acba2420
JM		 687 if (mlx4_is_master(dev)) {
688 ret = mlx4_get_slave_from_resource_id(dev,
689 RES_CQ,
690 be32_to_cpu(eqe->event.cq_err.cqn)
691 & 0xffffff, &slave);
692 if (ret && ret != -ENOENT) {
1a91de28
JP		 693 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n",
694 eqe->type, eqe->subtype,
695 eq->eqn, eq->cons_index, ret);
acba2420
JM		 696 break;
697 }
698
699 if (!ret && slave != dev->caps.function) {
700 mlx4_slave_event(dev, slave, eqe);
701 break;
702 }
703 }
704 mlx4_cq_event(dev,
705 be32_to_cpu(eqe->event.cq_err.cqn)
706 & 0xffffff,
225c7b1f
RD		 707 eqe->type);
708 break;
709
710 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
711 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
712 break;
713
fe6f700d
YP		 714 case MLX4_EVENT_TYPE_OP_REQUIRED:
715 atomic_inc(&priv->opreq_count);
716 /* FW commands can't be executed from interrupt context
717 * working in deferred task
718 */
719 queue_work(mlx4_wq, &priv->opreq_task);
720 break;
721
acba2420
JM		 722 case MLX4_EVENT_TYPE_COMM_CHANNEL:
723 if (!mlx4_is_master(dev)) {
1a91de28 724 mlx4_warn(dev, "Received comm channel event for non master device\n");
acba2420
JM		 725 break;
726 }
727 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
728 eqe->event.comm_channel_arm.bit_vec,
729 sizeof eqe->event.comm_channel_arm.bit_vec);
730 queue_work(priv->mfunc.master.comm_wq,
731 &priv->mfunc.master.comm_work);
732 break;
733
734 case MLX4_EVENT_TYPE_FLR_EVENT:
735 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
736 if (!mlx4_is_master(dev)) {
1a91de28 737 mlx4_warn(dev, "Non-master function received FLR event\n");
acba2420
JM		 738 break;
739 }
740
741 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
742
30f7c73b 743 if (flr_slave >= dev->num_slaves) {
acba2420
JM		 744 mlx4_warn(dev,
745 "Got FLR for unknown function: %d\n",
746 flr_slave);
747 update_slave_state = 0;
748 } else
749 update_slave_state = 1;
750
311f813a 751 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
acba2420
JM		 752 if (update_slave_state) {
753 priv->mfunc.master.slave_state[flr_slave].active = false;
754 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
755 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
756 }
311f813a 757 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
a0667a83
YH		 758 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN,
759 flr_slave);
acba2420
JM		 760 queue_work(priv->mfunc.master.comm_wq,
761 &priv->mfunc.master.slave_flr_event_work);
762 break;
5984be90
JM		 763
764 case MLX4_EVENT_TYPE_FATAL_WARNING:
765 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
766 if (mlx4_is_master(dev))
767 for (i = 0; i < dev->num_slaves; i++) {
1a91de28
JP		 768 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n",
769 __func__, i);
5984be90
JM		 770 if (i == dev->caps.function)
771 continue;
772 mlx4_slave_event(dev, i, eqe);
773 }
1a91de28
JP		 774 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n",
775 be16_to_cpu(eqe->event.warming.warning_threshold),
776 be16_to_cpu(eqe->event.warming.current_temperature));
5984be90 777 } else
1a91de28 778 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
5984be90
JM		 779 eqe->type, eqe->subtype, eq->eqn,
780 eq->cons_index, eqe->owner, eq->nent,
781 eqe->slave_id,
782 !!(eqe->owner & 0x80) ^
783 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
784
785 break;
786
00f5ce99
JM		 787 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
788 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
789 (unsigned long) eqe);
790 break;
791
be6a6b43
JM		 792 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT:
793 switch (eqe->subtype) {
794 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE:
795 mlx4_warn(dev, "Bad cable detected on port %u\n",
796 eqe->event.bad_cable.port);
797 break;
798 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE:
799 mlx4_warn(dev, "Unsupported cable detected\n");
800 break;
801 default:
802 mlx4_dbg(dev,
803 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n",
804 eqe->type, eqe->subtype, eq->eqn,
805 eq->cons_index, eqe->owner, eq->nent,
806 !!(eqe->owner & 0x80) ^
807 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
808 break;
809 }
810 break;
811
225c7b1f
RD		 812 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
813 case MLX4_EVENT_TYPE_ECC_DETECT:
814 default:
1a91de28 815 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n",
acba2420
JM		 816 eqe->type, eqe->subtype, eq->eqn,
817 eq->cons_index, eqe->owner, eq->nent,
818 eqe->slave_id,
819 !!(eqe->owner & 0x80) ^
820 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
225c7b1f 821 break;
acba2420 822 };
225c7b1f
RD		 823
824 ++eq->cons_index;
825 eqes_found = 1;
826 ++set_ci;
827
828 /*
829 * The HCA will think the queue has overflowed if we
830 * don't tell it we've been processing events. We
831 * create our EQs with MLX4_NUM_SPARE_EQE extra
832 * entries, so we must update our consumer index at
833 * least that often.
834 */
835 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
225c7b1f
RD		 836 eq_set_ci(eq, 0);
837 set_ci = 0;
838 }
839 }
840
841 eq_set_ci(eq, 1);
842
3dca0f42
MB		 843 /* cqn is 24bit wide but is initialized such that its higher bits
844 * are ones too. Thus, if we got any event, cqn's high bits should be off
845 * and we need to schedule the tasklet.
846 */
847 if (!(cqn & ~0xffffff))
848 tasklet_schedule(&eq->tasklet_ctx.task);
849
225c7b1f
RD		 850 return eqes_found;
851}
852
853static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
854{
855 struct mlx4_dev *dev = dev_ptr;
856 struct mlx4_priv *priv = mlx4_priv(dev);
857 int work = 0;
858 int i;
859
860 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
861
b8dd786f 862 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f
RD		 863 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
864
865 return IRQ_RETVAL(work);
866}
867
868static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
869{
870 struct mlx4_eq *eq = eq_ptr;
871 struct mlx4_dev *dev = eq->dev;
872
873 mlx4_eq_int(dev, eq);
874
875 /* MSI-X vectors always belong to us */
876 return IRQ_HANDLED;
877}
878
acba2420
JM		 879int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
880 struct mlx4_vhcr *vhcr,
881 struct mlx4_cmd_mailbox *inbox,
882 struct mlx4_cmd_mailbox *outbox,
883 struct mlx4_cmd_info *cmd)
884{
885 struct mlx4_priv *priv = mlx4_priv(dev);
886 struct mlx4_slave_event_eq_info *event_eq =
803143fb 887 priv->mfunc.master.slave_state[slave].event_eq;
acba2420 888 u32 in_modifier = vhcr->in_modifier;
c101c81b 889 u32 eqn = in_modifier & 0x3FF;
acba2420
JM		 890 u64 in_param = vhcr->in_param;
891 int err = 0;
803143fb 892 int i;
acba2420
JM		 893
894 if (slave == dev->caps.function)
895 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
896 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
897 MLX4_CMD_NATIVE);
803143fb
MA		 898 if (!err)
899 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
900 if (in_param & (1LL << i))
901 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
902
acba2420
JM		 903 return err;
904}
905
225c7b1f
RD		 906static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
907 int eq_num)
908{
909 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
f9baff50
JM		 910 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
911 MLX4_CMD_WRAPPED);
225c7b1f
RD		 912}
913
914static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
915 int eq_num)
916{
eb41049f 917 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
acba2420 918 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
f9baff50 919 MLX4_CMD_WRAPPED);
225c7b1f
RD		 920}
921
30a5da5b 922static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num)
225c7b1f 923{
30a5da5b
JM		 924 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ,
925 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 926}
927
b8dd786f
YP		 928static int mlx4_num_eq_uar(struct mlx4_dev *dev)
929{
930 /*
931 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
932 * we need to map, take the difference of highest index and
933 * the lowest index we'll use and add 1.
934 */
c66fa19c
MB		 935 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 -
936 dev->caps.reserved_eqs / 4 + 1;
b8dd786f
YP		 937}
938
3d73c288 939static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
225c7b1f
RD		 940{
941 struct mlx4_priv *priv = mlx4_priv(dev);
942 int index;
943
944 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
945
946 if (!priv->eq_table.uar_map[index]) {
947 priv->eq_table.uar_map[index] =
85743f1e
HN		 948 ioremap(
949 pci_resource_start(dev->persist->pdev, 2) +
950 ((eq->eqn / 4) << (dev->uar_page_shift)),
951 (1 << (dev->uar_page_shift)));
225c7b1f
RD		 952 if (!priv->eq_table.uar_map[index]) {
953 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
954 eq->eqn);
955 return NULL;
956 }
957 }
958
959 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
960}
961
bfc0d8c3
DB		 962static void mlx4_unmap_uar(struct mlx4_dev *dev)
963{
964 struct mlx4_priv *priv = mlx4_priv(dev);
965 int i;
966
967 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
968 if (priv->eq_table.uar_map[i]) {
969 iounmap(priv->eq_table.uar_map[i]);
970 priv->eq_table.uar_map[i] = NULL;
971 }
972}
973
3d73c288
RD		 974static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
975 u8 intr, struct mlx4_eq *eq)
225c7b1f
RD		 976{
977 struct mlx4_priv *priv = mlx4_priv(dev);
978 struct mlx4_cmd_mailbox *mailbox;
979 struct mlx4_eq_context *eq_context;
980 int npages;
981 u64 *dma_list = NULL;
982 dma_addr_t t;
983 u64 mtt_addr;
984 int err = -ENOMEM;
985 int i;
986
987 eq->dev = dev;
988 eq->nent = roundup_pow_of_two(max(nent, 2));
43c816c6
IS		 989 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
990 * strides of 64B,128B and 256B.
991 */
992 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE;
225c7b1f
RD		 993
994 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
995 GFP_KERNEL);
996 if (!eq->page_list)
997 goto err_out;
998
999 for (i = 0; i < npages; ++i)
1000 eq->page_list[i].buf = NULL;
1001
1002 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
1003 if (!dma_list)
1004 goto err_out_free;
1005
1006 mailbox = mlx4_alloc_cmd_mailbox(dev);
1007 if (IS_ERR(mailbox))
1008 goto err_out_free;
1009 eq_context = mailbox->buf;
1010
1011 for (i = 0; i < npages; ++i) {
872bf2fb
YH		 1012 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist->
1013 pdev->dev,
1014 PAGE_SIZE, &t,
1015 GFP_KERNEL);
225c7b1f
RD		 1016 if (!eq->page_list[i].buf)
1017 goto err_out_free_pages;
1018
1019 dma_list[i] = t;
1020 eq->page_list[i].map = t;
1021
1022 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
1023 }
1024
1025 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
1026 if (eq->eqn == -1)
1027 goto err_out_free_pages;
1028
1029 eq->doorbell = mlx4_get_eq_uar(dev, eq);
1030 if (!eq->doorbell) {
1031 err = -ENOMEM;
1032 goto err_out_free_eq;
1033 }
1034
1035 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
1036 if (err)
1037 goto err_out_free_eq;
1038
1039 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
1040 if (err)
1041 goto err_out_free_mtt;
1042
225c7b1f
RD		 1043 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
1044 MLX4_EQ_STATE_ARMED);
1045 eq_context->log_eq_size = ilog2(eq->nent);
1046 eq_context->intr = intr;
1047 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
1048
1049 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
1050 eq_context->mtt_base_addr_h = mtt_addr >> 32;
1051 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
1052
1053 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
1054 if (err) {
1055 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
1056 goto err_out_free_mtt;
1057 }
1058
1059 kfree(dma_list);
1060 mlx4_free_cmd_mailbox(dev, mailbox);
1061
1062 eq->cons_index = 0;
1063
3dca0f42
MB		 1064 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
1065 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
1066 spin_lock_init(&eq->tasklet_ctx.lock);
1067 tasklet_init(&eq->tasklet_ctx.task, mlx4_cq_tasklet_cb,
1068 (unsigned long)&eq->tasklet_ctx);
1069
225c7b1f
RD		 1070 return err;
1071
1072err_out_free_mtt:
1073 mlx4_mtt_cleanup(dev, &eq->mtt);
1074
1075err_out_free_eq:
7c6d74d2 1076 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
225c7b1f
RD		 1077
1078err_out_free_pages:
1079 for (i = 0; i < npages; ++i)
1080 if (eq->page_list[i].buf)
872bf2fb 1081 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
225c7b1f
RD		 1082 eq->page_list[i].buf,
1083 eq->page_list[i].map);
1084
1085 mlx4_free_cmd_mailbox(dev, mailbox);
1086
1087err_out_free:
1088 kfree(eq->page_list);
1089 kfree(dma_list);
1090
1091err_out:
1092 return err;
1093}
1094
1095static void mlx4_free_eq(struct mlx4_dev *dev,
1096 struct mlx4_eq *eq)
1097{
1098 struct mlx4_priv *priv = mlx4_priv(dev);
225c7b1f 1099 int err;
225c7b1f 1100 int i;
43c816c6
IS		 1101 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with
1102 * strides of 64B,128B and 256B
1103 */
1104 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE;
225c7b1f 1105
30a5da5b 1106 err = mlx4_HW2SW_EQ(dev, eq->eqn);
225c7b1f
RD		 1107 if (err)
1108 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
1109
bf1bac5b 1110 synchronize_irq(eq->irq);
3dca0f42 1111 tasklet_disable(&eq->tasklet_ctx.task);
225c7b1f
RD		 1112
1113 mlx4_mtt_cleanup(dev, &eq->mtt);
1114 for (i = 0; i < npages; ++i)
872bf2fb
YH		 1115 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
1116 eq->page_list[i].buf,
1117 eq->page_list[i].map);
225c7b1f
RD		 1118
1119 kfree(eq->page_list);
7c6d74d2 1120 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR);
225c7b1f
RD		 1121}
1122
1123static void mlx4_free_irqs(struct mlx4_dev *dev)
1124{
1125 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
c66fa19c 1126 int i;
225c7b1f
RD		 1127
1128 if (eq_table->have_irq)
872bf2fb 1129 free_irq(dev->persist->pdev->irq, dev);
0b7ca5a9 1130
b8dd786f 1131 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
d1fdf24b 1132 if (eq_table->eq[i].have_irq) {
de161803
IS		 1133 free_cpumask_var(eq_table->eq[i].affinity_mask);
1134#if defined(CONFIG_SMP)
1135 irq_set_affinity_hint(eq_table->eq[i].irq, NULL);
1136#endif
225c7b1f 1137 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
d1fdf24b
RD		 1138 eq_table->eq[i].have_irq = 0;
1139 }
b8dd786f
YP		 1140
1141 kfree(eq_table->irq_names);
225c7b1f
RD		 1142}
1143
3d73c288 1144static int mlx4_map_clr_int(struct mlx4_dev *dev)
225c7b1f
RD		 1145{
1146 struct mlx4_priv *priv = mlx4_priv(dev);
1147
872bf2fb
YH		 1148 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev,
1149 priv->fw.clr_int_bar) +
225c7b1f
RD		 1150 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1151 if (!priv->clr_base) {
1a91de28 1152 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n");
225c7b1f
RD		 1153 return -ENOMEM;
1154 }
1155
1156 return 0;
1157}
1158
1159static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1160{
1161 struct mlx4_priv *priv = mlx4_priv(dev);
1162
1163 iounmap(priv->clr_base);
1164}
1165
b8dd786f
YP		 1166int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1167{
1168 struct mlx4_priv *priv = mlx4_priv(dev);
1169
1170 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1171 sizeof *priv->eq_table.eq, GFP_KERNEL);
1172 if (!priv->eq_table.eq)
1173 return -ENOMEM;
1174
1175 return 0;
1176}
1177
1178void mlx4_free_eq_table(struct mlx4_dev *dev)
1179{
1180 kfree(mlx4_priv(dev)->eq_table.eq);
1181}
1182
3d73c288 1183int mlx4_init_eq_table(struct mlx4_dev *dev)
225c7b1f
RD		 1184{
1185 struct mlx4_priv *priv = mlx4_priv(dev);
1186 int err;
1187 int i;
1188
758ff235
AL		 1189 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1190 sizeof *priv->eq_table.uar_map,
1191 GFP_KERNEL);
b8dd786f
YP		 1192 if (!priv->eq_table.uar_map) {
1193 err = -ENOMEM;
1194 goto err_out_free;
1195 }
1196
7ae0e400
MB		 1197 err = mlx4_bitmap_init(&priv->eq_table.bitmap,
1198 roundup_pow_of_two(dev->caps.num_eqs),
1199 dev->caps.num_eqs - 1,
1200 dev->caps.reserved_eqs,
1201 roundup_pow_of_two(dev->caps.num_eqs) -
1202 dev->caps.num_eqs);
225c7b1f 1203 if (err)
b8dd786f 1204 goto err_out_free;
225c7b1f 1205
b8dd786f 1206 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
225c7b1f
RD		 1207 priv->eq_table.uar_map[i] = NULL;
1208
acba2420
JM		 1209 if (!mlx4_is_slave(dev)) {
1210 err = mlx4_map_clr_int(dev);
1211 if (err)
1212 goto err_out_bitmap;
225c7b1f 1213
acba2420
JM		 1214 priv->eq_table.clr_mask =
1215 swab32(1 << (priv->eq_table.inta_pin & 31));
1216 priv->eq_table.clr_int = priv->clr_base +
1217 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1218 }
225c7b1f 1219
f5f5951c 1220 priv->eq_table.irq_names =
c66fa19c 1221 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1),
f5f5951c 1222 GFP_KERNEL);
b8dd786f
YP		 1223 if (!priv->eq_table.irq_names) {
1224 err = -ENOMEM;
c66fa19c 1225 goto err_out_clr_int;
b8dd786f
YP		 1226 }
1227
c66fa19c
MB		 1228 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1229 if (i == MLX4_EQ_ASYNC) {
1230 err = mlx4_create_eq(dev,
1231 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1232 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]);
1233 } else {
c66fa19c 1234 struct mlx4_eq *eq = &priv->eq_table.eq[i];
db9777e3 1235#ifdef CONFIG_RFS_ACCEL
c66fa19c
MB		 1236 int port = find_first_bit(eq->actv_ports.ports,
1237 dev->caps.num_ports) + 1;
1238
1239 if (port <= dev->caps.num_ports) {
1240 struct mlx4_port_info *info =
1241 &mlx4_priv(dev)->port[port];
1242
1243 if (!info->rmap) {
1244 info->rmap = alloc_irq_cpu_rmap(
1245 mlx4_get_eqs_per_port(dev, port));
1246 if (!info->rmap) {
1247 mlx4_warn(dev, "Failed to allocate cpu rmap\n");
1248 err = -ENOMEM;
1249 goto err_out_unmap;
1250 }
1251 }
0b7ca5a9 1252
c66fa19c
MB		 1253 err = irq_cpu_rmap_add(
1254 info->rmap, eq->irq);
1255 if (err)
1256 mlx4_warn(dev, "Failed adding irq rmap\n");
1257 }
1258#endif
1259 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1260 dev->caps.reserved_cqs +
1261 MLX4_NUM_SPARE_EQE,
1262 (dev->flags & MLX4_FLAG_MSI_X) ?
1263 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0,
1264 eq);
0b7ca5a9 1265 }
c66fa19c
MB		 1266 if (err)
1267 goto err_out_unmap;
0b7ca5a9
YP		 1268 }
1269
225c7b1f 1270 if (dev->flags & MLX4_FLAG_MSI_X) {
b8dd786f
YP		 1271 const char *eq_name;
1272
c66fa19c
MB		 1273 snprintf(priv->eq_table.irq_names +
1274 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE,
1275 MLX4_IRQNAME_SIZE,
1276 "mlx4-async@pci:%s",
1277 pci_name(dev->persist->pdev));
1278 eq_name = priv->eq_table.irq_names +
1279 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE;
225c7b1f 1280
c66fa19c
MB		 1281 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq,
1282 mlx4_msi_x_interrupt, 0, eq_name,
1283 priv->eq_table.eq + MLX4_EQ_ASYNC);
1284 if (err)
1285 goto err_out_unmap;
225c7b1f 1286
c66fa19c 1287 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1;
225c7b1f 1288 } else {
f5f5951c
AB		 1289 snprintf(priv->eq_table.irq_names,
1290 MLX4_IRQNAME_SIZE,
1291 DRV_NAME "@pci:%s",
872bf2fb
YH		 1292 pci_name(dev->persist->pdev));
1293 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt,
f5f5951c 1294 IRQF_SHARED, priv->eq_table.irq_names, dev);
225c7b1f 1295 if (err)
c66fa19c 1296 goto err_out_unmap;
225c7b1f
RD		 1297
1298 priv->eq_table.have_irq = 1;
1299 }
1300
00f5ce99 1301 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
c66fa19c 1302 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
225c7b1f
RD		 1303 if (err)
1304 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
c66fa19c 1305 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err);
225c7b1f 1306
c66fa19c
MB		 1307 /* arm ASYNC eq */
1308 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1);
225c7b1f 1309
225c7b1f
RD		 1310 return 0;
1311
225c7b1f 1312err_out_unmap:
2a292822
SO		 1313 while (i > 0)
1314 mlx4_free_eq(dev, &priv->eq_table.eq[--i]);
c66fa19c
MB		 1315#ifdef CONFIG_RFS_ACCEL
1316 for (i = 1; i <= dev->caps.num_ports; i++) {
1317 if (mlx4_priv(dev)->port[i].rmap) {
1318 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1319 mlx4_priv(dev)->port[i].rmap = NULL;
1320 }
b8dd786f 1321 }
c66fa19c
MB		 1322#endif
1323 mlx4_free_irqs(dev);
1324
1325err_out_clr_int:
acba2420
JM		 1326 if (!mlx4_is_slave(dev))
1327 mlx4_unmap_clr_int(dev);
225c7b1f 1328
b8dd786f 1329err_out_bitmap:
bfc0d8c3 1330 mlx4_unmap_uar(dev);
225c7b1f 1331 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f
YP		 1332
1333err_out_free:
1334 kfree(priv->eq_table.uar_map);
1335
225c7b1f
RD		 1336 return err;
1337}
1338
1339void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1340{
1341 struct mlx4_priv *priv = mlx4_priv(dev);
1342 int i;
1343
00f5ce99 1344 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
c66fa19c 1345 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
225c7b1f 1346
c66fa19c
MB		 1347#ifdef CONFIG_RFS_ACCEL
1348 for (i = 1; i <= dev->caps.num_ports; i++) {
1349 if (mlx4_priv(dev)->port[i].rmap) {
1350 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap);
1351 mlx4_priv(dev)->port[i].rmap = NULL;
1352 }
1353 }
1354#endif
225c7b1f
RD		 1355 mlx4_free_irqs(dev);
1356
c66fa19c 1357 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
225c7b1f 1358 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
225c7b1f 1359
acba2420
JM		 1360 if (!mlx4_is_slave(dev))
1361 mlx4_unmap_clr_int(dev);
225c7b1f 1362
bfc0d8c3 1363 mlx4_unmap_uar(dev);
225c7b1f 1364 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
b8dd786f
YP		 1365
1366 kfree(priv->eq_table.uar_map);
225c7b1f 1367}
e7c1c2c4 1368
6f2e0d2c
EE		 1369/* A test that verifies that we can accept interrupts
1370 * on the vector allocated for asynchronous events
1371 */
1372int mlx4_test_async(struct mlx4_dev *dev)
1373{
1374 return mlx4_NOP(dev);
1375}
1376EXPORT_SYMBOL(mlx4_test_async);
1377
1378/* A test that verifies that we can accept interrupts
1379 * on the given irq vector of the tested port.
e7c1c2c4
YP		 1380 * Interrupts are checked using the NOP command.
1381 */
6f2e0d2c 1382int mlx4_test_interrupt(struct mlx4_dev *dev, int vector)
e7c1c2c4
YP		 1383{
1384 struct mlx4_priv *priv = mlx4_priv(dev);
e7c1c2c4
YP		 1385 int err;
1386
6f2e0d2c
EE		 1387 /* Temporary use polling for command completions */
1388 mlx4_cmd_use_polling(dev);
e7c1c2c4 1389
6f2e0d2c
EE		 1390 /* Map the new eq to handle all asynchronous events */
1391 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1392 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn);
1393 if (err) {
1394 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1395 goto out;
e7c1c2c4
YP		 1396 }
1397
6f2e0d2c
EE		 1398 /* Go back to using events */
1399 mlx4_cmd_use_events(dev);
1400 err = mlx4_NOP(dev);
1401
e7c1c2c4 1402 /* Return to default */
6f2e0d2c
EE		 1403 mlx4_cmd_use_polling(dev);
1404out:
00f5ce99 1405 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
c66fa19c 1406 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn);
6f2e0d2c
EE		 1407 mlx4_cmd_use_events(dev);
1408
e7c1c2c4
YP		 1409 return err;
1410}
6f2e0d2c 1411EXPORT_SYMBOL(mlx4_test_interrupt);
0b7ca5a9 1412
c66fa19c 1413bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector)
0b7ca5a9 1414{
c66fa19c 1415 struct mlx4_priv *priv = mlx4_priv(dev);
0b7ca5a9 1416
c66fa19c
MB		 1417 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1418 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) ||
1419 (vector == MLX4_EQ_ASYNC))
1420 return false;
1421
1422 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports);
1423}
1424EXPORT_SYMBOL(mlx4_is_eq_vector_valid);
1425
1426u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port)
1427{
1428 struct mlx4_priv *priv = mlx4_priv(dev);
1429 unsigned int i;
1430 unsigned int sum = 0;
1431
1432 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++)
1433 sum += !!test_bit(port - 1,
1434 priv->eq_table.eq[i].actv_ports.ports);
1435
1436 return sum;
1437}
1438EXPORT_SYMBOL(mlx4_get_eqs_per_port);
1439
1440int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector)
1441{
1442 struct mlx4_priv *priv = mlx4_priv(dev);
1443
1444 vector = MLX4_CQ_TO_EQ_VECTOR(vector);
1445 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1))
1446 return -EINVAL;
1447
1448 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports,
1449 dev->caps.num_ports) > 1);
1450}
1451EXPORT_SYMBOL(mlx4_is_eq_shared);
1452
1453struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port)
1454{
1455 return mlx4_priv(dev)->port[port].rmap;
1456}
1457EXPORT_SYMBOL(mlx4_get_cpu_rmap);
1458
1459int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector)
1460{
0b7ca5a9 1461 struct mlx4_priv *priv = mlx4_priv(dev);
c66fa19c
MB		 1462 int err = 0, i = 0;
1463 u32 min_ref_count_val = (u32)-1;
1464 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector);
1465 int *prequested_vector = NULL;
1466
0b7ca5a9 1467
730c41d5 1468 mutex_lock(&priv->msix_ctl.pool_lock);
c66fa19c
MB		 1469 if (requested_vector < (dev->caps.num_comp_vectors + 1) &&
1470 (requested_vector >= 0) &&
1471 (requested_vector != MLX4_EQ_ASYNC)) {
1472 if (test_bit(port - 1,
1473 priv->eq_table.eq[requested_vector].actv_ports.ports)) {
1474 prequested_vector = &requested_vector;
1475 } else {
1476 struct mlx4_eq *eq;
1477
1478 for (i = 1; i < port;
1479 requested_vector += mlx4_get_eqs_per_port(dev, i++))
1480 ;
1481
1482 eq = &priv->eq_table.eq[requested_vector];
1483 if (requested_vector < dev->caps.num_comp_vectors + 1 &&
1484 test_bit(port - 1, eq->actv_ports.ports)) {
1485 prequested_vector = &requested_vector;
d9236c3f 1486 }
c66fa19c
MB		 1487 }
1488 }
1489
1490 if (!prequested_vector) {
1491 requested_vector = -1;
1492 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1;
1493 i++) {
1494 struct mlx4_eq *eq = &priv->eq_table.eq[i];
1495
1496 if (min_ref_count_val > eq->ref_count &&
1497 test_bit(port - 1, eq->actv_ports.ports)) {
1498 min_ref_count_val = eq->ref_count;
1499 requested_vector = i;
0b7ca5a9 1500 }
c66fa19c 1501 }
2eacc23c 1502
c66fa19c
MB		 1503 if (requested_vector < 0) {
1504 err = -ENOSPC;
1505 goto err_unlock;
0b7ca5a9 1506 }
c66fa19c
MB		 1507
1508 prequested_vector = &requested_vector;
0b7ca5a9 1509 }
c66fa19c
MB		 1510
1511 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) &&
1512 dev->flags & MLX4_FLAG_MSI_X) {
1513 set_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1514 snprintf(priv->eq_table.irq_names +
1515 *prequested_vector * MLX4_IRQNAME_SIZE,
1516 MLX4_IRQNAME_SIZE, "mlx4-%d@%s",
1517 *prequested_vector, dev_name(&dev->persist->pdev->dev));
1518
1519 err = request_irq(priv->eq_table.eq[*prequested_vector].irq,
1520 mlx4_msi_x_interrupt, 0,
1521 &priv->eq_table.irq_names[*prequested_vector << 5],
1522 priv->eq_table.eq + *prequested_vector);
1523
1524 if (err) {
1525 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm);
1526 *prequested_vector = -1;
1527 } else {
de161803
IS		 1528#if defined(CONFIG_SMP)
1529 mlx4_set_eq_affinity_hint(priv, *prequested_vector);
1530#endif
c66fa19c
MB		 1531 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1);
1532 priv->eq_table.eq[*prequested_vector].have_irq = 1;
1533 }
1534 }
1535
1536 if (!err && *prequested_vector >= 0)
1537 priv->eq_table.eq[*prequested_vector].ref_count++;
1538
1539err_unlock:
730c41d5 1540 mutex_unlock(&priv->msix_ctl.pool_lock);
0b7ca5a9 1541
c66fa19c
MB		 1542 if (!err && *prequested_vector >= 0)
1543 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector);
1544 else
0b7ca5a9 1545 *vector = 0;
c66fa19c 1546
0b7ca5a9
YP		 1547 return err;
1548}
1549EXPORT_SYMBOL(mlx4_assign_eq);
1550
c66fa19c 1551int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec)
35f6f453
AV		 1552{
1553 struct mlx4_priv *priv = mlx4_priv(dev);
1554
c66fa19c 1555 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq;
35f6f453
AV		 1556}
1557EXPORT_SYMBOL(mlx4_eq_get_irq);
1558
0b7ca5a9
YP		 1559void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1560{
1561 struct mlx4_priv *priv = mlx4_priv(dev);
c66fa19c
MB		 1562 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec);
1563
1564 mutex_lock(&priv->msix_ctl.pool_lock);
1565 priv->eq_table.eq[eq_vec].ref_count--;
0b7ca5a9 1566
c66fa19c
MB		 1567 /* once we allocated EQ, we don't release it because it might be binded
1568 * to cpu_rmap.
1569 */
1570 mutex_unlock(&priv->msix_ctl.pool_lock);
0b7ca5a9
YP		 1571}
1572EXPORT_SYMBOL(mlx4_release_eq);
1573
Linux 6.x block layer and io_uring tree(s)