Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
09067122 | 44 | #include <linux/ipv6.h> |
6eb07caf | 45 | #include <linux/moduleparam.h> |
c27a02cd YP |
46 | |
47 | #include "mlx4_en.h" | |
48 | ||
c27a02cd | 49 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 50 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 51 | u16 stride, int node, int queue_index) |
c27a02cd YP |
52 | { |
53 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 54 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
55 | int tmp; |
56 | int err; | |
57 | ||
163561a4 | 58 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 59 | if (!ring) { |
163561a4 EE |
60 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
61 | if (!ring) { | |
62 | en_err(priv, "Failed allocating TX ring\n"); | |
63 | return -ENOMEM; | |
64 | } | |
41d942d5 EE |
65 | } |
66 | ||
c27a02cd YP |
67 | ring->size = size; |
68 | ring->size_mask = size - 1; | |
e3f42f84 | 69 | ring->sp_stride = stride; |
488a9b48 | 70 | ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; |
c27a02cd | 71 | |
c27a02cd | 72 | tmp = size * sizeof(struct mlx4_en_tx_info); |
752ade68 | 73 | ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); |
41d942d5 | 74 | if (!ring->tx_info) { |
752ade68 MH |
75 | err = -ENOMEM; |
76 | goto err_ring; | |
41d942d5 | 77 | } |
e404decb | 78 | |
453a6082 | 79 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
80 | ring->tx_info, tmp); |
81 | ||
163561a4 | 82 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 83 | if (!ring->bounce_buf) { |
163561a4 EE |
84 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
85 | if (!ring->bounce_buf) { | |
86 | err = -ENOMEM; | |
87 | goto err_info; | |
88 | } | |
c27a02cd | 89 | } |
e3f42f84 | 90 | ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); |
c27a02cd | 91 | |
163561a4 | 92 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 93 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
e3f42f84 | 94 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
872bf2fb | 95 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 96 | if (err) { |
453a6082 | 97 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
98 | goto err_bounce; |
99 | } | |
100 | ||
e3f42f84 | 101 | ring->buf = ring->sp_wqres.buf.direct.buf; |
c27a02cd | 102 | |
1a91de28 JP |
103 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
104 | ring, ring->buf, ring->size, ring->buf_size, | |
e3f42f84 | 105 | (unsigned long long) ring->sp_wqres.buf.direct.map); |
c27a02cd | 106 | |
ddae0349 EE |
107 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
108 | MLX4_RESERVE_ETH_BF_QP); | |
109 | if (err) { | |
110 | en_err(priv, "failed reserving qp for TX ring\n"); | |
73898db0 | 111 | goto err_hwq_res; |
ddae0349 EE |
112 | } |
113 | ||
e3f42f84 | 114 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp, GFP_KERNEL); |
c27a02cd | 115 | if (err) { |
453a6082 | 116 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 117 | goto err_reserve; |
c27a02cd | 118 | } |
e3f42f84 | 119 | ring->sp_qp.event = mlx4_en_sqp_event; |
c27a02cd | 120 | |
163561a4 | 121 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 122 | if (err) { |
1a91de28 | 123 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
124 | ring->bf.uar = &mdev->priv_uar; |
125 | ring->bf.uar->map = mdev->uar_map; | |
126 | ring->bf_enabled = false; | |
0fef9d03 AV |
127 | ring->bf_alloced = false; |
128 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
129 | } else { | |
130 | ring->bf_alloced = true; | |
131 | ring->bf_enabled = !!(priv->pflags & | |
132 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
133 | } | |
87a5c389 | 134 | |
ec693d47 | 135 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
136 | ring->queue_index = queue_index; |
137 | ||
42eab005 | 138 | if (queue_index < priv->num_tx_rings_p_up) |
f36963c9 RR |
139 | cpumask_set_cpu(cpumask_local_spread(queue_index, |
140 | priv->mdev->dev->numa_node), | |
e3f42f84 | 141 | &ring->sp_affinity_mask); |
ec693d47 | 142 | |
41d942d5 | 143 | *pring = ring; |
c27a02cd YP |
144 | return 0; |
145 | ||
ddae0349 EE |
146 | err_reserve: |
147 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd | 148 | err_hwq_res: |
e3f42f84 | 149 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
150 | err_bounce: |
151 | kfree(ring->bounce_buf); | |
152 | ring->bounce_buf = NULL; | |
41d942d5 | 153 | err_info: |
dc9b06d1 | 154 | kvfree(ring->tx_info); |
c27a02cd | 155 | ring->tx_info = NULL; |
41d942d5 EE |
156 | err_ring: |
157 | kfree(ring); | |
158 | *pring = NULL; | |
c27a02cd YP |
159 | return err; |
160 | } | |
161 | ||
162 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 163 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
164 | { |
165 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 166 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 167 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 168 | |
0fef9d03 | 169 | if (ring->bf_alloced) |
87a5c389 | 170 | mlx4_bf_free(mdev->dev, &ring->bf); |
e3f42f84 ED |
171 | mlx4_qp_remove(mdev->dev, &ring->sp_qp); |
172 | mlx4_qp_free(mdev->dev, &ring->sp_qp); | |
0eb08514 | 173 | mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); |
e3f42f84 | 174 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
175 | kfree(ring->bounce_buf); |
176 | ring->bounce_buf = NULL; | |
dc9b06d1 | 177 | kvfree(ring->tx_info); |
c27a02cd | 178 | ring->tx_info = NULL; |
41d942d5 EE |
179 | kfree(ring); |
180 | *pring = NULL; | |
c27a02cd YP |
181 | } |
182 | ||
183 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
184 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 185 | int cq, int user_prio) |
c27a02cd YP |
186 | { |
187 | struct mlx4_en_dev *mdev = priv->mdev; | |
188 | int err; | |
189 | ||
e3f42f84 | 190 | ring->sp_cqn = cq; |
c27a02cd YP |
191 | ring->prod = 0; |
192 | ring->cons = 0xffffffff; | |
193 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
194 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
195 | memset(ring->buf, 0, ring->buf_size); | |
9ecc2d86 | 196 | ring->free_tx_desc = mlx4_en_free_tx_desc; |
c27a02cd | 197 | |
e3f42f84 ED |
198 | ring->sp_qp_state = MLX4_QP_STATE_RST; |
199 | ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); | |
6a4e8121 | 200 | ring->mr_key = cpu_to_be32(mdev->mr.key); |
c27a02cd | 201 | |
e3f42f84 ED |
202 | mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, |
203 | ring->sp_cqn, user_prio, &ring->sp_context); | |
0fef9d03 | 204 | if (ring->bf_alloced) |
e3f42f84 | 205 | ring->sp_context.usr_page = |
85743f1e HN |
206 | cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, |
207 | ring->bf.uar->index)); | |
c27a02cd | 208 | |
e3f42f84 ED |
209 | err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, |
210 | &ring->sp_qp, &ring->sp_qp_state); | |
211 | if (!cpumask_empty(&ring->sp_affinity_mask)) | |
212 | netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, | |
d03a68f8 | 213 | ring->queue_index); |
c27a02cd YP |
214 | |
215 | return err; | |
216 | } | |
217 | ||
218 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
219 | struct mlx4_en_tx_ring *ring) | |
220 | { | |
221 | struct mlx4_en_dev *mdev = priv->mdev; | |
222 | ||
e3f42f84 ED |
223 | mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, |
224 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); | |
c27a02cd YP |
225 | } |
226 | ||
488a9b48 IS |
227 | static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) |
228 | { | |
229 | return ring->prod - ring->cons > ring->full_size; | |
230 | } | |
231 | ||
2d4b6466 EE |
232 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
233 | struct mlx4_en_tx_ring *ring, int index, | |
234 | u8 owner) | |
235 | { | |
236 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
237 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
238 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
239 | void *end = ring->buf + ring->buf_size; | |
240 | __be32 *ptr = (__be32 *)tx_desc; | |
241 | int i; | |
242 | ||
243 | /* Optimize the common case when there are no wraparounds */ | |
244 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
245 | /* Stamp the freed descriptor */ | |
246 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
247 | i += STAMP_STRIDE) { | |
248 | *ptr = stamp; | |
249 | ptr += STAMP_DWORDS; | |
250 | } | |
251 | } else { | |
252 | /* Stamp the freed descriptor */ | |
253 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
254 | i += STAMP_STRIDE) { | |
255 | *ptr = stamp; | |
256 | ptr += STAMP_DWORDS; | |
257 | if ((void *)ptr >= end) { | |
258 | ptr = ring->buf; | |
259 | stamp ^= cpu_to_be32(0x80000000); | |
260 | } | |
261 | } | |
262 | } | |
263 | } | |
264 | ||
c27a02cd | 265 | |
9ecc2d86 BB |
266 | u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
267 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 268 | int index, u64 timestamp, |
9ecc2d86 | 269 | int napi_mode) |
c27a02cd | 270 | { |
c27a02cd YP |
271 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
272 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
273 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
c27a02cd | 274 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
275 | struct sk_buff *skb = tx_info->skb; |
276 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 277 | int i; |
ec693d47 | 278 | |
29d40c90 ED |
279 | /* We do not touch skb here, so prefetch skb->users location |
280 | * to speedup consume_skb() | |
281 | */ | |
282 | prefetchw(&skb->users); | |
283 | ||
3d03641c ED |
284 | if (unlikely(timestamp)) { |
285 | struct skb_shared_hwtstamps hwts; | |
286 | ||
287 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
288 | skb_tstamp_tx(skb, &hwts); |
289 | } | |
c27a02cd YP |
290 | |
291 | /* Optimize the common case when there are no wraparounds */ | |
292 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a | 293 | if (!tx_info->inl) { |
3d03641c | 294 | if (tx_info->linear) |
ebf8c9aa | 295 | dma_unmap_single(priv->ddev, |
3d03641c ED |
296 | tx_info->map0_dma, |
297 | tx_info->map0_byte_count, | |
298 | PCI_DMA_TODEVICE); | |
299 | else | |
300 | dma_unmap_page(priv->ddev, | |
301 | tx_info->map0_dma, | |
302 | tx_info->map0_byte_count, | |
303 | PCI_DMA_TODEVICE); | |
304 | for (i = 1; i < nr_maps; i++) { | |
305 | data++; | |
ebf8c9aa | 306 | dma_unmap_page(priv->ddev, |
3d03641c ED |
307 | (dma_addr_t)be64_to_cpu(data->addr), |
308 | be32_to_cpu(data->byte_count), | |
309 | PCI_DMA_TODEVICE); | |
41efea5a | 310 | } |
c27a02cd | 311 | } |
c27a02cd | 312 | } else { |
41efea5a YP |
313 | if (!tx_info->inl) { |
314 | if ((void *) data >= end) { | |
43d620c8 | 315 | data = ring->buf + ((void *)data - end); |
41efea5a | 316 | } |
c27a02cd | 317 | |
3d03641c | 318 | if (tx_info->linear) |
ebf8c9aa | 319 | dma_unmap_single(priv->ddev, |
3d03641c ED |
320 | tx_info->map0_dma, |
321 | tx_info->map0_byte_count, | |
322 | PCI_DMA_TODEVICE); | |
323 | else | |
324 | dma_unmap_page(priv->ddev, | |
325 | tx_info->map0_dma, | |
326 | tx_info->map0_byte_count, | |
327 | PCI_DMA_TODEVICE); | |
328 | for (i = 1; i < nr_maps; i++) { | |
329 | data++; | |
41efea5a YP |
330 | /* Check for wraparound before unmapping */ |
331 | if ((void *) data >= end) | |
43d620c8 | 332 | data = ring->buf; |
ebf8c9aa | 333 | dma_unmap_page(priv->ddev, |
3d03641c ED |
334 | (dma_addr_t)be64_to_cpu(data->addr), |
335 | be32_to_cpu(data->byte_count), | |
336 | PCI_DMA_TODEVICE); | |
41efea5a | 337 | } |
c27a02cd | 338 | } |
c27a02cd | 339 | } |
b4a53379 JDB |
340 | napi_consume_skb(skb, napi_mode); |
341 | ||
c27a02cd YP |
342 | return tx_info->nr_txbb; |
343 | } | |
344 | ||
9ecc2d86 BB |
345 | u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
346 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 347 | int index, u64 timestamp, |
9ecc2d86 BB |
348 | int napi_mode) |
349 | { | |
350 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
351 | struct mlx4_en_rx_alloc frame = { | |
352 | .page = tx_info->page, | |
353 | .dma = tx_info->map0_dma, | |
9ecc2d86 BB |
354 | }; |
355 | ||
356 | if (!mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { | |
357 | dma_unmap_page(priv->ddev, tx_info->map0_dma, | |
69ba9431 | 358 | PAGE_SIZE, priv->dma_dir); |
9ecc2d86 BB |
359 | put_page(tx_info->page); |
360 | } | |
361 | ||
362 | return tx_info->nr_txbb; | |
363 | } | |
c27a02cd YP |
364 | |
365 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
366 | { | |
367 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
368 | int cnt = 0; | |
369 | ||
370 | /* Skip last polled descriptor */ | |
371 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 372 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
373 | ring->cons, ring->prod); |
374 | ||
375 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
376 | if (netif_msg_tx_err(priv)) | |
453a6082 | 377 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
378 | return 0; |
379 | } | |
380 | ||
381 | while (ring->cons != ring->prod) { | |
9ecc2d86 | 382 | ring->last_nr_txbb = ring->free_tx_desc(priv, ring, |
c27a02cd | 383 | ring->cons & ring->size_mask, |
cf97050d | 384 | 0, 0 /* Non-NAPI caller */); |
c27a02cd YP |
385 | ring->cons += ring->last_nr_txbb; |
386 | cnt++; | |
387 | } | |
388 | ||
67f8b1dc TT |
389 | if (ring->tx_queue) |
390 | netdev_tx_reset_queue(ring->tx_queue); | |
41b74920 | 391 | |
c27a02cd | 392 | if (cnt) |
453a6082 | 393 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
394 | |
395 | return cnt; | |
396 | } | |
397 | ||
fbc6daf1 | 398 | static bool mlx4_en_process_tx_cq(struct net_device *dev, |
b4a53379 | 399 | struct mlx4_en_cq *cq, int napi_budget) |
c27a02cd YP |
400 | { |
401 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
402 | struct mlx4_cq *mcq = &cq->mcq; | |
67f8b1dc | 403 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; |
f0ab34f0 | 404 | struct mlx4_cqe *cqe; |
cc26a490 | 405 | u16 index, ring_index, stamp_index; |
c27a02cd | 406 | u32 txbbs_skipped = 0; |
2d4b6466 | 407 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
408 | u32 cons_index = mcq->cons_index; |
409 | int size = cq->size; | |
410 | u32 size_mask = ring->size_mask; | |
411 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
412 | u32 packets = 0; |
413 | u32 bytes = 0; | |
08ff3235 | 414 | int factor = priv->cqe_factor; |
0276a330 | 415 | int done = 0; |
fbc6daf1 | 416 | int budget = priv->tx_work_limit; |
fb1843ee ED |
417 | u32 last_nr_txbb; |
418 | u32 ring_cons; | |
c27a02cd | 419 | |
cc26a490 | 420 | if (unlikely(!priv->port_up)) |
fbc6daf1 | 421 | return true; |
c27a02cd | 422 | |
53511453 ED |
423 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
424 | ||
f0ab34f0 | 425 | index = cons_index & size_mask; |
b1b6b4da | 426 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
fb1843ee ED |
427 | last_nr_txbb = ACCESS_ONCE(ring->last_nr_txbb); |
428 | ring_cons = ACCESS_ONCE(ring->cons); | |
429 | ring_index = ring_cons & size_mask; | |
2d4b6466 | 430 | stamp_index = ring_index; |
f0ab34f0 YP |
431 | |
432 | /* Process all completed CQEs */ | |
433 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 434 | cons_index & size) && (done < budget)) { |
cc26a490 TT |
435 | u16 new_index; |
436 | ||
f0ab34f0 YP |
437 | /* |
438 | * make sure we read the CQE after we read the | |
439 | * ownership bit | |
440 | */ | |
12b3375f | 441 | dma_rmb(); |
f0ab34f0 | 442 | |
bd2f631d AV |
443 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
444 | MLX4_CQE_OPCODE_ERROR)) { | |
445 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
446 | ||
447 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
448 | cqe_err->vendor_err_syndrome, | |
449 | cqe_err->syndrome); | |
450 | } | |
451 | ||
f0ab34f0 YP |
452 | /* Skip over last polled CQE */ |
453 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
454 | ||
c27a02cd | 455 | do { |
fc96256c ED |
456 | u64 timestamp = 0; |
457 | ||
fb1843ee ED |
458 | txbbs_skipped += last_nr_txbb; |
459 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
fc96256c ED |
460 | |
461 | if (unlikely(ring->tx_info[ring_index].ts_requested)) | |
ec693d47 AV |
462 | timestamp = mlx4_en_get_cqe_ts(cqe); |
463 | ||
f0ab34f0 | 464 | /* free next descriptor */ |
9ecc2d86 | 465 | last_nr_txbb = ring->free_tx_desc( |
f0ab34f0 | 466 | priv, ring, ring_index, |
cf97050d | 467 | timestamp, napi_budget); |
2d4b6466 EE |
468 | |
469 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 470 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
471 | ring->size)); |
472 | stamp_index = ring_index; | |
473 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
474 | packets++; |
475 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 476 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
477 | |
478 | ++cons_index; | |
479 | index = cons_index & size_mask; | |
b1b6b4da | 480 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 481 | } |
c27a02cd | 482 | |
c27a02cd YP |
483 | /* |
484 | * To prevent CQ overflow we first update CQ consumer and only then | |
485 | * the ring consumer. | |
486 | */ | |
f0ab34f0 | 487 | mcq->cons_index = cons_index; |
c27a02cd YP |
488 | mlx4_cq_set_ci(mcq); |
489 | wmb(); | |
fb1843ee ED |
490 | |
491 | /* we want to dirty this cache line once */ | |
492 | ACCESS_ONCE(ring->last_nr_txbb) = last_nr_txbb; | |
493 | ACCESS_ONCE(ring->cons) = ring_cons + txbbs_skipped; | |
494 | ||
cc26a490 | 495 | if (cq->type == TX_XDP) |
9ecc2d86 BB |
496 | return done < budget; |
497 | ||
5b263f53 | 498 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 499 | |
488a9b48 | 500 | /* Wakeup Tx queue if this stopped, and ring is not full. |
c18520bd | 501 | */ |
488a9b48 IS |
502 | if (netif_tx_queue_stopped(ring->tx_queue) && |
503 | !mlx4_en_is_tx_ring_full(ring)) { | |
c18520bd | 504 | netif_tx_wake_queue(ring->tx_queue); |
15bffdff | 505 | ring->wake_queue++; |
c27a02cd | 506 | } |
cc26a490 | 507 | |
fbc6daf1 | 508 | return done < budget; |
c27a02cd YP |
509 | } |
510 | ||
511 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
512 | { | |
513 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
514 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 515 | |
477b35b4 ED |
516 | if (likely(priv->port_up)) |
517 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
518 | else |
519 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
520 | } |
521 | ||
0276a330 EE |
522 | /* TX CQ polling - called by NAPI */ |
523 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
524 | { | |
525 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
526 | struct net_device *dev = cq->dev; | |
527 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
cc26a490 | 528 | bool clean_complete; |
0276a330 | 529 | |
b4a53379 | 530 | clean_complete = mlx4_en_process_tx_cq(dev, cq, budget); |
fbc6daf1 AV |
531 | if (!clean_complete) |
532 | return budget; | |
0276a330 | 533 | |
fbc6daf1 AV |
534 | napi_complete(napi); |
535 | mlx4_en_arm_cq(priv, cq); | |
536 | ||
537 | return 0; | |
0276a330 | 538 | } |
c27a02cd | 539 | |
c27a02cd YP |
540 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
541 | struct mlx4_en_tx_ring *ring, | |
542 | u32 index, | |
543 | unsigned int desc_size) | |
544 | { | |
545 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
546 | int i; | |
547 | ||
548 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
549 | if ((i & (TXBB_SIZE - 1)) == 0) | |
550 | wmb(); | |
551 | ||
552 | *((u32 *) (ring->buf + i)) = | |
553 | *((u32 *) (ring->bounce_buf + copy + i)); | |
554 | } | |
555 | ||
556 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
557 | if ((i & (TXBB_SIZE - 1)) == 0) | |
558 | wmb(); | |
559 | ||
560 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
561 | *((u32 *) (ring->bounce_buf + i)); | |
562 | } | |
563 | ||
564 | /* Return real descriptor location */ | |
565 | return ring->buf + index * TXBB_SIZE; | |
566 | } | |
567 | ||
acea73d6 ED |
568 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
569 | * | |
570 | * It seems strange we do not simply use skb_copy_bits(). | |
571 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
572 | * | |
573 | * Note that caller already checked skb was not a gso packet | |
574 | */ | |
7dfa4b41 | 575 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 576 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 577 | void **pfrag) |
c27a02cd YP |
578 | { |
579 | void *ptr; | |
580 | ||
acea73d6 ED |
581 | if (skb->len > inline_thold || !inline_thold) |
582 | return false; | |
c27a02cd | 583 | |
acea73d6 ED |
584 | if (shinfo->nr_frags == 1) { |
585 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
586 | if (unlikely(!ptr)) | |
587 | return false; | |
588 | *pfrag = ptr; | |
589 | return true; | |
c27a02cd | 590 | } |
acea73d6 ED |
591 | if (shinfo->nr_frags) |
592 | return false; | |
593 | return true; | |
c27a02cd YP |
594 | } |
595 | ||
7dfa4b41 | 596 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
597 | { |
598 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
599 | <= MLX4_INLINE_ALIGN) | |
600 | return ALIGN(skb->len + CTRL_SIZE + | |
601 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
602 | else | |
603 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
604 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
605 | } | |
606 | ||
7dfa4b41 | 607 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 608 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 609 | struct net_device *dev, |
acea73d6 ED |
610 | int *lso_header_size, |
611 | bool *inline_ok, | |
612 | void **pfrag) | |
c27a02cd YP |
613 | { |
614 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
615 | int real_size; |
616 | ||
b9d8839a | 617 | if (shinfo->gso_size) { |
acea73d6 | 618 | *inline_ok = false; |
837052d0 OG |
619 | if (skb->encapsulation) |
620 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
621 | else | |
622 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
b9d8839a | 623 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
c27a02cd YP |
624 | ALIGN(*lso_header_size + 4, DS_SIZE); |
625 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
626 | /* We add a segment for the skb linear buffer only if | |
627 | * it contains data */ | |
628 | if (*lso_header_size < skb_headlen(skb)) | |
629 | real_size += DS_SIZE; | |
630 | else { | |
631 | if (netif_msg_tx_err(priv)) | |
453a6082 | 632 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
633 | return 0; |
634 | } | |
635 | } | |
c27a02cd YP |
636 | } else { |
637 | *lso_header_size = 0; | |
acea73d6 ED |
638 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
639 | shinfo, pfrag); | |
640 | ||
641 | if (*inline_ok) | |
c27a02cd | 642 | real_size = inline_size(skb); |
acea73d6 ED |
643 | else |
644 | real_size = CTRL_SIZE + | |
645 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
646 | } |
647 | ||
648 | return real_size; | |
649 | } | |
650 | ||
7dfa4b41 ED |
651 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
652 | const struct sk_buff *skb, | |
b9d8839a | 653 | const struct skb_shared_info *shinfo, |
224e92e0 | 654 | void *fragptr) |
c27a02cd YP |
655 | { |
656 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
657 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
e533ac7e | 658 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
659 | |
660 | if (skb->len <= spc) { | |
93591aaa EE |
661 | if (likely(skb->len >= MIN_PKT_LEN)) { |
662 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
663 | } else { | |
664 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
665 | memset(((void *)(inl + 1)) + skb->len, 0, | |
666 | MIN_PKT_LEN - skb->len); | |
667 | } | |
e533ac7e | 668 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
b9d8839a | 669 | if (shinfo->nr_frags) |
e533ac7e | 670 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
b9d8839a | 671 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
672 | |
673 | } else { | |
674 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e ED |
675 | if (hlen <= spc) { |
676 | skb_copy_from_linear_data(skb, inl + 1, hlen); | |
677 | if (hlen < spc) { | |
678 | memcpy(((void *)(inl + 1)) + hlen, | |
679 | fragptr, spc - hlen); | |
680 | fragptr += spc - hlen; | |
c27a02cd YP |
681 | } |
682 | inl = (void *) (inl + 1) + spc; | |
683 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
684 | } else { | |
685 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
686 | inl = (void *) (inl + 1) + spc; | |
687 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
e533ac7e | 688 | hlen - spc); |
b9d8839a | 689 | if (shinfo->nr_frags) |
e533ac7e | 690 | memcpy(((void *)(inl + 1)) + hlen - spc, |
b9d8839a ED |
691 | fragptr, |
692 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
693 | } |
694 | ||
12b3375f | 695 | dma_wmb(); |
c27a02cd YP |
696 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
697 | } | |
c27a02cd YP |
698 | } |
699 | ||
f663dd9a | 700 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 701 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 702 | { |
bc6a4744 | 703 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 704 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 705 | u8 up = 0; |
c27a02cd | 706 | |
4b5e5b7e | 707 | if (netdev_get_num_tc(dev)) |
bc6a4744 AV |
708 | return skb_tx_hash(dev, skb); |
709 | ||
df8a39de JP |
710 | if (skb_vlan_tag_present(skb)) |
711 | up = skb_vlan_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 712 | |
99932d4f | 713 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
714 | } |
715 | ||
7dfa4b41 ED |
716 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
717 | unsigned int bytecnt) | |
87a5c389 YP |
718 | { |
719 | __iowrite64_copy(dst, src, bytecnt / 8); | |
720 | } | |
721 | ||
224e92e0 BB |
722 | void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) |
723 | { | |
724 | wmb(); | |
725 | /* Since there is no iowrite*_native() that writes the | |
726 | * value as is, without byteswapping - using the one | |
727 | * the doesn't do byteswapping in the relevant arch | |
728 | * endianness. | |
729 | */ | |
730 | #if defined(__LITTLE_ENDIAN) | |
731 | iowrite32( | |
732 | #else | |
733 | iowrite32be( | |
734 | #endif | |
735 | ring->doorbell_qpn, | |
736 | ring->bf.uar->map + MLX4_SEND_DOORBELL); | |
737 | } | |
738 | ||
739 | static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, | |
740 | struct mlx4_en_tx_desc *tx_desc, | |
741 | union mlx4_wqe_qpn_vlan qpn_vlan, | |
742 | int desc_size, int bf_index, | |
743 | __be32 op_own, bool bf_ok, | |
744 | bool send_doorbell) | |
745 | { | |
746 | tx_desc->ctrl.qpn_vlan = qpn_vlan; | |
747 | ||
748 | if (bf_ok) { | |
749 | op_own |= htonl((bf_index & 0xffff) << 8); | |
750 | /* Ensure new descriptor hits memory | |
751 | * before setting ownership of this descriptor to HW | |
752 | */ | |
753 | dma_wmb(); | |
754 | tx_desc->ctrl.owner_opcode = op_own; | |
755 | ||
756 | wmb(); | |
757 | ||
758 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, | |
759 | desc_size); | |
760 | ||
761 | wmb(); | |
762 | ||
763 | ring->bf.offset ^= ring->bf.buf_size; | |
764 | } else { | |
765 | /* Ensure new descriptor hits memory | |
766 | * before setting ownership of this descriptor to HW | |
767 | */ | |
768 | dma_wmb(); | |
769 | tx_desc->ctrl.owner_opcode = op_own; | |
770 | if (send_doorbell) | |
771 | mlx4_en_xmit_doorbell(ring); | |
772 | else | |
773 | ring->xmit_more++; | |
774 | } | |
775 | } | |
776 | ||
61357325 | 777 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 778 | { |
b9d8839a | 779 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 780 | struct mlx4_en_priv *priv = netdev_priv(dev); |
224e92e0 | 781 | union mlx4_wqe_qpn_vlan qpn_vlan = {}; |
237a3a3b | 782 | struct device *ddev = priv->ddev; |
c27a02cd | 783 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
784 | struct mlx4_en_tx_desc *tx_desc; |
785 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
786 | struct mlx4_en_tx_info *tx_info; |
787 | int tx_ind = 0; | |
788 | int nr_txbb; | |
789 | int desc_size; | |
790 | int real_size; | |
87a5c389 | 791 | u32 index, bf_index; |
c27a02cd | 792 | __be32 op_own; |
e38af4fa | 793 | u16 vlan_proto = 0; |
b9d8839a | 794 | int i_frag; |
c27a02cd | 795 | int lso_header_size; |
acea73d6 | 796 | void *fragptr = NULL; |
87a5c389 | 797 | bool bounce = false; |
5804283d | 798 | bool send_doorbell; |
fe971b95 | 799 | bool stop_queue; |
acea73d6 | 800 | bool inline_ok; |
f905c79e | 801 | u32 ring_cons; |
224e92e0 | 802 | bool bf_ok; |
c27a02cd | 803 | |
f905c79e | 804 | tx_ind = skb_get_queue_mapping(skb); |
67f8b1dc | 805 | ring = priv->tx_ring[TX][tx_ind]; |
f905c79e | 806 | |
63a664b7 ED |
807 | if (!priv->port_up) |
808 | goto tx_drop; | |
809 | ||
f905c79e ED |
810 | /* fetch ring->cons far ahead before needing it to avoid stall */ |
811 | ring_cons = ACCESS_ONCE(ring->cons); | |
812 | ||
acea73d6 ED |
813 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
814 | &inline_ok, &fragptr); | |
c27a02cd | 815 | if (unlikely(!real_size)) |
7a61fc86 | 816 | goto tx_drop_count; |
c27a02cd | 817 | |
25985edc | 818 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
819 | desc_size = ALIGN(real_size, TXBB_SIZE); |
820 | nr_txbb = desc_size / TXBB_SIZE; | |
821 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
822 | if (netif_msg_tx_err(priv)) | |
453a6082 | 823 | en_warn(priv, "Oversized header or SG list\n"); |
7a61fc86 | 824 | goto tx_drop_count; |
c27a02cd YP |
825 | } |
826 | ||
224e92e0 | 827 | bf_ok = ring->bf_enabled; |
e38af4fa | 828 | if (skb_vlan_tag_present(skb)) { |
224e92e0 | 829 | qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); |
e38af4fa | 830 | vlan_proto = be16_to_cpu(skb->vlan_proto); |
224e92e0 BB |
831 | if (vlan_proto == ETH_P_8021AD) |
832 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; | |
833 | else if (vlan_proto == ETH_P_8021Q) | |
834 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; | |
835 | else | |
836 | qpn_vlan.ins_vlan = 0; | |
837 | bf_ok = false; | |
e38af4fa | 838 | } |
c27a02cd | 839 | |
53511453 | 840 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 841 | |
c27a02cd YP |
842 | /* Track current inflight packets for performance analysis */ |
843 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
f905c79e | 844 | (u32)(ring->prod - ring_cons - 1)); |
c27a02cd YP |
845 | |
846 | /* Packet is good - grab an index and transmit it */ | |
847 | index = ring->prod & ring->size_mask; | |
87a5c389 | 848 | bf_index = ring->prod; |
c27a02cd YP |
849 | |
850 | /* See if we have enough space for whole descriptor TXBB for setting | |
851 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
852 | if (likely(index + nr_txbb <= ring->size)) | |
853 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 854 | else { |
c27a02cd | 855 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 | 856 | bounce = true; |
224e92e0 | 857 | bf_ok = false; |
87a5c389 | 858 | } |
c27a02cd YP |
859 | |
860 | /* Save skb in tx_info ring */ | |
861 | tx_info = &ring->tx_info[index]; | |
862 | tx_info->skb = skb; | |
863 | tx_info->nr_txbb = nr_txbb; | |
864 | ||
7dfa4b41 | 865 | data = &tx_desc->data; |
237a3a3b AV |
866 | if (lso_header_size) |
867 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
868 | DS_SIZE)); | |
237a3a3b AV |
869 | |
870 | /* valid only for none inline segments */ | |
871 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
872 | ||
acea73d6 ED |
873 | tx_info->inl = inline_ok; |
874 | ||
237a3a3b | 875 | tx_info->linear = (lso_header_size < skb_headlen(skb) && |
acea73d6 | 876 | !inline_ok) ? 1 : 0; |
237a3a3b | 877 | |
b9d8839a | 878 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 879 | data += tx_info->nr_maps - 1; |
237a3a3b | 880 | |
acea73d6 | 881 | if (!tx_info->inl) { |
3d03641c ED |
882 | dma_addr_t dma = 0; |
883 | u32 byte_count = 0; | |
884 | ||
7dfa4b41 | 885 | /* Map fragments if any */ |
b9d8839a | 886 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { |
7dfa4b41 | 887 | const struct skb_frag_struct *frag; |
b9d8839a ED |
888 | |
889 | frag = &shinfo->frags[i_frag]; | |
3d03641c | 890 | byte_count = skb_frag_size(frag); |
237a3a3b | 891 | dma = skb_frag_dma_map(ddev, frag, |
3d03641c | 892 | 0, byte_count, |
237a3a3b AV |
893 | DMA_TO_DEVICE); |
894 | if (dma_mapping_error(ddev, dma)) | |
895 | goto tx_drop_unmap; | |
896 | ||
897 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 898 | data->lkey = ring->mr_key; |
12b3375f | 899 | dma_wmb(); |
3d03641c | 900 | data->byte_count = cpu_to_be32(byte_count); |
237a3a3b AV |
901 | --data; |
902 | } | |
903 | ||
7dfa4b41 | 904 | /* Map linear part if needed */ |
237a3a3b | 905 | if (tx_info->linear) { |
3d03641c | 906 | byte_count = skb_headlen(skb) - lso_header_size; |
5f1cd200 | 907 | |
237a3a3b AV |
908 | dma = dma_map_single(ddev, skb->data + |
909 | lso_header_size, byte_count, | |
910 | PCI_DMA_TODEVICE); | |
911 | if (dma_mapping_error(ddev, dma)) | |
912 | goto tx_drop_unmap; | |
913 | ||
914 | data->addr = cpu_to_be64(dma); | |
6a4e8121 | 915 | data->lkey = ring->mr_key; |
12b3375f | 916 | dma_wmb(); |
237a3a3b AV |
917 | data->byte_count = cpu_to_be32(byte_count); |
918 | } | |
3d03641c ED |
919 | /* tx completion can avoid cache line miss for common cases */ |
920 | tx_info->map0_dma = dma; | |
921 | tx_info->map0_byte_count = byte_count; | |
237a3a3b AV |
922 | } |
923 | ||
ec693d47 AV |
924 | /* |
925 | * For timestamping add flag to skb_shinfo and | |
926 | * set flag for further reference | |
927 | */ | |
e70602a8 | 928 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
929 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
930 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
931 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
932 | tx_info->ts_requested = 1; |
933 | } | |
934 | ||
c27a02cd YP |
935 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
936 | * whether LSO is used */ | |
60d6fe99 | 937 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 938 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
939 | if (!skb->encapsulation) |
940 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
941 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
942 | else | |
943 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 944 | ring->tx_csum++; |
c27a02cd YP |
945 | } |
946 | ||
79aeaccd | 947 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
948 | struct ethhdr *ethh; |
949 | ||
213815a1 YB |
950 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
951 | * so that VFs and PF can communicate with each other | |
952 | */ | |
953 | ethh = (struct ethhdr *)skb->data; | |
954 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
955 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
956 | } | |
957 | ||
c27a02cd YP |
958 | /* Handle LSO (TSO) packets */ |
959 | if (lso_header_size) { | |
b9d8839a ED |
960 | int i; |
961 | ||
c27a02cd YP |
962 | /* Mark opcode as LSO */ |
963 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
964 | ((ring->prod & ring->size) ? | |
965 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
966 | ||
967 | /* Fill in the LSO prefix */ | |
968 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 969 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd YP |
970 | |
971 | /* Copy headers; | |
972 | * note that we already verified that it is linear */ | |
973 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd | 974 | |
9fab426d | 975 | ring->tso_packets++; |
b9d8839a | 976 | |
75d04aa3 | 977 | i = shinfo->gso_segs; |
5b263f53 | 978 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
979 | ring->packets += i; |
980 | } else { | |
981 | /* Normal (Non LSO) packet */ | |
982 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
983 | ((ring->prod & ring->size) ? | |
984 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 985 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 986 | ring->packets++; |
c27a02cd | 987 | } |
5b263f53 YP |
988 | ring->bytes += tx_info->nr_bytes; |
989 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
990 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
991 | ||
acea73d6 | 992 | if (tx_info->inl) |
224e92e0 | 993 | build_inline_wqe(tx_desc, skb, shinfo, fragptr); |
c27a02cd | 994 | |
837052d0 | 995 | if (skb->encapsulation) { |
09067122 AD |
996 | union { |
997 | struct iphdr *v4; | |
998 | struct ipv6hdr *v6; | |
999 | unsigned char *hdr; | |
1000 | } ip; | |
1001 | u8 proto; | |
1002 | ||
1003 | ip.hdr = skb_inner_network_header(skb); | |
1004 | proto = (ip.v4->version == 4) ? ip.v4->protocol : | |
1005 | ip.v6->nexthdr; | |
1006 | ||
1007 | if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) | |
837052d0 OG |
1008 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); |
1009 | else | |
1010 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
1011 | } | |
1012 | ||
c27a02cd YP |
1013 | ring->prod += nr_txbb; |
1014 | ||
1015 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 1016 | if (unlikely(bounce)) |
c27a02cd YP |
1017 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
1018 | ||
eb0cabbd AV |
1019 | skb_tx_timestamp(skb); |
1020 | ||
fe971b95 | 1021 | /* Check available TXBBs And 2K spare for prefetch */ |
488a9b48 | 1022 | stop_queue = mlx4_en_is_tx_ring_full(ring); |
fe971b95 ED |
1023 | if (unlikely(stop_queue)) { |
1024 | netif_tx_stop_queue(ring->tx_queue); | |
1025 | ring->queue_stopped++; | |
1026 | } | |
5804283d ED |
1027 | send_doorbell = !skb->xmit_more || netif_xmit_stopped(ring->tx_queue); |
1028 | ||
6a4e8121 ED |
1029 | real_size = (real_size / 16) & 0x3f; |
1030 | ||
224e92e0 | 1031 | bf_ok &= desc_size <= MAX_BF && send_doorbell; |
e38af4fa | 1032 | |
224e92e0 BB |
1033 | if (bf_ok) |
1034 | qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); | |
1035 | else | |
1036 | qpn_vlan.fence_size = real_size; | |
7dfa4b41 | 1037 | |
224e92e0 BB |
1038 | mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, |
1039 | op_own, bf_ok, send_doorbell); | |
c27a02cd | 1040 | |
fe971b95 ED |
1041 | if (unlikely(stop_queue)) { |
1042 | /* If queue was emptied after the if (stop_queue) , and before | |
1043 | * the netif_tx_stop_queue() - need to wake the queue, | |
1044 | * or else it will remain stopped forever. | |
1045 | * Need a memory barrier to make sure ring->cons was not | |
1046 | * updated before queue was stopped. | |
1047 | */ | |
1048 | smp_rmb(); | |
1049 | ||
1050 | ring_cons = ACCESS_ONCE(ring->cons); | |
488a9b48 | 1051 | if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { |
fe971b95 ED |
1052 | netif_tx_wake_queue(ring->tx_queue); |
1053 | ring->wake_queue++; | |
1054 | } | |
1055 | } | |
ec634fe3 | 1056 | return NETDEV_TX_OK; |
7e230913 | 1057 | |
237a3a3b AV |
1058 | tx_drop_unmap: |
1059 | en_err(priv, "DMA mapping error\n"); | |
1060 | ||
b9d8839a ED |
1061 | while (++i_frag < shinfo->nr_frags) { |
1062 | ++data; | |
237a3a3b AV |
1063 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), |
1064 | be32_to_cpu(data->byte_count), | |
1065 | PCI_DMA_TODEVICE); | |
1066 | } | |
1067 | ||
7a61fc86 MS |
1068 | tx_drop_count: |
1069 | ring->tx_dropped++; | |
7e230913 YP |
1070 | tx_drop: |
1071 | dev_kfree_skb_any(skb); | |
7e230913 | 1072 | return NETDEV_TX_OK; |
c27a02cd YP |
1073 | } |
1074 | ||
15fca2c8 TT |
1075 | netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, |
1076 | struct mlx4_en_rx_alloc *frame, | |
9ecc2d86 BB |
1077 | struct net_device *dev, unsigned int length, |
1078 | int tx_ind, int *doorbell_pending) | |
1079 | { | |
1080 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1081 | union mlx4_wqe_qpn_vlan qpn_vlan = {}; | |
1082 | struct mlx4_en_tx_ring *ring; | |
1083 | struct mlx4_en_tx_desc *tx_desc; | |
1084 | struct mlx4_wqe_data_seg *data; | |
1085 | struct mlx4_en_tx_info *tx_info; | |
1086 | int index, bf_index; | |
1087 | bool send_doorbell; | |
1088 | int nr_txbb = 1; | |
1089 | bool stop_queue; | |
1090 | dma_addr_t dma; | |
1091 | int real_size; | |
1092 | __be32 op_own; | |
1093 | u32 ring_cons; | |
1094 | bool bf_ok; | |
1095 | ||
1096 | BUILD_BUG_ON_MSG(ALIGN(CTRL_SIZE + DS_SIZE, TXBB_SIZE) != TXBB_SIZE, | |
1097 | "mlx4_en_xmit_frame requires minimum size tx desc"); | |
1098 | ||
67f8b1dc | 1099 | ring = priv->tx_ring[TX_XDP][tx_ind]; |
9ecc2d86 BB |
1100 | |
1101 | if (!priv->port_up) | |
1102 | goto tx_drop; | |
1103 | ||
1104 | if (mlx4_en_is_tx_ring_full(ring)) | |
7a61fc86 | 1105 | goto tx_drop_count; |
9ecc2d86 BB |
1106 | |
1107 | /* fetch ring->cons far ahead before needing it to avoid stall */ | |
1108 | ring_cons = READ_ONCE(ring->cons); | |
1109 | ||
1110 | index = ring->prod & ring->size_mask; | |
1111 | tx_info = &ring->tx_info[index]; | |
1112 | ||
1113 | bf_ok = ring->bf_enabled; | |
1114 | ||
1115 | /* Track current inflight packets for performance analysis */ | |
1116 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
1117 | (u32)(ring->prod - ring_cons - 1)); | |
1118 | ||
1119 | bf_index = ring->prod; | |
1120 | tx_desc = ring->buf + index * TXBB_SIZE; | |
1121 | data = &tx_desc->data; | |
1122 | ||
1123 | dma = frame->dma; | |
1124 | ||
1125 | tx_info->page = frame->page; | |
1126 | frame->page = NULL; | |
1127 | tx_info->map0_dma = dma; | |
ea3349a0 | 1128 | tx_info->map0_byte_count = PAGE_SIZE; |
9ecc2d86 BB |
1129 | tx_info->nr_txbb = nr_txbb; |
1130 | tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); | |
1131 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
1132 | tx_info->ts_requested = 0; | |
1133 | tx_info->nr_maps = 1; | |
1134 | tx_info->linear = 1; | |
1135 | tx_info->inl = 0; | |
1136 | ||
ea3349a0 MKL |
1137 | dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, |
1138 | length, PCI_DMA_TODEVICE); | |
9ecc2d86 | 1139 | |
ea3349a0 | 1140 | data->addr = cpu_to_be64(dma + frame->page_offset); |
9ecc2d86 BB |
1141 | data->lkey = ring->mr_key; |
1142 | dma_wmb(); | |
1143 | data->byte_count = cpu_to_be32(length); | |
1144 | ||
1145 | /* tx completion can avoid cache line miss for common cases */ | |
1146 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; | |
1147 | ||
1148 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1149 | ((ring->prod & ring->size) ? | |
1150 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1151 | ||
15fca2c8 | 1152 | rx_ring->xdp_tx++; |
9ecc2d86 BB |
1153 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, length); |
1154 | ||
1155 | ring->prod += nr_txbb; | |
1156 | ||
1157 | stop_queue = mlx4_en_is_tx_ring_full(ring); | |
1158 | send_doorbell = stop_queue || | |
1159 | *doorbell_pending > MLX4_EN_DOORBELL_BUDGET; | |
1160 | bf_ok &= send_doorbell; | |
1161 | ||
1162 | real_size = ((CTRL_SIZE + nr_txbb * DS_SIZE) / 16) & 0x3f; | |
1163 | ||
1164 | if (bf_ok) | |
1165 | qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); | |
1166 | else | |
1167 | qpn_vlan.fence_size = real_size; | |
1168 | ||
1169 | mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, TXBB_SIZE, bf_index, | |
1170 | op_own, bf_ok, send_doorbell); | |
1171 | *doorbell_pending = send_doorbell ? 0 : *doorbell_pending + 1; | |
1172 | ||
1173 | return NETDEV_TX_OK; | |
1174 | ||
7a61fc86 | 1175 | tx_drop_count: |
15fca2c8 | 1176 | rx_ring->xdp_tx_full++; |
7a61fc86 | 1177 | tx_drop: |
9ecc2d86 BB |
1178 | return NETDEV_TX_BUSY; |
1179 | } |