Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
09067122 | 44 | #include <linux/ipv6.h> |
310660a1 | 45 | #include <linux/indirect_call_wrapper.h> |
1169a642 | 46 | #include <net/ipv6.h> |
c27a02cd YP |
47 | |
48 | #include "mlx4_en.h" | |
49 | ||
c27a02cd | 50 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 51 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 52 | u16 stride, int node, int queue_index) |
c27a02cd YP |
53 | { |
54 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 55 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
56 | int tmp; |
57 | int err; | |
58 | ||
163561a4 | 59 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 60 | if (!ring) { |
4beaacc6 ED |
61 | en_err(priv, "Failed allocating TX ring\n"); |
62 | return -ENOMEM; | |
41d942d5 EE |
63 | } |
64 | ||
c27a02cd YP |
65 | ring->size = size; |
66 | ring->size_mask = size - 1; | |
e3f42f84 | 67 | ring->sp_stride = stride; |
35f31ff0 | 68 | ring->full_size = ring->size - HEADROOM - MLX4_MAX_DESC_TXBBS; |
c27a02cd | 69 | |
c27a02cd | 70 | tmp = size * sizeof(struct mlx4_en_tx_info); |
752ade68 | 71 | ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); |
41d942d5 | 72 | if (!ring->tx_info) { |
752ade68 MH |
73 | err = -ENOMEM; |
74 | goto err_ring; | |
41d942d5 | 75 | } |
e404decb | 76 | |
453a6082 | 77 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
78 | ring->tx_info, tmp); |
79 | ||
35f31ff0 ED |
80 | ring->bounce_buf = kmalloc_node(MLX4_TX_BOUNCE_BUFFER_SIZE, |
81 | GFP_KERNEL, node); | |
c27a02cd | 82 | if (!ring->bounce_buf) { |
35f31ff0 ED |
83 | ring->bounce_buf = kmalloc(MLX4_TX_BOUNCE_BUFFER_SIZE, |
84 | GFP_KERNEL); | |
163561a4 EE |
85 | if (!ring->bounce_buf) { |
86 | err = -ENOMEM; | |
87 | goto err_info; | |
88 | } | |
c27a02cd | 89 | } |
e3f42f84 | 90 | ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); |
c27a02cd | 91 | |
163561a4 | 92 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 93 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
e3f42f84 | 94 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
872bf2fb | 95 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 96 | if (err) { |
453a6082 | 97 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
98 | goto err_bounce; |
99 | } | |
100 | ||
e3f42f84 | 101 | ring->buf = ring->sp_wqres.buf.direct.buf; |
c27a02cd | 102 | |
1a91de28 JP |
103 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
104 | ring, ring->buf, ring->size, ring->buf_size, | |
e3f42f84 | 105 | (unsigned long long) ring->sp_wqres.buf.direct.map); |
c27a02cd | 106 | |
ddae0349 | 107 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
f3301870 MS |
108 | MLX4_RESERVE_ETH_BF_QP, |
109 | MLX4_RES_USAGE_DRIVER); | |
ddae0349 EE |
110 | if (err) { |
111 | en_err(priv, "failed reserving qp for TX ring\n"); | |
73898db0 | 112 | goto err_hwq_res; |
ddae0349 EE |
113 | } |
114 | ||
8900b894 | 115 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); |
c27a02cd | 116 | if (err) { |
453a6082 | 117 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 118 | goto err_reserve; |
c27a02cd | 119 | } |
e3f42f84 | 120 | ring->sp_qp.event = mlx4_en_sqp_event; |
c27a02cd | 121 | |
163561a4 | 122 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 123 | if (err) { |
1a91de28 | 124 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
125 | ring->bf.uar = &mdev->priv_uar; |
126 | ring->bf.uar->map = mdev->uar_map; | |
127 | ring->bf_enabled = false; | |
0fef9d03 AV |
128 | ring->bf_alloced = false; |
129 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
130 | } else { | |
131 | ring->bf_alloced = true; | |
132 | ring->bf_enabled = !!(priv->pflags & | |
133 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
134 | } | |
9ac93627 | 135 | ring->doorbell_address = ring->bf.uar->map + MLX4_SEND_DOORBELL; |
87a5c389 | 136 | |
ec693d47 | 137 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
138 | ring->queue_index = queue_index; |
139 | ||
42eab005 | 140 | if (queue_index < priv->num_tx_rings_p_up) |
f36963c9 RR |
141 | cpumask_set_cpu(cpumask_local_spread(queue_index, |
142 | priv->mdev->dev->numa_node), | |
e3f42f84 | 143 | &ring->sp_affinity_mask); |
ec693d47 | 144 | |
41d942d5 | 145 | *pring = ring; |
c27a02cd YP |
146 | return 0; |
147 | ||
ddae0349 EE |
148 | err_reserve: |
149 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd | 150 | err_hwq_res: |
e3f42f84 | 151 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
152 | err_bounce: |
153 | kfree(ring->bounce_buf); | |
154 | ring->bounce_buf = NULL; | |
41d942d5 | 155 | err_info: |
dc9b06d1 | 156 | kvfree(ring->tx_info); |
c27a02cd | 157 | ring->tx_info = NULL; |
41d942d5 EE |
158 | err_ring: |
159 | kfree(ring); | |
160 | *pring = NULL; | |
c27a02cd YP |
161 | return err; |
162 | } | |
163 | ||
164 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 165 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
166 | { |
167 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 168 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 169 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 170 | |
0fef9d03 | 171 | if (ring->bf_alloced) |
87a5c389 | 172 | mlx4_bf_free(mdev->dev, &ring->bf); |
e3f42f84 ED |
173 | mlx4_qp_remove(mdev->dev, &ring->sp_qp); |
174 | mlx4_qp_free(mdev->dev, &ring->sp_qp); | |
0eb08514 | 175 | mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); |
e3f42f84 | 176 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
177 | kfree(ring->bounce_buf); |
178 | ring->bounce_buf = NULL; | |
dc9b06d1 | 179 | kvfree(ring->tx_info); |
c27a02cd | 180 | ring->tx_info = NULL; |
41d942d5 EE |
181 | kfree(ring); |
182 | *pring = NULL; | |
c27a02cd YP |
183 | } |
184 | ||
185 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
186 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 187 | int cq, int user_prio) |
c27a02cd YP |
188 | { |
189 | struct mlx4_en_dev *mdev = priv->mdev; | |
190 | int err; | |
191 | ||
e3f42f84 | 192 | ring->sp_cqn = cq; |
c27a02cd YP |
193 | ring->prod = 0; |
194 | ring->cons = 0xffffffff; | |
195 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
196 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
197 | memset(ring->buf, 0, ring->buf_size); | |
9ecc2d86 | 198 | ring->free_tx_desc = mlx4_en_free_tx_desc; |
c27a02cd | 199 | |
e3f42f84 ED |
200 | ring->sp_qp_state = MLX4_QP_STATE_RST; |
201 | ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); | |
6a4e8121 | 202 | ring->mr_key = cpu_to_be32(mdev->mr.key); |
c27a02cd | 203 | |
e3f42f84 ED |
204 | mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, |
205 | ring->sp_cqn, user_prio, &ring->sp_context); | |
0fef9d03 | 206 | if (ring->bf_alloced) |
e3f42f84 | 207 | ring->sp_context.usr_page = |
85743f1e HN |
208 | cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, |
209 | ring->bf.uar->index)); | |
c27a02cd | 210 | |
e3f42f84 ED |
211 | err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, |
212 | &ring->sp_qp, &ring->sp_qp_state); | |
213 | if (!cpumask_empty(&ring->sp_affinity_mask)) | |
214 | netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, | |
d03a68f8 | 215 | ring->queue_index); |
c27a02cd YP |
216 | |
217 | return err; | |
218 | } | |
219 | ||
220 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
221 | struct mlx4_en_tx_ring *ring) | |
222 | { | |
223 | struct mlx4_en_dev *mdev = priv->mdev; | |
224 | ||
e3f42f84 ED |
225 | mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, |
226 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); | |
c27a02cd YP |
227 | } |
228 | ||
488a9b48 IS |
229 | static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) |
230 | { | |
9a714997 JK |
231 | u32 used = READ_ONCE(ring->prod) - READ_ONCE(ring->cons); |
232 | ||
233 | return used > ring->full_size; | |
488a9b48 IS |
234 | } |
235 | ||
2d4b6466 EE |
236 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
237 | struct mlx4_en_tx_ring *ring, int index, | |
238 | u8 owner) | |
239 | { | |
240 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
9573e0d3 | 241 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
2d4b6466 EE |
242 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
243 | void *end = ring->buf + ring->buf_size; | |
244 | __be32 *ptr = (__be32 *)tx_desc; | |
245 | int i; | |
246 | ||
247 | /* Optimize the common case when there are no wraparounds */ | |
9573e0d3 TT |
248 | if (likely((void *)tx_desc + |
249 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
2d4b6466 | 250 | /* Stamp the freed descriptor */ |
9573e0d3 | 251 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
252 | i += STAMP_STRIDE) { |
253 | *ptr = stamp; | |
254 | ptr += STAMP_DWORDS; | |
255 | } | |
256 | } else { | |
257 | /* Stamp the freed descriptor */ | |
9573e0d3 | 258 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
259 | i += STAMP_STRIDE) { |
260 | *ptr = stamp; | |
261 | ptr += STAMP_DWORDS; | |
262 | if ((void *)ptr >= end) { | |
263 | ptr = ring->buf; | |
264 | stamp ^= cpu_to_be32(0x80000000); | |
265 | } | |
266 | } | |
267 | } | |
268 | } | |
269 | ||
310660a1 ED |
270 | INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
271 | struct mlx4_en_tx_ring *ring, | |
272 | int index, u64 timestamp, | |
273 | int napi_mode)); | |
c27a02cd | 274 | |
9ecc2d86 BB |
275 | u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
276 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 277 | int index, u64 timestamp, |
9ecc2d86 | 278 | int napi_mode) |
c27a02cd | 279 | { |
c27a02cd | 280 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
9573e0d3 | 281 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd | 282 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; |
c27a02cd | 283 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
284 | struct sk_buff *skb = tx_info->skb; |
285 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 286 | int i; |
ec693d47 | 287 | |
29d40c90 ED |
288 | /* We do not touch skb here, so prefetch skb->users location |
289 | * to speedup consume_skb() | |
290 | */ | |
291 | prefetchw(&skb->users); | |
292 | ||
3d03641c ED |
293 | if (unlikely(timestamp)) { |
294 | struct skb_shared_hwtstamps hwts; | |
295 | ||
296 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
297 | skb_tstamp_tx(skb, &hwts); |
298 | } | |
c27a02cd | 299 | |
4c07c132 TT |
300 | if (!tx_info->inl) { |
301 | if (tx_info->linear) | |
302 | dma_unmap_single(priv->ddev, | |
303 | tx_info->map0_dma, | |
304 | tx_info->map0_byte_count, | |
eb9c5c0d | 305 | DMA_TO_DEVICE); |
4c07c132 TT |
306 | else |
307 | dma_unmap_page(priv->ddev, | |
308 | tx_info->map0_dma, | |
309 | tx_info->map0_byte_count, | |
eb9c5c0d | 310 | DMA_TO_DEVICE); |
4c07c132 TT |
311 | /* Optimize the common case when there are no wraparounds */ |
312 | if (likely((void *)tx_desc + | |
313 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
3d03641c ED |
314 | for (i = 1; i < nr_maps; i++) { |
315 | data++; | |
ebf8c9aa | 316 | dma_unmap_page(priv->ddev, |
3d03641c ED |
317 | (dma_addr_t)be64_to_cpu(data->addr), |
318 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 319 | DMA_TO_DEVICE); |
41efea5a | 320 | } |
4c07c132 TT |
321 | } else { |
322 | if ((void *)data >= end) | |
43d620c8 | 323 | data = ring->buf + ((void *)data - end); |
c27a02cd | 324 | |
3d03641c ED |
325 | for (i = 1; i < nr_maps; i++) { |
326 | data++; | |
41efea5a YP |
327 | /* Check for wraparound before unmapping */ |
328 | if ((void *) data >= end) | |
43d620c8 | 329 | data = ring->buf; |
ebf8c9aa | 330 | dma_unmap_page(priv->ddev, |
3d03641c ED |
331 | (dma_addr_t)be64_to_cpu(data->addr), |
332 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 333 | DMA_TO_DEVICE); |
41efea5a | 334 | } |
c27a02cd | 335 | } |
c27a02cd | 336 | } |
b4a53379 JDB |
337 | napi_consume_skb(skb, napi_mode); |
338 | ||
c27a02cd YP |
339 | return tx_info->nr_txbb; |
340 | } | |
341 | ||
310660a1 ED |
342 | INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
343 | struct mlx4_en_tx_ring *ring, | |
344 | int index, u64 timestamp, | |
345 | int napi_mode)); | |
346 | ||
9ecc2d86 BB |
347 | u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
348 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 349 | int index, u64 timestamp, |
9ecc2d86 BB |
350 | int napi_mode) |
351 | { | |
352 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
353 | struct mlx4_en_rx_alloc frame = { | |
354 | .page = tx_info->page, | |
355 | .dma = tx_info->map0_dma, | |
9ecc2d86 BB |
356 | }; |
357 | ||
b2b8a927 | 358 | if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { |
9ecc2d86 | 359 | dma_unmap_page(priv->ddev, tx_info->map0_dma, |
69ba9431 | 360 | PAGE_SIZE, priv->dma_dir); |
9ecc2d86 BB |
361 | put_page(tx_info->page); |
362 | } | |
363 | ||
364 | return tx_info->nr_txbb; | |
365 | } | |
c27a02cd YP |
366 | |
367 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
368 | { | |
369 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
370 | int cnt = 0; | |
371 | ||
372 | /* Skip last polled descriptor */ | |
373 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 374 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
375 | ring->cons, ring->prod); |
376 | ||
377 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
378 | if (netif_msg_tx_err(priv)) | |
453a6082 | 379 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
380 | return 0; |
381 | } | |
382 | ||
383 | while (ring->cons != ring->prod) { | |
9ecc2d86 | 384 | ring->last_nr_txbb = ring->free_tx_desc(priv, ring, |
c27a02cd | 385 | ring->cons & ring->size_mask, |
cf97050d | 386 | 0, 0 /* Non-NAPI caller */); |
c27a02cd YP |
387 | ring->cons += ring->last_nr_txbb; |
388 | cnt++; | |
389 | } | |
390 | ||
67f8b1dc TT |
391 | if (ring->tx_queue) |
392 | netdev_tx_reset_queue(ring->tx_queue); | |
41b74920 | 393 | |
c27a02cd | 394 | if (cnt) |
453a6082 | 395 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
396 | |
397 | return cnt; | |
398 | } | |
399 | ||
ba603d9d MS |
400 | static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe, |
401 | u16 cqe_index, struct mlx4_en_tx_ring *ring) | |
402 | { | |
403 | struct mlx4_en_dev *mdev = priv->mdev; | |
404 | struct mlx4_en_tx_info *tx_info; | |
405 | struct mlx4_en_tx_desc *tx_desc; | |
406 | u16 wqe_index; | |
407 | int desc_size; | |
408 | ||
409 | en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n", | |
410 | ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome); | |
411 | print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe), | |
412 | false); | |
413 | ||
414 | wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask; | |
415 | tx_info = &ring->tx_info[wqe_index]; | |
416 | desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE; | |
417 | en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn, | |
418 | wqe_index, desc_size); | |
419 | tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE); | |
420 | print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false); | |
421 | ||
422 | if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state)) | |
423 | return; | |
424 | ||
425 | en_err(priv, "Scheduling port restart\n"); | |
426 | queue_work(mdev->workqueue, &priv->restart_task); | |
427 | } | |
428 | ||
cf4058db ED |
429 | int mlx4_en_process_tx_cq(struct net_device *dev, |
430 | struct mlx4_en_cq *cq, int napi_budget) | |
c27a02cd YP |
431 | { |
432 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
433 | struct mlx4_cq *mcq = &cq->mcq; | |
67f8b1dc | 434 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; |
f0ab34f0 | 435 | struct mlx4_cqe *cqe; |
cc26a490 | 436 | u16 index, ring_index, stamp_index; |
c27a02cd | 437 | u32 txbbs_skipped = 0; |
2d4b6466 | 438 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
439 | u32 cons_index = mcq->cons_index; |
440 | int size = cq->size; | |
441 | u32 size_mask = ring->size_mask; | |
442 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
443 | u32 packets = 0; |
444 | u32 bytes = 0; | |
08ff3235 | 445 | int factor = priv->cqe_factor; |
0276a330 | 446 | int done = 0; |
fbc6daf1 | 447 | int budget = priv->tx_work_limit; |
fb1843ee ED |
448 | u32 last_nr_txbb; |
449 | u32 ring_cons; | |
c27a02cd | 450 | |
cc26a490 | 451 | if (unlikely(!priv->port_up)) |
cf4058db | 452 | return 0; |
c27a02cd | 453 | |
53511453 ED |
454 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
455 | ||
f0ab34f0 | 456 | index = cons_index & size_mask; |
b1b6b4da | 457 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
6aa7de05 MR |
458 | last_nr_txbb = READ_ONCE(ring->last_nr_txbb); |
459 | ring_cons = READ_ONCE(ring->cons); | |
fb1843ee | 460 | ring_index = ring_cons & size_mask; |
2d4b6466 | 461 | stamp_index = ring_index; |
f0ab34f0 YP |
462 | |
463 | /* Process all completed CQEs */ | |
464 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 465 | cons_index & size) && (done < budget)) { |
cc26a490 TT |
466 | u16 new_index; |
467 | ||
f0ab34f0 YP |
468 | /* |
469 | * make sure we read the CQE after we read the | |
470 | * ownership bit | |
471 | */ | |
12b3375f | 472 | dma_rmb(); |
f0ab34f0 | 473 | |
bd2f631d | 474 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
ba603d9d MS |
475 | MLX4_CQE_OPCODE_ERROR)) |
476 | if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state)) | |
477 | mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index, | |
478 | ring); | |
bd2f631d | 479 | |
f0ab34f0 YP |
480 | /* Skip over last polled CQE */ |
481 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
482 | ||
c27a02cd | 483 | do { |
fc96256c ED |
484 | u64 timestamp = 0; |
485 | ||
fb1843ee ED |
486 | txbbs_skipped += last_nr_txbb; |
487 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
fc96256c ED |
488 | |
489 | if (unlikely(ring->tx_info[ring_index].ts_requested)) | |
ec693d47 AV |
490 | timestamp = mlx4_en_get_cqe_ts(cqe); |
491 | ||
f0ab34f0 | 492 | /* free next descriptor */ |
310660a1 ED |
493 | last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc, |
494 | mlx4_en_free_tx_desc, | |
495 | mlx4_en_recycle_tx_desc, | |
f0ab34f0 | 496 | priv, ring, ring_index, |
cf97050d | 497 | timestamp, napi_budget); |
2d4b6466 EE |
498 | |
499 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 500 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
501 | ring->size)); |
502 | stamp_index = ring_index; | |
503 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
504 | packets++; |
505 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 506 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
507 | |
508 | ++cons_index; | |
509 | index = cons_index & size_mask; | |
b1b6b4da | 510 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 511 | } |
c27a02cd | 512 | |
c27a02cd YP |
513 | /* |
514 | * To prevent CQ overflow we first update CQ consumer and only then | |
515 | * the ring consumer. | |
516 | */ | |
f0ab34f0 | 517 | mcq->cons_index = cons_index; |
c27a02cd YP |
518 | mlx4_cq_set_ci(mcq); |
519 | wmb(); | |
fb1843ee ED |
520 | |
521 | /* we want to dirty this cache line once */ | |
6aa7de05 MR |
522 | WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); |
523 | WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); | |
fb1843ee | 524 | |
cc26a490 | 525 | if (cq->type == TX_XDP) |
cf4058db | 526 | return done; |
9ecc2d86 | 527 | |
5b263f53 | 528 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 529 | |
488a9b48 | 530 | /* Wakeup Tx queue if this stopped, and ring is not full. |
c18520bd | 531 | */ |
488a9b48 IS |
532 | if (netif_tx_queue_stopped(ring->tx_queue) && |
533 | !mlx4_en_is_tx_ring_full(ring)) { | |
c18520bd | 534 | netif_tx_wake_queue(ring->tx_queue); |
15bffdff | 535 | ring->wake_queue++; |
c27a02cd | 536 | } |
cc26a490 | 537 | |
cf4058db | 538 | return done; |
c27a02cd YP |
539 | } |
540 | ||
541 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
542 | { | |
543 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
544 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 545 | |
477b35b4 ED |
546 | if (likely(priv->port_up)) |
547 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
548 | else |
549 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
550 | } |
551 | ||
0276a330 EE |
552 | /* TX CQ polling - called by NAPI */ |
553 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
554 | { | |
555 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
556 | struct net_device *dev = cq->dev; | |
557 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
cf4058db | 558 | int work_done; |
0276a330 | 559 | |
cf4058db ED |
560 | work_done = mlx4_en_process_tx_cq(dev, cq, budget); |
561 | if (work_done >= budget) | |
fbc6daf1 | 562 | return budget; |
0276a330 | 563 | |
cf4058db ED |
564 | if (napi_complete_done(napi, work_done)) |
565 | mlx4_en_arm_cq(priv, cq); | |
fbc6daf1 AV |
566 | |
567 | return 0; | |
0276a330 | 568 | } |
c27a02cd | 569 | |
c27a02cd YP |
570 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
571 | struct mlx4_en_tx_ring *ring, | |
572 | u32 index, | |
573 | unsigned int desc_size) | |
574 | { | |
9573e0d3 | 575 | u32 copy = (ring->size - index) << LOG_TXBB_SIZE; |
c27a02cd YP |
576 | int i; |
577 | ||
578 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
579 | if ((i & (TXBB_SIZE - 1)) == 0) | |
580 | wmb(); | |
581 | ||
582 | *((u32 *) (ring->buf + i)) = | |
583 | *((u32 *) (ring->bounce_buf + copy + i)); | |
584 | } | |
585 | ||
586 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
587 | if ((i & (TXBB_SIZE - 1)) == 0) | |
588 | wmb(); | |
589 | ||
9573e0d3 | 590 | *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = |
c27a02cd YP |
591 | *((u32 *) (ring->bounce_buf + i)); |
592 | } | |
593 | ||
594 | /* Return real descriptor location */ | |
9573e0d3 | 595 | return ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd YP |
596 | } |
597 | ||
acea73d6 ED |
598 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
599 | * | |
600 | * It seems strange we do not simply use skb_copy_bits(). | |
601 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
602 | * | |
603 | * Note that caller already checked skb was not a gso packet | |
604 | */ | |
7dfa4b41 | 605 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 606 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 607 | void **pfrag) |
c27a02cd YP |
608 | { |
609 | void *ptr; | |
610 | ||
acea73d6 ED |
611 | if (skb->len > inline_thold || !inline_thold) |
612 | return false; | |
c27a02cd | 613 | |
acea73d6 ED |
614 | if (shinfo->nr_frags == 1) { |
615 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
616 | if (unlikely(!ptr)) | |
617 | return false; | |
618 | *pfrag = ptr; | |
619 | return true; | |
c27a02cd | 620 | } |
acea73d6 ED |
621 | if (shinfo->nr_frags) |
622 | return false; | |
623 | return true; | |
c27a02cd YP |
624 | } |
625 | ||
7dfa4b41 | 626 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
627 | { |
628 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
629 | <= MLX4_INLINE_ALIGN) | |
630 | return ALIGN(skb->len + CTRL_SIZE + | |
631 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
632 | else | |
633 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
634 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
635 | } | |
636 | ||
7dfa4b41 | 637 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 638 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 639 | struct net_device *dev, |
acea73d6 ED |
640 | int *lso_header_size, |
641 | bool *inline_ok, | |
1169a642 ED |
642 | void **pfrag, |
643 | int *hopbyhop) | |
c27a02cd YP |
644 | { |
645 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
646 | int real_size; |
647 | ||
b9d8839a | 648 | if (shinfo->gso_size) { |
acea73d6 | 649 | *inline_ok = false; |
1169a642 ED |
650 | *hopbyhop = 0; |
651 | if (skb->encapsulation) { | |
504148fe | 652 | *lso_header_size = skb_inner_tcp_all_headers(skb); |
1169a642 ED |
653 | } else { |
654 | /* Detects large IPV6 TCP packets and prepares for removal of | |
655 | * HBH header that has been pushed by ip6_xmit(), | |
656 | * mainly so that tcpdump can dissect them. | |
657 | */ | |
658 | if (ipv6_has_hopopt_jumbo(skb)) | |
659 | *hopbyhop = sizeof(struct hop_jumbo_hdr); | |
504148fe | 660 | *lso_header_size = skb_tcp_all_headers(skb); |
1169a642 | 661 | } |
b9d8839a | 662 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
1169a642 | 663 | ALIGN(*lso_header_size - *hopbyhop + 4, DS_SIZE); |
c27a02cd YP |
664 | if (unlikely(*lso_header_size != skb_headlen(skb))) { |
665 | /* We add a segment for the skb linear buffer only if | |
666 | * it contains data */ | |
667 | if (*lso_header_size < skb_headlen(skb)) | |
668 | real_size += DS_SIZE; | |
669 | else { | |
670 | if (netif_msg_tx_err(priv)) | |
453a6082 | 671 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
672 | return 0; |
673 | } | |
674 | } | |
c27a02cd YP |
675 | } else { |
676 | *lso_header_size = 0; | |
acea73d6 ED |
677 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
678 | shinfo, pfrag); | |
679 | ||
680 | if (*inline_ok) | |
c27a02cd | 681 | real_size = inline_size(skb); |
acea73d6 ED |
682 | else |
683 | real_size = CTRL_SIZE + | |
684 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
685 | } |
686 | ||
687 | return real_size; | |
688 | } | |
689 | ||
7dfa4b41 ED |
690 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
691 | const struct sk_buff *skb, | |
b9d8839a | 692 | const struct skb_shared_info *shinfo, |
224e92e0 | 693 | void *fragptr) |
c27a02cd YP |
694 | { |
695 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
31975e27 | 696 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); |
e533ac7e | 697 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
698 | |
699 | if (skb->len <= spc) { | |
93591aaa EE |
700 | if (likely(skb->len >= MIN_PKT_LEN)) { |
701 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
702 | } else { | |
703 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
f8f185e3 | 704 | memset(inl->data + skb->len, 0, |
93591aaa EE |
705 | MIN_PKT_LEN - skb->len); |
706 | } | |
f8f185e3 | 707 | skb_copy_from_linear_data(skb, inl->data, hlen); |
b9d8839a | 708 | if (shinfo->nr_frags) |
f8f185e3 | 709 | memcpy(inl->data + hlen, fragptr, |
b9d8839a | 710 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
711 | |
712 | } else { | |
713 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e | 714 | if (hlen <= spc) { |
f8f185e3 | 715 | skb_copy_from_linear_data(skb, inl->data, hlen); |
e533ac7e | 716 | if (hlen < spc) { |
f8f185e3 | 717 | memcpy(inl->data + hlen, |
e533ac7e ED |
718 | fragptr, spc - hlen); |
719 | fragptr += spc - hlen; | |
c27a02cd | 720 | } |
f8f185e3 KC |
721 | inl = (void *)inl->data + spc; |
722 | memcpy(inl->data, fragptr, skb->len - spc); | |
c27a02cd | 723 | } else { |
f8f185e3 KC |
724 | skb_copy_from_linear_data(skb, inl->data, spc); |
725 | inl = (void *)inl->data + spc; | |
726 | skb_copy_from_linear_data_offset(skb, spc, inl->data, | |
e533ac7e | 727 | hlen - spc); |
b9d8839a | 728 | if (shinfo->nr_frags) |
f8f185e3 | 729 | memcpy(inl->data + hlen - spc, |
b9d8839a ED |
730 | fragptr, |
731 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
732 | } |
733 | ||
12b3375f | 734 | dma_wmb(); |
c27a02cd YP |
735 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
736 | } | |
c27a02cd YP |
737 | } |
738 | ||
f663dd9a | 739 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
a350ecce | 740 | struct net_device *sb_dev) |
c27a02cd | 741 | { |
bc6a4744 | 742 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 743 | u16 rings_p_up = priv->num_tx_rings_p_up; |
c27a02cd | 744 | |
4b5e5b7e | 745 | if (netdev_get_num_tc(dev)) |
a350ecce | 746 | return netdev_pick_tx(dev, skb, NULL); |
bc6a4744 | 747 | |
a350ecce | 748 | return netdev_pick_tx(dev, skb, NULL) % rings_p_up; |
c27a02cd YP |
749 | } |
750 | ||
7dfa4b41 ED |
751 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
752 | unsigned int bytecnt) | |
87a5c389 YP |
753 | { |
754 | __iowrite64_copy(dst, src, bytecnt / 8); | |
755 | } | |
756 | ||
224e92e0 BB |
757 | void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) |
758 | { | |
759 | wmb(); | |
760 | /* Since there is no iowrite*_native() that writes the | |
761 | * value as is, without byteswapping - using the one | |
762 | * the doesn't do byteswapping in the relevant arch | |
763 | * endianness. | |
764 | */ | |
765 | #if defined(__LITTLE_ENDIAN) | |
766 | iowrite32( | |
767 | #else | |
768 | iowrite32be( | |
769 | #endif | |
9ac93627 | 770 | (__force u32)ring->doorbell_qpn, ring->doorbell_address); |
224e92e0 BB |
771 | } |
772 | ||
773 | static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, | |
774 | struct mlx4_en_tx_desc *tx_desc, | |
775 | union mlx4_wqe_qpn_vlan qpn_vlan, | |
776 | int desc_size, int bf_index, | |
777 | __be32 op_own, bool bf_ok, | |
778 | bool send_doorbell) | |
779 | { | |
780 | tx_desc->ctrl.qpn_vlan = qpn_vlan; | |
781 | ||
782 | if (bf_ok) { | |
783 | op_own |= htonl((bf_index & 0xffff) << 8); | |
784 | /* Ensure new descriptor hits memory | |
785 | * before setting ownership of this descriptor to HW | |
786 | */ | |
787 | dma_wmb(); | |
788 | tx_desc->ctrl.owner_opcode = op_own; | |
789 | ||
790 | wmb(); | |
791 | ||
792 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, | |
793 | desc_size); | |
794 | ||
795 | wmb(); | |
796 | ||
797 | ring->bf.offset ^= ring->bf.buf_size; | |
798 | } else { | |
799 | /* Ensure new descriptor hits memory | |
800 | * before setting ownership of this descriptor to HW | |
801 | */ | |
802 | dma_wmb(); | |
803 | tx_desc->ctrl.owner_opcode = op_own; | |
804 | if (send_doorbell) | |
805 | mlx4_en_xmit_doorbell(ring); | |
806 | else | |
807 | ring->xmit_more++; | |
808 | } | |
809 | } | |
810 | ||
f28186d6 TT |
811 | static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, |
812 | struct skb_shared_info *shinfo, | |
813 | struct mlx4_wqe_data_seg *data, | |
814 | struct sk_buff *skb, | |
815 | int lso_header_size, | |
816 | __be32 mr_key, | |
817 | struct mlx4_en_tx_info *tx_info) | |
818 | { | |
819 | struct device *ddev = priv->ddev; | |
820 | dma_addr_t dma = 0; | |
821 | u32 byte_count = 0; | |
822 | int i_frag; | |
823 | ||
824 | /* Map fragments if any */ | |
825 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { | |
d7840976 | 826 | const skb_frag_t *frag = &shinfo->frags[i_frag]; |
f28186d6 TT |
827 | byte_count = skb_frag_size(frag); |
828 | dma = skb_frag_dma_map(ddev, frag, | |
829 | 0, byte_count, | |
830 | DMA_TO_DEVICE); | |
831 | if (dma_mapping_error(ddev, dma)) | |
832 | goto tx_drop_unmap; | |
833 | ||
834 | data->addr = cpu_to_be64(dma); | |
835 | data->lkey = mr_key; | |
836 | dma_wmb(); | |
837 | data->byte_count = cpu_to_be32(byte_count); | |
838 | --data; | |
839 | } | |
840 | ||
841 | /* Map linear part if needed */ | |
842 | if (tx_info->linear) { | |
843 | byte_count = skb_headlen(skb) - lso_header_size; | |
844 | ||
845 | dma = dma_map_single(ddev, skb->data + | |
846 | lso_header_size, byte_count, | |
eb9c5c0d | 847 | DMA_TO_DEVICE); |
f28186d6 TT |
848 | if (dma_mapping_error(ddev, dma)) |
849 | goto tx_drop_unmap; | |
850 | ||
851 | data->addr = cpu_to_be64(dma); | |
852 | data->lkey = mr_key; | |
853 | dma_wmb(); | |
854 | data->byte_count = cpu_to_be32(byte_count); | |
855 | } | |
856 | /* tx completion can avoid cache line miss for common cases */ | |
857 | tx_info->map0_dma = dma; | |
858 | tx_info->map0_byte_count = byte_count; | |
859 | ||
860 | return true; | |
861 | ||
862 | tx_drop_unmap: | |
863 | en_err(priv, "DMA mapping error\n"); | |
864 | ||
865 | while (++i_frag < shinfo->nr_frags) { | |
866 | ++data; | |
867 | dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), | |
868 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 869 | DMA_TO_DEVICE); |
f28186d6 TT |
870 | } |
871 | ||
872 | return false; | |
873 | } | |
874 | ||
61357325 | 875 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 876 | { |
b9d8839a | 877 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 878 | struct mlx4_en_priv *priv = netdev_priv(dev); |
224e92e0 | 879 | union mlx4_wqe_qpn_vlan qpn_vlan = {}; |
c27a02cd | 880 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
881 | struct mlx4_en_tx_desc *tx_desc; |
882 | struct mlx4_wqe_data_seg *data; | |
c27a02cd | 883 | struct mlx4_en_tx_info *tx_info; |
7c8c0291 | 884 | u32 __maybe_unused ring_cons; |
f28186d6 | 885 | int tx_ind; |
c27a02cd YP |
886 | int nr_txbb; |
887 | int desc_size; | |
888 | int real_size; | |
87a5c389 | 889 | u32 index, bf_index; |
1169a642 | 890 | struct ipv6hdr *h6; |
c27a02cd | 891 | __be32 op_own; |
c27a02cd | 892 | int lso_header_size; |
acea73d6 | 893 | void *fragptr = NULL; |
87a5c389 | 894 | bool bounce = false; |
5804283d | 895 | bool send_doorbell; |
fe971b95 | 896 | bool stop_queue; |
acea73d6 | 897 | bool inline_ok; |
f28186d6 | 898 | u8 data_offset; |
1169a642 | 899 | int hopbyhop; |
224e92e0 | 900 | bool bf_ok; |
c27a02cd | 901 | |
f905c79e | 902 | tx_ind = skb_get_queue_mapping(skb); |
67f8b1dc | 903 | ring = priv->tx_ring[TX][tx_ind]; |
f905c79e | 904 | |
f28186d6 | 905 | if (unlikely(!priv->port_up)) |
63a664b7 ED |
906 | goto tx_drop; |
907 | ||
acea73d6 | 908 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
1169a642 | 909 | &inline_ok, &fragptr, &hopbyhop); |
c27a02cd | 910 | if (unlikely(!real_size)) |
7a61fc86 | 911 | goto tx_drop_count; |
c27a02cd | 912 | |
25985edc | 913 | /* Align descriptor to TXBB size */ |
c27a02cd | 914 | desc_size = ALIGN(real_size, TXBB_SIZE); |
9573e0d3 | 915 | nr_txbb = desc_size >> LOG_TXBB_SIZE; |
c27a02cd | 916 | |
224e92e0 | 917 | bf_ok = ring->bf_enabled; |
e38af4fa | 918 | if (skb_vlan_tag_present(skb)) { |
f28186d6 TT |
919 | u16 vlan_proto; |
920 | ||
224e92e0 | 921 | qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); |
e38af4fa | 922 | vlan_proto = be16_to_cpu(skb->vlan_proto); |
224e92e0 BB |
923 | if (vlan_proto == ETH_P_8021AD) |
924 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; | |
925 | else if (vlan_proto == ETH_P_8021Q) | |
926 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; | |
927 | else | |
928 | qpn_vlan.ins_vlan = 0; | |
929 | bf_ok = false; | |
e38af4fa | 930 | } |
c27a02cd | 931 | |
53511453 | 932 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 933 | |
c27a02cd YP |
934 | /* Packet is good - grab an index and transmit it */ |
935 | index = ring->prod & ring->size_mask; | |
87a5c389 | 936 | bf_index = ring->prod; |
c27a02cd YP |
937 | |
938 | /* See if we have enough space for whole descriptor TXBB for setting | |
939 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
940 | if (likely(index + nr_txbb <= ring->size)) | |
9573e0d3 | 941 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
87a5c389 | 942 | else { |
0e706f79 ED |
943 | if (unlikely(nr_txbb > MLX4_MAX_DESC_TXBBS)) { |
944 | if (netif_msg_tx_err(priv)) | |
945 | en_warn(priv, "Oversized header or SG list\n"); | |
946 | goto tx_drop_count; | |
947 | } | |
c27a02cd | 948 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 | 949 | bounce = true; |
224e92e0 | 950 | bf_ok = false; |
87a5c389 | 951 | } |
c27a02cd YP |
952 | |
953 | /* Save skb in tx_info ring */ | |
954 | tx_info = &ring->tx_info[index]; | |
955 | tx_info->skb = skb; | |
956 | tx_info->nr_txbb = nr_txbb; | |
957 | ||
f28186d6 TT |
958 | if (!lso_header_size) { |
959 | data = &tx_desc->data; | |
960 | data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
961 | } else { | |
1169a642 | 962 | int lso_align = ALIGN(lso_header_size - hopbyhop + 4, DS_SIZE); |
f28186d6 TT |
963 | |
964 | data = (void *)&tx_desc->lso + lso_align; | |
965 | data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; | |
966 | } | |
237a3a3b AV |
967 | |
968 | /* valid only for none inline segments */ | |
f28186d6 | 969 | tx_info->data_offset = data_offset; |
237a3a3b | 970 | |
acea73d6 ED |
971 | tx_info->inl = inline_ok; |
972 | ||
f28186d6 | 973 | tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; |
237a3a3b | 974 | |
b9d8839a | 975 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 976 | data += tx_info->nr_maps - 1; |
237a3a3b | 977 | |
f28186d6 TT |
978 | if (!tx_info->inl) |
979 | if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, | |
980 | lso_header_size, ring->mr_key, | |
981 | tx_info)) | |
982 | goto tx_drop_count; | |
237a3a3b | 983 | |
ec693d47 AV |
984 | /* |
985 | * For timestamping add flag to skb_shinfo and | |
986 | * set flag for further reference | |
987 | */ | |
e70602a8 | 988 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
989 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
990 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
991 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
992 | tx_info->ts_requested = 1; |
993 | } | |
994 | ||
6cc9c6fb | 995 | /* Prepare ctrl segment apart opcode+ownership, which depends on |
c27a02cd | 996 | * whether LSO is used */ |
60d6fe99 | 997 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 998 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
999 | if (!skb->encapsulation) |
1000 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
1001 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
1002 | else | |
1003 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 1004 | ring->tx_csum++; |
c27a02cd YP |
1005 | } |
1006 | ||
79aeaccd | 1007 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
1008 | struct ethhdr *ethh; |
1009 | ||
213815a1 YB |
1010 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
1011 | * so that VFs and PF can communicate with each other | |
1012 | */ | |
1013 | ethh = (struct ethhdr *)skb->data; | |
1014 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
1015 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
1016 | } | |
1017 | ||
c27a02cd YP |
1018 | /* Handle LSO (TSO) packets */ |
1019 | if (lso_header_size) { | |
b9d8839a ED |
1020 | int i; |
1021 | ||
c27a02cd YP |
1022 | /* Mark opcode as LSO */ |
1023 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
1024 | ((ring->prod & ring->size) ? | |
1025 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1026 | ||
1169a642 | 1027 | lso_header_size -= hopbyhop; |
c27a02cd YP |
1028 | /* Fill in the LSO prefix */ |
1029 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 1030 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd | 1031 | |
c27a02cd | 1032 | |
1169a642 ED |
1033 | if (unlikely(hopbyhop)) { |
1034 | /* remove the HBH header. | |
1035 | * Layout: [Ethernet header][IPv6 header][HBH][TCP header] | |
1036 | */ | |
1037 | memcpy(tx_desc->lso.header, skb->data, ETH_HLEN + sizeof(*h6)); | |
1038 | h6 = (struct ipv6hdr *)((char *)tx_desc->lso.header + ETH_HLEN); | |
1039 | h6->nexthdr = IPPROTO_TCP; | |
1040 | /* Copy the TCP header after the IPv6 one */ | |
1041 | memcpy(h6 + 1, | |
1042 | skb->data + ETH_HLEN + sizeof(*h6) + | |
1043 | sizeof(struct hop_jumbo_hdr), | |
1044 | tcp_hdrlen(skb)); | |
1045 | /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */ | |
1046 | } else { | |
1047 | /* Copy headers; | |
1048 | * note that we already verified that it is linear | |
1049 | */ | |
1050 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
1051 | } | |
9fab426d | 1052 | ring->tso_packets++; |
b9d8839a | 1053 | |
75d04aa3 | 1054 | i = shinfo->gso_segs; |
5b263f53 | 1055 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
1056 | ring->packets += i; |
1057 | } else { | |
1058 | /* Normal (Non LSO) packet */ | |
1059 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1060 | ((ring->prod & ring->size) ? | |
1061 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 1062 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 1063 | ring->packets++; |
c27a02cd | 1064 | } |
5b263f53 | 1065 | ring->bytes += tx_info->nr_bytes; |
c27a02cd | 1066 | |
acea73d6 | 1067 | if (tx_info->inl) |
224e92e0 | 1068 | build_inline_wqe(tx_desc, skb, shinfo, fragptr); |
c27a02cd | 1069 | |
837052d0 | 1070 | if (skb->encapsulation) { |
09067122 AD |
1071 | union { |
1072 | struct iphdr *v4; | |
1073 | struct ipv6hdr *v6; | |
1074 | unsigned char *hdr; | |
1075 | } ip; | |
1076 | u8 proto; | |
1077 | ||
1078 | ip.hdr = skb_inner_network_header(skb); | |
1079 | proto = (ip.v4->version == 4) ? ip.v4->protocol : | |
1080 | ip.v6->nexthdr; | |
1081 | ||
1082 | if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) | |
837052d0 OG |
1083 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); |
1084 | else | |
1085 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
1086 | } | |
1087 | ||
9a714997 | 1088 | WRITE_ONCE(ring->prod, ring->prod + nr_txbb); |
c27a02cd YP |
1089 | |
1090 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 1091 | if (unlikely(bounce)) |
c27a02cd YP |
1092 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
1093 | ||
eb0cabbd AV |
1094 | skb_tx_timestamp(skb); |
1095 | ||
fe971b95 | 1096 | /* Check available TXBBs And 2K spare for prefetch */ |
488a9b48 | 1097 | stop_queue = mlx4_en_is_tx_ring_full(ring); |
fe971b95 ED |
1098 | if (unlikely(stop_queue)) { |
1099 | netif_tx_stop_queue(ring->tx_queue); | |
1100 | ring->queue_stopped++; | |
1101 | } | |
c2973444 ED |
1102 | |
1103 | send_doorbell = __netdev_tx_sent_queue(ring->tx_queue, | |
1104 | tx_info->nr_bytes, | |
3c31ff22 | 1105 | netdev_xmit_more()); |
5804283d | 1106 | |
6a4e8121 ED |
1107 | real_size = (real_size / 16) & 0x3f; |
1108 | ||
224e92e0 | 1109 | bf_ok &= desc_size <= MAX_BF && send_doorbell; |
e38af4fa | 1110 | |
224e92e0 BB |
1111 | if (bf_ok) |
1112 | qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); | |
1113 | else | |
1114 | qpn_vlan.fence_size = real_size; | |
7dfa4b41 | 1115 | |
224e92e0 BB |
1116 | mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, |
1117 | op_own, bf_ok, send_doorbell); | |
c27a02cd | 1118 | |
fe971b95 ED |
1119 | if (unlikely(stop_queue)) { |
1120 | /* If queue was emptied after the if (stop_queue) , and before | |
1121 | * the netif_tx_stop_queue() - need to wake the queue, | |
1122 | * or else it will remain stopped forever. | |
1123 | * Need a memory barrier to make sure ring->cons was not | |
1124 | * updated before queue was stopped. | |
1125 | */ | |
1126 | smp_rmb(); | |
1127 | ||
488a9b48 | 1128 | if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { |
fe971b95 ED |
1129 | netif_tx_wake_queue(ring->tx_queue); |
1130 | ring->wake_queue++; | |
1131 | } | |
1132 | } | |
ec634fe3 | 1133 | return NETDEV_TX_OK; |
7e230913 | 1134 | |
7a61fc86 MS |
1135 | tx_drop_count: |
1136 | ring->tx_dropped++; | |
7e230913 YP |
1137 | tx_drop: |
1138 | dev_kfree_skb_any(skb); | |
7e230913 | 1139 | return NETDEV_TX_OK; |
c27a02cd YP |
1140 | } |
1141 | ||
36ea7964 TT |
1142 | #define MLX4_EN_XDP_TX_NRTXBB 1 |
1143 | #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ | |
1144 | / 16) & 0x3f) | |
1145 | ||
f025fd60 TT |
1146 | void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, |
1147 | struct mlx4_en_tx_ring *ring) | |
1148 | { | |
1149 | int i; | |
1150 | ||
1151 | for (i = 0; i < ring->size; i++) { | |
1152 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; | |
1153 | struct mlx4_en_tx_desc *tx_desc = ring->buf + | |
1154 | (i << LOG_TXBB_SIZE); | |
1155 | ||
1156 | tx_info->map0_byte_count = PAGE_SIZE; | |
1157 | tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; | |
1158 | tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
1159 | tx_info->ts_requested = 0; | |
1160 | tx_info->nr_maps = 1; | |
1161 | tx_info->linear = 1; | |
1162 | tx_info->inl = 0; | |
1163 | ||
1164 | tx_desc->data.lkey = ring->mr_key; | |
1165 | tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; | |
1166 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; | |
1167 | } | |
1168 | } | |
1169 | ||
15fca2c8 TT |
1170 | netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, |
1171 | struct mlx4_en_rx_alloc *frame, | |
5dad61b8 | 1172 | struct mlx4_en_priv *priv, unsigned int length, |
36ea7964 | 1173 | int tx_ind, bool *doorbell_pending) |
9ecc2d86 | 1174 | { |
9ecc2d86 | 1175 | struct mlx4_en_tx_desc *tx_desc; |
9ecc2d86 | 1176 | struct mlx4_en_tx_info *tx_info; |
36ea7964 TT |
1177 | struct mlx4_wqe_data_seg *data; |
1178 | struct mlx4_en_tx_ring *ring; | |
9ecc2d86 | 1179 | dma_addr_t dma; |
9ecc2d86 | 1180 | __be32 op_own; |
36ea7964 | 1181 | int index; |
9ecc2d86 | 1182 | |
36ea7964 TT |
1183 | if (unlikely(!priv->port_up)) |
1184 | goto tx_drop; | |
9ecc2d86 | 1185 | |
67f8b1dc | 1186 | ring = priv->tx_ring[TX_XDP][tx_ind]; |
9ecc2d86 | 1187 | |
36ea7964 | 1188 | if (unlikely(mlx4_en_is_tx_ring_full(ring))) |
7a61fc86 | 1189 | goto tx_drop_count; |
9ecc2d86 | 1190 | |
9ecc2d86 BB |
1191 | index = ring->prod & ring->size_mask; |
1192 | tx_info = &ring->tx_info[index]; | |
1193 | ||
9573e0d3 | 1194 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
9ecc2d86 BB |
1195 | data = &tx_desc->data; |
1196 | ||
1197 | dma = frame->dma; | |
1198 | ||
1199 | tx_info->page = frame->page; | |
1200 | frame->page = NULL; | |
1201 | tx_info->map0_dma = dma; | |
9ecc2d86 | 1202 | tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); |
9ecc2d86 | 1203 | |
ea3349a0 | 1204 | dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, |
eb9c5c0d | 1205 | length, DMA_TO_DEVICE); |
9ecc2d86 | 1206 | |
ea3349a0 | 1207 | data->addr = cpu_to_be64(dma + frame->page_offset); |
9ecc2d86 BB |
1208 | dma_wmb(); |
1209 | data->byte_count = cpu_to_be32(length); | |
1210 | ||
1211 | /* tx completion can avoid cache line miss for common cases */ | |
9ecc2d86 BB |
1212 | |
1213 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1214 | ((ring->prod & ring->size) ? | |
1215 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1216 | ||
15fca2c8 | 1217 | rx_ring->xdp_tx++; |
9ecc2d86 | 1218 | |
9a714997 | 1219 | WRITE_ONCE(ring->prod, ring->prod + MLX4_EN_XDP_TX_NRTXBB); |
9ecc2d86 | 1220 | |
f6f0aa97 TT |
1221 | /* Ensure new descriptor hits memory |
1222 | * before setting ownership of this descriptor to HW | |
1223 | */ | |
1224 | dma_wmb(); | |
1225 | tx_desc->ctrl.owner_opcode = op_own; | |
1226 | ring->xmit_more++; | |
9ecc2d86 | 1227 | |
36ea7964 | 1228 | *doorbell_pending = true; |
9ecc2d86 BB |
1229 | |
1230 | return NETDEV_TX_OK; | |
1231 | ||
7a61fc86 | 1232 | tx_drop_count: |
15fca2c8 | 1233 | rx_ring->xdp_tx_full++; |
6c78511b | 1234 | *doorbell_pending = true; |
7a61fc86 | 1235 | tx_drop: |
9ecc2d86 BB |
1236 | return NETDEV_TX_BUSY; |
1237 | } |