Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
29d40c90 | 40 | #include <linux/prefetch.h> |
c27a02cd | 41 | #include <linux/vmalloc.h> |
fa37a958 | 42 | #include <linux/tcp.h> |
837052d0 | 43 | #include <linux/ip.h> |
09067122 | 44 | #include <linux/ipv6.h> |
310660a1 | 45 | #include <linux/indirect_call_wrapper.h> |
1169a642 | 46 | #include <net/ipv6.h> |
c27a02cd YP |
47 | |
48 | #include "mlx4_en.h" | |
49 | ||
c27a02cd | 50 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, |
ddae0349 | 51 | struct mlx4_en_tx_ring **pring, u32 size, |
d03a68f8 | 52 | u16 stride, int node, int queue_index) |
c27a02cd YP |
53 | { |
54 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 55 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
56 | int tmp; |
57 | int err; | |
58 | ||
163561a4 | 59 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 60 | if (!ring) { |
4beaacc6 ED |
61 | en_err(priv, "Failed allocating TX ring\n"); |
62 | return -ENOMEM; | |
41d942d5 EE |
63 | } |
64 | ||
c27a02cd YP |
65 | ring->size = size; |
66 | ring->size_mask = size - 1; | |
e3f42f84 | 67 | ring->sp_stride = stride; |
488a9b48 | 68 | ring->full_size = ring->size - HEADROOM - MAX_DESC_TXBBS; |
c27a02cd | 69 | |
c27a02cd | 70 | tmp = size * sizeof(struct mlx4_en_tx_info); |
752ade68 | 71 | ring->tx_info = kvmalloc_node(tmp, GFP_KERNEL, node); |
41d942d5 | 72 | if (!ring->tx_info) { |
752ade68 MH |
73 | err = -ENOMEM; |
74 | goto err_ring; | |
41d942d5 | 75 | } |
e404decb | 76 | |
453a6082 | 77 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
78 | ring->tx_info, tmp); |
79 | ||
163561a4 | 80 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 81 | if (!ring->bounce_buf) { |
163561a4 EE |
82 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
83 | if (!ring->bounce_buf) { | |
84 | err = -ENOMEM; | |
85 | goto err_info; | |
86 | } | |
c27a02cd | 87 | } |
e3f42f84 | 88 | ring->buf_size = ALIGN(size * ring->sp_stride, MLX4_EN_PAGE_SIZE); |
c27a02cd | 89 | |
163561a4 | 90 | /* Allocate HW buffers on provided NUMA node */ |
872bf2fb | 91 | set_dev_node(&mdev->dev->persist->pdev->dev, node); |
e3f42f84 | 92 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
872bf2fb | 93 | set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 94 | if (err) { |
453a6082 | 95 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
96 | goto err_bounce; |
97 | } | |
98 | ||
e3f42f84 | 99 | ring->buf = ring->sp_wqres.buf.direct.buf; |
c27a02cd | 100 | |
1a91de28 JP |
101 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", |
102 | ring, ring->buf, ring->size, ring->buf_size, | |
e3f42f84 | 103 | (unsigned long long) ring->sp_wqres.buf.direct.map); |
c27a02cd | 104 | |
ddae0349 | 105 | err = mlx4_qp_reserve_range(mdev->dev, 1, 1, &ring->qpn, |
f3301870 MS |
106 | MLX4_RESERVE_ETH_BF_QP, |
107 | MLX4_RES_USAGE_DRIVER); | |
ddae0349 EE |
108 | if (err) { |
109 | en_err(priv, "failed reserving qp for TX ring\n"); | |
73898db0 | 110 | goto err_hwq_res; |
ddae0349 EE |
111 | } |
112 | ||
8900b894 | 113 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->sp_qp); |
c27a02cd | 114 | if (err) { |
453a6082 | 115 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
ddae0349 | 116 | goto err_reserve; |
c27a02cd | 117 | } |
e3f42f84 | 118 | ring->sp_qp.event = mlx4_en_sqp_event; |
c27a02cd | 119 | |
163561a4 | 120 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 | 121 | if (err) { |
1a91de28 | 122 | en_dbg(DRV, priv, "working without blueflame (%d)\n", err); |
87a5c389 YP |
123 | ring->bf.uar = &mdev->priv_uar; |
124 | ring->bf.uar->map = mdev->uar_map; | |
125 | ring->bf_enabled = false; | |
0fef9d03 AV |
126 | ring->bf_alloced = false; |
127 | priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME; | |
128 | } else { | |
129 | ring->bf_alloced = true; | |
130 | ring->bf_enabled = !!(priv->pflags & | |
131 | MLX4_EN_PRIV_FLAGS_BLUEFLAME); | |
132 | } | |
9ac93627 | 133 | ring->doorbell_address = ring->bf.uar->map + MLX4_SEND_DOORBELL; |
87a5c389 | 134 | |
ec693d47 | 135 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
136 | ring->queue_index = queue_index; |
137 | ||
42eab005 | 138 | if (queue_index < priv->num_tx_rings_p_up) |
f36963c9 RR |
139 | cpumask_set_cpu(cpumask_local_spread(queue_index, |
140 | priv->mdev->dev->numa_node), | |
e3f42f84 | 141 | &ring->sp_affinity_mask); |
ec693d47 | 142 | |
41d942d5 | 143 | *pring = ring; |
c27a02cd YP |
144 | return 0; |
145 | ||
ddae0349 EE |
146 | err_reserve: |
147 | mlx4_qp_release_range(mdev->dev, ring->qpn, 1); | |
c27a02cd | 148 | err_hwq_res: |
e3f42f84 | 149 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
150 | err_bounce: |
151 | kfree(ring->bounce_buf); | |
152 | ring->bounce_buf = NULL; | |
41d942d5 | 153 | err_info: |
dc9b06d1 | 154 | kvfree(ring->tx_info); |
c27a02cd | 155 | ring->tx_info = NULL; |
41d942d5 EE |
156 | err_ring: |
157 | kfree(ring); | |
158 | *pring = NULL; | |
c27a02cd YP |
159 | return err; |
160 | } | |
161 | ||
162 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 163 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
164 | { |
165 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 166 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 167 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 168 | |
0fef9d03 | 169 | if (ring->bf_alloced) |
87a5c389 | 170 | mlx4_bf_free(mdev->dev, &ring->bf); |
e3f42f84 ED |
171 | mlx4_qp_remove(mdev->dev, &ring->sp_qp); |
172 | mlx4_qp_free(mdev->dev, &ring->sp_qp); | |
0eb08514 | 173 | mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); |
e3f42f84 | 174 | mlx4_free_hwq_res(mdev->dev, &ring->sp_wqres, ring->buf_size); |
c27a02cd YP |
175 | kfree(ring->bounce_buf); |
176 | ring->bounce_buf = NULL; | |
dc9b06d1 | 177 | kvfree(ring->tx_info); |
c27a02cd | 178 | ring->tx_info = NULL; |
41d942d5 EE |
179 | kfree(ring); |
180 | *pring = NULL; | |
c27a02cd YP |
181 | } |
182 | ||
183 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
184 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 185 | int cq, int user_prio) |
c27a02cd YP |
186 | { |
187 | struct mlx4_en_dev *mdev = priv->mdev; | |
188 | int err; | |
189 | ||
e3f42f84 | 190 | ring->sp_cqn = cq; |
c27a02cd YP |
191 | ring->prod = 0; |
192 | ring->cons = 0xffffffff; | |
193 | ring->last_nr_txbb = 1; | |
c27a02cd YP |
194 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
195 | memset(ring->buf, 0, ring->buf_size); | |
9ecc2d86 | 196 | ring->free_tx_desc = mlx4_en_free_tx_desc; |
c27a02cd | 197 | |
e3f42f84 ED |
198 | ring->sp_qp_state = MLX4_QP_STATE_RST; |
199 | ring->doorbell_qpn = cpu_to_be32(ring->sp_qp.qpn << 8); | |
6a4e8121 | 200 | ring->mr_key = cpu_to_be32(mdev->mr.key); |
c27a02cd | 201 | |
e3f42f84 ED |
202 | mlx4_en_fill_qp_context(priv, ring->size, ring->sp_stride, 1, 0, ring->qpn, |
203 | ring->sp_cqn, user_prio, &ring->sp_context); | |
0fef9d03 | 204 | if (ring->bf_alloced) |
e3f42f84 | 205 | ring->sp_context.usr_page = |
85743f1e HN |
206 | cpu_to_be32(mlx4_to_hw_uar_index(mdev->dev, |
207 | ring->bf.uar->index)); | |
c27a02cd | 208 | |
e3f42f84 ED |
209 | err = mlx4_qp_to_ready(mdev->dev, &ring->sp_wqres.mtt, &ring->sp_context, |
210 | &ring->sp_qp, &ring->sp_qp_state); | |
211 | if (!cpumask_empty(&ring->sp_affinity_mask)) | |
212 | netif_set_xps_queue(priv->dev, &ring->sp_affinity_mask, | |
d03a68f8 | 213 | ring->queue_index); |
c27a02cd YP |
214 | |
215 | return err; | |
216 | } | |
217 | ||
218 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
219 | struct mlx4_en_tx_ring *ring) | |
220 | { | |
221 | struct mlx4_en_dev *mdev = priv->mdev; | |
222 | ||
e3f42f84 ED |
223 | mlx4_qp_modify(mdev->dev, NULL, ring->sp_qp_state, |
224 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->sp_qp); | |
c27a02cd YP |
225 | } |
226 | ||
488a9b48 IS |
227 | static inline bool mlx4_en_is_tx_ring_full(struct mlx4_en_tx_ring *ring) |
228 | { | |
229 | return ring->prod - ring->cons > ring->full_size; | |
230 | } | |
231 | ||
2d4b6466 EE |
232 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
233 | struct mlx4_en_tx_ring *ring, int index, | |
234 | u8 owner) | |
235 | { | |
236 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
9573e0d3 | 237 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
2d4b6466 EE |
238 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
239 | void *end = ring->buf + ring->buf_size; | |
240 | __be32 *ptr = (__be32 *)tx_desc; | |
241 | int i; | |
242 | ||
243 | /* Optimize the common case when there are no wraparounds */ | |
9573e0d3 TT |
244 | if (likely((void *)tx_desc + |
245 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
2d4b6466 | 246 | /* Stamp the freed descriptor */ |
9573e0d3 | 247 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
248 | i += STAMP_STRIDE) { |
249 | *ptr = stamp; | |
250 | ptr += STAMP_DWORDS; | |
251 | } | |
252 | } else { | |
253 | /* Stamp the freed descriptor */ | |
9573e0d3 | 254 | for (i = 0; i < tx_info->nr_txbb << LOG_TXBB_SIZE; |
2d4b6466 EE |
255 | i += STAMP_STRIDE) { |
256 | *ptr = stamp; | |
257 | ptr += STAMP_DWORDS; | |
258 | if ((void *)ptr >= end) { | |
259 | ptr = ring->buf; | |
260 | stamp ^= cpu_to_be32(0x80000000); | |
261 | } | |
262 | } | |
263 | } | |
264 | } | |
265 | ||
310660a1 ED |
266 | INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
267 | struct mlx4_en_tx_ring *ring, | |
268 | int index, u64 timestamp, | |
269 | int napi_mode)); | |
c27a02cd | 270 | |
9ecc2d86 BB |
271 | u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, |
272 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 273 | int index, u64 timestamp, |
9ecc2d86 | 274 | int napi_mode) |
c27a02cd | 275 | { |
c27a02cd | 276 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
9573e0d3 | 277 | struct mlx4_en_tx_desc *tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd | 278 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; |
c27a02cd | 279 | void *end = ring->buf + ring->buf_size; |
3d03641c ED |
280 | struct sk_buff *skb = tx_info->skb; |
281 | int nr_maps = tx_info->nr_maps; | |
c27a02cd | 282 | int i; |
ec693d47 | 283 | |
29d40c90 ED |
284 | /* We do not touch skb here, so prefetch skb->users location |
285 | * to speedup consume_skb() | |
286 | */ | |
287 | prefetchw(&skb->users); | |
288 | ||
3d03641c ED |
289 | if (unlikely(timestamp)) { |
290 | struct skb_shared_hwtstamps hwts; | |
291 | ||
292 | mlx4_en_fill_hwtstamps(priv->mdev, &hwts, timestamp); | |
ec693d47 AV |
293 | skb_tstamp_tx(skb, &hwts); |
294 | } | |
c27a02cd | 295 | |
4c07c132 TT |
296 | if (!tx_info->inl) { |
297 | if (tx_info->linear) | |
298 | dma_unmap_single(priv->ddev, | |
299 | tx_info->map0_dma, | |
300 | tx_info->map0_byte_count, | |
eb9c5c0d | 301 | DMA_TO_DEVICE); |
4c07c132 TT |
302 | else |
303 | dma_unmap_page(priv->ddev, | |
304 | tx_info->map0_dma, | |
305 | tx_info->map0_byte_count, | |
eb9c5c0d | 306 | DMA_TO_DEVICE); |
4c07c132 TT |
307 | /* Optimize the common case when there are no wraparounds */ |
308 | if (likely((void *)tx_desc + | |
309 | (tx_info->nr_txbb << LOG_TXBB_SIZE) <= end)) { | |
3d03641c ED |
310 | for (i = 1; i < nr_maps; i++) { |
311 | data++; | |
ebf8c9aa | 312 | dma_unmap_page(priv->ddev, |
3d03641c ED |
313 | (dma_addr_t)be64_to_cpu(data->addr), |
314 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 315 | DMA_TO_DEVICE); |
41efea5a | 316 | } |
4c07c132 TT |
317 | } else { |
318 | if ((void *)data >= end) | |
43d620c8 | 319 | data = ring->buf + ((void *)data - end); |
c27a02cd | 320 | |
3d03641c ED |
321 | for (i = 1; i < nr_maps; i++) { |
322 | data++; | |
41efea5a YP |
323 | /* Check for wraparound before unmapping */ |
324 | if ((void *) data >= end) | |
43d620c8 | 325 | data = ring->buf; |
ebf8c9aa | 326 | dma_unmap_page(priv->ddev, |
3d03641c ED |
327 | (dma_addr_t)be64_to_cpu(data->addr), |
328 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 329 | DMA_TO_DEVICE); |
41efea5a | 330 | } |
c27a02cd | 331 | } |
c27a02cd | 332 | } |
b4a53379 JDB |
333 | napi_consume_skb(skb, napi_mode); |
334 | ||
c27a02cd YP |
335 | return tx_info->nr_txbb; |
336 | } | |
337 | ||
310660a1 ED |
338 | INDIRECT_CALLABLE_DECLARE(u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
339 | struct mlx4_en_tx_ring *ring, | |
340 | int index, u64 timestamp, | |
341 | int napi_mode)); | |
342 | ||
9ecc2d86 BB |
343 | u32 mlx4_en_recycle_tx_desc(struct mlx4_en_priv *priv, |
344 | struct mlx4_en_tx_ring *ring, | |
cf97050d | 345 | int index, u64 timestamp, |
9ecc2d86 BB |
346 | int napi_mode) |
347 | { | |
348 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
349 | struct mlx4_en_rx_alloc frame = { | |
350 | .page = tx_info->page, | |
351 | .dma = tx_info->map0_dma, | |
9ecc2d86 BB |
352 | }; |
353 | ||
b2b8a927 | 354 | if (!napi_mode || !mlx4_en_rx_recycle(ring->recycle_ring, &frame)) { |
9ecc2d86 | 355 | dma_unmap_page(priv->ddev, tx_info->map0_dma, |
69ba9431 | 356 | PAGE_SIZE, priv->dma_dir); |
9ecc2d86 BB |
357 | put_page(tx_info->page); |
358 | } | |
359 | ||
360 | return tx_info->nr_txbb; | |
361 | } | |
c27a02cd YP |
362 | |
363 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
364 | { | |
365 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
366 | int cnt = 0; | |
367 | ||
368 | /* Skip last polled descriptor */ | |
369 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 370 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
371 | ring->cons, ring->prod); |
372 | ||
373 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
374 | if (netif_msg_tx_err(priv)) | |
453a6082 | 375 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
376 | return 0; |
377 | } | |
378 | ||
379 | while (ring->cons != ring->prod) { | |
9ecc2d86 | 380 | ring->last_nr_txbb = ring->free_tx_desc(priv, ring, |
c27a02cd | 381 | ring->cons & ring->size_mask, |
cf97050d | 382 | 0, 0 /* Non-NAPI caller */); |
c27a02cd YP |
383 | ring->cons += ring->last_nr_txbb; |
384 | cnt++; | |
385 | } | |
386 | ||
67f8b1dc TT |
387 | if (ring->tx_queue) |
388 | netdev_tx_reset_queue(ring->tx_queue); | |
41b74920 | 389 | |
c27a02cd | 390 | if (cnt) |
453a6082 | 391 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
392 | |
393 | return cnt; | |
394 | } | |
395 | ||
ba603d9d MS |
396 | static void mlx4_en_handle_err_cqe(struct mlx4_en_priv *priv, struct mlx4_err_cqe *err_cqe, |
397 | u16 cqe_index, struct mlx4_en_tx_ring *ring) | |
398 | { | |
399 | struct mlx4_en_dev *mdev = priv->mdev; | |
400 | struct mlx4_en_tx_info *tx_info; | |
401 | struct mlx4_en_tx_desc *tx_desc; | |
402 | u16 wqe_index; | |
403 | int desc_size; | |
404 | ||
405 | en_err(priv, "CQE error - cqn 0x%x, ci 0x%x, vendor syndrome: 0x%x syndrome: 0x%x\n", | |
406 | ring->sp_cqn, cqe_index, err_cqe->vendor_err_syndrome, err_cqe->syndrome); | |
407 | print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe, sizeof(*err_cqe), | |
408 | false); | |
409 | ||
410 | wqe_index = be16_to_cpu(err_cqe->wqe_index) & ring->size_mask; | |
411 | tx_info = &ring->tx_info[wqe_index]; | |
412 | desc_size = tx_info->nr_txbb << LOG_TXBB_SIZE; | |
413 | en_err(priv, "Related WQE - qpn 0x%x, wqe index 0x%x, wqe size 0x%x\n", ring->qpn, | |
414 | wqe_index, desc_size); | |
415 | tx_desc = ring->buf + (wqe_index << LOG_TXBB_SIZE); | |
416 | print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, tx_desc, desc_size, false); | |
417 | ||
418 | if (test_and_set_bit(MLX4_EN_STATE_FLAG_RESTARTING, &priv->state)) | |
419 | return; | |
420 | ||
421 | en_err(priv, "Scheduling port restart\n"); | |
422 | queue_work(mdev->workqueue, &priv->restart_task); | |
423 | } | |
424 | ||
cf4058db ED |
425 | int mlx4_en_process_tx_cq(struct net_device *dev, |
426 | struct mlx4_en_cq *cq, int napi_budget) | |
c27a02cd YP |
427 | { |
428 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
429 | struct mlx4_cq *mcq = &cq->mcq; | |
67f8b1dc | 430 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->type][cq->ring]; |
f0ab34f0 | 431 | struct mlx4_cqe *cqe; |
cc26a490 | 432 | u16 index, ring_index, stamp_index; |
c27a02cd | 433 | u32 txbbs_skipped = 0; |
2d4b6466 | 434 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
435 | u32 cons_index = mcq->cons_index; |
436 | int size = cq->size; | |
437 | u32 size_mask = ring->size_mask; | |
438 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
439 | u32 packets = 0; |
440 | u32 bytes = 0; | |
08ff3235 | 441 | int factor = priv->cqe_factor; |
0276a330 | 442 | int done = 0; |
fbc6daf1 | 443 | int budget = priv->tx_work_limit; |
fb1843ee ED |
444 | u32 last_nr_txbb; |
445 | u32 ring_cons; | |
c27a02cd | 446 | |
cc26a490 | 447 | if (unlikely(!priv->port_up)) |
cf4058db | 448 | return 0; |
c27a02cd | 449 | |
53511453 ED |
450 | netdev_txq_bql_complete_prefetchw(ring->tx_queue); |
451 | ||
f0ab34f0 | 452 | index = cons_index & size_mask; |
b1b6b4da | 453 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
6aa7de05 MR |
454 | last_nr_txbb = READ_ONCE(ring->last_nr_txbb); |
455 | ring_cons = READ_ONCE(ring->cons); | |
fb1843ee | 456 | ring_index = ring_cons & size_mask; |
2d4b6466 | 457 | stamp_index = ring_index; |
f0ab34f0 YP |
458 | |
459 | /* Process all completed CQEs */ | |
460 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 461 | cons_index & size) && (done < budget)) { |
cc26a490 TT |
462 | u16 new_index; |
463 | ||
f0ab34f0 YP |
464 | /* |
465 | * make sure we read the CQE after we read the | |
466 | * ownership bit | |
467 | */ | |
12b3375f | 468 | dma_rmb(); |
f0ab34f0 | 469 | |
bd2f631d | 470 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
ba603d9d MS |
471 | MLX4_CQE_OPCODE_ERROR)) |
472 | if (!test_and_set_bit(MLX4_EN_TX_RING_STATE_RECOVERING, &ring->state)) | |
473 | mlx4_en_handle_err_cqe(priv, (struct mlx4_err_cqe *)cqe, index, | |
474 | ring); | |
bd2f631d | 475 | |
f0ab34f0 YP |
476 | /* Skip over last polled CQE */ |
477 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
478 | ||
c27a02cd | 479 | do { |
fc96256c ED |
480 | u64 timestamp = 0; |
481 | ||
fb1843ee ED |
482 | txbbs_skipped += last_nr_txbb; |
483 | ring_index = (ring_index + last_nr_txbb) & size_mask; | |
fc96256c ED |
484 | |
485 | if (unlikely(ring->tx_info[ring_index].ts_requested)) | |
ec693d47 AV |
486 | timestamp = mlx4_en_get_cqe_ts(cqe); |
487 | ||
f0ab34f0 | 488 | /* free next descriptor */ |
310660a1 ED |
489 | last_nr_txbb = INDIRECT_CALL_2(ring->free_tx_desc, |
490 | mlx4_en_free_tx_desc, | |
491 | mlx4_en_recycle_tx_desc, | |
f0ab34f0 | 492 | priv, ring, ring_index, |
cf97050d | 493 | timestamp, napi_budget); |
2d4b6466 EE |
494 | |
495 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
fb1843ee | 496 | !!((ring_cons + txbbs_stamp) & |
2d4b6466 EE |
497 | ring->size)); |
498 | stamp_index = ring_index; | |
499 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
500 | packets++; |
501 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 502 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
503 | |
504 | ++cons_index; | |
505 | index = cons_index & size_mask; | |
b1b6b4da | 506 | cqe = mlx4_en_get_cqe(buf, index, priv->cqe_size) + factor; |
f0ab34f0 | 507 | } |
c27a02cd | 508 | |
c27a02cd YP |
509 | /* |
510 | * To prevent CQ overflow we first update CQ consumer and only then | |
511 | * the ring consumer. | |
512 | */ | |
f0ab34f0 | 513 | mcq->cons_index = cons_index; |
c27a02cd YP |
514 | mlx4_cq_set_ci(mcq); |
515 | wmb(); | |
fb1843ee ED |
516 | |
517 | /* we want to dirty this cache line once */ | |
6aa7de05 MR |
518 | WRITE_ONCE(ring->last_nr_txbb, last_nr_txbb); |
519 | WRITE_ONCE(ring->cons, ring_cons + txbbs_skipped); | |
fb1843ee | 520 | |
cc26a490 | 521 | if (cq->type == TX_XDP) |
cf4058db | 522 | return done; |
9ecc2d86 | 523 | |
5b263f53 | 524 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 525 | |
488a9b48 | 526 | /* Wakeup Tx queue if this stopped, and ring is not full. |
c18520bd | 527 | */ |
488a9b48 IS |
528 | if (netif_tx_queue_stopped(ring->tx_queue) && |
529 | !mlx4_en_is_tx_ring_full(ring)) { | |
c18520bd | 530 | netif_tx_wake_queue(ring->tx_queue); |
15bffdff | 531 | ring->wake_queue++; |
c27a02cd | 532 | } |
cc26a490 | 533 | |
cf4058db | 534 | return done; |
c27a02cd YP |
535 | } |
536 | ||
537 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
538 | { | |
539 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
540 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 541 | |
477b35b4 ED |
542 | if (likely(priv->port_up)) |
543 | napi_schedule_irqoff(&cq->napi); | |
0276a330 EE |
544 | else |
545 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
546 | } |
547 | ||
0276a330 EE |
548 | /* TX CQ polling - called by NAPI */ |
549 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
550 | { | |
551 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
552 | struct net_device *dev = cq->dev; | |
553 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
cf4058db | 554 | int work_done; |
0276a330 | 555 | |
cf4058db ED |
556 | work_done = mlx4_en_process_tx_cq(dev, cq, budget); |
557 | if (work_done >= budget) | |
fbc6daf1 | 558 | return budget; |
0276a330 | 559 | |
cf4058db ED |
560 | if (napi_complete_done(napi, work_done)) |
561 | mlx4_en_arm_cq(priv, cq); | |
fbc6daf1 AV |
562 | |
563 | return 0; | |
0276a330 | 564 | } |
c27a02cd | 565 | |
c27a02cd YP |
566 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
567 | struct mlx4_en_tx_ring *ring, | |
568 | u32 index, | |
569 | unsigned int desc_size) | |
570 | { | |
9573e0d3 | 571 | u32 copy = (ring->size - index) << LOG_TXBB_SIZE; |
c27a02cd YP |
572 | int i; |
573 | ||
574 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
575 | if ((i & (TXBB_SIZE - 1)) == 0) | |
576 | wmb(); | |
577 | ||
578 | *((u32 *) (ring->buf + i)) = | |
579 | *((u32 *) (ring->bounce_buf + copy + i)); | |
580 | } | |
581 | ||
582 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
583 | if ((i & (TXBB_SIZE - 1)) == 0) | |
584 | wmb(); | |
585 | ||
9573e0d3 | 586 | *((u32 *)(ring->buf + (index << LOG_TXBB_SIZE) + i)) = |
c27a02cd YP |
587 | *((u32 *) (ring->bounce_buf + i)); |
588 | } | |
589 | ||
590 | /* Return real descriptor location */ | |
9573e0d3 | 591 | return ring->buf + (index << LOG_TXBB_SIZE); |
c27a02cd YP |
592 | } |
593 | ||
acea73d6 ED |
594 | /* Decide if skb can be inlined in tx descriptor to avoid dma mapping |
595 | * | |
596 | * It seems strange we do not simply use skb_copy_bits(). | |
597 | * This would allow to inline all skbs iff skb->len <= inline_thold | |
598 | * | |
599 | * Note that caller already checked skb was not a gso packet | |
600 | */ | |
7dfa4b41 | 601 | static bool is_inline(int inline_thold, const struct sk_buff *skb, |
b9d8839a | 602 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 603 | void **pfrag) |
c27a02cd YP |
604 | { |
605 | void *ptr; | |
606 | ||
acea73d6 ED |
607 | if (skb->len > inline_thold || !inline_thold) |
608 | return false; | |
c27a02cd | 609 | |
acea73d6 ED |
610 | if (shinfo->nr_frags == 1) { |
611 | ptr = skb_frag_address_safe(&shinfo->frags[0]); | |
612 | if (unlikely(!ptr)) | |
613 | return false; | |
614 | *pfrag = ptr; | |
615 | return true; | |
c27a02cd | 616 | } |
acea73d6 ED |
617 | if (shinfo->nr_frags) |
618 | return false; | |
619 | return true; | |
c27a02cd YP |
620 | } |
621 | ||
7dfa4b41 | 622 | static int inline_size(const struct sk_buff *skb) |
c27a02cd YP |
623 | { |
624 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
625 | <= MLX4_INLINE_ALIGN) | |
626 | return ALIGN(skb->len + CTRL_SIZE + | |
627 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
628 | else | |
629 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
630 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
631 | } | |
632 | ||
7dfa4b41 | 633 | static int get_real_size(const struct sk_buff *skb, |
b9d8839a | 634 | const struct skb_shared_info *shinfo, |
7dfa4b41 | 635 | struct net_device *dev, |
acea73d6 ED |
636 | int *lso_header_size, |
637 | bool *inline_ok, | |
1169a642 ED |
638 | void **pfrag, |
639 | int *hopbyhop) | |
c27a02cd YP |
640 | { |
641 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
642 | int real_size; |
643 | ||
b9d8839a | 644 | if (shinfo->gso_size) { |
acea73d6 | 645 | *inline_ok = false; |
1169a642 ED |
646 | *hopbyhop = 0; |
647 | if (skb->encapsulation) { | |
504148fe | 648 | *lso_header_size = skb_inner_tcp_all_headers(skb); |
1169a642 ED |
649 | } else { |
650 | /* Detects large IPV6 TCP packets and prepares for removal of | |
651 | * HBH header that has been pushed by ip6_xmit(), | |
652 | * mainly so that tcpdump can dissect them. | |
653 | */ | |
654 | if (ipv6_has_hopopt_jumbo(skb)) | |
655 | *hopbyhop = sizeof(struct hop_jumbo_hdr); | |
504148fe | 656 | *lso_header_size = skb_tcp_all_headers(skb); |
1169a642 | 657 | } |
b9d8839a | 658 | real_size = CTRL_SIZE + shinfo->nr_frags * DS_SIZE + |
1169a642 | 659 | ALIGN(*lso_header_size - *hopbyhop + 4, DS_SIZE); |
c27a02cd YP |
660 | if (unlikely(*lso_header_size != skb_headlen(skb))) { |
661 | /* We add a segment for the skb linear buffer only if | |
662 | * it contains data */ | |
663 | if (*lso_header_size < skb_headlen(skb)) | |
664 | real_size += DS_SIZE; | |
665 | else { | |
666 | if (netif_msg_tx_err(priv)) | |
453a6082 | 667 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
668 | return 0; |
669 | } | |
670 | } | |
c27a02cd YP |
671 | } else { |
672 | *lso_header_size = 0; | |
acea73d6 ED |
673 | *inline_ok = is_inline(priv->prof->inline_thold, skb, |
674 | shinfo, pfrag); | |
675 | ||
676 | if (*inline_ok) | |
c27a02cd | 677 | real_size = inline_size(skb); |
acea73d6 ED |
678 | else |
679 | real_size = CTRL_SIZE + | |
680 | (shinfo->nr_frags + 1) * DS_SIZE; | |
c27a02cd YP |
681 | } |
682 | ||
683 | return real_size; | |
684 | } | |
685 | ||
7dfa4b41 ED |
686 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, |
687 | const struct sk_buff *skb, | |
b9d8839a | 688 | const struct skb_shared_info *shinfo, |
224e92e0 | 689 | void *fragptr) |
c27a02cd YP |
690 | { |
691 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
31975e27 | 692 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof(*inl); |
e533ac7e | 693 | unsigned int hlen = skb_headlen(skb); |
c27a02cd YP |
694 | |
695 | if (skb->len <= spc) { | |
93591aaa EE |
696 | if (likely(skb->len >= MIN_PKT_LEN)) { |
697 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
698 | } else { | |
699 | inl->byte_count = cpu_to_be32(1 << 31 | MIN_PKT_LEN); | |
700 | memset(((void *)(inl + 1)) + skb->len, 0, | |
701 | MIN_PKT_LEN - skb->len); | |
702 | } | |
e533ac7e | 703 | skb_copy_from_linear_data(skb, inl + 1, hlen); |
b9d8839a | 704 | if (shinfo->nr_frags) |
e533ac7e | 705 | memcpy(((void *)(inl + 1)) + hlen, fragptr, |
b9d8839a | 706 | skb_frag_size(&shinfo->frags[0])); |
c27a02cd YP |
707 | |
708 | } else { | |
709 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
e533ac7e ED |
710 | if (hlen <= spc) { |
711 | skb_copy_from_linear_data(skb, inl + 1, hlen); | |
712 | if (hlen < spc) { | |
713 | memcpy(((void *)(inl + 1)) + hlen, | |
714 | fragptr, spc - hlen); | |
715 | fragptr += spc - hlen; | |
c27a02cd YP |
716 | } |
717 | inl = (void *) (inl + 1) + spc; | |
718 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
719 | } else { | |
720 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
721 | inl = (void *) (inl + 1) + spc; | |
722 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
e533ac7e | 723 | hlen - spc); |
b9d8839a | 724 | if (shinfo->nr_frags) |
e533ac7e | 725 | memcpy(((void *)(inl + 1)) + hlen - spc, |
b9d8839a ED |
726 | fragptr, |
727 | skb_frag_size(&shinfo->frags[0])); | |
c27a02cd YP |
728 | } |
729 | ||
12b3375f | 730 | dma_wmb(); |
c27a02cd YP |
731 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); |
732 | } | |
c27a02cd YP |
733 | } |
734 | ||
f663dd9a | 735 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
a350ecce | 736 | struct net_device *sb_dev) |
c27a02cd | 737 | { |
bc6a4744 | 738 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 739 | u16 rings_p_up = priv->num_tx_rings_p_up; |
c27a02cd | 740 | |
4b5e5b7e | 741 | if (netdev_get_num_tc(dev)) |
a350ecce | 742 | return netdev_pick_tx(dev, skb, NULL); |
bc6a4744 | 743 | |
a350ecce | 744 | return netdev_pick_tx(dev, skb, NULL) % rings_p_up; |
c27a02cd YP |
745 | } |
746 | ||
7dfa4b41 ED |
747 | static void mlx4_bf_copy(void __iomem *dst, const void *src, |
748 | unsigned int bytecnt) | |
87a5c389 YP |
749 | { |
750 | __iowrite64_copy(dst, src, bytecnt / 8); | |
751 | } | |
752 | ||
224e92e0 BB |
753 | void mlx4_en_xmit_doorbell(struct mlx4_en_tx_ring *ring) |
754 | { | |
755 | wmb(); | |
756 | /* Since there is no iowrite*_native() that writes the | |
757 | * value as is, without byteswapping - using the one | |
758 | * the doesn't do byteswapping in the relevant arch | |
759 | * endianness. | |
760 | */ | |
761 | #if defined(__LITTLE_ENDIAN) | |
762 | iowrite32( | |
763 | #else | |
764 | iowrite32be( | |
765 | #endif | |
9ac93627 | 766 | (__force u32)ring->doorbell_qpn, ring->doorbell_address); |
224e92e0 BB |
767 | } |
768 | ||
769 | static void mlx4_en_tx_write_desc(struct mlx4_en_tx_ring *ring, | |
770 | struct mlx4_en_tx_desc *tx_desc, | |
771 | union mlx4_wqe_qpn_vlan qpn_vlan, | |
772 | int desc_size, int bf_index, | |
773 | __be32 op_own, bool bf_ok, | |
774 | bool send_doorbell) | |
775 | { | |
776 | tx_desc->ctrl.qpn_vlan = qpn_vlan; | |
777 | ||
778 | if (bf_ok) { | |
779 | op_own |= htonl((bf_index & 0xffff) << 8); | |
780 | /* Ensure new descriptor hits memory | |
781 | * before setting ownership of this descriptor to HW | |
782 | */ | |
783 | dma_wmb(); | |
784 | tx_desc->ctrl.owner_opcode = op_own; | |
785 | ||
786 | wmb(); | |
787 | ||
788 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, &tx_desc->ctrl, | |
789 | desc_size); | |
790 | ||
791 | wmb(); | |
792 | ||
793 | ring->bf.offset ^= ring->bf.buf_size; | |
794 | } else { | |
795 | /* Ensure new descriptor hits memory | |
796 | * before setting ownership of this descriptor to HW | |
797 | */ | |
798 | dma_wmb(); | |
799 | tx_desc->ctrl.owner_opcode = op_own; | |
800 | if (send_doorbell) | |
801 | mlx4_en_xmit_doorbell(ring); | |
802 | else | |
803 | ring->xmit_more++; | |
804 | } | |
805 | } | |
806 | ||
f28186d6 TT |
807 | static bool mlx4_en_build_dma_wqe(struct mlx4_en_priv *priv, |
808 | struct skb_shared_info *shinfo, | |
809 | struct mlx4_wqe_data_seg *data, | |
810 | struct sk_buff *skb, | |
811 | int lso_header_size, | |
812 | __be32 mr_key, | |
813 | struct mlx4_en_tx_info *tx_info) | |
814 | { | |
815 | struct device *ddev = priv->ddev; | |
816 | dma_addr_t dma = 0; | |
817 | u32 byte_count = 0; | |
818 | int i_frag; | |
819 | ||
820 | /* Map fragments if any */ | |
821 | for (i_frag = shinfo->nr_frags - 1; i_frag >= 0; i_frag--) { | |
d7840976 | 822 | const skb_frag_t *frag = &shinfo->frags[i_frag]; |
f28186d6 TT |
823 | byte_count = skb_frag_size(frag); |
824 | dma = skb_frag_dma_map(ddev, frag, | |
825 | 0, byte_count, | |
826 | DMA_TO_DEVICE); | |
827 | if (dma_mapping_error(ddev, dma)) | |
828 | goto tx_drop_unmap; | |
829 | ||
830 | data->addr = cpu_to_be64(dma); | |
831 | data->lkey = mr_key; | |
832 | dma_wmb(); | |
833 | data->byte_count = cpu_to_be32(byte_count); | |
834 | --data; | |
835 | } | |
836 | ||
837 | /* Map linear part if needed */ | |
838 | if (tx_info->linear) { | |
839 | byte_count = skb_headlen(skb) - lso_header_size; | |
840 | ||
841 | dma = dma_map_single(ddev, skb->data + | |
842 | lso_header_size, byte_count, | |
eb9c5c0d | 843 | DMA_TO_DEVICE); |
f28186d6 TT |
844 | if (dma_mapping_error(ddev, dma)) |
845 | goto tx_drop_unmap; | |
846 | ||
847 | data->addr = cpu_to_be64(dma); | |
848 | data->lkey = mr_key; | |
849 | dma_wmb(); | |
850 | data->byte_count = cpu_to_be32(byte_count); | |
851 | } | |
852 | /* tx completion can avoid cache line miss for common cases */ | |
853 | tx_info->map0_dma = dma; | |
854 | tx_info->map0_byte_count = byte_count; | |
855 | ||
856 | return true; | |
857 | ||
858 | tx_drop_unmap: | |
859 | en_err(priv, "DMA mapping error\n"); | |
860 | ||
861 | while (++i_frag < shinfo->nr_frags) { | |
862 | ++data; | |
863 | dma_unmap_page(ddev, (dma_addr_t)be64_to_cpu(data->addr), | |
864 | be32_to_cpu(data->byte_count), | |
eb9c5c0d | 865 | DMA_TO_DEVICE); |
f28186d6 TT |
866 | } |
867 | ||
868 | return false; | |
869 | } | |
870 | ||
61357325 | 871 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd | 872 | { |
b9d8839a | 873 | struct skb_shared_info *shinfo = skb_shinfo(skb); |
c27a02cd | 874 | struct mlx4_en_priv *priv = netdev_priv(dev); |
224e92e0 | 875 | union mlx4_wqe_qpn_vlan qpn_vlan = {}; |
c27a02cd | 876 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
877 | struct mlx4_en_tx_desc *tx_desc; |
878 | struct mlx4_wqe_data_seg *data; | |
c27a02cd | 879 | struct mlx4_en_tx_info *tx_info; |
7c8c0291 | 880 | u32 __maybe_unused ring_cons; |
f28186d6 | 881 | int tx_ind; |
c27a02cd YP |
882 | int nr_txbb; |
883 | int desc_size; | |
884 | int real_size; | |
87a5c389 | 885 | u32 index, bf_index; |
1169a642 | 886 | struct ipv6hdr *h6; |
c27a02cd | 887 | __be32 op_own; |
c27a02cd | 888 | int lso_header_size; |
acea73d6 | 889 | void *fragptr = NULL; |
87a5c389 | 890 | bool bounce = false; |
5804283d | 891 | bool send_doorbell; |
fe971b95 | 892 | bool stop_queue; |
acea73d6 | 893 | bool inline_ok; |
f28186d6 | 894 | u8 data_offset; |
1169a642 | 895 | int hopbyhop; |
224e92e0 | 896 | bool bf_ok; |
c27a02cd | 897 | |
f905c79e | 898 | tx_ind = skb_get_queue_mapping(skb); |
67f8b1dc | 899 | ring = priv->tx_ring[TX][tx_ind]; |
f905c79e | 900 | |
f28186d6 | 901 | if (unlikely(!priv->port_up)) |
63a664b7 ED |
902 | goto tx_drop; |
903 | ||
acea73d6 | 904 | real_size = get_real_size(skb, shinfo, dev, &lso_header_size, |
1169a642 | 905 | &inline_ok, &fragptr, &hopbyhop); |
c27a02cd | 906 | if (unlikely(!real_size)) |
7a61fc86 | 907 | goto tx_drop_count; |
c27a02cd | 908 | |
25985edc | 909 | /* Align descriptor to TXBB size */ |
c27a02cd | 910 | desc_size = ALIGN(real_size, TXBB_SIZE); |
9573e0d3 | 911 | nr_txbb = desc_size >> LOG_TXBB_SIZE; |
c27a02cd YP |
912 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { |
913 | if (netif_msg_tx_err(priv)) | |
453a6082 | 914 | en_warn(priv, "Oversized header or SG list\n"); |
7a61fc86 | 915 | goto tx_drop_count; |
c27a02cd YP |
916 | } |
917 | ||
224e92e0 | 918 | bf_ok = ring->bf_enabled; |
e38af4fa | 919 | if (skb_vlan_tag_present(skb)) { |
f28186d6 TT |
920 | u16 vlan_proto; |
921 | ||
224e92e0 | 922 | qpn_vlan.vlan_tag = cpu_to_be16(skb_vlan_tag_get(skb)); |
e38af4fa | 923 | vlan_proto = be16_to_cpu(skb->vlan_proto); |
224e92e0 BB |
924 | if (vlan_proto == ETH_P_8021AD) |
925 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_SVLAN; | |
926 | else if (vlan_proto == ETH_P_8021Q) | |
927 | qpn_vlan.ins_vlan = MLX4_WQE_CTRL_INS_CVLAN; | |
928 | else | |
929 | qpn_vlan.ins_vlan = 0; | |
930 | bf_ok = false; | |
e38af4fa | 931 | } |
c27a02cd | 932 | |
53511453 | 933 | netdev_txq_bql_enqueue_prefetchw(ring->tx_queue); |
29d40c90 | 934 | |
c27a02cd YP |
935 | /* Packet is good - grab an index and transmit it */ |
936 | index = ring->prod & ring->size_mask; | |
87a5c389 | 937 | bf_index = ring->prod; |
c27a02cd YP |
938 | |
939 | /* See if we have enough space for whole descriptor TXBB for setting | |
940 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
941 | if (likely(index + nr_txbb <= ring->size)) | |
9573e0d3 | 942 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
87a5c389 | 943 | else { |
c27a02cd | 944 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 | 945 | bounce = true; |
224e92e0 | 946 | bf_ok = false; |
87a5c389 | 947 | } |
c27a02cd YP |
948 | |
949 | /* Save skb in tx_info ring */ | |
950 | tx_info = &ring->tx_info[index]; | |
951 | tx_info->skb = skb; | |
952 | tx_info->nr_txbb = nr_txbb; | |
953 | ||
f28186d6 TT |
954 | if (!lso_header_size) { |
955 | data = &tx_desc->data; | |
956 | data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
957 | } else { | |
1169a642 | 958 | int lso_align = ALIGN(lso_header_size - hopbyhop + 4, DS_SIZE); |
f28186d6 TT |
959 | |
960 | data = (void *)&tx_desc->lso + lso_align; | |
961 | data_offset = offsetof(struct mlx4_en_tx_desc, lso) + lso_align; | |
962 | } | |
237a3a3b AV |
963 | |
964 | /* valid only for none inline segments */ | |
f28186d6 | 965 | tx_info->data_offset = data_offset; |
237a3a3b | 966 | |
acea73d6 ED |
967 | tx_info->inl = inline_ok; |
968 | ||
f28186d6 | 969 | tx_info->linear = lso_header_size < skb_headlen(skb) && !inline_ok; |
237a3a3b | 970 | |
b9d8839a | 971 | tx_info->nr_maps = shinfo->nr_frags + tx_info->linear; |
3d03641c | 972 | data += tx_info->nr_maps - 1; |
237a3a3b | 973 | |
f28186d6 TT |
974 | if (!tx_info->inl) |
975 | if (!mlx4_en_build_dma_wqe(priv, shinfo, data, skb, | |
976 | lso_header_size, ring->mr_key, | |
977 | tx_info)) | |
978 | goto tx_drop_count; | |
237a3a3b | 979 | |
ec693d47 AV |
980 | /* |
981 | * For timestamping add flag to skb_shinfo and | |
982 | * set flag for further reference | |
983 | */ | |
e70602a8 | 984 | tx_info->ts_requested = 0; |
7dfa4b41 ED |
985 | if (unlikely(ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && |
986 | shinfo->tx_flags & SKBTX_HW_TSTAMP)) { | |
987 | shinfo->tx_flags |= SKBTX_IN_PROGRESS; | |
ec693d47 AV |
988 | tx_info->ts_requested = 1; |
989 | } | |
990 | ||
c27a02cd YP |
991 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
992 | * whether LSO is used */ | |
60d6fe99 | 993 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd | 994 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
a4f2dacb OG |
995 | if (!skb->encapsulation) |
996 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
997 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
998 | else | |
999 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM); | |
ad04378c | 1000 | ring->tx_csum++; |
c27a02cd YP |
1001 | } |
1002 | ||
79aeaccd | 1003 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
1004 | struct ethhdr *ethh; |
1005 | ||
213815a1 YB |
1006 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
1007 | * so that VFs and PF can communicate with each other | |
1008 | */ | |
1009 | ethh = (struct ethhdr *)skb->data; | |
1010 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
1011 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
1012 | } | |
1013 | ||
c27a02cd YP |
1014 | /* Handle LSO (TSO) packets */ |
1015 | if (lso_header_size) { | |
b9d8839a ED |
1016 | int i; |
1017 | ||
c27a02cd YP |
1018 | /* Mark opcode as LSO */ |
1019 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
1020 | ((ring->prod & ring->size) ? | |
1021 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1022 | ||
1169a642 | 1023 | lso_header_size -= hopbyhop; |
c27a02cd YP |
1024 | /* Fill in the LSO prefix */ |
1025 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
b9d8839a | 1026 | shinfo->gso_size << 16 | lso_header_size); |
c27a02cd | 1027 | |
c27a02cd | 1028 | |
1169a642 ED |
1029 | if (unlikely(hopbyhop)) { |
1030 | /* remove the HBH header. | |
1031 | * Layout: [Ethernet header][IPv6 header][HBH][TCP header] | |
1032 | */ | |
1033 | memcpy(tx_desc->lso.header, skb->data, ETH_HLEN + sizeof(*h6)); | |
1034 | h6 = (struct ipv6hdr *)((char *)tx_desc->lso.header + ETH_HLEN); | |
1035 | h6->nexthdr = IPPROTO_TCP; | |
1036 | /* Copy the TCP header after the IPv6 one */ | |
1037 | memcpy(h6 + 1, | |
1038 | skb->data + ETH_HLEN + sizeof(*h6) + | |
1039 | sizeof(struct hop_jumbo_hdr), | |
1040 | tcp_hdrlen(skb)); | |
1041 | /* Leave ipv6 payload_len set to 0, as LSO v2 specs request. */ | |
1042 | } else { | |
1043 | /* Copy headers; | |
1044 | * note that we already verified that it is linear | |
1045 | */ | |
1046 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
1047 | } | |
9fab426d | 1048 | ring->tso_packets++; |
b9d8839a | 1049 | |
75d04aa3 | 1050 | i = shinfo->gso_segs; |
5b263f53 | 1051 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
1052 | ring->packets += i; |
1053 | } else { | |
1054 | /* Normal (Non LSO) packet */ | |
1055 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1056 | ((ring->prod & ring->size) ? | |
1057 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 1058 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd | 1059 | ring->packets++; |
c27a02cd | 1060 | } |
5b263f53 | 1061 | ring->bytes += tx_info->nr_bytes; |
c27a02cd | 1062 | |
acea73d6 | 1063 | if (tx_info->inl) |
224e92e0 | 1064 | build_inline_wqe(tx_desc, skb, shinfo, fragptr); |
c27a02cd | 1065 | |
837052d0 | 1066 | if (skb->encapsulation) { |
09067122 AD |
1067 | union { |
1068 | struct iphdr *v4; | |
1069 | struct ipv6hdr *v6; | |
1070 | unsigned char *hdr; | |
1071 | } ip; | |
1072 | u8 proto; | |
1073 | ||
1074 | ip.hdr = skb_inner_network_header(skb); | |
1075 | proto = (ip.v4->version == 4) ? ip.v4->protocol : | |
1076 | ip.v6->nexthdr; | |
1077 | ||
1078 | if (proto == IPPROTO_TCP || proto == IPPROTO_UDP) | |
837052d0 OG |
1079 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); |
1080 | else | |
1081 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
1082 | } | |
1083 | ||
c27a02cd YP |
1084 | ring->prod += nr_txbb; |
1085 | ||
1086 | /* If we used a bounce buffer then copy descriptor back into place */ | |
7dfa4b41 | 1087 | if (unlikely(bounce)) |
c27a02cd YP |
1088 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
1089 | ||
eb0cabbd AV |
1090 | skb_tx_timestamp(skb); |
1091 | ||
fe971b95 | 1092 | /* Check available TXBBs And 2K spare for prefetch */ |
488a9b48 | 1093 | stop_queue = mlx4_en_is_tx_ring_full(ring); |
fe971b95 ED |
1094 | if (unlikely(stop_queue)) { |
1095 | netif_tx_stop_queue(ring->tx_queue); | |
1096 | ring->queue_stopped++; | |
1097 | } | |
c2973444 ED |
1098 | |
1099 | send_doorbell = __netdev_tx_sent_queue(ring->tx_queue, | |
1100 | tx_info->nr_bytes, | |
3c31ff22 | 1101 | netdev_xmit_more()); |
5804283d | 1102 | |
6a4e8121 ED |
1103 | real_size = (real_size / 16) & 0x3f; |
1104 | ||
224e92e0 | 1105 | bf_ok &= desc_size <= MAX_BF && send_doorbell; |
e38af4fa | 1106 | |
224e92e0 BB |
1107 | if (bf_ok) |
1108 | qpn_vlan.bf_qpn = ring->doorbell_qpn | cpu_to_be32(real_size); | |
1109 | else | |
1110 | qpn_vlan.fence_size = real_size; | |
7dfa4b41 | 1111 | |
224e92e0 BB |
1112 | mlx4_en_tx_write_desc(ring, tx_desc, qpn_vlan, desc_size, bf_index, |
1113 | op_own, bf_ok, send_doorbell); | |
c27a02cd | 1114 | |
fe971b95 ED |
1115 | if (unlikely(stop_queue)) { |
1116 | /* If queue was emptied after the if (stop_queue) , and before | |
1117 | * the netif_tx_stop_queue() - need to wake the queue, | |
1118 | * or else it will remain stopped forever. | |
1119 | * Need a memory barrier to make sure ring->cons was not | |
1120 | * updated before queue was stopped. | |
1121 | */ | |
1122 | smp_rmb(); | |
1123 | ||
488a9b48 | 1124 | if (unlikely(!mlx4_en_is_tx_ring_full(ring))) { |
fe971b95 ED |
1125 | netif_tx_wake_queue(ring->tx_queue); |
1126 | ring->wake_queue++; | |
1127 | } | |
1128 | } | |
ec634fe3 | 1129 | return NETDEV_TX_OK; |
7e230913 | 1130 | |
7a61fc86 MS |
1131 | tx_drop_count: |
1132 | ring->tx_dropped++; | |
7e230913 YP |
1133 | tx_drop: |
1134 | dev_kfree_skb_any(skb); | |
7e230913 | 1135 | return NETDEV_TX_OK; |
c27a02cd YP |
1136 | } |
1137 | ||
36ea7964 TT |
1138 | #define MLX4_EN_XDP_TX_NRTXBB 1 |
1139 | #define MLX4_EN_XDP_TX_REAL_SZ (((CTRL_SIZE + MLX4_EN_XDP_TX_NRTXBB * DS_SIZE) \ | |
1140 | / 16) & 0x3f) | |
1141 | ||
f025fd60 TT |
1142 | void mlx4_en_init_tx_xdp_ring_descs(struct mlx4_en_priv *priv, |
1143 | struct mlx4_en_tx_ring *ring) | |
1144 | { | |
1145 | int i; | |
1146 | ||
1147 | for (i = 0; i < ring->size; i++) { | |
1148 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[i]; | |
1149 | struct mlx4_en_tx_desc *tx_desc = ring->buf + | |
1150 | (i << LOG_TXBB_SIZE); | |
1151 | ||
1152 | tx_info->map0_byte_count = PAGE_SIZE; | |
1153 | tx_info->nr_txbb = MLX4_EN_XDP_TX_NRTXBB; | |
1154 | tx_info->data_offset = offsetof(struct mlx4_en_tx_desc, data); | |
1155 | tx_info->ts_requested = 0; | |
1156 | tx_info->nr_maps = 1; | |
1157 | tx_info->linear = 1; | |
1158 | tx_info->inl = 0; | |
1159 | ||
1160 | tx_desc->data.lkey = ring->mr_key; | |
1161 | tx_desc->ctrl.qpn_vlan.fence_size = MLX4_EN_XDP_TX_REAL_SZ; | |
1162 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; | |
1163 | } | |
1164 | } | |
1165 | ||
15fca2c8 TT |
1166 | netdev_tx_t mlx4_en_xmit_frame(struct mlx4_en_rx_ring *rx_ring, |
1167 | struct mlx4_en_rx_alloc *frame, | |
5dad61b8 | 1168 | struct mlx4_en_priv *priv, unsigned int length, |
36ea7964 | 1169 | int tx_ind, bool *doorbell_pending) |
9ecc2d86 | 1170 | { |
9ecc2d86 | 1171 | struct mlx4_en_tx_desc *tx_desc; |
9ecc2d86 | 1172 | struct mlx4_en_tx_info *tx_info; |
36ea7964 TT |
1173 | struct mlx4_wqe_data_seg *data; |
1174 | struct mlx4_en_tx_ring *ring; | |
9ecc2d86 | 1175 | dma_addr_t dma; |
9ecc2d86 | 1176 | __be32 op_own; |
36ea7964 | 1177 | int index; |
9ecc2d86 | 1178 | |
36ea7964 TT |
1179 | if (unlikely(!priv->port_up)) |
1180 | goto tx_drop; | |
9ecc2d86 | 1181 | |
67f8b1dc | 1182 | ring = priv->tx_ring[TX_XDP][tx_ind]; |
9ecc2d86 | 1183 | |
36ea7964 | 1184 | if (unlikely(mlx4_en_is_tx_ring_full(ring))) |
7a61fc86 | 1185 | goto tx_drop_count; |
9ecc2d86 | 1186 | |
9ecc2d86 BB |
1187 | index = ring->prod & ring->size_mask; |
1188 | tx_info = &ring->tx_info[index]; | |
1189 | ||
9573e0d3 | 1190 | tx_desc = ring->buf + (index << LOG_TXBB_SIZE); |
9ecc2d86 BB |
1191 | data = &tx_desc->data; |
1192 | ||
1193 | dma = frame->dma; | |
1194 | ||
1195 | tx_info->page = frame->page; | |
1196 | frame->page = NULL; | |
1197 | tx_info->map0_dma = dma; | |
9ecc2d86 | 1198 | tx_info->nr_bytes = max_t(unsigned int, length, ETH_ZLEN); |
9ecc2d86 | 1199 | |
ea3349a0 | 1200 | dma_sync_single_range_for_device(priv->ddev, dma, frame->page_offset, |
eb9c5c0d | 1201 | length, DMA_TO_DEVICE); |
9ecc2d86 | 1202 | |
ea3349a0 | 1203 | data->addr = cpu_to_be64(dma + frame->page_offset); |
9ecc2d86 BB |
1204 | dma_wmb(); |
1205 | data->byte_count = cpu_to_be32(length); | |
1206 | ||
1207 | /* tx completion can avoid cache line miss for common cases */ | |
9ecc2d86 BB |
1208 | |
1209 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
1210 | ((ring->prod & ring->size) ? | |
1211 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
1212 | ||
15fca2c8 | 1213 | rx_ring->xdp_tx++; |
9ecc2d86 | 1214 | |
36ea7964 | 1215 | ring->prod += MLX4_EN_XDP_TX_NRTXBB; |
9ecc2d86 | 1216 | |
f6f0aa97 TT |
1217 | /* Ensure new descriptor hits memory |
1218 | * before setting ownership of this descriptor to HW | |
1219 | */ | |
1220 | dma_wmb(); | |
1221 | tx_desc->ctrl.owner_opcode = op_own; | |
1222 | ring->xmit_more++; | |
9ecc2d86 | 1223 | |
36ea7964 | 1224 | *doorbell_pending = true; |
9ecc2d86 BB |
1225 | |
1226 | return NETDEV_TX_OK; | |
1227 | ||
7a61fc86 | 1228 | tx_drop_count: |
15fca2c8 | 1229 | rx_ring->xdp_tx_full++; |
6c78511b | 1230 | *doorbell_pending = true; |
7a61fc86 | 1231 | tx_drop: |
9ecc2d86 BB |
1232 | return NETDEV_TX_BUSY; |
1233 | } |