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Merge tag 'amlogic-dt-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman...
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
47a38e15 34#include <linux/bpf.h>
c27a02cd
YP		 35#include <linux/etherdevice.h>
36#include <linux/tcp.h>
37#include <linux/if_vlan.h>
38#include <linux/delay.h>
5a0e3ad6 39#include <linux/slab.h>
1eb8c695
AV		 40#include <linux/hash.h>
41#include <net/ip.h>
076bb0c8 42#include <net/busy_poll.h>
1b136de1 43#include <net/vxlan.h>
09d4d087 44#include <net/devlink.h>
c27a02cd
YP		 45
46#include <linux/mlx4/driver.h>
47#include <linux/mlx4/device.h>
48#include <linux/mlx4/cmd.h>
49#include <linux/mlx4/cq.h>
50
51#include "mlx4_en.h"
52#include "en_port.h"
53
ea3349a0
MKL		 54#define MLX4_EN_MAX_XDP_MTU ((int)(PAGE_SIZE - ETH_HLEN - (2 * VLAN_HLEN) - \
55 XDP_PACKET_HEADROOM))
b45f0674 56
d317966b 57int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 58{
bc6a4744
AV		 59 struct mlx4_en_priv *priv = netdev_priv(dev);
60 int i;
d317966b 61 unsigned int offset = 0;
bc6a4744 62
f21ad614 63 if (up && up != MLX4_EN_NUM_UP_HIGH)
897d7846
AV		 64 return -EINVAL;
65
bc6a4744 66 netdev_set_num_tc(dev, up);
ec327f7a 67 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
bc6a4744 68 /* Partition Tx queues evenly amongst UP's */
bc6a4744 69 for (i = 0; i < up; i++) {
d317966b
AV		 70 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
71 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 72 }
73
af7d5185
RS		 74#ifdef CONFIG_MLX4_EN_DCB
75 if (!mlx4_is_slave(priv->mdev->dev)) {
76 if (up) {
564ed9b1
TT		 77 if (priv->dcbx_cap)
78 priv->flags |= MLX4_EN_FLAG_DCB_ENABLED;
af7d5185
RS		 79 } else {
80 priv->flags &= ~MLX4_EN_FLAG_DCB_ENABLED;
564ed9b1 81 priv->cee_config.pfc_state = false;
af7d5185
RS		 82 }
83 }
84#endif /* CONFIG_MLX4_EN_DCB */
85
897d7846
AV		 86 return 0;
87}
88
ec327f7a
IK		 89int mlx4_en_alloc_tx_queue_per_tc(struct net_device *dev, u8 tc)
90{
91 struct mlx4_en_priv *priv = netdev_priv(dev);
92 struct mlx4_en_dev *mdev = priv->mdev;
93 struct mlx4_en_port_profile new_prof;
94 struct mlx4_en_priv *tmp;
95 int port_up = 0;
96 int err = 0;
97
98 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
99 if (!tmp)
100 return -ENOMEM;
101
102 mutex_lock(&mdev->state_lock);
103 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
104 new_prof.num_up = (tc == 0) ? MLX4_EN_NUM_UP_LOW :
105 MLX4_EN_NUM_UP_HIGH;
106 new_prof.tx_ring_num[TX] = new_prof.num_tx_rings_p_up *
107 new_prof.num_up;
108 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
109 if (err)
110 goto out;
111
112 if (priv->port_up) {
113 port_up = 1;
114 mlx4_en_stop_port(dev, 1);
115 }
116
117 mlx4_en_safe_replace_resources(priv, tmp);
118 if (port_up) {
119 err = mlx4_en_start_port(dev);
120 if (err) {
121 en_err(priv, "Failed starting port for setup TC\n");
122 goto out;
123 }
124 }
125
126 err = mlx4_en_setup_tc(dev, tc);
127out:
128 mutex_unlock(&mdev->state_lock);
129 kfree(tmp);
130 return err;
131}
132
2572ac53 133static int __mlx4_en_setup_tc(struct net_device *dev, enum tc_setup_type type,
de4784ca 134 void *type_data)
e4c6734e 135{
de4784ca
JP		 136 struct tc_mqprio_qopt *mqprio = type_data;
137
575ed7d3 138 if (type != TC_SETUP_QDISC_MQPRIO)
38cf0426 139 return -EOPNOTSUPP;
e4c6734e 140
de4784ca 141 if (mqprio->num_tc && mqprio->num_tc != MLX4_EN_NUM_UP_HIGH)
ec327f7a
IK		 142 return -EINVAL;
143
de4784ca 144 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
56f36acd 145
de4784ca 146 return mlx4_en_alloc_tx_queue_per_tc(dev, mqprio->num_tc);
e4c6734e
JF		 147}
148
1eb8c695
AV		 149#ifdef CONFIG_RFS_ACCEL
150
151struct mlx4_en_filter {
152 struct list_head next;
153 struct work_struct work;
154
75a353d4 155 u8 ip_proto;
1eb8c695
AV		 156 __be32 src_ip;
157 __be32 dst_ip;
158 __be16 src_port;
159 __be16 dst_port;
160
161 int rxq_index;
162 struct mlx4_en_priv *priv;
163 u32 flow_id; /* RFS infrastructure id */
164 int id; /* mlx4_en driver id */
165 u64 reg_id; /* Flow steering API id */
166 u8 activated; /* Used to prevent expiry before filter
167 * is attached
168 */
169 struct hlist_node filter_chain;
170};
171
172static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
173
75a353d4
EP		 174static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
175{
176 switch (ip_proto) {
177 case IPPROTO_UDP:
178 return MLX4_NET_TRANS_RULE_ID_UDP;
179 case IPPROTO_TCP:
180 return MLX4_NET_TRANS_RULE_ID_TCP;
181 default:
c3ca5205 182 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 183 }
184};
185
b6e01232
TT		 186/* Must not acquire state_lock, as its corresponding work_sync
187 * is done under it.
188 */
1eb8c695
AV		 189static void mlx4_en_filter_work(struct work_struct *work)
190{
191 struct mlx4_en_filter *filter = container_of(work,
192 struct mlx4_en_filter,
193 work);
194 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 195 struct mlx4_spec_list spec_tcp_udp = {
196 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 197 {
198 .tcp_udp = {
199 .dst_port = filter->dst_port,
200 .dst_port_msk = (__force __be16)-1,
201 .src_port = filter->src_port,
202 .src_port_msk = (__force __be16)-1,
203 },
204 },
205 };
206 struct mlx4_spec_list spec_ip = {
207 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
208 {
209 .ipv4 = {
210 .dst_ip = filter->dst_ip,
211 .dst_ip_msk = (__force __be32)-1,
212 .src_ip = filter->src_ip,
213 .src_ip_msk = (__force __be32)-1,
214 },
215 },
216 };
217 struct mlx4_spec_list spec_eth = {
218 .id = MLX4_NET_TRANS_RULE_ID_ETH,
219 };
220 struct mlx4_net_trans_rule rule = {
221 .list = LIST_HEAD_INIT(rule.list),
222 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
223 .exclusive = 1,
224 .allow_loopback = 1,
f9162539 225 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 226 .port = priv->port,
227 .priority = MLX4_DOMAIN_RFS,
228 };
229 int rc;
1eb8c695
AV		 230 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
231
c3ca5205 232 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 233 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
234 filter->ip_proto);
235 goto ignore;
236 }
1eb8c695
AV		 237 list_add_tail(&spec_eth.list, &rule.list);
238 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 239 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 240
1eb8c695 241 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 242 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 243 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
244
245 filter->activated = 0;
246
247 if (filter->reg_id) {
248 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
249 if (rc && rc != -ENOENT)
250 en_err(priv, "Error detaching flow. rc = %d\n", rc);
251 }
252
253 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
254 if (rc)
255 en_err(priv, "Error attaching flow. err = %d\n", rc);
256
75a353d4 257ignore:
1eb8c695
AV		 258 mlx4_en_filter_rfs_expire(priv);
259
260 filter->activated = 1;
261}
262
263static inline struct hlist_head *
264filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
265 __be16 src_port, __be16 dst_port)
266{
267 unsigned long l;
268 int bucket_idx;
269
270 l = (__force unsigned long)src_port |
271 ((__force unsigned long)dst_port << 2);
272 l ^= (__force unsigned long)(src_ip ^ dst_ip);
273
274 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
275
276 return &priv->filter_hash[bucket_idx];
277}
278
279static struct mlx4_en_filter *
280mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 281 __be32 dst_ip, u8 ip_proto, __be16 src_port,
282 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 283{
284 struct mlx4_en_filter *filter = NULL;
285
286 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
287 if (!filter)
288 return NULL;
289
290 filter->priv = priv;
291 filter->rxq_index = rxq_index;
292 INIT_WORK(&filter->work, mlx4_en_filter_work);
293
294 filter->src_ip = src_ip;
295 filter->dst_ip = dst_ip;
75a353d4 296 filter->ip_proto = ip_proto;
1eb8c695
AV		 297 filter->src_port = src_port;
298 filter->dst_port = dst_port;
299
300 filter->flow_id = flow_id;
301
ee64c0ee 302 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 303
304 list_add_tail(&filter->next, &priv->filters);
305 hlist_add_head(&filter->filter_chain,
306 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
307 dst_port));
308
309 return filter;
310}
311
312static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
313{
314 struct mlx4_en_priv *priv = filter->priv;
315 int rc;
316
317 list_del(&filter->next);
318
319 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
320 if (rc && rc != -ENOENT)
321 en_err(priv, "Error detaching flow. rc = %d\n", rc);
322
323 kfree(filter);
324}
325
326static inline struct mlx4_en_filter *
327mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 328 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 329{
1eb8c695
AV		 330 struct mlx4_en_filter *filter;
331 struct mlx4_en_filter *ret = NULL;
332
b67bfe0d 333 hlist_for_each_entry(filter,
1eb8c695
AV		 334 filter_hash_bucket(priv, src_ip, dst_ip,
335 src_port, dst_port),
336 filter_chain) {
337 if (filter->src_ip == src_ip &&
338 filter->dst_ip == dst_ip &&
75a353d4 339 filter->ip_proto == ip_proto &&
1eb8c695
AV		 340 filter->src_port == src_port &&
341 filter->dst_port == dst_port) {
342 ret = filter;
343 break;
344 }
345 }
346
347 return ret;
348}
349
350static int
351mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
352 u16 rxq_index, u32 flow_id)
353{
354 struct mlx4_en_priv *priv = netdev_priv(net_dev);
355 struct mlx4_en_filter *filter;
356 const struct iphdr *ip;
357 const __be16 *ports;
75a353d4 358 u8 ip_proto;
1eb8c695
AV		 359 __be32 src_ip;
360 __be32 dst_ip;
361 __be16 src_port;
362 __be16 dst_port;
363 int nhoff = skb_network_offset(skb);
364 int ret = 0;
365
366 if (skb->protocol != htons(ETH_P_IP))
367 return -EPROTONOSUPPORT;
368
369 ip = (const struct iphdr *)(skb->data + nhoff);
370 if (ip_is_fragment(ip))
371 return -EPROTONOSUPPORT;
372
75a353d4
EP		 373 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
374 return -EPROTONOSUPPORT;
1eb8c695
AV		 375 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
376
75a353d4 377 ip_proto = ip->protocol;
1eb8c695
AV		 378 src_ip = ip->saddr;
379 dst_ip = ip->daddr;
380 src_port = ports[0];
381 dst_port = ports[1];
382
1eb8c695 383 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 384 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
385 src_port, dst_port);
1eb8c695
AV		 386 if (filter) {
387 if (filter->rxq_index == rxq_index)
388 goto out;
389
390 filter->rxq_index = rxq_index;
391 } else {
392 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 393 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 394 src_port, dst_port, flow_id);
395 if (!filter) {
396 ret = -ENOMEM;
397 goto err;
398 }
399 }
400
401 queue_work(priv->mdev->workqueue, &filter->work);
402
403out:
404 ret = filter->id;
405err:
406 spin_unlock_bh(&priv->filters_lock);
407
408 return ret;
409}
410
41d942d5 411void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 412{
413 struct mlx4_en_filter *filter, *tmp;
414 LIST_HEAD(del_list);
415
416 spin_lock_bh(&priv->filters_lock);
417 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
418 list_move(&filter->next, &del_list);
419 hlist_del(&filter->filter_chain);
420 }
421 spin_unlock_bh(&priv->filters_lock);
422
423 list_for_each_entry_safe(filter, tmp, &del_list, next) {
424 cancel_work_sync(&filter->work);
425 mlx4_en_filter_free(filter);
426 }
427}
428
429static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
430{
431 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
432 LIST_HEAD(del_list);
433 int i = 0;
434
435 spin_lock_bh(&priv->filters_lock);
436 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
437 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
438 break;
439
440 if (filter->activated &&
441 !work_pending(&filter->work) &&
442 rps_may_expire_flow(priv->dev,
443 filter->rxq_index, filter->flow_id,
444 filter->id)) {
445 list_move(&filter->next, &del_list);
446 hlist_del(&filter->filter_chain);
447 } else
448 last_filter = filter;
449
450 i++;
451 }
452
453 if (last_filter && (&last_filter->next != priv->filters.next))
454 list_move(&priv->filters, &last_filter->next);
455
456 spin_unlock_bh(&priv->filters_lock);
457
458 list_for_each_entry_safe(filter, tmp, &del_list, next)
459 mlx4_en_filter_free(filter);
460}
461#endif
462
80d5c368
PM		 463static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
464 __be16 proto, u16 vid)
c27a02cd
YP		 465{
466 struct mlx4_en_priv *priv = netdev_priv(dev);
467 struct mlx4_en_dev *mdev = priv->mdev;
468 int err;
4c3eb3ca 469 int idx;
c27a02cd 470
f1b553fb 471 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 472
f1b553fb 473 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 474
475 /* Add VID to port VLAN filter */
476 mutex_lock(&mdev->state_lock);
477 if (mdev->device_up && priv->port_up) {
f1b553fb 478 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
93c098af 479 if (err) {
453a6082 480 en_err(priv, "Failed configuring VLAN filter\n");
93c098af
KH		 481 goto out;
482 }
c27a02cd 483 }
93c098af
KH		 484 err = mlx4_register_vlan(mdev->dev, priv->port, vid, &idx);
485 if (err)
486 en_dbg(HW, priv, "Failed adding vlan %d\n", vid);
4c3eb3ca 487
93c098af
KH		 488out:
489 mutex_unlock(&mdev->state_lock);
490 return err;
c27a02cd
YP		 491}
492
80d5c368
PM		 493static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
494 __be16 proto, u16 vid)
c27a02cd
YP		 495{
496 struct mlx4_en_priv *priv = netdev_priv(dev);
497 struct mlx4_en_dev *mdev = priv->mdev;
93c098af 498 int err = 0;
c27a02cd 499
f1b553fb 500 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 501
f1b553fb 502 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 503
504 /* Remove VID from port VLAN filter */
505 mutex_lock(&mdev->state_lock);
2009d005 506 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 507
c27a02cd 508 if (mdev->device_up && priv->port_up) {
f1b553fb 509 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 510 if (err)
453a6082 511 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 512 }
513 mutex_unlock(&mdev->state_lock);
8e586137 514
93c098af 515 return err;
c27a02cd
YP		 516}
517
6bbb6d99
YB		 518static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
519{
bab6a9ea
YB		 520 int i;
521 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 522 dst_mac[i] = src_mac & 0xff;
523 src_mac >>= 8;
524 }
525 memset(&dst_mac[ETH_ALEN], 0, 2);
526}
527
837052d0
OG		 528
529static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
530 int qpn, u64 *reg_id)
531{
532 int err;
837052d0 533
5eff6dad
OG		 534 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
535 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 536 return 0; /* do nothing */
537
b95089d0
OG		 538 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
539 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 540 if (err) {
541 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
542 return err;
543 }
544 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
545 return 0;
546}
547
548
16a10ffd
YB		 549static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
550 unsigned char *mac, int *qpn, u64 *reg_id)
551{
552 struct mlx4_en_dev *mdev = priv->mdev;
553 struct mlx4_dev *dev = mdev->dev;
554 int err;
555
556 switch (dev->caps.steering_mode) {
557 case MLX4_STEERING_MODE_B0: {
558 struct mlx4_qp qp;
559 u8 gid[16] = {0};
560
561 qp.qpn = *qpn;
562 memcpy(&gid[10], mac, ETH_ALEN);
563 gid[5] = priv->port;
564
565 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
566 break;
567 }
568 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
569 struct mlx4_spec_list spec_eth = { {NULL} };
570 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
571
572 struct mlx4_net_trans_rule rule = {
573 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
574 .exclusive = 0,
575 .allow_loopback = 1,
f9162539 576 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 577 .priority = MLX4_DOMAIN_NIC,
578 };
579
580 rule.port = priv->port;
581 rule.qpn = *qpn;
582 INIT_LIST_HEAD(&rule.list);
583
584 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
585 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
586 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
587 list_add_tail(&spec_eth.list, &rule.list);
588
589 err = mlx4_flow_attach(dev, &rule, reg_id);
590 break;
591 }
592 default:
593 return -EINVAL;
594 }
595 if (err)
596 en_warn(priv, "Failed Attaching Unicast\n");
597
598 return err;
599}
600
601static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
602 unsigned char *mac, int qpn, u64 reg_id)
603{
604 struct mlx4_en_dev *mdev = priv->mdev;
605 struct mlx4_dev *dev = mdev->dev;
606
607 switch (dev->caps.steering_mode) {
608 case MLX4_STEERING_MODE_B0: {
609 struct mlx4_qp qp;
610 u8 gid[16] = {0};
611
612 qp.qpn = qpn;
613 memcpy(&gid[10], mac, ETH_ALEN);
614 gid[5] = priv->port;
615
616 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
617 break;
618 }
619 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
620 mlx4_flow_detach(dev, reg_id);
621 break;
622 }
623 default:
624 en_err(priv, "Invalid steering mode.\n");
625 }
626}
627
628static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
629{
630 struct mlx4_en_dev *mdev = priv->mdev;
631 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 632 int index = 0;
633 int err = 0;
16a10ffd 634 int *qpn = &priv->base_qpn;
9813337a 635 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 636
637 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
638 priv->dev->dev_addr);
639 index = mlx4_register_mac(dev, priv->port, mac);
640 if (index < 0) {
641 err = index;
642 en_err(priv, "Failed adding MAC: %pM\n",
643 priv->dev->dev_addr);
644 return err;
645 }
646
4931c6ef
SM		 647 en_info(priv, "Steering Mode %d\n", dev->caps.steering_mode);
648
16a10ffd
YB		 649 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
650 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
651 *qpn = base_qpn + index;
652 return 0;
653 }
654
f3301870
MS		 655 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP,
656 MLX4_RES_USAGE_DRIVER);
16a10ffd
YB		 657 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
658 if (err) {
659 en_err(priv, "Failed to reserve qp for mac registration\n");
ba4b87ae
IS		 660 mlx4_unregister_mac(dev, priv->port, mac);
661 return err;
16a10ffd 662 }
16a10ffd 663
c07cb4b0 664 return 0;
16a10ffd
YB		 665}
666
667static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
668{
669 struct mlx4_en_dev *mdev = priv->mdev;
670 struct mlx4_dev *dev = mdev->dev;
16a10ffd 671 int qpn = priv->base_qpn;
16a10ffd 672
83a5a6ce 673 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
ba4b87ae 674 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 675 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
676 priv->dev->dev_addr);
677 mlx4_unregister_mac(dev, priv->port, mac);
678 } else {
83a5a6ce
YB		 679 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
680 priv->port, qpn);
681 mlx4_qp_release_range(dev, qpn, 1);
682 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 683 }
684}
685
686static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 687 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 688{
689 struct mlx4_en_dev *mdev = priv->mdev;
690 struct mlx4_dev *dev = mdev->dev;
16a10ffd 691 int err = 0;
9813337a 692 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 693
694 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 695 struct hlist_head *bucket;
696 unsigned int mac_hash;
697 struct mlx4_mac_entry *entry;
b67bfe0d 698 struct hlist_node *tmp;
9813337a 699 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 700
701 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 702 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 703 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
704 mlx4_en_uc_steer_release(priv, entry->mac,
705 qpn, entry->reg_id);
706 mlx4_unregister_mac(dev, priv->port,
707 prev_mac_u64);
708 hlist_del_rcu(&entry->hlist);
709 synchronize_rcu();
710 memcpy(entry->mac, new_mac, ETH_ALEN);
711 entry->reg_id = 0;
712 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
713 hlist_add_head_rcu(&entry->hlist,
714 &priv->mac_hash[mac_hash]);
715 mlx4_register_mac(dev, priv->port, new_mac_u64);
716 err = mlx4_en_uc_steer_add(priv, new_mac,
717 &qpn,
718 &entry->reg_id);
2a2083f7
OG		 719 if (err)
720 return err;
721 if (priv->tunnel_reg_id) {
722 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
723 priv->tunnel_reg_id = 0;
724 }
725 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
726 &priv->tunnel_reg_id);
c07cb4b0
YB		 727 return err;
728 }
729 }
730 return -EINVAL;
16a10ffd
YB		 731 }
732
733 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
734}
735
be599603
MS		 736static void mlx4_en_update_user_mac(struct mlx4_en_priv *priv,
737 unsigned char new_mac[ETH_ALEN + 2])
738{
739 struct mlx4_en_dev *mdev = priv->mdev;
740 int err;
741
742 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_USER_MAC_EN))
743 return;
744
745 err = mlx4_SET_PORT_user_mac(mdev->dev, priv->port, new_mac);
746 if (err)
747 en_err(priv, "Failed to pass user MAC(%pM) to Firmware for port %d, with error %d\n",
748 new_mac, priv->port, err);
749}
750
2695bab2
NO		 751static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
752 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 753{
c27a02cd
YP		 754 int err = 0;
755
c27a02cd
YP		 756 if (priv->port_up) {
757 /* Remove old MAC and insert the new one */
16a10ffd 758 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 759 new_mac, priv->current_mac);
c27a02cd 760 if (err)
453a6082 761 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 762 } else
48e551ff 763 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 764
2695bab2
NO		 765 if (!err)
766 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 767
bfa8ab47
YB		 768 return err;
769}
770
771static int mlx4_en_set_mac(struct net_device *dev, void *addr)
772{
773 struct mlx4_en_priv *priv = netdev_priv(dev);
774 struct mlx4_en_dev *mdev = priv->mdev;
775 struct sockaddr *saddr = addr;
2695bab2 776 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 777 int err;
778
779 if (!is_valid_ether_addr(saddr->sa_data))
780 return -EADDRNOTAVAIL;
781
bfa8ab47 782 mutex_lock(&mdev->state_lock);
2695bab2
NO		 783 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
784 err = mlx4_en_do_set_mac(priv, new_mac);
be599603
MS		 785 if (err)
786 goto out;
787
788 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
789 mlx4_en_update_user_mac(priv, new_mac);
790out:
c27a02cd 791 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 792
793 return err;
c27a02cd
YP		 794}
795
796static void mlx4_en_clear_list(struct net_device *dev)
797{
798 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 799 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 800
6d199937
YP		 801 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
802 list_del(&mc_to_del->list);
803 kfree(mc_to_del);
804 }
c27a02cd
YP		 805}
806
807static void mlx4_en_cache_mclist(struct net_device *dev)
808{
809 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 810 struct netdev_hw_addr *ha;
6d199937 811 struct mlx4_en_mc_list *tmp;
ff6e2163 812
0e03567a 813 mlx4_en_clear_list(dev);
6d199937
YP		 814 netdev_for_each_mc_addr(ha, dev) {
815 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
816 if (!tmp) {
6d199937
YP		 817 mlx4_en_clear_list(dev);
818 return;
819 }
820 memcpy(tmp->addr, ha->addr, ETH_ALEN);
821 list_add_tail(&tmp->list, &priv->mc_list);
822 }
c27a02cd
YP		 823}
824
6d199937
YP		 825static void update_mclist_flags(struct mlx4_en_priv *priv,
826 struct list_head *dst,
827 struct list_head *src)
828{
829 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
830 bool found;
831
832 /* Find all the entries that should be removed from dst,
833 * These are the entries that are not found in src
834 */
835 list_for_each_entry(dst_tmp, dst, list) {
836 found = false;
837 list_for_each_entry(src_tmp, src, list) {
c0623e58 838 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 839 found = true;
840 break;
841 }
842 }
843 if (!found)
844 dst_tmp->action = MCLIST_REM;
845 }
846
847 /* Add entries that exist in src but not in dst
848 * mark them as need to add
849 */
850 list_for_each_entry(src_tmp, src, list) {
851 found = false;
852 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 853 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 854 dst_tmp->action = MCLIST_NONE;
855 found = true;
856 break;
857 }
858 }
859 if (!found) {
14f8dc49
JP		 860 new_mc = kmemdup(src_tmp,
861 sizeof(struct mlx4_en_mc_list),
6d199937 862 GFP_KERNEL);
14f8dc49 863 if (!new_mc)
6d199937 864 return;
14f8dc49 865
6d199937
YP		 866 new_mc->action = MCLIST_ADD;
867 list_add_tail(&new_mc->list, dst);
868 }
869 }
870}
c27a02cd 871
0eb74fdd 872static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 873{
874 struct mlx4_en_priv *priv = netdev_priv(dev);
875
876 if (!priv->port_up)
877 return;
878
0eb74fdd 879 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 880}
881
0eb74fdd
YB		 882static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
883 struct mlx4_en_dev *mdev)
c27a02cd 884{
c96d97f4 885 int err = 0;
c27a02cd 886
0eb74fdd 887 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 888 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 889 en_warn(priv, "Entering promiscuous mode\n");
890 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 891
0eb74fdd 892 /* Enable promiscouos mode */
c96d97f4 893 switch (mdev->dev->caps.steering_mode) {
592e49dd 894 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 895 err = mlx4_flow_steer_promisc_add(mdev->dev,
896 priv->port,
897 priv->base_qpn,
f9162539 898 MLX4_FS_ALL_DEFAULT);
592e49dd 899 if (err)
0eb74fdd
YB		 900 en_err(priv, "Failed enabling promiscuous mode\n");
901 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 902 break;
903
c96d97f4 904 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 905 err = mlx4_unicast_promisc_add(mdev->dev,
906 priv->base_qpn,
907 priv->port);
c96d97f4 908 if (err)
0eb74fdd
YB		 909 en_err(priv, "Failed enabling unicast promiscuous mode\n");
910
911 /* Add the default qp number as multicast
912 * promisc
913 */
914 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
915 err = mlx4_multicast_promisc_add(mdev->dev,
916 priv->base_qpn,
917 priv->port);
c96d97f4 918 if (err)
0eb74fdd
YB		 919 en_err(priv, "Failed enabling multicast promiscuous mode\n");
920 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 921 }
922 break;
c27a02cd 923
c96d97f4
HHZ		 924 case MLX4_STEERING_MODE_A0:
925 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
926 priv->port,
0eb74fdd
YB		 927 priv->base_qpn,
928 1);
1679200f 929 if (err)
0eb74fdd 930 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 931 break;
1679200f
YP		 932 }
933
0eb74fdd
YB		 934 /* Disable port multicast filter (unconditionally) */
935 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
936 0, MLX4_MCAST_DISABLE);
937 if (err)
938 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 939 }
940}
941
942static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
943 struct mlx4_en_dev *mdev)
944{
945 int err = 0;
946
947 if (netif_msg_rx_status(priv))
948 en_warn(priv, "Leaving promiscuous mode\n");
949 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
950
951 /* Disable promiscouos mode */
952 switch (mdev->dev->caps.steering_mode) {
953 case MLX4_STEERING_MODE_DEVICE_MANAGED:
954 err = mlx4_flow_steer_promisc_remove(mdev->dev,
955 priv->port,
f9162539 956 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 957 if (err)
958 en_err(priv, "Failed disabling promiscuous mode\n");
959 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
960 break;
961
962 case MLX4_STEERING_MODE_B0:
963 err = mlx4_unicast_promisc_remove(mdev->dev,
964 priv->base_qpn,
965 priv->port);
966 if (err)
967 en_err(priv, "Failed disabling unicast promiscuous mode\n");
968 /* Disable Multicast promisc */
969 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
970 err = mlx4_multicast_promisc_remove(mdev->dev,
971 priv->base_qpn,
972 priv->port);
973 if (err)
974 en_err(priv, "Failed disabling multicast promiscuous mode\n");
975 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
976 }
977 break;
978
979 case MLX4_STEERING_MODE_A0:
980 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
981 priv->port,
982 priv->base_qpn, 0);
983 if (err)
984 en_err(priv, "Failed disabling promiscuous mode\n");
985 break;
c27a02cd 986 }
0eb74fdd
YB		 987}
988
989static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
990 struct net_device *dev,
991 struct mlx4_en_dev *mdev)
992{
993 struct mlx4_en_mc_list *mclist, *tmp;
994 u64 mcast_addr = 0;
995 u8 mc_list[16] = {0};
996 int err = 0;
997
c27a02cd
YP		 998 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
999 if (dev->flags & IFF_ALLMULTI) {
1000 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1001 0, MLX4_MCAST_DISABLE);
1002 if (err)
453a6082 1003 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 1004
1005 /* Add the default qp number as multicast promisc */
1006 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 1007 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1008 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1009 err = mlx4_flow_steer_promisc_add(mdev->dev,
1010 priv->port,
1011 priv->base_qpn,
f9162539 1012 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1013 break;
1014
c96d97f4
HHZ		 1015 case MLX4_STEERING_MODE_B0:
1016 err = mlx4_multicast_promisc_add(mdev->dev,
1017 priv->base_qpn,
1018 priv->port);
1019 break;
1020
1021 case MLX4_STEERING_MODE_A0:
1022 break;
1023 }
1679200f
YP		 1024 if (err)
1025 en_err(priv, "Failed entering multicast promisc mode\n");
1026 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1027 }
c27a02cd 1028 } else {
1679200f
YP		 1029 /* Disable Multicast promisc */
1030 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1031 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1032 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1033 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1034 priv->port,
f9162539 1035 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1036 break;
1037
c96d97f4
HHZ		 1038 case MLX4_STEERING_MODE_B0:
1039 err = mlx4_multicast_promisc_remove(mdev->dev,
1040 priv->base_qpn,
1041 priv->port);
1042 break;
1043
1044 case MLX4_STEERING_MODE_A0:
1045 break;
1046 }
1679200f 1047 if (err)
25985edc 1048 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1049 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1050 }
ff6e2163 1051
c27a02cd
YP		 1052 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1053 0, MLX4_MCAST_DISABLE);
1054 if (err)
453a6082 1055 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1056
1057 /* Flush mcast filter and init it with broadcast address */
1058 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1059 1, MLX4_MCAST_CONFIG);
1060
1061 /* Update multicast list - we cache all addresses so they won't
1062 * change while HW is updated holding the command semaphor */
dbd501a8 1063 netif_addr_lock_bh(dev);
c27a02cd 1064 mlx4_en_cache_mclist(dev);
dbd501a8 1065 netif_addr_unlock_bh(dev);
6d199937 1066 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 1067 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 1068 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1069 mcast_addr, 0, MLX4_MCAST_CONFIG);
1070 }
1071 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1072 0, MLX4_MCAST_ENABLE);
1073 if (err)
453a6082 1074 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1075
1076 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1077 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1078 if (mclist->action == MCLIST_REM) {
1079 /* detach this address and delete from list */
1080 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1081 mc_list[5] = priv->port;
1082 err = mlx4_multicast_detach(mdev->dev,
4931c6ef 1083 priv->rss_map.indir_qp,
6d199937 1084 mc_list,
0ff1fb65
HHZ		 1085 MLX4_PROT_ETH,
1086 mclist->reg_id);
6d199937
YP		 1087 if (err)
1088 en_err(priv, "Fail to detach multicast address\n");
1089
837052d0
OG		 1090 if (mclist->tunnel_reg_id) {
1091 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1092 if (err)
1093 en_err(priv, "Failed to detach multicast address\n");
1094 }
1095
6d199937
YP		 1096 /* remove from list */
1097 list_del(&mclist->list);
1098 kfree(mclist);
9c64508a 1099 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1100 /* attach the address */
1101 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1102 /* needed for B0 steering support */
6d199937
YP		 1103 mc_list[5] = priv->port;
1104 err = mlx4_multicast_attach(mdev->dev,
4931c6ef 1105 priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1106 mc_list,
1107 priv->port, 0,
1108 MLX4_PROT_ETH,
1109 &mclist->reg_id);
6d199937
YP		 1110 if (err)
1111 en_err(priv, "Fail to attach multicast address\n");
1112
837052d0
OG		 1113 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1114 &mclist->tunnel_reg_id);
1115 if (err)
1116 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1117 }
1118 }
c27a02cd 1119 }
0eb74fdd
YB		 1120}
1121
cc5387f7
YB		 1122static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1123 struct net_device *dev,
1124 struct mlx4_en_dev *mdev)
1125{
1126 struct netdev_hw_addr *ha;
1127 struct mlx4_mac_entry *entry;
b67bfe0d 1128 struct hlist_node *tmp;
cc5387f7
YB		 1129 bool found;
1130 u64 mac;
1131 int err = 0;
1132 struct hlist_head *bucket;
1133 unsigned int i;
1134 int removed = 0;
1135 u32 prev_flags;
1136
1137 /* Note that we do not need to protect our mac_hash traversal with rcu,
1138 * since all modification code is protected by mdev->state_lock
1139 */
1140
1141 /* find what to remove */
1142 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1143 bucket = &priv->mac_hash[i];
b67bfe0d 1144 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1145 found = false;
1146 netdev_for_each_uc_addr(ha, dev) {
1147 if (ether_addr_equal_64bits(entry->mac,
1148 ha->addr)) {
1149 found = true;
1150 break;
1151 }
1152 }
1153
1154 /* MAC address of the port is not in uc list */
2695bab2
NO		 1155 if (ether_addr_equal_64bits(entry->mac,
1156 priv->current_mac))
cc5387f7
YB		 1157 found = true;
1158
1159 if (!found) {
9813337a 1160 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1161 mlx4_en_uc_steer_release(priv, entry->mac,
1162 priv->base_qpn,
1163 entry->reg_id);
1164 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1165
1166 hlist_del_rcu(&entry->hlist);
1167 kfree_rcu(entry, rcu);
1168 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1169 entry->mac, priv->port);
1170 ++removed;
1171 }
1172 }
1173 }
1174
1175 /* if we didn't remove anything, there is no use in trying to add
1176 * again once we are in a forced promisc mode state
1177 */
1178 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1179 return;
1180
1181 prev_flags = priv->flags;
1182 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1183
1184 /* find what to add */
1185 netdev_for_each_uc_addr(ha, dev) {
1186 found = false;
1187 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1188 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1189 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1190 found = true;
1191 break;
1192 }
1193 }
1194
1195 if (!found) {
1196 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1197 if (!entry) {
1198 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1199 ha->addr, priv->port);
1200 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1201 break;
1202 }
9813337a 1203 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1204 memcpy(entry->mac, ha->addr, ETH_ALEN);
1205 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1206 if (err < 0) {
1207 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1208 ha->addr, priv->port, err);
1209 kfree(entry);
1210 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1211 break;
1212 }
1213 err = mlx4_en_uc_steer_add(priv, ha->addr,
1214 &priv->base_qpn,
1215 &entry->reg_id);
1216 if (err) {
1217 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1218 ha->addr, priv->port, err);
1219 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1220 kfree(entry);
1221 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1222 break;
1223 } else {
1224 unsigned int mac_hash;
1225 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1226 ha->addr, priv->port);
1227 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1228 bucket = &priv->mac_hash[mac_hash];
1229 hlist_add_head_rcu(&entry->hlist, bucket);
1230 }
1231 }
1232 }
1233
1234 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1235 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1236 priv->port);
1237 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1238 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1239 priv->port);
1240 }
1241}
1242
0eb74fdd
YB		 1243static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1244{
1245 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1246 rx_mode_task);
1247 struct mlx4_en_dev *mdev = priv->mdev;
1248 struct net_device *dev = priv->dev;
1249
1250 mutex_lock(&mdev->state_lock);
1251 if (!mdev->device_up) {
1252 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1253 goto out;
1254 }
1255 if (!priv->port_up) {
1256 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1257 goto out;
1258 }
1259
1260 if (!netif_carrier_ok(dev)) {
1261 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1262 if (priv->port_state.link_state) {
1263 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1264 netif_carrier_on(dev);
1265 en_dbg(LINK, priv, "Link Up\n");
1266 }
1267 }
1268 }
1269
cc5387f7
YB		 1270 if (dev->priv_flags & IFF_UNICAST_FLT)
1271 mlx4_en_do_uc_filter(priv, dev, mdev);
1272
0eb74fdd 1273 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1274 if ((dev->flags & IFF_PROMISC) ||
1275 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1276 mlx4_en_set_promisc_mode(priv, mdev);
1277 goto out;
1278 }
1279
1280 /* Not in promiscuous mode */
1281 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1282 mlx4_en_clear_promisc_mode(priv, mdev);
1283
1284 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1285out:
1286 mutex_unlock(&mdev->state_lock);
1287}
1288
1289#ifdef CONFIG_NET_POLL_CONTROLLER
1290static void mlx4_en_netpoll(struct net_device *dev)
1291{
1292 struct mlx4_en_priv *priv = netdev_priv(dev);
1293 struct mlx4_en_cq *cq;
c27a02cd
YP		 1294 int i;
1295
67f8b1dc
TT		 1296 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1297 cq = priv->tx_cq[TX][i];
c98235cb 1298 napi_schedule(&cq->napi);
c27a02cd
YP		 1299 }
1300}
1301#endif
1302
ba4b87ae
IS		 1303static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1304{
1305 u64 reg_id;
1306 int err = 0;
1307 int *qpn = &priv->base_qpn;
1308 struct mlx4_mac_entry *entry;
1309
1310 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
1311 if (err)
1312 return err;
1313
1314 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1315 &priv->tunnel_reg_id);
1316 if (err)
1317 goto tunnel_err;
1318
1319 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1320 if (!entry) {
1321 err = -ENOMEM;
1322 goto alloc_err;
1323 }
1324
1325 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1326 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1327 entry->reg_id = reg_id;
1328 hlist_add_head_rcu(&entry->hlist,
1329 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1330
1331 return 0;
1332
1333alloc_err:
1334 if (priv->tunnel_reg_id)
1335 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1336
1337tunnel_err:
1338 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1339 return err;
1340}
1341
1342static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1343{
1344 u64 mac;
1345 unsigned int i;
1346 int qpn = priv->base_qpn;
1347 struct hlist_head *bucket;
1348 struct hlist_node *tmp;
1349 struct mlx4_mac_entry *entry;
1350
1351 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1352 bucket = &priv->mac_hash[i];
1353 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1354 mac = mlx4_mac_to_u64(entry->mac);
1355 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1356 entry->mac);
1357 mlx4_en_uc_steer_release(priv, entry->mac,
1358 qpn, entry->reg_id);
1359
1360 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1361 hlist_del_rcu(&entry->hlist);
1362 kfree_rcu(entry, rcu);
1363 }
1364 }
1365
1366 if (priv->tunnel_reg_id) {
1367 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1368 priv->tunnel_reg_id = 0;
1369 }
1370}
1371
c27a02cd
YP		 1372static void mlx4_en_tx_timeout(struct net_device *dev)
1373{
1374 struct mlx4_en_priv *priv = netdev_priv(dev);
1375 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1376 int i;
c27a02cd
YP		 1377
1378 if (netif_msg_timer(priv))
453a6082 1379 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1380
67f8b1dc
TT		 1381 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
1382 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][i];
1383
b944ebec
YP		 1384 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1385 continue;
1386 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
e3f42f84 1387 i, tx_ring->qpn, tx_ring->sp_cqn,
67f8b1dc 1388 tx_ring->cons, tx_ring->prod);
b944ebec
YP		 1389 }
1390
1e338db5 1391 priv->port_stats.tx_timeout++;
453a6082 1392 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1393 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1394}
1395
1396
bc1f4470 1397static void
9ed17db1 1398mlx4_en_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
c27a02cd
YP		 1399{
1400 struct mlx4_en_priv *priv = netdev_priv(dev);
1401
1402 spin_lock_bh(&priv->stats_lock);
40931b85 1403 mlx4_en_fold_software_stats(dev);
f73a6f43 1404 netdev_stats_to_stats64(stats, &dev->stats);
c27a02cd 1405 spin_unlock_bh(&priv->stats_lock);
c27a02cd
YP		 1406}
1407
1408static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1409{
c27a02cd 1410 struct mlx4_en_cq *cq;
67f8b1dc 1411 int i, t;
c27a02cd
YP		 1412
1413 /* If we haven't received a specific coalescing setting
98a1708d 1414 * (module param), we set the moderation parameters as follows:
c27a02cd 1415 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1416 * satisfy our coalescing target.
c27a02cd
YP		 1417 * - moder_time is set to a fixed value.
1418 */
3db36fb2 1419 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1420 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1421 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1422 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
593814d1 1423 en_dbg(INTR, priv, "Default coalescing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
48e551ff 1424 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1425
1426 /* Setup cq moderation params */
1427 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1428 cq = priv->rx_cq[i];
c27a02cd
YP		 1429 cq->moder_cnt = priv->rx_frames;
1430 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1431 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1432 priv->last_moder_packets[i] = 0;
1433 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1434 }
1435
67f8b1dc
TT		 1436 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
1437 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1438 cq = priv->tx_cq[t][i];
1439 cq->moder_cnt = priv->tx_frames;
1440 cq->moder_time = priv->tx_usecs;
1441 }
c27a02cd
YP		 1442 }
1443
1444 /* Reset auto-moderation params */
1445 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1446 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1447 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1448 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1449 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1450 priv->adaptive_rx_coal = 1;
c27a02cd 1451 priv->last_moder_jiffies = 0;
c27a02cd 1452 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1453}
1454
1455static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1456{
1457 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
f5a57723 1458 u32 pkt_rate_high, pkt_rate_low;
c27a02cd
YP		 1459 struct mlx4_en_cq *cq;
1460 unsigned long packets;
1461 unsigned long rate;
1462 unsigned long avg_pkt_size;
1463 unsigned long rx_packets;
1464 unsigned long rx_bytes;
c27a02cd
YP		 1465 unsigned long rx_pkt_diff;
1466 int moder_time;
6b4d8d9f 1467 int ring, err;
c27a02cd
YP		 1468
1469 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1470 return;
1471
f5a57723
ED		 1472 pkt_rate_low = READ_ONCE(priv->pkt_rate_low);
1473 pkt_rate_high = READ_ONCE(priv->pkt_rate_high);
1474
6b4d8d9f 1475 for (ring = 0; ring < priv->rx_ring_num; ring++) {
b9972d22
ED		 1476 rx_packets = READ_ONCE(priv->rx_ring[ring]->packets);
1477 rx_bytes = READ_ONCE(priv->rx_ring[ring]->bytes);
6b4d8d9f 1478
f5a57723 1479 rx_pkt_diff = rx_packets - priv->last_moder_packets[ring];
6b4d8d9f
AG		 1480 packets = rx_pkt_diff;
1481 rate = packets * HZ / period;
f5a57723
ED		 1482 avg_pkt_size = packets ? (rx_bytes -
1483 priv->last_moder_bytes[ring]) / packets : 0;
6b4d8d9f
AG		 1484
1485 /* Apply auto-moderation only when packet rate
1486 * exceeds a rate that it matters */
1487 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1488 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
f5a57723 1489 if (rate <= pkt_rate_low)
c27a02cd 1490 moder_time = priv->rx_usecs_low;
f5a57723 1491 else if (rate >= pkt_rate_high)
c27a02cd
YP		 1492 moder_time = priv->rx_usecs_high;
1493 else
f5a57723 1494 moder_time = (rate - pkt_rate_low) *
c27a02cd 1495 (priv->rx_usecs_high - priv->rx_usecs_low) /
f5a57723 1496 (pkt_rate_high - pkt_rate_low) +
c27a02cd 1497 priv->rx_usecs_low;
6b4d8d9f
AG		 1498 } else {
1499 moder_time = priv->rx_usecs_low;
c27a02cd 1500 }
c27a02cd 1501
f5a57723
ED		 1502 cq = priv->rx_cq[ring];
1503 if (moder_time != priv->last_moder_time[ring] ||
1504 cq->moder_cnt != priv->rx_frames) {
6b4d8d9f 1505 priv->last_moder_time[ring] = moder_time;
c27a02cd 1506 cq->moder_time = moder_time;
a1c6693a 1507 cq->moder_cnt = priv->rx_frames;
c27a02cd 1508 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1509 if (err)
48e551ff
YB		 1510 en_err(priv, "Failed modifying moderation for cq:%d\n",
1511 ring);
c27a02cd 1512 }
6b4d8d9f
AG		 1513 priv->last_moder_packets[ring] = rx_packets;
1514 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1515 }
1516
c27a02cd
YP		 1517 priv->last_moder_jiffies = jiffies;
1518}
1519
1520static void mlx4_en_do_get_stats(struct work_struct *work)
1521{
bf6aede7 1522 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1523 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1524 stats_task);
1525 struct mlx4_en_dev *mdev = priv->mdev;
1526 int err;
1527
c27a02cd
YP		 1528 mutex_lock(&mdev->state_lock);
1529 if (mdev->device_up) {
6123db2e
JM		 1530 if (priv->port_up) {
1531 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1532 if (err)
1533 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1534
c27a02cd 1535 mlx4_en_auto_moderation(priv);
6123db2e 1536 }
c27a02cd
YP		 1537
1538 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1539 }
d7e1a487 1540 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1541 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1542 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1543 }
c27a02cd
YP		 1544 mutex_unlock(&mdev->state_lock);
1545}
1546
b6c39bfc
AV		 1547/* mlx4_en_service_task - Run service task for tasks that needed to be done
1548 * periodically
1549 */
1550static void mlx4_en_service_task(struct work_struct *work)
1551{
1552 struct delayed_work *delay = to_delayed_work(work);
1553 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1554 service_task);
1555 struct mlx4_en_dev *mdev = priv->mdev;
1556
1557 mutex_lock(&mdev->state_lock);
1558 if (mdev->device_up) {
dc8142ea
AV		 1559 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1560 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1561
07841f9d 1562 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1563 queue_delayed_work(mdev->workqueue, &priv->service_task,
1564 SERVICE_TASK_DELAY);
1565 }
1566 mutex_unlock(&mdev->state_lock);
1567}
1568
c27a02cd
YP		 1569static void mlx4_en_linkstate(struct work_struct *work)
1570{
1571 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1572 linkstate_task);
1573 struct mlx4_en_dev *mdev = priv->mdev;
1574 int linkstate = priv->link_state;
1575
1576 mutex_lock(&mdev->state_lock);
1577 /* If observable port state changed set carrier state and
1578 * report to system log */
1579 if (priv->last_link_state != linkstate) {
1580 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1581 en_info(priv, "Link Down\n");
c27a02cd
YP		 1582 netif_carrier_off(priv->dev);
1583 } else {
e5cc44b2 1584 en_info(priv, "Link Up\n");
c27a02cd
YP		 1585 netif_carrier_on(priv->dev);
1586 }
1587 }
1588 priv->last_link_state = linkstate;
1589 mutex_unlock(&mdev->state_lock);
1590}
1591
9e311e77
YA		 1592static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1593{
1594 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1595 int numa_node = priv->mdev->dev->numa_node;
9e311e77
YA		 1596
1597 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1598 return -ENOMEM;
1599
f36963c9
RR		 1600 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1601 ring->affinity_mask);
1602 return 0;
9e311e77
YA		 1603}
1604
1605static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1606{
1607 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1608}
c27a02cd 1609
9ecc2d86
BB		 1610static void mlx4_en_init_recycle_ring(struct mlx4_en_priv *priv,
1611 int tx_ring_idx)
1612{
67f8b1dc
TT		 1613 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX_XDP][tx_ring_idx];
1614 int rr_index = tx_ring_idx;
9ecc2d86 1615
67f8b1dc
TT		 1616 tx_ring->free_tx_desc = mlx4_en_recycle_tx_desc;
1617 tx_ring->recycle_ring = priv->rx_ring[rr_index];
1618 en_dbg(DRV, priv, "Set tx_ring[%d][%d]->recycle_ring = rx_ring[%d]\n",
1619 TX_XDP, tx_ring_idx, rr_index);
9ecc2d86
BB		 1620}
1621
18cc42a3 1622int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1623{
1624 struct mlx4_en_priv *priv = netdev_priv(dev);
1625 struct mlx4_en_dev *mdev = priv->mdev;
1626 struct mlx4_en_cq *cq;
1627 struct mlx4_en_tx_ring *tx_ring;
c27a02cd 1628 int rx_index = 0;
c27a02cd 1629 int err = 0;
67f8b1dc 1630 int i, t;
c27a02cd 1631 int j;
1679200f 1632 u8 mc_list[16] = {0};
c27a02cd
YP		 1633
1634 if (priv->port_up) {
453a6082 1635 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1636 return 0;
1637 }
1638
6d199937
YP		 1639 INIT_LIST_HEAD(&priv->mc_list);
1640 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1641 INIT_LIST_HEAD(&priv->ethtool_list);
1642 memset(&priv->ethtool_rules[0], 0,
1643 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1644
c27a02cd
YP		 1645 /* Calculate Rx buf size */
1646 dev->mtu = min(dev->mtu, priv->max_mtu);
1647 mlx4_en_calc_rx_buf(dev);
453a6082 1648 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1649
c27a02cd 1650 /* Configure rx cq's and rings */
38aab07c
YP		 1651 err = mlx4_en_activate_rx_rings(priv);
1652 if (err) {
453a6082 1653 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1654 return err;
1655 }
c27a02cd 1656 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1657 cq = priv->rx_cq[i];
c27a02cd 1658
9e311e77
YA		 1659 err = mlx4_en_init_affinity_hint(priv, i);
1660 if (err) {
1661 en_err(priv, "Failed preparing IRQ affinity hint\n");
1662 goto cq_err;
1663 }
1664
76532d0c 1665 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1666 if (err) {
453a6082 1667 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1668 mlx4_en_free_affinity_hint(priv, i);
a4233304 1669 goto cq_err;
c27a02cd 1670 }
c3f2511f
IS		 1671
1672 for (j = 0; j < cq->size; j++) {
1673 struct mlx4_cqe *cqe = NULL;
1674
1675 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1676 priv->cqe_factor;
1677 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1678 }
1679
c27a02cd
YP		 1680 err = mlx4_en_set_cq_moder(priv, cq);
1681 if (err) {
1a91de28 1682 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1683 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1684 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1685 goto cq_err;
1686 }
1687 mlx4_en_arm_cq(priv, cq);
41d942d5 1688 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1689 ++rx_index;
1690 }
1691
ffe455ad
EE		 1692 /* Set qp number */
1693 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1694 err = mlx4_en_get_qp(priv);
1679200f 1695 if (err) {
ffe455ad 1696 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1697 goto cq_err;
1698 }
1699 mdev->mac_removed[priv->port] = 0;
1700
6de5f7f6
EBE		 1701 priv->counter_index =
1702 mlx4_get_default_counter_index(mdev->dev, priv->port);
1703
c27a02cd
YP		 1704 err = mlx4_en_config_rss_steer(priv);
1705 if (err) {
453a6082 1706 en_err(priv, "Failed configuring rss steering\n");
1679200f 1707 goto mac_err;
c27a02cd
YP		 1708 }
1709
cabdc8ee
HHZ		 1710 err = mlx4_en_create_drop_qp(priv);
1711 if (err)
1712 goto rss_err;
1713
c27a02cd 1714 /* Configure tx cq's and rings */
67f8b1dc 1715 for (t = 0 ; t < MLX4_EN_NUM_TX_TYPES; t++) {
eb9def61
TT		 1716 u8 num_tx_rings_p_up = t == TX ?
1717 priv->num_tx_rings_p_up : priv->tx_ring_num[t];
c27a02cd 1718
67f8b1dc
TT		 1719 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1720 /* Configure cq */
1721 cq = priv->tx_cq[t][i];
1722 err = mlx4_en_activate_cq(priv, cq, i);
1723 if (err) {
1724 en_err(priv, "Failed allocating Tx CQ\n");
1725 goto tx_err;
1726 }
1727 err = mlx4_en_set_cq_moder(priv, cq);
1728 if (err) {
1729 en_err(priv, "Failed setting cq moderation parameters\n");
1730 mlx4_en_deactivate_cq(priv, cq);
1731 goto tx_err;
1732 }
1733 en_dbg(DRV, priv,
1734 "Resetting index of collapsed CQ:%d to -1\n", i);
1735 cq->buf->wqe_index = cpu_to_be16(0xffff);
1736
1737 /* Configure ring */
1738 tx_ring = priv->tx_ring[t][i];
1739 err = mlx4_en_activate_tx_ring(priv, tx_ring,
1740 cq->mcq.cqn,
1741 i / num_tx_rings_p_up);
1742 if (err) {
1743 en_err(priv, "Failed allocating Tx ring\n");
1744 mlx4_en_deactivate_cq(priv, cq);
1745 goto tx_err;
1746 }
1747 if (t != TX_XDP) {
1748 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
1749 tx_ring->recycle_ring = NULL;
6c78511b
TT		 1750
1751 /* Arm CQ for TX completions */
1752 mlx4_en_arm_cq(priv, cq);
1753
67f8b1dc 1754 } else {
f025fd60 1755 mlx4_en_init_tx_xdp_ring_descs(priv, tx_ring);
67f8b1dc 1756 mlx4_en_init_recycle_ring(priv, i);
6c78511b 1757 /* XDP TX CQ should never be armed */
67f8b1dc 1758 }
9ecc2d86 1759
67f8b1dc
TT		 1760 /* Set initial ownership of all Tx TXBBs to SW (1) */
1761 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1762 *((u32 *)(tx_ring->buf + j)) = 0xffffffff;
1763 }
c27a02cd
YP		 1764 }
1765
1766 /* Configure port */
1767 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1768 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1769 priv->prof->tx_pause,
1770 priv->prof->tx_ppp,
1771 priv->prof->rx_pause,
1772 priv->prof->rx_ppp);
c27a02cd 1773 if (err) {
48e551ff
YB		 1774 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1775 priv->port, err);
c27a02cd
YP		 1776 goto tx_err;
1777 }
40fb4fc1
SD		 1778
1779 err = mlx4_SET_PORT_user_mtu(mdev->dev, priv->port, dev->mtu);
1780 if (err) {
1781 en_err(priv, "Failed to pass user MTU(%d) to Firmware for port %d, with error %d\n",
1782 dev->mtu, priv->port, err);
1783 goto tx_err;
1784 }
1785
c27a02cd
YP		 1786 /* Set default qp number */
1787 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1788 if (err) {
453a6082 1789 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1790 goto tx_err;
1791 }
c27a02cd 1792
837052d0 1793 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1794 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1795 if (err) {
1796 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1797 err);
1798 goto tx_err;
1799 }
1800 }
1801
c27a02cd 1802 /* Init port */
453a6082 1803 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1804 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1805 if (err) {
453a6082 1806 en_err(priv, "Failed Initializing port\n");
1679200f 1807 goto tx_err;
c27a02cd
YP		 1808 }
1809
ba4b87ae
IS		 1810 /* Set Unicast and VXLAN steering rules */
1811 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1812 mlx4_en_set_rss_steer_rules(priv))
1813 mlx4_warn(mdev, "Failed setting steering rules\n");
1814
1679200f 1815 /* Attach rx QP to bradcast address */
c7bf7169 1816 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1817 mc_list[5] = priv->port; /* needed for B0 steering support */
4931c6ef 1818 if (mlx4_multicast_attach(mdev->dev, priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1819 priv->port, 0, MLX4_PROT_ETH,
1820 &priv->broadcast_id))
1679200f
YP		 1821 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1822
b5845f98
HX		 1823 /* Must redo promiscuous mode setup. */
1824 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1825
c27a02cd 1826 /* Schedule multicast task to populate multicast list */
0eb74fdd 1827 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1828
9737c6ab 1829 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
a831274a
AD		 1830 udp_tunnel_get_rx_info(dev);
1831
c27a02cd 1832 priv->port_up = true;
8d59de8f
ES		 1833
1834 /* Process all completions if exist to prevent
1835 * the queues freezing if they are full
1836 */
8cf699ec
ED		 1837 for (i = 0; i < priv->rx_ring_num; i++) {
1838 local_bh_disable();
8d59de8f 1839 napi_schedule(&priv->rx_cq[i]->napi);
8cf699ec
ED		 1840 local_bh_enable();
1841 }
8d59de8f 1842
a11faac7 1843 netif_tx_start_all_queues(dev);
3484aac1
AV		 1844 netif_device_attach(dev);
1845
c27a02cd
YP		 1846 return 0;
1847
c27a02cd 1848tx_err:
67f8b1dc
TT		 1849 if (t == MLX4_EN_NUM_TX_TYPES) {
1850 t--;
1851 i = priv->tx_ring_num[t];
1852 }
1853 while (t >= 0) {
1854 while (i--) {
1855 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1856 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1857 }
1858 if (!t--)
1859 break;
1860 i = priv->tx_ring_num[t];
c27a02cd 1861 }
cabdc8ee
HHZ		 1862 mlx4_en_destroy_drop_qp(priv);
1863rss_err:
c27a02cd 1864 mlx4_en_release_rss_steer(priv);
1679200f 1865mac_err:
16a10ffd 1866 mlx4_en_put_qp(priv);
c27a02cd 1867cq_err:
9e311e77 1868 while (rx_index--) {
41d942d5 1869 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1870 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1871 }
38aab07c 1872 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1873 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1874
1875 return err; /* need to close devices */
1876}
1877
1878
3484aac1 1879void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1880{
1881 struct mlx4_en_priv *priv = netdev_priv(dev);
1882 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1883 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1884 struct ethtool_flow_id *flow, *tmp_flow;
67f8b1dc 1885 int i, t;
1679200f 1886 u8 mc_list[16] = {0};
c27a02cd
YP		 1887
1888 if (!priv->port_up) {
453a6082 1889 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1890 return;
1891 }
c27a02cd 1892
0cc5c8bf
EE		 1893 /* close port*/
1894 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1895
c27a02cd
YP		 1896 /* Synchronize with tx routine */
1897 netif_tx_lock_bh(dev);
3484aac1
AV		 1898 if (detach)
1899 netif_device_detach(dev);
3c05f5ef 1900 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1901 netif_tx_unlock_bh(dev);
1902
3484aac1
AV		 1903 netif_tx_disable(dev);
1904
7f7bf160
ED		 1905 spin_lock_bh(&priv->stats_lock);
1906 mlx4_en_fold_software_stats(dev);
7c287380 1907 /* Set port as not active */
3c05f5ef 1908 priv->port_up = false;
7f7bf160
ED		 1909 spin_unlock_bh(&priv->stats_lock);
1910
6de5f7f6 1911 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
c27a02cd 1912
db0e7cba
AY		 1913 /* Promsicuous mode */
1914 if (mdev->dev->caps.steering_mode ==
1915 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1916 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1917 MLX4_EN_FLAG_MC_PROMISC);
1918 mlx4_flow_steer_promisc_remove(mdev->dev,
1919 priv->port,
f9162539 1920 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1921 mlx4_flow_steer_promisc_remove(mdev->dev,
1922 priv->port,
f9162539 1923 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1924 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1925 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1926
1927 /* Disable promiscouos mode */
1928 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1929 priv->port);
1930
1931 /* Disable Multicast promisc */
1932 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1933 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1934 priv->port);
1935 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1936 }
1937 }
1938
1679200f 1939 /* Detach All multicasts */
c7bf7169 1940 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1941 mc_list[5] = priv->port; /* needed for B0 steering support */
4931c6ef 1942 mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp, mc_list,
0ff1fb65 1943 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1944 list_for_each_entry(mclist, &priv->curr_list, list) {
1945 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f 1946 mc_list[5] = priv->port;
4931c6ef 1947 mlx4_multicast_detach(mdev->dev, priv->rss_map.indir_qp,
0ff1fb65 1948 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1949 if (mclist->tunnel_reg_id)
1950 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1951 }
1952 mlx4_en_clear_list(dev);
6d199937
YP		 1953 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1954 list_del(&mclist->list);
1955 kfree(mclist);
1956 }
1957
1679200f
YP		 1958 /* Flush multicast filter */
1959 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1960
6efb5fac
HHZ		 1961 /* Remove flow steering rules for the port*/
1962 if (mdev->dev->caps.steering_mode ==
1963 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1964 ASSERT_RTNL();
1965 list_for_each_entry_safe(flow, tmp_flow,
1966 &priv->ethtool_list, list) {
1967 mlx4_flow_detach(mdev->dev, flow->id);
1968 list_del(&flow->list);
1969 }
1970 }
1971
cabdc8ee
HHZ		 1972 mlx4_en_destroy_drop_qp(priv);
1973
c27a02cd 1974 /* Free TX Rings */
67f8b1dc
TT		 1975 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
1976 for (i = 0; i < priv->tx_ring_num[t]; i++) {
1977 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[t][i]);
1978 mlx4_en_deactivate_cq(priv, priv->tx_cq[t][i]);
1979 }
c27a02cd
YP		 1980 }
1981 msleep(10);
1982
67f8b1dc
TT		 1983 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++)
1984 for (i = 0; i < priv->tx_ring_num[t]; i++)
1985 mlx4_en_free_tx_buf(dev, priv->tx_ring[t][i]);
c27a02cd 1986
ba4b87ae
IS		 1987 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1988 mlx4_en_delete_rss_steer_rules(priv);
1989
c27a02cd
YP		 1990 /* Free RSS qps */
1991 mlx4_en_release_rss_steer(priv);
1992
ffe455ad 1993 /* Unregister Mac address for the port */
16a10ffd 1994 mlx4_en_put_qp(priv);
5930e8d0 1995 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1996 mdev->mac_removed[priv->port] = 1;
ffe455ad 1997
c27a02cd
YP		 1998 /* Free RX Rings */
1999 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 2000 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8 2001
f4a36751 2002 napi_synchronize(&cq->napi);
41d942d5 2003 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 2004 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 2005
2006 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 2007 }
2008}
2009
2010static void mlx4_en_restart(struct work_struct *work)
2011{
2012 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2013 watchdog_task);
2014 struct mlx4_en_dev *mdev = priv->mdev;
2015 struct net_device *dev = priv->dev;
2016
453a6082 2017 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5 2018
0c5c3252 2019 rtnl_lock();
1e338db5
YP		 2020 mutex_lock(&mdev->state_lock);
2021 if (priv->port_up) {
3484aac1 2022 mlx4_en_stop_port(dev, 1);
1e338db5 2023 if (mlx4_en_start_port(dev))
453a6082 2024 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 2025 }
2026 mutex_unlock(&mdev->state_lock);
0c5c3252 2027 rtnl_unlock();
c27a02cd
YP		 2028}
2029
b477ba62 2030static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 2031{
2032 struct mlx4_en_priv *priv = netdev_priv(dev);
2033 struct mlx4_en_dev *mdev = priv->mdev;
67f8b1dc 2034 struct mlx4_en_tx_ring **tx_ring;
c27a02cd 2035 int i;
c27a02cd 2036
eb4b6788
TT		 2037 if (!mlx4_is_slave(mdev->dev))
2038 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
2039 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd 2040
c27a02cd 2041 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 2042 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
2043 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 2044 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
2045 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
2046 memset(&priv->rx_priority_flowstats, 0,
2047 sizeof(priv->rx_priority_flowstats));
2048 memset(&priv->tx_priority_flowstats, 0,
2049 sizeof(priv->tx_priority_flowstats));
b42de4d0 2050 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
c27a02cd 2051
67f8b1dc
TT		 2052 tx_ring = priv->tx_ring[TX];
2053 for (i = 0; i < priv->tx_ring_num[TX]; i++) {
2054 tx_ring[i]->bytes = 0;
2055 tx_ring[i]->packets = 0;
2056 tx_ring[i]->tx_csum = 0;
2057 tx_ring[i]->tx_dropped = 0;
2058 tx_ring[i]->queue_stopped = 0;
2059 tx_ring[i]->wake_queue = 0;
2060 tx_ring[i]->tso_packets = 0;
2061 tx_ring[i]->xmit_more = 0;
c27a02cd
YP		 2062 }
2063 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 2064 priv->rx_ring[i]->bytes = 0;
2065 priv->rx_ring[i]->packets = 0;
2066 priv->rx_ring[i]->csum_ok = 0;
2067 priv->rx_ring[i]->csum_none = 0;
f8c6455b 2068 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 2069 }
b477ba62
EE		 2070}
2071
2072static int mlx4_en_open(struct net_device *dev)
2073{
2074 struct mlx4_en_priv *priv = netdev_priv(dev);
2075 struct mlx4_en_dev *mdev = priv->mdev;
2076 int err = 0;
2077
2078 mutex_lock(&mdev->state_lock);
2079
2080 if (!mdev->device_up) {
2081 en_err(priv, "Cannot open - device down/disabled\n");
2082 err = -EBUSY;
2083 goto out;
2084 }
2085
2086 /* Reset HW statistics and SW counters */
2087 mlx4_en_clear_stats(dev);
c27a02cd 2088
c27a02cd
YP		 2089 err = mlx4_en_start_port(dev);
2090 if (err)
453a6082 2091 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 2092
2093out:
2094 mutex_unlock(&mdev->state_lock);
2095 return err;
2096}
2097
2098
2099static int mlx4_en_close(struct net_device *dev)
2100{
2101 struct mlx4_en_priv *priv = netdev_priv(dev);
2102 struct mlx4_en_dev *mdev = priv->mdev;
2103
453a6082 2104 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 2105
2106 mutex_lock(&mdev->state_lock);
2107
3484aac1 2108 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 2109 netif_carrier_off(dev);
2110
2111 mutex_unlock(&mdev->state_lock);
2112 return 0;
2113}
2114
ec25bc04 2115static void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd 2116{
67f8b1dc 2117 int i, t;
c27a02cd 2118
1eb8c695 2119#ifdef CONFIG_RFS_ACCEL
1eb8c695
AV		 2120 priv->dev->rx_cpu_rmap = NULL;
2121#endif
2122
67f8b1dc
TT		 2123 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2124 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2125 if (priv->tx_ring[t] && priv->tx_ring[t][i])
2126 mlx4_en_destroy_tx_ring(priv,
2127 &priv->tx_ring[t][i]);
2128 if (priv->tx_cq[t] && priv->tx_cq[t][i])
2129 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2130 }
f32b20e8
MKL		 2131 kfree(priv->tx_ring[t]);
2132 kfree(priv->tx_cq[t]);
c27a02cd
YP		 2133 }
2134
2135 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 2136 if (priv->rx_ring[i])
68355f71
TLSC		 2137 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2138 priv->prof->rx_ring_size, priv->stride);
41d942d5 2139 if (priv->rx_cq[i])
fe0af03c 2140 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 2141 }
044ca2a5 2142
c27a02cd
YP		 2143}
2144
ec25bc04 2145static int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 2146{
c27a02cd 2147 struct mlx4_en_port_profile *prof = priv->prof;
67f8b1dc 2148 int i, t;
163561a4 2149 int node;
87a5c389 2150
c27a02cd 2151 /* Create tx Rings */
67f8b1dc
TT		 2152 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2153 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2154 node = cpu_to_node(i % num_online_cpus());
2155 if (mlx4_en_create_cq(priv, &priv->tx_cq[t][i],
2156 prof->tx_ring_size, i, t, node))
2157 goto err;
2158
2159 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[t][i],
2160 prof->tx_ring_size,
2161 TXBB_SIZE, node, i))
2162 goto err;
2163 }
c27a02cd
YP		 2164 }
2165
2166 /* Create rx Rings */
2167 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2168 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2169 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2170 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2171 goto err;
2172
2173 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4 2174 prof->rx_ring_size, priv->stride,
ae75415d 2175 node, i))
c27a02cd 2176 goto err;
ae75415d 2177
c27a02cd
YP		 2178 }
2179
1eb8c695 2180#ifdef CONFIG_RFS_ACCEL
c66fa19c 2181 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
1eb8c695
AV		 2182#endif
2183
c27a02cd
YP		 2184 return 0;
2185
2186err:
453a6082 2187 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2188 for (i = 0; i < priv->rx_ring_num; i++) {
2189 if (priv->rx_ring[i])
2190 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2191 prof->rx_ring_size,
2192 priv->stride);
2193 if (priv->rx_cq[i])
2194 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2195 }
67f8b1dc
TT		 2196 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2197 for (i = 0; i < priv->tx_ring_num[t]; i++) {
2198 if (priv->tx_ring[t][i])
2199 mlx4_en_destroy_tx_ring(priv,
2200 &priv->tx_ring[t][i]);
2201 if (priv->tx_cq[t][i])
2202 mlx4_en_destroy_cq(priv, &priv->tx_cq[t][i]);
2203 }
41d942d5 2204 }
c27a02cd
YP		 2205 return -ENOMEM;
2206}
2207
2208
ec25bc04
EE		 2209static int mlx4_en_copy_priv(struct mlx4_en_priv *dst,
2210 struct mlx4_en_priv *src,
2211 struct mlx4_en_port_profile *prof)
2212{
67f8b1dc
TT		 2213 int t;
2214
ec25bc04
EE		 2215 memcpy(&dst->hwtstamp_config, &prof->hwtstamp_config,
2216 sizeof(dst->hwtstamp_config));
ec327f7a 2217 dst->num_tx_rings_p_up = prof->num_tx_rings_p_up;
ec25bc04
EE		 2218 dst->rx_ring_num = prof->rx_ring_num;
2219 dst->flags = prof->flags;
2220 dst->mdev = src->mdev;
2221 dst->port = src->port;
2222 dst->dev = src->dev;
2223 dst->prof = prof;
2224 dst->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2225 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2226
67f8b1dc
TT		 2227 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2228 dst->tx_ring_num[t] = prof->tx_ring_num[t];
2229 if (!dst->tx_ring_num[t])
2230 continue;
ec25bc04 2231
67f8b1dc
TT		 2232 dst->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
2233 MAX_TX_RINGS, GFP_KERNEL);
2234 if (!dst->tx_ring[t])
2235 goto err_free_tx;
2236
2237 dst->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
2238 MAX_TX_RINGS, GFP_KERNEL);
2239 if (!dst->tx_cq[t]) {
2240 kfree(dst->tx_ring[t]);
2241 goto err_free_tx;
2242 }
ec25bc04 2243 }
67f8b1dc 2244
ec25bc04 2245 return 0;
67f8b1dc
TT		 2246
2247err_free_tx:
2248 while (t--) {
2249 kfree(dst->tx_ring[t]);
2250 kfree(dst->tx_cq[t]);
2251 }
2252 return -ENOMEM;
ec25bc04
EE		 2253}
2254
2255static void mlx4_en_update_priv(struct mlx4_en_priv *dst,
2256 struct mlx4_en_priv *src)
2257{
67f8b1dc 2258 int t;
ec25bc04
EE		 2259 memcpy(dst->rx_ring, src->rx_ring,
2260 sizeof(struct mlx4_en_rx_ring *) * src->rx_ring_num);
2261 memcpy(dst->rx_cq, src->rx_cq,
2262 sizeof(struct mlx4_en_cq *) * src->rx_ring_num);
2263 memcpy(&dst->hwtstamp_config, &src->hwtstamp_config,
2264 sizeof(dst->hwtstamp_config));
67f8b1dc
TT		 2265 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2266 dst->tx_ring_num[t] = src->tx_ring_num[t];
2267 dst->tx_ring[t] = src->tx_ring[t];
2268 dst->tx_cq[t] = src->tx_cq[t];
2269 }
ec327f7a 2270 dst->num_tx_rings_p_up = src->num_tx_rings_p_up;
ec25bc04 2271 dst->rx_ring_num = src->rx_ring_num;
ec25bc04
EE		 2272 memcpy(dst->prof, src->prof, sizeof(struct mlx4_en_port_profile));
2273}
2274
2275int mlx4_en_try_alloc_resources(struct mlx4_en_priv *priv,
2276 struct mlx4_en_priv *tmp,
770f8225
MKL		 2277 struct mlx4_en_port_profile *prof,
2278 bool carry_xdp_prog)
ec25bc04 2279{
770f8225
MKL		 2280 struct bpf_prog *xdp_prog;
2281 int i, t;
67f8b1dc 2282
ec25bc04
EE		 2283 mlx4_en_copy_priv(tmp, priv, prof);
2284
2285 if (mlx4_en_alloc_resources(tmp)) {
2286 en_warn(priv,
2287 "%s: Resource allocation failed, using previous configuration\n",
2288 __func__);
67f8b1dc
TT		 2289 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
2290 kfree(tmp->tx_ring[t]);
2291 kfree(tmp->tx_cq[t]);
2292 }
ec25bc04
EE		 2293 return -ENOMEM;
2294 }
770f8225
MKL		 2295
2296 /* All rx_rings has the same xdp_prog. Pick the first one. */
2297 xdp_prog = rcu_dereference_protected(
2298 priv->rx_ring[0]->xdp_prog,
2299 lockdep_is_held(&priv->mdev->state_lock));
2300
2301 if (xdp_prog && carry_xdp_prog) {
2302 xdp_prog = bpf_prog_add(xdp_prog, tmp->rx_ring_num);
2303 if (IS_ERR(xdp_prog)) {
2304 mlx4_en_free_resources(tmp);
2305 return PTR_ERR(xdp_prog);
2306 }
2307 for (i = 0; i < tmp->rx_ring_num; i++)
2308 rcu_assign_pointer(tmp->rx_ring[i]->xdp_prog,
2309 xdp_prog);
2310 }
2311
ec25bc04
EE		 2312 return 0;
2313}
2314
2315void mlx4_en_safe_replace_resources(struct mlx4_en_priv *priv,
2316 struct mlx4_en_priv *tmp)
2317{
2318 mlx4_en_free_resources(priv);
2319 mlx4_en_update_priv(priv, tmp);
2320}
2321
c27a02cd
YP		 2322void mlx4_en_destroy_netdev(struct net_device *dev)
2323{
2324 struct mlx4_en_priv *priv = netdev_priv(dev);
2325 struct mlx4_en_dev *mdev = priv->mdev;
2326
453a6082 2327 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2328
2329 /* Unregister device - this will close the port if it was up */
09d4d087
JP		 2330 if (priv->registered) {
2331 devlink_port_type_clear(mlx4_get_devlink_port(mdev->dev,
2332 priv->port));
b4353708 2333 unregister_netdev(dev);
09d4d087 2334 }
c27a02cd
YP		 2335
2336 if (priv->allocated)
2337 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2338
2339 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2340 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2341 /* flush any pending task for this netdev */
2342 flush_workqueue(mdev->workqueue);
2343
90683061
EE		 2344 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2345 mlx4_en_remove_timestamp(mdev);
2346
c27a02cd
YP		 2347 /* Detach the netdev so tasks would not attempt to access it */
2348 mutex_lock(&mdev->state_lock);
2349 mdev->pndev[priv->port] = NULL;
5da03547 2350 mdev->upper[priv->port] = NULL;
c27a02cd 2351
30f56e3c
EE		 2352#ifdef CONFIG_RFS_ACCEL
2353 mlx4_en_cleanup_filters(priv);
2354#endif
2355
fe0af03c 2356 mlx4_en_free_resources(priv);
b6e01232 2357 mutex_unlock(&mdev->state_lock);
564c274c 2358
b4353708 2359 free_netdev(dev);
c27a02cd
YP		 2360}
2361
b45f0674
MKL		 2362static bool mlx4_en_check_xdp_mtu(struct net_device *dev, int mtu)
2363{
2364 struct mlx4_en_priv *priv = netdev_priv(dev);
2365
2366 if (mtu > MLX4_EN_MAX_XDP_MTU) {
2367 en_err(priv, "mtu:%d > max:%d when XDP prog is attached\n",
2368 mtu, MLX4_EN_MAX_XDP_MTU);
2369 return false;
2370 }
2371
2372 return true;
2373}
2374
c27a02cd
YP		 2375static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2376{
2377 struct mlx4_en_priv *priv = netdev_priv(dev);
2378 struct mlx4_en_dev *mdev = priv->mdev;
2379 int err = 0;
2380
453a6082 2381 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2382 dev->mtu, new_mtu);
2383
b45f0674
MKL		 2384 if (priv->tx_ring_num[TX_XDP] &&
2385 !mlx4_en_check_xdp_mtu(dev, new_mtu))
9f9b74ef 2386 return -EOPNOTSUPP;
b45f0674 2387
c27a02cd
YP		 2388 dev->mtu = new_mtu;
2389
2390 if (netif_running(dev)) {
2391 mutex_lock(&mdev->state_lock);
2392 if (!mdev->device_up) {
2393 /* NIC is probably restarting - let watchdog task reset
2394 * the port */
453a6082 2395 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2396 } else {
3484aac1 2397 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2398 err = mlx4_en_start_port(dev);
2399 if (err) {
453a6082 2400 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2401 priv->port);
2402 queue_work(mdev->workqueue, &priv->watchdog_task);
2403 }
2404 }
2405 mutex_unlock(&mdev->state_lock);
2406 }
2407 return 0;
2408}
2409
100dbda8 2410static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2411{
2412 struct mlx4_en_priv *priv = netdev_priv(dev);
2413 struct mlx4_en_dev *mdev = priv->mdev;
2414 struct hwtstamp_config config;
2415
2416 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2417 return -EFAULT;
2418
2419 /* reserved for future extensions */
2420 if (config.flags)
2421 return -EINVAL;
2422
2423 /* device doesn't support time stamping */
2424 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2425 return -EINVAL;
2426
2427 /* TX HW timestamp */
2428 switch (config.tx_type) {
2429 case HWTSTAMP_TX_OFF:
2430 case HWTSTAMP_TX_ON:
2431 break;
2432 default:
2433 return -ERANGE;
2434 }
2435
2436 /* RX HW timestamp */
2437 switch (config.rx_filter) {
2438 case HWTSTAMP_FILTER_NONE:
2439 break;
2440 case HWTSTAMP_FILTER_ALL:
2441 case HWTSTAMP_FILTER_SOME:
2442 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2443 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2444 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2445 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2446 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2447 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2448 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2449 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2450 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2451 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2452 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2453 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
e3412575 2454 case HWTSTAMP_FILTER_NTP_ALL:
ec693d47
AV		 2455 config.rx_filter = HWTSTAMP_FILTER_ALL;
2456 break;
2457 default:
2458 return -ERANGE;
2459 }
2460
7787fa66 2461 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2462 config.tx_type = HWTSTAMP_TX_OFF;
2463 config.rx_filter = HWTSTAMP_FILTER_NONE;
2464 }
2465
2466 return copy_to_user(ifr->ifr_data, &config,
2467 sizeof(config)) ? -EFAULT : 0;
2468}
2469
100dbda8
BH		 2470static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2471{
2472 struct mlx4_en_priv *priv = netdev_priv(dev);
2473
2474 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2475 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2476}
2477
ec693d47
AV		 2478static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2479{
2480 switch (cmd) {
2481 case SIOCSHWTSTAMP:
100dbda8
BH		 2482 return mlx4_en_hwtstamp_set(dev, ifr);
2483 case SIOCGHWTSTAMP:
2484 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2485 default:
2486 return -EOPNOTSUPP;
2487 }
2488}
2489
e38af4fa
HHZ		 2490static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2491 netdev_features_t features)
2492{
2493 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2494 struct mlx4_en_dev *mdev = en_priv->mdev;
2495
2496 /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2497 * enable/disable make sure S-TAG flag is always in same state as
2498 * C-TAG.
2499 */
2500 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2501 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2502 features |= NETIF_F_HW_VLAN_STAG_RX;
2503 else
2504 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2505
2506 return features;
2507}
2508
60d6fe99
AV		 2509static int mlx4_en_set_features(struct net_device *netdev,
2510 netdev_features_t features)
2511{
2512 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2513 bool reset = false;
537f6f95
SM		 2514 int ret = 0;
2515
f0df3503
MM		 2516 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2517 en_info(priv, "Turn %s RX-FCS\n",
2518 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2519 reset = true;
2520 }
2521
78500b8c
MM		 2522 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2523 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2524
2525 en_info(priv, "Turn %s RX-ALL\n",
2526 ignore_fcs_value ? "ON" : "OFF");
2527 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2528 priv->port, ignore_fcs_value);
2529 if (ret)
2530 return ret;
2531 }
2532
537f6f95
SM		 2533 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2534 en_info(priv, "Turn %s RX vlan strip offload\n",
2535 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2536 reset = true;
537f6f95 2537 }
60d6fe99 2538
cfb53f36
IS		 2539 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2540 en_info(priv, "Turn %s TX vlan strip offload\n",
2541 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2542
e38af4fa
HHZ		 2543 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2544 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2545 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2546
241a08c3
IS		 2547 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2548 en_info(priv, "Turn %s loopback\n",
2549 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2550 mlx4_en_update_loopback_state(netdev, features);
2551 }
79aeaccd 2552
f0df3503
MM		 2553 if (reset) {
2554 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2555 features);
2556 if (ret)
2557 return ret;
2558 }
60d6fe99 2559
f0df3503 2560 return 0;
60d6fe99
AV		 2561}
2562
8f7ba3ca
RE		 2563static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2564{
2565 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2566 struct mlx4_en_dev *mdev = en_priv->mdev;
8f7ba3ca 2567
745d8ae4 2568 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac);
8f7ba3ca
RE		 2569}
2570
79aab093
MS		 2571static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
2572 __be16 vlan_proto)
3f7fb021
RE		 2573{
2574 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2575 struct mlx4_en_dev *mdev = en_priv->mdev;
2576
b42959dc
MS		 2577 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos,
2578 vlan_proto);
3f7fb021
RE		 2579}
2580
cda373f4
IS		 2581static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2582 int max_tx_rate)
2583{
2584 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2585 struct mlx4_en_dev *mdev = en_priv->mdev;
2586
2587 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2588 max_tx_rate);
2589}
2590
e6b6a231
RE		 2591static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2592{
2593 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2594 struct mlx4_en_dev *mdev = en_priv->mdev;
2595
2596 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2597}
2598
2cccb9e4
RE		 2599static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2600{
2601 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2602 struct mlx4_en_dev *mdev = en_priv->mdev;
2603
2604 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2605}
8f7ba3ca 2606
948e306d
RE		 2607static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2608{
2609 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2610 struct mlx4_en_dev *mdev = en_priv->mdev;
2611
2612 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2613}
84c86403 2614
62a89055
EBE		 2615static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2616 struct ifla_vf_stats *vf_stats)
2617{
2618 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2619 struct mlx4_en_dev *mdev = en_priv->mdev;
2620
2621 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2622}
2623
84c86403
HHZ		 2624#define PORT_ID_BYTE_LEN 8
2625static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2626 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2627{
2628 struct mlx4_en_priv *priv = netdev_priv(dev);
2629 struct mlx4_dev *mdev = priv->mdev->dev;
2630 int i;
2631 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2632
2633 if (!phys_port_id)
2634 return -EOPNOTSUPP;
2635
2636 ppid->id_len = sizeof(phys_port_id);
2637 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2638 ppid->id[i] = phys_port_id & 0xff;
2639 phys_port_id >>= 8;
2640 }
2641 return 0;
2642}
2643
1b136de1
OG		 2644static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2645{
2646 int ret;
2647 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2648 vxlan_add_task);
2649
2650 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2651 if (ret)
2652 goto out;
2653
2654 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2655 VXLAN_STEER_BY_OUTER_MAC, 1);
2656out:
f4a1edd5 2657 if (ret) {
1b136de1 2658 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2659 return;
2660 }
2661
2662 /* set offloads */
09067122
AD		 2663 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2664 NETIF_F_RXCSUM |
2665 NETIF_F_TSO | NETIF_F_TSO6 |
2666 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2667 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2668 NETIF_F_GSO_PARTIAL;
1b136de1
OG		 2669}
2670
2671static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2672{
2673 int ret;
2674 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2675 vxlan_del_task);
f4a1edd5 2676 /* unset offloads */
09067122
AD		 2677 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2678 NETIF_F_RXCSUM |
2679 NETIF_F_TSO | NETIF_F_TSO6 |
2680 NETIF_F_GSO_UDP_TUNNEL |
3c9346b2
AD		 2681 NETIF_F_GSO_UDP_TUNNEL_CSUM |
2682 NETIF_F_GSO_PARTIAL);
1b136de1
OG		 2683
2684 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2685 VXLAN_STEER_BY_OUTER_MAC, 0);
2686 if (ret)
2687 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2688
2689 priv->vxlan_port = 0;
2690}
2691
2692static void mlx4_en_add_vxlan_port(struct net_device *dev,
a831274a 2693 struct udp_tunnel_info *ti)
1b136de1
OG		 2694{
2695 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2696 __be16 port = ti->port;
1b136de1
OG		 2697 __be16 current_port;
2698
a831274a 2699 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2700 return;
2701
a831274a
AD		 2702 if (ti->sa_family != AF_INET)
2703 return;
2704
2705 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2706 return;
2707
2708 current_port = priv->vxlan_port;
2709 if (current_port && current_port != port) {
2710 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2711 ntohs(current_port), ntohs(port));
2712 return;
2713 }
2714
2715 priv->vxlan_port = port;
2716 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2717}
2718
2719static void mlx4_en_del_vxlan_port(struct net_device *dev,
a831274a 2720 struct udp_tunnel_info *ti)
1b136de1
OG		 2721{
2722 struct mlx4_en_priv *priv = netdev_priv(dev);
a831274a 2723 __be16 port = ti->port;
1b136de1
OG		 2724 __be16 current_port;
2725
a831274a 2726 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
1b136de1
OG		 2727 return;
2728
a831274a
AD		 2729 if (ti->sa_family != AF_INET)
2730 return;
2731
2732 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2733 return;
2734
2735 current_port = priv->vxlan_port;
2736 if (current_port != port) {
2737 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2738 return;
2739 }
2740
2741 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2742}
956bdab2 2743
5f35227e
JG		 2744static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2745 struct net_device *dev,
2746 netdev_features_t features)
956bdab2 2747{
8cb65d00 2748 features = vlan_features_check(skb, features);
09067122
AD		 2749 features = vxlan_features_check(skb, features);
2750
2751 /* The ConnectX-3 doesn't support outer IPv6 checksums but it does
2752 * support inner IPv6 checksums and segmentation so we need to
2753 * strip that feature if this is an IPv6 encapsulated frame.
2754 */
2755 if (skb->encapsulation &&
a547224d
AD		 2756 (skb->ip_summed == CHECKSUM_PARTIAL)) {
2757 struct mlx4_en_priv *priv = netdev_priv(dev);
2758
2759 if (!priv->vxlan_port ||
2760 (ip_hdr(skb)->version != 4) ||
2761 (udp_hdr(skb)->dest != priv->vxlan_port))
2762 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2763 }
09067122
AD		 2764
2765 return features;
956bdab2 2766}
1b136de1 2767
de1cf8a7 2768static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2769{
2770 struct mlx4_en_priv *priv = netdev_priv(dev);
67f8b1dc 2771 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[TX][queue_index];
c10e4fc6
OG		 2772 struct mlx4_update_qp_params params;
2773 int err;
2774
2775 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2776 return -EOPNOTSUPP;
2777
2778 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2779 if (maxrate >> 12) {
2780 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2781 params.rate_val = maxrate / 1000;
2782 } else if (maxrate) {
2783 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2784 params.rate_val = maxrate;
2785 } else { /* zero serves to revoke the QP rate-limitation */
2786 params.rate_unit = 0;
2787 params.rate_val = 0;
2788 }
2789
2790 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2791 &params);
2792 return err;
2793}
2794
47a38e15
BB		 2795static int mlx4_xdp_set(struct net_device *dev, struct bpf_prog *prog)
2796{
2797 struct mlx4_en_priv *priv = netdev_priv(dev);
d576acf0 2798 struct mlx4_en_dev *mdev = priv->mdev;
67f8b1dc 2799 struct mlx4_en_port_profile new_prof;
47a38e15 2800 struct bpf_prog *old_prog;
67f8b1dc
TT		 2801 struct mlx4_en_priv *tmp;
2802 int tx_changed = 0;
47a38e15 2803 int xdp_ring_num;
d576acf0
BB		 2804 int port_up = 0;
2805 int err;
47a38e15
BB		 2806 int i;
2807
67f8b1dc 2808 xdp_ring_num = prog ? priv->rx_ring_num : 0;
47a38e15 2809
d576acf0
BB		 2810 /* No need to reconfigure buffers when simply swapping the
2811 * program for a new one.
2812 */
67f8b1dc 2813 if (priv->tx_ring_num[TX_XDP] == xdp_ring_num) {
d576acf0
BB		 2814 if (prog) {
2815 prog = bpf_prog_add(prog, priv->rx_ring_num - 1);
2816 if (IS_ERR(prog))
2817 return PTR_ERR(prog);
2818 }
326fe02d 2819 mutex_lock(&mdev->state_lock);
d576acf0 2820 for (i = 0; i < priv->rx_ring_num; i++) {
326fe02d
BB		 2821 old_prog = rcu_dereference_protected(
2822 priv->rx_ring[i]->xdp_prog,
2823 lockdep_is_held(&mdev->state_lock));
2824 rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
d576acf0
BB		 2825 if (old_prog)
2826 bpf_prog_put(old_prog);
2827 }
326fe02d 2828 mutex_unlock(&mdev->state_lock);
d576acf0
BB		 2829 return 0;
2830 }
2831
b45f0674 2832 if (!mlx4_en_check_xdp_mtu(dev, dev->mtu))
47a38e15 2833 return -EOPNOTSUPP;
47a38e15 2834
67f8b1dc
TT		 2835 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
2836 if (!tmp)
2837 return -ENOMEM;
9ecc2d86 2838
47a38e15
BB		 2839 if (prog) {
2840 prog = bpf_prog_add(prog, priv->rx_ring_num - 1);
67f8b1dc
TT		 2841 if (IS_ERR(prog)) {
2842 err = PTR_ERR(prog);
2843 goto out;
2844 }
47a38e15
BB		 2845 }
2846
d576acf0 2847 mutex_lock(&mdev->state_lock);
67f8b1dc
TT		 2848 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
2849 new_prof.tx_ring_num[TX_XDP] = xdp_ring_num;
2850
2851 if (priv->tx_ring_num[TX] + xdp_ring_num > MAX_TX_RINGS) {
2852 tx_changed = 1;
2853 new_prof.tx_ring_num[TX] =
f21ad614 2854 MAX_TX_RINGS - ALIGN(xdp_ring_num, priv->prof->num_up);
67f8b1dc
TT		 2855 en_warn(priv, "Reducing the number of TX rings, to not exceed the max total rings number.\n");
2856 }
2857
770f8225 2858 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, false);
c540594f
DB		 2859 if (err) {
2860 if (prog)
2861 bpf_prog_sub(prog, priv->rx_ring_num - 1);
67f8b1dc 2862 goto unlock_out;
c540594f 2863 }
67f8b1dc 2864
d576acf0
BB		 2865 if (priv->port_up) {
2866 port_up = 1;
2867 mlx4_en_stop_port(dev, 1);
2868 }
2869
67f8b1dc
TT		 2870 mlx4_en_safe_replace_resources(priv, tmp);
2871 if (tx_changed)
2872 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
47a38e15 2873
47a38e15 2874 for (i = 0; i < priv->rx_ring_num; i++) {
326fe02d
BB		 2875 old_prog = rcu_dereference_protected(
2876 priv->rx_ring[i]->xdp_prog,
2877 lockdep_is_held(&mdev->state_lock));
2878 rcu_assign_pointer(priv->rx_ring[i]->xdp_prog, prog);
47a38e15
BB		 2879 if (old_prog)
2880 bpf_prog_put(old_prog);
2881 }
2882
d576acf0
BB		 2883 if (port_up) {
2884 err = mlx4_en_start_port(dev);
2885 if (err) {
2886 en_err(priv, "Failed starting port %d for XDP change\n",
2887 priv->port);
2888 queue_work(mdev->workqueue, &priv->watchdog_task);
2889 }
2890 }
2891
67f8b1dc 2892unlock_out:
d576acf0 2893 mutex_unlock(&mdev->state_lock);
67f8b1dc
TT		 2894out:
2895 kfree(tmp);
2896 return err;
47a38e15
BB		 2897}
2898
2e37e9b0 2899static u32 mlx4_xdp_query(struct net_device *dev)
47a38e15
BB		 2900{
2901 struct mlx4_en_priv *priv = netdev_priv(dev);
2e37e9b0
MKL		 2902 struct mlx4_en_dev *mdev = priv->mdev;
2903 const struct bpf_prog *xdp_prog;
2904 u32 prog_id = 0;
2905
2906 if (!priv->tx_ring_num[TX_XDP])
2907 return prog_id;
2908
2909 mutex_lock(&mdev->state_lock);
2910 xdp_prog = rcu_dereference_protected(
2911 priv->rx_ring[0]->xdp_prog,
2912 lockdep_is_held(&mdev->state_lock));
2913 if (xdp_prog)
2914 prog_id = xdp_prog->aux->id;
2915 mutex_unlock(&mdev->state_lock);
47a38e15 2916
2e37e9b0 2917 return prog_id;
47a38e15
BB		 2918}
2919
f4e63525 2920static int mlx4_xdp(struct net_device *dev, struct netdev_bpf *xdp)
47a38e15
BB		 2921{
2922 switch (xdp->command) {
2923 case XDP_SETUP_PROG:
2924 return mlx4_xdp_set(dev, xdp->prog);
2925 case XDP_QUERY_PROG:
2e37e9b0
MKL		 2926 xdp->prog_id = mlx4_xdp_query(dev);
2927 xdp->prog_attached = !!xdp->prog_id;
47a38e15
BB		 2928 return 0;
2929 default:
2930 return -EINVAL;
2931 }
2932}
2933
3addc568
SH		 2934static const struct net_device_ops mlx4_netdev_ops = {
2935 .ndo_open = mlx4_en_open,
2936 .ndo_stop = mlx4_en_close,
2937 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2938 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2939 .ndo_get_stats64 = mlx4_en_get_stats64,
0eb74fdd 2940 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2941 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2942 .ndo_validate_addr = eth_validate_addr,
3addc568 2943 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2944 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2945 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2946 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2947 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2948#ifdef CONFIG_NET_POLL_CONTROLLER
2949 .ndo_poll_controller = mlx4_en_netpoll,
2950#endif
60d6fe99 2951 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2952 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2953 .ndo_setup_tc = __mlx4_en_setup_tc,
1eb8c695
AV		 2954#ifdef CONFIG_RFS_ACCEL
2955 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
9e77a2b8 2956#endif
84c86403 2957 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2958 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2959 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2960 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2961 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
f4e63525 2962 .ndo_bpf = mlx4_xdp,
3addc568
SH		 2963};
2964
8f7ba3ca
RE		 2965static const struct net_device_ops mlx4_netdev_ops_master = {
2966 .ndo_open = mlx4_en_open,
2967 .ndo_stop = mlx4_en_close,
2968 .ndo_start_xmit = mlx4_en_xmit,
2969 .ndo_select_queue = mlx4_en_select_queue,
9ed17db1 2970 .ndo_get_stats64 = mlx4_en_get_stats64,
8f7ba3ca
RE		 2971 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2972 .ndo_set_mac_address = mlx4_en_set_mac,
2973 .ndo_validate_addr = eth_validate_addr,
2974 .ndo_change_mtu = mlx4_en_change_mtu,
2975 .ndo_tx_timeout = mlx4_en_tx_timeout,
2976 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2977 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2978 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2979 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2980 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2981 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2982 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
62a89055 2983 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2cccb9e4 2984 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2985#ifdef CONFIG_NET_POLL_CONTROLLER
2986 .ndo_poll_controller = mlx4_en_netpoll,
2987#endif
2988 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2989 .ndo_fix_features = mlx4_en_fix_features,
e4c6734e 2990 .ndo_setup_tc = __mlx4_en_setup_tc,
8f7ba3ca
RE		 2991#ifdef CONFIG_RFS_ACCEL
2992 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2993#endif
84c86403 2994 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a831274a
AD		 2995 .ndo_udp_tunnel_add = mlx4_en_add_vxlan_port,
2996 .ndo_udp_tunnel_del = mlx4_en_del_vxlan_port,
5f35227e 2997 .ndo_features_check = mlx4_en_features_check,
c10e4fc6 2998 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
f4e63525 2999 .ndo_bpf = mlx4_xdp,
8f7ba3ca
RE		 3000};
3001
5da03547
MS		 3002struct mlx4_en_bond {
3003 struct work_struct work;
3004 struct mlx4_en_priv *priv;
3005 int is_bonded;
3006 struct mlx4_port_map port_map;
3007};
3008
3009static void mlx4_en_bond_work(struct work_struct *work)
3010{
3011 struct mlx4_en_bond *bond = container_of(work,
3012 struct mlx4_en_bond,
3013 work);
3014 int err = 0;
3015 struct mlx4_dev *dev = bond->priv->mdev->dev;
3016
3017 if (bond->is_bonded) {
3018 if (!mlx4_is_bonded(dev)) {
3019 err = mlx4_bond(dev);
3020 if (err)
3021 en_err(bond->priv, "Fail to bond device\n");
3022 }
3023 if (!err) {
3024 err = mlx4_port_map_set(dev, &bond->port_map);
3025 if (err)
3026 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
3027 bond->port_map.port1,
3028 bond->port_map.port2,
3029 err);
3030 }
3031 } else if (mlx4_is_bonded(dev)) {
3032 err = mlx4_unbond(dev);
3033 if (err)
3034 en_err(bond->priv, "Fail to unbond device\n");
3035 }
3036 dev_put(bond->priv->dev);
3037 kfree(bond);
3038}
3039
3040static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
3041 u8 v2p_p1, u8 v2p_p2)
3042{
3043 struct mlx4_en_bond *bond = NULL;
3044
3045 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
3046 if (!bond)
3047 return -ENOMEM;
3048
3049 INIT_WORK(&bond->work, mlx4_en_bond_work);
3050 bond->priv = priv;
3051 bond->is_bonded = is_bonded;
3052 bond->port_map.port1 = v2p_p1;
3053 bond->port_map.port2 = v2p_p2;
3054 dev_hold(priv->dev);
3055 queue_work(priv->mdev->workqueue, &bond->work);
3056 return 0;
3057}
3058
3059int mlx4_en_netdev_event(struct notifier_block *this,
3060 unsigned long event, void *ptr)
3061{
3062 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3063 u8 port = 0;
3064 struct mlx4_en_dev *mdev;
3065 struct mlx4_dev *dev;
3066 int i, num_eth_ports = 0;
3067 bool do_bond = true;
3068 struct mlx4_en_priv *priv;
3069 u8 v2p_port1 = 0;
3070 u8 v2p_port2 = 0;
3071
3072 if (!net_eq(dev_net(ndev), &init_net))
3073 return NOTIFY_DONE;
3074
3075 mdev = container_of(this, struct mlx4_en_dev, nb);
3076 dev = mdev->dev;
3077
3078 /* Go into this mode only when two network devices set on two ports
3079 * of the same mlx4 device are slaves of the same bonding master
3080 */
3081 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
3082 ++num_eth_ports;
3083 if (!port && (mdev->pndev[i] == ndev))
3084 port = i;
3085 mdev->upper[i] = mdev->pndev[i] ?
3086 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
3087 /* condition not met: network device is a slave */
3088 if (!mdev->upper[i])
3089 do_bond = false;
3090 if (num_eth_ports < 2)
3091 continue;
3092 /* condition not met: same master */
3093 if (mdev->upper[i] != mdev->upper[i-1])
3094 do_bond = false;
3095 }
3096 /* condition not met: 2 salves */
3097 do_bond = (num_eth_ports == 2) ? do_bond : false;
3098
3099 /* handle only events that come with enough info */
3100 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
3101 return NOTIFY_DONE;
3102
3103 priv = netdev_priv(ndev);
3104 if (do_bond) {
3105 struct netdev_notifier_bonding_info *notifier_info = ptr;
3106 struct netdev_bonding_info *bonding_info =
3107 &notifier_info->bonding_info;
3108
3109 /* required mode 1, 2 or 4 */
3110 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
3111 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
3112 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
3113 do_bond = false;
3114
3115 /* require exactly 2 slaves */
3116 if (bonding_info->master.num_slaves != 2)
3117 do_bond = false;
3118
3119 /* calc v2p */
3120 if (do_bond) {
3121 if (bonding_info->master.bond_mode ==
3122 BOND_MODE_ACTIVEBACKUP) {
3123 /* in active-backup mode virtual ports are
3124 * mapped to the physical port of the active
3125 * slave */
3126 if (bonding_info->slave.state ==
3127 BOND_STATE_BACKUP) {
3128 if (port == 1) {
3129 v2p_port1 = 2;
3130 v2p_port2 = 2;
3131 } else {
3132 v2p_port1 = 1;
3133 v2p_port2 = 1;
3134 }
3135 } else { /* BOND_STATE_ACTIVE */
3136 if (port == 1) {
3137 v2p_port1 = 1;
3138 v2p_port2 = 1;
3139 } else {
3140 v2p_port1 = 2;
3141 v2p_port2 = 2;
3142 }
3143 }
3144 } else { /* Active-Active */
3145 /* in active-active mode a virtual port is
3146 * mapped to the native physical port if and only
3147 * if the physical port is up */
3148 __s8 link = bonding_info->slave.link;
3149
3150 if (port == 1)
3151 v2p_port2 = 2;
3152 else
3153 v2p_port1 = 1;
3154 if ((link == BOND_LINK_UP) ||
3155 (link == BOND_LINK_FAIL)) {
3156 if (port == 1)
3157 v2p_port1 = 1;
3158 else
3159 v2p_port2 = 2;
3160 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
3161 if (port == 1)
3162 v2p_port1 = 2;
3163 else
3164 v2p_port2 = 1;
3165 }
3166 }
3167 }
3168 }
3169
3170 mlx4_en_queue_bond_work(priv, do_bond,
3171 v2p_port1, v2p_port2);
3172
3173 return NOTIFY_DONE;
3174}
3175
0b131561
MB		 3176void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
3177 struct mlx4_en_stats_bitmap *stats_bitmap,
3178 u8 rx_ppp, u8 rx_pause,
3179 u8 tx_ppp, u8 tx_pause)
3180{
b42de4d0 3181 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
0b131561
MB		 3182
3183 if (!mlx4_is_slave(dev) &&
3184 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
3185 mutex_lock(&stats_bitmap->mutex);
3186 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
3187
3188 if (rx_ppp)
3189 bitmap_set(stats_bitmap->bitmap, last_i,
3190 NUM_FLOW_PRIORITY_STATS_RX);
3191 last_i += NUM_FLOW_PRIORITY_STATS_RX;
3192
3193 if (rx_pause && !(rx_ppp))
3194 bitmap_set(stats_bitmap->bitmap, last_i,
3195 NUM_FLOW_STATS_RX);
3196 last_i += NUM_FLOW_STATS_RX;
3197
3198 if (tx_ppp)
3199 bitmap_set(stats_bitmap->bitmap, last_i,
3200 NUM_FLOW_PRIORITY_STATS_TX);
3201 last_i += NUM_FLOW_PRIORITY_STATS_TX;
3202
3203 if (tx_pause && !(tx_ppp))
3204 bitmap_set(stats_bitmap->bitmap, last_i,
3205 NUM_FLOW_STATS_TX);
3206 last_i += NUM_FLOW_STATS_TX;
3207
3208 mutex_unlock(&stats_bitmap->mutex);
3209 }
3210}
3211
6fcd2735 3212void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 3213 struct mlx4_en_stats_bitmap *stats_bitmap,
3214 u8 rx_ppp, u8 rx_pause,
3215 u8 tx_ppp, u8 tx_pause)
ffa88f37 3216{
6fcd2735
EBE		 3217 int last_i = 0;
3218
3da8a36c
EBE		 3219 mutex_init(&stats_bitmap->mutex);
3220 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 3221
3222 if (mlx4_is_slave(dev)) {
3da8a36c 3223 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3224 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 3225 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3226 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 3227 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3228 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 3229 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3230 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 3231 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 3232 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 3233 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 3234 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
3235 } else {
3da8a36c 3236 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 3237 }
6fcd2735 3238 last_i += NUM_MAIN_STATS;
ffa88f37 3239
3da8a36c 3240 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 3241 last_i += NUM_PORT_STATS;
ffa88f37 3242
b42de4d0
EBE		 3243 if (mlx4_is_master(dev))
3244 bitmap_set(stats_bitmap->bitmap, last_i,
3245 NUM_PF_STATS);
3246 last_i += NUM_PF_STATS;
3247
0b131561
MB		 3248 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
3249 rx_ppp, rx_pause,
3250 tx_ppp, tx_pause);
3251 last_i += NUM_FLOW_STATS;
3252
6fcd2735 3253 if (!mlx4_is_slave(dev))
3da8a36c 3254 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
15fca2c8
TT		 3255 last_i += NUM_PKT_STATS;
3256
3257 bitmap_set(stats_bitmap->bitmap, last_i, NUM_XDP_STATS);
3258 last_i += NUM_XDP_STATS;
f26d0d25
EBE		 3259
3260 if (!mlx4_is_slave(dev))
3261 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PHY_STATS);
3262 last_i += NUM_PHY_STATS;
ffa88f37
EBE		 3263}
3264
c27a02cd
YP		 3265int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
3266 struct mlx4_en_port_profile *prof)
3267{
3268 struct net_device *dev;
3269 struct mlx4_en_priv *priv;
67f8b1dc 3270 int i, t;
c27a02cd
YP		 3271 int err;
3272
f1593d22 3273 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 3274 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 3275 if (dev == NULL)
c27a02cd 3276 return -ENOMEM;
c27a02cd 3277
67f8b1dc 3278 netif_set_real_num_tx_queues(dev, prof->tx_ring_num[TX]);
d317966b
AV		 3279 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
3280
872bf2fb 3281 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 3282 dev->dev_port = port - 1;
c27a02cd
YP		 3283
3284 /*
3285 * Initialize driver private data
3286 */
3287
3288 priv = netdev_priv(dev);
3289 memset(priv, 0, sizeof(struct mlx4_en_priv));
6de5f7f6 3290 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
207af6c5
EE		 3291 spin_lock_init(&priv->stats_lock);
3292 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
3293 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
3294 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
3295 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
3296 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
207af6c5
EE		 3297 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
3298 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
207af6c5
EE		 3299#ifdef CONFIG_RFS_ACCEL
3300 INIT_LIST_HEAD(&priv->filters);
3301 spin_lock_init(&priv->filters_lock);
3302#endif
3303
c27a02cd
YP		 3304 priv->dev = dev;
3305 priv->mdev = mdev;
ebf8c9aa 3306 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 3307 priv->prof = prof;
3308 priv->port = port;
3309 priv->port_up = false;
c27a02cd 3310 priv->flags = prof->flags;
0fef9d03 3311 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 3312 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
3313 MLX4_WQE_CTRL_SOLICITED);
7e1dc5e9 3314 priv->num_tx_rings_p_up = mdev->profile.max_num_tx_rings_p_up;
fbc6daf1 3315 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 3316 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 3317
67f8b1dc
TT		 3318 for (t = 0; t < MLX4_EN_NUM_TX_TYPES; t++) {
3319 priv->tx_ring_num[t] = prof->tx_ring_num[t];
3320 if (!priv->tx_ring_num[t])
3321 continue;
3322
3323 priv->tx_ring[t] = kzalloc(sizeof(struct mlx4_en_tx_ring *) *
3324 MAX_TX_RINGS, GFP_KERNEL);
3325 if (!priv->tx_ring[t]) {
3326 err = -ENOMEM;
a577d868 3327 goto out;
67f8b1dc
TT		 3328 }
3329 priv->tx_cq[t] = kzalloc(sizeof(struct mlx4_en_cq *) *
3330 MAX_TX_RINGS, GFP_KERNEL);
3331 if (!priv->tx_cq[t]) {
67f8b1dc
TT		 3332 err = -ENOMEM;
3333 goto out;
3334 }
bc6a4744 3335 }
c27a02cd 3336 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 3337 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 3338 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 3339 priv->mac_index = -1;
3340 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 3341#ifdef CONFIG_MLX4_EN_DCB
540b3a39 3342 if (!mlx4_is_slave(priv->mdev->dev)) {
a42b63c1
MS		 3343 u8 prio;
3344
3345 for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; ++prio) {
3346 priv->ets.prio_tc[prio] = prio;
3347 priv->ets.tc_tsa[prio] = IEEE_8021QAZ_TSA_VENDOR;
3348 }
3349
564ed9b1
TT		 3350 priv->dcbx_cap = DCB_CAP_DCBX_VER_CEE | DCB_CAP_DCBX_HOST |
3351 DCB_CAP_DCBX_VER_IEEE;
af7d5185 3352 priv->flags |= MLX4_EN_DCB_ENABLED;
564ed9b1 3353 priv->cee_config.pfc_state = false;
af7d5185 3354
f21ad614 3355 for (i = 0; i < MLX4_EN_NUM_UP_HIGH; i++)
564ed9b1 3356 priv->cee_config.dcb_pfc[i] = pfc_disabled;
af7d5185 3357
3742cc65 3358 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 3359 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
3360 } else {
3361 en_info(priv, "enabling only PFC DCB ops\n");
3362 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
3363 }
3364 }
564c274c 3365#endif
c27a02cd 3366
c07cb4b0
YB		 3367 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
3368 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 3369
c27a02cd
YP		 3370 /* Query for default mac and max mtu */
3371 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 3372
f8c6455b
SM		 3373 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
3374 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
3375 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
3376
6bbb6d99
YB		 3377 /* Set default MAC */
3378 dev->addr_len = ETH_ALEN;
3379 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
3380 if (!is_valid_ether_addr(dev->dev_addr)) {
2b3ddf27
JM		 3381 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
3382 priv->port, dev->dev_addr);
3383 err = -EINVAL;
3384 goto out;
3385 } else if (mlx4_is_slave(priv->mdev->dev) &&
3386 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
3387 /* Random MAC was assigned in mlx4_slave_cap
3388 * in mlx4_core module
3389 */
3390 dev->addr_assign_type |= NET_ADDR_RANDOM;
3391 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
c27a02cd
YP		 3392 }
3393
2695bab2 3394 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 3395
c27a02cd
YP		 3396 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
3397 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
3398 err = mlx4_en_alloc_resources(priv);
3399 if (err)
3400 goto out;
3401
ec693d47
AV		 3402 /* Initialize time stamping config */
3403 priv->hwtstamp_config.flags = 0;
3404 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
3405 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
3406
c27a02cd
YP		 3407 /* Allocate page for receive rings */
3408 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
73898db0 3409 MLX4_EN_PAGE_SIZE);
c27a02cd 3410 if (err) {
453a6082 3411 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 3412 goto out;
3413 }
3414 priv->allocated = 1;
3415
c27a02cd
YP		 3416 /*
3417 * Initialize netdev entry points
3418 */
8f7ba3ca
RE		 3419 if (mlx4_is_master(priv->mdev->dev))
3420 dev->netdev_ops = &mlx4_netdev_ops_master;
3421 else
3422 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 3423 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
67f8b1dc 3424 netif_set_real_num_tx_queues(dev, priv->tx_ring_num[TX]);
1eb63a28 3425 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 3426
7ad24ea4 3427 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 3428
c27a02cd
YP		 3429 /*
3430 * Set driver features
3431 */
c8c64cff
MM		 3432 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
3433 if (mdev->LSO_support)
3434 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
3435
3436 dev->vlan_features = dev->hw_features;
3437
ad86107f 3438 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 3439 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 3440 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
3441 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 3442 dev->hw_features |= NETIF_F_LOOPBACK |
3443 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 3444
e38af4fa
HHZ		 3445 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
3446 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
3447 NETIF_F_HW_VLAN_STAG_FILTER;
3448 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
3449 }
3450
3451 if (mlx4_is_slave(mdev->dev)) {
0815fe3a 3452 bool vlan_offload_disabled;
e38af4fa
HHZ		 3453 int phv;
3454
3455 err = get_phv_bit(mdev->dev, port, &phv);
3456 if (!err && phv) {
3457 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3458 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
3459 }
0815fe3a
MS		 3460 err = mlx4_get_is_vlan_offload_disabled(mdev->dev, port,
3461 &vlan_offload_disabled);
3462 if (!err && vlan_offload_disabled) {
3463 dev->hw_features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3464 NETIF_F_HW_VLAN_CTAG_RX |
3465 NETIF_F_HW_VLAN_STAG_TX |
3466 NETIF_F_HW_VLAN_STAG_RX);
3467 dev->features &= ~(NETIF_F_HW_VLAN_CTAG_TX |
3468 NETIF_F_HW_VLAN_CTAG_RX |
3469 NETIF_F_HW_VLAN_STAG_TX |
3470 NETIF_F_HW_VLAN_STAG_RX);
3471 }
e38af4fa
HHZ		 3472 } else {
3473 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
3474 !(mdev->dev->caps.flags2 &
3475 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
3476 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
3477 }
3478
f0df3503
MM		 3479 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
3480 dev->hw_features |= NETIF_F_RXFCS;
3481
78500b8c
MM		 3482 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
3483 dev->hw_features |= NETIF_F_RXALL;
3484
1eb8c695 3485 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 3486 MLX4_STEERING_MODE_DEVICE_MANAGED &&
3487 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 3488 dev->hw_features |= NETIF_F_NTUPLE;
3489
cc5387f7
YB		 3490 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
3491 dev->priv_flags |= IFF_UNICAST_FLT;
3492
947cbb0a
EP		 3493 /* Setting a default hash function value */
3494 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
3495 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3496 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
3497 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
3498 } else {
3499 en_warn(priv,
3500 "No RSS hash capabilities exposed, using Toeplitz\n");
3501 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
3502 }
3503
925ab1aa 3504 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
3c9346b2
AD		 3505 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
3506 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3507 NETIF_F_GSO_PARTIAL;
3508 dev->features |= NETIF_F_GSO_UDP_TUNNEL |
3509 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3510 NETIF_F_GSO_PARTIAL;
3511 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
925ab1aa
EE		 3512 }
3513
b80f71f5
JW		 3514 /* MTU range: 46 - hw-specific max */
3515 dev->min_mtu = MLX4_EN_MIN_MTU;
3516 dev->max_mtu = priv->max_mtu;
3517
c27a02cd 3518 mdev->pndev[port] = dev;
5da03547 3519 mdev->upper[port] = NULL;
c27a02cd
YP		 3520
3521 netif_carrier_off(dev);
4801ae70
EE		 3522 mlx4_en_set_default_moderation(priv);
3523
67f8b1dc 3524 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num[TX]);
453a6082
YP		 3525 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
3526
79aeaccd
YB		 3527 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
3528
90822265 3529 /* Configure port */
5c8e9046 3530 mlx4_en_calc_rx_buf(dev);
90822265 3531 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 3532 priv->rx_skb_size + ETH_FCS_LEN,
3533 prof->tx_pause, prof->tx_ppp,
3534 prof->rx_pause, prof->rx_ppp);
90822265 3535 if (err) {
1a91de28
JP		 3536 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3537 priv->port, err);
90822265
YP		 3538 goto out;
3539 }
3540
837052d0 3541 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 3542 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 3543 if (err) {
3544 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3545 err);
3546 goto out;
3547 }
3548 }
3549
90822265
YP		 3550 /* Init port */
3551 en_warn(priv, "Initializing port\n");
3552 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3553 if (err) {
3554 en_err(priv, "Failed Initializing port\n");
3555 goto out;
3556 }
c27a02cd 3557 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea 3558
90683061 3559 /* Initialize time stamp mechanism */
dc8142ea 3560 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
90683061
EE		 3561 mlx4_en_init_timestamp(mdev);
3562
fc9f5ea9
EE		 3563 queue_delayed_work(mdev->workqueue, &priv->service_task,
3564 SERVICE_TASK_DELAY);
dc8142ea 3565
0b131561
MB		 3566 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3567 mdev->profile.prof[priv->port].rx_ppp,
3568 mdev->profile.prof[priv->port].rx_pause,
3569 mdev->profile.prof[priv->port].tx_ppp,
3570 mdev->profile.prof[priv->port].tx_pause);
39de961a 3571
e5eda89d
IS		 3572 err = register_netdev(dev);
3573 if (err) {
3574 en_err(priv, "Netdev registration failed for port %d\n", port);
3575 goto out;
3576 }
3577
3578 priv->registered = 1;
09d4d087
JP		 3579 devlink_port_type_eth_set(mlx4_get_devlink_port(mdev->dev, priv->port),
3580 dev);
e5eda89d 3581
c27a02cd
YP		 3582 return 0;
3583
3584out:
3585 mlx4_en_destroy_netdev(dev);
3586 return err;
3587}
3588
537f6f95
SM		 3589int mlx4_en_reset_config(struct net_device *dev,
3590 struct hwtstamp_config ts_config,
3591 netdev_features_t features)
3592{
3593 struct mlx4_en_priv *priv = netdev_priv(dev);
3594 struct mlx4_en_dev *mdev = priv->mdev;
ec25bc04
EE		 3595 struct mlx4_en_port_profile new_prof;
3596 struct mlx4_en_priv *tmp;
537f6f95
SM		 3597 int port_up = 0;
3598 int err = 0;
3599
3600 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3601 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3602 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3603 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3604 return 0; /* Nothing to change */
3605
3606 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3607 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3608 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3609 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3610 return -EINVAL;
3611 }
3612
ec25bc04
EE		 3613 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
3614 if (!tmp)
3615 return -ENOMEM;
3616
537f6f95 3617 mutex_lock(&mdev->state_lock);
ec25bc04
EE		 3618
3619 memcpy(&new_prof, priv->prof, sizeof(struct mlx4_en_port_profile));
3620 memcpy(&new_prof.hwtstamp_config, &ts_config, sizeof(ts_config));
3621
770f8225 3622 err = mlx4_en_try_alloc_resources(priv, tmp, &new_prof, true);
ec25bc04
EE		 3623 if (err)
3624 goto out;
3625
537f6f95
SM		 3626 if (priv->port_up) {
3627 port_up = 1;
3628 mlx4_en_stop_port(dev, 1);
3629 }
3630
ec25bc04 3631 mlx4_en_safe_replace_resources(priv, tmp);
537f6f95
SM		 3632
3633 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3634 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3635 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3636 else
3637 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3638 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3639 /* RX time-stamping is OFF, update the RX vlan offload
3640 * to the latest wanted state
3641 */
3642 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3643 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3644 else
3645 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3646 }
3647
f0df3503
MM		 3648 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3649 if (features & NETIF_F_RXFCS)
3650 dev->features |= NETIF_F_RXFCS;
3651 else
3652 dev->features &= ~NETIF_F_RXFCS;
3653 }
3654
537f6f95
SM		 3655 /* RX vlan offload and RX time-stamping can't co-exist !
3656 * Regardless of the caller's choice,
3657 * Turn Off RX vlan offload in case of time-stamping is ON
3658 */
3659 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3660 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3661 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3662 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3663 }
3664
537f6f95
SM		 3665 if (port_up) {
3666 err = mlx4_en_start_port(dev);
3667 if (err)
3668 en_err(priv, "Failed starting port\n");
3669 }
3670
3671out:
3672 mutex_unlock(&mdev->state_lock);
ec25bc04
EE		 3673 kfree(tmp);
3674 if (!err)
3675 netdev_features_change(dev);
537f6f95
SM		 3676 return err;
3677}
Linux 6.x block layer and io_uring tree(s)