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net/mlx4_core: Fix wrong dump of the vxlan offloads device capability
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
c27a02cd
YP		 42
43#include <linux/mlx4/driver.h>
44#include <linux/mlx4/device.h>
45#include <linux/mlx4/cmd.h>
46#include <linux/mlx4/cq.h>
47
48#include "mlx4_en.h"
49#include "en_port.h"
50
d317966b 51int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 52{
bc6a4744
AV		 53 struct mlx4_en_priv *priv = netdev_priv(dev);
54 int i;
d317966b 55 unsigned int offset = 0;
bc6a4744
AV		 56
57 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 58 return -EINVAL;
59
bc6a4744
AV		 60 netdev_set_num_tc(dev, up);
61
62 /* Partition Tx queues evenly amongst UP's */
bc6a4744 63 for (i = 0; i < up; i++) {
d317966b
AV		 64 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
65 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 66 }
67
897d7846
AV		 68 return 0;
69}
70
e0d1095a 71#ifdef CONFIG_NET_RX_BUSY_POLL
9e77a2b8
AV		 72/* must be called with local_bh_disable()d */
73static int mlx4_en_low_latency_recv(struct napi_struct *napi)
74{
75 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
76 struct net_device *dev = cq->dev;
77 struct mlx4_en_priv *priv = netdev_priv(dev);
41d942d5 78 struct mlx4_en_rx_ring *rx_ring = priv->rx_ring[cq->ring];
9e77a2b8
AV		 79 int done;
80
81 if (!priv->port_up)
82 return LL_FLUSH_FAILED;
83
84 if (!mlx4_en_cq_lock_poll(cq))
85 return LL_FLUSH_BUSY;
86
87 done = mlx4_en_process_rx_cq(dev, cq, 4);
8501841a
AV		 88 if (likely(done))
89 rx_ring->cleaned += done;
90 else
91 rx_ring->misses++;
9e77a2b8
AV		 92
93 mlx4_en_cq_unlock_poll(cq);
94
95 return done;
96}
e0d1095a 97#endif /* CONFIG_NET_RX_BUSY_POLL */
9e77a2b8 98
1eb8c695
AV		 99#ifdef CONFIG_RFS_ACCEL
100
101struct mlx4_en_filter {
102 struct list_head next;
103 struct work_struct work;
104
75a353d4 105 u8 ip_proto;
1eb8c695
AV		 106 __be32 src_ip;
107 __be32 dst_ip;
108 __be16 src_port;
109 __be16 dst_port;
110
111 int rxq_index;
112 struct mlx4_en_priv *priv;
113 u32 flow_id; /* RFS infrastructure id */
114 int id; /* mlx4_en driver id */
115 u64 reg_id; /* Flow steering API id */
116 u8 activated; /* Used to prevent expiry before filter
117 * is attached
118 */
119 struct hlist_node filter_chain;
120};
121
122static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
123
75a353d4
EP		 124static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
125{
126 switch (ip_proto) {
127 case IPPROTO_UDP:
128 return MLX4_NET_TRANS_RULE_ID_UDP;
129 case IPPROTO_TCP:
130 return MLX4_NET_TRANS_RULE_ID_TCP;
131 default:
132 return -EPROTONOSUPPORT;
133 }
134};
135
1eb8c695
AV		 136static void mlx4_en_filter_work(struct work_struct *work)
137{
138 struct mlx4_en_filter *filter = container_of(work,
139 struct mlx4_en_filter,
140 work);
141 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 142 struct mlx4_spec_list spec_tcp_udp = {
143 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 144 {
145 .tcp_udp = {
146 .dst_port = filter->dst_port,
147 .dst_port_msk = (__force __be16)-1,
148 .src_port = filter->src_port,
149 .src_port_msk = (__force __be16)-1,
150 },
151 },
152 };
153 struct mlx4_spec_list spec_ip = {
154 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
155 {
156 .ipv4 = {
157 .dst_ip = filter->dst_ip,
158 .dst_ip_msk = (__force __be32)-1,
159 .src_ip = filter->src_ip,
160 .src_ip_msk = (__force __be32)-1,
161 },
162 },
163 };
164 struct mlx4_spec_list spec_eth = {
165 .id = MLX4_NET_TRANS_RULE_ID_ETH,
166 };
167 struct mlx4_net_trans_rule rule = {
168 .list = LIST_HEAD_INIT(rule.list),
169 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
170 .exclusive = 1,
171 .allow_loopback = 1,
f9162539 172 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 173 .port = priv->port,
174 .priority = MLX4_DOMAIN_RFS,
175 };
176 int rc;
1eb8c695
AV		 177 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
178
75a353d4
EP		 179 if (spec_tcp_udp.id < 0) {
180 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
181 filter->ip_proto);
182 goto ignore;
183 }
1eb8c695
AV		 184 list_add_tail(&spec_eth.list, &rule.list);
185 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 186 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 187
1eb8c695 188 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 189 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 190 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
191
192 filter->activated = 0;
193
194 if (filter->reg_id) {
195 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
196 if (rc && rc != -ENOENT)
197 en_err(priv, "Error detaching flow. rc = %d\n", rc);
198 }
199
200 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
201 if (rc)
202 en_err(priv, "Error attaching flow. err = %d\n", rc);
203
75a353d4 204ignore:
1eb8c695
AV		 205 mlx4_en_filter_rfs_expire(priv);
206
207 filter->activated = 1;
208}
209
210static inline struct hlist_head *
211filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
212 __be16 src_port, __be16 dst_port)
213{
214 unsigned long l;
215 int bucket_idx;
216
217 l = (__force unsigned long)src_port |
218 ((__force unsigned long)dst_port << 2);
219 l ^= (__force unsigned long)(src_ip ^ dst_ip);
220
221 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
222
223 return &priv->filter_hash[bucket_idx];
224}
225
226static struct mlx4_en_filter *
227mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 228 __be32 dst_ip, u8 ip_proto, __be16 src_port,
229 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 230{
231 struct mlx4_en_filter *filter = NULL;
232
233 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
234 if (!filter)
235 return NULL;
236
237 filter->priv = priv;
238 filter->rxq_index = rxq_index;
239 INIT_WORK(&filter->work, mlx4_en_filter_work);
240
241 filter->src_ip = src_ip;
242 filter->dst_ip = dst_ip;
75a353d4 243 filter->ip_proto = ip_proto;
1eb8c695
AV		 244 filter->src_port = src_port;
245 filter->dst_port = dst_port;
246
247 filter->flow_id = flow_id;
248
ee64c0ee 249 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 250
251 list_add_tail(&filter->next, &priv->filters);
252 hlist_add_head(&filter->filter_chain,
253 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
254 dst_port));
255
256 return filter;
257}
258
259static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
260{
261 struct mlx4_en_priv *priv = filter->priv;
262 int rc;
263
264 list_del(&filter->next);
265
266 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
267 if (rc && rc != -ENOENT)
268 en_err(priv, "Error detaching flow. rc = %d\n", rc);
269
270 kfree(filter);
271}
272
273static inline struct mlx4_en_filter *
274mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 275 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 276{
1eb8c695
AV		 277 struct mlx4_en_filter *filter;
278 struct mlx4_en_filter *ret = NULL;
279
b67bfe0d 280 hlist_for_each_entry(filter,
1eb8c695
AV		 281 filter_hash_bucket(priv, src_ip, dst_ip,
282 src_port, dst_port),
283 filter_chain) {
284 if (filter->src_ip == src_ip &&
285 filter->dst_ip == dst_ip &&
75a353d4 286 filter->ip_proto == ip_proto &&
1eb8c695
AV		 287 filter->src_port == src_port &&
288 filter->dst_port == dst_port) {
289 ret = filter;
290 break;
291 }
292 }
293
294 return ret;
295}
296
297static int
298mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
299 u16 rxq_index, u32 flow_id)
300{
301 struct mlx4_en_priv *priv = netdev_priv(net_dev);
302 struct mlx4_en_filter *filter;
303 const struct iphdr *ip;
304 const __be16 *ports;
75a353d4 305 u8 ip_proto;
1eb8c695
AV		 306 __be32 src_ip;
307 __be32 dst_ip;
308 __be16 src_port;
309 __be16 dst_port;
310 int nhoff = skb_network_offset(skb);
311 int ret = 0;
312
313 if (skb->protocol != htons(ETH_P_IP))
314 return -EPROTONOSUPPORT;
315
316 ip = (const struct iphdr *)(skb->data + nhoff);
317 if (ip_is_fragment(ip))
318 return -EPROTONOSUPPORT;
319
75a353d4
EP		 320 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
321 return -EPROTONOSUPPORT;
1eb8c695
AV		 322 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
323
75a353d4 324 ip_proto = ip->protocol;
1eb8c695
AV		 325 src_ip = ip->saddr;
326 dst_ip = ip->daddr;
327 src_port = ports[0];
328 dst_port = ports[1];
329
1eb8c695 330 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 331 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
332 src_port, dst_port);
1eb8c695
AV		 333 if (filter) {
334 if (filter->rxq_index == rxq_index)
335 goto out;
336
337 filter->rxq_index = rxq_index;
338 } else {
339 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 340 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 341 src_port, dst_port, flow_id);
342 if (!filter) {
343 ret = -ENOMEM;
344 goto err;
345 }
346 }
347
348 queue_work(priv->mdev->workqueue, &filter->work);
349
350out:
351 ret = filter->id;
352err:
353 spin_unlock_bh(&priv->filters_lock);
354
355 return ret;
356}
357
41d942d5 358void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 359{
360 struct mlx4_en_filter *filter, *tmp;
361 LIST_HEAD(del_list);
362
363 spin_lock_bh(&priv->filters_lock);
364 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
365 list_move(&filter->next, &del_list);
366 hlist_del(&filter->filter_chain);
367 }
368 spin_unlock_bh(&priv->filters_lock);
369
370 list_for_each_entry_safe(filter, tmp, &del_list, next) {
371 cancel_work_sync(&filter->work);
372 mlx4_en_filter_free(filter);
373 }
374}
375
376static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
377{
378 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
379 LIST_HEAD(del_list);
380 int i = 0;
381
382 spin_lock_bh(&priv->filters_lock);
383 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
384 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
385 break;
386
387 if (filter->activated &&
388 !work_pending(&filter->work) &&
389 rps_may_expire_flow(priv->dev,
390 filter->rxq_index, filter->flow_id,
391 filter->id)) {
392 list_move(&filter->next, &del_list);
393 hlist_del(&filter->filter_chain);
394 } else
395 last_filter = filter;
396
397 i++;
398 }
399
400 if (last_filter && (&last_filter->next != priv->filters.next))
401 list_move(&priv->filters, &last_filter->next);
402
403 spin_unlock_bh(&priv->filters_lock);
404
405 list_for_each_entry_safe(filter, tmp, &del_list, next)
406 mlx4_en_filter_free(filter);
407}
408#endif
409
80d5c368
PM		 410static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
411 __be16 proto, u16 vid)
c27a02cd
YP		 412{
413 struct mlx4_en_priv *priv = netdev_priv(dev);
414 struct mlx4_en_dev *mdev = priv->mdev;
415 int err;
4c3eb3ca 416 int idx;
c27a02cd 417
f1b553fb 418 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 419
f1b553fb 420 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 421
422 /* Add VID to port VLAN filter */
423 mutex_lock(&mdev->state_lock);
424 if (mdev->device_up && priv->port_up) {
f1b553fb 425 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 426 if (err)
453a6082 427 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 428 }
4c3eb3ca 429 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 430 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 431 mutex_unlock(&mdev->state_lock);
4c3eb3ca 432
8e586137 433 return 0;
c27a02cd
YP		 434}
435
80d5c368
PM		 436static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
437 __be16 proto, u16 vid)
c27a02cd
YP		 438{
439 struct mlx4_en_priv *priv = netdev_priv(dev);
440 struct mlx4_en_dev *mdev = priv->mdev;
441 int err;
442
f1b553fb 443 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 444
f1b553fb 445 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 446
447 /* Remove VID from port VLAN filter */
448 mutex_lock(&mdev->state_lock);
2009d005 449 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 450
c27a02cd 451 if (mdev->device_up && priv->port_up) {
f1b553fb 452 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 453 if (err)
453a6082 454 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 455 }
456 mutex_unlock(&mdev->state_lock);
8e586137
JP		 457
458 return 0;
c27a02cd
YP		 459}
460
6bbb6d99
YB		 461static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
462{
bab6a9ea
YB		 463 int i;
464 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 465 dst_mac[i] = src_mac & 0xff;
466 src_mac >>= 8;
467 }
468 memset(&dst_mac[ETH_ALEN], 0, 2);
469}
470
837052d0
OG		 471
472static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
473 int qpn, u64 *reg_id)
474{
475 int err;
476 struct mlx4_spec_list spec_eth_outer = { {NULL} };
477 struct mlx4_spec_list spec_vxlan = { {NULL} };
478 struct mlx4_spec_list spec_eth_inner = { {NULL} };
479
480 struct mlx4_net_trans_rule rule = {
481 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
482 .exclusive = 0,
483 .allow_loopback = 1,
484 .promisc_mode = MLX4_FS_REGULAR,
485 .priority = MLX4_DOMAIN_NIC,
486 };
487
488 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
489
490 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
491 return 0; /* do nothing */
492
493 rule.port = priv->port;
494 rule.qpn = qpn;
495 INIT_LIST_HEAD(&rule.list);
496
497 spec_eth_outer.id = MLX4_NET_TRANS_RULE_ID_ETH;
498 memcpy(spec_eth_outer.eth.dst_mac, addr, ETH_ALEN);
499 memcpy(spec_eth_outer.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
500
501 spec_vxlan.id = MLX4_NET_TRANS_RULE_ID_VXLAN; /* any vxlan header */
502 spec_eth_inner.id = MLX4_NET_TRANS_RULE_ID_ETH; /* any inner eth header */
503
504 list_add_tail(&spec_eth_outer.list, &rule.list);
505 list_add_tail(&spec_vxlan.list, &rule.list);
506 list_add_tail(&spec_eth_inner.list, &rule.list);
507
508 err = mlx4_flow_attach(priv->mdev->dev, &rule, reg_id);
509 if (err) {
510 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
511 return err;
512 }
513 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
514 return 0;
515}
516
517
16a10ffd
YB		 518static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
519 unsigned char *mac, int *qpn, u64 *reg_id)
520{
521 struct mlx4_en_dev *mdev = priv->mdev;
522 struct mlx4_dev *dev = mdev->dev;
523 int err;
524
525 switch (dev->caps.steering_mode) {
526 case MLX4_STEERING_MODE_B0: {
527 struct mlx4_qp qp;
528 u8 gid[16] = {0};
529
530 qp.qpn = *qpn;
531 memcpy(&gid[10], mac, ETH_ALEN);
532 gid[5] = priv->port;
533
534 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
535 break;
536 }
537 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
538 struct mlx4_spec_list spec_eth = { {NULL} };
539 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
540
541 struct mlx4_net_trans_rule rule = {
542 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
543 .exclusive = 0,
544 .allow_loopback = 1,
f9162539 545 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 546 .priority = MLX4_DOMAIN_NIC,
547 };
548
549 rule.port = priv->port;
550 rule.qpn = *qpn;
551 INIT_LIST_HEAD(&rule.list);
552
553 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
554 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
555 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
556 list_add_tail(&spec_eth.list, &rule.list);
557
558 err = mlx4_flow_attach(dev, &rule, reg_id);
559 break;
560 }
561 default:
562 return -EINVAL;
563 }
564 if (err)
565 en_warn(priv, "Failed Attaching Unicast\n");
566
567 return err;
568}
569
570static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
571 unsigned char *mac, int qpn, u64 reg_id)
572{
573 struct mlx4_en_dev *mdev = priv->mdev;
574 struct mlx4_dev *dev = mdev->dev;
575
576 switch (dev->caps.steering_mode) {
577 case MLX4_STEERING_MODE_B0: {
578 struct mlx4_qp qp;
579 u8 gid[16] = {0};
580
581 qp.qpn = qpn;
582 memcpy(&gid[10], mac, ETH_ALEN);
583 gid[5] = priv->port;
584
585 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
586 break;
587 }
588 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
589 mlx4_flow_detach(dev, reg_id);
590 break;
591 }
592 default:
593 en_err(priv, "Invalid steering mode.\n");
594 }
595}
596
597static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
598{
599 struct mlx4_en_dev *mdev = priv->mdev;
600 struct mlx4_dev *dev = mdev->dev;
601 struct mlx4_mac_entry *entry;
602 int index = 0;
603 int err = 0;
604 u64 reg_id;
605 int *qpn = &priv->base_qpn;
606 u64 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
607
608 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
609 priv->dev->dev_addr);
610 index = mlx4_register_mac(dev, priv->port, mac);
611 if (index < 0) {
612 err = index;
613 en_err(priv, "Failed adding MAC: %pM\n",
614 priv->dev->dev_addr);
615 return err;
616 }
617
618 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
619 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
620 *qpn = base_qpn + index;
621 return 0;
622 }
623
624 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
625 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
626 if (err) {
627 en_err(priv, "Failed to reserve qp for mac registration\n");
628 goto qp_err;
629 }
630
631 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
632 if (err)
633 goto steer_err;
634
9ba75fb0
WY		 635 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
636 &priv->tunnel_reg_id);
637 if (err)
837052d0
OG		 638 goto tunnel_err;
639
16a10ffd
YB		 640 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
641 if (!entry) {
642 err = -ENOMEM;
643 goto alloc_err;
644 }
645 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
646 entry->reg_id = reg_id;
647
c07cb4b0
YB		 648 hlist_add_head_rcu(&entry->hlist,
649 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
16a10ffd 650
c07cb4b0 651 return 0;
16a10ffd
YB		 652
653alloc_err:
837052d0
OG		 654 if (priv->tunnel_reg_id)
655 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
656tunnel_err:
16a10ffd
YB		 657 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
658
659steer_err:
660 mlx4_qp_release_range(dev, *qpn, 1);
661
662qp_err:
663 mlx4_unregister_mac(dev, priv->port, mac);
664 return err;
665}
666
667static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
668{
669 struct mlx4_en_dev *mdev = priv->mdev;
670 struct mlx4_dev *dev = mdev->dev;
16a10ffd 671 int qpn = priv->base_qpn;
83a5a6ce 672 u64 mac;
16a10ffd 673
83a5a6ce
YB		 674 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
675 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr);
676 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
677 priv->dev->dev_addr);
678 mlx4_unregister_mac(dev, priv->port, mac);
679 } else {
c07cb4b0 680 struct mlx4_mac_entry *entry;
b67bfe0d 681 struct hlist_node *tmp;
c07cb4b0 682 struct hlist_head *bucket;
83a5a6ce 683 unsigned int i;
c07cb4b0 684
83a5a6ce
YB		 685 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
686 bucket = &priv->mac_hash[i];
687 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
688 mac = mlx4_en_mac_to_u64(entry->mac);
689 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
690 entry->mac);
c07cb4b0
YB		 691 mlx4_en_uc_steer_release(priv, entry->mac,
692 qpn, entry->reg_id);
c07cb4b0 693
83a5a6ce 694 mlx4_unregister_mac(dev, priv->port, mac);
c07cb4b0
YB		 695 hlist_del_rcu(&entry->hlist);
696 kfree_rcu(entry, rcu);
c07cb4b0 697 }
16a10ffd 698 }
83a5a6ce 699
837052d0
OG		 700 if (priv->tunnel_reg_id) {
701 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
702 priv->tunnel_reg_id = 0;
703 }
704
83a5a6ce
YB		 705 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
706 priv->port, qpn);
707 mlx4_qp_release_range(dev, qpn, 1);
708 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 709 }
710}
711
712static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 713 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 714{
715 struct mlx4_en_dev *mdev = priv->mdev;
716 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 717 int err = 0;
718 u64 new_mac_u64 = mlx4_en_mac_to_u64(new_mac);
719
720 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 721 struct hlist_head *bucket;
722 unsigned int mac_hash;
723 struct mlx4_mac_entry *entry;
b67bfe0d 724 struct hlist_node *tmp;
c07cb4b0
YB		 725 u64 prev_mac_u64 = mlx4_en_mac_to_u64(prev_mac);
726
727 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 728 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 729 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
730 mlx4_en_uc_steer_release(priv, entry->mac,
731 qpn, entry->reg_id);
732 mlx4_unregister_mac(dev, priv->port,
733 prev_mac_u64);
734 hlist_del_rcu(&entry->hlist);
735 synchronize_rcu();
736 memcpy(entry->mac, new_mac, ETH_ALEN);
737 entry->reg_id = 0;
738 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
739 hlist_add_head_rcu(&entry->hlist,
740 &priv->mac_hash[mac_hash]);
741 mlx4_register_mac(dev, priv->port, new_mac_u64);
742 err = mlx4_en_uc_steer_add(priv, new_mac,
743 &qpn,
744 &entry->reg_id);
745 return err;
746 }
747 }
748 return -EINVAL;
16a10ffd
YB		 749 }
750
751 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
752}
753
e7c1c2c4 754u64 mlx4_en_mac_to_u64(u8 *addr)
c27a02cd
YP		 755{
756 u64 mac = 0;
757 int i;
758
759 for (i = 0; i < ETH_ALEN; i++) {
760 mac <<= 8;
761 mac |= addr[i];
762 }
763 return mac;
764}
765
bfa8ab47 766static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv)
c27a02cd 767{
c27a02cd
YP		 768 int err = 0;
769
c27a02cd
YP		 770 if (priv->port_up) {
771 /* Remove old MAC and insert the new one */
16a10ffd 772 err = mlx4_en_replace_mac(priv, priv->base_qpn,
90bbb74a 773 priv->dev->dev_addr, priv->prev_mac);
c27a02cd 774 if (err)
453a6082 775 en_err(priv, "Failed changing HW MAC address\n");
6bbb6d99
YB		 776 memcpy(priv->prev_mac, priv->dev->dev_addr,
777 sizeof(priv->prev_mac));
c27a02cd 778 } else
48e551ff 779 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 780
bfa8ab47
YB		 781 return err;
782}
783
784static int mlx4_en_set_mac(struct net_device *dev, void *addr)
785{
786 struct mlx4_en_priv *priv = netdev_priv(dev);
787 struct mlx4_en_dev *mdev = priv->mdev;
788 struct sockaddr *saddr = addr;
789 int err;
790
791 if (!is_valid_ether_addr(saddr->sa_data))
792 return -EADDRNOTAVAIL;
793
794 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
795
796 mutex_lock(&mdev->state_lock);
797 err = mlx4_en_do_set_mac(priv);
c27a02cd 798 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 799
800 return err;
c27a02cd
YP		 801}
802
803static void mlx4_en_clear_list(struct net_device *dev)
804{
805 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 806 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 807
6d199937
YP		 808 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
809 list_del(&mc_to_del->list);
810 kfree(mc_to_del);
811 }
c27a02cd
YP		 812}
813
814static void mlx4_en_cache_mclist(struct net_device *dev)
815{
816 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 817 struct netdev_hw_addr *ha;
6d199937 818 struct mlx4_en_mc_list *tmp;
ff6e2163 819
0e03567a 820 mlx4_en_clear_list(dev);
6d199937
YP		 821 netdev_for_each_mc_addr(ha, dev) {
822 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
823 if (!tmp) {
6d199937
YP		 824 mlx4_en_clear_list(dev);
825 return;
826 }
827 memcpy(tmp->addr, ha->addr, ETH_ALEN);
828 list_add_tail(&tmp->list, &priv->mc_list);
829 }
c27a02cd
YP		 830}
831
6d199937
YP		 832static void update_mclist_flags(struct mlx4_en_priv *priv,
833 struct list_head *dst,
834 struct list_head *src)
835{
836 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
837 bool found;
838
839 /* Find all the entries that should be removed from dst,
840 * These are the entries that are not found in src
841 */
842 list_for_each_entry(dst_tmp, dst, list) {
843 found = false;
844 list_for_each_entry(src_tmp, src, list) {
c0623e58 845 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 846 found = true;
847 break;
848 }
849 }
850 if (!found)
851 dst_tmp->action = MCLIST_REM;
852 }
853
854 /* Add entries that exist in src but not in dst
855 * mark them as need to add
856 */
857 list_for_each_entry(src_tmp, src, list) {
858 found = false;
859 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 860 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 861 dst_tmp->action = MCLIST_NONE;
862 found = true;
863 break;
864 }
865 }
866 if (!found) {
14f8dc49
JP		 867 new_mc = kmemdup(src_tmp,
868 sizeof(struct mlx4_en_mc_list),
6d199937 869 GFP_KERNEL);
14f8dc49 870 if (!new_mc)
6d199937 871 return;
14f8dc49 872
6d199937
YP		 873 new_mc->action = MCLIST_ADD;
874 list_add_tail(&new_mc->list, dst);
875 }
876 }
877}
c27a02cd 878
0eb74fdd 879static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 880{
881 struct mlx4_en_priv *priv = netdev_priv(dev);
882
883 if (!priv->port_up)
884 return;
885
0eb74fdd 886 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 887}
888
0eb74fdd
YB		 889static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
890 struct mlx4_en_dev *mdev)
c27a02cd 891{
c96d97f4 892 int err = 0;
c27a02cd 893
0eb74fdd 894 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 895 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 896 en_warn(priv, "Entering promiscuous mode\n");
897 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 898
0eb74fdd 899 /* Enable promiscouos mode */
c96d97f4 900 switch (mdev->dev->caps.steering_mode) {
592e49dd 901 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 902 err = mlx4_flow_steer_promisc_add(mdev->dev,
903 priv->port,
904 priv->base_qpn,
f9162539 905 MLX4_FS_ALL_DEFAULT);
592e49dd 906 if (err)
0eb74fdd
YB		 907 en_err(priv, "Failed enabling promiscuous mode\n");
908 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 909 break;
910
c96d97f4 911 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 912 err = mlx4_unicast_promisc_add(mdev->dev,
913 priv->base_qpn,
914 priv->port);
c96d97f4 915 if (err)
0eb74fdd
YB		 916 en_err(priv, "Failed enabling unicast promiscuous mode\n");
917
918 /* Add the default qp number as multicast
919 * promisc
920 */
921 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
922 err = mlx4_multicast_promisc_add(mdev->dev,
923 priv->base_qpn,
924 priv->port);
c96d97f4 925 if (err)
0eb74fdd
YB		 926 en_err(priv, "Failed enabling multicast promiscuous mode\n");
927 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 928 }
929 break;
c27a02cd 930
c96d97f4
HHZ		 931 case MLX4_STEERING_MODE_A0:
932 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
933 priv->port,
0eb74fdd
YB		 934 priv->base_qpn,
935 1);
1679200f 936 if (err)
0eb74fdd 937 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 938 break;
1679200f
YP		 939 }
940
0eb74fdd
YB		 941 /* Disable port multicast filter (unconditionally) */
942 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
943 0, MLX4_MCAST_DISABLE);
944 if (err)
945 en_err(priv, "Failed disabling multicast filter\n");
946
947 /* Disable port VLAN filter */
f1b553fb 948 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 949 if (err)
0eb74fdd
YB		 950 en_err(priv, "Failed disabling VLAN filter\n");
951 }
952}
953
954static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
955 struct mlx4_en_dev *mdev)
956{
957 int err = 0;
958
959 if (netif_msg_rx_status(priv))
960 en_warn(priv, "Leaving promiscuous mode\n");
961 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
962
963 /* Disable promiscouos mode */
964 switch (mdev->dev->caps.steering_mode) {
965 case MLX4_STEERING_MODE_DEVICE_MANAGED:
966 err = mlx4_flow_steer_promisc_remove(mdev->dev,
967 priv->port,
f9162539 968 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 969 if (err)
970 en_err(priv, "Failed disabling promiscuous mode\n");
971 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
972 break;
973
974 case MLX4_STEERING_MODE_B0:
975 err = mlx4_unicast_promisc_remove(mdev->dev,
976 priv->base_qpn,
977 priv->port);
978 if (err)
979 en_err(priv, "Failed disabling unicast promiscuous mode\n");
980 /* Disable Multicast promisc */
981 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
982 err = mlx4_multicast_promisc_remove(mdev->dev,
983 priv->base_qpn,
984 priv->port);
985 if (err)
986 en_err(priv, "Failed disabling multicast promiscuous mode\n");
987 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
988 }
989 break;
990
991 case MLX4_STEERING_MODE_A0:
992 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
993 priv->port,
994 priv->base_qpn, 0);
995 if (err)
996 en_err(priv, "Failed disabling promiscuous mode\n");
997 break;
c27a02cd
YP		 998 }
999
0eb74fdd
YB		 1000 /* Enable port VLAN filter */
1001 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
1002 if (err)
1003 en_err(priv, "Failed enabling VLAN filter\n");
1004}
1005
1006static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
1007 struct net_device *dev,
1008 struct mlx4_en_dev *mdev)
1009{
1010 struct mlx4_en_mc_list *mclist, *tmp;
1011 u64 mcast_addr = 0;
1012 u8 mc_list[16] = {0};
1013 int err = 0;
1014
c27a02cd
YP		 1015 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
1016 if (dev->flags & IFF_ALLMULTI) {
1017 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1018 0, MLX4_MCAST_DISABLE);
1019 if (err)
453a6082 1020 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 1021
1022 /* Add the default qp number as multicast promisc */
1023 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 1024 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1025 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1026 err = mlx4_flow_steer_promisc_add(mdev->dev,
1027 priv->port,
1028 priv->base_qpn,
f9162539 1029 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1030 break;
1031
c96d97f4
HHZ		 1032 case MLX4_STEERING_MODE_B0:
1033 err = mlx4_multicast_promisc_add(mdev->dev,
1034 priv->base_qpn,
1035 priv->port);
1036 break;
1037
1038 case MLX4_STEERING_MODE_A0:
1039 break;
1040 }
1679200f
YP		 1041 if (err)
1042 en_err(priv, "Failed entering multicast promisc mode\n");
1043 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
1044 }
c27a02cd 1045 } else {
1679200f
YP		 1046 /* Disable Multicast promisc */
1047 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 1048 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 1049 case MLX4_STEERING_MODE_DEVICE_MANAGED:
1050 err = mlx4_flow_steer_promisc_remove(mdev->dev,
1051 priv->port,
f9162539 1052 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 1053 break;
1054
c96d97f4
HHZ		 1055 case MLX4_STEERING_MODE_B0:
1056 err = mlx4_multicast_promisc_remove(mdev->dev,
1057 priv->base_qpn,
1058 priv->port);
1059 break;
1060
1061 case MLX4_STEERING_MODE_A0:
1062 break;
1063 }
1679200f 1064 if (err)
25985edc 1065 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 1066 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1067 }
ff6e2163 1068
c27a02cd
YP		 1069 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1070 0, MLX4_MCAST_DISABLE);
1071 if (err)
453a6082 1072 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 1073
1074 /* Flush mcast filter and init it with broadcast address */
1075 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
1076 1, MLX4_MCAST_CONFIG);
1077
1078 /* Update multicast list - we cache all addresses so they won't
1079 * change while HW is updated holding the command semaphor */
dbd501a8 1080 netif_addr_lock_bh(dev);
c27a02cd 1081 mlx4_en_cache_mclist(dev);
dbd501a8 1082 netif_addr_unlock_bh(dev);
6d199937
YP		 1083 list_for_each_entry(mclist, &priv->mc_list, list) {
1084 mcast_addr = mlx4_en_mac_to_u64(mclist->addr);
c27a02cd
YP		 1085 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
1086 mcast_addr, 0, MLX4_MCAST_CONFIG);
1087 }
1088 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
1089 0, MLX4_MCAST_ENABLE);
1090 if (err)
453a6082 1091 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 1092
1093 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
1094 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1095 if (mclist->action == MCLIST_REM) {
1096 /* detach this address and delete from list */
1097 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1098 mc_list[5] = priv->port;
1099 err = mlx4_multicast_detach(mdev->dev,
1100 &priv->rss_map.indir_qp,
1101 mc_list,
0ff1fb65
HHZ		 1102 MLX4_PROT_ETH,
1103 mclist->reg_id);
6d199937
YP		 1104 if (err)
1105 en_err(priv, "Fail to detach multicast address\n");
1106
837052d0
OG		 1107 if (mclist->tunnel_reg_id) {
1108 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
1109 if (err)
1110 en_err(priv, "Failed to detach multicast address\n");
1111 }
1112
6d199937
YP		 1113 /* remove from list */
1114 list_del(&mclist->list);
1115 kfree(mclist);
9c64508a 1116 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 1117 /* attach the address */
1118 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 1119 /* needed for B0 steering support */
6d199937
YP		 1120 mc_list[5] = priv->port;
1121 err = mlx4_multicast_attach(mdev->dev,
1122 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1123 mc_list,
1124 priv->port, 0,
1125 MLX4_PROT_ETH,
1126 &mclist->reg_id);
6d199937
YP		 1127 if (err)
1128 en_err(priv, "Fail to attach multicast address\n");
1129
837052d0
OG		 1130 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1131 &mclist->tunnel_reg_id);
1132 if (err)
1133 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1134 }
1135 }
c27a02cd 1136 }
0eb74fdd
YB		 1137}
1138
cc5387f7
YB		 1139static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1140 struct net_device *dev,
1141 struct mlx4_en_dev *mdev)
1142{
1143 struct netdev_hw_addr *ha;
1144 struct mlx4_mac_entry *entry;
b67bfe0d 1145 struct hlist_node *tmp;
cc5387f7
YB		 1146 bool found;
1147 u64 mac;
1148 int err = 0;
1149 struct hlist_head *bucket;
1150 unsigned int i;
1151 int removed = 0;
1152 u32 prev_flags;
1153
1154 /* Note that we do not need to protect our mac_hash traversal with rcu,
1155 * since all modification code is protected by mdev->state_lock
1156 */
1157
1158 /* find what to remove */
1159 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1160 bucket = &priv->mac_hash[i];
b67bfe0d 1161 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1162 found = false;
1163 netdev_for_each_uc_addr(ha, dev) {
1164 if (ether_addr_equal_64bits(entry->mac,
1165 ha->addr)) {
1166 found = true;
1167 break;
1168 }
1169 }
1170
1171 /* MAC address of the port is not in uc list */
1172 if (ether_addr_equal_64bits(entry->mac, dev->dev_addr))
1173 found = true;
1174
1175 if (!found) {
1176 mac = mlx4_en_mac_to_u64(entry->mac);
1177 mlx4_en_uc_steer_release(priv, entry->mac,
1178 priv->base_qpn,
1179 entry->reg_id);
1180 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1181
1182 hlist_del_rcu(&entry->hlist);
1183 kfree_rcu(entry, rcu);
1184 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1185 entry->mac, priv->port);
1186 ++removed;
1187 }
1188 }
1189 }
1190
1191 /* if we didn't remove anything, there is no use in trying to add
1192 * again once we are in a forced promisc mode state
1193 */
1194 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1195 return;
1196
1197 prev_flags = priv->flags;
1198 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1199
1200 /* find what to add */
1201 netdev_for_each_uc_addr(ha, dev) {
1202 found = false;
1203 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1204 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1205 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1206 found = true;
1207 break;
1208 }
1209 }
1210
1211 if (!found) {
1212 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1213 if (!entry) {
1214 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1215 ha->addr, priv->port);
1216 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1217 break;
1218 }
1219 mac = mlx4_en_mac_to_u64(ha->addr);
1220 memcpy(entry->mac, ha->addr, ETH_ALEN);
1221 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1222 if (err < 0) {
1223 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1224 ha->addr, priv->port, err);
1225 kfree(entry);
1226 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1227 break;
1228 }
1229 err = mlx4_en_uc_steer_add(priv, ha->addr,
1230 &priv->base_qpn,
1231 &entry->reg_id);
1232 if (err) {
1233 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1234 ha->addr, priv->port, err);
1235 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1236 kfree(entry);
1237 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1238 break;
1239 } else {
1240 unsigned int mac_hash;
1241 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1242 ha->addr, priv->port);
1243 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1244 bucket = &priv->mac_hash[mac_hash];
1245 hlist_add_head_rcu(&entry->hlist, bucket);
1246 }
1247 }
1248 }
1249
1250 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1251 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1252 priv->port);
1253 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1254 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1255 priv->port);
1256 }
1257}
1258
0eb74fdd
YB		 1259static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1260{
1261 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1262 rx_mode_task);
1263 struct mlx4_en_dev *mdev = priv->mdev;
1264 struct net_device *dev = priv->dev;
1265
1266 mutex_lock(&mdev->state_lock);
1267 if (!mdev->device_up) {
1268 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1269 goto out;
1270 }
1271 if (!priv->port_up) {
1272 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1273 goto out;
1274 }
1275
1276 if (!netif_carrier_ok(dev)) {
1277 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1278 if (priv->port_state.link_state) {
1279 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1280 netif_carrier_on(dev);
1281 en_dbg(LINK, priv, "Link Up\n");
1282 }
1283 }
1284 }
1285
cc5387f7
YB		 1286 if (dev->priv_flags & IFF_UNICAST_FLT)
1287 mlx4_en_do_uc_filter(priv, dev, mdev);
1288
0eb74fdd 1289 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1290 if ((dev->flags & IFF_PROMISC) ||
1291 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1292 mlx4_en_set_promisc_mode(priv, mdev);
1293 goto out;
1294 }
1295
1296 /* Not in promiscuous mode */
1297 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1298 mlx4_en_clear_promisc_mode(priv, mdev);
1299
1300 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1301out:
1302 mutex_unlock(&mdev->state_lock);
1303}
1304
1305#ifdef CONFIG_NET_POLL_CONTROLLER
1306static void mlx4_en_netpoll(struct net_device *dev)
1307{
1308 struct mlx4_en_priv *priv = netdev_priv(dev);
1309 struct mlx4_en_cq *cq;
1310 unsigned long flags;
1311 int i;
1312
1313 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1314 cq = priv->rx_cq[i];
c27a02cd
YP		 1315 spin_lock_irqsave(&cq->lock, flags);
1316 napi_synchronize(&cq->napi);
1317 mlx4_en_process_rx_cq(dev, cq, 0);
1318 spin_unlock_irqrestore(&cq->lock, flags);
1319 }
1320}
1321#endif
1322
1323static void mlx4_en_tx_timeout(struct net_device *dev)
1324{
1325 struct mlx4_en_priv *priv = netdev_priv(dev);
1326 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1327 int i;
c27a02cd
YP		 1328
1329 if (netif_msg_timer(priv))
453a6082 1330 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1331
b944ebec
YP		 1332 for (i = 0; i < priv->tx_ring_num; i++) {
1333 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1334 continue;
1335 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1336 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1337 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1338 }
1339
1e338db5 1340 priv->port_stats.tx_timeout++;
453a6082 1341 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1342 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1343}
1344
1345
1346static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1347{
1348 struct mlx4_en_priv *priv = netdev_priv(dev);
1349
1350 spin_lock_bh(&priv->stats_lock);
1351 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1352 spin_unlock_bh(&priv->stats_lock);
1353
1354 return &priv->ret_stats;
1355}
1356
1357static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1358{
c27a02cd
YP		 1359 struct mlx4_en_cq *cq;
1360 int i;
1361
1362 /* If we haven't received a specific coalescing setting
98a1708d 1363 * (module param), we set the moderation parameters as follows:
c27a02cd 1364 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1365 * satisfy our coalescing target.
c27a02cd
YP		 1366 * - moder_time is set to a fixed value.
1367 */
3db36fb2 1368 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1369 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1370 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1371 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1372 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1373 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1374
1375 /* Setup cq moderation params */
1376 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1377 cq = priv->rx_cq[i];
c27a02cd
YP		 1378 cq->moder_cnt = priv->rx_frames;
1379 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1380 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1381 priv->last_moder_packets[i] = 0;
1382 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1383 }
1384
1385 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1386 cq = priv->tx_cq[i];
a19a848a
YP		 1387 cq->moder_cnt = priv->tx_frames;
1388 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1389 }
1390
1391 /* Reset auto-moderation params */
1392 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1393 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1394 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1395 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1396 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1397 priv->adaptive_rx_coal = 1;
c27a02cd 1398 priv->last_moder_jiffies = 0;
c27a02cd 1399 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1400}
1401
1402static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1403{
1404 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1405 struct mlx4_en_cq *cq;
1406 unsigned long packets;
1407 unsigned long rate;
1408 unsigned long avg_pkt_size;
1409 unsigned long rx_packets;
1410 unsigned long rx_bytes;
c27a02cd
YP		 1411 unsigned long rx_pkt_diff;
1412 int moder_time;
6b4d8d9f 1413 int ring, err;
c27a02cd
YP		 1414
1415 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1416 return;
1417
6b4d8d9f
AG		 1418 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1419 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1420 rx_packets = priv->rx_ring[ring]->packets;
1421 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1422 spin_unlock_bh(&priv->stats_lock);
1423
1424 rx_pkt_diff = ((unsigned long) (rx_packets -
1425 priv->last_moder_packets[ring]));
1426 packets = rx_pkt_diff;
1427 rate = packets * HZ / period;
1428 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1429 priv->last_moder_bytes[ring])) / packets : 0;
1430
1431 /* Apply auto-moderation only when packet rate
1432 * exceeds a rate that it matters */
1433 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1434 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1435 if (rate < priv->pkt_rate_low)
1436 moder_time = priv->rx_usecs_low;
1437 else if (rate > priv->pkt_rate_high)
1438 moder_time = priv->rx_usecs_high;
1439 else
1440 moder_time = (rate - priv->pkt_rate_low) *
1441 (priv->rx_usecs_high - priv->rx_usecs_low) /
1442 (priv->pkt_rate_high - priv->pkt_rate_low) +
1443 priv->rx_usecs_low;
6b4d8d9f
AG		 1444 } else {
1445 moder_time = priv->rx_usecs_low;
c27a02cd 1446 }
c27a02cd 1447
6b4d8d9f
AG		 1448 if (moder_time != priv->last_moder_time[ring]) {
1449 priv->last_moder_time[ring] = moder_time;
41d942d5 1450 cq = priv->rx_cq[ring];
c27a02cd 1451 cq->moder_time = moder_time;
a1c6693a 1452 cq->moder_cnt = priv->rx_frames;
c27a02cd 1453 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1454 if (err)
48e551ff
YB		 1455 en_err(priv, "Failed modifying moderation for cq:%d\n",
1456 ring);
c27a02cd 1457 }
6b4d8d9f
AG		 1458 priv->last_moder_packets[ring] = rx_packets;
1459 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1460 }
1461
c27a02cd
YP		 1462 priv->last_moder_jiffies = jiffies;
1463}
1464
1465static void mlx4_en_do_get_stats(struct work_struct *work)
1466{
bf6aede7 1467 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1468 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1469 stats_task);
1470 struct mlx4_en_dev *mdev = priv->mdev;
1471 int err;
1472
c27a02cd
YP		 1473 mutex_lock(&mdev->state_lock);
1474 if (mdev->device_up) {
6123db2e
JM		 1475 if (priv->port_up) {
1476 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1477 if (err)
1478 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1479
c27a02cd 1480 mlx4_en_auto_moderation(priv);
6123db2e 1481 }
c27a02cd
YP		 1482
1483 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1484 }
d7e1a487 1485 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
bfa8ab47 1486 mlx4_en_do_set_mac(priv);
d7e1a487
YP		 1487 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1488 }
c27a02cd
YP		 1489 mutex_unlock(&mdev->state_lock);
1490}
1491
b6c39bfc
AV		 1492/* mlx4_en_service_task - Run service task for tasks that needed to be done
1493 * periodically
1494 */
1495static void mlx4_en_service_task(struct work_struct *work)
1496{
1497 struct delayed_work *delay = to_delayed_work(work);
1498 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1499 service_task);
1500 struct mlx4_en_dev *mdev = priv->mdev;
1501
1502 mutex_lock(&mdev->state_lock);
1503 if (mdev->device_up) {
dc8142ea
AV		 1504 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1505 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc
AV		 1506
1507 queue_delayed_work(mdev->workqueue, &priv->service_task,
1508 SERVICE_TASK_DELAY);
1509 }
1510 mutex_unlock(&mdev->state_lock);
1511}
1512
c27a02cd
YP		 1513static void mlx4_en_linkstate(struct work_struct *work)
1514{
1515 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1516 linkstate_task);
1517 struct mlx4_en_dev *mdev = priv->mdev;
1518 int linkstate = priv->link_state;
1519
1520 mutex_lock(&mdev->state_lock);
1521 /* If observable port state changed set carrier state and
1522 * report to system log */
1523 if (priv->last_link_state != linkstate) {
1524 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1525 en_info(priv, "Link Down\n");
c27a02cd
YP		 1526 netif_carrier_off(priv->dev);
1527 } else {
e5cc44b2 1528 en_info(priv, "Link Up\n");
c27a02cd
YP		 1529 netif_carrier_on(priv->dev);
1530 }
1531 }
1532 priv->last_link_state = linkstate;
1533 mutex_unlock(&mdev->state_lock);
1534}
1535
1536
18cc42a3 1537int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1538{
1539 struct mlx4_en_priv *priv = netdev_priv(dev);
1540 struct mlx4_en_dev *mdev = priv->mdev;
1541 struct mlx4_en_cq *cq;
1542 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1543 int rx_index = 0;
1544 int tx_index = 0;
c27a02cd
YP		 1545 int err = 0;
1546 int i;
1547 int j;
1679200f 1548 u8 mc_list[16] = {0};
c27a02cd
YP		 1549
1550 if (priv->port_up) {
453a6082 1551 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1552 return 0;
1553 }
1554
6d199937
YP		 1555 INIT_LIST_HEAD(&priv->mc_list);
1556 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1557 INIT_LIST_HEAD(&priv->ethtool_list);
1558 memset(&priv->ethtool_rules[0], 0,
1559 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1560
c27a02cd
YP		 1561 /* Calculate Rx buf size */
1562 dev->mtu = min(dev->mtu, priv->max_mtu);
1563 mlx4_en_calc_rx_buf(dev);
453a6082 1564 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1565
c27a02cd 1566 /* Configure rx cq's and rings */
38aab07c
YP		 1567 err = mlx4_en_activate_rx_rings(priv);
1568 if (err) {
453a6082 1569 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1570 return err;
1571 }
c27a02cd 1572 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1573 cq = priv->rx_cq[i];
c27a02cd 1574
9e77a2b8
AV		 1575 mlx4_en_cq_init_lock(cq);
1576
76532d0c 1577 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1578 if (err) {
453a6082 1579 en_err(priv, "Failed activating Rx CQ\n");
a4233304 1580 goto cq_err;
c27a02cd
YP		 1581 }
1582 for (j = 0; j < cq->size; j++)
1583 cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1584 err = mlx4_en_set_cq_moder(priv, cq);
1585 if (err) {
453a6082 1586 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1587 mlx4_en_deactivate_cq(priv, cq);
1588 goto cq_err;
1589 }
1590 mlx4_en_arm_cq(priv, cq);
41d942d5 1591 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1592 ++rx_index;
1593 }
1594
ffe455ad
EE		 1595 /* Set qp number */
1596 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1597 err = mlx4_en_get_qp(priv);
1679200f 1598 if (err) {
ffe455ad 1599 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1600 goto cq_err;
1601 }
1602 mdev->mac_removed[priv->port] = 0;
1603
c27a02cd
YP		 1604 err = mlx4_en_config_rss_steer(priv);
1605 if (err) {
453a6082 1606 en_err(priv, "Failed configuring rss steering\n");
1679200f 1607 goto mac_err;
c27a02cd
YP		 1608 }
1609
cabdc8ee
HHZ		 1610 err = mlx4_en_create_drop_qp(priv);
1611 if (err)
1612 goto rss_err;
1613
c27a02cd
YP		 1614 /* Configure tx cq's and rings */
1615 for (i = 0; i < priv->tx_ring_num; i++) {
1616 /* Configure cq */
41d942d5 1617 cq = priv->tx_cq[i];
76532d0c 1618 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1619 if (err) {
453a6082 1620 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1621 goto tx_err;
1622 }
1623 err = mlx4_en_set_cq_moder(priv, cq);
1624 if (err) {
453a6082 1625 en_err(priv, "Failed setting cq moderation parameters");
c27a02cd
YP		 1626 mlx4_en_deactivate_cq(priv, cq);
1627 goto tx_err;
1628 }
453a6082 1629 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1630 cq->buf->wqe_index = cpu_to_be16(0xffff);
1631
1632 /* Configure ring */
41d942d5 1633 tx_ring = priv->tx_ring[i];
0e98b523 1634 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1635 i / priv->num_tx_rings_p_up);
c27a02cd 1636 if (err) {
453a6082 1637 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1638 mlx4_en_deactivate_cq(priv, cq);
1639 goto tx_err;
1640 }
5b263f53 1641 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1642
1643 /* Arm CQ for TX completions */
1644 mlx4_en_arm_cq(priv, cq);
1645
c27a02cd
YP		 1646 /* Set initial ownership of all Tx TXBBs to SW (1) */
1647 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1648 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1649 ++tx_index;
1650 }
1651
1652 /* Configure port */
1653 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1654 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1655 priv->prof->tx_pause,
1656 priv->prof->tx_ppp,
1657 priv->prof->rx_pause,
1658 priv->prof->rx_ppp);
c27a02cd 1659 if (err) {
48e551ff
YB		 1660 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1661 priv->port, err);
c27a02cd
YP		 1662 goto tx_err;
1663 }
1664 /* Set default qp number */
1665 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1666 if (err) {
453a6082 1667 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1668 goto tx_err;
1669 }
c27a02cd 1670
837052d0
OG		 1671 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1672 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
1673 if (err) {
1674 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1675 err);
1676 goto tx_err;
1677 }
1678 }
1679
c27a02cd 1680 /* Init port */
453a6082 1681 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1682 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1683 if (err) {
453a6082 1684 en_err(priv, "Failed Initializing port\n");
1679200f 1685 goto tx_err;
c27a02cd
YP		 1686 }
1687
1679200f
YP		 1688 /* Attach rx QP to bradcast address */
1689 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1690 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1691 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1692 priv->port, 0, MLX4_PROT_ETH,
1693 &priv->broadcast_id))
1679200f
YP		 1694 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1695
b5845f98
HX		 1696 /* Must redo promiscuous mode setup. */
1697 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1698
c27a02cd 1699 /* Schedule multicast task to populate multicast list */
0eb74fdd 1700 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1701
93ece0c1
EE		 1702 mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap);
1703
c27a02cd 1704 priv->port_up = true;
a11faac7 1705 netif_tx_start_all_queues(dev);
3484aac1
AV		 1706 netif_device_attach(dev);
1707
c27a02cd
YP		 1708 return 0;
1709
c27a02cd
YP		 1710tx_err:
1711 while (tx_index--) {
41d942d5
EE		 1712 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1713 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1714 }
cabdc8ee
HHZ		 1715 mlx4_en_destroy_drop_qp(priv);
1716rss_err:
c27a02cd 1717 mlx4_en_release_rss_steer(priv);
1679200f 1718mac_err:
16a10ffd 1719 mlx4_en_put_qp(priv);
c27a02cd
YP		 1720cq_err:
1721 while (rx_index--)
41d942d5 1722 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
38aab07c 1723 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1724 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1725
1726 return err; /* need to close devices */
1727}
1728
1729
3484aac1 1730void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1731{
1732 struct mlx4_en_priv *priv = netdev_priv(dev);
1733 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1734 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1735 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1736 int i;
1679200f 1737 u8 mc_list[16] = {0};
c27a02cd
YP		 1738
1739 if (!priv->port_up) {
453a6082 1740 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1741 return;
1742 }
c27a02cd 1743
0cc5c8bf
EE		 1744 /* close port*/
1745 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1746
c27a02cd
YP		 1747 /* Synchronize with tx routine */
1748 netif_tx_lock_bh(dev);
3484aac1
AV		 1749 if (detach)
1750 netif_device_detach(dev);
3c05f5ef 1751 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1752 netif_tx_unlock_bh(dev);
1753
3484aac1
AV		 1754 netif_tx_disable(dev);
1755
7c287380 1756 /* Set port as not active */
3c05f5ef 1757 priv->port_up = false;
c27a02cd 1758
db0e7cba
AY		 1759 /* Promsicuous mode */
1760 if (mdev->dev->caps.steering_mode ==
1761 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1762 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1763 MLX4_EN_FLAG_MC_PROMISC);
1764 mlx4_flow_steer_promisc_remove(mdev->dev,
1765 priv->port,
f9162539 1766 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1767 mlx4_flow_steer_promisc_remove(mdev->dev,
1768 priv->port,
f9162539 1769 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1770 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1771 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1772
1773 /* Disable promiscouos mode */
1774 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1775 priv->port);
1776
1777 /* Disable Multicast promisc */
1778 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1779 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1780 priv->port);
1781 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1782 }
1783 }
1784
1679200f
YP		 1785 /* Detach All multicasts */
1786 memset(&mc_list[10], 0xff, ETH_ALEN);
0ff1fb65 1787 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1788 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1789 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1790 list_for_each_entry(mclist, &priv->curr_list, list) {
1791 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1792 mc_list[5] = priv->port;
1793 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1794 mc_list, MLX4_PROT_ETH, mclist->reg_id);
1679200f
YP		 1795 }
1796 mlx4_en_clear_list(dev);
6d199937
YP		 1797 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1798 list_del(&mclist->list);
1799 kfree(mclist);
1800 }
1801
1679200f
YP		 1802 /* Flush multicast filter */
1803 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1804
6efb5fac
HHZ		 1805 /* Remove flow steering rules for the port*/
1806 if (mdev->dev->caps.steering_mode ==
1807 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1808 ASSERT_RTNL();
1809 list_for_each_entry_safe(flow, tmp_flow,
1810 &priv->ethtool_list, list) {
1811 mlx4_flow_detach(mdev->dev, flow->id);
1812 list_del(&flow->list);
1813 }
1814 }
1815
cabdc8ee
HHZ		 1816 mlx4_en_destroy_drop_qp(priv);
1817
c27a02cd
YP		 1818 /* Free TX Rings */
1819 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1820 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1821 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1822 }
1823 msleep(10);
1824
1825 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1826 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd
YP		 1827
1828 /* Free RSS qps */
1829 mlx4_en_release_rss_steer(priv);
1830
ffe455ad 1831 /* Unregister Mac address for the port */
16a10ffd 1832 mlx4_en_put_qp(priv);
5930e8d0 1833 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1834 mdev->mac_removed[priv->port] = 1;
ffe455ad 1835
c27a02cd
YP		 1836 /* Free RX Rings */
1837 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1838 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8
AV		 1839
1840 local_bh_disable();
1841 while (!mlx4_en_cq_lock_napi(cq)) {
1842 pr_info("CQ %d locked\n", i);
1843 mdelay(1);
1844 }
1845 local_bh_enable();
1846
9e77a2b8 1847 while (test_bit(NAPI_STATE_SCHED, &cq->napi.state))
c27a02cd 1848 msleep(1);
41d942d5 1849 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1850 mlx4_en_deactivate_cq(priv, cq);
c27a02cd
YP		 1851 }
1852}
1853
1854static void mlx4_en_restart(struct work_struct *work)
1855{
1856 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1857 watchdog_task);
1858 struct mlx4_en_dev *mdev = priv->mdev;
1859 struct net_device *dev = priv->dev;
1860
453a6082 1861 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1862
1863 mutex_lock(&mdev->state_lock);
1864 if (priv->port_up) {
3484aac1 1865 mlx4_en_stop_port(dev, 1);
1e338db5 1866 if (mlx4_en_start_port(dev))
453a6082 1867 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1868 }
1869 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1870}
1871
b477ba62 1872static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1873{
1874 struct mlx4_en_priv *priv = netdev_priv(dev);
1875 struct mlx4_en_dev *mdev = priv->mdev;
1876 int i;
c27a02cd 1877
c27a02cd 1878 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1879 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1880
1881 memset(&priv->stats, 0, sizeof(priv->stats));
1882 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1883 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1884 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
c27a02cd
YP		 1885
1886 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1887 priv->tx_ring[i]->bytes = 0;
1888 priv->tx_ring[i]->packets = 0;
1889 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1890 }
1891 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1892 priv->rx_ring[i]->bytes = 0;
1893 priv->rx_ring[i]->packets = 0;
1894 priv->rx_ring[i]->csum_ok = 0;
1895 priv->rx_ring[i]->csum_none = 0;
c27a02cd 1896 }
b477ba62
EE		 1897}
1898
1899static int mlx4_en_open(struct net_device *dev)
1900{
1901 struct mlx4_en_priv *priv = netdev_priv(dev);
1902 struct mlx4_en_dev *mdev = priv->mdev;
1903 int err = 0;
1904
1905 mutex_lock(&mdev->state_lock);
1906
1907 if (!mdev->device_up) {
1908 en_err(priv, "Cannot open - device down/disabled\n");
1909 err = -EBUSY;
1910 goto out;
1911 }
1912
1913 /* Reset HW statistics and SW counters */
1914 mlx4_en_clear_stats(dev);
c27a02cd 1915
c27a02cd
YP		 1916 err = mlx4_en_start_port(dev);
1917 if (err)
453a6082 1918 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1919
1920out:
1921 mutex_unlock(&mdev->state_lock);
1922 return err;
1923}
1924
1925
1926static int mlx4_en_close(struct net_device *dev)
1927{
1928 struct mlx4_en_priv *priv = netdev_priv(dev);
1929 struct mlx4_en_dev *mdev = priv->mdev;
1930
453a6082 1931 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1932
1933 mutex_lock(&mdev->state_lock);
1934
3484aac1 1935 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1936 netif_carrier_off(dev);
1937
1938 mutex_unlock(&mdev->state_lock);
1939 return 0;
1940}
1941
fe0af03c 1942void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1943{
1944 int i;
1945
1eb8c695
AV		 1946#ifdef CONFIG_RFS_ACCEL
1947 free_irq_cpu_rmap(priv->dev->rx_cpu_rmap);
1948 priv->dev->rx_cpu_rmap = NULL;
1949#endif
1950
c27a02cd 1951 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1952 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1953 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1954 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1955 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1956 }
1957
1958 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1959 if (priv->rx_ring[i])
68355f71
TLSC		 1960 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1961 priv->prof->rx_ring_size, priv->stride);
41d942d5 1962 if (priv->rx_cq[i])
fe0af03c 1963 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1964 }
044ca2a5
YP		 1965
1966 if (priv->base_tx_qpn) {
1967 mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num);
1968 priv->base_tx_qpn = 0;
1969 }
c27a02cd
YP		 1970}
1971
18cc42a3 1972int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1973{
c27a02cd
YP		 1974 struct mlx4_en_port_profile *prof = priv->prof;
1975 int i;
044ca2a5 1976 int err;
163561a4 1977 int node;
87a5c389 1978
044ca2a5 1979 err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn);
87a5c389
YP		 1980 if (err) {
1981 en_err(priv, "failed reserving range for TX rings\n");
1982 return err;
1983 }
c27a02cd
YP		 1984
1985 /* Create tx Rings */
1986 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1987 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1988 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1989 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1990 goto err;
1991
d03a68f8
IS		 1992 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
1993 priv->base_tx_qpn + i,
1994 prof->tx_ring_size, TXBB_SIZE,
1995 node, i))
c27a02cd
YP		 1996 goto err;
1997 }
1998
1999 /* Create rx Rings */
2000 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 2001 node = cpu_to_node(i % num_online_cpus());
c27a02cd 2002 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 2003 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 2004 goto err;
2005
2006 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 2007 prof->rx_ring_size, priv->stride,
2008 node))
c27a02cd
YP		 2009 goto err;
2010 }
2011
1eb8c695 2012#ifdef CONFIG_RFS_ACCEL
a229e488
AV		 2013 if (priv->mdev->dev->caps.comp_pool) {
2014 priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool);
2015 if (!priv->dev->rx_cpu_rmap)
2016 goto err;
2017 }
1eb8c695
AV		 2018#endif
2019
c27a02cd
YP		 2020 return 0;
2021
2022err:
453a6082 2023 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2024 for (i = 0; i < priv->rx_ring_num; i++) {
2025 if (priv->rx_ring[i])
2026 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2027 prof->rx_ring_size,
2028 priv->stride);
2029 if (priv->rx_cq[i])
2030 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2031 }
2032 for (i = 0; i < priv->tx_ring_num; i++) {
2033 if (priv->tx_ring[i])
2034 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2035 if (priv->tx_cq[i])
2036 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2037 }
c27a02cd
YP		 2038 return -ENOMEM;
2039}
2040
2041
2042void mlx4_en_destroy_netdev(struct net_device *dev)
2043{
2044 struct mlx4_en_priv *priv = netdev_priv(dev);
2045 struct mlx4_en_dev *mdev = priv->mdev;
2046
453a6082 2047 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2048
2049 /* Unregister device - this will close the port if it was up */
2050 if (priv->registered)
2051 unregister_netdev(dev);
2052
2053 if (priv->allocated)
2054 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2055
2056 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2057 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2058 /* flush any pending task for this netdev */
2059 flush_workqueue(mdev->workqueue);
2060
2061 /* Detach the netdev so tasks would not attempt to access it */
2062 mutex_lock(&mdev->state_lock);
2063 mdev->pndev[priv->port] = NULL;
2064 mutex_unlock(&mdev->state_lock);
2065
fe0af03c 2066 mlx4_en_free_resources(priv);
564c274c 2067
bc6a4744
AV		 2068 kfree(priv->tx_ring);
2069 kfree(priv->tx_cq);
2070
c27a02cd
YP		 2071 free_netdev(dev);
2072}
2073
2074static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2075{
2076 struct mlx4_en_priv *priv = netdev_priv(dev);
2077 struct mlx4_en_dev *mdev = priv->mdev;
2078 int err = 0;
2079
453a6082 2080 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2081 dev->mtu, new_mtu);
2082
2083 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2084 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2085 return -EPERM;
2086 }
2087 dev->mtu = new_mtu;
2088
2089 if (netif_running(dev)) {
2090 mutex_lock(&mdev->state_lock);
2091 if (!mdev->device_up) {
2092 /* NIC is probably restarting - let watchdog task reset
2093 * the port */
453a6082 2094 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2095 } else {
3484aac1 2096 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2097 err = mlx4_en_start_port(dev);
2098 if (err) {
453a6082 2099 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2100 priv->port);
2101 queue_work(mdev->workqueue, &priv->watchdog_task);
2102 }
2103 }
2104 mutex_unlock(&mdev->state_lock);
2105 }
2106 return 0;
2107}
2108
100dbda8 2109static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2110{
2111 struct mlx4_en_priv *priv = netdev_priv(dev);
2112 struct mlx4_en_dev *mdev = priv->mdev;
2113 struct hwtstamp_config config;
2114
2115 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2116 return -EFAULT;
2117
2118 /* reserved for future extensions */
2119 if (config.flags)
2120 return -EINVAL;
2121
2122 /* device doesn't support time stamping */
2123 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2124 return -EINVAL;
2125
2126 /* TX HW timestamp */
2127 switch (config.tx_type) {
2128 case HWTSTAMP_TX_OFF:
2129 case HWTSTAMP_TX_ON:
2130 break;
2131 default:
2132 return -ERANGE;
2133 }
2134
2135 /* RX HW timestamp */
2136 switch (config.rx_filter) {
2137 case HWTSTAMP_FILTER_NONE:
2138 break;
2139 case HWTSTAMP_FILTER_ALL:
2140 case HWTSTAMP_FILTER_SOME:
2141 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2142 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2143 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2144 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2145 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2146 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2147 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2148 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2149 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2150 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2151 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2152 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2153 config.rx_filter = HWTSTAMP_FILTER_ALL;
2154 break;
2155 default:
2156 return -ERANGE;
2157 }
2158
2159 if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) {
2160 config.tx_type = HWTSTAMP_TX_OFF;
2161 config.rx_filter = HWTSTAMP_FILTER_NONE;
2162 }
2163
2164 return copy_to_user(ifr->ifr_data, &config,
2165 sizeof(config)) ? -EFAULT : 0;
2166}
2167
100dbda8
BH		 2168static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2169{
2170 struct mlx4_en_priv *priv = netdev_priv(dev);
2171
2172 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2173 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2174}
2175
ec693d47
AV		 2176static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2177{
2178 switch (cmd) {
2179 case SIOCSHWTSTAMP:
100dbda8
BH		 2180 return mlx4_en_hwtstamp_set(dev, ifr);
2181 case SIOCGHWTSTAMP:
2182 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2183 default:
2184 return -EOPNOTSUPP;
2185 }
2186}
2187
60d6fe99
AV		 2188static int mlx4_en_set_features(struct net_device *netdev,
2189 netdev_features_t features)
2190{
2191 struct mlx4_en_priv *priv = netdev_priv(netdev);
2192
2193 if (features & NETIF_F_LOOPBACK)
2194 priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
2195 else
2196 priv->ctrl_flags &=
2197 cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK);
2198
79aeaccd
YB		 2199 mlx4_en_update_loopback_state(netdev, features);
2200
60d6fe99
AV		 2201 return 0;
2202
2203}
2204
8f7ba3ca
RE		 2205static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2206{
2207 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2208 struct mlx4_en_dev *mdev = en_priv->mdev;
2209 u64 mac_u64 = mlx4_en_mac_to_u64(mac);
2210
2211 if (!is_valid_ether_addr(mac))
2212 return -EINVAL;
2213
2214 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2215}
2216
3f7fb021
RE		 2217static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2218{
2219 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2220 struct mlx4_en_dev *mdev = en_priv->mdev;
2221
2222 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2223}
2224
e6b6a231
RE		 2225static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2226{
2227 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2228 struct mlx4_en_dev *mdev = en_priv->mdev;
2229
2230 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2231}
2232
2cccb9e4
RE		 2233static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2234{
2235 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2236 struct mlx4_en_dev *mdev = en_priv->mdev;
2237
2238 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2239}
8f7ba3ca 2240
948e306d
RE		 2241static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2242{
2243 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2244 struct mlx4_en_dev *mdev = en_priv->mdev;
2245
2246 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2247}
84c86403
HHZ		 2248
2249#define PORT_ID_BYTE_LEN 8
2250static int mlx4_en_get_phys_port_id(struct net_device *dev,
2251 struct netdev_phys_port_id *ppid)
2252{
2253 struct mlx4_en_priv *priv = netdev_priv(dev);
2254 struct mlx4_dev *mdev = priv->mdev->dev;
2255 int i;
2256 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2257
2258 if (!phys_port_id)
2259 return -EOPNOTSUPP;
2260
2261 ppid->id_len = sizeof(phys_port_id);
2262 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2263 ppid->id[i] = phys_port_id & 0xff;
2264 phys_port_id >>= 8;
2265 }
2266 return 0;
2267}
2268
3addc568
SH		 2269static const struct net_device_ops mlx4_netdev_ops = {
2270 .ndo_open = mlx4_en_open,
2271 .ndo_stop = mlx4_en_close,
2272 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2273 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2274 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2275 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2276 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2277 .ndo_validate_addr = eth_validate_addr,
3addc568 2278 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2279 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2280 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2281 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2282 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2283#ifdef CONFIG_NET_POLL_CONTROLLER
2284 .ndo_poll_controller = mlx4_en_netpoll,
2285#endif
60d6fe99 2286 .ndo_set_features = mlx4_en_set_features,
897d7846 2287 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2288#ifdef CONFIG_RFS_ACCEL
2289 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2290#endif
e0d1095a 2291#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 2292 .ndo_busy_poll = mlx4_en_low_latency_recv,
9e77a2b8 2293#endif
84c86403 2294 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
3addc568
SH		 2295};
2296
8f7ba3ca
RE		 2297static const struct net_device_ops mlx4_netdev_ops_master = {
2298 .ndo_open = mlx4_en_open,
2299 .ndo_stop = mlx4_en_close,
2300 .ndo_start_xmit = mlx4_en_xmit,
2301 .ndo_select_queue = mlx4_en_select_queue,
2302 .ndo_get_stats = mlx4_en_get_stats,
2303 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2304 .ndo_set_mac_address = mlx4_en_set_mac,
2305 .ndo_validate_addr = eth_validate_addr,
2306 .ndo_change_mtu = mlx4_en_change_mtu,
2307 .ndo_tx_timeout = mlx4_en_tx_timeout,
2308 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2309 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2310 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2311 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
e6b6a231 2312 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2313 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
2cccb9e4 2314 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2315#ifdef CONFIG_NET_POLL_CONTROLLER
2316 .ndo_poll_controller = mlx4_en_netpoll,
2317#endif
2318 .ndo_set_features = mlx4_en_set_features,
2319 .ndo_setup_tc = mlx4_en_setup_tc,
2320#ifdef CONFIG_RFS_ACCEL
2321 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2322#endif
84c86403 2323 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
8f7ba3ca
RE		 2324};
2325
c27a02cd
YP		 2326int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2327 struct mlx4_en_port_profile *prof)
2328{
2329 struct net_device *dev;
2330 struct mlx4_en_priv *priv;
c07cb4b0 2331 int i;
c27a02cd 2332 int err;
ef96f7d4 2333 u64 mac_u64;
c27a02cd 2334
f1593d22 2335 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2336 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2337 if (dev == NULL)
c27a02cd 2338 return -ENOMEM;
c27a02cd 2339
d317966b
AV		 2340 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2341 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2342
c27a02cd 2343 SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev);
741a00be 2344 dev->dev_id = port - 1;
c27a02cd
YP		 2345
2346 /*
2347 * Initialize driver private data
2348 */
2349
2350 priv = netdev_priv(dev);
2351 memset(priv, 0, sizeof(struct mlx4_en_priv));
2352 priv->dev = dev;
2353 priv->mdev = mdev;
ebf8c9aa 2354 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2355 priv->prof = prof;
2356 priv->port = port;
2357 priv->port_up = false;
c27a02cd 2358 priv->flags = prof->flags;
60d6fe99
AV		 2359 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2360 MLX4_WQE_CTRL_SOLICITED);
d317966b 2361 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2362 priv->tx_ring_num = prof->tx_ring_num;
d317966b 2363
41d942d5 2364 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2365 GFP_KERNEL);
bc6a4744
AV		 2366 if (!priv->tx_ring) {
2367 err = -ENOMEM;
2368 goto out;
2369 }
41d942d5 2370 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2371 GFP_KERNEL);
bc6a4744
AV		 2372 if (!priv->tx_cq) {
2373 err = -ENOMEM;
2374 goto out;
2375 }
c27a02cd 2376 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2377 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
c27a02cd
YP		 2378 priv->mac_index = -1;
2379 priv->msg_enable = MLX4_EN_MSG_LEVEL;
2380 spin_lock_init(&priv->stats_lock);
0eb74fdd 2381 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
c27a02cd
YP		 2382 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2383 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2384 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
b6c39bfc 2385 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
564c274c 2386#ifdef CONFIG_MLX4_EN_DCB
540b3a39
OG		 2387 if (!mlx4_is_slave(priv->mdev->dev)) {
2388 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
2389 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2390 } else {
2391 en_info(priv, "enabling only PFC DCB ops\n");
2392 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2393 }
2394 }
564c274c 2395#endif
c27a02cd 2396
c07cb4b0
YB		 2397 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2398 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2399
c27a02cd
YP		 2400 /* Query for default mac and max mtu */
2401 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99
YB		 2402
2403 /* Set default MAC */
2404 dev->addr_len = ETH_ALEN;
2405 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2406 if (!is_valid_ether_addr(dev->dev_addr)) {
ef96f7d4
OG		 2407 if (mlx4_is_slave(priv->mdev->dev)) {
2408 eth_hw_addr_random(dev);
2409 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
2410 mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
2411 mdev->dev->caps.def_mac[priv->port] = mac_u64;
2412 } else {
2413 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2414 priv->port, dev->dev_addr);
2415 err = -EINVAL;
2416 goto out;
2417 }
c27a02cd
YP		 2418 }
2419
6bbb6d99
YB		 2420 memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
2421
c27a02cd
YP		 2422 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2423 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2424 err = mlx4_en_alloc_resources(priv);
2425 if (err)
2426 goto out;
2427
78fb2de7
AV		 2428#ifdef CONFIG_RFS_ACCEL
2429 INIT_LIST_HEAD(&priv->filters);
2430 spin_lock_init(&priv->filters_lock);
2431#endif
2432
ec693d47
AV		 2433 /* Initialize time stamping config */
2434 priv->hwtstamp_config.flags = 0;
2435 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2436 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2437
c27a02cd
YP		 2438 /* Allocate page for receive rings */
2439 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2440 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2441 if (err) {
453a6082 2442 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2443 goto out;
2444 }
2445 priv->allocated = 1;
2446
c27a02cd
YP		 2447 /*
2448 * Initialize netdev entry points
2449 */
8f7ba3ca
RE		 2450 if (mlx4_is_master(priv->mdev->dev))
2451 dev->netdev_ops = &mlx4_netdev_ops_master;
2452 else
2453 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2454 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2455 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2456 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2457
c27a02cd
YP		 2458 SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops);
2459
c27a02cd
YP		 2460 /*
2461 * Set driver features
2462 */
c8c64cff
MM		 2463 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2464 if (mdev->LSO_support)
2465 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2466
2467 dev->vlan_features = dev->hw_features;
2468
ad86107f 2469 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2470 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2471 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2472 NETIF_F_HW_VLAN_CTAG_FILTER;
60d6fe99 2473 dev->hw_features |= NETIF_F_LOOPBACK;
c27a02cd 2474
1eb8c695
AV		 2475 if (mdev->dev->caps.steering_mode ==
2476 MLX4_STEERING_MODE_DEVICE_MANAGED)
2477 dev->hw_features |= NETIF_F_NTUPLE;
2478
cc5387f7
YB		 2479 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2480 dev->priv_flags |= IFF_UNICAST_FLT;
2481
837052d0
OG		 2482 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2483 dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2484 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2485 dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2486 dev->features |= NETIF_F_GSO_UDP_TUNNEL;
2487 }
2488
c27a02cd
YP		 2489 mdev->pndev[port] = dev;
2490
2491 netif_carrier_off(dev);
4801ae70
EE		 2492 mlx4_en_set_default_moderation(priv);
2493
c27a02cd
YP		 2494 err = register_netdev(dev);
2495 if (err) {
453a6082 2496 en_err(priv, "Netdev registration failed for port %d\n", port);
c27a02cd
YP		 2497 goto out;
2498 }
4234144f 2499 priv->registered = 1;
453a6082
YP		 2500
2501 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2502 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2503
79aeaccd
YB		 2504 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2505
90822265 2506 /* Configure port */
5c8e9046 2507 mlx4_en_calc_rx_buf(dev);
90822265 2508 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2509 priv->rx_skb_size + ETH_FCS_LEN,
2510 prof->tx_pause, prof->tx_ppp,
2511 prof->rx_pause, prof->rx_ppp);
90822265
YP		 2512 if (err) {
2513 en_err(priv, "Failed setting port general configurations "
2514 "for port %d, with error %d\n", priv->port, err);
2515 goto out;
2516 }
2517
837052d0
OG		 2518 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2519 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC);
2520 if (err) {
2521 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
2522 err);
2523 goto out;
2524 }
2525 }
2526
90822265
YP		 2527 /* Init port */
2528 en_warn(priv, "Initializing port\n");
2529 err = mlx4_INIT_PORT(mdev->dev, priv->port);
2530 if (err) {
2531 en_err(priv, "Failed Initializing port\n");
2532 goto out;
2533 }
c27a02cd 2534 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea
AV		 2535
2536 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2537 queue_delayed_work(mdev->workqueue, &priv->service_task,
2538 SERVICE_TASK_DELAY);
2539
c27a02cd
YP		 2540 return 0;
2541
2542out:
2543 mlx4_en_destroy_netdev(dev);
2544 return err;
2545}
2546
Linux 6.x block layer and io_uring tree(s)